diff --git a/main/acle.md b/main/acle.md
index 1823e1de..e5301faa 100644
--- a/main/acle.md
+++ b/main/acle.md
@@ -488,7 +488,7 @@ Armv8.4-A [[ARMARMv84]](#ARMARMv84). Support is added for the Dot Product intrin
 * Added [**Alpha**](#current-status-and-anticipated-changes) support
   for Brain 16-bit floating-point vector multiplication intrinsics.
 * Redesigned atomic store with hints intrinsics.
-
+* Added support for producer-consumer data placement hints. [**Alpha** state]
 ### References
 
 This document refers to the following documents.
@@ -1849,6 +1849,11 @@ execution state. Intrinsics for the use of these instructions are specified in
 data placement hints (FEAT_PCDPHINT) instructions and their associated
 intrinsics are available on the target.
 
+### Contention Management hints [**Alpha** state]
+
+`__ARM_FEATURE_CMH` is defined to `1` if the Contention Management hints
+(FEAT_CMH) instructions and their associated intrinsics are available on the target.
+
 ## Floating-point and vector hardware
 
 ### Hardware floating point
@@ -2655,6 +2660,7 @@ be found in [[BA]](#BA).
 | [`__ARM_FEATURE_CDE`](#custom-datapath-extension)                                                                                                       | Custom Datapath Extension                                                                          | 0x01        |
 | [`__ARM_FEATURE_CDE_COPROC`](#custom-datapath-extension)                                                                                                | Custom Datapath Extension                                                                          | 0xf         |
 | [`__ARM_FEATURE_CLZ`](#clz)                                                                                                                             | CLZ instruction                                                                                    | 1           |
+| [`__ARM_FEATURE_CMH`](#contention-management-hints)                                                                                                     | Contention management hints                                                                        | 1           |
 | [`__ARM_FEATURE_COMPLEX`](#complex-number-intrinsics)                                                                                                   | Armv8.3-A extension                                                                                | 1           |
 | [`__ARM_FEATURE_COPROC`](#coprocessor-intrinsics)                                                                                                       | Coprocessor Intrinsics                                                                             | 1           |
 | [`__ARM_FEATURE_CRC32`](#crc32-extension)                                                                                                               | CRC32 extension                                                                                    | 1           |
@@ -4985,6 +4991,40 @@ target. The following hint values are defined:
 | ---------------- | --------- | -------------------------- | --------------------------------------------------------------------------------- |
 | HINT_STSHH_KEEP  | 0         | `__ARM_FEATURE_PCDPHINT`   | Requests retention of the updated location in the local cache of the updating PE. |
 | HINT_STSHH_STRM  | 1         | `__ARM_FEATURE_PCDPHINT`   | Requests that the updated location not be retained in the local cache of the updating PE. |
+| HINT_STCPH       | 2         | `__ARM_FEATURE_CMH`        | Ensures that the memory write effect of the next instruction occurs before any other effects from other threads.|
+| HINT_SHUH        | 3         | `__ARM_FEATURE_CMH`        | Informs that the next instruction generates an effect in a location that one or more other threads of execution are likely to subsequently update. |
+| HINT_SHUH_PH     | 4         | `__ARM_FEATURE_CMH`        | PH adds the effects of STCPH to SHUH. |
+
+## Atomic fetch with hints intrinsics [**Alpha** state]
+
+These intrinsics provide some atomic fetch operations, which will
+make use of hint instructions immediately followed by the
+associated fetch instructions. These intrinsics are type generic and 
+supports scalar integral and floating-point types of 8, 16, 32, and 64 bits.
+
+To access these intrinsics, `<arm_acle.h>` should be included.
+
+``` c
+  type __arm_atomic_fetch_add_with_hint(type *ptr, type data, int memory_order, int hint);
+  type __arm_atomic_fetch_sub_with_hint(type *ptr, type data, int memory_order, int hint);
+  type __arm_atomic_fetch_and_with_hint(type *ptr, type data, int memory_order, int hint);
+  type __arm_atomic_fetch_xor_with_hint(type *ptr, type data, int memory_order, int hint);
+  type __arm_atomic_fetch_or_with_hint(type *ptr, type data, int memory_order, int hint);
+```
+
+The first argument in these intrinsic is a pointer `ptr` which is the location to store to.
+The second argument `data` is the data which is to be stored.
+The third argument `mem` can be one of 6 memory ordering variables supported by atomic_fetch:
+__ATOMIC_RELAXED, __ATOMIC_SEQ_CST, __ATOMIC_ACQUIRE, __ATOMIC_CONSUME, __ATOMIC_ACQ_REL and __ATOMIC_RELEASE.
+
+The fourth argument `hint` selects the requested hint. The set of valid
+hint values depends on the architectural features supported by the
+target. The following hint values are defined:
+
+| **Hint**         | **Value** | **Feature**                | **Summary**                                                                       |
+| ---------------- | --------- | -------------------------- | --------------------------------------------------------------------------------- |
+| HINT_SHUH        | 0         | `__ARM_FEATURE_CMH`        | Informs that the next instruction generates an effect in a location that one or more other threads of execution are likely to subsequently update. |
+| HINT_SHUH_PH     | 1         | `__ARM_FEATURE_CMH`        | PH adds the effects of STCPH to SHUH. |
 
 # Custom Datapath Extension