RISC-Processor/decoder.sv at master · Arnab035/RISC-Processor · GitHub

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
`include "Sysbus.defs"

module decoder
#(
  BUS_DATA_WIDTH = 64
)
(
  input  clk,
  input  decode_en,
  input  [BUS_DATA_WIDTH-1:0] data
);

`include "decode.sv"

  logic signed [63:0] pc = 0;

  always @ (posedge clk) begin
    if (decode_en) begin
	  pc <= pc + 8;
      decode(pc, data);
    end
  end
endmodule