diff --git a/Task7_PCB_Design_Proposal.pdf b/Task7_PCB_Design_Proposal.pdf
new file mode 100644
index 0000000..ed2e75f
Binary files /dev/null and b/Task7_PCB_Design_Proposal.pdf differ
diff --git a/Task7_PowerSupply-cache.lib b/Task7_PowerSupply-cache.lib
new file mode 100644
index 0000000..a205125
--- /dev/null
+++ b/Task7_PowerSupply-cache.lib
@@ -0,0 +1,129 @@
+EESchema-LIBRARY Version 2.3
+#encoding utf-8
+#
+# Conn_01x02
+#
+DEF Conn_01x02 J 0 40 Y N 1 F N
+F0 "J" 0 100 50 H V C CNN
+F1 "Conn_01x02" 0 -200 50 H V C CNN
+F2 "" 0 0 50 H I C CNN
+F3 "" 0 0 50 H I C CNN
+$FPLIST
+ Connector*:*_??x*mm*
+ Connector*:*1x??x*mm*
+ Pin?Header?Straight?1X*
+ Pin?Header?Angled?1X*
+ Socket?Strip?Straight?1X*
+ Socket?Strip?Angled?1X*
+$ENDFPLIST
+DRAW
+S -50 -95 0 -105 1 1 6 N
+S -50 5 0 -5 1 1 6 N
+S -50 50 50 -150 1 1 10 f
+X Pin_1 1 -200 0 150 R 50 50 1 1 P
+X Pin_2 2 -200 -100 150 R 50 50 1 1 P
+ENDDRAW
+ENDDEF
+#
+# L7805
+#
+DEF L7805 U 0 10 Y Y 1 F N
+F0 "U" -150 125 50 H V C CNN
+F1 "L7805" 0 125 50 H V L CNN
+F2 "" 25 -150 50 H I L CIN
+F3 "" 0 -50 50 H I C CNN
+ALIAS L7806 L7808 L7885 L7809 L7812 L7815 L7818 L7824
+$FPLIST
+ TO?252*
+ TO?263*
+ TO?220*
+$ENDFPLIST
+DRAW
+S -200 75 200 -200 0 1 10 f
+X IN 1 -300 0 100 R 50 50 1 1 W
+X GND 2 0 -300 100 U 50 50 1 1 W
+X OUT 3 300 0 100 L 50 50 1 1 w
+ENDDRAW
+ENDDEF
+#
+# eSim_C
+#
+DEF eSim_C C 0 10 N Y 1 F N
+F0 "C" 25 100 50 H V L CNN
+F1 "eSim_C" 25 -100 50 H V L CNN
+F2 "" 38 -150 30 H V C CNN
+F3 "" 0 0 60 H V C CNN
+ALIAS capacitor
+$FPLIST
+ C_*
+$ENDFPLIST
+DRAW
+P 2 0 1 20 -80 -30 80 -30 N
+P 2 0 1 20 -80 30 80 30 N
+X ~ 1 0 150 110 D 40 40 1 1 P
+X ~ 2 0 -150 110 U 40 40 1 1 P
+ENDDRAW
+ENDDEF
+#
+# eSim_CP1
+#
+DEF eSim_CP1 C 0 10 N N 1 F N
+F0 "C" 25 100 50 H V L CNN
+F1 "eSim_CP1" 25 -100 50 H V L CNN
+F2 "" 0 0 50 H I C CNN
+F3 "" 0 0 50 H I C CNN
+ALIAS capacitor_polarised
+$FPLIST
+ CP_*
+$ENDFPLIST
+DRAW
+A 0 -150 128 1287 513 0 1 20 N -80 -50 80 -50
+P 2 0 1 20 -80 30 80 30 N
+P 2 0 1 0 -70 90 -30 90 N
+P 2 0 1 0 -50 70 -50 110 N
+X ~ 1 0 150 110 D 50 50 1 1 P
+X ~ 2 0 -150 130 U 50 50 1 1 P
+ENDDRAW
+ENDDEF
+#
+# eSim_LED
+#
+DEF eSim_LED D 0 40 Y N 1 F N
+F0 "D" 0 100 50 H V C CNN
+F1 "eSim_LED" 50 -100 31 H V C CNN
+F2 "" 0 0 50 H I C CNN
+F3 "" 0 0 50 H I C CNN
+$FPLIST
+ LED*
+$ENDFPLIST
+DRAW
+P 2 0 1 8 -50 -50 -50 50 N
+P 2 0 1 0 -50 0 50 0 N
+P 4 0 1 8 50 -50 50 50 -50 0 50 -50 N
+P 5 0 1 0 -120 -30 -180 -90 -150 -90 -180 -90 -180 -60 N
+P 5 0 1 0 -70 -30 -130 -90 -100 -90 -130 -90 -130 -60 N
+X A 1 150 0 100 L 50 50 1 1 P
+X K 2 -150 0 100 R 50 50 1 1 P
+ENDDRAW
+ENDDEF
+#
+# eSim_R
+#
+DEF eSim_R R 0 0 N Y 1 F N
+F0 "R" 50 130 50 H V C CNN
+F1 "eSim_R" 50 -50 50 H V C CNN
+F2 "" 50 -20 30 H V C CNN
+F3 "" 50 50 30 V V C CNN
+ALIAS resistor
+$FPLIST
+ R_*
+ Resistor_*
+$ENDFPLIST
+DRAW
+S 150 10 -50 90 0 1 10 N
+X ~ 1 -100 50 50 R 60 60 1 1 P
+X ~ 2 200 50 50 L 60 60 1 1 P
+ENDDRAW
+ENDDEF
+#
+#End Library
diff --git a/Task7_PowerSupply.bak b/Task7_PowerSupply.bak
new file mode 100644
index 0000000..233d592
--- /dev/null
+++ b/Task7_PowerSupply.bak
@@ -0,0 +1,201 @@
+EESchema Schematic File Version 2
+LIBS:adc-dac
+LIBS:memory
+LIBS:xilinx
+LIBS:microcontrollers
+LIBS:dsp
+LIBS:microchip
+LIBS:analog_switches
+LIBS:motorola
+LIBS:texas
+LIBS:intel
+LIBS:audio
+LIBS:interface
+LIBS:digital-audio
+LIBS:philips
+LIBS:display
+LIBS:cypress
+LIBS:siliconi
+LIBS:opto
+LIBS:atmel
+LIBS:contrib
+LIBS:power
+LIBS:eSim_Plot
+LIBS:transistors
+LIBS:conn
+LIBS:eSim_User
+LIBS:regul
+LIBS:74xx
+LIBS:cmos4000
+LIBS:eSim_Analog
+LIBS:eSim_Devices
+LIBS:eSim_Digital
+LIBS:eSim_Hybrid
+LIBS:eSim_Miscellaneous
+LIBS:eSim_Power
+LIBS:eSim_Sources
+LIBS:eSim_Subckt
+LIBS:eSim_Nghdl
+LIBS:eSim_Ngveri
+LIBS:eSim_SKY130
+LIBS:eSim_SKY130_Subckts
+EELAYER 25 0
+EELAYER END
+$Descr A4 11693 8268
+encoding utf-8
+Sheet 1 1
+Title ""
+Date ""
+Rev ""
+Comp ""
+Comment1 ""
+Comment2 ""
+Comment3 ""
+Comment4 ""
+$EndDescr
+$Comp
+L Conn_01x02 J1
+U 1 1 6A893EDE
+P 4950 3600
+F 0 "J1" H 4950 3700 50  0000 C CNN
+F 1 "Conn_01x02" H 4950 3400 50  0000 C CNN
+F 2 "" H 4950 3600 50  0001 C CNN
+F 3 "" H 4950 3600 50  0001 C CNN
+	1    4950 3600
+	1    0    0    -1  
+$EndComp
+$Comp
+L eSim_CP1 C2
+U 1 1 6A893F37
+P 5250 3650
+F 0 "C2" H 5275 3750 50  0000 L CNN
+F 1 "eSim_CP1" H 5275 3550 50  0000 L CNN
+F 2 "" H 5250 3650 50  0001 C CNN
+F 3 "" H 5250 3650 50  0001 C CNN
+	1    5250 3650
+	1    0    0    -1  
+$EndComp
+$Comp
+L eSim_C C1
+U 1 1 6A89400C
+P 5650 3650
+F 0 "C1" H 5675 3750 50  0000 L CNN
+F 1 "eSim_C" H 5675 3550 50  0000 L CNN
+F 2 "" H 5688 3500 30  0000 C CNN
+F 3 "" H 5650 3650 60  0000 C CNN
+	1    5650 3650
+	1    0    0    -1  
+$EndComp
+$Comp
+L L7805 U1
+U 1 1 6A894156
+P 6200 3600
+F 0 "U1" H 6050 3725 50  0000 C CNN
+F 1 "L7805" H 6200 3725 50  0000 L CNN
+F 2 "" H 6225 3450 50  0001 L CIN
+F 3 "" H 6200 3550 50  0001 C CNN
+	1    6200 3600
+	1    0    0    -1  
+$EndComp
+$Comp
+L eSim_C C3
+U 1 1 6A8941CB
+P 6600 3650
+F 0 "C3" H 6625 3750 50  0000 L CNN
+F 1 "eSim_C" H 6625 3550 50  0000 L CNN
+F 2 "" H 6638 3500 30  0000 C CNN
+F 3 "" H 6600 3650 60  0000 C CNN
+	1    6600 3650
+	1    0    0    -1  
+$EndComp
+$Comp
+L eSim_R R1
+U 1 1 6A89426C
+P 7050 3700
+F 0 "R1" H 7100 3830 50  0000 C CNN
+F 1 "eSim_R" H 7100 3650 50  0000 C CNN
+F 2 "" H 7100 3680 30  0000 C CNN
+F 3 "" V 7100 3750 30  0000 C CNN
+	1    7050 3700
+	1    0    0    -1  
+$EndComp
+$Comp
+L eSim_LED D1
+U 1 1 6A8942FF
+P 7600 3650
+F 0 "D1" H 7600 3750 50  0000 C CNN
+F 1 "eSim_LED" H 7650 3550 31  0000 C CNN
+F 2 "" H 7600 3650 50  0001 C CNN
+F 3 "" H 7600 3650 50  0001 C CNN
+	1    7600 3650
+	1    0    0    -1  
+$EndComp
+$Comp
+L Conn_01x02 J2
+U 1 1 6A89452E
+P 8100 3600
+F 0 "J2" H 8100 3700 50  0000 C CNN
+F 1 "Conn_01x02" H 8100 3400 50  0000 C CNN
+F 2 "" H 8100 3600 50  0001 C CNN
+F 3 "" H 8100 3600 50  0001 C CNN
+	1    8100 3600
+	1    0    0    -1  
+$EndComp
+Wire Wire Line
+	4750 3500 5900 3500
+Wire Wire Line
+	6500 3600 6500 3500
+Wire Wire Line
+	6500 3500 6950 3500
+Wire Wire Line
+	6950 3500 7550 3500
+Wire Wire Line
+	7550 3500 7900 3500
+Connection ~ 6950 3500
+Connection ~ 7550 3500
+Wire Wire Line
+	4750 3850 5250 3850
+Wire Wire Line
+	5250 3850 5650 3850
+Wire Wire Line
+	5650 3850 5900 3850
+Wire Wire Line
+	5900 3500 5900 3600
+Wire Wire Line
+	5900 3850 5900 3900
+Wire Wire Line
+	5900 3900 6200 3900
+Wire Wire Line
+	6200 3900 6600 3900
+Wire Wire Line
+	6600 3900 7750 3900
+Wire Wire Line
+	7750 3900 7900 3900
+Connection ~ 6200 3900
+Wire Wire Line
+	5650 3800 5650 3850
+Connection ~ 5650 3850
+Wire Wire Line
+	5250 3800 5250 3850
+Connection ~ 5250 3850
+Wire Wire Line
+	4750 3600 4750 3500
+Wire Wire Line
+	4750 3700 4750 3850
+Wire Wire Line
+	6600 3800 6600 3900
+Connection ~ 6600 3900
+Wire Wire Line
+	6950 3500 6950 3650
+Wire Wire Line
+	7250 3650 7450 3650
+Wire Wire Line
+	7750 3650 7750 3900
+Connection ~ 7750 3900
+Wire Wire Line
+	7900 3500 7900 3600
+Connection ~ 7900 3500
+Wire Wire Line
+	7900 3700 7900 3900
+Connection ~ 7900 3900
+$EndSCHEMATC
diff --git a/Task7_PowerSupply.kicad_pcb b/Task7_PowerSupply.kicad_pcb
new file mode 100644
index 0000000..6ca98b0
--- /dev/null
+++ b/Task7_PowerSupply.kicad_pcb
@@ -0,0 +1,592 @@
+(kicad_pcb (version 4) (host pcbnew 4.0.7)
+
+  (general
+    (links 10)
+    (no_connects 0)
+    (area 0 0 0 0)
+    (thickness 1.6)
+    (drawings 0)
+    (tracks 45)
+    (zones 0)
+    (modules 8)
+    (nets 8)
+  )
+
+  (page A4)
+  (layers
+    (0 F.Cu signal)
+    (31 B.Cu signal)
+    (32 B.Adhes user)
+    (33 F.Adhes user)
+    (34 B.Paste user)
+    (35 F.Paste user)
+    (36 B.SilkS user)
+    (37 F.SilkS user)
+    (38 B.Mask user)
+    (39 F.Mask user)
+    (40 Dwgs.User user)
+    (41 Cmts.User user)
+    (42 Eco1.User user)
+    (43 Eco2.User user)
+    (44 Edge.Cuts user)
+    (45 Margin user)
+    (46 B.CrtYd user)
+    (47 F.CrtYd user)
+    (48 B.Fab user)
+    (49 F.Fab user)
+  )
+
+  (setup
+    (last_trace_width 0.25)
+    (trace_clearance 0.2)
+    (zone_clearance 0.508)
+    (zone_45_only no)
+    (trace_min 0.2)
+    (segment_width 0.2)
+    (edge_width 0.1)
+    (via_size 0.6)
+    (via_drill 0.4)
+    (via_min_size 0.4)
+    (via_min_drill 0.3)
+    (uvia_size 0.3)
+    (uvia_drill 0.1)
+    (uvias_allowed no)
+    (uvia_min_size 0.2)
+    (uvia_min_drill 0.1)
+    (pcb_text_width 0.3)
+    (pcb_text_size 1.5 1.5)
+    (mod_edge_width 0.15)
+    (mod_text_size 1 1)
+    (mod_text_width 0.15)
+    (pad_size 1.5 1.5)
+    (pad_drill 0.6)
+    (pad_to_mask_clearance 0)
+    (aux_axis_origin 0 0)
+    (visible_elements FFFFFF7F)
+    (pcbplotparams
+      (layerselection 0x00030_80000001)
+      (usegerberextensions false)
+      (excludeedgelayer true)
+      (linewidth 0.100000)
+      (plotframeref false)
+      (viasonmask false)
+      (mode 1)
+      (useauxorigin false)
+      (hpglpennumber 1)
+      (hpglpenspeed 20)
+      (hpglpendiameter 15)
+      (hpglpenoverlay 2)
+      (psnegative false)
+      (psa4output false)
+      (plotreference true)
+      (plotvalue true)
+      (plotinvisibletext false)
+      (padsonsilk false)
+      (subtractmaskfromsilk false)
+      (outputformat 1)
+      (mirror false)
+      (drillshape 1)
+      (scaleselection 1)
+      (outputdirectory ""))
+  )
+
+  (net 0 "")
+  (net 1 "Net-(C1-Pad1)")
+  (net 2 "Net-(C1-Pad2)")
+  (net 3 "Net-(C2-Pad1)")
+  (net 4 "Net-(C3-Pad1)")
+  (net 5 "Net-(D1-Pad2)")
+  (net 6 "Net-(J1-Pad1)")
+  (net 7 "Net-(J2-Pad1)")
+
+  (net_class Default "This is the default net class."
+    (clearance 0.2)
+    (trace_width 0.25)
+    (via_dia 0.6)
+    (via_drill 0.4)
+    (uvia_dia 0.3)
+    (uvia_drill 0.1)
+    (add_net "Net-(C1-Pad1)")
+    (add_net "Net-(C1-Pad2)")
+    (add_net "Net-(C2-Pad1)")
+    (add_net "Net-(C3-Pad1)")
+    (add_net "Net-(D1-Pad2)")
+    (add_net "Net-(J1-Pad1)")
+    (add_net "Net-(J2-Pad1)")
+  )
+
+  (module Capacitors_THT:C_Disc_D3.0mm_W2.0mm_P2.50mm (layer F.Cu) (tedit 597BC7C2) (tstamp 6A8951E6)
+    (at 146.05 106.68)
+    (descr "C, Disc series, Radial, pin pitch=2.50mm, , diameter*width=3*2mm^2, Capacitor")
+    (tags "C Disc series Radial pin pitch 2.50mm  diameter 3mm width 2mm Capacitor")
+    (path /6A89400C)
+    (fp_text reference C1 (at 1.25 -2.31) (layer F.SilkS)
+      (effects (font (size 1 1) (thickness 0.15)))
+    )
+    (fp_text value eSim_C (at 1.25 2.31) (layer F.Fab)
+      (effects (font (size 1 1) (thickness 0.15)))
+    )
+    (fp_line (start -0.25 -1) (end -0.25 1) (layer F.Fab) (width 0.1))
+    (fp_line (start -0.25 1) (end 2.75 1) (layer F.Fab) (width 0.1))
+    (fp_line (start 2.75 1) (end 2.75 -1) (layer F.Fab) (width 0.1))
+    (fp_line (start 2.75 -1) (end -0.25 -1) (layer F.Fab) (width 0.1))
+    (fp_line (start -0.31 -1.06) (end 2.81 -1.06) (layer F.SilkS) (width 0.12))
+    (fp_line (start -0.31 1.06) (end 2.81 1.06) (layer F.SilkS) (width 0.12))
+    (fp_line (start -0.31 -1.06) (end -0.31 -0.996) (layer F.SilkS) (width 0.12))
+    (fp_line (start -0.31 0.996) (end -0.31 1.06) (layer F.SilkS) (width 0.12))
+    (fp_line (start 2.81 -1.06) (end 2.81 -0.996) (layer F.SilkS) (width 0.12))
+    (fp_line (start 2.81 0.996) (end 2.81 1.06) (layer F.SilkS) (width 0.12))
+    (fp_line (start -1.05 -1.35) (end -1.05 1.35) (layer F.CrtYd) (width 0.05))
+    (fp_line (start -1.05 1.35) (end 3.55 1.35) (layer F.CrtYd) (width 0.05))
+    (fp_line (start 3.55 1.35) (end 3.55 -1.35) (layer F.CrtYd) (width 0.05))
+    (fp_line (start 3.55 -1.35) (end -1.05 -1.35) (layer F.CrtYd) (width 0.05))
+    (fp_text user %R (at 1.25 0) (layer F.Fab)
+      (effects (font (size 1 1) (thickness 0.15)))
+    )
+    (pad 1 thru_hole circle (at 0 0) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
+      (net 1 "Net-(C1-Pad1)"))
+    (pad 2 thru_hole circle (at 2.5 0) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
+      (net 2 "Net-(C1-Pad2)"))
+    (model ${KISYS3DMOD}/Capacitors_THT.3dshapes/C_Disc_D3.0mm_W2.0mm_P2.50mm.wrl
+      (at (xyz 0 0 0))
+      (scale (xyz 1 1 1))
+      (rotate (xyz 0 0 0))
+    )
+  )
+
+  (module Capacitors_THT:CP_Radial_D5.0mm_P2.00mm (layer F.Cu) (tedit 597BC7C2) (tstamp 6A89526B)
+    (at 138.43 106.68)
+    (descr "CP, Radial series, Radial, pin pitch=2.00mm, , diameter=5mm, Electrolytic Capacitor")
+    (tags "CP Radial series Radial pin pitch 2.00mm  diameter 5mm Electrolytic Capacitor")
+    (path /6A893F37)
+    (fp_text reference C2 (at 1 -3.81) (layer F.SilkS)
+      (effects (font (size 1 1) (thickness 0.15)))
+    )
+    (fp_text value eSim_CP1 (at 1 3.81) (layer F.Fab)
+      (effects (font (size 1 1) (thickness 0.15)))
+    )
+    (fp_arc (start 1 0) (end -1.30558 -1.18) (angle 125.8) (layer F.SilkS) (width 0.12))
+    (fp_arc (start 1 0) (end -1.30558 1.18) (angle -125.8) (layer F.SilkS) (width 0.12))
+    (fp_arc (start 1 0) (end 3.30558 -1.18) (angle 54.2) (layer F.SilkS) (width 0.12))
+    (fp_circle (center 1 0) (end 3.5 0) (layer F.Fab) (width 0.1))
+    (fp_line (start -2.2 0) (end -1 0) (layer F.Fab) (width 0.1))
+    (fp_line (start -1.6 -0.65) (end -1.6 0.65) (layer F.Fab) (width 0.1))
+    (fp_line (start 1 -2.55) (end 1 2.55) (layer F.SilkS) (width 0.12))
+    (fp_line (start 1.04 -2.55) (end 1.04 -0.98) (layer F.SilkS) (width 0.12))
+    (fp_line (start 1.04 0.98) (end 1.04 2.55) (layer F.SilkS) (width 0.12))
+    (fp_line (start 1.08 -2.549) (end 1.08 -0.98) (layer F.SilkS) (width 0.12))
+    (fp_line (start 1.08 0.98) (end 1.08 2.549) (layer F.SilkS) (width 0.12))
+    (fp_line (start 1.12 -2.548) (end 1.12 -0.98) (layer F.SilkS) (width 0.12))
+    (fp_line (start 1.12 0.98) (end 1.12 2.548) (layer F.SilkS) (width 0.12))
+    (fp_line (start 1.16 -2.546) (end 1.16 -0.98) (layer F.SilkS) (width 0.12))
+    (fp_line (start 1.16 0.98) (end 1.16 2.546) (layer F.SilkS) (width 0.12))
+    (fp_line (start 1.2 -2.543) (end 1.2 -0.98) (layer F.SilkS) (width 0.12))
+    (fp_line (start 1.2 0.98) (end 1.2 2.543) (layer F.SilkS) (width 0.12))
+    (fp_line (start 1.24 -2.539) (end 1.24 -0.98) (layer F.SilkS) (width 0.12))
+    (fp_line (start 1.24 0.98) (end 1.24 2.539) (layer F.SilkS) (width 0.12))
+    (fp_line (start 1.28 -2.535) (end 1.28 -0.98) (layer F.SilkS) (width 0.12))
+    (fp_line (start 1.28 0.98) (end 1.28 2.535) (layer F.SilkS) (width 0.12))
+    (fp_line (start 1.32 -2.531) (end 1.32 -0.98) (layer F.SilkS) (width 0.12))
+    (fp_line (start 1.32 0.98) (end 1.32 2.531) (layer F.SilkS) (width 0.12))
+    (fp_line (start 1.36 -2.525) (end 1.36 -0.98) (layer F.SilkS) (width 0.12))
+    (fp_line (start 1.36 0.98) (end 1.36 2.525) (layer F.SilkS) (width 0.12))
+    (fp_line (start 1.4 -2.519) (end 1.4 -0.98) (layer F.SilkS) (width 0.12))
+    (fp_line (start 1.4 0.98) (end 1.4 2.519) (layer F.SilkS) (width 0.12))
+    (fp_line (start 1.44 -2.513) (end 1.44 -0.98) (layer F.SilkS) (width 0.12))
+    (fp_line (start 1.44 0.98) (end 1.44 2.513) (layer F.SilkS) (width 0.12))
+    (fp_line (start 1.48 -2.506) (end 1.48 -0.98) (layer F.SilkS) (width 0.12))
+    (fp_line (start 1.48 0.98) (end 1.48 2.506) (layer F.SilkS) (width 0.12))
+    (fp_line (start 1.52 -2.498) (end 1.52 -0.98) (layer F.SilkS) (width 0.12))
+    (fp_line (start 1.52 0.98) (end 1.52 2.498) (layer F.SilkS) (width 0.12))
+    (fp_line (start 1.56 -2.489) (end 1.56 -0.98) (layer F.SilkS) (width 0.12))
+    (fp_line (start 1.56 0.98) (end 1.56 2.489) (layer F.SilkS) (width 0.12))
+    (fp_line (start 1.6 -2.48) (end 1.6 -0.98) (layer F.SilkS) (width 0.12))
+    (fp_line (start 1.6 0.98) (end 1.6 2.48) (layer F.SilkS) (width 0.12))
+    (fp_line (start 1.64 -2.47) (end 1.64 -0.98) (layer F.SilkS) (width 0.12))
+    (fp_line (start 1.64 0.98) (end 1.64 2.47) (layer F.SilkS) (width 0.12))
+    (fp_line (start 1.68 -2.46) (end 1.68 -0.98) (layer F.SilkS) (width 0.12))
+    (fp_line (start 1.68 0.98) (end 1.68 2.46) (layer F.SilkS) (width 0.12))
+    (fp_line (start 1.721 -2.448) (end 1.721 -0.98) (layer F.SilkS) (width 0.12))
+    (fp_line (start 1.721 0.98) (end 1.721 2.448) (layer F.SilkS) (width 0.12))
+    (fp_line (start 1.761 -2.436) (end 1.761 -0.98) (layer F.SilkS) (width 0.12))
+    (fp_line (start 1.761 0.98) (end 1.761 2.436) (layer F.SilkS) (width 0.12))
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+    (fp_line (start 1.801 0.98) (end 1.801 2.424) (layer F.SilkS) (width 0.12))
+    (fp_line (start 1.841 -2.41) (end 1.841 -0.98) (layer F.SilkS) (width 0.12))
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+    (fp_line (start 1.881 -2.396) (end 1.881 -0.98) (layer F.SilkS) (width 0.12))
+    (fp_line (start 1.881 0.98) (end 1.881 2.396) (layer F.SilkS) (width 0.12))
+    (fp_line (start 1.921 -2.382) (end 1.921 -0.98) (layer F.SilkS) (width 0.12))
+    (fp_line (start 1.921 0.98) (end 1.921 2.382) (layer F.SilkS) (width 0.12))
+    (fp_line (start 1.961 -2.366) (end 1.961 -0.98) (layer F.SilkS) (width 0.12))
+    (fp_line (start 1.961 0.98) (end 1.961 2.366) (layer F.SilkS) (width 0.12))
+    (fp_line (start 2.001 -2.35) (end 2.001 -0.98) (layer F.SilkS) (width 0.12))
+    (fp_line (start 2.001 0.98) (end 2.001 2.35) (layer F.SilkS) (width 0.12))
+    (fp_line (start 2.041 -2.333) (end 2.041 -0.98) (layer F.SilkS) (width 0.12))
+    (fp_line (start 2.041 0.98) (end 2.041 2.333) (layer F.SilkS) (width 0.12))
+    (fp_line (start 2.081 -2.315) (end 2.081 -0.98) (layer F.SilkS) (width 0.12))
+    (fp_line (start 2.081 0.98) (end 2.081 2.315) (layer F.SilkS) (width 0.12))
+    (fp_line (start 2.121 -2.296) (end 2.121 -0.98) (layer F.SilkS) (width 0.12))
+    (fp_line (start 2.121 0.98) (end 2.121 2.296) (layer F.SilkS) (width 0.12))
+    (fp_line (start 2.161 -2.276) (end 2.161 -0.98) (layer F.SilkS) (width 0.12))
+    (fp_line (start 2.161 0.98) (end 2.161 2.276) (layer F.SilkS) (width 0.12))
+    (fp_line (start 2.201 -2.256) (end 2.201 -0.98) (layer F.SilkS) (width 0.12))
+    (fp_line (start 2.201 0.98) (end 2.201 2.256) (layer F.SilkS) (width 0.12))
+    (fp_line (start 2.241 -2.234) (end 2.241 -0.98) (layer F.SilkS) (width 0.12))
+    (fp_line (start 2.241 0.98) (end 2.241 2.234) (layer F.SilkS) (width 0.12))
+    (fp_line (start 2.281 -2.212) (end 2.281 -0.98) (layer F.SilkS) (width 0.12))
+    (fp_line (start 2.281 0.98) (end 2.281 2.212) (layer F.SilkS) (width 0.12))
+    (fp_line (start 2.321 -2.189) (end 2.321 -0.98) (layer F.SilkS) (width 0.12))
+    (fp_line (start 2.321 0.98) (end 2.321 2.189) (layer F.SilkS) (width 0.12))
+    (fp_line (start 2.361 -2.165) (end 2.361 -0.98) (layer F.SilkS) (width 0.12))
+    (fp_line (start 2.361 0.98) (end 2.361 2.165) (layer F.SilkS) (width 0.12))
+    (fp_line (start 2.401 -2.14) (end 2.401 -0.98) (layer F.SilkS) (width 0.12))
+    (fp_line (start 2.401 0.98) (end 2.401 2.14) (layer F.SilkS) (width 0.12))
+    (fp_line (start 2.441 -2.113) (end 2.441 -0.98) (layer F.SilkS) (width 0.12))
+    (fp_line (start 2.441 0.98) (end 2.441 2.113) (layer F.SilkS) (width 0.12))
+    (fp_line (start 2.481 -2.086) (end 2.481 -0.98) (layer F.SilkS) (width 0.12))
+    (fp_line (start 2.481 0.98) (end 2.481 2.086) (layer F.SilkS) (width 0.12))
+    (fp_line (start 2.521 -2.058) (end 2.521 -0.98) (layer F.SilkS) (width 0.12))
+    (fp_line (start 2.521 0.98) (end 2.521 2.058) (layer F.SilkS) (width 0.12))
+    (fp_line (start 2.561 -2.028) (end 2.561 -0.98) (layer F.SilkS) (width 0.12))
+    (fp_line (start 2.561 0.98) (end 2.561 2.028) (layer F.SilkS) (width 0.12))
+    (fp_line (start 2.601 -1.997) (end 2.601 -0.98) (layer F.SilkS) (width 0.12))
+    (fp_line (start 2.601 0.98) (end 2.601 1.997) (layer F.SilkS) (width 0.12))
+    (fp_line (start 2.641 -1.965) (end 2.641 -0.98) (layer F.SilkS) (width 0.12))
+    (fp_line (start 2.641 0.98) (end 2.641 1.965) (layer F.SilkS) (width 0.12))
+    (fp_line (start 2.681 -1.932) (end 2.681 -0.98) (layer F.SilkS) (width 0.12))
+    (fp_line (start 2.681 0.98) (end 2.681 1.932) (layer F.SilkS) (width 0.12))
+    (fp_line (start 2.721 -1.897) (end 2.721 -0.98) (layer F.SilkS) (width 0.12))
+    (fp_line (start 2.721 0.98) (end 2.721 1.897) (layer F.SilkS) (width 0.12))
+    (fp_line (start 2.761 -1.861) (end 2.761 -0.98) (layer F.SilkS) (width 0.12))
+    (fp_line (start 2.761 0.98) (end 2.761 1.861) (layer F.SilkS) (width 0.12))
+    (fp_line (start 2.801 -1.823) (end 2.801 -0.98) (layer F.SilkS) (width 0.12))
+    (fp_line (start 2.801 0.98) (end 2.801 1.823) (layer F.SilkS) (width 0.12))
+    (fp_line (start 2.841 -1.783) (end 2.841 -0.98) (layer F.SilkS) (width 0.12))
+    (fp_line (start 2.841 0.98) (end 2.841 1.783) (layer F.SilkS) (width 0.12))
+    (fp_line (start 2.881 -1.742) (end 2.881 -0.98) (layer F.SilkS) (width 0.12))
+    (fp_line (start 2.881 0.98) (end 2.881 1.742) (layer F.SilkS) (width 0.12))
+    (fp_line (start 2.921 -1.699) (end 2.921 -0.98) (layer F.SilkS) (width 0.12))
+    (fp_line (start 2.921 0.98) (end 2.921 1.699) (layer F.SilkS) (width 0.12))
+    (fp_line (start 2.961 -1.654) (end 2.961 -0.98) (layer F.SilkS) (width 0.12))
+    (fp_line (start 2.961 0.98) (end 2.961 1.654) (layer F.SilkS) (width 0.12))
+    (fp_line (start 3.001 -1.606) (end 3.001 1.606) (layer F.SilkS) (width 0.12))
+    (fp_line (start 3.041 -1.556) (end 3.041 1.556) (layer F.SilkS) (width 0.12))
+    (fp_line (start 3.081 -1.504) (end 3.081 1.504) (layer F.SilkS) (width 0.12))
+    (fp_line (start 3.121 -1.448) (end 3.121 1.448) (layer F.SilkS) (width 0.12))
+    (fp_line (start 3.161 -1.39) (end 3.161 1.39) (layer F.SilkS) (width 0.12))
+    (fp_line (start 3.201 -1.327) (end 3.201 1.327) (layer F.SilkS) (width 0.12))
+    (fp_line (start 3.241 -1.261) (end 3.241 1.261) (layer F.SilkS) (width 0.12))
+    (fp_line (start 3.281 -1.189) (end 3.281 1.189) (layer F.SilkS) (width 0.12))
+    (fp_line (start 3.321 -1.112) (end 3.321 1.112) (layer F.SilkS) (width 0.12))
+    (fp_line (start 3.361 -1.028) (end 3.361 1.028) (layer F.SilkS) (width 0.12))
+    (fp_line (start 3.401 -0.934) (end 3.401 0.934) (layer F.SilkS) (width 0.12))
+    (fp_line (start 3.441 -0.829) (end 3.441 0.829) (layer F.SilkS) (width 0.12))
+    (fp_line (start 3.481 -0.707) (end 3.481 0.707) (layer F.SilkS) (width 0.12))
+    (fp_line (start 3.521 -0.559) (end 3.521 0.559) (layer F.SilkS) (width 0.12))
+    (fp_line (start 3.561 -0.354) (end 3.561 0.354) (layer F.SilkS) (width 0.12))
+    (fp_line (start -2.2 0) (end -1 0) (layer F.SilkS) (width 0.12))
+    (fp_line (start -1.6 -0.65) (end -1.6 0.65) (layer F.SilkS) (width 0.12))
+    (fp_line (start -1.85 -2.85) (end -1.85 2.85) (layer F.CrtYd) (width 0.05))
+    (fp_line (start -1.85 2.85) (end 3.85 2.85) (layer F.CrtYd) (width 0.05))
+    (fp_line (start 3.85 2.85) (end 3.85 -2.85) (layer F.CrtYd) (width 0.05))
+    (fp_line (start 3.85 -2.85) (end -1.85 -2.85) (layer F.CrtYd) (width 0.05))
+    (fp_text user %R (at 1 0) (layer F.Fab)
+      (effects (font (size 1 1) (thickness 0.15)))
+    )
+    (pad 1 thru_hole rect (at 0 0) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
+      (net 3 "Net-(C2-Pad1)"))
+    (pad 2 thru_hole circle (at 2 0) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
+      (net 2 "Net-(C1-Pad2)"))
+    (model ${KISYS3DMOD}/Capacitors_THT.3dshapes/CP_Radial_D5.0mm_P2.00mm.wrl
+      (at (xyz 0 0 0))
+      (scale (xyz 1 1 1))
+      (rotate (xyz 0 0 0))
+    )
+  )
+
+  (module Capacitors_THT:C_Disc_D3.0mm_W2.0mm_P2.50mm (layer F.Cu) (tedit 597BC7C2) (tstamp 6A895280)
+    (at 165.1 106.68)
+    (descr "C, Disc series, Radial, pin pitch=2.50mm, , diameter*width=3*2mm^2, Capacitor")
+    (tags "C Disc series Radial pin pitch 2.50mm  diameter 3mm width 2mm Capacitor")
+    (path /6A8941CB)
+    (fp_text reference C3 (at 1.25 -2.31) (layer F.SilkS)
+      (effects (font (size 1 1) (thickness 0.15)))
+    )
+    (fp_text value eSim_C (at 1.25 2.31) (layer F.Fab)
+      (effects (font (size 1 1) (thickness 0.15)))
+    )
+    (fp_line (start -0.25 -1) (end -0.25 1) (layer F.Fab) (width 0.1))
+    (fp_line (start -0.25 1) (end 2.75 1) (layer F.Fab) (width 0.1))
+    (fp_line (start 2.75 1) (end 2.75 -1) (layer F.Fab) (width 0.1))
+    (fp_line (start 2.75 -1) (end -0.25 -1) (layer F.Fab) (width 0.1))
+    (fp_line (start -0.31 -1.06) (end 2.81 -1.06) (layer F.SilkS) (width 0.12))
+    (fp_line (start -0.31 1.06) (end 2.81 1.06) (layer F.SilkS) (width 0.12))
+    (fp_line (start -0.31 -1.06) (end -0.31 -0.996) (layer F.SilkS) (width 0.12))
+    (fp_line (start -0.31 0.996) (end -0.31 1.06) (layer F.SilkS) (width 0.12))
+    (fp_line (start 2.81 -1.06) (end 2.81 -0.996) (layer F.SilkS) (width 0.12))
+    (fp_line (start 2.81 0.996) (end 2.81 1.06) (layer F.SilkS) (width 0.12))
+    (fp_line (start -1.05 -1.35) (end -1.05 1.35) (layer F.CrtYd) (width 0.05))
+    (fp_line (start -1.05 1.35) (end 3.55 1.35) (layer F.CrtYd) (width 0.05))
+    (fp_line (start 3.55 1.35) (end 3.55 -1.35) (layer F.CrtYd) (width 0.05))
+    (fp_line (start 3.55 -1.35) (end -1.05 -1.35) (layer F.CrtYd) (width 0.05))
+    (fp_text user %R (at 1.25 0) (layer F.Fab)
+      (effects (font (size 1 1) (thickness 0.15)))
+    )
+    (pad 1 thru_hole circle (at 0 0) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
+      (net 4 "Net-(C3-Pad1)"))
+    (pad 2 thru_hole circle (at 2.5 0) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
+      (net 2 "Net-(C1-Pad2)"))
+    (model ${KISYS3DMOD}/Capacitors_THT.3dshapes/C_Disc_D3.0mm_W2.0mm_P2.50mm.wrl
+      (at (xyz 0 0 0))
+      (scale (xyz 1 1 1))
+      (rotate (xyz 0 0 0))
+    )
+  )
+
+  (module LEDs:LED_D5.0mm (layer F.Cu) (tedit 5995936A) (tstamp 6A895292)
+    (at 186.69 106.68)
+    (descr "LED, diameter 5.0mm, 2 pins, http://cdn-reichelt.de/documents/datenblatt/A500/LL-504BC2E-009.pdf")
+    (tags "LED diameter 5.0mm 2 pins")
+    (path /6A8942FF)
+    (fp_text reference D1 (at 1.27 -3.96) (layer F.SilkS)
+      (effects (font (size 1 1) (thickness 0.15)))
+    )
+    (fp_text value eSim_LED (at 1.27 3.96) (layer F.Fab)
+      (effects (font (size 1 1) (thickness 0.15)))
+    )
+    (fp_arc (start 1.27 0) (end -1.23 -1.469694) (angle 299.1) (layer F.Fab) (width 0.1))
+    (fp_arc (start 1.27 0) (end -1.29 -1.54483) (angle 148.9) (layer F.SilkS) (width 0.12))
+    (fp_arc (start 1.27 0) (end -1.29 1.54483) (angle -148.9) (layer F.SilkS) (width 0.12))
+    (fp_circle (center 1.27 0) (end 3.77 0) (layer F.Fab) (width 0.1))
+    (fp_circle (center 1.27 0) (end 3.77 0) (layer F.SilkS) (width 0.12))
+    (fp_line (start -1.23 -1.469694) (end -1.23 1.469694) (layer F.Fab) (width 0.1))
+    (fp_line (start -1.29 -1.545) (end -1.29 1.545) (layer F.SilkS) (width 0.12))
+    (fp_line (start -1.95 -3.25) (end -1.95 3.25) (layer F.CrtYd) (width 0.05))
+    (fp_line (start -1.95 3.25) (end 4.5 3.25) (layer F.CrtYd) (width 0.05))
+    (fp_line (start 4.5 3.25) (end 4.5 -3.25) (layer F.CrtYd) (width 0.05))
+    (fp_line (start 4.5 -3.25) (end -1.95 -3.25) (layer F.CrtYd) (width 0.05))
+    (fp_text user %R (at 1.25 0) (layer F.Fab)
+      (effects (font (size 0.8 0.8) (thickness 0.2)))
+    )
+    (pad 1 thru_hole rect (at 0 0) (size 1.8 1.8) (drill 0.9) (layers *.Cu *.Mask)
+      (net 2 "Net-(C1-Pad2)"))
+    (pad 2 thru_hole circle (at 2.54 0) (size 1.8 1.8) (drill 0.9) (layers *.Cu *.Mask)
+      (net 5 "Net-(D1-Pad2)"))
+    (model ${KISYS3DMOD}/LEDs.3dshapes/LED_D5.0mm.wrl
+      (at (xyz 0 0 0))
+      (scale (xyz 0.393701 0.393701 0.393701))
+      (rotate (xyz 0 0 0))
+    )
+  )
+
+  (module Pin_Headers:Pin_Header_Straight_1x02_Pitch2.54mm (layer F.Cu) (tedit 59650532) (tstamp 6A8952A8)
+    (at 130.81 105.41)
+    (descr "Through hole straight pin header, 1x02, 2.54mm pitch, single row")
+    (tags "Through hole pin header THT 1x02 2.54mm single row")
+    (path /6A893EDE)
+    (fp_text reference J1 (at 0 -2.33) (layer F.SilkS)
+      (effects (font (size 1 1) (thickness 0.15)))
+    )
+    (fp_text value Conn_01x02 (at 0 4.87) (layer F.Fab)
+      (effects (font (size 1 1) (thickness 0.15)))
+    )
+    (fp_line (start -0.635 -1.27) (end 1.27 -1.27) (layer F.Fab) (width 0.1))
+    (fp_line (start 1.27 -1.27) (end 1.27 3.81) (layer F.Fab) (width 0.1))
+    (fp_line (start 1.27 3.81) (end -1.27 3.81) (layer F.Fab) (width 0.1))
+    (fp_line (start -1.27 3.81) (end -1.27 -0.635) (layer F.Fab) (width 0.1))
+    (fp_line (start -1.27 -0.635) (end -0.635 -1.27) (layer F.Fab) (width 0.1))
+    (fp_line (start -1.33 3.87) (end 1.33 3.87) (layer F.SilkS) (width 0.12))
+    (fp_line (start -1.33 1.27) (end -1.33 3.87) (layer F.SilkS) (width 0.12))
+    (fp_line (start 1.33 1.27) (end 1.33 3.87) (layer F.SilkS) (width 0.12))
+    (fp_line (start -1.33 1.27) (end 1.33 1.27) (layer F.SilkS) (width 0.12))
+    (fp_line (start -1.33 0) (end -1.33 -1.33) (layer F.SilkS) (width 0.12))
+    (fp_line (start -1.33 -1.33) (end 0 -1.33) (layer F.SilkS) (width 0.12))
+    (fp_line (start -1.8 -1.8) (end -1.8 4.35) (layer F.CrtYd) (width 0.05))
+    (fp_line (start -1.8 4.35) (end 1.8 4.35) (layer F.CrtYd) (width 0.05))
+    (fp_line (start 1.8 4.35) (end 1.8 -1.8) (layer F.CrtYd) (width 0.05))
+    (fp_line (start 1.8 -1.8) (end -1.8 -1.8) (layer F.CrtYd) (width 0.05))
+    (fp_text user %R (at 0 1.27 90) (layer F.Fab)
+      (effects (font (size 1 1) (thickness 0.15)))
+    )
+    (pad 1 thru_hole rect (at 0 0) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
+      (net 6 "Net-(J1-Pad1)"))
+    (pad 2 thru_hole oval (at 0 2.54) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
+      (net 2 "Net-(C1-Pad2)"))
+    (model ${KISYS3DMOD}/Pin_Headers.3dshapes/Pin_Header_Straight_1x02_Pitch2.54mm.wrl
+      (at (xyz 0 0 0))
+      (scale (xyz 1 1 1))
+      (rotate (xyz 0 0 0))
+    )
+  )
+
+  (module Pin_Headers:Pin_Header_Straight_1x02_Pitch2.54mm (layer F.Cu) (tedit 59650532) (tstamp 6A8952BE)
+    (at 198.12 105.41)
+    (descr "Through hole straight pin header, 1x02, 2.54mm pitch, single row")
+    (tags "Through hole pin header THT 1x02 2.54mm single row")
+    (path /6A89452E)
+    (fp_text reference J2 (at 0 -2.33) (layer F.SilkS)
+      (effects (font (size 1 1) (thickness 0.15)))
+    )
+    (fp_text value Conn_01x02 (at 0 4.87) (layer F.Fab)
+      (effects (font (size 1 1) (thickness 0.15)))
+    )
+    (fp_line (start -0.635 -1.27) (end 1.27 -1.27) (layer F.Fab) (width 0.1))
+    (fp_line (start 1.27 -1.27) (end 1.27 3.81) (layer F.Fab) (width 0.1))
+    (fp_line (start 1.27 3.81) (end -1.27 3.81) (layer F.Fab) (width 0.1))
+    (fp_line (start -1.27 3.81) (end -1.27 -0.635) (layer F.Fab) (width 0.1))
+    (fp_line (start -1.27 -0.635) (end -0.635 -1.27) (layer F.Fab) (width 0.1))
+    (fp_line (start -1.33 3.87) (end 1.33 3.87) (layer F.SilkS) (width 0.12))
+    (fp_line (start -1.33 1.27) (end -1.33 3.87) (layer F.SilkS) (width 0.12))
+    (fp_line (start 1.33 1.27) (end 1.33 3.87) (layer F.SilkS) (width 0.12))
+    (fp_line (start -1.33 1.27) (end 1.33 1.27) (layer F.SilkS) (width 0.12))
+    (fp_line (start -1.33 0) (end -1.33 -1.33) (layer F.SilkS) (width 0.12))
+    (fp_line (start -1.33 -1.33) (end 0 -1.33) (layer F.SilkS) (width 0.12))
+    (fp_line (start -1.8 -1.8) (end -1.8 4.35) (layer F.CrtYd) (width 0.05))
+    (fp_line (start -1.8 4.35) (end 1.8 4.35) (layer F.CrtYd) (width 0.05))
+    (fp_line (start 1.8 4.35) (end 1.8 -1.8) (layer F.CrtYd) (width 0.05))
+    (fp_line (start 1.8 -1.8) (end -1.8 -1.8) (layer F.CrtYd) (width 0.05))
+    (fp_text user %R (at 0 1.27 90) (layer F.Fab)
+      (effects (font (size 1 1) (thickness 0.15)))
+    )
+    (pad 1 thru_hole rect (at 0 0) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
+      (net 7 "Net-(J2-Pad1)"))
+    (pad 2 thru_hole oval (at 0 2.54) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
+      (net 2 "Net-(C1-Pad2)"))
+    (model ${KISYS3DMOD}/Pin_Headers.3dshapes/Pin_Header_Straight_1x02_Pitch2.54mm.wrl
+      (at (xyz 0 0 0))
+      (scale (xyz 1 1 1))
+      (rotate (xyz 0 0 0))
+    )
+  )
+
+  (module Resistors_THT:R_Axial_DIN0207_L6.3mm_D2.5mm_P7.62mm_Horizontal (layer F.Cu) (tedit 5874F706) (tstamp 6A8952D4)
+    (at 171.45 106.68)
+    (descr "Resistor, Axial_DIN0207 series, Axial, Horizontal, pin pitch=7.62mm, 0.25W = 1/4W, length*diameter=6.3*2.5mm^2, http://cdn-reichelt.de/documents/datenblatt/B400/1_4W%23YAG.pdf")
+    (tags "Resistor Axial_DIN0207 series Axial Horizontal pin pitch 7.62mm 0.25W = 1/4W length 6.3mm diameter 2.5mm")
+    (path /6A89426C)
+    (fp_text reference R1 (at 3.81 -2.31) (layer F.SilkS)
+      (effects (font (size 1 1) (thickness 0.15)))
+    )
+    (fp_text value eSim_R (at 3.81 2.31) (layer F.Fab)
+      (effects (font (size 1 1) (thickness 0.15)))
+    )
+    (fp_line (start 0.66 -1.25) (end 0.66 1.25) (layer F.Fab) (width 0.1))
+    (fp_line (start 0.66 1.25) (end 6.96 1.25) (layer F.Fab) (width 0.1))
+    (fp_line (start 6.96 1.25) (end 6.96 -1.25) (layer F.Fab) (width 0.1))
+    (fp_line (start 6.96 -1.25) (end 0.66 -1.25) (layer F.Fab) (width 0.1))
+    (fp_line (start 0 0) (end 0.66 0) (layer F.Fab) (width 0.1))
+    (fp_line (start 7.62 0) (end 6.96 0) (layer F.Fab) (width 0.1))
+    (fp_line (start 0.6 -0.98) (end 0.6 -1.31) (layer F.SilkS) (width 0.12))
+    (fp_line (start 0.6 -1.31) (end 7.02 -1.31) (layer F.SilkS) (width 0.12))
+    (fp_line (start 7.02 -1.31) (end 7.02 -0.98) (layer F.SilkS) (width 0.12))
+    (fp_line (start 0.6 0.98) (end 0.6 1.31) (layer F.SilkS) (width 0.12))
+    (fp_line (start 0.6 1.31) (end 7.02 1.31) (layer F.SilkS) (width 0.12))
+    (fp_line (start 7.02 1.31) (end 7.02 0.98) (layer F.SilkS) (width 0.12))
+    (fp_line (start -1.05 -1.6) (end -1.05 1.6) (layer F.CrtYd) (width 0.05))
+    (fp_line (start -1.05 1.6) (end 8.7 1.6) (layer F.CrtYd) (width 0.05))
+    (fp_line (start 8.7 1.6) (end 8.7 -1.6) (layer F.CrtYd) (width 0.05))
+    (fp_line (start 8.7 -1.6) (end -1.05 -1.6) (layer F.CrtYd) (width 0.05))
+    (pad 1 thru_hole circle (at 0 0) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
+      (net 7 "Net-(J2-Pad1)"))
+    (pad 2 thru_hole oval (at 7.62 0) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
+      (net 5 "Net-(D1-Pad2)"))
+    (model ${KISYS3DMOD}/Resistors_THT.3dshapes/R_Axial_DIN0207_L6.3mm_D2.5mm_P7.62mm_Horizontal.wrl
+      (at (xyz 0 0 0))
+      (scale (xyz 0.393701 0.393701 0.393701))
+      (rotate (xyz 0 0 0))
+    )
+  )
+
+  (module TO_SOT_Packages_THT:TO-220_Vertical (layer F.Cu) (tedit 58CE52AD) (tstamp 6A8952EE)
+    (at 153.67 106.68)
+    (descr "TO-220, Vertical, RM 2.54mm")
+    (tags "TO-220 Vertical RM 2.54mm")
+    (path /6A894156)
+    (fp_text reference U1 (at 2.54 -3.62) (layer F.SilkS)
+      (effects (font (size 1 1) (thickness 0.15)))
+    )
+    (fp_text value L7805 (at 2.54 3.92) (layer F.Fab)
+      (effects (font (size 1 1) (thickness 0.15)))
+    )
+    (fp_text user %R (at 2.54 -3.62) (layer F.Fab)
+      (effects (font (size 1 1) (thickness 0.15)))
+    )
+    (fp_line (start -2.46 -2.5) (end -2.46 1.9) (layer F.Fab) (width 0.1))
+    (fp_line (start -2.46 1.9) (end 7.54 1.9) (layer F.Fab) (width 0.1))
+    (fp_line (start 7.54 1.9) (end 7.54 -2.5) (layer F.Fab) (width 0.1))
+    (fp_line (start 7.54 -2.5) (end -2.46 -2.5) (layer F.Fab) (width 0.1))
+    (fp_line (start -2.46 -1.23) (end 7.54 -1.23) (layer F.Fab) (width 0.1))
+    (fp_line (start 0.69 -2.5) (end 0.69 -1.23) (layer F.Fab) (width 0.1))
+    (fp_line (start 4.39 -2.5) (end 4.39 -1.23) (layer F.Fab) (width 0.1))
+    (fp_line (start -2.58 -2.62) (end 7.66 -2.62) (layer F.SilkS) (width 0.12))
+    (fp_line (start -2.58 2.021) (end 7.66 2.021) (layer F.SilkS) (width 0.12))
+    (fp_line (start -2.58 -2.62) (end -2.58 2.021) (layer F.SilkS) (width 0.12))
+    (fp_line (start 7.66 -2.62) (end 7.66 2.021) (layer F.SilkS) (width 0.12))
+    (fp_line (start -2.58 -1.11) (end 7.66 -1.11) (layer F.SilkS) (width 0.12))
+    (fp_line (start 0.69 -2.62) (end 0.69 -1.11) (layer F.SilkS) (width 0.12))
+    (fp_line (start 4.391 -2.62) (end 4.391 -1.11) (layer F.SilkS) (width 0.12))
+    (fp_line (start -2.71 -2.75) (end -2.71 2.16) (layer F.CrtYd) (width 0.05))
+    (fp_line (start -2.71 2.16) (end 7.79 2.16) (layer F.CrtYd) (width 0.05))
+    (fp_line (start 7.79 2.16) (end 7.79 -2.75) (layer F.CrtYd) (width 0.05))
+    (fp_line (start 7.79 -2.75) (end -2.71 -2.75) (layer F.CrtYd) (width 0.05))
+    (pad 1 thru_hole rect (at 0 0) (size 1.8 1.8) (drill 1) (layers *.Cu *.Mask)
+      (net 6 "Net-(J1-Pad1)"))
+    (pad 2 thru_hole oval (at 2.54 0) (size 1.8 1.8) (drill 1) (layers *.Cu *.Mask)
+      (net 2 "Net-(C1-Pad2)"))
+    (pad 3 thru_hole oval (at 5.08 0) (size 1.8 1.8) (drill 1) (layers *.Cu *.Mask)
+      (net 7 "Net-(J2-Pad1)"))
+    (model ${KISYS3DMOD}/TO_SOT_Packages_THT.3dshapes/TO-220_Vertical.wrl
+      (at (xyz 0.1 0 0))
+      (scale (xyz 0.393701 0.393701 0.393701))
+      (rotate (xyz 0 0 0))
+    )
+  )
+
+  (segment (start 130.81 107.95) (end 130.81 111.76) (width 0.25) (layer B.Cu) (net 2))
+  (segment (start 140.43 111.03) (end 140.43 106.68) (width 0.25) (layer B.Cu) (net 2) (tstamp 6A895D95))
+  (segment (start 139.7 111.76) (end 140.43 111.03) (width 0.25) (layer B.Cu) (net 2) (tstamp 6A895D93))
+  (segment (start 130.81 111.76) (end 139.7 111.76) (width 0.25) (layer B.Cu) (net 2) (tstamp 6A895D8E))
+  (segment (start 140.43 106.68) (end 143.51 109.76) (width 0.25) (layer B.Cu) (net 2) (tstamp 6A895D97))
+  (segment (start 143.51 109.76) (end 143.51 111.76) (width 0.25) (layer B.Cu) (net 2) (tstamp 6A895D99))
+  (segment (start 143.51 111.76) (end 148.59 111.76) (width 0.25) (layer B.Cu) (net 2) (tstamp 6A895D9D))
+  (segment (start 148.59 111.76) (end 148.55 111.72) (width 0.25) (layer B.Cu) (net 2) (tstamp 6A895D9F))
+  (segment (start 148.55 111.72) (end 148.55 106.68) (width 0.25) (layer B.Cu) (net 2) (tstamp 6A895DA1))
+  (segment (start 148.55 106.68) (end 151.13 109.26) (width 0.25) (layer B.Cu) (net 2) (tstamp 6A895DA2))
+  (segment (start 151.13 109.26) (end 151.13 111.76) (width 0.25) (layer B.Cu) (net 2) (tstamp 6A895DA4))
+  (segment (start 151.13 111.76) (end 156.21 111.76) (width 0.25) (layer B.Cu) (net 2) (tstamp 6A895DA7))
+  (segment (start 156.21 111.76) (end 156.21 106.68) (width 0.25) (layer B.Cu) (net 2) (tstamp 6A895DA9))
+  (segment (start 156.21 106.68) (end 160.02 110.49) (width 0.25) (layer B.Cu) (net 2) (tstamp 6A895DAC))
+  (segment (start 160.02 110.49) (end 160.02 111.76) (width 0.25) (layer B.Cu) (net 2) (tstamp 6A895DAD))
+  (segment (start 160.02 111.76) (end 167.64 111.76) (width 0.25) (layer B.Cu) (net 2) (tstamp 6A895DB6))
+  (segment (start 167.64 111.76) (end 167.6 111.72) (width 0.25) (layer B.Cu) (net 2) (tstamp 6A895DB8))
+  (segment (start 167.6 111.72) (end 167.6 106.68) (width 0.25) (layer B.Cu) (net 2) (tstamp 6A895DBB))
+  (segment (start 167.6 106.68) (end 170.18 109.26) (width 0.25) (layer B.Cu) (net 2) (tstamp 6A895DBD))
+  (segment (start 170.18 109.26) (end 170.18 111.76) (width 0.25) (layer B.Cu) (net 2) (tstamp 6A895DBF))
+  (segment (start 170.18 111.76) (end 180.34 111.76) (width 0.25) (layer B.Cu) (net 2) (tstamp 6A895DC2))
+  (segment (start 180.34 111.76) (end 181.61 111.76) (width 0.25) (layer B.Cu) (net 2) (tstamp 6A895DC3))
+  (segment (start 181.61 111.76) (end 186.69 106.68) (width 0.25) (layer B.Cu) (net 2) (tstamp 6A895DC6))
+  (segment (start 186.69 106.68) (end 186.69 113.03) (width 0.25) (layer B.Cu) (net 2) (tstamp 6A895DCA))
+  (segment (start 186.69 113.03) (end 194.31 113.03) (width 0.25) (layer B.Cu) (net 2) (tstamp 6A895DCD))
+  (segment (start 194.31 113.03) (end 198.12 109.22) (width 0.25) (layer B.Cu) (net 2) (tstamp 6A895DCF))
+  (segment (start 198.12 109.22) (end 198.12 107.95) (width 0.25) (layer B.Cu) (net 2) (tstamp 6A895DD1))
+  (segment (start 179.07 106.68) (end 180.34 106.68) (width 0.25) (layer F.Cu) (net 5))
+  (segment (start 186.69 104.14) (end 189.23 106.68) (width 0.25) (layer F.Cu) (net 5) (tstamp 6A895F59))
+  (segment (start 182.88 104.14) (end 186.69 104.14) (width 0.25) (layer F.Cu) (net 5) (tstamp 6A895F57))
+  (segment (start 180.34 106.68) (end 182.88 104.14) (width 0.25) (layer F.Cu) (net 5) (tstamp 6A895F4B))
+  (segment (start 130.81 105.41) (end 130.81 104.14) (width 0.25) (layer F.Cu) (net 6))
+  (segment (start 153.67 104.14) (end 153.67 106.68) (width 0.25) (layer F.Cu) (net 6) (tstamp 6A895E94))
+  (segment (start 152.4 102.87) (end 153.67 104.14) (width 0.25) (layer F.Cu) (net 6) (tstamp 6A895E92))
+  (segment (start 132.08 102.87) (end 152.4 102.87) (width 0.25) (layer F.Cu) (net 6) (tstamp 6A895E8F))
+  (segment (start 130.81 104.14) (end 132.08 102.87) (width 0.25) (layer F.Cu) (net 6) (tstamp 6A895E8B))
+  (segment (start 158.75 106.68) (end 158.75 104.14) (width 0.25) (layer F.Cu) (net 7))
+  (segment (start 171.45 104.14) (end 171.45 106.68) (width 0.25) (layer F.Cu) (net 7) (tstamp 6A895E70))
+  (segment (start 170.18 102.87) (end 171.45 104.14) (width 0.25) (layer F.Cu) (net 7) (tstamp 6A895E6F))
+  (segment (start 167.64 102.87) (end 170.18 102.87) (width 0.25) (layer F.Cu) (net 7) (tstamp 6A895E6A))
+  (segment (start 160.02 102.87) (end 167.64 102.87) (width 0.25) (layer F.Cu) (net 7) (tstamp 6A895E5B))
+  (segment (start 158.75 104.14) (end 160.02 102.87) (width 0.25) (layer F.Cu) (net 7) (tstamp 6A895E50))
+  (segment (start 171.45 106.68) (end 175.26 102.87) (width 0.25) (layer F.Cu) (net 7) (tstamp 6A895E72))
+  (segment (start 175.26 102.87) (end 195.58 102.87) (width 0.25) (layer F.Cu) (net 7) (tstamp 6A895E73))
+  (segment (start 195.58 102.87) (end 198.12 105.41) (width 0.25) (layer F.Cu) (net 7) (tstamp 6A895E7B))
+
+)
diff --git a/Task7_PowerSupply.net b/Task7_PowerSupply.net
new file mode 100644
index 0000000..16a383c
--- /dev/null
+++ b/Task7_PowerSupply.net
@@ -0,0 +1,180 @@
+(export (version D)
+  (design
+    (source C:\eSim-Workspace\Task7_PowerSupply\Task7_PowerSupply.sch)
+    (date "08/22/26 13:02:09")
+    (tool "Eeschema 4.0.7")
+    (sheet (number 1) (name /) (tstamps /)
+      (title_block
+        (title)
+        (company)
+        (rev)
+        (date)
+        (source Task7_PowerSupply.sch)
+        (comment (number 1) (value ""))
+        (comment (number 2) (value ""))
+        (comment (number 3) (value ""))
+        (comment (number 4) (value "")))))
+  (components
+    (comp (ref J1)
+      (value Conn_01x02)
+      (footprint Pin_Headers:Pin_Header_Straight_1x02_Pitch2.54mm)
+      (libsource (lib conn) (part Conn_01x02))
+      (sheetpath (names /) (tstamps /))
+      (tstamp 6A893EDE))
+    (comp (ref C2)
+      (value eSim_CP1)
+      (footprint Capacitors_THT:CP_Radial_D5.0mm_P2.00mm)
+      (libsource (lib eSim_Devices) (part eSim_CP1))
+      (sheetpath (names /) (tstamps /))
+      (tstamp 6A893F37))
+    (comp (ref C1)
+      (value eSim_C)
+      (footprint Capacitors_THT:C_Disc_D3.0mm_W2.0mm_P2.50mm)
+      (libsource (lib eSim_Devices) (part eSim_C))
+      (sheetpath (names /) (tstamps /))
+      (tstamp 6A89400C))
+    (comp (ref U1)
+      (value L7805)
+      (footprint TO_SOT_Packages_THT:TO-220_Vertical)
+      (libsource (lib regul) (part L7805))
+      (sheetpath (names /) (tstamps /))
+      (tstamp 6A894156))
+    (comp (ref C3)
+      (value eSim_C)
+      (footprint Capacitors_THT:C_Disc_D3.0mm_W2.0mm_P2.50mm)
+      (libsource (lib eSim_Devices) (part eSim_C))
+      (sheetpath (names /) (tstamps /))
+      (tstamp 6A8941CB))
+    (comp (ref R1)
+      (value eSim_R)
+      (footprint Resistors_THT:R_Axial_DIN0207_L6.3mm_D2.5mm_P7.62mm_Horizontal)
+      (libsource (lib eSim_Devices) (part eSim_R))
+      (sheetpath (names /) (tstamps /))
+      (tstamp 6A89426C))
+    (comp (ref D1)
+      (value eSim_LED)
+      (footprint LEDs:LED_D5.0mm)
+      (libsource (lib eSim_Devices) (part eSim_LED))
+      (sheetpath (names /) (tstamps /))
+      (tstamp 6A8942FF))
+    (comp (ref J2)
+      (value Conn_01x02)
+      (footprint Pin_Headers:Pin_Header_Straight_1x02_Pitch2.54mm)
+      (libsource (lib conn) (part Conn_01x02))
+      (sheetpath (names /) (tstamps /))
+      (tstamp 6A89452E)))
+  (libparts
+    (libpart (lib conn) (part Conn_01x02)
+      (description "Generic connector, single row, 01x02")
+      (docs ~)
+      (footprints
+        (fp Connector*:*_??x*mm*)
+        (fp Connector*:*1x??x*mm*)
+        (fp Pin?Header?Straight?1X*)
+        (fp Pin?Header?Angled?1X*)
+        (fp Socket?Strip?Straight?1X*)
+        (fp Socket?Strip?Angled?1X*))
+      (fields
+        (field (name Reference) J)
+        (field (name Value) Conn_01x02))
+      (pins
+        (pin (num 1) (name Pin_1) (type passive))
+        (pin (num 2) (name Pin_2) (type passive))))
+    (libpart (lib regul) (part L7805)
+      (aliases
+        (alias L7806)
+        (alias L7808)
+        (alias L7885)
+        (alias L7809)
+        (alias L7812)
+        (alias L7815)
+        (alias L7818)
+        (alias L7824))
+      (description "Positive 1.5A 35V Linear Regulator, Fixed Output 5V, TO-220/TO-263/TO-252")
+      (docs http://www.st.com/content/ccc/resource/technical/document/datasheet/41/4f/b3/b0/12/d4/47/88/CD00000444.pdf/files/CD00000444.pdf/jcr:content/translations/en.CD00000444.pdf)
+      (footprints
+        (fp TO?252*)
+        (fp TO?263*)
+        (fp TO?220*))
+      (fields
+        (field (name Reference) U)
+        (field (name Value) L7805))
+      (pins
+        (pin (num 1) (name IN) (type power_in))
+        (pin (num 2) (name GND) (type power_in))
+        (pin (num 3) (name OUT) (type power_out))))
+    (libpart (lib eSim_Devices) (part eSim_C)
+      (aliases
+        (alias capacitor))
+      (footprints
+        (fp C_*))
+      (fields
+        (field (name Reference) C)
+        (field (name Value) eSim_C))
+      (pins
+        (pin (num 1) (name ~) (type passive))
+        (pin (num 2) (name ~) (type passive))))
+    (libpart (lib eSim_Devices) (part eSim_CP1)
+      (aliases
+        (alias capacitor_polarised))
+      (footprints
+        (fp CP_*))
+      (fields
+        (field (name Reference) C)
+        (field (name Value) eSim_CP1))
+      (pins
+        (pin (num 1) (name ~) (type passive))
+        (pin (num 2) (name ~) (type passive))))
+    (libpart (lib eSim_Devices) (part eSim_LED)
+      (footprints
+        (fp LED*))
+      (fields
+        (field (name Reference) D)
+        (field (name Value) eSim_LED))
+      (pins
+        (pin (num 1) (name A) (type passive))
+        (pin (num 2) (name K) (type passive))))
+    (libpart (lib eSim_Devices) (part eSim_R)
+      (aliases
+        (alias resistor))
+      (footprints
+        (fp R_*)
+        (fp Resistor_*))
+      (fields
+        (field (name Reference) R)
+        (field (name Value) eSim_R))
+      (pins
+        (pin (num 1) (name ~) (type passive))
+        (pin (num 2) (name ~) (type passive)))))
+  (libraries
+    (library (logical regul)
+      (uri C:\FOSSEE\KiCad\share\kicad\library\regul.lib))
+    (library (logical eSim_Devices)
+      (uri C:\FOSSEE\KiCad\share\kicad\library\eSim_Devices.lib))
+    (library (logical conn)
+      (uri C:\FOSSEE\KiCad\share\kicad\library\conn.lib)))
+  (nets
+    (net (code 1) (name "Net-(J1-Pad1)")
+      (node (ref U1) (pin 1))
+      (node (ref J1) (pin 1)))
+    (net (code 2) (name "Net-(J2-Pad1)")
+      (node (ref R1) (pin 1))
+      (node (ref U1) (pin 3))
+      (node (ref J2) (pin 1)))
+    (net (code 3) (name "Net-(D1-Pad2)")
+      (node (ref R1) (pin 2))
+      (node (ref D1) (pin 2)))
+    (net (code 4) (name "Net-(C2-Pad1)")
+      (node (ref C2) (pin 1)))
+    (net (code 5) (name "Net-(C1-Pad1)")
+      (node (ref C1) (pin 1)))
+    (net (code 6) (name "Net-(C1-Pad2)")
+      (node (ref D1) (pin 1))
+      (node (ref C3) (pin 2))
+      (node (ref J2) (pin 2))
+      (node (ref U1) (pin 2))
+      (node (ref C1) (pin 2))
+      (node (ref C2) (pin 2))
+      (node (ref J1) (pin 2)))
+    (net (code 7) (name "Net-(C3-Pad1)")
+      (node (ref C3) (pin 1)))))
\ No newline at end of file
diff --git a/Task7_PowerSupply.pro b/Task7_PowerSupply.pro
new file mode 100644
index 0000000..e27a398
--- /dev/null
+++ b/Task7_PowerSupply.pro
@@ -0,0 +1,73 @@
+update=22/05/2015 07:44:53
+version=1
+last_client=kicad
+[general]
+version=1
+RootSch=
+BoardNm=
+[pcbnew]
+version=1
+LastNetListRead=
+UseCmpFile=1
+PadDrill=0.600000000000
+PadDrillOvalY=0.600000000000
+PadSizeH=1.500000000000
+PadSizeV=1.500000000000
+PcbTextSizeV=1.500000000000
+PcbTextSizeH=1.500000000000
+PcbTextThickness=0.300000000000
+ModuleTextSizeV=1.000000000000
+ModuleTextSizeH=1.000000000000
+ModuleTextSizeThickness=0.150000000000
+SolderMaskClearance=0.000000000000
+SolderMaskMinWidth=0.000000000000
+DrawSegmentWidth=0.200000000000
+BoardOutlineThickness=0.100000000000
+ModuleOutlineThickness=0.150000000000
+[cvpcb]
+version=1
+NetIExt=net
+[eeschema]
+version=1
+LibDir=
+[eeschema/libraries]
+LibName1=adc-dac
+LibName2=memory
+LibName3=xilinx
+LibName4=microcontrollers
+LibName5=dsp
+LibName6=microchip
+LibName7=analog_switches
+LibName8=motorola
+LibName9=texas
+LibName10=intel
+LibName11=audio
+LibName12=interface
+LibName13=digital-audio
+LibName14=philips
+LibName15=display
+LibName16=cypress
+LibName17=siliconi
+LibName18=opto
+LibName19=atmel
+LibName20=contrib
+LibName21=power
+LibName22=eSim_Plot
+LibName23=transistors
+LibName24=conn
+LibName25=eSim_User
+LibName26=regul
+LibName27=74xx
+LibName28=cmos4000
+LibName29=eSim_Analog
+LibName30=eSim_Devices
+LibName31=eSim_Digital
+LibName32=eSim_Hybrid
+LibName33=eSim_Miscellaneous
+LibName34=eSim_Power
+LibName35=eSim_Sources
+LibName36=eSim_Subckt
+LibName37=eSim_Nghdl
+LibName38=eSim_Ngveri
+LibName39=eSim_SKY130
+LibName40=eSim_SKY130_Subckts
diff --git a/Task7_PowerSupply.proj b/Task7_PowerSupply.proj
new file mode 100644
index 0000000..791c2e9
--- /dev/null
+++ b/Task7_PowerSupply.proj
@@ -0,0 +1 @@
+schematicFile Task7_PowerSupply.sch
diff --git a/Task7_PowerSupply.sch b/Task7_PowerSupply.sch
new file mode 100644
index 0000000..2aef566
--- /dev/null
+++ b/Task7_PowerSupply.sch
@@ -0,0 +1,187 @@
+EESchema Schematic File Version 2
+LIBS:adc-dac
+LIBS:memory
+LIBS:xilinx
+LIBS:microcontrollers
+LIBS:dsp
+LIBS:microchip
+LIBS:analog_switches
+LIBS:motorola
+LIBS:texas
+LIBS:intel
+LIBS:audio
+LIBS:interface
+LIBS:digital-audio
+LIBS:philips
+LIBS:display
+LIBS:cypress
+LIBS:siliconi
+LIBS:opto
+LIBS:atmel
+LIBS:contrib
+LIBS:power
+LIBS:eSim_Plot
+LIBS:transistors
+LIBS:conn
+LIBS:eSim_User
+LIBS:regul
+LIBS:74xx
+LIBS:cmos4000
+LIBS:eSim_Analog
+LIBS:eSim_Devices
+LIBS:eSim_Digital
+LIBS:eSim_Hybrid
+LIBS:eSim_Miscellaneous
+LIBS:eSim_Power
+LIBS:eSim_Sources
+LIBS:eSim_Subckt
+LIBS:eSim_Nghdl
+LIBS:eSim_Ngveri
+LIBS:eSim_SKY130
+LIBS:eSim_SKY130_Subckts
+EELAYER 25 0
+EELAYER END
+$Descr A4 11693 8268
+encoding utf-8
+Sheet 1 1
+Title ""
+Date ""
+Rev ""
+Comp ""
+Comment1 ""
+Comment2 ""
+Comment3 ""
+Comment4 ""
+$EndDescr
+$Comp
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+U 1 1 6A893EDE
+P 4950 3600
+F 0 "J1" H 4950 3700 50  0000 C CNN
+F 1 "Conn_01x02" H 4950 3400 50  0000 C CNN
+F 2 "Pin_Headers:Pin_Header_Straight_1x02_Pitch2.54mm" H 4950 3600 50  0001 C CNN
+F 3 "" H 4950 3600 50  0001 C CNN
+	1    4950 3600
+	1    0    0    -1  
+$EndComp
+$Comp
+L eSim_CP1 C2
+U 1 1 6A893F37
+P 5250 3650
+F 0 "C2" H 5275 3750 50  0000 L CNN
+F 1 "eSim_CP1" H 5275 3550 50  0000 L CNN
+F 2 "Capacitors_THT:CP_Radial_D5.0mm_P2.00mm" H 5250 3650 50  0001 C CNN
+F 3 "" H 5250 3650 50  0001 C CNN
+	1    5250 3650
+	1    0    0    -1  
+$EndComp
+$Comp
+L eSim_C C1
+U 1 1 6A89400C
+P 5650 3650
+F 0 "C1" H 5675 3750 50  0000 L CNN
+F 1 "eSim_C" H 5675 3550 50  0000 L CNN
+F 2 "Capacitors_THT:C_Disc_D3.0mm_W2.0mm_P2.50mm" H 5688 3500 30  0001 C CNN
+F 3 "" H 5650 3650 60  0000 C CNN
+	1    5650 3650
+	1    0    0    -1  
+$EndComp
+$Comp
+L L7805 U1
+U 1 1 6A894156
+P 6200 3600
+F 0 "U1" H 6050 3725 50  0000 C CNN
+F 1 "L7805" H 6200 3725 50  0000 L CNN
+F 2 "TO_SOT_Packages_THT:TO-220_Vertical" H 6225 3450 50  0001 L CIN
+F 3 "" H 6200 3550 50  0001 C CNN
+	1    6200 3600
+	1    0    0    -1  
+$EndComp
+$Comp
+L eSim_C C3
+U 1 1 6A8941CB
+P 6600 3650
+F 0 "C3" H 6625 3750 50  0000 L CNN
+F 1 "eSim_C" H 6625 3550 50  0000 L CNN
+F 2 "Capacitors_THT:C_Disc_D3.0mm_W2.0mm_P2.50mm" H 6638 3500 30  0001 C CNN
+F 3 "" H 6600 3650 60  0000 C CNN
+	1    6600 3650
+	1    0    0    -1  
+$EndComp
+$Comp
+L eSim_R R1
+U 1 1 6A89426C
+P 7050 3700
+F 0 "R1" H 7100 3830 50  0000 C CNN
+F 1 "eSim_R" H 7100 3650 50  0000 C CNN
+F 2 "Resistors_THT:R_Axial_DIN0207_L6.3mm_D2.5mm_P7.62mm_Horizontal" H 7100 3680 30  0001 C CNN
+F 3 "" V 7100 3750 30  0000 C CNN
+	1    7050 3700
+	1    0    0    -1  
+$EndComp
+$Comp
+L eSim_LED D1
+U 1 1 6A8942FF
+P 7600 3650
+F 0 "D1" H 7600 3750 50  0000 C CNN
+F 1 "eSim_LED" H 7650 3550 31  0000 C CNN
+F 2 "LEDs:LED_D5.0mm" H 7600 3650 50  0001 C CNN
+F 3 "" H 7600 3650 50  0001 C CNN
+	1    7600 3650
+	1    0    0    -1  
+$EndComp
+$Comp
+L Conn_01x02 J2
+U 1 1 6A89452E
+P 8100 3600
+F 0 "J2" H 8100 3700 50  0000 C CNN
+F 1 "Conn_01x02" H 8100 3400 50  0000 C CNN
+F 2 "Pin_Headers:Pin_Header_Straight_1x02_Pitch2.54mm" H 8100 3600 50  0001 C CNN
+F 3 "" H 8100 3600 50  0001 C CNN
+	1    8100 3600
+	1    0    0    -1  
+$EndComp
+Wire Wire Line
+	4750 3500 5900 3500
+Wire Wire Line
+	6500 3600 6500 3500
+Wire Wire Line
+	6500 3500 7900 3500
+Connection ~ 6950 3500
+Connection ~ 7550 3500
+Wire Wire Line
+	4750 3850 5900 3850
+Wire Wire Line
+	5900 3500 5900 3600
+Wire Wire Line
+	5900 3850 5900 3900
+Wire Wire Line
+	5900 3900 7900 3900
+Connection ~ 6200 3900
+Wire Wire Line
+	5650 3800 5650 3850
+Connection ~ 5650 3850
+Wire Wire Line
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+Connection ~ 5250 3850
+Wire Wire Line
+	4750 3600 4750 3500
+Wire Wire Line
+	4750 3700 4750 3850
+Wire Wire Line
+	6600 3800 6600 3900
+Connection ~ 6600 3900
+Wire Wire Line
+	6950 3500 6950 3650
+Wire Wire Line
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+Wire Wire Line
+	7750 3650 7750 3900
+Connection ~ 7750 3900
+Wire Wire Line
+	7900 3500 7900 3600
+Connection ~ 7900 3500
+Wire Wire Line
+	7900 3900 7900 3700
+Connection ~ 7900 3900
+$EndSCHEMATC