Optimize channelize_poly CUDA kernels and dispatch - #1253
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Add fused FIR+DFT kernels that keep filtered samples on chip, avoiding the intermediate tensor and separate cuFFT launch: small-channel leaves for critically sampled M=2..6 (replacing FusedChan) and general leaves for M=8, 10, 16, 20, 32, 40, 64, and 80, plus oversampled M=3..6. Rework the FIR+cuFFT backends: tuning of tile sizes and launch configuration. Select backends through SelectPlan/ExecutePlan using device attributes (SM count, L2 size, FP64 throughput, memory bus width). Tests compare every launchable backend, including windowed launches, against the host implementation. channelize_poly_bench gains single-case options. Across a 4,832-shape sweep, the geometric-mean speedup over the previous implementation is 1.89x on L4 and 2.15x on GH200. Signed-off-by: Thomas Benson <tbenson@nvidia.com>
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cliffburdick
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Oct 1, 2026
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Add fused FIR+DFT kernels that keep filtered samples in shared memory or registers, avoiding the intermediate tensor and separate cuFFT launch. Add small-channel leaves for critically sampled M=2..6 (replacing the prior FusedChan kernel) and general leaves for M=8, 10, 16, 20, 32, 40, 64, and 80, plus oversampled M=3..6. The infrastructure is in-place to extend coverage of fusion, but this PR does not do so in order to limit template instantiations. Instead, the aim is for a future PR to add a compile-time property that allows users to opt-in specific channel counts for fusion.
Rework the FIR+cuFFT backends via tuning of tile sizes and launch configuration. Select backends through SelectPlan/ExecutePlan using device attributes (SM count, L2 size, FP64 throughput, memory bus width).
Tests compare every launchable backend, including windowed launches, against the host implementation.
Across a 4,832-shape sweep, the geometric-mean speedup over the previous implementation is 1.89x on L4 and 2.15x on GH200. Some regressions remain with these changes, but the vast majority of cases improve with some cases being more than twice as fast.