From 79cd4b816cd7cf2997b459227386af2e3b69c5b3 Mon Sep 17 00:00:00 2001 From: "jacky.cheng" Date: Tue, 22 Sep 2026 13:51:46 +0000 Subject: [PATCH 1/2] [AMD][Qwen3.5] Bump MI355X AgentX image to v0.5.20-rocm720-mi35x-20260922 --- configs/amd-master.yaml | 6 +++--- perf-changelog.yaml | 9 +++++++++ 2 files changed, 12 insertions(+), 3 deletions(-) diff --git a/configs/amd-master.yaml b/configs/amd-master.yaml index bae2efc100..afa82cbc08 100644 --- a/configs/amd-master.yaml +++ b/configs/amd-master.yaml @@ -314,7 +314,7 @@ qwen3.5-fp4-mi355x-sglang-mtp: - { tp: 4, conc-start: 4, conc-end: 16, spec-decoding: mtp } qwen3.5-fp4-mi355x-sglang-agentic-mtp: - image: lmsysorg/sglang-rocm:v0.5.19-rocm720-mi35x-20260915 + image: lmsysorg/sglang-rocm:v0.5.20-rocm720-mi35x-20260922 model: amd/Qwen3.5-397B-A17B-MXFP4-AttnFP8-V2 model-prefix: qwen3.5 runner: cluster:mi355x-amds @@ -326,8 +326,8 @@ qwen3.5-fp4-mi355x-sglang-agentic-mtp: - dram-utilization: 0.80 search-space: - { tp: 4, ep: 1, spec-decoding: mtp, kv-offloading: none, conc-list: [1, 4, 8, 12, 16] } - - { tp: 2, ep: 1, spec-decoding: mtp, kv-offloading: none, conc-list: [1, 4, 8, 12, 16, 20] } - - { tp: 2, ep: 1, spec-decoding: mtp, kv-offloading: dram, kv-offload-backend: { name: hicache }, conc-list: [20, 24, 28, 32, 36, 40] } + - { tp: 2, ep: 1, spec-decoding: mtp, kv-offloading: none, conc-list: [1, 4, 8, 12] } + - { tp: 2, ep: 1, spec-decoding: mtp, kv-offloading: dram, kv-offload-backend: { name: hicache }, conc-list: [16, 20, 24, 28, 32, 36, 40] } qwen3.5-fp4-mi355x-sglang-disagg: image: lmsysorg/sglang-rocm:v0.5.12.post1-rocm720-mi35x-20260523 diff --git a/perf-changelog.yaml b/perf-changelog.yaml index 86eb8dbb63..8d2119b375 100644 --- a/perf-changelog.yaml +++ b/perf-changelog.yaml @@ -8587,3 +8587,12 @@ - "将镜像从已失效的 nightly-eed1f3d0 重新固定到 vllm/vllm-openai-rocm:nightly-rocm100-3df4ae153eb385e27b52f26c81f8edb9e20b9984（与 MI355X 臂在 SemiAnalysisAI/InferenceX#3326 中所用相同 commit 的 ROCm 10.0 nightly 渠道构建）；该镜像包含 vllm-project/vllm#57491，将两处 is_cuda() 判定放宽为 is_cuda_alike()，使 engram_config 在 gfx942 上可解析；由于 cpu_offload 现通过 VLLM_PLE_CPU_OFFLOAD 默认开启，配方按 TP 显式设置该值" - "新增 --no-swa-bounded-replay：vllm-project/vllm#56227 在两个 pin 之间将 SWA bounded replay 默认开启，其依赖的 window clamp 在 ROCm sparse SWA 路径中缺失，曾使所有 gfx950 数据点以 HSA_STATUS_ERROR_MEMORY_FAULT 崩溃；gfx942 使用同一路径。prefix caching 保持开启" pr-link: https://github.com/SemiAnalysisAI/InferenceX/pull/3337 + +- config-keys: + - qwen3.5-fp4-mi355x-sglang-agentic-mtp + scenario-type: + - agentic-coding + description: + - "Bump the SGLang ROCm image from lmsysorg/sglang-rocm:v0.5.19-rocm720-mi35x-20260915 to lmsysorg/sglang-rocm:v0.5.20-rocm720-mi35x-20260922." + - "Move TP2 concurrency 16 from GPU-resident KV to HiCache and remove the TP2 GPU-resident concurrency-20 point. Keep TP4 GPU-resident [1, 4, 8, 12, 16]. The resulting TP2 grids are resident [1, 4, 8, 12] and HiCache [16, 20, 24, 28, 32, 36, 40]." + pr-link: https://github.com/SemiAnalysisAI/InferenceX/pull/3364 From a99150a6b022786b612c3d41f0e7c8b49ea263cc Mon Sep 17 00:00:00 2001 From: "jacky.cheng" Date: Thu, 24 Sep 2026 14:56:37 +0000 Subject: [PATCH 2/2] [AMD][Qwen3.5] Bump MI355X AgentX image to v0.5.20-rocm720-mi35x-20260924 --- .../single_node/agentic/qwen3.5_fp4_mi355x_sglang_mtp.sh | 4 +++- configs/amd-master.yaml | 2 +- perf-changelog.yaml | 3 ++- 3 files changed, 6 insertions(+), 3 deletions(-) diff --git a/benchmarks/single_node/agentic/qwen3.5_fp4_mi355x_sglang_mtp.sh b/benchmarks/single_node/agentic/qwen3.5_fp4_mi355x_sglang_mtp.sh index 88311f2b04..942020cfef 100644 --- a/benchmarks/single_node/agentic/qwen3.5_fp4_mi355x_sglang_mtp.sh +++ b/benchmarks/single_node/agentic/qwen3.5_fp4_mi355x_sglang_mtp.sh @@ -58,13 +58,15 @@ trap 'exit 143' TERM CACHE_ARGS=() if require_agentic_kv_offload_backend hicache; then HICACHE_RATIO="1.5" + HICACHE_SIZE="253" HICACHE_WRITE_POLICY="write_through" HICACHE_IO_BACKEND="kernel" HICACHE_MEM_LAYOUT="page_first" - echo "HiCache CPU tier: ratio=$HICACHE_RATIO, write_policy=$HICACHE_WRITE_POLICY, io_backend=$HICACHE_IO_BACKEND, mem_layout=$HICACHE_MEM_LAYOUT, dram_budget=${TOTAL_CPU_DRAM_GB} GB, tp=$TP" + echo "HiCache CPU tier: ratio=$HICACHE_RATIO, size=$HICACHE_SIZE GB, write_policy=$HICACHE_WRITE_POLICY, io_backend=$HICACHE_IO_BACKEND, mem_layout=$HICACHE_MEM_LAYOUT, dram_budget=${TOTAL_CPU_DRAM_GB} GB, tp=$TP" CACHE_ARGS=( --enable-hierarchical-cache --hicache-ratio "$HICACHE_RATIO" + --hicache-size "$HICACHE_SIZE" --hicache-write-policy "$HICACHE_WRITE_POLICY" --hicache-io-backend "$HICACHE_IO_BACKEND" --hicache-mem-layout "$HICACHE_MEM_LAYOUT" diff --git a/configs/amd-master.yaml b/configs/amd-master.yaml index afa82cbc08..a61f461bc2 100644 --- a/configs/amd-master.yaml +++ b/configs/amd-master.yaml @@ -314,7 +314,7 @@ qwen3.5-fp4-mi355x-sglang-mtp: - { tp: 4, conc-start: 4, conc-end: 16, spec-decoding: mtp } qwen3.5-fp4-mi355x-sglang-agentic-mtp: - image: lmsysorg/sglang-rocm:v0.5.20-rocm720-mi35x-20260922 + image: lmsysorg/sglang-rocm:v0.5.20-rocm720-mi35x-20260924 model: amd/Qwen3.5-397B-A17B-MXFP4-AttnFP8-V2 model-prefix: qwen3.5 runner: cluster:mi355x-amds diff --git a/perf-changelog.yaml b/perf-changelog.yaml index 8d2119b375..b7e0d5fd9b 100644 --- a/perf-changelog.yaml +++ b/perf-changelog.yaml @@ -8593,6 +8593,7 @@ scenario-type: - agentic-coding description: - - "Bump the SGLang ROCm image from lmsysorg/sglang-rocm:v0.5.19-rocm720-mi35x-20260915 to lmsysorg/sglang-rocm:v0.5.20-rocm720-mi35x-20260922." + - "Bump the SGLang ROCm image from lmsysorg/sglang-rocm:v0.5.19-rocm720-mi35x-20260915 to lmsysorg/sglang-rocm:v0.5.20-rocm720-mi35x-20260924." - "Move TP2 concurrency 16 from GPU-resident KV to HiCache and remove the TP2 GPU-resident concurrency-20 point. Keep TP4 GPU-resident [1, 4, 8, 12, 16]. The resulting TP2 grids are resident [1, 4, 8, 12] and HiCache [16, 20, 24, 28, 32, 36, 40]." + - "Pin the AgentX HiCache host pool with --hicache-size 253 (overrides --hicache-ratio)." pr-link: https://github.com/SemiAnalysisAI/InferenceX/pull/3364