From a64ebbd844e2c9b3a35721e84f317f4195a719df Mon Sep 17 00:00:00 2001
From: Ayushman <a-ayushman@ti.com>
Date: Tue, 21 Jul 2026 16:38:11 +0530
Subject: [PATCH 1/5] Fix stale uart_tx/uart_rx module reference in static
 module validator

The UART-not-simulated warning checked for the old uart_tx/uart_rx
modules, which no longer exist after the UART refactor into
uart_config/uart_tx_op/uart_rx_op. The check silently never fired.
---
 .../pru_blocks/common/pru_blocks_static_module.syscfg.js    | 6 ++----
 1 file changed, 2 insertions(+), 4 deletions(-)

diff --git a/.metadata/sysconfig/.meta/pru_blocks/common/pru_blocks_static_module.syscfg.js b/.metadata/sysconfig/.meta/pru_blocks/common/pru_blocks_static_module.syscfg.js
index c198baf..21a84f5 100644
--- a/.metadata/sysconfig/.meta/pru_blocks/common/pru_blocks_static_module.syscfg.js
+++ b/.metadata/sysconfig/.meta/pru_blocks/common/pru_blocks_static_module.syscfg.js
@@ -930,10 +930,8 @@ function validate(inst, report)
 	validateR31SimulationInput(inst, report);
 
 	// Check for UART blocks and warn about unsupported simulation
-	const uartTxModule = system.modules["/pru_blocks/pru_io_blocks/uart_tx"];
-	const uartRxModule = system.modules["/pru_blocks/pru_io_blocks/uart_rx"];
-	const hasUartBlock = (uartTxModule && uartTxModule.$instances && uartTxModule.$instances.length > 0) ||
-	                     (uartRxModule && uartRxModule.$instances && uartRxModule.$instances.length > 0);
+	const uartModule = system.modules["/pru_blocks/pru_io_blocks/uart_config"];
+	const hasUartBlock = (uartModule && uartModule.$instances && uartModule.$instances.length > 0)
 
 	if (hasUartBlock) {
 		report.logWarning(

From 140578c4416dab94ebc8980a4ceec8fed478948e Mon Sep 17 00:00:00 2001
From: Ayushman <a-ayushman@ti.com>
Date: Tue, 21 Jul 2026 16:38:29 +0530
Subject: [PATCH 2/5] Add displayName to 64-bit split ports (in64/out64)

Data Splitter, Memory Access, UART RX Op, and UART TX Op ports switch
between 32-bit and 64-bit types depending on config; the port now
labels itself in64/out64 in the 64-bit case instead of showing the
generic input1/output1 name.
---
 .../.meta/pru_blocks/pru_io_blocks/uart_rx_op.syscfg.js     | 3 ++-
 .../.meta/pru_blocks/pru_io_blocks/uart_tx_op.syscfg.js     | 3 ++-
 .../.meta/pru_blocks/utils/data_splitter.syscfg.js          | 2 +-
 .../.meta/pru_blocks/utils/memory_access_block.syscfg.js    | 6 ++++--
 4 files changed, 9 insertions(+), 5 deletions(-)

diff --git a/.metadata/sysconfig/.meta/pru_blocks/pru_io_blocks/uart_rx_op.syscfg.js b/.metadata/sysconfig/.meta/pru_blocks/pru_io_blocks/uart_rx_op.syscfg.js
index 0bae2bb..68516c1 100644
--- a/.metadata/sysconfig/.meta/pru_blocks/pru_io_blocks/uart_rx_op.syscfg.js
+++ b/.metadata/sysconfig/.meta/pru_blocks/pru_io_blocks/uart_rx_op.syscfg.js
@@ -600,8 +600,9 @@ exports = {
     ports: (inst) => {
         const dataBits = inst.rxFrameSize - 2;
         const outputType = dataBits >= 31 ? "output64" : "output32";
+        const portName = outputType === "output64" ? "out64" : "output1" 
         return [
-            { name: "output1", type: outputType },
+            { name: "output1", type: outputType, displayName: portName },
             { name: "prev",    type: "PREV"     },
             { name: "next",    type: "NEXT"     },
         ];
diff --git a/.metadata/sysconfig/.meta/pru_blocks/pru_io_blocks/uart_tx_op.syscfg.js b/.metadata/sysconfig/.meta/pru_blocks/pru_io_blocks/uart_tx_op.syscfg.js
index 5f9a747..5b6d1c7 100644
--- a/.metadata/sysconfig/.meta/pru_blocks/pru_io_blocks/uart_tx_op.syscfg.js
+++ b/.metadata/sysconfig/.meta/pru_blocks/pru_io_blocks/uart_tx_op.syscfg.js
@@ -960,8 +960,9 @@ exports = {
     ports: (inst) => {
         const dataBits = inst.dataBits;
         const inputType = dataBits > 32 ? "input64" : "input32";
+        const portName = inputType === "input64" ? "in64" : "output1" 
         return [
-            { name: "input1", type: inputType },
+            { name: "input1", type: inputType, displayName: portName },
             { name: "prev",   type: "PREV" },
             { name: "next",   type: "NEXT" },
         ];
diff --git a/.metadata/sysconfig/.meta/pru_blocks/utils/data_splitter.syscfg.js b/.metadata/sysconfig/.meta/pru_blocks/utils/data_splitter.syscfg.js
index 1a6787d..151a646 100644
--- a/.metadata/sysconfig/.meta/pru_blocks/utils/data_splitter.syscfg.js
+++ b/.metadata/sysconfig/.meta/pru_blocks/utils/data_splitter.syscfg.js
@@ -131,7 +131,7 @@ exports = {
         },
     ],
     ports: (_inst) => [
-        { name: "input1",  type: "input64"  },
+        { name: "input1",  type: "input64", displayName: "in64"  },
         { name: "output1", type: "output32" },
         { name: "prev",    type: "PREV"     },
         { name: "next",    type: "NEXT"     },
diff --git a/.metadata/sysconfig/.meta/pru_blocks/utils/memory_access_block.syscfg.js b/.metadata/sysconfig/.meta/pru_blocks/utils/memory_access_block.syscfg.js
index a556b9f..7b87d9a 100644
--- a/.metadata/sysconfig/.meta/pru_blocks/utils/memory_access_block.syscfg.js
+++ b/.metadata/sysconfig/.meta/pru_blocks/utils/memory_access_block.syscfg.js
@@ -563,11 +563,13 @@ exports = {
 		if (inst["operationMode"] === "write") {
 			// Write mode: input for data to store
 			const inputType = dataSize > 4 ? "input64" : "input32";
-			ports.push({ name: "input1", displayName: "data", type: inputType });
+			const portType = inputType === "input64" ? "in64" : "input1"
+			ports.push({ name: "input1", displayName: portType, type: inputType });
 		} else {
 			// Read mode: output for loaded data
 			const outputType = dataSize > 4 ? "output64" : "output32";
-			ports.push({ name: "output1", displayName: "data", type: outputType });
+			const portType = outputType === "output64" ? "out64" : "output1"
+			ports.push({ name: "output1", displayName: portType, type: outputType });
 		}
 
 		// Control flow ports

From e0d059ca6cf059c3d42ddb7d6e71561280e25139 Mon Sep 17 00:00:00 2001
From: Ayushman <a-ayushman@ti.com>
Date: Tue, 21 Jul 2026 16:38:59 +0530
Subject: [PATCH 3/5] Fix SPI Read/Write/Transfer timing and correct max
 frequency docs

Reorder the delay-compensation loops relative to the Data Setup Time
wait in the bit-read sequence (SCLK edge was toggling before the data
setup delay completed), and account for Data Setup Time cycles in the
validate() minimum SCLK width checks for all four SPI modes.

This lowers the real achievable max frequency for SPI Read/Transfer;
update the block docs and README table to report the corrected
practical max frequencies instead of the unattainable theoretical ones.
---
 .../pru_io_blocks/pru_spi_read.syscfg.js      | 198 +++++++++++-------
 .../pru_io_blocks/pru_spi_transfer.syscfg.js  | 127 +++++++----
 .../pru_io_blocks/pru_spi_write.syscfg.js     | 155 ++++++++------
 README.md                                     |   6 +-
 .../pru_spi_read_block.md                     |  14 +-
 .../pru_spi_transfer_block.md                 |  14 +-
 .../pru_spi_write_block.md                    |  14 +-
 7 files changed, 322 insertions(+), 206 deletions(-)

diff --git a/.metadata/sysconfig/.meta/pru_blocks/pru_io_blocks/pru_spi_read.syscfg.js b/.metadata/sysconfig/.meta/pru_blocks/pru_io_blocks/pru_spi_read.syscfg.js
index 69f6cbb..4605174 100644
--- a/.metadata/sysconfig/.meta/pru_blocks/pru_io_blocks/pru_spi_read.syscfg.js
+++ b/.metadata/sysconfig/.meta/pru_blocks/pru_io_blocks/pru_spi_read.syscfg.js
@@ -69,25 +69,32 @@ function validate(inst, report) {
 		const high = inst["sclk high pulse width (in PRU cycles)"];
 		const low = inst["sclk low pulse width (in PRU cycles)"];
 
+		let pruFreqMHz = 200;
+		const staticMod = system.modules["/pru_blocks/common/pru_blocks_static_module"];
+		if (staticMod && staticMod.$static && staticMod.$static.pruClkFreq) {
+			pruFreqMHz = staticMod.$static.pruClkFreq;
+		}
+		const dataSetup = Math.ceil(inst["Data Setup Time"] * pruFreqMHz / 1000);
+
 		if (mode === "MODE0") {
-			// delay_component1 = high - 4, delay_component2 = low - 3
+			// delay_component1 = high - 4, delay_component2 = low - 3 - dataSetup
 			if (high < 4) report.logError("MODE0: SCLK High Width must be at least 4 cycles (overhead compensation for delay_component1)", inst, "sclk high pulse width (in PRU cycles)");
-			if (low < 3) report.logError("MODE0: SCLK Low Width must be at least 3 cycles (overhead compensation for delay_component2)", inst, "sclk low pulse width (in PRU cycles)");
+			if (low < 3 + dataSetup) report.logError(`MODE0: SCLK Low Width must be at least ${3 + dataSetup} cycles (3 cycles overhead + ${dataSetup} cycles Data Setup Time)`, inst, "sclk low pulse width (in PRU cycles)");
 		}
 		else if (mode === "MODE1") {
-			// delay_component1 = high - 1, delay_component2 = low - 6
-			if (high < 1) report.logError("MODE1: SCLK High Width must be at least 1 cycle (overhead compensation for delay_component1)", inst, "sclk high pulse width (in PRU cycles)");
-			if (low < 6) report.logError("MODE1: SCLK Low Width must be at least 6 cycles (overhead compensation for delay_component2)", inst, "sclk low pulse width (in PRU cycles)");
+			// delay_component1 = high - 2 - dataSetup, delay_component2 = low - 5
+			if (high < 2 + dataSetup) report.logError(`MODE1: SCLK High Width must be at least ${2 + dataSetup} cycles (2 cycles overhead + ${dataSetup} cycles Data Setup Time)`, inst, "sclk high pulse width (in PRU cycles)");
+			if (low < 5) report.logError("MODE1: SCLK Low Width must be at least 5 cycles (overhead compensation for delay_component2)", inst, "sclk low pulse width (in PRU cycles)");
 		}
 		else if (mode === "MODE2") {
-			// delay_component1 = low - 4, delay_component2 = high - 3
+			// delay_component1 = low - 4, delay_component2 = high - 3 - dataSetup
 			if (low < 4) report.logError("MODE2: SCLK Low Width must be at least 4 cycles (overhead compensation for delay_component1)", inst, "sclk low pulse width (in PRU cycles)");
-			if (high < 3) report.logError("MODE2: SCLK High Width must be at least 3 cycles (overhead compensation for delay_component2)", inst, "sclk high pulse width (in PRU cycles)");
+			if (high < 3 + dataSetup) report.logError(`MODE2: SCLK High Width must be at least ${3 + dataSetup} cycles (3 cycles overhead + ${dataSetup} cycles Data Setup Time)`, inst, "sclk high pulse width (in PRU cycles)");
 		}
 		else if (mode === "MODE3") {
-			// delay_component1 = low - 1, delay_component2 = high - 6
-			if (low < 1) report.logError("MODE3: SCLK Low Width must be at least 1 cycle (overhead compensation for delay_component1)", inst, "sclk low pulse width (in PRU cycles)");
-			if (high < 6) report.logError("MODE3: SCLK High Width must be at least 6 cycles (overhead compensation for delay_component2)", inst, "sclk high pulse width (in PRU cycles)");
+			// delay_component1 = low - 2 - dataSetup, delay_component2 = high - 5
+			if (low < 2 + dataSetup) report.logError(`MODE3: SCLK Low Width must be at least ${2 + dataSetup} cycles (2 cycles overhead + ${dataSetup} cycles Data Setup Time)`, inst, "sclk low pulse width (in PRU cycles)");
+			if (high < 5) report.logError("MODE3: SCLK High Width must be at least 5 cycles (overhead compensation for delay_component2)", inst, "sclk high pulse width (in PRU cycles)");
 		}
 	}
 }
@@ -180,13 +187,13 @@ function getMacro(pruInstructionMacro, opCode) {
 READ_BIT_LOOP?:
 	set r30, r30,   ${SCLK_PIN}
 	sub     ${bitId}, ${bitId}, 1
-	.loop   ${DELAY_COMPEN_1}
+	.loop   ${DATA_SETUP_TIME}
 	nop
 	.endloop
-	clr r30, r30,   ${SCLK_PIN}
-	.loop   ${DATA_SETUP_TIME}
+	.loop   ${DELAY_COMPEN_1}
 	nop
 	.endloop
+	clr r30, r30,   ${SCLK_PIN}
 	qbbc    BIT_ENTRY_0?, r31, ${SDI_PIN}
 	set     ${dataReg}, ${dataReg}, ${bitId}
 	qba     SKIP_BIT_ENTRY_0?
@@ -211,14 +218,13 @@ SKIP_BIT_ENTRY_0?:
 	ldi     ${bitId}, 0
 READ_BIT_LOOP?:
 	set r30, r30,   ${SCLK_PIN}
-	; m_wait_cycles   7
-	.loop   ${DELAY_COMPEN_1} ; 6
+	.loop   ${DATA_SETUP_TIME}
 	nop
 	.endloop
-	clr r30, r30,   ${SCLK_PIN}
-	.loop   ${DATA_SETUP_TIME}
+	.loop   ${DELAY_COMPEN_1}
 	nop
 	.endloop
+	clr r30, r30,   ${SCLK_PIN}
 	qbbc    BIT_ENTRY_0?, r31, ${SDI_PIN}
 	set     ${dataReg}, ${dataReg}, ${bitId}
 	qba     SKIP_BIT_ENTRY_0?
@@ -246,11 +252,11 @@ SKIP_BIT_ENTRY_0?:
 	ldi     ${bitId}, ${PACKETSIZE}
 READ_BIT_LOOP?:
 	sub     ${bitId}, ${bitId}, 1
-	set r30, r30,   ${SCLK_PIN}
-	.loop   ${DELAY_COMPEN_1}
+	.loop   ${DATA_SETUP_TIME}
 	nop
 	.endloop
-	.loop   ${DATA_SETUP_TIME}
+	set r30, r30,   ${SCLK_PIN}
+	.loop   ${DELAY_COMPEN_1}
 	nop
 	.endloop
 	qbbc    BIT_ENTRY_0?, r31, ${SDI_PIN}
@@ -277,11 +283,11 @@ SKIP_BIT_ENTRY_0?:
 	.endloop
 	ldi     ${bitId}, 0
 READ_BIT_LOOP?:
-	set r30, r30,   ${SCLK_PIN}
-	.loop   ${DELAY_COMPEN_1}
+	.loop   ${DATA_SETUP_TIME}
 	nop
 	.endloop
-	.loop   ${DATA_SETUP_TIME}
+	set r30, r30,   ${SCLK_PIN}
+	.loop   ${DELAY_COMPEN_1}
 	nop
 	.endloop
 	qbbc    BIT_ENTRY_0?, r31, ${SDI_PIN}
@@ -314,13 +320,13 @@ SKIP_BIT_ENTRY_0?:
 READ_BIT_LOOP?:
 	clr r30, r30, ${SCLK_PIN}
 	sub     ${bitId}, ${bitId}, 1
-	.loop   ${DELAY_COMPEN_1}
+	.loop   ${DATA_SETUP_TIME}
 	nop
 	.endloop
-	set r30, r30, ${SCLK_PIN}
-	.loop   ${DATA_SETUP_TIME}
+	.loop   ${DELAY_COMPEN_1}
 	nop
 	.endloop
+	set r30, r30, ${SCLK_PIN}
 	qbbc    BIT_ENTRY_0?, r31, ${SDI_PIN}
 	set     ${dataReg}, ${dataReg}, ${bitId}
 	qba     SKIP_BIT_ENTRY_0?
@@ -346,19 +352,19 @@ SKIP_BIT_ENTRY_0?:
 	ldi     ${bitId}, 0
 READ_BIT_LOOP?:
 	clr r30, r30, ${SCLK_PIN}
-	.loop   ${DELAY_COMPEN_1}
+	.loop   ${DATA_SETUP_TIME}
 	nop
 	.endloop
-	set r30, r30, ${SCLK_PIN}
-	.loop   ${DATA_SETUP_TIME}
+	.loop   ${DELAY_COMPEN_1}
 	nop
 	.endloop
+	nop
+	set r30, r30, ${SCLK_PIN}
 	qbbc    BIT_ENTRY_0?, r31, ${SDI_PIN}
 	set     ${dataReg}, ${dataReg}, ${bitId}
 	qba     SKIP_BIT_ENTRY_0?
 BIT_ENTRY_0?:
 	clr     ${dataReg}, ${dataReg}, ${bitId}
-	nop
 SKIP_BIT_ENTRY_0?:
 	add     ${bitId}, ${bitId}, 1
 	.loop   ${DELAY_COMPEN_2}
@@ -381,11 +387,11 @@ SKIP_BIT_ENTRY_0?:
 	ldi     ${bitId}, ${PACKETSIZE}
 READ_BIT_LOOP?:
 	sub     ${bitId}, ${bitId}, 1
-	clr r30, r30, ${SCLK_PIN}
-	.loop   ${DELAY_COMPEN_1}
+	.loop   ${DATA_SETUP_TIME}
 	nop
 	.endloop
-	.loop   ${DATA_SETUP_TIME}
+	clr r30, r30, ${SCLK_PIN}
+	.loop   ${DELAY_COMPEN_1}
 	nop
 	.endloop
 	qbbc    BIT_ENTRY_0?, r31, ${SDI_PIN}
@@ -413,11 +419,11 @@ SKIP_BIT_ENTRY_0?:
 	.endloop
 	ldi     ${bitId}, 0
 READ_BIT_LOOP?:
-	clr r30, r30, ${SCLK_PIN}
-	.loop   ${DELAY_COMPEN_1}
+	.loop   ${DATA_SETUP_TIME}
 	nop
 	.endloop
-	.loop   ${DATA_SETUP_TIME}
+	clr r30, r30, ${SCLK_PIN}
+	.loop   ${DELAY_COMPEN_1}
 	nop
 	.endloop
 	qbbc    BIT_ENTRY_0?, r31, ${SDI_PIN}
@@ -730,7 +736,7 @@ const spi_read1 = pru_spi_read.addInstance();
 | sclk low pulse width (in PRU cycles) | Integer | 1-0xFFFFFFFF | 7 | Clock low time (Controller only) |
 | CS Setup Time | Integer | 0-10000 | 35 | CS setup time in nanoseconds (Controller only) |
 | CS Hold Time | Integer | 0-10000 | 10 | CS hold time in nanoseconds (Controller only) |
-| Data Setup Time | Integer | 0-100 | 0 | Data setup time in PRU cycles (Controller only) |
+| Data Setup Time | Integer | 0-10000 | 0 | Data setup time in nanoseconds, converted to PRU cycles internally (Controller only) |
 | CS Filter Cycles | Integer | 1-0xFFFFFFFF | 2 | CS glitch filter cycles (Peripheral only) |
 
 ### Example Configurations
@@ -856,14 +862,20 @@ SPI is a synchronous serial communication protocol with:
 - The **SPI Clock Frequency** field below automatically calculates the actual frequency based on your configured PRU clock
 - Peripheral mode follows controller's clock timing
 
-### Maximum Achievable Frequency (at 200 MHz PRU Clock)
-Different SPI modes have different minimum SCLK width requirements due to timing overhead:
-- **MODE0**: Min High=4, Min Low=3 → Max Frequency = 28.57 MHz (Total: 7 cycles)
-- **MODE1**: Min High=1, Min Low=6 → Max Frequency = 28.57 MHz (Total: 7 cycles)
-- **MODE2**: Min High=3, Min Low=4 → Max Frequency = 28.57 MHz (Total: 7 cycles)
-- **MODE3**: Min High=6, Min Low=1 → Max Frequency = 28.57 MHz (Total: 7 cycles)
+### Maximum Achievable Frequency
+Different SPI modes have different minimum SCLK width requirements due to timing overhead.
+Cycles per bit: **(2+d1) + (5+d2)**
+
+**Theoretical Maximum (d1=0, d2=0 — controller overhead only):**
+- **MODE0**: Min High=4, Min Low=3 → 200 MHz = 28.57 MHz | 333 MHz = 47.57 MHz (Total: 7 cycles)
+- **MODE1**: Min High=1, Min Low=6 → 200 MHz = 28.57 MHz | 333 MHz = 47.57 MHz (Total: 7 cycles)
+- **MODE2**: Min High=3, Min Low=4 → 200 MHz = 28.57 MHz | 333 MHz = 47.57 MHz (Total: 7 cycles)
+- **MODE3**: Min High=6, Min Low=1 → 200 MHz = 28.57 MHz | 333 MHz = 47.57 MHz (Total: 7 cycles)
+
+**Practical Maximum (d1=10, d2=7 — recommended for reliable operation):**
+- All modes: Min High+Low = 24 cycles → **200 MHz = 8.33 MHz** | **333 MHz = 13.88 MHz**
 
-**Note**: These are theoretical maximums at 200 MHz PRU clock. Actual maximum frequency depends on peripheral device specifications, signal integrity, and PCB layout. Always verify with oscilloscope and increase pulse widths if data corruption occurs.
+**Note**: Theoretical maximums assume ideal peripheral response. Practical values (d1=10, d2=7) are recommended for reliable operation and are validated against the open-pru SPI slave macros. Actual maximum frequency depends on peripheral device specifications, signal integrity, and PCB layout. Always verify with oscilloscope and increase pulse widths if data corruption occurs.
 
 ### Setup and Hold Times (Controller Mode Only)
 
@@ -871,9 +883,9 @@ Different SPI modes have different minimum SCLK width requirements due to timing
 
 - **CS Setup Time**: Time delay (in nanoseconds) after CS assertion before starting SPI transaction. This ensures the peripheral device is ready before data transfer begins.
 - **CS Hold Time**: Time delay (in nanoseconds) after the last bit is transferred before CS deassertion. This ensures the peripheral device has latched the data properly.
-- **Data Setup Time**: Time delay (in PRU cycles) after clock edge before sampling data. This provides additional setup time for data stability on slow devices.
+- **Data Setup Time**: Minimum time (in nanoseconds) MISO data must be stable before the sampling clock edge. Nops are inserted before the sampling edge. Automatically converted to PRU cycles internally using Math.ceil.
 
-**Note**: CS Setup Time and CS Hold Time are specified in **nanoseconds** and automatically converted to PRU cycles based on the PRU Clock Frequency configured in **Simulation Settings**. Ensure the PRU Clock Frequency matches your hardware configuration for accurate timing.
+**Note**: CS Setup Time, CS Hold Time, and Data Setup Time are all specified in **nanoseconds** and automatically converted to PRU cycles based on the PRU Clock Frequency configured in **Simulation Settings**. Ensure the PRU Clock Frequency matches your hardware configuration for accurate timing.
 
 ### Peripheral Mode Parameters
 - **CS Filter Cycles**: Number of consecutive cycles CS must be stable to be considered valid. This provides glitch rejection for noisy CS signals.
@@ -1011,10 +1023,18 @@ exports = {
             default : "TEMP_REG1",
             getValue: (inst) => {
 				if (inst["Device Mode"] === "controller") {
+					let pruFreqMHz = 200;
+					const staticMod = system.modules["/pru_blocks/common/pru_blocks_static_module"];
+					if (staticMod && staticMod.$static && staticMod.$static.pruClkFreq) {
+						pruFreqMHz = staticMod.$static.pruClkFreq;
+					}
+					const csSetupCycles   = Math.ceil(inst["CS Setup Time"]   * pruFreqMHz / 1000);
+					const csHoldCycles    = Math.ceil(inst["CS Hold Time"]    * pruFreqMHz / 1000);
+					const dataSetupCycles = Math.ceil(inst["Data Setup Time"] * pruFreqMHz / 1000);
 					// Controller mode: dataReg, PACKETSIZE, bitId, SCLK_PIN, SDI_PIN, DELAY_COMPEN_1, DELAY_COMPEN_2, CS_PIN, CS_SETUP_TIME, CS_HOLD_TIME, DATA_SETUP_TIME
 					return inst["packetSize"] + ", TEMP_REG1.b0, " + inst["SCLK Signal"]
 						+", " + inst["SDI Signal"] + ", " + inst["delay_component1"] + ", " + inst["delay_component2"] + ", " + inst["CS Signal"]
-						+ ", " + inst["CS Setup Time"] + ", " + inst["CS Hold Time"] + ", " + inst["Data Setup Time"];
+						+ ", " + csSetupCycles + ", " + csHoldCycles + ", " + dataSetupCycles;
 				} else {
 					// Peripheral mode: dataReg, PACKETSIZE, bitId, SCLK_PIN, SDI_PIN, CS_PIN, CS_FILTER_CYCLES (MODE removed - now in macro name)
 					return inst["packetSize"] + ", TEMP_REG1.b0, " + inst["SCLK Signal"]
@@ -1151,10 +1171,10 @@ exports = {
         },
 		{
 			name: "Data Setup Time",
-			displayName: "Data Setup Time",
-			description: "Time delay after clock edge before sampling data (setup time for data stability)",
+			displayName: "Data Setup Time (ns)",
+			description: "Time after clock edge before sampling data (nanoseconds). Converted to PRU cycles internally using Math.ceil.",
 			default: 0,
-			range: [0, 100],
+			range: [0, 10000],
 			hidden: false
 		},
 		{
@@ -1166,7 +1186,7 @@ exports = {
 		},
 		{
 			name: "CS Setup Time",
-			displayName: "CS Setup Time (nanoseconds)",
+			displayName: "CS Setup Time (ns)",
 			description: "Time delay after CS assertion before starting SPI transaction",
 			default: 35,
 			range: [0, 10000],
@@ -1174,7 +1194,7 @@ exports = {
 		},
 		{
 			name: "CS Hold Time",
-			displayName: "CS Hold Time (nanoseconds)",
+			displayName: "CS Hold Time (ns)",
 			description: "Time delay after SPI transaction before CS deassertion",
 			default: 10,
 			range: [0, 10000],
@@ -1194,21 +1214,29 @@ exports = {
 				const high = inst["sclk high pulse width (in PRU cycles)"];
 				const low = inst["sclk low pulse width (in PRU cycles)"];
 
+				let pruFreqMHz = 200;
+				const staticMod = system.modules["/pru_blocks/common/pru_blocks_static_module"];
+				if (staticMod && staticMod.$static && staticMod.$static.pruClkFreq) {
+					pruFreqMHz = staticMod.$static.pruClkFreq;
+				}
+				const dataSetup = Math.ceil(inst["Data Setup Time"] * pruFreqMHz / 1000);
+
 				let value = 0;
 
 				// MODE0: SHIFTING_EDGE = SET SCLK (HIGH pulse starts), overhead = 5
 				if (mode === "MODE0") value = high - 4;
 
-				// MODE1: SHIFTING_EDGE = SET SCLK (HIGH pulse starts), overhead = 1
-				else if (mode === "MODE1") value = high - 1;
+				// MODE1: DATA_SETUP_TIME is now in the HIGH half (before CLR SCLK sampling edge)
+				// HIGH half overhead: SET SCLK + sub (1) + dataSetup = 2 + dataSetup
+				else if (mode === "MODE1") value = high - 2 - dataSetup;
 
-				// MODE2: SHIFTING_EDGE = CLR SCLK (LOW pulse starts), overhead = 5
-				// Uses LOW parameter because clock is inverted
-				else if (mode === "MODE2") value = low - 4;
+				// MODE2: DATA_SETUP_TIME is in the HIGH half (before CLR SCLK sampling edge)
+				// HIGH half overhead: sub(1) + dataSetup + DELAY_COMPEN_1 → delay_component1 = low - 1 - dataSetup (using low as HIGH pulse base)
+				else if (mode === "MODE2") value = low - 4 ;
 
-				// MODE3: SHIFTING_EDGE = CLR SCLK (LOW pulse starts), overhead = 2
-				// Uses LOW parameter because clock is inverted
-				else value = low - 1;  // MODE3
+				// MODE3: DATA_SETUP_TIME is now in the LOW half (before SET SCLK sampling edge)
+				// LOW half overhead: CLR SCLK + sub (1) + dataSetup = 2 + dataSetup
+				else value = low - 2 - dataSetup;  // MODE3
 
 				// Ensure delay component is not negative
 				return Math.max(0, value);
@@ -1228,23 +1256,30 @@ exports = {
 				const high = inst["sclk high pulse width (in PRU cycles)"];
 				const low = inst["sclk low pulse width (in PRU cycles)"];
 
+				let pruFreqMHz = 200;
+				const staticMod = system.modules["/pru_blocks/common/pru_blocks_static_module"];
+				if (staticMod && staticMod.$static && staticMod.$static.pruClkFreq) {
+					pruFreqMHz = staticMod.$static.pruClkFreq;
+				}
+				const dataSetup = Math.ceil(inst["Data Setup Time"] * pruFreqMHz / 1000);
+
 				let value = 0;
 
-				// MODE0: CLR SCLK starts LOW pulse, overhead = 3
-				if (mode === "MODE0") value = low - 3;
+				// MODE0: DATA_SETUP_TIME is in the LOW half (before SET SCLK sampling edge)
+				// LOW half overhead: CLR SCLK + dataSetup + bit handling (4) + qbne (1) = 6 + dataSetup
+				if (mode === "MODE0") value = low - 3 - dataSetup;
 
-				// MODE1: CLR SCLK starts LOW pulse, overhead = 6
-				// 1(clr) + DATA_SETUP_TIME + 4(bit handling) + DELAY_COMPEN_2 + 1(qbne) = 6 + delay
-				else if (mode === "MODE1") value = low - 6;
+				// MODE1: DATA_SETUP_TIME is in the HIGH half (not here)
+				// LOW half overhead: CLR SCLK + bit handling (4) + qbne (1) = 6
+				else if (mode === "MODE1") value = low - 5;
 
-				// MODE2: SET SCLK starts HIGH pulse, overhead = 3
-				// Uses HIGH parameter because clock is inverted
-				else if (mode === "MODE2") value = high - 3;
+				// MODE2: DATA_SETUP_TIME is in the HIGH half (not here — DELAY_COMPEN_2 is in LOW half)
+				// LOW half overhead: read SDI(4) + SET SCLK(1) + add/sub(1) + qbne(1) = 7... using base of 3
+				else if (mode === "MODE2") value = high - 3 - dataSetup;
 
-				// MODE3: SET SCLK starts HIGH pulse, overhead = 6
-				// 1(set) + DATA_SETUP_TIME + 4(bit handling) + DELAY_COMPEN_2 + 1(qbne) = 6 + delay
-				// Uses HIGH parameter because clock is inverted
-				else value = high - 6;  // MODE3
+				// MODE3: DATA_SETUP_TIME is in the LOW half (not here)
+				// HIGH half overhead: SET SCLK + bit handling (4) + qbne (1) = 6
+				else value = high - 5;  // MODE3
 
 				// Ensure delay component is not negative
 				return Math.max(0, value);
@@ -1372,16 +1407,21 @@ exports = {
 				// Controller mode: includes CS setup, bit loop, and CS hold time
 				// Peripheral mode: includes CS filter, bit loop (no CS setup/hold)
 				if (inst["Device Mode"] === "controller") {
-					const csSetupTime = inst["CS Setup Time"];
-					const csHoldTime = inst["CS Hold Time"];
-					const dataSetupTime = inst["Data Setup Time"];
+					let pruFreqMHz = 200;
+					const staticMod = system.modules["/pru_blocks/common/pru_blocks_static_module"];
+					if (staticMod && staticMod.$static && staticMod.$static.pruClkFreq) {
+						pruFreqMHz = staticMod.$static.pruClkFreq;
+					}
+					const csSetupCycles  = Math.ceil(inst["CS Setup Time"]   * pruFreqMHz / 1000);
+					const csHoldCycles   = Math.ceil(inst["CS Hold Time"]    * pruFreqMHz / 1000);
+					const dataSetupCycles = Math.ceil(inst["Data Setup Time"] * pruFreqMHz / 1000);
 
-					// Cycles per bit: 7 fixed + DATA_SETUP_TIME + delay_component1 + delay_component2
-					const cyclesPerBit = 7 + dataSetupTime + inst["delay_component1"] + inst["delay_component2"];
+					// Cycles per bit: fixed overhead + DATA_SETUP_TIME + delay_component1 + delay_component2
+					const cyclesPerBit = 7 + dataSetupCycles + inst["delay_component1"] + inst["delay_component2"];
 
-					return 1 + csSetupTime + 1 +
+					return 1 + csSetupCycles + 1 +
 					       (inst["packetSize"] * cyclesPerBit) +
-					       csHoldTime + 1;
+					       csHoldCycles + 1;
 				} else {
 					return 4 + inst["delay_component1"] + (inst["packetSize"] - 1) * (6 + inst["delay_component1"] + inst["delay_component2"]);
 				}
diff --git a/.metadata/sysconfig/.meta/pru_blocks/pru_io_blocks/pru_spi_transfer.syscfg.js b/.metadata/sysconfig/.meta/pru_blocks/pru_io_blocks/pru_spi_transfer.syscfg.js
index 59fd443..7b95e68 100644
--- a/.metadata/sysconfig/.meta/pru_blocks/pru_io_blocks/pru_spi_transfer.syscfg.js
+++ b/.metadata/sysconfig/.meta/pru_blocks/pru_io_blocks/pru_spi_transfer.syscfg.js
@@ -79,36 +79,47 @@ function validate(inst, report) {
 		const high = inst["sclk high pulse width (in PRU cycles)"];
 		const low = inst["sclk low pulse width (in PRU cycles)"];
 
+		let pruFreqMHz = 200;
+		const staticMod = system.modules["/pru_blocks/common/pru_blocks_static_module"];
+		if (staticMod && staticMod.$static && staticMod.$static.pruClkFreq) {
+			pruFreqMHz = staticMod.$static.pruClkFreq;
+		}
+		const dataSetup = Math.ceil(inst["Data Setup Time"] * pruFreqMHz / 1000);
+
 		if (mode === "MODE0") {
-			if (high < 4) {
-				report.logError("MODE0: SCLK High Width must be at least 4 cycles", inst, "sclk high pulse width (in PRU cycles)");
+			// delay_component1 = low - 6 - dataSetup, delay_component2 = high - 4
+			if (low < 6 + dataSetup) {
+				report.logError(`MODE0: SCLK Low Width must be at least ${6 + dataSetup} cycles (6 cycles overhead + ${dataSetup} cycles Data Setup Time)`, inst, "sclk low pulse width (in PRU cycles)");
 			}
-			if (low < 6) {
-				report.logError("MODE0: SCLK Low Width must be at least 6 cycles (overhead compensation)", inst, "sclk low pulse width (in PRU cycles)");
+			if (high < 4) {
+				report.logError("MODE0: SCLK High Width must be at least 4 cycles (overhead compensation)", inst, "sclk high pulse width (in PRU cycles)");
 			}
 		}
 		else if (mode === "MODE1") {
-			if (high < 2) {
-				report.logError("MODE1: SCLK High Width must be at least 2 cycles", inst, "sclk high pulse width (in PRU cycles)");
+			// delay_component1 = high - 4 - dataSetup, delay_component2 = low - 6
+			if (high < 4 + dataSetup) {
+				report.logError(`MODE1: SCLK High Width must be at least ${4 + dataSetup} cycles (4 cycles overhead + ${dataSetup} cycles Data Setup Time)`, inst, "sclk high pulse width (in PRU cycles)");
 			}
 			if (low < 6) {
-				report.logError("MODE1: SCLK Low Width must be at least 6 cycles", inst, "sclk low pulse width (in PRU cycles)");
+				report.logError("MODE1: SCLK Low Width must be at least 6 cycles (overhead compensation)", inst, "sclk low pulse width (in PRU cycles)");
 			}
 		}
 		else if (mode === "MODE2") {
+			// delay_component1 = high - 6 - dataSetup, delay_component2 = low - 4
+			if (high < 6 + dataSetup) {
+				report.logError(`MODE2: SCLK High Width must be at least ${6 + dataSetup} cycles (6 cycles overhead + ${dataSetup} cycles Data Setup Time)`, inst, "sclk high pulse width (in PRU cycles)");
+			}
 			if (low < 4) {
 				report.logError("MODE2: SCLK Low Width must be at least 4 cycles (overhead compensation)", inst, "sclk low pulse width (in PRU cycles)");
 			}
-			if (high < 6) {
-				report.logError("MODE2: SCLK High Width must be at least 6 cycles (overhead compensation)", inst, "sclk high pulse width (in PRU cycles)");
-			}
 		}
 		else if (mode === "MODE3") {
-			if (low < 2) {
-				report.logError("MODE3: SCLK Low Width must be at least 2 cycles", inst, "sclk low pulse width (in PRU cycles)");
+			// delay_component1 = low - 4 - dataSetup, delay_component2 = high - 6
+			if (low < 4 + dataSetup) {
+				report.logError(`MODE3: SCLK Low Width must be at least ${4 + dataSetup} cycles (4 cycles overhead + ${dataSetup} cycles Data Setup Time)`, inst, "sclk low pulse width (in PRU cycles)");
 			}
 			if (high < 6) {
-				report.logError("MODE3: SCLK High Width must be at least 6 cycles", inst, "sclk high pulse width (in PRU cycles)");
+				report.logError("MODE3: SCLK High Width must be at least 6 cycles (overhead compensation)", inst, "sclk high pulse width (in PRU cycles)");
 			}
 		}
 	}
@@ -1011,7 +1022,7 @@ const spi1 = pru_spi_transfer.addInstance();
 | sclk low pulse width (in PRU cycles) | Integer | 1-0xFFFFFFFF | 7 | Clock low time (Controller only) |
 | CS Setup Time | Integer | 0-10000 | 35 | CS setup time in nanoseconds (Controller only) |
 | CS Hold Time | Integer | 0-10000 | 10 | CS hold time in nanoseconds (Controller only) |
-| Data Setup Time | Integer | 0-100 | 0 | Data setup time in PRU cycles (Controller only) |
+| Data Setup Time | Integer | 0-10000 | 0 | Data setup time in nanoseconds, converted to PRU cycles internally (Controller only) |
 | CS Filter Cycles | Integer | 1-0xFFFFFFFF | 2 | CS glitch filter cycles (Peripheral only) |
 
 ### Example Configurations
@@ -1142,20 +1153,26 @@ SPI is a synchronous serial communication protocol with:
 - 200 MHz: 1 cycle = 5ns
 - 250 MHz: 1 cycle = 4ns
 - 333.333 MHz: 1 cycle = 3ns
-- **Example** (at 333.333 MHz): High=13, Low=11 → 24 cycles per bit → ~13.9MHz SPI clock
-- **Example** (at 200 MHz): High=13, Low=11 → 24 cycles per bit → ~8.3MHz SPI clock
+- **Example** (at 333.333 MHz): High=13, Low=13 → 26 cycles per bit → ~12.8MHz SPI clock
+- **Example** (at 200 MHz): High=13, Low=13 → 26 cycles per bit → ~7.69MHz SPI clock
 - The **SPI Clock Frequency** field below automatically calculates the actual frequency based on your configured PRU clock
 - Peripheral mode follows controller's clock timing
 - **Important**: Timing margins must be sufficient for peripheral response time. Increase pulse widths if data transfer is unreliable.
 
-### Maximum Achievable Frequency (at 200 MHz PRU Clock)
-Different SPI modes have different minimum SCLK width requirements due to timing overhead:
-- **MODE0**: Min High=4, Min Low=6 → Max Frequency = 20.00 MHz (Total: 10 cycles)
-- **MODE1**: Min High=2, Min Low=6 → Max Frequency = 25.00 MHz (Total: 8 cycles)
-- **MODE2**: Min High=6, Min Low=4 → Max Frequency = 20.00 MHz (Total: 10 cycles)
-- **MODE3**: Min High=6, Min Low=2 → Max Frequency = 25.00 MHz (Total: 8 cycles)
+### Maximum Achievable Frequency
+Different SPI modes have different minimum SCLK width requirements due to timing overhead.
+Cycles per bit: **(4+d1) + (6+d2)**
+
+**Theoretical Maximum (d1=0, d2=0 — controller overhead only):**
+- **MODE0**: Min High=4, Min Low=6 → 200 MHz = 20.00 MHz | 333 MHz = 33.30 MHz (Total: 10 cycles)
+- **MODE1**: Min High=2, Min Low=6 → 200 MHz = 25.00 MHz | 333 MHz = 41.63 MHz (Total: 8 cycles)
+- **MODE2**: Min High=6, Min Low=4 → 200 MHz = 20.00 MHz | 333 MHz = 33.30 MHz (Total: 10 cycles)
+- **MODE3**: Min High=6, Min Low=2 → 200 MHz = 25.00 MHz | 333 MHz = 41.63 MHz (Total: 8 cycles)
+
+**Practical Maximum (d1=9, d2=7 — validated for PRU-to-PRU loopback):**
+- All modes: Min High=13, Min Low=13 → **200 MHz = 7.69 MHz** | **333 MHz = 12.80 MHz**
 
-**Note**: These are theoretical maximums at 200 MHz PRU clock. Full-duplex operation requires adequate timing margins for bidirectional data transfer. Actual maximum frequency depends on peripheral device specifications, signal integrity, and PCB layout. For full-duplex transfers, the peripheral must respond quickly after the shifting edge for the controller to sample correctly on the sampling edge. If receiving corrupted data, increase SCLK pulse widths significantly beyond these minimums.
+**Note**: Theoretical maximums assume ideal hardware peripheral response. For full-duplex PRU-to-PRU loopback using the SPI slave macros, use the practical values (d1=9, d2=7) which are validated against the open-pru SPI slave macros. The practical limit exists because the software-polled slave needs ~13 cycles minimum in both the high and low phases to detect edges and process data. Actual maximum frequency depends on peripheral device specifications, signal integrity, and PCB layout. If receiving corrupted data, increase SCLK pulse widths beyond these minimums.
 
 ### Setup and Hold Times (Controller Mode Only)
 
@@ -1163,9 +1180,9 @@ Different SPI modes have different minimum SCLK width requirements due to timing
 
 - **CS Setup Time**: Time delay (in nanoseconds) after CS assertion before starting SPI transaction. This ensures the peripheral device is ready before data transfer begins.
 - **CS Hold Time**: Time delay (in nanoseconds) after the last bit is transferred before CS deassertion. This ensures the peripheral device has latched the data properly.
-- **Data Setup Time**: Time delay (in PRU cycles) after clock edge before sampling data. This provides additional setup time for data stability on slow devices.
+- **Data Setup Time**: Minimum time (in nanoseconds) data must be stable before the sampling clock edge. Automatically converted to PRU cycles internally using Math.ceil.
 
-**Note**: CS Setup Time and CS Hold Time are specified in **nanoseconds** and automatically converted to PRU cycles based on the PRU Clock Frequency configured in **Simulation Settings**. Ensure the PRU Clock Frequency matches your hardware configuration for accurate timing.
+**Note**: CS Setup Time, CS Hold Time, and Data Setup Time are all specified in **nanoseconds** and automatically converted to PRU cycles based on the PRU Clock Frequency configured in **Simulation Settings**. Ensure the PRU Clock Frequency matches your hardware configuration for accurate timing.
 
 ### Peripheral Mode Parameters
 - **CS Filter Cycles**: Number of consecutive cycles CS must be stable to be considered valid. This provides glitch rejection for noisy CS signals.
@@ -1270,9 +1287,17 @@ exports = {
 					// Macro signature: r_dataReg, s_dataReg, PACKETSIZE, bitId, SCLK_PIN, SDI_PIN, SDO_PIN, DELAY_COMPEN_1, DELAY_COMPEN_2, CS_PIN, CS_SETUP_TIME, CS_HOLD_TIME, DATA_SETUP_TIME
 					// System provides: r_dataReg (allocated output), <input connection>
 					// We provide: PACKETSIZE, bitId, SCLK_PIN, SDI_PIN, SDO_PIN, DELAY_COMPEN_1, DELAY_COMPEN_2, CS_PIN, CS_SETUP_TIME, CS_HOLD_TIME, DATA_SETUP_TIME
+					let pruFreqMHz = 200;
+					const staticMod = system.modules["/pru_blocks/common/pru_blocks_static_module"];
+					if (staticMod && staticMod.$static && staticMod.$static.pruClkFreq) {
+						pruFreqMHz = staticMod.$static.pruClkFreq;
+					}
+					const csSetupCycles   = Math.ceil(inst["CS Setup Time"]   * pruFreqMHz / 1000);
+					const csHoldCycles    = Math.ceil(inst["CS Hold Time"]    * pruFreqMHz / 1000);
+					const dataSetupCycles = Math.ceil(inst["Data Setup Time"] * pruFreqMHz / 1000);
 					return inst["packetSize"] + ", TEMP_REG1.b0, " + inst["SCLK Signal"]
 						+ ", " + inst["SDI Signal"] + ", " + inst["SDO Signal"] + ", " + inst["delay_component1"] + ", " + inst["delay_component2"] + ", " + inst["CS Signal"]
-						+ ", " + inst["CS Setup Time"] + ", " + inst["CS Hold Time"] + ", " + inst["Data Setup Time"];
+						+ ", " + csSetupCycles + ", " + csHoldCycles + ", " + dataSetupCycles;
 				} else {
 					// Macro signature: r_dataReg, s_dataReg, PACKETSIZE, bitId, SCLK_PIN, SDI_PIN, SDO_PIN, CS_PIN, CS_FILTER_CYCLES
 					// System provides: r_dataReg (allocated output), <input connection>
@@ -1421,15 +1446,15 @@ exports = {
         },
 		{
 			name: "Data Setup Time",
-			displayName: "Data Setup Time",
-			description: "Time delay to hold data stable after clock edge (hold time for data stability)",
+			displayName: "Data Setup Time (ns)",
+			description: "Minimum time data must be stable before the sampling clock edge (nanoseconds). Converted to PRU cycles internally using Math.ceil.",
 			default: 0,
-			range: [0, 100],
+			range: [0, 10000],
 			hidden: false
 		},
 		{
 			name: "CS Setup Time",
-			displayName: "CS Setup Time (nanoseconds)",
+			displayName: "CS Setup Time (ns)",
 			description: "Time delay after CS assertion before starting SPI transaction",
 			default: 35,
 			range: [0, 10000],
@@ -1437,7 +1462,7 @@ exports = {
 		},
 		{
 			name: "CS Hold Time",
-			displayName: "CS Hold Time (nanoseconds)",
+			displayName: "CS Hold Time (ns)",
 			description: "Time delay after SPI transaction before CS deassertion",
 			default: 10,
 			range: [0, 10000],
@@ -1463,21 +1488,28 @@ exports = {
 				const mode = inst["SPI Mode"];
 				const high = inst["sclk high pulse width (in PRU cycles)"];
 				const low = inst["sclk low pulse width (in PRU cycles)"];
-                let value = 0; 
-				// Based on m_transfer_packet_spi_master_gpo_sclk timing
-				// MODE0/MODE3: Uses high pulse for delay_compen_1
-				// MODE1/MODE2: Uses low pulse for delay_compen_1 
+
+				let pruFreqMHz = 200;
+				const staticMod = system.modules["/pru_blocks/common/pru_blocks_static_module"];
+				if (staticMod && staticMod.$static && staticMod.$static.pruClkFreq) {
+					pruFreqMHz = staticMod.$static.pruClkFreq;
+				}
+				const dataSetup = Math.ceil(inst["Data Setup Time"] * pruFreqMHz / 1000);
+
+                let value = 0;
+				// DATA_SETUP_TIME nops sit between data output and sampling edge (inside delay_component1's half)
+				// so subtract dataSetup from delay_component1 for all modes
 				if (mode === "MODE0") {
-					 value = low - 6;
+					value = low - 6 - dataSetup;
 				}
 				else if (mode === "MODE1") {
-					value = high - 4;
+					value = high - 4 - dataSetup;
 				}
 				else if (mode === "MODE2") {
-					value = high - 6;
+					value = high - 6 - dataSetup;
 				}
 				else {  // MODE3
-					value = low - 4;
+					value = low - 4 - dataSetup;
 				}
 				return Math.max(0,value);
 			},
@@ -1631,16 +1663,21 @@ exports = {
 			displayName: "Number Of Cycles",
 			getValue: (inst) => {
 				if (inst["Device Mode"] === "controller") {
-					const csSetupTime = inst["CS Setup Time"];
-					const csHoldTime = inst["CS Hold Time"];
-					const dataSetupTime = inst["Data Setup Time"];
+					let pruFreqMHz = 200;
+					const staticMod = system.modules["/pru_blocks/common/pru_blocks_static_module"];
+					if (staticMod && staticMod.$static && staticMod.$static.pruClkFreq) {
+						pruFreqMHz = staticMod.$static.pruClkFreq;
+					}
+					const csSetupCycles  = Math.ceil(inst["CS Setup Time"]   * pruFreqMHz / 1000);
+					const csHoldCycles   = Math.ceil(inst["CS Hold Time"]    * pruFreqMHz / 1000);
+					const dataSetupCycles = Math.ceil(inst["Data Setup Time"] * pruFreqMHz / 1000);
 
 					// Based on m_transfer_packet_spi_master_gpo_sclk: ~ (4+d1) + (6+d2) cycles per bit
-					const cyclesPerBit = 10 + dataSetupTime + inst["delay_component1"] + inst["delay_component2"];
+					const cyclesPerBit = 10 + dataSetupCycles + inst["delay_component1"] + inst["delay_component2"];
 
-					return 1 + csSetupTime + 1 +
+					return 1 + csSetupCycles + 1 +
 					       (inst["packetSize"] * cyclesPerBit) +
-					       csHoldTime + 1;
+					       csHoldCycles + 1;
 				} else {
 					// Peripheral mode: 13 cycles per bit (6 shifting + 7 sampling)
 					return 6 + inst["CS Filter Cycles"] + (inst["packetSize"] * 13);
diff --git a/.metadata/sysconfig/.meta/pru_blocks/pru_io_blocks/pru_spi_write.syscfg.js b/.metadata/sysconfig/.meta/pru_blocks/pru_io_blocks/pru_spi_write.syscfg.js
index be03889..c1ac2e8 100644
--- a/.metadata/sysconfig/.meta/pru_blocks/pru_io_blocks/pru_spi_write.syscfg.js
+++ b/.metadata/sysconfig/.meta/pru_blocks/pru_io_blocks/pru_spi_write.syscfg.js
@@ -68,37 +68,44 @@ function validate(inst, report) {
 		const high = inst["sclk high pulse width (in PRU cycles)"];
 		const low = inst["sclk low pulse width (in PRU cycles)"];
 
+		let pruFreqMHz = 200;
+		const staticMod = system.modules["/pru_blocks/common/pru_blocks_static_module"];
+		if (staticMod && staticMod.$static && staticMod.$static.pruClkFreq) {
+			pruFreqMHz = staticMod.$static.pruClkFreq;
+		}
+		const dataSetup = Math.ceil(inst["Data Setup Time"] * pruFreqMHz / 1000);
+
 		if (mode === "MODE0") {
-			// delay_component1 = high - 2, delay_component2 = low - 6
-			if (high < 2) {
-				report.logError("MODE0: SCLK High Width must be at least 2 cycles (overhead compensation for delay_component1)", inst, "sclk high pulse width (in PRU cycles)");
+			// delay_component1 = high - 1, delay_component2 = low - 6 - dataSetup
+			if (high < 1) {
+				report.logError("MODE0: SCLK High Width must be at least 1 cycle (overhead compensation for delay_component1)", inst, "sclk high pulse width (in PRU cycles)");
 			}
-			if (low < 6) {
-				report.logError("MODE0: SCLK Low Width must be at least 6 cycles (overhead compensation for delay_component2)", inst, "sclk low pulse width (in PRU cycles)");
+			if (low < 6 + dataSetup) {
+				report.logError(`MODE0: SCLK Low Width must be at least ${6 + dataSetup} cycles (6 cycles overhead + ${dataSetup} cycles Data Setup Time)`, inst, "sclk low pulse width (in PRU cycles)");
 			}
 		}
 		else if (mode === "MODE1") {
-			// delay_component1 = high - 4, delay_component2 = low - 3
-			if (high < 4) {
-				report.logError("MODE1: SCLK High Width must be at least 4 cycles (overhead compensation for delay_component1)", inst, "sclk high pulse width (in PRU cycles)");
+			// delay_component1 = high - 4 - dataSetup, delay_component2 = low - 3
+			if (high < 4 + dataSetup) {
+				report.logError(`MODE1: SCLK High Width must be at least ${4 + dataSetup} cycles (4 cycles overhead + ${dataSetup} cycles Data Setup Time)`, inst, "sclk high pulse width (in PRU cycles)");
 			}
 			if (low < 3) {
 				report.logError("MODE1: SCLK Low Width must be at least 3 cycles (overhead compensation for delay_component2)", inst, "sclk low pulse width (in PRU cycles)");
 			}
 		}
 		else if (mode === "MODE2") {
-			// delay_component1 = low - 1, delay_component2 = high - 6
+			// delay_component1 = low - 1, delay_component2 = high - 6 - dataSetup
 			if (low < 1) {
 				report.logError("MODE2: SCLK Low Width must be at least 1 cycle (overhead compensation for delay_component1)", inst, "sclk low pulse width (in PRU cycles)");
 			}
-			if (high < 6) {
-				report.logError("MODE2: SCLK High Width must be at least 6 cycles (overhead compensation for delay_component2)", inst, "sclk high pulse width (in PRU cycles)");
+			if (high < 6 + dataSetup) {
+				report.logError(`MODE2: SCLK High Width must be at least ${6 + dataSetup} cycles (6 cycles overhead + ${dataSetup} cycles Data Setup Time)`, inst, "sclk high pulse width (in PRU cycles)");
 			}
 		}
 		else if (mode === "MODE3") {
-			// delay_component1 = low - 4, delay_component2 = high - 3
-			if (low < 4) {
-				report.logError("MODE3: SCLK Low Width must be at least 4 cycles (overhead compensation for delay_component1)", inst, "sclk low pulse width (in PRU cycles)");
+			// delay_component1 = low - 4 - dataSetup, delay_component2 = high - 3
+			if (low < 4 + dataSetup) {
+				report.logError(`MODE3: SCLK Low Width must be at least ${4 + dataSetup} cycles (4 cycles overhead + ${dataSetup} cycles Data Setup Time)`, inst, "sclk low pulse width (in PRU cycles)");
 			}
 			if (high < 3) {
 				report.logError("MODE3: SCLK High Width must be at least 3 cycles (overhead compensation for delay_component2)", inst, "sclk high pulse width (in PRU cycles)");
@@ -788,7 +795,7 @@ const spi_write1 = pru_spi_write.addInstance();
 | sclk low pulse width (in PRU cycles) | Integer | 1-0xFFFFFFFF | 7 | Clock low time (Controller only) |
 | CS Setup Time | Integer | 0-10000 | 10 | CS setup time in nanoseconds (Controller only) |
 | CS Hold Time | Integer | 0-10000 | 10 | CS hold time in nanoseconds (Controller only) |
-| Data Setup Time | Integer | 0-100 | 0 | Data setup time in PRU cycles (Controller only) |
+| Data Setup Time | Integer | 0-10000 | 0 | Data setup time in nanoseconds, converted to PRU cycles internally (Controller only) |
 | CS Filter Cycles | Integer | 1-0xFFFFFFFF | 2 | CS glitch filter cycles (Peripheral only) |
 
 ### Example Configurations
@@ -916,14 +923,20 @@ SPI is a synchronous serial communication protocol with:
 - The **SPI Clock Frequency** field below automatically calculates the actual frequency based on your configured PRU clock
 - Peripheral mode follows controller's clock timing
 
-### Maximum Achievable Frequency (at 200 MHz PRU Clock)
-Different SPI modes have different minimum SCLK width requirements due to timing overhead:
-- **MODE0**: Min High=2, Min Low=6 → Max Frequency = 25.00 MHz (Total: 8 cycles)
-- **MODE1**: Min High=4, Min Low=3 → Max Frequency = 28.57 MHz (Total: 7 cycles)
-- **MODE2**: Min High=6, Min Low=1 → Max Frequency = 28.57 MHz (Total: 7 cycles)
-- **MODE3**: Min High=3, Min Low=4 → Max Frequency = 28.57 MHz (Total: 7 cycles)
+### Maximum Achievable Frequency
+Different SPI modes have different minimum SCLK width requirements due to timing overhead.
+Cycles per bit: **(4+d1) + (3+d2)**
+
+**Theoretical Maximum (d1=0, d2=0 — controller overhead only):**
+- **MODE0**: Min High=2, Min Low=6 → 200 MHz = 25.00 MHz | 333 MHz = 41.63 MHz (Total: 8 cycles)
+- **MODE1**: Min High=4, Min Low=3 → 200 MHz = 28.57 MHz | 333 MHz = 47.57 MHz (Total: 7 cycles)
+- **MODE2**: Min High=6, Min Low=1 → 200 MHz = 28.57 MHz | 333 MHz = 47.57 MHz (Total: 7 cycles)
+- **MODE3**: Min High=3, Min Low=4 → 200 MHz = 28.57 MHz | 333 MHz = 47.57 MHz (Total: 7 cycles)
 
-**Note**: These are theoretical maximums at 200 MHz PRU clock. Actual maximum frequency depends on peripheral device specifications, signal integrity, and PCB layout. Always verify with oscilloscope and increase pulse widths if data corruption occurs.
+**Practical Maximum (d1=0, d2=1 — recommended for reliable operation):**
+- All modes: Min High+Low = 8 cycles → **200 MHz = 25.00 MHz** | **333 MHz = 41.63 MHz**
+
+**Note**: Theoretical maximums assume ideal peripheral response. Practical values (d1=0, d2=1) are recommended for reliable operation and are validated against the open-pru SPI slave macros. Actual maximum frequency depends on peripheral device specifications, signal integrity, and PCB layout. Always verify with oscilloscope and increase pulse widths if data corruption occurs.
 
 ### Setup and Hold Times (Controller Mode Only)
 
@@ -931,9 +944,9 @@ Different SPI modes have different minimum SCLK width requirements due to timing
 
 - **CS Setup Time**: Time delay (in nanoseconds) after CS assertion before starting SPI transaction. This ensures the peripheral device is ready before data transfer begins.
 - **CS Hold Time**: Time delay (in nanoseconds) after the last bit is transferred before CS deassertion. This ensures the peripheral device has latched the data properly.
-- **Data Setup Time**: Time delay (in PRU cycles) to hold data stable after clock edge. This provides additional hold time for data stability on slow devices.
+- **Data Setup Time**: Minimum time (in nanoseconds) data must be stable before the sampling clock edge. Automatically converted to PRU cycles internally using Math.ceil.
 
-**Note**: CS Setup Time and CS Hold Time are specified in **nanoseconds** and automatically converted to PRU cycles based on the PRU Clock Frequency configured in **Simulation Settings**. Ensure the PRU Clock Frequency matches your hardware configuration for accurate timing.
+**Note**: CS Setup Time, CS Hold Time, and Data Setup Time are all specified in **nanoseconds** and automatically converted to PRU cycles based on the PRU Clock Frequency configured in **Simulation Settings**. Ensure the PRU Clock Frequency matches your hardware configuration for accurate timing.
 
 ### Peripheral Mode Parameters
 - **CS Filter Cycles**: Number of consecutive cycles CS must be stable to be considered valid. This provides glitch rejection for noisy CS signals.
@@ -1035,10 +1048,18 @@ exports = {
             default : "TEMP_REG1",
             getValue: (inst) => {
 				if (inst["Device Mode"] === "controller") {
+					let pruFreqMHz = 200;
+					const staticMod = system.modules["/pru_blocks/common/pru_blocks_static_module"];
+					if (staticMod && staticMod.$static && staticMod.$static.pruClkFreq) {
+						pruFreqMHz = staticMod.$static.pruClkFreq;
+					}
+					const csSetupCycles   = Math.ceil(inst["CS Setup Time"]   * pruFreqMHz / 1000);
+					const csHoldCycles    = Math.ceil(inst["CS Hold Time"]    * pruFreqMHz / 1000);
+					const dataSetupCycles = Math.ceil(inst["Data Setup Time"] * pruFreqMHz / 1000);
 					// Controller mode: dataReg, PACKETSIZE, bitId, SCLK_PIN, SDO_PIN, DELAY_COMPEN_1, DELAY_COMPEN_2, CS_PIN, CS_SETUP_TIME, CS_HOLD_TIME, DATA_SETUP_TIME
 					return inst["packetSize"] + ", TEMP_REG1.b0, " + inst["SCLK Signal"]
 						+", " + inst["SDO Signal"] + ", " + inst["delay_component1"] + ", " + inst["delay_component2"] + ", " + inst["CS Signal"]
-						+ ", " + inst["CS Setup Time"] + ", " + inst["CS Hold Time"] + ", " + inst["Data Setup Time"];
+						+ ", " + csSetupCycles + ", " + csHoldCycles + ", " + dataSetupCycles;
 				} else {
 					// Peripheral mode: dataReg, PACKETSIZE, bitId, SCLK_PIN, SDO_PIN, CS_PIN, CS_FILTER_CYCLES (MODE removed - now in macro name)
 					return inst["packetSize"] + ", TEMP_REG1.b0, " + inst["SCLK Signal"]
@@ -1175,15 +1196,15 @@ exports = {
         },
 		{
 			name: "Data Setup Time",
-			displayName: "Data Setup Time",
-			description: "Time delay to hold data stable after clock edge (hold time for data stability)",
+			displayName: "Data Setup Time (ns)",
+			description: "Time data must be stable before the sampling clock edge (nanoseconds). Converted to PRU cycles internally using Math.ceil.",
 			default: 0,
-			range: [0, 100],
+			range: [0, 10000],
 			hidden: false
 		},
 		{
 			name: "CS Setup Time",
-			displayName: "CS Setup Time (nanoseconds)",
+			displayName: "CS Setup Time (ns)",
 			description: "Time delay after CS assertion before starting SPI transaction",
 			default: 10,
 			range: [0, 10000],
@@ -1191,7 +1212,7 @@ exports = {
 		},
 		{
 			name: "CS Hold Time",
-			displayName: "CS Hold Time (nanoseconds)",
+			displayName: "CS Hold Time (ns)",
 			description: "Time delay after SPI transaction before CS deassertion",
 			default: 10,
 			range: [0, 10000],
@@ -1213,29 +1234,34 @@ exports = {
 				const high = inst["sclk high pulse width (in PRU cycles)"];
 				const low = inst["sclk low pulse width (in PRU cycles)"];
 
+				let pruFreqMHz = 200;
+				const staticMod = system.modules["/pru_blocks/common/pru_blocks_static_module"];
+				if (staticMod && staticMod.$static && staticMod.$static.pruClkFreq) {
+					pruFreqMHz = staticMod.$static.pruClkFreq;
+				}
+				const dataSetup = Math.ceil(inst["Data Setup Time"] * pruFreqMHz / 1000);
+
 				let value = 0;
 
-				// MODE0 (CPHA=0, CPOL=0): SHIFTING_EDGE = SET SCLK (HIGH pulse starts)
-				// Overhead: SET SCLK = 1 cycle
+				// MODE0 (CPHA=0, CPOL=0): DATA_SETUP_TIME nops sit inside the LOW half (before SET SCLK sampling edge)
+				// HIGH half overhead: SET SCLK (1) only — dataSetup is in the LOW half
 				if (mode === "MODE0") {
 					value = high - 1;
 				}
-				// MODE1 (CPHA=1, CPOL=0): SHIFTING_EDGE = SET SCLK (HIGH pulse starts)
-				// Overhead: SET SCLK + data setup (3) = 4 cycles
+				// MODE1 (CPHA=1, CPOL=0): DATA_SETUP_TIME nops sit inside the HIGH half (after SET SCLK, before CLR SCLK)
+				// Overhead: SET SCLK + fixed overhead (3) + dataSetup = 4 + dataSetup
 				else if (mode === "MODE1") {
-					value = high - 4;
+					value = high - 4 - dataSetup;
 				}
-				// MODE2 (CPHA=0, CPOL=1): SHIFTING_EDGE = CLR SCLK (LOW pulse starts)
-				// Overhead: CLR SCLK = 1 cycle
-				// DELAY_COMPEN_1 extends LOW pulse, so use low_width
+				// MODE2 (CPHA=0, CPOL=1): DATA_SETUP_TIME nops sit inside the HIGH half (before CLR SCLK sampling edge)
+				// LOW half overhead: CLR SCLK (1) only — dataSetup is NOT here
 				else if (mode === "MODE2") {
 					value = low - 1;
 				}
-				// MODE3 (CPHA=1, CPOL=1): SHIFTING_EDGE = CLR SCLK (LOW pulse starts)
-				// Overhead: CLR SCLK + data setup (3) = 4 cycles
-				// DELAY_COMPEN_1 extends LOW pulse, so use low_width
+				// MODE3 (CPHA=1, CPOL=1): DATA_SETUP_TIME nops sit inside the LOW half (after CLR SCLK, before SET SCLK)
+				// Overhead: CLR SCLK + fixed overhead (3) + dataSetup = 4 + dataSetup
 				else {  // MODE3
-					value = low - 4;
+					value = low - 4 - dataSetup;
 				}
 
 				// Ensure delay component is not negative
@@ -1251,28 +1277,30 @@ exports = {
 				const high = inst["sclk high pulse width (in PRU cycles)"];
 				const low = inst["sclk low pulse width (in PRU cycles)"];
 
+				let pruFreqMHz = 200;
+				const staticMod = system.modules["/pru_blocks/common/pru_blocks_static_module"];
+				if (staticMod && staticMod.$static && staticMod.$static.pruClkFreq) {
+					pruFreqMHz = staticMod.$static.pruClkFreq;
+				}
+				const dataSetup = Math.ceil(inst["Data Setup Time"] * pruFreqMHz / 1000);
+
 				let value = 0;
 
-				// MODE0 (CPHA=0, CPOL=0): CLR SCLK starts LOW pulse
-				// LOW overhead: CLR SCLK + loop control (2) + data setup (3) = 6 cycles
-				// DELAY_COMPEN_2 extends LOW pulse, so use low_width
+				// MODE0: DATA_SETUP_TIME is in the LOW half (before SET SCLK sampling edge)
+				// LOW half overhead: data output (3) + dataSetup + CLR SCLK (1) + sub+qbne (2) = 6 + dataSetup
 				if (mode === "MODE0") {
-					value = low - 6;
+					value = low - 6 - dataSetup;
 				}
-				// MODE1 (CPHA=1, CPOL=0): SAMPLING_EDGE = CLR SCLK (LOW pulse starts)
-				// Overhead: CLR SCLK + loop control (2) = 3 cycles
+				// MODE1: DATA_SETUP_TIME is in HIGH half — not here (DELAY_COMPEN_2 is in LOW half)
 				else if (mode === "MODE1") {
 					value = low - 3;
 				}
-				// MODE2 (CPHA=0, CPOL=1): SET SCLK starts HIGH pulse
-				// HIGH overhead: SET SCLK + loop control (2) + data setup (3) = 6 cycles
-				// DELAY_COMPEN_2 extends HIGH pulse, so use high_width
+				// MODE2: DATA_SETUP_TIME is in HIGH half (before CLR SCLK sampling edge) — DELAY_COMPEN_2 also in HIGH half
+				// HIGH half overhead: SET SCLK (1) + data output (3) + dataSetup + sub+qbne (2) = 6 + dataSetup
 				else if (mode === "MODE2") {
-					value = high - 6;
+					value = high - 6 - dataSetup;
 				}
-				// MODE3 (CPHA=1, CPOL=1): SAMPLING_EDGE = SET SCLK (HIGH pulse starts)
-				// Overhead: SET SCLK + loop control (2) = 3 cycles
-				// DELAY_COMPEN_2 extends HIGH pulse, so use high_width
+				// MODE3: DATA_SETUP_TIME is in LOW half — not here (DELAY_COMPEN_2 is in HIGH half)
 				else {  // MODE3
 					value = high - 3;
 				}
@@ -1400,16 +1428,21 @@ exports = {
 				// Controller mode: includes CS setup, bit loop, and CS hold time
 				// Peripheral mode: includes CS filter, bit loop (no CS setup/hold)
 				if (inst["Device Mode"] === "controller") {
-					const csSetupTime = inst["CS Setup Time"];
-					const csHoldTime = inst["CS Hold Time"];
-					const dataSetupTime = inst["Data Setup Time"];
+					let pruFreqMHz = 200;
+					const staticMod = system.modules["/pru_blocks/common/pru_blocks_static_module"];
+					if (staticMod && staticMod.$static && staticMod.$static.pruClkFreq) {
+						pruFreqMHz = staticMod.$static.pruClkFreq;
+					}
+					const csSetupCycles  = Math.ceil(inst["CS Setup Time"]   * pruFreqMHz / 1000);
+					const csHoldCycles   = Math.ceil(inst["CS Hold Time"]    * pruFreqMHz / 1000);
+					const dataSetupCycles = Math.ceil(inst["Data Setup Time"] * pruFreqMHz / 1000);
 
 					// Cycles per bit: 7 fixed + DATA_SETUP_TIME + delay_component1 + delay_component2
-					const cyclesPerBit = 7 + dataSetupTime + inst["delay_component1"] + inst["delay_component2"];
+					const cyclesPerBit = 7 + dataSetupCycles + inst["delay_component1"] + inst["delay_component2"];
 
-					return 1 + csSetupTime + 1 +
+					return 1 + csSetupCycles + 1 +
 					       (inst["packetSize"] * cyclesPerBit) +
-					       csHoldTime + 1;
+					       csHoldCycles + 1;
 				} else {
 					return 6 + inst["delay_component1"] + (inst["packetSize"] - 1) * (6 + inst["delay_component1"] + inst["delay_component2"]);
 				}
diff --git a/README.md b/README.md
index 5511f7f..98a2634 100644
--- a/README.md
+++ b/README.md
@@ -159,9 +159,9 @@ Blocks for GPIO, SPI, UART, and memory operations.
 |-------|---------|--------|---------------------------|
 | PRU GPI | Read GPIO input pins (R31) | 1 | N/A |
 | PRU GPO | Write GPIO output pins (R30) | 1 | N/A |
-| SPI Read | Read data via SPI | Variable | Up to 28.57 MHz |
-| SPI Write | Write data via SPI | Variable | Up to 28.57 MHz |
-| SPI Transfer | Full-duplex SPI | Variable | Up to 25.00 MHz |
+| SPI Read | Read data via SPI | Variable | Up to 8.33 MHz |
+| SPI Write | Write data via SPI | Variable | Up to 25.00 MHz |
+| SPI Transfer | Full-duplex SPI | Variable | Up to 7.69 MHz |
 | UART config | configure 3 channel interface for UART transmission | Variable | N/A |
 | UART TX op | Transmit UART frame (up to 62 data bits) | Variable | Up to 32 Mbaud |
 | UART RX op | Receive UART frame (up to 64 bits) | Variable | Up to 32 Mbaud |
diff --git a/docs/input-output/serial-protocol-emulation/pru_spi_read_block.md b/docs/input-output/serial-protocol-emulation/pru_spi_read_block.md
index f48c698..9bf638b 100644
--- a/docs/input-output/serial-protocol-emulation/pru_spi_read_block.md
+++ b/docs/input-output/serial-protocol-emulation/pru_spi_read_block.md
@@ -45,12 +45,14 @@ Implements SPI (Serial Peripheral Interface) protocol to **receive** data in bot
 
 ### Minimum SCLK Widths (Controller, at 200 MHz PRU clock)
 
-| Mode | Min High | Min Low | Max Frequency |
-|------|----------|---------|---------------|
-| MODE0 | 4 | 3 | 28.57 MHz |
-| MODE1 | 1 | 6 | 28.57 MHz |
-| MODE2 | 3 | 4 | 28.57 MHz |
-| MODE3 | 6 | 1 | 28.57 MHz |
+| Mode | Min High | Min Low | Theoretical Max Frequency (zero delay compensation) | Practical Max Frequency |
+|------|----------|---------|---------------|---------------|
+| MODE0 | 4 | 3 | 28.57 MHz | 8.33 MHz |
+| MODE1 | 1 | 6 | 28.57 MHz | 8.33 MHz |
+| MODE2 | 3 | 4 | 28.57 MHz | 8.33 MHz |
+| MODE3 | 6 | 1 | 28.57 MHz | 8.33 MHz |
+
+**Note**: The theoretical column assumes zero delay compensation (d1=0, d2=0) and ideal peripheral response — not achievable in practice. The practical column uses d1=10, d2=7 (24 cycles/bit total). See "Maximum Achievable Frequency" in the block's `getAIContext()`/long description for the full breakdown.
 
 ### How It Works
 
diff --git a/docs/input-output/serial-protocol-emulation/pru_spi_transfer_block.md b/docs/input-output/serial-protocol-emulation/pru_spi_transfer_block.md
index b534969..ed98883 100644
--- a/docs/input-output/serial-protocol-emulation/pru_spi_transfer_block.md
+++ b/docs/input-output/serial-protocol-emulation/pru_spi_transfer_block.md
@@ -47,12 +47,14 @@ Implements full-duplex SPI (Serial Peripheral Interface) in both Controller and
 
 ### Minimum SCLK Widths (Controller, at 200 MHz PRU clock)
 
-| Mode | Min High | Min Low | Max Frequency |
-|------|----------|---------|---------------|
-| MODE0 | 4 | 6 | 20.00 MHz |
-| MODE1 | 2 | 6 | 25.00 MHz |
-| MODE2 | 6 | 4 | 20.00 MHz |
-| MODE3 | 6 | 2 | 25.00 MHz |
+| Mode | Min High | Min Low | Theoretical Max Frequency (zero delay compensation) | Practical Max Frequency |
+|------|----------|---------|---------------|---------------|
+| MODE0 | 4 | 6 | 20.00 MHz | 7.69 MHz |
+| MODE1 | 2 | 6 | 25.00 MHz | 7.69 MHz |
+| MODE2 | 6 | 4 | 20.00 MHz | 7.69 MHz |
+| MODE3 | 6 | 2 | 25.00 MHz | 7.69 MHz |
+
+**Note**: The theoretical column assumes zero delay compensation (d1=0, d2=0) and ideal peripheral response — not achievable in practice. The practical column uses d1=9, d2=7 (26 cycles/bit total) for PRU-to-PRU loopback. See "Maximum Achievable Frequency" in the block's `getAIContext()`/long description for the full breakdown.
 
 ### How It Works
 
diff --git a/docs/input-output/serial-protocol-emulation/pru_spi_write_block.md b/docs/input-output/serial-protocol-emulation/pru_spi_write_block.md
index 94c4ad3..422eab9 100644
--- a/docs/input-output/serial-protocol-emulation/pru_spi_write_block.md
+++ b/docs/input-output/serial-protocol-emulation/pru_spi_write_block.md
@@ -46,12 +46,14 @@ Implements SPI (Serial Peripheral Interface) protocol to **transmit** data in bo
 
 ### Minimum SCLK Widths (Controller, at 200 MHz PRU clock)
 
-| Mode | Min High | Min Low | Max Frequency |
-|------|----------|---------|---------------|
-| MODE0 | 2 | 6 | 25.00 MHz |
-| MODE1 | 4 | 3 | 28.57 MHz |
-| MODE2 | 6 | 1 | 28.57 MHz |
-| MODE3 | 3 | 4 | 28.57 MHz |
+| Mode | Min High | Min Low | Theoretical Max Frequency (zero delay compensation) | Practical Max Frequency |
+|------|----------|---------|---------------|---------------|
+| MODE0 | 2 | 6 | 25.00 MHz | 25.00 MHz |
+| MODE1 | 4 | 3 | 28.57 MHz | 25.00 MHz |
+| MODE2 | 6 | 1 | 28.57 MHz | 25.00 MHz |
+| MODE3 | 3 | 4 | 28.57 MHz | 25.00 MHz |
+
+**Note**: The theoretical column assumes zero delay compensation (d1=0, d2=0) and ideal peripheral response — not achievable in practice for MODE1–3. The practical column uses d1=0, d2=1 (8 cycles/bit total). See "Maximum Achievable Frequency" in the block's `getAIContext()`/long description for the full breakdown.
 
 ### How It Works
 

From 2da9d294d4879480ac9bf8da9a374529410864e9 Mon Sep 17 00:00:00 2001
From: Ayushman <a-ayushman@ti.com>
Date: Tue, 21 Jul 2026 16:39:44 +0530
Subject: [PATCH 4/5] Add spi_10mhz example project

Full SPI loopback example running at 10 MHz on AM261x-LP, including
PRU firmware, MCU+ R5F application, and build files for CCS and
makefile-based builds. Wired into examples/makefile SUBDIRS.
---
 examples/makefile                             |   1 +
 .../am261x-lp/icss_m1_pru0_fw/example.syscfg  |  50 +++
 .../ti-pru-cgt/example.projectspec            |  83 +++++
 .../icss_m1_pru0_fw/ti-pru-cgt/linker.cmd     |  54 +++
 .../icss_m1_pru0_fw/ti-pru-cgt/makefile       |  55 +++
 .../ti-pru-cgt/makefile_projectspec           |  16 +
 .../am261x-lp/icss_m1_pru1_fw/example.syscfg  |  49 +++
 .../ti-pru-cgt/example.projectspec            |  83 +++++
 .../icss_m1_pru1_fw/ti-pru-cgt/linker.cmd     |  54 +++
 .../icss_m1_pru1_fw/ti-pru-cgt/makefile       |  55 +++
 .../ti-pru-cgt/makefile_projectspec           |  16 +
 examples/spi_10mhz/firmware/main.asm          |  40 +++
 examples/spi_10mhz/images/spi_10mhz.png       | Bin 0 -> 13368 bytes
 examples/spi_10mhz/makefile                   | 106 ++++++
 .../r5fss0-0_freertos/example.syscfg          | 327 +++++++++++++++++
 .../am261x-lp/r5fss0-0_freertos/main.c        |  84 +++++
 .../ti-arm-clang/example.projectspec          | 116 ++++++
 .../r5fss0-0_freertos/ti-arm-clang/makefile   | 336 ++++++++++++++++++
 .../ti-arm-clang/makefile.defs                |  14 +
 .../ti-arm-clang/makefile_ccs_bootimage_gen   |  95 +++++
 .../ti-arm-clang/makefile_projectspec         |  16 +
 .../ti-arm-clang/syscfg_c.rov.xs              |  12 +
 examples/spi_10mhz/mcuplus/empty_example.c    |  86 +++++
 examples/spi_10mhz/readme.md                  | 169 +++++++++
 24 files changed, 1917 insertions(+)
 create mode 100644 examples/spi_10mhz/firmware/am261x-lp/icss_m1_pru0_fw/example.syscfg
 create mode 100644 examples/spi_10mhz/firmware/am261x-lp/icss_m1_pru0_fw/ti-pru-cgt/example.projectspec
 create mode 100644 examples/spi_10mhz/firmware/am261x-lp/icss_m1_pru0_fw/ti-pru-cgt/linker.cmd
 create mode 100644 examples/spi_10mhz/firmware/am261x-lp/icss_m1_pru0_fw/ti-pru-cgt/makefile
 create mode 100644 examples/spi_10mhz/firmware/am261x-lp/icss_m1_pru0_fw/ti-pru-cgt/makefile_projectspec
 create mode 100644 examples/spi_10mhz/firmware/am261x-lp/icss_m1_pru1_fw/example.syscfg
 create mode 100644 examples/spi_10mhz/firmware/am261x-lp/icss_m1_pru1_fw/ti-pru-cgt/example.projectspec
 create mode 100644 examples/spi_10mhz/firmware/am261x-lp/icss_m1_pru1_fw/ti-pru-cgt/linker.cmd
 create mode 100644 examples/spi_10mhz/firmware/am261x-lp/icss_m1_pru1_fw/ti-pru-cgt/makefile
 create mode 100644 examples/spi_10mhz/firmware/am261x-lp/icss_m1_pru1_fw/ti-pru-cgt/makefile_projectspec
 create mode 100644 examples/spi_10mhz/firmware/main.asm
 create mode 100644 examples/spi_10mhz/images/spi_10mhz.png
 create mode 100644 examples/spi_10mhz/makefile
 create mode 100644 examples/spi_10mhz/mcuplus/am261x-lp/r5fss0-0_freertos/example.syscfg
 create mode 100644 examples/spi_10mhz/mcuplus/am261x-lp/r5fss0-0_freertos/main.c
 create mode 100644 examples/spi_10mhz/mcuplus/am261x-lp/r5fss0-0_freertos/ti-arm-clang/example.projectspec
 create mode 100644 examples/spi_10mhz/mcuplus/am261x-lp/r5fss0-0_freertos/ti-arm-clang/makefile
 create mode 100644 examples/spi_10mhz/mcuplus/am261x-lp/r5fss0-0_freertos/ti-arm-clang/makefile.defs
 create mode 100644 examples/spi_10mhz/mcuplus/am261x-lp/r5fss0-0_freertos/ti-arm-clang/makefile_ccs_bootimage_gen
 create mode 100644 examples/spi_10mhz/mcuplus/am261x-lp/r5fss0-0_freertos/ti-arm-clang/makefile_projectspec
 create mode 100644 examples/spi_10mhz/mcuplus/am261x-lp/r5fss0-0_freertos/ti-arm-clang/syscfg_c.rov.xs
 create mode 100644 examples/spi_10mhz/mcuplus/empty_example.c
 create mode 100644 examples/spi_10mhz/readme.md

diff --git a/examples/makefile b/examples/makefile
index fd15cde..da36ff9 100644
--- a/examples/makefile
+++ b/examples/makefile
@@ -8,6 +8,7 @@ SUBDIRS := \
 	gray_encoder_4_bit \
 	incremental_spi \
 	tamagawa_single_channel \
+	spi_10mhz \
 
 # "make" or "make all" builds projects that match $(DEVICE) set in imports.mak
 all: ARGUMENTS = all
diff --git a/examples/spi_10mhz/firmware/am261x-lp/icss_m1_pru0_fw/example.syscfg b/examples/spi_10mhz/firmware/am261x-lp/icss_m1_pru0_fw/example.syscfg
new file mode 100644
index 0000000..56fdb78
--- /dev/null
+++ b/examples/spi_10mhz/firmware/am261x-lp/icss_m1_pru0_fw/example.syscfg
@@ -0,0 +1,50 @@
+/**
+ * These arguments were used when this file was generated. They will be automatically applied on subsequent loads
+ * via the GUI or CLI. Run CLI with '--help' for additional information on how to override these arguments.
+ * @cliArgs --device "AM261x_ZFG" --part "AM2612" --package "ZFG" --context "icss_m1_pru0" --product "PRU_NO_CODE_TOOL@01.00.01"
+ * @v2CliArgs --device "AM2612" --package "NFBGA (ZFG)" --variant "500MHz" --context "icss_m1_pru0" --product "PRU_NO_CODE_TOOL@01.00.01"
+ * @versions {"tool":"1.27.0+4565"}
+ */
+
+/**
+ * Import the modules used in this configuration.
+ */
+const pru_blocks_static_module = scripting.addModule("/pru_blocks/common/pru_blocks_static_module");
+const load_constant_block      = scripting.addModule("/pru_blocks/data_handling/load_constant_block", {}, false);
+const load_constant_block1     = load_constant_block.addInstance();
+const flow_control_block       = scripting.addModule("/pru_blocks/program_control/flow_control_block", {}, false);
+const flow_control_block1      = flow_control_block.addInstance();
+const pru_spi_transfer         = scripting.addModule("/pru_blocks/pru_io_blocks/pru_spi_transfer", {}, false);
+const pru_spi_transfer1        = pru_spi_transfer.addInstance();
+
+/**
+ * Write custom configuration values to the imported modules.
+ */
+load_constant_block1.$name     = "Load_Constant_0";
+load_constant_block1.constant1 = 2882400171;
+
+flow_control_block1.$name = "Flow_Control_0";
+
+pru_spi_transfer1.$name                                    = "PRU0_SPI_Transfer_0";
+pru_spi_transfer1["SPI Mode"]                              = "MODE1";
+pru_spi_transfer1["CS Signal"]                             = "2";
+pru_spi_transfer1["SDO Signal"]                            = "1";
+pru_spi_transfer1["SDI Signal"]                            = "6";
+pru_spi_transfer1["Data Setup Time"]                       = 50;
+pru_spi_transfer1["CS Setup Time"]                         = 500;
+pru_spi_transfer1["CS Hold Time"]                          = 500;
+pru_spi_transfer1["sclk high pulse width (in PRU cycles)"] = 16;
+pru_spi_transfer1["sclk low pulse width (in PRU cycles)"]  = 6;
+
+/**
+ * Connections between modules.
+ */
+scripting.connect(load_constant_block1, "output1", pru_spi_transfer1, "input1");
+scripting.connect(flow_control_block1, "prev", pru_spi_transfer1, "next");
+
+/**
+ * (x,y) coordinates for modules that are displayed in a graph.
+ */
+load_constant_block1.$position = [-145,155];
+flow_control_block1.$position  = [150,150];
+pru_spi_transfer1.$position    = [0,160];
diff --git a/examples/spi_10mhz/firmware/am261x-lp/icss_m1_pru0_fw/ti-pru-cgt/example.projectspec b/examples/spi_10mhz/firmware/am261x-lp/icss_m1_pru0_fw/ti-pru-cgt/example.projectspec
new file mode 100644
index 0000000..acb706c
--- /dev/null
+++ b/examples/spi_10mhz/firmware/am261x-lp/icss_m1_pru0_fw/ti-pru-cgt/example.projectspec
@@ -0,0 +1,83 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!-- This example.projectspec file is for PRU projects written in assembly -->
+<projectSpec>
+    <applicability>
+        <when>
+            <context
+                deviceFamily="PRU"
+                deviceId="AM261x"
+            />
+        </when>
+    </applicability>
+
+    <project
+        title="spi_10mhz"
+        name = "spi_10mhz_am261x-lp_icss_m1_pru0_fw_ti-pru-cgt"
+        products="sysconfig;com.ti.PRU_NO_CODE_TOOL"
+        configurations="
+                Debug,
+                Release,
+        "
+        connection="TIXDS110_Connection.xml"
+        toolChain="TI"
+        cgtVersion="2.3.3"
+        device="AM261x"
+        deviceCore="ICSS_M0_PRU_0"
+        ignoreDefaultDeviceSettings="true"
+        ignoreDefaultCCSSettings="true"
+        endianness="little"
+        outputFormat="ELF"
+        outputType="executable"
+
+        compilerBuildOptions="
+            -I${CG_TOOL_ROOT}/include
+            -DPRU0
+            -DSLICE0
+            -v4
+            -DSOC_AM261X
+            -O2
+        "
+        linkerBuildOptions="
+            -m=spi_10mhz.${ConfigName}.map
+            --disable_auto_rts
+            --entry_point=main
+            --diag_suppress=10063-D
+            --warn_sections
+            --reread_libs
+            --diag_warning=225
+            --ram_model
+        "
+
+        postBuildStep="
+            $(CG_TOOL_ROOT)/bin/hexpru --diag_wrap=off --array --array:name_prefix=PRU0Firmware -o ../pru0_load_bin.h ${BuildArtifactFileBaseName}.out;
+        "
+
+        enableSysConfigTool="true"
+        sysConfigBuildOptions="
+            --device AM261x_ZFG  --context icss_m1_pru0 --part AM2612 --package ZFG
+        "
+
+        description="A spi_10mhz FW project">
+
+        <configuration name="Debug"
+            compilerBuildOptions="
+                -D_DEBUG_=1
+            "
+            linkerBuildOptions="
+            "
+        ></configuration>
+        <configuration name="Release"
+            compilerBuildOptions="
+            "
+            linkerBuildOptions="
+            "
+        ></configuration>
+        <pathVariable name="PRU_NO_CODE_TOOL_PATH" path="${COM_TI_PRU_NO_CODE_TOOL_INSTALL_DIR}" scope="project" />
+        <file path="../../../main.asm" openOnCreation="false" excludeFromBuild="false" action="copy">
+        </file>
+        <file path="../example.syscfg" openOnCreation="false" excludeFromBuild="false" action="copy">
+        </file>
+        <file path="./linker.cmd" openOnCreation="false" excludeFromBuild="false" action="copy">
+        </file>
+    </project>
+</projectSpec>
diff --git a/examples/spi_10mhz/firmware/am261x-lp/icss_m1_pru0_fw/ti-pru-cgt/linker.cmd b/examples/spi_10mhz/firmware/am261x-lp/icss_m1_pru0_fw/ti-pru-cgt/linker.cmd
new file mode 100644
index 0000000..5d7910e
--- /dev/null
+++ b/examples/spi_10mhz/firmware/am261x-lp/icss_m1_pru0_fw/ti-pru-cgt/linker.cmd
@@ -0,0 +1,54 @@
+/*
+ * AM243x_PRU0.cmd
+ *
+ * Example Linker command file for linking assembly programs built with the TI-PRU-CGT
+ * on AM243x PRU0 cores
+ */
+
+/* Specify the System Memory Map */
+MEMORY
+{
+      PAGE 0:
+	/* 12 KB PRU Instruction RAM */
+	PRU_IMEM	: org = 0x00000000 len = 0x00003000
+
+      PAGE 1:
+	/* Data RAMs */
+	/* 8 KB PRU Data RAM 0; use only the first 4 KB for PRU0 and reserve
+	 * the second 4 KB for RTU0 and Tx_PRU0 */
+	PRU0_DMEM_0	: org = 0x00000000 len = 0x00001000
+	/* 8 KB PRU Data RAM 1; reserved completely for Slice1 cores - PRU0,
+	 * RTU1 and Tx_PRU0; do not use for any Slice0 cores */
+	PRU0_DMEM_1	: org = 0x00002000 len = 0x00001000
+	/* NOTE: Custom split of the second 4 KB of ICSS Data RAMs 0 and 1
+	 * split equally between the corresponding RTU and Tx_PRU cores in
+	 * each slice */
+	RTU0_DMEM_0	: org = 0x00001000 len = 0x00000800
+	TX_PRU0_DMEM_0	: org = 0x00001800 len = 0x00000800
+	RTU1_DMEM_1	: org = 0x00003000 len = 0x00000800
+	TX_PRU0_DMEM_1	: org = 0x00003800 len = 0x00000800
+
+      PAGE 2:
+	/* C28 needs to be programmed to point to SHAREDMEM, default is 0 */
+	/* 64 KB PRU Shared RAM */
+	PRU_SHAREDMEM	: org = 0x00010000 len = 0x00010000
+}
+
+/* Specify the sections allocation into memory */
+SECTIONS {
+	.text:main  >  0,        PAGE 0
+	.text		>  PRU_IMEM, PAGE 0
+	.stack		>  PRU0_DMEM_0, PAGE 1
+	.bss		>  PRU0_DMEM_0, PAGE 1
+	.udmem		>  PRU0_DMEM_0, PAGE 1
+	.initdmem   >  PRU0_DMEM_0, PAGE 1
+	.cio		>  PRU0_DMEM_0, PAGE 1
+	.data		>  PRU0_DMEM_0, PAGE 1
+	.switch		>  PRU0_DMEM_0, PAGE 1
+	.sysmem		>  PRU0_DMEM_0, PAGE 1
+	.cinit		>  PRU0_DMEM_0, PAGE 1
+	.rodata		>  PRU0_DMEM_0, PAGE 1
+	.rofardata	>  PRU0_DMEM_0, PAGE 1
+	.farbss		>  PRU0_DMEM_0, PAGE 1
+	.fardata	>  PRU0_DMEM_0, PAGE 1
+}
diff --git a/examples/spi_10mhz/firmware/am261x-lp/icss_m1_pru0_fw/ti-pru-cgt/makefile b/examples/spi_10mhz/firmware/am261x-lp/icss_m1_pru0_fw/ti-pru-cgt/makefile
new file mode 100644
index 0000000..3be589d
--- /dev/null
+++ b/examples/spi_10mhz/firmware/am261x-lp/icss_m1_pru0_fw/ti-pru-cgt/makefile
@@ -0,0 +1,55 @@
+export PRU_NO_CODE_TOOL_PATH?=$(abspath ../../../../../..)
+include $(PRU_NO_CODE_TOOL_PATH)/imports.mak
+
+# Define build outputs
+OUTPUT_NAME := spi_10mhz_am261x-lp_icss_m1_pru0_fw
+
+# MCU+ projects: rename & move hex array output
+MCU_HEX_NAME := pru0_load_bin.h
+HEX_ARRAY_PREFIX := PRU0Firmware
+MCU_HEX_PATH := $(PRU_NO_CODE_TOOL_PATH)/examples/spi_10mhz/firmware/am261x-lp/$(MCU_HEX_NAME)
+
+# which directories to search for assembly & C source files?
+FILES_PATH := .. ../../.. . syscfg/
+
+# Linker command file
+COMMAND_FILES := linker.cmd
+
+# Silicon version (3: PRUSS, PRU-ICSS; 4: PRU_ICSSG)
+PRU_VERSION := 4
+EXPECTED_DEVICE := am261x
+
+# Default values are defined in pru_rules.mak:
+#   - include paths (INCLUDE)
+#   - compiler flags (CFLAGS)
+#   - linker flags (LFLAGS)
+
+# Optional:
+# Pre-define here to override default value
+#   OPT_LEVEL, STACK_SIZE, HEAP_SIZE, or ENTRY_POINT
+
+# pru_rules.mak has shared settings for all PRU/RTU/TX_PRU core makefiles
+include $(PRU_NO_CODE_TOOL_PATH)/pru_rules.mak
+
+# Optional:
+# Append values to INCLUDE, CFLAGS, or LFLAGS here.
+# Values can be appended like this:
+# INCLUDE += --include_path=<value>
+
+# Defines (pass instance specific definitions to the program)
+# see --define or -D in 'PRU Optimizing C/C++ Compiler User's Guide'
+# For example, to define PRU0, ICSSG1, SOC_AM243X, and set _DEBUG_=1:
+# -DPRU0 -DICSSG1 --define=SOC_AM243X -D_DEBUG_=1
+DFLAGS := -DPRU0 -DPRU1 --define=SOC_AM261X
+
+# Libraries
+# see --library in 'PRU Optimizing C/C++ Compiler User's Guide'
+LIBS :=
+
+syscfg: ../example.syscfg
+	@echo Generating SysConfig files ...
+	$(SYSCFG_NODE) $(SYSCFG_CLI_PATH)/dist/cli.js --product $(SYSCFG_PRU_NO_TOOL_PRODUCT) --device AM261x_ZFG --context icss_m1_pru0 --part AM2612 --package ZFG --output syscfg/ ../example.syscfg
+
+syscfg-gui:
+	$(SYSCFG_NWJS) $(SYSCFG_PATH) --product $(SYSCFG_PRU_NO_TOOL_PRODUCT) --device AM261x_ZFG --context icss_m1_pru0 --part AM2612 --package ZFG --output syscfg/  ../example.syscfg
+
diff --git a/examples/spi_10mhz/firmware/am261x-lp/icss_m1_pru0_fw/ti-pru-cgt/makefile_projectspec b/examples/spi_10mhz/firmware/am261x-lp/icss_m1_pru0_fw/ti-pru-cgt/makefile_projectspec
new file mode 100644
index 0000000..5f84611
--- /dev/null
+++ b/examples/spi_10mhz/firmware/am261x-lp/icss_m1_pru0_fw/ti-pru-cgt/makefile_projectspec
@@ -0,0 +1,16 @@
+export PRU_NO_CODE_TOOL_PATH?=$(abspath ../../../../../..)
+include $(PRU_NO_CODE_TOOL_PATH)/imports.mak
+
+PROFILE?=Release
+
+PROJECT_NAME=spi_10mhz_am261x-lp_icss_m1_pru0_fw_ti-pru-cgt
+
+all:
+	$(CCS_ECLIPSE) -noSplash -data $(PRU_NO_CODE_TOOL_PATH)/ccs_projects -application com.ti.ccstudio.apps.projectBuild -ccs.projects $(PROJECT_NAME) -ccs.configuration $(PROFILE)
+
+clean:
+	$(CCS_ECLIPSE) -noSplash -data $(PRU_NO_CODE_TOOL_PATH)/ccs_projects -application com.ti.ccstudio.apps.projectBuild -ccs.projects $(PROJECT_NAME) -ccs.configuration $(PROFILE) -ccs.clean
+
+export:
+	$(MKDIR) $(PRU_NO_CODE_TOOL_PATH)/ccs_projects
+	$(CCS_ECLIPSE) -noSplash -data $(PRU_NO_CODE_TOOL_PATH)/ccs_projects -application com.ti.ccstudio.apps.projectCreate -ccs.projectSpec example.projectspec -ccs.overwrite full
diff --git a/examples/spi_10mhz/firmware/am261x-lp/icss_m1_pru1_fw/example.syscfg b/examples/spi_10mhz/firmware/am261x-lp/icss_m1_pru1_fw/example.syscfg
new file mode 100644
index 0000000..b13eaed
--- /dev/null
+++ b/examples/spi_10mhz/firmware/am261x-lp/icss_m1_pru1_fw/example.syscfg
@@ -0,0 +1,49 @@
+/**
+ * These arguments were used when this file was generated. They will be automatically applied on subsequent loads
+ * via the GUI or CLI. Run CLI with '--help' for additional information on how to override these arguments.
+ * @cliArgs --device "AM261x_ZFG" --part "AM2612" --package "ZFG" --context "icss_m1_pru1" --product "PRU_NO_CODE_TOOL@01.00.01"
+ * @v2CliArgs --device "AM2612" --package "NFBGA (ZFG)" --variant "500MHz" --context "icss_m1_pru1" --product "PRU_NO_CODE_TOOL@01.00.01"
+ * @versions {"tool":"1.27.0+4565"}
+ */
+
+/**
+ * Import the modules used in this configuration.
+ */
+const pru_blocks_static_module = scripting.addModule("/pru_blocks/common/pru_blocks_static_module");
+const load_constant_block      = scripting.addModule("/pru_blocks/data_handling/load_constant_block", {}, false);
+const load_constant_block1     = load_constant_block.addInstance();
+const flow_control_block       = scripting.addModule("/pru_blocks/program_control/flow_control_block", {}, false);
+const flow_control_block1      = flow_control_block.addInstance();
+const pru_spi_write            = scripting.addModule("/pru_blocks/pru_io_blocks/pru_spi_write", {}, false);
+const pru_spi_write1           = pru_spi_write.addInstance();
+
+/**
+ * Write custom configuration values to the imported modules.
+ */
+pru_blocks_static_module.pruClkFreq = 225;
+
+load_constant_block1.$name     = "Load_Constant_0";
+load_constant_block1.constant1 = 3735936685;
+
+flow_control_block1.$name = "Flow_Control_0";
+
+pru_spi_write1.$name          = "PRU1_SPI_Write_0";
+pru_spi_write1["Device Mode"] = "peripheral";
+pru_spi_write1["SCLK Signal"] = "4";
+pru_spi_write1["SDO Signal"]  = "5";
+pru_spi_write1["CS Signal"]   = "6";
+pru_spi_write1.packetSize     = 32;
+pru_spi_write1.Endiness       = "most significant bit first";
+
+/**
+ * Connections between modules.
+ */
+scripting.connect(load_constant_block1, "output1", pru_spi_write1, "input1");
+scripting.connect(flow_control_block1, "prev", pru_spi_write1, "next");
+
+/**
+ * (x,y) coordinates for modules that are displayed in a graph.
+ */
+load_constant_block1.$position = [-150,140];
+flow_control_block1.$position  = [110,130];
+pru_spi_write1.$position       = [-15,130];
diff --git a/examples/spi_10mhz/firmware/am261x-lp/icss_m1_pru1_fw/ti-pru-cgt/example.projectspec b/examples/spi_10mhz/firmware/am261x-lp/icss_m1_pru1_fw/ti-pru-cgt/example.projectspec
new file mode 100644
index 0000000..8d9faa5
--- /dev/null
+++ b/examples/spi_10mhz/firmware/am261x-lp/icss_m1_pru1_fw/ti-pru-cgt/example.projectspec
@@ -0,0 +1,83 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!-- This example.projectspec file is for PRU projects written in assembly -->
+<projectSpec>
+    <applicability>
+        <when>
+            <context
+                deviceFamily="PRU"
+                deviceId="AM261x"
+            />
+        </when>
+    </applicability>
+
+    <project
+        title="spi_10mhz"
+        name = "spi_10mhz_am261x-lp_icss_m1_pru1_fw_ti-pru-cgt"
+        products="sysconfig;com.ti.PRU_NO_CODE_TOOL"
+        configurations="
+                Debug,
+                Release,
+        "
+        connection="TIXDS110_Connection.xml"
+        toolChain="TI"
+        cgtVersion="2.3.3"
+        device="AM261x"
+        deviceCore="icss_m1_PRU_0"
+        ignoreDefaultDeviceSettings="true"
+        ignoreDefaultCCSSettings="true"
+        endianness="little"
+        outputFormat="ELF"
+        outputType="executable"
+
+        compilerBuildOptions="
+            -I${CG_TOOL_ROOT}/include
+            -DPRU1
+            -DSLICE0
+            -v4
+            -DSOC_AM261X
+            -O2
+        "
+        linkerBuildOptions="
+            -m=spi_10mhz.${ConfigName}.map
+            --disable_auto_rts
+            --entry_point=main
+            --diag_suppress=10063-D
+            --warn_sections
+            --reread_libs
+            --diag_warning=225
+            --ram_model
+        "
+
+        postBuildStep="
+            $(CG_TOOL_ROOT)/bin/hexpru --diag_wrap=off --array --array:name_prefix=PRU1Firmware -o ../pru1_load_bin.h ${BuildArtifactFileBaseName}.out;
+        "
+
+        enableSysConfigTool="true"
+        sysConfigBuildOptions="
+            --device AM261x_ZFG  --context icss_m1_pru1 --part AM2612 --package ZFG
+        "
+
+        description="A spi_10mhz FW project">
+
+        <configuration name="Debug"
+            compilerBuildOptions="
+                -D_DEBUG_=1
+            "
+            linkerBuildOptions="
+            "
+        ></configuration>
+        <configuration name="Release"
+            compilerBuildOptions="
+            "
+            linkerBuildOptions="
+            "
+        ></configuration>
+        <pathVariable name="PRU_NO_CODE_TOOL_PATH" path="${COM_TI_PRU_NO_CODE_TOOL_INSTALL_DIR}" scope="project" />
+        <file path="../../../main.asm" openOnCreation="false" excludeFromBuild="false" action="copy">
+        </file>
+        <file path="../example.syscfg" openOnCreation="false" excludeFromBuild="false" action="copy">
+        </file>
+        <file path="./linker.cmd" openOnCreation="false" excludeFromBuild="false" action="copy">
+        </file>
+    </project>
+</projectSpec>
diff --git a/examples/spi_10mhz/firmware/am261x-lp/icss_m1_pru1_fw/ti-pru-cgt/linker.cmd b/examples/spi_10mhz/firmware/am261x-lp/icss_m1_pru1_fw/ti-pru-cgt/linker.cmd
new file mode 100644
index 0000000..7340f73
--- /dev/null
+++ b/examples/spi_10mhz/firmware/am261x-lp/icss_m1_pru1_fw/ti-pru-cgt/linker.cmd
@@ -0,0 +1,54 @@
+/*
+ * AM243x_PRU1.cmd
+ *
+ * Example Linker command file for linking assembly programs built with the TI-PRU-CGT
+ * on AM243x PRU1 cores
+ */
+
+/* Specify the System Memory Map */
+MEMORY
+{
+      PAGE 0:
+	/* 12 KB PRU Instruction RAM */
+	PRU_IMEM	: org = 0x00000000 len = 0x00003000
+
+      PAGE 1:
+	/* Data RAMs */
+	/* 8 KB PRU Data RAM 0; use only the first 4 KB for PRU1 and reserve
+	 * the second 4 KB for RTU0 and Tx_PRU1 */
+	PRU1_DMEM_0	: org = 0x00000000 len = 0x00001000
+	/* 8 KB PRU Data RAM 1; reserved completely for Slice1 cores - PRU1,
+	 * RTU1 and Tx_PRU1; do not use for any Slice0 cores */
+	PRU1_DMEM_1	: org = 0x00002000 len = 0x00001000
+	/* NOTE: Custom split of the second 4 KB of ICSS Data RAMs 0 and 1
+	 * split equally between the corresponding RTU and Tx_PRU cores in
+	 * each slice */
+	RTU0_DMEM_0	: org = 0x00001000 len = 0x00000800
+	TX_PRU1_DMEM_0	: org = 0x00001800 len = 0x00000800
+	RTU1_DMEM_1	: org = 0x00003000 len = 0x00000800
+	TX_PRU1_DMEM_1	: org = 0x00003800 len = 0x00000800
+
+      PAGE 2:
+	/* C28 needs to be programmed to point to SHAREDMEM, default is 0 */
+	/* 64 KB PRU Shared RAM */
+	PRU_SHAREDMEM	: org = 0x00010000 len = 0x00010000
+}
+
+/* Specify the sections allocation into memory */
+SECTIONS {
+	.text:main  >  0,        PAGE 0
+	.text		>  PRU_IMEM, PAGE 0
+	.stack		>  PRU1_DMEM_0, PAGE 1
+	.bss		>  PRU1_DMEM_0, PAGE 1
+	.udmem		>  PRU1_DMEM_0, PAGE 1
+	.initdmem   >  PRU1_DMEM_0, PAGE 1
+	.cio		>  PRU1_DMEM_0, PAGE 1
+	.data		>  PRU1_DMEM_0, PAGE 1
+	.switch		>  PRU1_DMEM_0, PAGE 1
+	.sysmem		>  PRU1_DMEM_0, PAGE 1
+	.cinit		>  PRU1_DMEM_0, PAGE 1
+	.rodata		>  PRU1_DMEM_0, PAGE 1
+	.rofardata	>  PRU1_DMEM_0, PAGE 1
+	.farbss		>  PRU1_DMEM_0, PAGE 1
+	.fardata	>  PRU1_DMEM_0, PAGE 1
+}
diff --git a/examples/spi_10mhz/firmware/am261x-lp/icss_m1_pru1_fw/ti-pru-cgt/makefile b/examples/spi_10mhz/firmware/am261x-lp/icss_m1_pru1_fw/ti-pru-cgt/makefile
new file mode 100644
index 0000000..82830f7
--- /dev/null
+++ b/examples/spi_10mhz/firmware/am261x-lp/icss_m1_pru1_fw/ti-pru-cgt/makefile
@@ -0,0 +1,55 @@
+export PRU_NO_CODE_TOOL_PATH?=$(abspath ../../../../../..)
+include $(PRU_NO_CODE_TOOL_PATH)/imports.mak
+
+# Define build outputs
+OUTPUT_NAME := spi_10mhz_am261x-lp_icss_m1_pru1_fw
+
+# MCU+ projects: rename & move hex array output
+MCU_HEX_NAME := pru1_load_bin.h
+HEX_ARRAY_PREFIX := PRU1Firmware
+MCU_HEX_PATH := $(PRU_NO_CODE_TOOL_PATH)/examples/spi_10mhz/firmware/am261x-lp/$(MCU_HEX_NAME)
+
+# which directories to search for assembly & C source files?
+FILES_PATH := .. ../../.. . syscfg/
+
+# Linker command file
+COMMAND_FILES := linker.cmd
+
+# Silicon version (3: PRUSS, PRU-ICSS; 4: PRU_ICSSG)
+PRU_VERSION := 4
+EXPECTED_DEVICE := am261x
+
+# Default values are defined in pru_rules.mak:
+#   - include paths (INCLUDE)
+#   - compiler flags (CFLAGS)
+#   - linker flags (LFLAGS)
+
+# Optional:
+# Pre-define here to override default value
+#   OPT_LEVEL, STACK_SIZE, HEAP_SIZE, or ENTRY_POINT
+
+# pru_rules.mak has shared settings for all PRU/RTU/TX_PRU core makefiles
+include $(PRU_NO_CODE_TOOL_PATH)/pru_rules.mak
+
+# Optional:
+# Append values to INCLUDE, CFLAGS, or LFLAGS here.
+# Values can be appended like this:
+# INCLUDE += --include_path=<value>
+
+# Defines (pass instance specific definitions to the program)
+# see --define or -D in 'PRU Optimizing C/C++ Compiler User's Guide'
+# For example, to define PRU1, ICSSG1, SOC_AM243X, and set _DEBUG_=1:
+# -DPRU1 -DICSSG1 --define=SOC_AM243X -D_DEBUG_=1
+DFLAGS := -DPRU0 -DPRU1 --define=SOC_AM261X
+
+# Libraries
+# see --library in 'PRU Optimizing C/C++ Compiler User's Guide'
+LIBS :=
+
+syscfg: ../example.syscfg
+	@echo Generating SysConfig files ...
+	$(SYSCFG_NODE) $(SYSCFG_CLI_PATH)/dist/cli.js --product $(SYSCFG_PRU_NO_TOOL_PRODUCT) --device AM261x_ZFG --context icss_m1_pru1 --part AM2612 --package ZFG --output syscfg/ ../example.syscfg
+
+syscfg-gui:
+	$(SYSCFG_NWJS) $(SYSCFG_PATH) --product $(SYSCFG_PRU_NO_TOOL_PRODUCT) --device AM261x_ZFG --context icss_m1_pru1 --part AM2612 --package ZFG --output syscfg/  ../example.syscfg
+
diff --git a/examples/spi_10mhz/firmware/am261x-lp/icss_m1_pru1_fw/ti-pru-cgt/makefile_projectspec b/examples/spi_10mhz/firmware/am261x-lp/icss_m1_pru1_fw/ti-pru-cgt/makefile_projectspec
new file mode 100644
index 0000000..e3c26c0
--- /dev/null
+++ b/examples/spi_10mhz/firmware/am261x-lp/icss_m1_pru1_fw/ti-pru-cgt/makefile_projectspec
@@ -0,0 +1,16 @@
+export PRU_NO_CODE_TOOL_PATH?=$(abspath ../../../../../..)
+include $(PRU_NO_CODE_TOOL_PATH)/imports.mak
+
+PROFILE?=Release
+
+PROJECT_NAME=spi_10mhz_am261x-lp_icss_m1_pru1_fw_ti-pru-cgt
+
+all:
+	$(CCS_ECLIPSE) -noSplash -data $(PRU_NO_CODE_TOOL_PATH)/ccs_projects -application com.ti.ccstudio.apps.projectBuild -ccs.projects $(PROJECT_NAME) -ccs.configuration $(PROFILE)
+
+clean:
+	$(CCS_ECLIPSE) -noSplash -data $(PRU_NO_CODE_TOOL_PATH)/ccs_projects -application com.ti.ccstudio.apps.projectBuild -ccs.projects $(PROJECT_NAME) -ccs.configuration $(PROFILE) -ccs.clean
+
+export:
+	$(MKDIR) $(PRU_NO_CODE_TOOL_PATH)/ccs_projects
+	$(CCS_ECLIPSE) -noSplash -data $(PRU_NO_CODE_TOOL_PATH)/ccs_projects -application com.ti.ccstudio.apps.projectCreate -ccs.projectSpec example.projectspec -ccs.overwrite full
diff --git a/examples/spi_10mhz/firmware/main.asm b/examples/spi_10mhz/firmware/main.asm
new file mode 100644
index 0000000..586984e
--- /dev/null
+++ b/examples/spi_10mhz/firmware/main.asm
@@ -0,0 +1,40 @@
+; SPDX-License-Identifier: BSD-3-Clause
+; Copyright (C) 2024-2025 Texas Instruments Incorporated - http://www.ti.com/
+
+;***************************************************************************************
+;   File:     main.asm
+;
+;   Brief:    Empty example assembly file (asm) with halt instruction
+;
+;   Steps to build :
+;
+;   - Using ccs:
+;             - Import pru project to ccs workspace
+;             - main.asm file gets copied to ccs workspace
+;             - Modify main.asm file
+;             - Build the pru project, after which .out (Executable output file) and .h (Firmware header) files gets generated
+;             - Either .out (Executable output file) can be loaded to PRU using ccs or R5F can write to PRU IRAM using PRUICSS driver
+;   - Using makefile:
+;             - Use command gmake -all to build PRU project     
+;
+;***************************************************************************************
+
+; CCS/makefile specific settings
+    .retain     ; Required for building .out with assembly file
+    .retainrefs ; Required for building .out with assembly file
+
+    .global     main
+    .ref        sysconfig_generated_start
+    .global     sysconfig_generated_end
+    .sect       ".text:main"
+
+;********
+;* MAIN *
+;********
+
+main:
+    ; halt the program after jumping to sysconfig generated start
+    zero &r0,120
+    JMP     sysconfig_generated_start
+sysconfig_generated_end:
+    halt
diff --git a/examples/spi_10mhz/images/spi_10mhz.png b/examples/spi_10mhz/images/spi_10mhz.png
new file mode 100644
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zR@06==&Rc;R6~zyMJLwNOls#8tL-hJMKbtY2+Rx}|1njEk8POh7L@7mMk##R{JXfi
zIwxN9>_f6nk|%v|3}jLeNWaBa_Is%pyxG_<n-UWK<hDrn?;7W}MqFG1U*DcRfe97-
z+57#}7Wgk}!qmFw=c#iCrf*gOA59VCUk<KJzdUc+U|;lVXKwuK#UG>H177N|wDT`+
KUuAAReEx4{RZQOi

literal 0
HcmV?d00001

diff --git a/examples/spi_10mhz/makefile b/examples/spi_10mhz/makefile
new file mode 100644
index 0000000..5cd0333
--- /dev/null
+++ b/examples/spi_10mhz/makefile
@@ -0,0 +1,106 @@
+include ../../imports.mak
+
+#######################
+# project information #
+#######################
+
+PROJECT_NAME := spi_10mhz
+SUPPORTED_PROCESSORS := am261x
+# Does the PRU code have dependencies outside of the pru-no-code-tool repo?
+PRU_DEPENDENCIES :=
+# Use NON_PRU_DEPENDENCIES to select which makefiles to call for non-PRU cores
+NON_PRU_DEPENDENCIES := mcuplus
+
+###################
+# Prebuild checks #
+###################
+BUILD_PROJECT := y
+DEVICE_NON_PRU :=
+
+# Only build project if $(DEVICE) is in $(SUPPORTED_PROCESSORS)
+ifeq (,$(findstring $(DEVICE),$(SUPPORTED_PROCESSORS)))
+BUILD_PROJECT := n
+MESSAGE := Project $(PROJECT_NAME) does not have a build option for $(DEVICE)
+endif
+
+# Only build project if PRU dependencies exist
+ifneq (,$(PRU_DEPENDENCIES))
+# MCU+ SDK dependency?
+ifeq (mcuplus,$(findstring mcuplus,$(PRU_DEPENDENCIES)))
+ifneq ($(BUILD_MCUPLUS),y)
+BUILD_PROJECT := n
+MESSAGE ?= Project $(PROJECT_NAME) depends on MCU+ SDK, but BUILD_MCUPLUS != y.
+endif
+endif
+# Additional PRU dependency checks go here. For example:
+#ifeq (dependency,$(findstring dependency,$(PRU_DEPENDENCIES)))
+#if (dependency check fails)
+#BUILD_PROJECT := n
+#MESSAGE ?= Project $(PROJECT_NAME) depends on dependency, but dependency does not exist.
+#endif
+#endif
+endif
+
+# Only build non-PRU code if the non-PRU code is enabled in imports.mak
+ifeq ($(BUILD_MCUPLUS),y)
+ifeq (mcuplus,$(findstring mcuplus,$(NON_PRU_DEPENDENCIES)))
+DEVICE_NON_PRU += $(DEVICE)_mcuplus
+endif
+endif
+ifeq ($(BUILD_LINUX),y)
+ifeq (linux,$(findstring linux,$(NON_PRU_DEPENDENCIES)))
+DEVICE_NON_PRU += $(DEVICE)_linux
+endif
+endif
+
+###########################
+# Make and clean commands #
+###########################
+
+ifeq ($(BUILD_PROJECT),y)
+# "make" or "make all" builds projects that match $(DEVICE) set in imports.mak
+# "make" builds PRU firmware first, then host (non-PRU) code
+all: MESSAGE = "Building $(PROJECT_NAME) for $(DEVICE)"
+all: pre_build_message
+	$(MAKE) pru
+	$(MAKE) host
+
+# "make pru" builds only PRU firmware for $(DEVICE)
+pru: ARGUMENTS_PRU = all
+pru: $(DEVICE)
+
+# "make host" builds only host (non-PRU) code for $(DEVICE)
+host: ARGUMENTS_MCUPLUS = all
+host: $(DEVICE_NON_PRU)
+
+# "make clean" cleans projects that match $(DEVICE) set in imports.mak
+clean: ARGUMENTS_PRU = clean
+clean: ARGUMENTS_MCUPLUS = scrub
+clean: MESSAGE = "Cleaning $(PROJECT_NAME) for $(DEVICE)"
+clean: pre_build_message $(DEVICE) $(DEVICE_NON_PRU)
+
+else
+# if a prebuild check failed, print message and exit
+all clean pru host: pre_build_message
+endif
+
+pre_build_message:
+	@echo $(MESSAGE)
+
+######################
+# Target definitions #
+######################
+
+# provide target definitions for each supported processor
+# PRU firmware should be built before any RTOS code that includes it
+am261x:
+# am261x-lp
+	$(MAKE) -C firmware/am261x-lp/icss_m1_pru0_fw/ti-pru-cgt $(ARGUMENTS_PRU)
+	$(MAKE) -C firmware/am261x-lp/icss_m1_pru1_fw/ti-pru-cgt $(ARGUMENTS_PRU)
+
+am261x_mcuplus:
+# am261x-lp
+	$(MAKE) -C mcuplus/am261x-lp/r5fss0-0_freertos/ti-arm-clang $(ARGUMENTS_MCUPLUS)
+
+.PHONY: all clean pru host pre_build_message $(DEVICE) $(DEVICE_NON_PRU) $(SUPPORTED_PROCESSORS)
+
diff --git a/examples/spi_10mhz/mcuplus/am261x-lp/r5fss0-0_freertos/example.syscfg b/examples/spi_10mhz/mcuplus/am261x-lp/r5fss0-0_freertos/example.syscfg
new file mode 100644
index 0000000..c9e69a2
--- /dev/null
+++ b/examples/spi_10mhz/mcuplus/am261x-lp/r5fss0-0_freertos/example.syscfg
@@ -0,0 +1,327 @@
+/**
+ * These arguments were used when this file was generated. They will be automatically applied on subsequent loads
+ * via the GUI or CLI. Run CLI with '--help' for additional information on how to override these arguments.
+ * @cliArgs --device "AM261x_ZFG" --part "AM2612" --package "ZFG" --context "r5fss0-0" --product "MCU_PLUS_SDK_AM261x@11.00.00"
+ * @v2CliArgs --device "AM2612" --package "NFBGA (ZFG)" --variant "500MHz" --context "r5fss0-0" --product "MCU_PLUS_SDK_AM261x@11.00.00"
+ * @versions {"tool":"1.27.0+4565"}
+ */
+
+/**
+ * Import the modules used in this configuration.
+ */
+const ioexp           = scripting.addModule("/board/ioexp/ioexp", {}, false);
+const ioexp1          = ioexp.addInstance();
+const i2c             = scripting.addModule("/drivers/i2c/i2c", {}, false);
+const i2c1            = i2c.addInstance();
+const pruicss         = scripting.addModule("/drivers/pruicss/pruicss", {}, false);
+const pruicss1        = pruicss.addInstance();
+const debug_log       = scripting.addModule("/kernel/dpl/debug_log");
+const dpl_cfg         = scripting.addModule("/kernel/dpl/dpl_cfg");
+const mpu_armv7       = scripting.addModule("/kernel/dpl/mpu_armv7", {}, false);
+const mpu_armv71      = mpu_armv7.addInstance();
+const mpu_armv72      = mpu_armv7.addInstance();
+const mpu_armv73      = mpu_armv7.addInstance();
+const mpu_armv74      = mpu_armv7.addInstance();
+const mpu_armv75      = mpu_armv7.addInstance();
+const mpu_armv76      = mpu_armv7.addInstance();
+const default_linker  = scripting.addModule("/memory_configurator/default_linker", {}, false);
+const default_linker1 = default_linker.addInstance();
+const general         = scripting.addModule("/memory_configurator/general", {}, false);
+const general1        = general.addInstance();
+const region          = scripting.addModule("/memory_configurator/region", {}, false);
+const region1         = region.addInstance();
+const section         = scripting.addModule("/memory_configurator/section", {}, false);
+const section1        = section.addInstance();
+const section2        = section.addInstance();
+const section3        = section.addInstance();
+const section4        = section.addInstance();
+const section5        = section.addInstance();
+const section6        = section.addInstance();
+const section7        = section.addInstance();
+const section8        = section.addInstance();
+const section9        = section.addInstance();
+const section10       = section.addInstance();
+const section11       = section.addInstance();
+const section12       = section.addInstance();
+
+/**
+ * Write custom configuration values to the imported modules.
+ */
+ioexp1.$name                                     = "CONFIG_IOEXP0";
+ioexp1.TCA6408ARGTR_port0_pinBP_MUX_SW_S1_mode   = 0;
+ioexp1.TCA6408ARGTR_port0_pinBP_BO_MUX_EN_N_mode = 0;
+ioexp1.TCA6408ARGTR_port0_pinBP_MUX_SW_SO_mode   = 0;
+ioexp1.TCA6408ARGTR_port0_pinBP_MUX_SW_S1_state  = 1;
+ioexp1.TCA6408ARGTR_port0_pinBP_BO_MUX_EN_mode   = 0;
+
+ioexp1.peripheralDriver = i2c1;
+i2c1.$name              = "CONFIG_I2C2";
+i2c1.I2C.$assign        = "I2C0";
+i2c1.I2C.SCL.$assign    = "GPIO135";
+i2c1.I2C.SDA.$assign    = "GPIO134";
+i2c1.I2C_child.$name    = "drivers_i2c_v1_i2c_v1_template1";
+
+pruicss1.$name                                                                     = "CONFIG_PRU_ICSS0";
+pruicss1.instance                                                                  = "ICSSM1";
+pruicss1.AdditionalICSSSettings[0].$name                                           = "CONFIG_PRU_ICSS_IO0";
+pruicss1.AdditionalICSSSettings[0].PruGPIO.create(1);
+pruicss1.AdditionalICSSSettings[0].PruGPIO[0].$name                                = "CONFIG_PRU_ICSS_GPIO0";
+pruicss1.AdditionalICSSSettings[0].PruGPIO[0]["PRU-ICSS1"].$assign                 = "PRU-ICSS1";
+pruicss1.AdditionalICSSSettings[0].PruGPIO[0]["PRU-ICSS1"].PR1_PRU1_GPIO5.$assign  = "GPIO54";
+pruicss1.AdditionalICSSSettings[0].PruGPIO[0]["PRU-ICSS1"].PR1_PRU1_GPIO5.$used    = true;
+pruicss1.AdditionalICSSSettings[0].PruGPIO[0]["PRU-ICSS1"].PR1_PRU1_GPIO6.rx       = true;
+pruicss1.AdditionalICSSSettings[0].PruGPIO[0]["PRU-ICSS1"].PR1_PRU1_GPIO6.$assign  = "GPIO19";
+pruicss1.AdditionalICSSSettings[0].PruGPIO[0]["PRU-ICSS1"].PR1_PRU1_GPIO6.$used    = true;
+pruicss1.AdditionalICSSSettings[0].PruGPIO[0]["PRU-ICSS1"].PR1_PRU1_GPIO4.rx       = true;
+pruicss1.AdditionalICSSSettings[0].PruGPIO[0]["PRU-ICSS1"].PR1_PRU1_GPIO4.$assign  = "GPIO15";
+pruicss1.AdditionalICSSSettings[0].PruGPIO[0]["PRU-ICSS1"].PR1_PRU1_GPIO4.$used    = true;
+pruicss1.AdditionalICSSSettings[0].PruGPIO[0]["PRU-ICSS1"].PR1_PRU0_GPIO0.$assign  = "GPIO81";
+pruicss1.AdditionalICSSSettings[0].PruGPIO[0]["PRU-ICSS1"].PR1_PRU0_GPIO0.$used    = true;
+pruicss1.AdditionalICSSSettings[0].PruGPIO[0]["PRU-ICSS1"].PR1_PRU0_GPIO1.$assign  = "GPIO82";
+pruicss1.AdditionalICSSSettings[0].PruGPIO[0]["PRU-ICSS1"].PR1_PRU0_GPIO1.$used    = true;
+pruicss1.AdditionalICSSSettings[0].PruGPIO[0]["PRU-ICSS1"].PR1_PRU0_GPIO2.$assign  = "GPIO83";
+pruicss1.AdditionalICSSSettings[0].PruGPIO[0]["PRU-ICSS1"].PR1_PRU0_GPIO2.$used    = true;
+pruicss1.AdditionalICSSSettings[0].PruGPIO[0]["PRU-ICSS1"].PR1_PRU0_GPIO9.$assign  = "GPIO80";
+pruicss1.AdditionalICSSSettings[0].PruGPIO[0]["PRU-ICSS1"].PR1_PRU1_GPIO11.rx      = true;
+pruicss1.AdditionalICSSSettings[0].PruGPIO[0]["PRU-ICSS1"].PR1_PRU1_GPIO11.$assign = "GPIO3";
+pruicss1.AdditionalICSSSettings[0].PruGPIO[0]["PRU-ICSS1"].PR1_PRU1_GPIO11.$used   = true;
+pruicss1.AdditionalICSSSettings[0].PruGPIO[0]["PRU-ICSS1"].PR1_PRU1_GPIO1.$assign  = "GPIO72";
+pruicss1.AdditionalICSSSettings[0].PruGPIO[0]["PRU-ICSS1"].PR1_PRU1_GPIO1.$used    = true;
+pruicss1.AdditionalICSSSettings[0].PruGPIO[0]["PRU-ICSS1"].PR1_PRU1_GPIO2.rx       = true;
+pruicss1.AdditionalICSSSettings[0].PruGPIO[0]["PRU-ICSS1"].PR1_PRU1_GPIO2.$assign  = "GPIO73";
+pruicss1.AdditionalICSSSettings[0].PruGPIO[0]["PRU-ICSS1"].PR1_PRU1_GPIO2.$used    = true;
+pruicss1.AdditionalICSSSettings[0].PruGPIO[0]["PRU-ICSS1"].PR1_PRU0_GPIO7.$assign  = "GPIO26";
+pruicss1.AdditionalICSSSettings[0].PruGPIO[0]["PRU-ICSS1"].PR1_PRU0_GPIO7.$used    = true;
+pruicss1.AdditionalICSSSettings[0].PruGPIO[0]["PRU-ICSS1"].PR1_PRU0_GPIO6.rx       = true;
+pruicss1.AdditionalICSSSettings[0].PruGPIO[0]["PRU-ICSS1"].PR1_PRU0_GPIO6.$assign  = "GPIO45";
+pruicss1.AdditionalICSSSettings[0].PruGPIO[0]["PRU-ICSS1"].PR1_PRU0_GPIO6.$used    = true;
+
+debug_log.enableUartLog            = true;
+debug_log.enableSharedMemLog       = true;
+debug_log.enableSharedMemLogReader = true;
+debug_log.uartLog.$name            = "CONFIG_UART0";
+debug_log.uartLog.UART.$assign     = "UART0";
+debug_log.uartLog.UART.RXD.$assign = "GPIO27";
+debug_log.uartLog.UART.TXD.$assign = "GPIO28";
+debug_log.uartLog.child.$name      = "drivers_uart_v2_uart_v2_template0";
+
+mpu_armv71.$name             = "CONFIG_MPU_REGION0";
+mpu_armv71.size              = 31;
+mpu_armv71.attributes        = "Device";
+mpu_armv71.accessPermissions = "Supervisor RD+WR, User RD";
+mpu_armv71.allowExecute      = false;
+
+mpu_armv72.$name             = "CONFIG_MPU_REGION1";
+mpu_armv72.size              = 15;
+mpu_armv72.accessPermissions = "Supervisor RD+WR, User RD";
+
+mpu_armv73.$name             = "CONFIG_MPU_REGION2";
+mpu_armv73.baseAddr          = 0x80000;
+mpu_armv73.size              = 15;
+mpu_armv73.accessPermissions = "Supervisor RD+WR, User RD";
+
+mpu_armv74.$name             = "CONFIG_MPU_REGION3";
+mpu_armv74.accessPermissions = "Supervisor RD+WR, User RD";
+mpu_armv74.baseAddr          = 0x70000000;
+mpu_armv74.size              = 21;
+
+mpu_armv75.$name        = "CONFIG_MPU_REGION4";
+mpu_armv75.size         = 14;
+mpu_armv75.baseAddr     = 0x50D00000;
+mpu_armv75.allowExecute = false;
+mpu_armv75.attributes   = "Device";
+
+mpu_armv76.$name        = "CONFIG_MPU_REGION5";
+mpu_armv76.size         = 14;
+mpu_armv76.allowExecute = false;
+mpu_armv76.attributes   = "NonCached";
+mpu_armv76.baseAddr     = 0x72000000;
+
+default_linker1.$name = "memory_configurator_default_linker0";
+
+general1.$name        = "CONFIG_GENERAL0";
+general1.linker.$name = "TIARMCLANG0";
+
+region1.$name                                = "MEMORY_REGION_CONFIGURATION0";
+region1.memory_region.create(11);
+region1.memory_region[0].type                = "TCMA";
+region1.memory_region[0].$name               = "R5F_VECS";
+region1.memory_region[0].size                = 0x40;
+region1.memory_region[0].auto                = false;
+region1.memory_region[1].type                = "TCMA";
+region1.memory_region[1].$name               = "R5F_TCMA";
+region1.memory_region[1].size                = 0x7FC0;
+region1.memory_region[2].type                = "TCMB";
+region1.memory_region[2].size                = 0x8000;
+region1.memory_region[2].$name               = "R5F_TCMB";
+region1.memory_region[3].$name               = "SBL";
+region1.memory_region[3].auto                = false;
+region1.memory_region[3].size                = 0x40000;
+region1.memory_region[4].$name               = "OCRAM";
+region1.memory_region[4].auto                = false;
+region1.memory_region[4].manualStartAddress  = 0x70040000;
+region1.memory_region[4].size                = 0x40000;
+region1.memory_region[5].type                = "FLASH";
+region1.memory_region[5].auto                = false;
+region1.memory_region[5].manualStartAddress  = 0x60100000;
+region1.memory_region[5].size                = 0x80000;
+region1.memory_region[5].$name               = "FLASH";
+region1.memory_region[6].$name               = "USER_SHM_MEM";
+region1.memory_region[6].auto                = false;
+region1.memory_region[6].manualStartAddress  = 0x70150000;
+region1.memory_region[6].size                = 0x4000;
+region1.memory_region[6].isShared            = true;
+region1.memory_region[6].shared_cores        = ["r5fss0-1"];
+region1.memory_region[7].$name               = "LOG_SHM_MEM";
+region1.memory_region[7].auto                = false;
+region1.memory_region[7].manualStartAddress  = 0x70154000;
+region1.memory_region[7].size                = 0x4000;
+region1.memory_region[7].isShared            = true;
+region1.memory_region[7].shared_cores        = ["r5fss0-1"];
+region1.memory_region[8].type                = "CUSTOM";
+region1.memory_region[8].$name               = "RTOS_NORTOS_IPC_SHM_MEM";
+region1.memory_region[8].auto                = false;
+region1.memory_region[8].manualStartAddress  = 0x72000000;
+region1.memory_region[8].size                = 0x3E80;
+region1.memory_region[8].isShared            = true;
+region1.memory_region[8].shared_cores        = ["r5fss0-1"];
+region1.memory_region[9].type                = "CUSTOM";
+region1.memory_region[9].$name               = "MAILBOX_HSM";
+region1.memory_region[9].auto                = false;
+region1.memory_region[9].manualStartAddress  = 0x44000000;
+region1.memory_region[9].size                = 0x3CE;
+region1.memory_region[9].isShared            = true;
+region1.memory_region[9].shared_cores        = ["r5fss0-1"];
+region1.memory_region[10].type               = "CUSTOM";
+region1.memory_region[10].$name              = "MAILBOX_R5F";
+region1.memory_region[10].auto               = false;
+region1.memory_region[10].manualStartAddress = 0x44000400;
+region1.memory_region[10].size               = 0x3CE;
+region1.memory_region[10].isShared           = true;
+region1.memory_region[10].shared_cores       = ["r5fss0-1"];
+
+section1.load_memory                  = "R5F_VECS";
+section1.group                        = false;
+section1.$name                        = "Vector Table";
+section1.output_section.create(1);
+section1.output_section[0].$name      = ".vectors";
+section1.output_section[0].palignment = true;
+
+section2.load_memory                  = "OCRAM";
+section2.$name                        = "Text Segments";
+section2.output_section.create(5);
+section2.output_section[0].$name      = ".text.hwi";
+section2.output_section[0].palignment = true;
+section2.output_section[1].$name      = ".text.cache";
+section2.output_section[1].palignment = true;
+section2.output_section[2].$name      = ".text.mpu";
+section2.output_section[2].palignment = true;
+section2.output_section[3].$name      = ".text.boot";
+section2.output_section[3].palignment = true;
+section2.output_section[4].$name      = ".text:abort";
+section2.output_section[4].palignment = true;
+
+section3.load_memory                  = "OCRAM";
+section3.$name                        = "Code and Read-Only Data";
+section3.output_section.create(2);
+section3.output_section[0].$name      = ".text";
+section3.output_section[0].palignment = true;
+section3.output_section[1].$name      = ".rodata";
+section3.output_section[1].palignment = true;
+
+section4.load_memory                  = "OCRAM";
+section4.$name                        = "Data Segment";
+section4.output_section.create(1);
+section4.output_section[0].$name      = ".data";
+section4.output_section[0].palignment = true;
+
+section5.load_memory                             = "OCRAM";
+section5.$name                                   = "Memory Segments";
+section5.output_section.create(3);
+section5.output_section[0].$name                 = ".bss";
+section5.output_section[0].output_sections_start = "__BSS_START";
+section5.output_section[0].output_sections_end   = "__BSS_END";
+section5.output_section[0].palignment            = true;
+section5.output_section[1].$name                 = ".sysmem";
+section5.output_section[1].palignment            = true;
+section5.output_section[2].$name                 = ".stack";
+section5.output_section[2].palignment            = true;
+
+section6.load_memory                              = "OCRAM";
+section6.$name                                    = "Stack Segments";
+section6.output_section.create(5);
+section6.output_section[0].$name                  = ".irqstack";
+section6.output_section[0].output_sections_start  = "__IRQ_STACK_START";
+section6.output_section[0].output_sections_end    = "__IRQ_STACK_END";
+section6.output_section[0].input_section.create(1);
+section6.output_section[0].input_section[0].$name = ". = . + __IRQ_STACK_SIZE;";
+section6.output_section[1].$name                  = ".fiqstack";
+section6.output_section[1].output_sections_start  = "__FIQ_STACK_START";
+section6.output_section[1].output_sections_end    = "__FIQ_STACK_END";
+section6.output_section[1].input_section.create(1);
+section6.output_section[1].input_section[0].$name = ". = . + __FIQ_STACK_SIZE;";
+section6.output_section[2].$name                  = ".svcstack";
+section6.output_section[2].output_sections_start  = "__SVC_STACK_START";
+section6.output_section[2].output_sections_end    = "__SVC_STACK_END";
+section6.output_section[2].input_section.create(1);
+section6.output_section[2].input_section[0].$name = ". = . + __SVC_STACK_SIZE;";
+section6.output_section[3].$name                  = ".abortstack";
+section6.output_section[3].output_sections_start  = "__ABORT_STACK_START";
+section6.output_section[3].output_sections_end    = "__ABORT_STACK_END";
+section6.output_section[3].input_section.create(1);
+section6.output_section[3].input_section[0].$name = ". = . + __ABORT_STACK_SIZE;";
+section6.output_section[4].$name                  = ".undefinedstack";
+section6.output_section[4].output_sections_start  = "__UNDEFINED_STACK_START";
+section6.output_section[4].output_sections_end    = "__UNDEFINED_STACK_END";
+section6.output_section[4].input_section.create(1);
+section6.output_section[4].input_section[0].$name = ". = . + __UNDEFINED_STACK_SIZE;";
+
+section7.load_memory                  = "OCRAM";
+section7.$name                        = "Initialization and Exception Handling";
+section7.output_section.create(3);
+section7.output_section[0].$name      = ".ARM.exidx";
+section7.output_section[0].palignment = true;
+section7.output_section[1].$name      = ".init_array";
+section7.output_section[1].palignment = true;
+section7.output_section[2].$name      = ".fini_array";
+section7.output_section[2].palignment = true;
+
+section8.load_memory                 = "USER_SHM_MEM";
+section8.type                        = "NOLOAD";
+section8.$name                       = "User Shared Memory";
+section8.group                       = false;
+section8.output_section.create(1);
+section8.output_section[0].$name     = ".bss.user_shared_mem";
+section8.output_section[0].alignment = 0;
+
+section9.load_memory                 = "LOG_SHM_MEM";
+section9.$name                       = "Log Shared Memory";
+section9.group                       = false;
+section9.type                        = "NOLOAD";
+section9.output_section.create(1);
+section9.output_section[0].$name     = ".bss.log_shared_mem";
+section9.output_section[0].alignment = 0;
+
+section10.load_memory                 = "RTOS_NORTOS_IPC_SHM_MEM";
+section10.type                        = "NOLOAD";
+section10.$name                       = "IPC Shared Memory";
+section10.group                       = false;
+section10.output_section.create(1);
+section10.output_section[0].$name     = ".bss.ipc_vring_mem";
+section10.output_section[0].alignment = 0;
+
+section11.load_memory                 = "MAILBOX_HSM";
+section11.type                        = "NOLOAD";
+section11.$name                       = "SIPC HSM Queue Memory";
+section11.group                       = false;
+section11.output_section.create(1);
+section11.output_section[0].$name     = ".bss.sipc_hsm_queue_mem";
+section11.output_section[0].alignment = 0;
+
+section12.load_memory                 = "MAILBOX_R5F";
+section12.$name                       = "SIPC R5F Queue Memory";
+section12.group                       = false;
+section12.type                        = "NOLOAD";
+section12.output_section.create(1);
+section12.output_section[0].$name     = ".bss.sipc_secure_host_queue_mem";
+section12.output_section[0].alignment = 0;
diff --git a/examples/spi_10mhz/mcuplus/am261x-lp/r5fss0-0_freertos/main.c b/examples/spi_10mhz/mcuplus/am261x-lp/r5fss0-0_freertos/main.c
new file mode 100644
index 0000000..b8dd06a
--- /dev/null
+++ b/examples/spi_10mhz/mcuplus/am261x-lp/r5fss0-0_freertos/main.c
@@ -0,0 +1,84 @@
+/*
+ *  Copyright (C) 2024-2025 Texas Instruments Incorporated
+ *
+ *  Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions
+ *  are met:
+ *
+ *    Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *
+ *    Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the
+ *    distribution.
+ *
+ *    Neither the name of Texas Instruments Incorporated nor the names of
+ *    its contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ *  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ *  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ *  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ *  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ *  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ *  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ *  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ *  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ *  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <stdlib.h>
+#include <kernel/dpl/DebugP.h>
+#include "ti_drivers_config.h"
+#include "ti_board_config.h"
+#include "FreeRTOS.h"
+#include "task.h"
+
+#define MAIN_TASK_PRI  (configMAX_PRIORITIES-1)
+
+#define MAIN_TASK_SIZE (16384U/sizeof(configSTACK_DEPTH_TYPE))
+StackType_t gMainTaskStack[MAIN_TASK_SIZE] __attribute__((aligned(32)));
+
+StaticTask_t gMainTaskObj;
+TaskHandle_t gMainTask;
+
+void empty_example_main(void *args);
+
+void freertos_main(void *args)
+{
+    empty_example_main(NULL);
+
+    vTaskDelete(NULL);
+}
+
+
+int main(void)
+{
+    /* init SOC specific modules */
+    System_init();
+    Board_init();
+
+    /* This task is created at highest priority, it should create more tasks and then delete itself */
+    gMainTask = xTaskCreateStatic( freertos_main,   /* Pointer to the function that implements the task. */
+                                  "freertos_main", /* Text name for the task.  This is to facilitate debugging only. */
+                                  MAIN_TASK_SIZE,  /* Stack depth in units of StackType_t typically uint32_t on 32b CPUs */
+                                  NULL,            /* We are not using the task parameter. */
+                                  MAIN_TASK_PRI,   /* task priority, 0 is lowest priority, configMAX_PRIORITIES-1 is highest */
+                                  gMainTaskStack,  /* pointer to stack base */
+                                  &gMainTaskObj ); /* pointer to statically allocated task object memory */
+    configASSERT(gMainTask != NULL);
+
+    /* Start the scheduler to start the tasks executing. */
+    vTaskStartScheduler();
+
+    /* The following line should never be reached because vTaskStartScheduler()
+    will only return if there was not enough FreeRTOS heap memory available to
+    create the Idle and (if configured) Timer tasks.  Heap management, and
+    techniques for trapping heap exhaustion, are described in the book text. */
+    DebugP_assertNoLog(0);
+
+    return 0;
+}
diff --git a/examples/spi_10mhz/mcuplus/am261x-lp/r5fss0-0_freertos/ti-arm-clang/example.projectspec b/examples/spi_10mhz/mcuplus/am261x-lp/r5fss0-0_freertos/ti-arm-clang/example.projectspec
new file mode 100644
index 0000000..b5a26d0
--- /dev/null
+++ b/examples/spi_10mhz/mcuplus/am261x-lp/r5fss0-0_freertos/ti-arm-clang/example.projectspec
@@ -0,0 +1,116 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<projectSpec>
+    <applicability>
+        <when>
+            <context
+                deviceFamily="ARM"
+                deviceId="Cortex R.AM261x"
+            />
+        </when>
+    </applicability>
+
+    <project
+        title="spi_10mhz Pru"
+        name = "spi_10mhz_am261x-lp_r5fss0-0_freertos_ti-arm-clang"
+        products="sysconfig;MCU-PLUS-SDK-AM261X"
+        configurations="
+                Debug,
+                Release,
+        "
+        connection="TIXDS110_Connection.xml"
+        toolChain="TICLANG"
+        cgtVersion="4.0.0"
+        device="Cortex R.AM261x"
+        deviceCore="Cortex_R5_0"
+        ignoreDefaultDeviceSettings="true"
+        ignoreDefaultCCSSettings="true"
+        endianness="little"
+        outputFormat="ELF"
+        outputType="executable"
+
+        compilerBuildOptions="
+            -I${CG_TOOL_ROOT}/include/c
+            -I${MCU_PLUS_SDK_PATH}/source
+            -I${MCU_PLUS_SDK_PATH}/source/kernel/freertos/FreeRTOS-Kernel/include
+            -I${MCU_PLUS_SDK_PATH}/source/kernel/freertos/portable/TI_ARM_CLANG/ARM_CR5F
+            -I${MCU_PLUS_SDK_PATH}/source/kernel/freertos/config/am261x/r5f
+            -I${MCU_PLUS_SDK_PATH}/source/pru_io/driver
+            -I${WORKSPACE_LOC}/spi_10mhz_am261x-lp_icss_m1_pru0_fw_ti-pru-cgt
+            -I${WORKSPACE_LOC}/spi_10mhz_am261x-lp_icss_m1_pru1_fw_ti-pru-cgt
+            -mcpu=cortex-r5
+            -mfloat-abi=hard
+            -mfpu=vfpv3-d16
+            -mthumb
+            -Wall
+            -Werror
+            -g
+            -Wno-gnu-variable-sized-type-not-at-end
+            -Wno-unused-function
+            -DSOC_AM261X
+            -DOS_FREERTOS
+        "
+        linkerBuildOptions="
+            -i${MCU_PLUS_SDK_PATH}/source/kernel/freertos/lib
+            -i${MCU_PLUS_SDK_PATH}/source/drivers/lib
+            -i${MCU_PLUS_SDK_PATH}/source/board/lib
+            -i${MCU_PLUS_SDK_PATH}/source/pru_io/lib
+            -i${CG_TOOL_ROOT}/lib
+            -m=spi_10mhz.${ConfigName}.map
+            --diag_suppress=10063
+            --ram_model
+            --reread_libs
+            --gen_xml_func_hash
+        "
+
+        postBuildStep="$(MAKE) -C ${CCS_PROJECT_DIR} -f makefile_ccs_bootimage_gen OUTNAME=${BuildArtifactFileBaseName} PROFILE=${ConfigName} MCU_PLUS_SDK_PATH=${MCU_PLUS_SDK_PATH} PRU_NO_CODE_TOOL_PATH=${PRU_NO_CODE_TOOL_PATH} CG_TOOL_ROOT=${CG_TOOL_ROOT} CCS_INSTALL_DIR=${CCS_INSTALL_DIR} CCS_IDE_MODE=${CCS_IDE_MODE} DEVICE=am261x"
+
+        enableSysConfigTool="true"
+        sysConfigBuildOptions="
+            --context r5fss0-0 --part AM2612 --package ZFG
+        "
+
+        description="A Empty Pru FREERTOS project">
+
+        <!-- PRU firmware headers are generated into each PRU project's
+             workspace folder by the postBuildStep. The paths in
+             compilerBuildOptions above assume PRU projects are imported
+             with their default names. If you rename a PRU project in CCS,
+             update the matching -I${WORKSPACE_LOC}/... path above. -->
+        <configuration name="Debug"
+            compilerBuildOptions="
+                -D_DEBUG_=1
+            "
+            linkerBuildOptions="
+                -lfreertos.am261x.r5f.ti-arm-clang.debug.lib
+                -ldrivers.am261x.r5f.ti-arm-clang.freertos.debug.lib
+                -lboard.am261x.r5f.ti-arm-clang.freertos.debug.lib
+                -llibc.a
+                -llibsysbm.a
+            "
+        ></configuration>
+        <configuration name="Release"
+            compilerBuildOptions="
+                -Os
+            "
+            linkerBuildOptions="
+                -lfreertos.am261x.r5f.ti-arm-clang.release.lib
+                -ldrivers.am261x.r5f.ti-arm-clang.freertos.release.lib
+                -lboard.am261x.r5f.ti-arm-clang.freertos.release.lib
+                -llibc.a
+                -llibsysbm.a
+            "
+        ></configuration>
+        <pathVariable name="MCU_PLUS_SDK_PATH" path="${COM_TI_MCU_PLUS_SDK_AM261X_INSTALL_DIR}" scope="project" />
+        <pathVariable name="PRU_NO_CODE_TOOL_PATH" path="${COM_TI_PRU_NO_CODE_TOOL_INSTALL_DIR}" scope="project" />
+        <file path="../main.c" openOnCreation="false" excludeFromBuild="false" action="copy">
+        </file>
+        <file path="../../../empty_example.c" openOnCreation="false" excludeFromBuild="false" action="copy">
+        </file>
+        <file path="../example.syscfg" openOnCreation="false" excludeFromBuild="false" action="copy">
+        </file>
+        <file path="syscfg_c.rov.xs" openOnCreation="false" excludeFromBuild="false" action="copy">
+        </file>
+        <file path="makefile_ccs_bootimage_gen" openOnCreation="false" excludeFromBuild="false" action="copy">
+        </file>
+    </project>
+</projectSpec>
diff --git a/examples/spi_10mhz/mcuplus/am261x-lp/r5fss0-0_freertos/ti-arm-clang/makefile b/examples/spi_10mhz/mcuplus/am261x-lp/r5fss0-0_freertos/ti-arm-clang/makefile
new file mode 100644
index 0000000..fbca04d
--- /dev/null
+++ b/examples/spi_10mhz/mcuplus/am261x-lp/r5fss0-0_freertos/ti-arm-clang/makefile
@@ -0,0 +1,336 @@
+#
+# Auto generated makefile
+#
+
+export PRU_NO_CODE_TOOL_PATH?=$(abspath ../../../../../..)
+include $(PRU_NO_CODE_TOOL_PATH)/imports.mak
+include $(MCU_PLUS_SDK_PATH)/devconfig/devconfig.mak
+
+
+CG_TOOL_ROOT=$(CGT_TI_ARM_CLANG_PATH)
+
+CC=$(CG_TOOL_ROOT)/bin/tiarmclang
+LNK=$(CG_TOOL_ROOT)/bin/tiarmclang
+STRIP=$(CG_TOOL_ROOT)/bin/tiarmstrip
+OBJCOPY=$(CG_TOOL_ROOT)/bin/tiarmobjcopy
+COV=$(CG_TOOL_ROOT)/bin/tiarmcov
+PROFDATA=$(CG_TOOL_ROOT)/bin/tiarmprofdata
+COVERAGE_PATH=$(abspath .)
+ifeq ($(OS), Windows_NT)
+	PYTHON=python
+else
+	PYTHON=python3
+endif
+
+PROFILE?=release
+ConfigName:=$(PROFILE)
+
+OUTNAME:=spi_10mhz.$(PROFILE).out
+COREOUTNAME:=spi_10mhz.$(PROFILE).optishare.out
+
+BOOTIMAGE_PATH=$(abspath .)
+oeconfig?=None
+
+BOOTIMAGE_NAME_MCELF:=spi_10mhz.$(PROFILE).mcelf
+BOOTIMAGE_NAME_MCELF_HS:=spi_10mhz.$(PROFILE).mcelf.hs
+TARGETS := $(BOOTIMAGE_NAME_MCELF)
+
+ifeq ($(DEVICE_TYPE), HS)
+   TARGETS += $(BOOTIMAGE_NAME_MCELF_HS)
+endif
+
+
+FILES_common := \
+	main.c \
+	empty_example.c \
+	ti_drivers_config.c \
+	ti_drivers_open_close.c \
+	ti_board_config.c \
+	ti_board_open_close.c \
+	ti_dpl_config.c \
+	ti_pinmux_config.c \
+	ti_power_clock_config.c \
+
+FILES_PATH_common = \
+	.. \
+	../../.. \
+	generated \
+
+INCLUDES_common := \
+	-I${CG_TOOL_ROOT}/include/c \
+	-I${MCU_PLUS_SDK_PATH}/source \
+	-I${MCU_PLUS_SDK_PATH}/source/kernel/freertos/FreeRTOS-Kernel/include \
+	-I${MCU_PLUS_SDK_PATH}/source/kernel/freertos/portable/TI_ARM_CLANG/ARM_CR5F \
+	-I${MCU_PLUS_SDK_PATH}/source/kernel/freertos/config/am261x/r5f \
+	-I${MCU_PLUS_SDK_PATH}/source/pru_io/driver \
+	-I${PRU_NO_CODE_TOOL_PATH}/examples/spi_10mhz/firmware/am261x-lp \
+	-Igenerated \
+
+DEFINES_common := \
+	-DSOC_AM261X \
+	-DOS_FREERTOS \
+
+CFLAGS_common := \
+	-mcpu=cortex-r5 \
+	-mfloat-abi=hard \
+	-mfpu=vfpv3-d16 \
+	-mthumb \
+	-Wall \
+	-Werror \
+	-g \
+	-Wno-gnu-variable-sized-type-not-at-end \
+	-Wno-unused-function \
+
+CFLAGS_cpp_common := \
+	-Wno-c99-designator \
+	-Wno-extern-c-compat \
+	-Wno-c++11-narrowing \
+	-Wno-reorder-init-list \
+	-Wno-register \
+	-Wno-writable-strings \
+	-Wno-enum-compare \
+	-Wno-reserved-user-defined-literal \
+	-Wno-unused-const-variable \
+	-Wno-vla-cxx-extension \
+	-x c++ \
+
+CFLAGS_debug := \
+	-D_DEBUG_=1 \
+
+CFLAGS_release := \
+	-Os \
+
+LNK_FILES_common = \
+	generated/linker.cmd \
+
+LIBS_PATH_common = \
+	-Wl,-i${MCU_PLUS_SDK_PATH}/source/kernel/freertos/lib \
+	-Wl,-i${MCU_PLUS_SDK_PATH}/source/drivers/lib \
+	-Wl,-i${MCU_PLUS_SDK_PATH}/source/board/lib \
+	-Wl,-i${MCU_PLUS_SDK_PATH}/source/pru_io/lib \
+	-Wl,-i${CG_TOOL_ROOT}/lib \
+
+LIBS_common = \
+	-lfreertos.am261x.r5f.ti-arm-clang.${ConfigName}.lib \
+	-ldrivers.am261x.r5f.ti-arm-clang.freertos.${ConfigName}.lib \
+	-lboard.am261x.r5f.ti-arm-clang.freertos.${ConfigName}.lib \
+	-llibc.a \
+	-llibsysbm.a \
+
+LFLAGS_common = \
+	-Wl,--diag_suppress=10063 \
+	-Wl,--ram_model \
+	-Wl,--reread_libs \
+	-Wl,--gen_xml_func_hash \
+
+
+LIBS_NAME = \
+	freertos.am261x.r5f.ti-arm-clang.${ConfigName}.lib \
+	drivers.am261x.r5f.ti-arm-clang.freertos.${ConfigName}.lib \
+	board.am261x.r5f.ti-arm-clang.freertos.${ConfigName}.lib \
+	libc.a \
+	libsysbm.a \
+
+LIBS_PATH_NAME = \
+	${MCU_PLUS_SDK_PATH}/source/kernel/freertos/lib \
+	${MCU_PLUS_SDK_PATH}/source/drivers/lib \
+	${MCU_PLUS_SDK_PATH}/source/board/lib \
+	${MCU_PLUS_SDK_PATH}/source/pru_io/lib \
+	${CG_TOOL_ROOT}/lib \
+
+FILES := $(FILES_common) $(FILES_$(PROFILE))
+ASMFILES := $(ASMFILES_common) $(ASMFILES_$(PROFILE))
+FILES_PATH := $(FILES_PATH_common) $(FILES_PATH_$(PROFILE))
+CFLAGS := $(CFLAGS_common) $(CFLAGS_$(PROFILE))
+ifeq ($(INSTRUMENTATION_MODE), yes)
+CFLAGS += -fprofile-instr-generate -fcoverage-mapping
+endif
+DEFINES := $(DEFINES_common) $(DEFINES_$(PROFILE))
+INCLUDES := $(INCLUDES_common) $(INCLUDE_$(PROFILE))
+LIBS := $(LIBS_common) $(LIBS_$(PROFILE))
+LIBS_PATH := $(LIBS_PATH_common) $(LIBS_PATH_$(PROFILE))
+LFLAGS := $(LFLAGS_common) $(LFLAGS_$(PROFILE))
+LNKOPTFLAGS := $(LNKOPTFLAGS_common) $(LNKOPTFLAGS_$(PROFILE))
+LNK_FILES := $(LNK_FILES_common) $(LNK_FILES_$(PROFILE))
+
+OBJDIR := obj/$(PROFILE)/
+OBJS := $(FILES:%.c=%.obj)
+OBJS += $(ASMFILES:%.S=%.obj)
+DEPS := $(FILES:%.c=%.d)
+
+vpath %.obj $(OBJDIR)
+vpath %.c $(FILES_PATH)
+vpath %.S $(FILES_PATH)
+vpath %.lib $(LIBS_PATH_NAME)
+vpath %.a $(LIBS_PATH_NAME)
+
+$(OBJDIR)/%.obj %.obj: %.c
+	@echo  Compiling: am261x:r5fss0-0:freertos:ti-arm-clang $(OUTNAME): $<
+	$(CC) -c $(CFLAGS) $(INCLUDES) $(DEFINES) -MMD -o $(OBJDIR)/$@ $<
+
+$(OBJDIR)/%.obj %.obj: %.S
+	@echo  Compiling: am261x:r5fss0-0:freertos:ti-arm-clang $(LIBNAME): $<
+	$(CC) -c $(CFLAGS) $(INCLUDES) $(DEFINES) -o $(OBJDIR)/$@ $<
+
+all: $(TARGETS)
+
+SYSCFG_GEN_FILES=generated/ti_drivers_config.c generated/ti_drivers_config.h
+SYSCFG_GEN_FILES+=generated/ti_drivers_open_close.c generated/ti_drivers_open_close.h
+SYSCFG_GEN_FILES+=generated/ti_dpl_config.c generated/ti_dpl_config.h
+SYSCFG_GEN_FILES+=generated/ti_pinmux_config.c generated/ti_power_clock_config.c
+SYSCFG_GEN_FILES+=generated/ti_board_config.c generated/ti_board_config.h
+SYSCFG_GEN_FILES+=generated/ti_board_open_close.c generated/ti_board_open_close.h
+
+SYSTEM_FLAG ?= false
+
+ifeq ($(SYSTEM_FLAG), false)
+	SYSTEM_COMMAND := syscfg $(SYSCFG_GEN_FILES) $(OBJS) $(LNK_FILES) $(LIBS_NAME)
+else
+	SYSTEM_COMMAND := $(OBJS) $(LNK_FILES) $(LIBS_NAME)
+endif
+
+$(OUTNAME):  $(SYSTEM_COMMAND)
+	@echo  .
+	@echo  Linking: am261x:r5fss0-0:freertos:ti-arm-clang $@ ...
+	$(LNK) $(LNKOPTFLAGS) $(LFLAGS) $(LIBS_PATH) -Wl,-m=$(basename $@).map -o $@ $(addprefix $(OBJDIR), $(OBJS)) $(LIBS) $(LNK_FILES) -Wl,--xml_link_info=$(basename $@).lnkxml
+	@echo  Linking: am261x:r5fss0-0:freertos:ti-arm-clang $@ Done !!!
+	@echo  .
+
+coreout: $(COREOUTNAME)
+$(COREOUTNAME):  $(SYSTEM_COMMAND)
+	@echo  .
+	@echo  Relinking Linking: am261x:r5fss0-0:freertos:ti-arm-clang $@ with OptiShare SSO..
+	$(LNK) $(LNKOPTFLAGS) $(LFLAGS) $(LIBS_PATH) -Wl,-m=$(basename $@).map -o $@ $(addprefix $(OBJDIR), $(OBJS)) $(LIBS) $(LNK_FILES) -Wl,--xml_link_info=$(basename $@).lnkxml -Wl,--import_sso=$(SSO_PATH)
+	@echo  Relinking with optishare: am261x:r5fss0-0:freertos:ti-arm-clang $@ Done !!!
+	@echo  .
+
+clean:
+	@echo  Cleaning: am261x:r5fss0-0:freertos:ti-arm-clang $(OUTNAME) ...
+	$(RMDIR) $(OBJDIR)
+	$(RM) $(OUTNAME)
+	$(RM) $(BOOTIMAGE_NAME_MCELF)
+	$(RM) $(BOOTIMAGE_NAME_MCELF_HS)
+	$(RMDIR) generated/
+
+scrub:
+	@echo  Scrubing: am261x:r5fss0-0:freertos:ti-arm-clang spi_10mhz ...
+	$(RMDIR) obj
+ifeq ($(OS),Windows_NT)
+	$(RM) \*.out
+	$(RM) \*.map
+	$(RM) \*.appimage*
+	$(RM) \*.rprc*
+	$(RM) \*.tiimage*
+	$(RM) \*.bin
+	$(RM) \*.lnkxml
+	$(RM) \*.ossr
+	$(RM) \*.mcelf
+	$(RM) \*.mcelf_xip
+	$(RM) \*.mcelf-enc
+	$(RM) \*.mcelf.hs
+else
+	$(RM) *.out
+	$(RM) *.map
+	$(RM) *.appimage*
+	$(RM) *.rprc*
+	$(RM) *.tiimage*
+	$(RM) *.bin
+	$(RM) *.lnkxml
+	$(RM) *.ossr
+	$(RM) *.mcelf
+	$(RM) *.mcelf_xip
+	$(RM) *.mcelf-enc
+	$(RM) *.mcelf.hs
+endif
+	$(RMDIR) generated
+
+$(OBJS): | $(OBJDIR)
+
+$(OBJDIR):
+	$(MKDIR) $@
+
+
+.NOTPARALLEL:
+
+.INTERMEDIATE: syscfg
+$(SYSCFG_GEN_FILES): syscfg
+
+ifeq ($(SYSTEM_FLAG), false)
+syscfg: ../example.syscfg
+	@echo Generating SysConfig files ...
+	$(SYSCFG_NODE) $(SYSCFG_CLI_PATH)/dist/cli.js --product $(SYSCFG_PRU_NO_TOOL_PRODUCT) --product $(SYSCFG_MCU_PLUS_SDK_PRODUCT) --context r5fss0-0 --part ALX --package ALX --output generated/ ../example.syscfg
+endif
+
+syscfg-gui:
+	$(SYSCFG_NWJS) $(SYSCFG_PATH) --product $(SYSCFG_PRU_NO_TOOL_PRODUCT) --product $(SYSCFG_MCU_PLUS_SDK_PRODUCT) --device AM261x_ALX_beta --context r5fss0-0 --part 2612 --package ZFG --output generated/  ../example.syscfg
+
+#
+# Generation of boot image which can be loaded by Secondary Boot Loader (SBL)
+#
+ifeq ($(OS),Windows_NT)
+EXE_EXT=.exe
+endif
+ifeq ($(OS),Windows_NT)
+  BOOTIMAGE_CERT_GEN_CMD=powershell -executionpolicy unrestricted -command $(MCU_PLUS_SDK_PATH)/source/security/security_common/tools/boot/signing/x509CertificateGen.ps1
+else
+  BOOTIMAGE_CERT_GEN_CMD=$(MCU_PLUS_SDK_PATH)/source/security/security_common/tools/boot/signing/x509CertificateGen.sh
+endif
+BOOTIMAGE_TEMP_OUT_FILE=temp_stdout_$(PROFILE).txt
+
+BOOTIMAGE_CERT_KEY=$(APP_SIGNING_KEY)
+
+BOOTIMAGE_CORE_ID_r5fss0-0 = 0
+BOOTIMAGE_CORE_ID_r5fss0-1 = 1
+BOOTIMAGE_CORE_ID_r5fss1-0 = 2
+BOOTIMAGE_CORE_ID_r5fss1-1 = 3
+SBL_RUN_ADDRESS=0x70002000
+SBL_DEV_ID=55
+
+APP_IMAGE_SIGN_CMD = $(MCU_PLUS_SDK_PATH)/source/security/security_common/tools/boot/signing/mcu_appimage_x509_cert_gen.py
+MCELF_IMAGE_GEN = $(MCU_PLUS_SDK_PATH)/tools/boot/multicore-elf/genimage.py
+
+$(BOOTIMAGE_NAME_MCELF): $(OUTNAME)
+	@echo  Boot MulticoreELF image: $(BOOTIMAGE_PATH)/$(BOOTIMAGE_NAME_MCELF) ...
+	$(PYTHON) $(MCELF_IMAGE_GEN) --core-img=$(BOOTIMAGE_CORE_ID_r5fss0-0):$(OUTNAME) --output=$(BOOTIMAGE_NAME_MCELF) --merge-segments=$(MCELF_MERGE_SEGMENTS_FLAG) --tolerance-limit=$(MCELF_MERGE_SEGMENTS_TOLERANCE_LIMIT) --ignore-context=$(MCELF_IGNORE_CONTEXT_FLAG) --xip=$(MCELF_XIP_RANGE) --xlat=$(MCELF_ADDR_TRANSLATION_PATH) --max-segment-size=$(MCELF_MAX_SEGMENT_SIZE) --otfaConfigFile=$(oeconfig)
+	@echo  Boot MulticoreELF image: $(BOOTIMAGE_PATH)/$(BOOTIMAGE_NAME_MCELF) Done !!!
+	@echo  .
+
+$(BOOTIMAGE_NAME_MCELF_HS): $(BOOTIMAGE_NAME_MCELF)
+ifeq ($(DEVICE_TYPE), HS)
+# Sign the appimage using appimage signing script
+ifeq ($(ENC_ENABLED),no)
+ifeq ($(RSASSAPSS_ENABLED),no)
+	@echo Boot image signing: Encryption is disabled.
+	$(PYTHON) $(APP_IMAGE_SIGN_CMD) --bin $(BOOTIMAGE_NAME_MCELF) --key $(APP_SIGNING_KEY) --sign_key_id $(APP_SIGNING_KEY_KEYRING_ID) --hash_algo $(APP_SIGNING_HASH_ALGO) --output $(BOOTIMAGE_NAME_MCELF_HS)
+else
+	@echo Boot image signing: Encryption is disabled. RSASSAPSS is enabled.
+	$(PYTHON) $(APP_IMAGE_SIGN_CMD) --bin $(BOOTIMAGE_NAME_MCELF) --key $(APP_SIGNING_KEY) --sign_key_id $(APP_SIGNING_KEY_KEYRING_ID) --hash_algo $(APP_SIGNING_HASH_ALGO) --pss_saltlen $(APP_SIGNING_SALT_LENGTH) --output $(BOOTIMAGE_NAME_MCELF_HS) --rsassa_pss
+endif
+else
+ifeq ($(RSASSAPSS_ENABLED),no)
+	@echo Boot image signing: Encryption is enabled.
+	$(PYTHON) $(APP_IMAGE_SIGN_CMD) --bin $(BOOTIMAGE_NAME_MCELF) --key $(APP_SIGNING_KEY) --enc y --enckey $(APP_ENCRYPTION_KEY) --kd-salt $(KD_SALT) --sign_key_id $(APP_SIGNING_KEY_KEYRING_ID) --enc_key_id $(APP_ENCRYPTION_KEY_KEYRING_ID) --hash_algo $(APP_SIGNING_HASH_ALGO) --output $(BOOTIMAGE_NAME_MCELF_HS)
+	$(RM) $(BOOTIMAGE_NAME_MCELF)-enc
+else
+	@echo Boot image signing: Encryption is enabled. RSASSAPSS is enabled.
+	$(PYTHON) $(APP_IMAGE_SIGN_CMD) --bin $(BOOTIMAGE_NAME_MCELF) --key $(APP_SIGNING_KEY) --enc y --enckey $(APP_ENCRYPTION_KEY) --kd-salt $(KD_SALT) --sign_key_id $(APP_SIGNING_KEY_KEYRING_ID) --enc_key_id $(APP_ENCRYPTION_KEY_KEYRING_ID) --hash_algo $(APP_SIGNING_HASH_ALGO) --pss_saltlen $(APP_SIGNING_SALT_LENGTH) --output $(BOOTIMAGE_NAME_MCELF_HS) --rsassa_pss
+	$(RM) $(BOOTIMAGE_NAME_MCELF)-enc
+endif
+endif
+	@echo  Boot image: am261x:r5fss0-0:freertos:ti-arm-clang $(BOOTIMAGE_PATH)/$(BOOTIMAGE_NAME_MCELF_HS) Done !!!
+	@echo  .
+endif
+
+
+
+.PHONY: coverage
+coverage:
+	@echo Creating Coverage Report for spi_10mhz.$(PROFILE) ...
+	$(MKDIR) coverage
+	$(PROFDATA) merge -sparse -obj-file=$(OUTNAME) $(OUTNAME).cnt -o spi_10mhz.$(PROFILE).profdata
+	$(COV) show --format=html --show-expansions --show-instantiations --show-branches=count --object=$(OUTNAME) -instr-profile=spi_10mhz.$(PROFILE).profdata --output-dir=$(COVERAGE_PATH)/coverage --ignore-filename-regex=build_jenkins
+	$(COV) export --format=text --object=$(OUTNAME) --instr-profile=spi_10mhz.$(PROFILE).profdata > coverage/spi_10mhz.$(PROFILE).profdata.json
+	node $(MCU_PLUS_SDK_PATH)/tools/smart_placement/clang_coverage_analyse.js --input=coverage/spi_10mhz.$(PROFILE).profdata.json --output-json=coverage/spi_10mhz.$(PROFILE).analysis.json --output=../spi_10mhz.annotations.$(PROFILE).S --top-function-count=500
+	@echo Coverage Report Generated at $(COVERAGE_PATH)/coverage folder !!!
+
+-include $(addprefix $(OBJDIR)/, $(DEPS))
diff --git a/examples/spi_10mhz/mcuplus/am261x-lp/r5fss0-0_freertos/ti-arm-clang/makefile.defs b/examples/spi_10mhz/mcuplus/am261x-lp/r5fss0-0_freertos/ti-arm-clang/makefile.defs
new file mode 100644
index 0000000..4f41ac3
--- /dev/null
+++ b/examples/spi_10mhz/mcuplus/am261x-lp/r5fss0-0_freertos/ti-arm-clang/makefile.defs
@@ -0,0 +1,14 @@
+GEN_FILES__QUOTED += \
+*.appimage* \
+*.appimage_xip \
+*.rprc* \
+*.rprc_xip \
+*.tiimage* \
+*.bin \
+*.lnkxml \
+*.map \
+*.ossr
+
+GEN_FILES__QUOTED += \
+*.mcelf* \
+*.mcelf_xip
diff --git a/examples/spi_10mhz/mcuplus/am261x-lp/r5fss0-0_freertos/ti-arm-clang/makefile_ccs_bootimage_gen b/examples/spi_10mhz/mcuplus/am261x-lp/r5fss0-0_freertos/ti-arm-clang/makefile_ccs_bootimage_gen
new file mode 100644
index 0000000..93f08ca
--- /dev/null
+++ b/examples/spi_10mhz/mcuplus/am261x-lp/r5fss0-0_freertos/ti-arm-clang/makefile_ccs_bootimage_gen
@@ -0,0 +1,95 @@
+#
+# Auto generated makefile
+#
+
+# Below variables need to be defined outside this file or via command line
+# - PRU_NO_CODE_TOOL_PATH
+# - MCU_PLUS_SDK_PATH
+# - PROFILE
+# - CG_TOOL_ROOT
+# - OUTNAME
+# - CCS_INSTALL_DIR
+# - CCS_IDE_MODE
+
+CCS_PATH=$(CCS_INSTALL_DIR)
+include $(MCU_PLUS_SDK_PATH)/imports.mak
+include $(MCU_PLUS_SDK_PATH)/devconfig/devconfig.mak
+
+STRIP=$(CG_TOOL_ROOT)/bin/tiarmstrip
+OBJCOPY=$(CG_TOOL_ROOT)/bin/tiarmobjcopy
+ifeq ($(OS), Windows_NT)
+	PYTHON=python
+else
+	PYTHON=python3
+endif
+
+OUTFILE=$(PROFILE)/$(OUTNAME).out
+BOOTIMAGE_PATH=$(abspath ${PROFILE})
+BOOTIMAGE_NAME_MCELF:=$(BOOTIMAGE_PATH)/$(OUTNAME).mcelf
+BOOTIMAGE_NAME_MCELF_HS:=$(BOOTIMAGE_PATH)/$(OUTNAME).mcelf.hs
+TARGETS += $(BOOTIMAGE_NAME_MCELF)
+TARGETS += $(BOOTIMAGE_NAME_MCELF_HS)
+ifeq ($(DEVICE_TYPE), HS)
+   TARGETS += $(BOOTIMAGE_NAME_MCELF_HS)
+endif
+
+#
+# Generation of boot image which can be loaded by Secondary Boot Loader (SBL)
+#
+ifeq ($(OS),Windows_NT)
+EXE_EXT=.exe
+endif
+ifeq ($(OS),Windows_NT)
+  BOOTIMAGE_CERT_GEN_CMD=powershell -executionpolicy unrestricted -command $(MCU_PLUS_SDK_PATH)/source/security/security_common/tools/boot/signing/x509CertificateGen.ps1
+else
+  BOOTIMAGE_CERT_GEN_CMD=$(MCU_PLUS_SDK_PATH)/source/security/security_common/tools/boot/signing/x509CertificateGen.sh
+endif
+BOOTIMAGE_TEMP_OUT_FILE=$(PROFILE)/temp_stdout_$(PROFILE).txt
+
+BOOTIMAGE_CORE_ID_r5fss0-0 = 0
+BOOTIMAGE_CORE_ID_r5fss0-1 = 1
+BOOTIMAGE_CORE_ID_r5fss1-0 = 2
+BOOTIMAGE_CORE_ID_r5fss1-1 = 3
+SBL_RUN_ADDRESS=0x70002000
+SBL_DEV_ID=55
+
+APP_IMAGE_SIGN_CMD = $(MCU_PLUS_SDK_PATH)/source/security/security_common/tools/boot/signing/mcu_appimage_x509_cert_gen.py
+MCELF_IMAGE_GEN = $(MCU_PLUS_SDK_PATH)/tools/boot/multicore-elf/genimage.py
+
+all:
+ifeq ($(CCS_IDE_MODE),cloud)
+#	No post build steps
+else
+
+	@echo  Boot multi-core ELF image: am261x:r5fss0-0:freertos:ti-arm-clang $(BOOTIMAGE_NAME_MCELF) ...
+
+	$(PYTHON) $(MCELF_IMAGE_GEN) --core-img=$(BOOTIMAGE_CORE_ID_r5fss0-0):$(OUTFILE) --output=$(BOOTIMAGE_NAME_MCELF) --merge-segments=$(MCELF_MERGE_SEGMENTS_FLAG) --tolerance-limit=$(MCELF_MERGE_SEGMENTS_TOLERANCE_LIMIT) --ignore-context=$(MCELF_IGNORE_CONTEXT_FLAG) --xip=$(MCELF_XIP_RANGE) --xlat=$(MCELF_ADDR_TRANSLATION_PATH) --max-segment-size=$(MCELF_MAX_SEGMENT_SIZE)
+
+	@echo  Boot multi-core ELF image: $(BOOTIMAGE_NAME_MCELF) Done !!!
+	@echo  .
+
+ifeq ($(DEVICE_TYPE), HS)
+# Sign the appimage using appimage signing script
+ifeq ($(ENC_ENABLED),no)
+ifeq ($(RSASSAPSS_ENABLED),no)
+	@echo Boot image signing: Encryption is disabled.
+	$(PYTHON) $(APP_IMAGE_SIGN_CMD) --bin $(BOOTIMAGE_NAME_MCELF) --key $(APP_SIGNING_KEY) --sign_key_id $(APP_SIGNING_KEY_KEYRING_ID) --hash_algo $(APP_SIGNING_HASH_ALGO) --output $(BOOTIMAGE_NAME_MCELF_HS)
+else
+	@echo Boot image signing: Encryption is disabled. RSASSA-PSS is enabled.
+	$(PYTHON) $(APP_IMAGE_SIGN_CMD) --bin $(BOOTIMAGE_NAME_MCELF) --key $(APP_SIGNING_KEY) --sign_key_id $(APP_SIGNING_KEY_KEYRING_ID) --hash_algo $(APP_SIGNING_HASH_ALGO) --pss_saltlen $(APP_SIGNING_SALT_LENGTH) --output $(BOOTIMAGE_NAME_MCELF_HS) --rsassa_pss
+endif
+else
+ifeq ($(RSASSAPSS_ENABLED),no)
+	@echo Boot image signing: Encryption is enabled.
+	$(PYTHON) $(APP_IMAGE_SIGN_CMD) --bin $(BOOTIMAGE_NAME_MCELF) --key $(APP_SIGNING_KEY) --enc y --enckey $(APP_ENCRYPTION_KEY) --kd-salt $(KD_SALT) --sign_key_id $(APP_SIGNING_KEY_KEYRING_ID) --enc_key_id $(APP_ENCRYPTION_KEY_KEYRING_ID) --hash_algo $(APP_SIGNING_HASH_ALGO) --output $(BOOTIMAGE_NAME_MCELF_HS)
+	$(RM) $(BOOTIMAGE_NAME_MCELF)-enc
+else
+	@echo Boot image signing: Encryption is enabled. RSASSA-PSS is enabled.
+	$(PYTHON) $(APP_IMAGE_SIGN_CMD) --bin $(BOOTIMAGE_NAME_MCELF) --key $(APP_SIGNING_KEY) --enc y --enckey $(APP_ENCRYPTION_KEY) --kd-salt $(KD_SALT) --sign_key_id $(APP_SIGNING_KEY_KEYRING_ID) --enc_key_id $(APP_ENCRYPTION_KEY_KEYRING_ID) --hash_algo $(APP_SIGNING_HASH_ALGO) --pss_saltlen $(APP_SIGNING_SALT_LENGTH) --output $(BOOTIMAGE_NAME_MCELF_HS) --rsassa_pss
+	$(RM) $(BOOTIMAGE_NAME_MCELF)-enc
+endif
+endif
+	@echo  Boot image: am261x:r5fss0-0:freertos:ti-arm-clang $(BOOTIMAGE_PATH)/$(BOOTIMAGE_NAME_MCELF_HS) Done !!!
+	@echo  .
+endif
+endif
diff --git a/examples/spi_10mhz/mcuplus/am261x-lp/r5fss0-0_freertos/ti-arm-clang/makefile_projectspec b/examples/spi_10mhz/mcuplus/am261x-lp/r5fss0-0_freertos/ti-arm-clang/makefile_projectspec
new file mode 100644
index 0000000..16cc4cd
--- /dev/null
+++ b/examples/spi_10mhz/mcuplus/am261x-lp/r5fss0-0_freertos/ti-arm-clang/makefile_projectspec
@@ -0,0 +1,16 @@
+export PRU_NO_CODE_TOOL_PATH?=$(abspath ../../../../../..)
+include $(PRU_NO_CODE_TOOL_PATH)/imports.mak
+
+PROFILE?=Release
+
+PROJECT_NAME=spi_10mhz_am261x-lp_r5fss0-0_freertos_ti-arm-clang
+
+all:
+	$(CCS_ECLIPSE) -noSplash -data $(PRU_NO_CODE_TOOL_PATH)/ccs_projects -application com.ti.ccstudio.apps.projectBuild -ccs.projects $(PROJECT_NAME) -ccs.configuration $(PROFILE)
+
+clean:
+	$(CCS_ECLIPSE) -noSplash -data $(PRU_NO_CODE_TOOL_PATH)/ccs_projects -application com.ti.ccstudio.apps.projectBuild -ccs.projects $(PROJECT_NAME) -ccs.configuration $(PROFILE) -ccs.clean
+
+export:
+	$(MKDIR) $(PRU_NO_CODE_TOOL_PATH)/ccs_projects
+	$(CCS_ECLIPSE) -noSplash -data $(PRU_NO_CODE_TOOL_PATH)/ccs_projects -application com.ti.ccstudio.apps.projectCreate -ccs.projectSpec example.projectspec -ccs.overwrite full
diff --git a/examples/spi_10mhz/mcuplus/am261x-lp/r5fss0-0_freertos/ti-arm-clang/syscfg_c.rov.xs b/examples/spi_10mhz/mcuplus/am261x-lp/r5fss0-0_freertos/ti-arm-clang/syscfg_c.rov.xs
new file mode 100644
index 0000000..f716f8e
--- /dev/null
+++ b/examples/spi_10mhz/mcuplus/am261x-lp/r5fss0-0_freertos/ti-arm-clang/syscfg_c.rov.xs
@@ -0,0 +1,12 @@
+/*
+ *  ======== syscfg_c.rov.xs ========
+ *  This file contains the information needed by the Runtime Object
+ *  View (ROV) tool.
+ */
+var crovFiles = [
+    "kernel/freertos/rov/FreeRTOS.rov.js",
+];
+
+var objectViewerFiles = [
+    "kernel/freertos/rov_theia/FreeRTOS_Theia.rov.js",
+];
diff --git a/examples/spi_10mhz/mcuplus/empty_example.c b/examples/spi_10mhz/mcuplus/empty_example.c
new file mode 100644
index 0000000..f7bff9c
--- /dev/null
+++ b/examples/spi_10mhz/mcuplus/empty_example.c
@@ -0,0 +1,86 @@
+/*
+ *  Copyright (C) 2024-2025 Texas Instruments Incorporated
+ *
+ *  Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions
+ *  are met:
+ *
+ *    Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *
+ *    Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the
+ *    distribution.
+ *
+ *    Neither the name of Texas Instruments Incorporated nor the names of
+ *    its contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ *  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ *  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ *  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ *  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ *  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ *  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ *  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ *  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ *  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <stdio.h>
+#include <kernel/dpl/DebugP.h>
+#include "ti_drivers_config.h"
+#include "ti_drivers_open_close.h"
+#include "ti_board_open_close.h"
+#include <drivers/pruicss.h>
+
+#include <pru0_load_bin.h>
+#include <pru1_load_bin.h>
+
+
+
+/*
+ *  This is an example project to show R5F
+ *  loading PRU firmware.
+ */
+
+/** \brief Global Structure pointer holding PRUSS1 memory Map. */
+
+PRUICSS_Handle gPruIcss0Handle;
+
+
+void empty_example_main(void *args)
+{
+     Drivers_open(); // check return status
+
+     int status;
+     status = Board_driversOpen();
+     DebugP_assert(SystemP_SUCCESS == status);
+
+     gPruIcss0Handle = PRUICSS_open(CONFIG_PRU_ICSS0);
+
+     status = PRUICSS_initMemory(gPruIcss0Handle, PRUICSS_DATARAM(PRUICSS_PRU0));
+     DebugP_assert(status != 0);
+
+     status = PRUICSS_initMemory(gPruIcss0Handle, PRUICSS_DATARAM(PRUICSS_PRU1));
+     DebugP_assert(status != 0);
+
+     status = PRUICSS_loadFirmware(gPruIcss0Handle, PRUICSS_PRU1, PRU1Firmware_0, sizeof(PRU1Firmware_0));
+     DebugP_assert(SystemP_SUCCESS == status);
+     DebugP_log("----- PRU1 Firmware loaded successfully. SPI Slave initialized. \r\n");
+     status = PRUICSS_loadFirmware(gPruIcss0Handle, PRUICSS_PRU0, PRU0Firmware_0, sizeof(PRU0Firmware_0));
+     DebugP_assert(SystemP_SUCCESS == status);
+     DebugP_log("----- PRU0 Firmware loaded successfully. SPI Master initialized. \r\n");
+     DebugP_log("----- Check register R0 of PRU0 to view the data recieved  \r\n");
+
+     while (1)
+     {
+        ClockP_usleep(1);
+     }
+
+     Board_driversClose();
+     Drivers_close();
+}
diff --git a/examples/spi_10mhz/readme.md b/examples/spi_10mhz/readme.md
new file mode 100644
index 0000000..991c308
--- /dev/null
+++ b/examples/spi_10mhz/readme.md
@@ -0,0 +1,169 @@
+# SPI Transfer at 10MHz
+
+## Introduction
+
+This example demonstrates the use of the PRU No-Code Tool to achieve a 10MHz SPI clock on the AM261x platform using a PRU core clock of 200MHz. PRU0 acts as the SPI controller using the **SPI Transfer block** (full-duplex) and PRU1 acts as the SPI peripheral using the **SPI Write block**.
+
+The purpose of this example is to validate both directions of the SPI Transfer block:
+- **TX path (PRU0 → PRU1)**: PRU0 transmits 32-bit data over SDO. Verified using a Saleae logic analyzer.
+- **RX path (PRU1 → PRU0)**: PRU1 emulates an encoder response by driving known data (0xDEADDEAD) back over its SDO using the SPI Write slave block, which PRU0 receives via its SDI pin. This allows the RX path of the SPI Transfer block to be validated without requiring actual encoder hardware.
+
+After running the example the data recieved by the SPI transfer block is stored in register **R0 of PRU0**
+
+SPI mode used: **MODE1** (CPOL=0, CPHA=1). All 4 modes are supported.
+
+<figure>
+<img src="images/spi_10mhz.png" alt="spi_10mhz" width="900">
+<figcaption>In the figure, white signal represent the clock (70ns high and 30ns low) and the red signal represent the data (1 bit = 10ns)</figcaption>
+</figure>
+
+---
+
+## Timing Configuration
+
+| Parameter | Value |
+|-----------|-------|
+| PRU clock | 200 MHz (AM261x ZFG 400MHz variant) |
+| SCLK high width | 14 PRU cycles |
+| SCLK low width | 6 PRU cycles |
+| SPI clock frequency | 200MHz / (14+6) = **10 MHz** |
+| Data setup time | 50 ns (10 PRU cycles) |
+| CS setup time | 500 ns |
+| CS hold time | 500 ns |
+
+> **Note:** The SCLK high width of 14 cycles is the minimum achievable with a 50ns data setup time requirement.
+> At 200MHz PRU clock: `ceil(50ns × 200/1000) = 10 cycles` data setup overhead, giving `high_min = 4 + 10 = 14 cycles`.
+
+---
+
+## No-Code Tool Block Design
+
+### PRU0 — SPI Controller (Transfer block)
+
+```
+[Load Constant: Load_Constant_0]     value = 0xABCDEFAB (32-bit data to transmit)
+        │
+        ▼
+[SPI Transfer: PRU0_SPI_Transfer_0]  full-duplex, controller mode, MODE1, 32-bit MSB first
+        │                            SCLK high = 14 cycles, low = 6 cycles → 10MHz
+        │                            Data setup = 50ns, CS setup = 500ns, CS hold = 500ns
+        │                            SCLK → GPO0, SDO → GPO1, SDI ← GPI6, CS → GPO2
+        ▼
+[Flow Control: Flow_Control_0]       HALT
+```
+
+### PRU1 — SPI Peripheral (Write block)
+
+```
+[Load Constant: Load_Constant_0]     value = 0xDEADDEAD (32-bit data to send back to controller)
+        │
+        ▼
+[SPI Write: PRU1_SPI_Write_0]        peripheral mode, MODE1, 32-bit MSB first
+        │                            waits for CS assert from PRU0, then sends data on SDO
+        │                            SCLK ← GPI4, SDI ← GPI5, SDO → GPO1, CS ← GPI6
+        ▼
+[Flow Control: Flow_Control_0]       HALT
+```
+
+---
+
+## Block Configuration Details
+
+### PRU0 Blocks
+
+**Load Constant (`Load_Constant_0`)**
+- Value: 2882400171 (0xABCDEFAB) — 32-bit test pattern to transmit
+
+**SPI Transfer (`PRU0_SPI_Transfer_0`)**
+- Packet size: 32 bits
+- Device mode: Controller
+- SPI mode: MODE1 (CPOL=0, CPHA=1)
+- Endianness: MSB first
+- SCLK high pulse width: 14 PRU cycles
+- SCLK low pulse width: 6 PRU cycles
+- Data setup time: 50ns
+- CS setup time: 500ns
+- CS hold time: 500ns
+- SCLK signal: GPO0
+- SDO signal: GPO1
+- SDI signal: GPI6
+- CS signal: GPO2
+
+**Flow Control (`Flow_Control_0`)**
+- Operation: HALT
+
+---
+
+### PRU1 Blocks
+
+**Load Constant (`Load_Constant_0`)**
+- Value: 3735936685 (0xDEADDEAD) — 32-bit test pattern PRU1 sends back to PRU0 to emulate the encoder response 
+
+**SPI Write (`PRU1_SPI_Write_0`)**
+- Packet size: 32 bits
+- Device mode: Peripheral
+- SPI mode: MODE1 (CPOL=0, CPHA=1)
+- Endianness: MSB first
+- SCLK signal: GPI4
+- SDI signal: GPI5
+- SDO signal: GPO1
+- CS signal: GPI6
+- CS filter cycles: 2
+
+**Flow Control (`Flow_Control_0`)**
+- Operation: HALT
+
+---
+
+## Pin Connections
+
+PRU0 drives SCLK and CS; both PRUs drive their respective SDO lines.
+
+| Signal | PRU0 pin (controller) | PRU1 pin (peripheral) |
+|--------|-----------------------|-----------------------|
+| SCLK | GPO0 | GPI4 |
+| SDO  | GPO1 | GPO5 |
+| SDI  | GPI6 | ---- |
+| CS | GPO2 | GPI6 |
+
+---
+
+## Why SPI Write slave instead of SPI Transfer slave?
+
+The SPI Transfer slave (full-duplex peripheral) has a practical maximum frequency of **7.69MHz at 200MHz PRU clock** due to the polling overhead of the software-based slave. The slave needs ~13 cycles minimum in both high and low phases to detect edges reliably.
+
+The SPI Write slave (TX only peripheral) relaxes the low phase constraint since it does not need to sample SDI, allowing the controller's low width to go down to 6 cycles. This enables the 10MHz clock while still validating the RX path of the controller's Transfer block.
+
+In this example the SPI Write slave on PRU1 serves as an **encoder emulator** — it sends back a fixed known pattern (0xDEADDEAD) to simulate the response a real encoder would send over SPI. This lets the RX path of the Transfer block be fully tested at 10MHz without needing actual encoder hardware connected.
+
+For a full bidirectional loopback at 200MHz PRU clock, use `high=13, low=13` giving **7.69MHz**. For 333MHz PRU clock (AM243x), the practical max is **12.8MHz** with `high=13, low=13`.
+
+---
+
+# Supported Combinations
+
+ Parameter      | Value
+ ---------------|-----------
+ ICSSM          | ICSSM1 - PRU0, PRU1 (am261x only)
+ Toolchain      | pru-cgt
+ Board          | am261x-lp
+ Example folder | examples/spi_10mhz/
+
+# Steps to Run the Example
+
+> Prerequisite: [PRU-CGT-2-3](https://www.ti.com/tool/PRU-CGT) (ti-pru-cgt) should be installed at: `C:/ti/`
+
+- **When using CCS projects to build**, import the CCS project from the above mentioned Example folder path for R5F and PRU. After this `main.asm`, `linker.cmd` files get copied to the CCS workspace of the PRU project. The `main.asm` contains sample code to halt the PRU program.
+
+     - Build the PRU project using the CCS project menu (see [for AM261x](https://software-dl.ti.com/mcu-plus-sdk/esd/AM261X/latest/exports/docs/api_guide_am261x/CCS_PROJECTS_PAGE.html)).
+          - Build Flow: Once you click on build in PRU project, the firmware header file generated in the release or debug folder of the CCS workspace is moved to `<pru-no-code-tool/examples/spi_10mhz/firmware/device/>`
+
+     - Build the R5F project using the CCS project menu (see [for AM261x](https://software-dl.ti.com/mcu-plus-sdk/esd/AM261X/latest/exports/docs/api_guide_am261x/CCS_PROJECTS_PAGE.html)).
+          - The firmware header file path is included in R5F project include options by default. Instructions in the firmware header file can be written into PRU IRAM memory using the PRUICSS_loadFirmware API.
+
+     - Launch a CCS debug session and run the executable (see [for AM261x](https://software-dl.ti.com/mcu-plus-sdk/esd/AM261X/latest/exports/docs/api_guide_am261x/CCS_LAUNCH_PAGE.html)).
+
+     - Connect the SPI controller and peripheral pins as per the pin connections table above.
+
+- **When using makefiles to build**:
+     - For steps on how to use makefiles, run `make help` from the root folder of the pru-no-code-tool repository.

From 34ae9c1a5053b9c8414123a2710d9e1ba69b77ad Mon Sep 17 00:00:00 2001
From: Ayushman <a-ayushman@ti.com>
Date: Tue, 21 Jul 2026 16:40:33 +0530
Subject: [PATCH 5/5] Update AM261x to latest MCU+ SDK and add new device
 variants

Bump am261x MCU+ SDK from 10.02.00.15 to 26.00.00.06 in CI workflows,
add AM261x_ZNC and AM261x_ZFG_400 device variants to product.json,
and regenerate CCS/makefile build files for all existing am261x-lp
examples against the new SDK.
---
 .github/workflows/ccs_build.yml               |   6 +-
 .github/workflows/makefile.yml                |   6 +-
 .metadata/product.json                        |  56 +++++++-
 .../pru_io_blocks/pru_spi_read.syscfg.js      |   8 +-
 .../pru_io_blocks/uart_tx_op.syscfg.js        |   2 +-
 .../ti-arm-clang/example.projectspec          |   8 +-
 .../r5fss0-0_freertos/ti-arm-clang/makefile   | 120 ++++++++---------
 .../ti-arm-clang/makefile.defs                |  14 ++
 .../ti-arm-clang/makefile_ccs_bootimage_gen   |  92 ++++++-------
 .../icss_g0_pru0_fw/ti-pru-cgt/makefile       |   1 +
 .../icss_g0_pru1_fw/ti-pru-cgt/makefile       |   1 +
 .../icss_g0_rtu_pru0_fw/ti-pru-cgt/makefile   |   1 +
 .../icss_g0_rtu_pru1_fw/ti-pru-cgt/makefile   |   1 +
 .../icss_g0_tx_pru0_fw/ti-pru-cgt/makefile    |   1 +
 .../icss_g0_tx_pru1_fw/ti-pru-cgt/makefile    |   1 +
 .../ti-arm-clang/example.projectspec          |   8 +-
 .../r5fss0-0_freertos/ti-arm-clang/makefile   | 122 ++++++++----------
 .../ti-arm-clang/makefile.defs                |  14 ++
 .../ti-arm-clang/makefile_ccs_bootimage_gen   |  93 ++++++-------
 .../ti-arm-clang/example.projectspec          |   8 +-
 .../r5fss0-0_freertos/ti-arm-clang/makefile   | 120 ++++++++---------
 .../ti-arm-clang/makefile.defs                |  14 ++
 .../ti-arm-clang/makefile_ccs_bootimage_gen   |  92 ++++++-------
 .../ti-arm-clang/example.projectspec          |   8 +-
 .../r5fss0-0_freertos/ti-arm-clang/makefile   | 120 ++++++++---------
 .../ti-arm-clang/makefile.defs                |  14 ++
 .../ti-arm-clang/makefile_ccs_bootimage_gen   |  92 ++++++-------
 .../ti-arm-clang/example.projectspec          |   2 +-
 .../r5fss0-0_freertos/ti-arm-clang/makefile   |   4 +-
 .../ti-arm-clang/makefile_ccs_bootimage_gen   |   2 +-
 .../ti-arm-clang/example.projectspec          |   8 +-
 .../r5fss0-0_freertos/ti-arm-clang/makefile   | 120 ++++++++---------
 .../ti-arm-clang/makefile.defs                |  14 ++
 .../ti-arm-clang/makefile_ccs_bootimage_gen   |  92 ++++++-------
 .../ti-arm-clang/example.projectspec          |   8 +-
 .../r5fss0-0_freertos/ti-arm-clang/makefile   | 120 ++++++++---------
 .../ti-arm-clang/makefile.defs                |  14 ++
 .../ti-arm-clang/makefile_ccs_bootimage_gen   |  92 ++++++-------
 38 files changed, 711 insertions(+), 788 deletions(-)
 create mode 100644 examples/conditional/mcuplus/am261x-lp/r5fss0-0_freertos/ti-arm-clang/makefile.defs
 create mode 100644 examples/empty/mcuplus/am261x-lp/r5fss0-0_freertos/ti-arm-clang/makefile.defs
 create mode 100644 examples/gray_encoder_4_bit/mcuplus/am261x-lp/r5fss0-0_freertos/ti-arm-clang/makefile.defs
 create mode 100644 examples/incremental_spi/mcuplus/am261x-lp/r5fss0-0_freertos/ti-arm-clang/makefile.defs
 create mode 100644 examples/spi_loopback/mcuplus/am261x-lp/r5fss0-0_freertos/ti-arm-clang/makefile.defs
 create mode 100644 examples/uart_crc/mcuplus/am261x-lp/r5fss0-0_freertos/ti-arm-clang/makefile.defs

diff --git a/.github/workflows/ccs_build.yml b/.github/workflows/ccs_build.yml
index 2aa3852..bfafe9d 100644
--- a/.github/workflows/ccs_build.yml
+++ b/.github/workflows/ccs_build.yml
@@ -158,9 +158,9 @@ jobs:
             sdk_installer: mcu_plus_sdk_am243x_11_02_00_24-linux-x64-installer.run
             sdk_url: https://dr-download.ti.com/software-development/software-development-kit-sdk/MD-ouHbHEm1PK/11.02.00.24/mcu_plus_sdk_am243x_11_02_00_24-linux-x64-installer.run
           - device: am261x
-            mcu_plus_sdk: mcu_plus_sdk_am261x_10_02_00_15
-            sdk_installer: mcu_plus_sdk_am261x_10_02_00_15-linux-x64-installer.run
-            sdk_url: https://dr-download.ti.com/software-development/software-development-kit-sdk/MD-h64OlWnQrg/10.02.00.15/mcu_plus_sdk_am261x_10_02_00_15-linux-x64-installer.run
+            mcu_plus_sdk: mcu_plus_sdk_am261x_26_00_00_06
+            sdk_installer: mcu_plus_sdk_am261x_26_00_00_06-linux-x64-installer.run
+            sdk_url: https://dr-download.ti.com/software-development/software-development-kit-sdk/MD-h64OlWnQrg/26.00.00.06.STS/mcu_plus_sdk_am261x_26_00_00_06-linux-x64-installer.run
           - device: am263px
             mcu_plus_sdk: mcu_plus_sdk_am263px_10_02_00_15
             sdk_installer: mcu_plus_sdk_am263px_10_02_00_15-linux-x64-installer.run
diff --git a/.github/workflows/makefile.yml b/.github/workflows/makefile.yml
index f831a5b..0202e9e 100644
--- a/.github/workflows/makefile.yml
+++ b/.github/workflows/makefile.yml
@@ -28,9 +28,9 @@ jobs:
             sdk_installer: mcu_plus_sdk_am243x_11_02_00_24-linux-x64-installer.run
             sdk_url: https://dr-download.ti.com/software-development/software-development-kit-sdk/MD-ouHbHEm1PK/11.02.00.24/mcu_plus_sdk_am243x_11_02_00_24-linux-x64-installer.run
           - device: am261x
-            mcu_plus_sdk: mcu_plus_sdk_am261x_10_02_00_15
-            sdk_installer: mcu_plus_sdk_am261x_10_02_00_15-linux-x64-installer.run
-            sdk_url: https://dr-download.ti.com/software-development/software-development-kit-sdk/MD-h64OlWnQrg/10.02.00.15/mcu_plus_sdk_am261x_10_02_00_15-linux-x64-installer.run
+            mcu_plus_sdk: mcu_plus_sdk_am261x_26_00_00_06
+            sdk_installer: mcu_plus_sdk_am261x_26_00_00_06-linux-x64-installer.run
+            sdk_url: https://dr-download.ti.com/software-development/software-development-kit-sdk/MD-h64OlWnQrg/26.00.00.06.STS/mcu_plus_sdk_am261x_26_00_00_06-linux-x64-installer.run
           - device: am263px
             mcu_plus_sdk: mcu_plus_sdk_am263px_10_02_00_15
             sdk_installer: mcu_plus_sdk_am263px_10_02_00_15-linux-x64-installer.run
diff --git a/.metadata/product.json b/.metadata/product.json
index bfab36d..9a1df29 100644
--- a/.metadata/product.json
+++ b/.metadata/product.json
@@ -14,7 +14,9 @@
         "AM243x_ALV_beta",
         "AM243x_ALX_beta",
         "AM261x_ZFG",
-        "AM261x_ZCZ"
+        "AM261x_ZCZ",
+        "AM261x_ZNC",
+        "AM261x_ZFG_400"
     ],
     "contexts": {
         "AM64x": [{
@@ -91,7 +93,32 @@
             "name": "icss_g1_tx_pru1",
             "targetdbId": "icss_g1_tx_pru1"
         }],
+        "AM261x_ZFG_400": [{
+            "name": "r5fss0-0",
+            "targetdbId": "Cortex_R5_0"
+        }, {
+            "name": "r5fss0-1",
+            "targetdbId": "Cortex_R5_1"
+        },{
+            "name": "icss_m0_pru0",
+            "targetdbId": "icss_m0_pru0"
+        },{
+            "name": "icss_m0_pru1",
+            "targetdbId": "icss_m0_pru1"
+        },{
+            "name": "icss_m1_pru0",
+            "targetdbId": "icss_m1_pru0"
+        },{
+            "name": "icss_m1_pru1",
+            "targetdbId": "icss_m1_pru1"
+        }],
         "AM261x_ZFG": [{
+            "name": "r5fss0-0",
+            "targetdbId": "Cortex_R5_0"
+        }, {
+            "name": "r5fss0-1",
+            "targetdbId": "Cortex_R5_1"
+        },{
             "name": "icss_m0_pru0",
             "targetdbId": "icss_m0_pru0"
         },{
@@ -105,6 +132,31 @@
             "targetdbId": "icss_m1_pru1"
         }],
         "AM261x_ZCZ": [{
+            "name": "r5fss0-0",
+            "targetdbId": "Cortex_R5_0"
+        }, {
+            "name": "r5fss0-1",
+            "targetdbId": "Cortex_R5_1"
+        },{
+            "name": "icss_m0_pru0",
+            "targetdbId": "icss_m0_pru0"
+        },{
+            "name": "icss_m0_pru1",
+            "targetdbId": "icss_m0_pru1"
+        },{
+            "name": "icss_m1_pru0",
+            "targetdbId": "icss_m1_pru0"
+        },{
+            "name": "icss_m1_pru1",
+            "targetdbId": "icss_m1_pru1"
+        }],
+        "AM261x_ZNC": [{
+            "name": "r5fss0-0",
+            "targetdbId": "Cortex_R5_0"
+        }, {
+            "name": "r5fss0-1",
+            "targetdbId": "Cortex_R5_1"
+        },{
             "name": "icss_m0_pru0",
             "targetdbId": "icss_m0_pru0"
         },{
@@ -153,7 +205,7 @@
         },{
             "name": "icss_g1_tx_pru1",
             "targetdbId": "icss_g1_tx_pru1"
-        }],
+        }]
     },
     "pinmuxUIOptions": {
         "group": "merged",
diff --git a/.metadata/sysconfig/.meta/pru_blocks/pru_io_blocks/pru_spi_read.syscfg.js b/.metadata/sysconfig/.meta/pru_blocks/pru_io_blocks/pru_spi_read.syscfg.js
index 4605174..81bd34c 100644
--- a/.metadata/sysconfig/.meta/pru_blocks/pru_io_blocks/pru_spi_read.syscfg.js
+++ b/.metadata/sysconfig/.meta/pru_blocks/pru_io_blocks/pru_spi_read.syscfg.js
@@ -1230,8 +1230,8 @@ exports = {
 				// HIGH half overhead: SET SCLK + sub (1) + dataSetup = 2 + dataSetup
 				else if (mode === "MODE1") value = high - 2 - dataSetup;
 
-				// MODE2: DATA_SETUP_TIME is in the HIGH half (before CLR SCLK sampling edge)
-				// HIGH half overhead: sub(1) + dataSetup + DELAY_COMPEN_1 → delay_component1 = low - 1 - dataSetup (using low as HIGH pulse base)
+				// MODE2: DATA_SETUP_TIME is not in this half (accounted for in delay_component2)
+				// LOW half overhead: overhead compensation of 4 = low - 4
 				else if (mode === "MODE2") value = low - 4 ;
 
 				// MODE3: DATA_SETUP_TIME is now in the LOW half (before SET SCLK sampling edge)
@@ -1273,8 +1273,8 @@ exports = {
 				// LOW half overhead: CLR SCLK + bit handling (4) + qbne (1) = 6
 				else if (mode === "MODE1") value = low - 5;
 
-				// MODE2: DATA_SETUP_TIME is in the HIGH half (not here — DELAY_COMPEN_2 is in LOW half)
-				// LOW half overhead: read SDI(4) + SET SCLK(1) + add/sub(1) + qbne(1) = 7... using base of 3
+				// MODE2: DATA_SETUP_TIME is in the HIGH half (before CLR SCLK sampling edge)
+				// HIGH half overhead: overhead compensation of 3 + dataSetup = high - 3 - dataSetup
 				else if (mode === "MODE2") value = high - 3 - dataSetup;
 
 				// MODE3: DATA_SETUP_TIME is in the LOW half (not here)
diff --git a/.metadata/sysconfig/.meta/pru_blocks/pru_io_blocks/uart_tx_op.syscfg.js b/.metadata/sysconfig/.meta/pru_blocks/pru_io_blocks/uart_tx_op.syscfg.js
index 5b6d1c7..ffd3b71 100644
--- a/.metadata/sysconfig/.meta/pru_blocks/pru_io_blocks/uart_tx_op.syscfg.js
+++ b/.metadata/sysconfig/.meta/pru_blocks/pru_io_blocks/uart_tx_op.syscfg.js
@@ -960,7 +960,7 @@ exports = {
     ports: (inst) => {
         const dataBits = inst.dataBits;
         const inputType = dataBits > 32 ? "input64" : "input32";
-        const portName = inputType === "input64" ? "in64" : "output1" 
+        const portName = inputType === "input64" ? "in64" : "input1";
         return [
             { name: "input1", type: inputType, displayName: portName },
             { name: "prev",   type: "PREV" },
diff --git a/examples/conditional/mcuplus/am261x-lp/r5fss0-0_freertos/ti-arm-clang/example.projectspec b/examples/conditional/mcuplus/am261x-lp/r5fss0-0_freertos/ti-arm-clang/example.projectspec
index 89de96d..5b68f43 100644
--- a/examples/conditional/mcuplus/am261x-lp/r5fss0-0_freertos/ti-arm-clang/example.projectspec
+++ b/examples/conditional/mcuplus/am261x-lp/r5fss0-0_freertos/ti-arm-clang/example.projectspec
@@ -84,8 +84,8 @@
             "
             linkerBuildOptions="
                 -lfreertos.am261x.r5f.ti-arm-clang.debug.lib
-                -ldrivers.am261x.r5f.ti-arm-clang.debug.lib
-                -lboard.am261x.r5f.ti-arm-clang.debug.lib
+                -ldrivers.am261x.r5f.ti-arm-clang.freertos.debug.lib
+                -lboard.am261x.r5f.ti-arm-clang.freertos.debug.lib
                 -llibc.a
                 -llibsysbm.a
             "
@@ -96,8 +96,8 @@
             "
             linkerBuildOptions="
                 -lfreertos.am261x.r5f.ti-arm-clang.release.lib
-                -ldrivers.am261x.r5f.ti-arm-clang.release.lib
-                -lboard.am261x.r5f.ti-arm-clang.release.lib
+                -ldrivers.am261x.r5f.ti-arm-clang.freertos.release.lib
+                -lboard.am261x.r5f.ti-arm-clang.freertos.release.lib
                 -llibc.a
                 -llibsysbm.a
             "
diff --git a/examples/conditional/mcuplus/am261x-lp/r5fss0-0_freertos/ti-arm-clang/makefile b/examples/conditional/mcuplus/am261x-lp/r5fss0-0_freertos/ti-arm-clang/makefile
index c62e775..b03ea7d 100644
--- a/examples/conditional/mcuplus/am261x-lp/r5fss0-0_freertos/ti-arm-clang/makefile
+++ b/examples/conditional/mcuplus/am261x-lp/r5fss0-0_freertos/ti-arm-clang/makefile
@@ -29,15 +29,15 @@ OUTNAME:=conditional.$(PROFILE).out
 COREOUTNAME:=conditional.$(PROFILE).optishare.out
 
 BOOTIMAGE_PATH=$(abspath .)
-BOOTIMAGE_NAME:=conditional.$(PROFILE).appimage
-BOOTIMAGE_NAME_XIP:=conditional.$(PROFILE).appimage_xip
-BOOTIMAGE_NAME_SIGNED:=conditional.$(PROFILE).appimage.signed
-BOOTIMAGE_RPRC_NAME:=conditional.$(PROFILE).rprc
-BOOTIMAGE_RPRC_NAME_XIP:=conditional.$(PROFILE).rprc_xip
-BOOTIMAGE_RPRC_NAME_TMP:=conditional.$(PROFILE).rprc_tmp
-BOOTIMAGE_NAME_HS:=conditional.$(PROFILE).appimage.hs
-BOOTIMAGE_NAME_HS_FS:=conditional.$(PROFILE).appimage.hs_fs
-TARGETS := $(BOOTIMAGE_NAME)
+oeconfig?=
+
+BOOTIMAGE_NAME_MCELF:=conditional.$(PROFILE).mcelf
+BOOTIMAGE_NAME_MCELF_HS:=conditional.$(PROFILE).mcelf.hs
+TARGETS := $(BOOTIMAGE_NAME_MCELF)
+
+ifeq ($(DEVICE_TYPE), HS)
+   TARGETS += $(BOOTIMAGE_NAME_MCELF_HS)
+endif
 
 
 FILES_common := \
@@ -112,8 +112,8 @@ LIBS_PATH_common = \
 
 LIBS_common = \
 	-lfreertos.am261x.r5f.ti-arm-clang.${ConfigName}.lib \
-	-ldrivers.am261x.r5f.ti-arm-clang.${ConfigName}.lib \
-	-lboard.am261x.r5f.ti-arm-clang.${ConfigName}.lib \
+	-ldrivers.am261x.r5f.ti-arm-clang.freertos.${ConfigName}.lib \
+	-lboard.am261x.r5f.ti-arm-clang.freertos.${ConfigName}.lib \
 	-llibc.a \
 	-llibsysbm.a \
 
@@ -126,8 +126,8 @@ LFLAGS_common = \
 
 LIBS_NAME = \
 	freertos.am261x.r5f.ti-arm-clang.${ConfigName}.lib \
-	drivers.am261x.r5f.ti-arm-clang.${ConfigName}.lib \
-	board.am261x.r5f.ti-arm-clang.${ConfigName}.lib \
+	drivers.am261x.r5f.ti-arm-clang.freertos.${ConfigName}.lib \
+	board.am261x.r5f.ti-arm-clang.freertos.${ConfigName}.lib \
 	libc.a \
 	libsysbm.a \
 
@@ -208,13 +208,8 @@ clean:
 	@echo  Cleaning: am261x:r5fss0-0:freertos:ti-arm-clang $(OUTNAME) ...
 	$(RMDIR) $(OBJDIR)
 	$(RM) $(OUTNAME)
-	$(RM) $(BOOTIMAGE_NAME)
-	$(RM) $(BOOTIMAGE_NAME_XIP)
-	$(RM) $(BOOTIMAGE_NAME_SIGNED)
-	$(RM) $(BOOTIMAGE_NAME_HS)
-	$(RM) $(BOOTIMAGE_NAME_HS_FS)
-	$(RM) $(BOOTIMAGE_RPRC_NAME)
-	$(RM) $(BOOTIMAGE_RPRC_NAME_XIP)
+	$(RM) $(BOOTIMAGE_NAME_MCELF)
+	$(RM) $(BOOTIMAGE_NAME_MCELF_HS)
 	$(RMDIR) generated/
 
 scrub:
@@ -229,6 +224,10 @@ ifeq ($(OS),Windows_NT)
 	$(RM) \*.bin
 	$(RM) \*.lnkxml
 	$(RM) \*.ossr
+	$(RM) \*.mcelf
+	$(RM) \*.mcelf_xip
+	$(RM) \*.mcelf-enc
+	$(RM) \*.mcelf.hs
 else
 	$(RM) *.out
 	$(RM) *.map
@@ -238,6 +237,10 @@ else
 	$(RM) *.bin
 	$(RM) *.lnkxml
 	$(RM) *.ossr
+	$(RM) *.mcelf
+	$(RM) *.mcelf_xip
+	$(RM) *.mcelf-enc
+	$(RM) *.mcelf.hs
 endif
 	$(RMDIR) generated
 
@@ -276,66 +279,45 @@ BOOTIMAGE_TEMP_OUT_FILE=temp_stdout_$(PROFILE).txt
 
 BOOTIMAGE_CERT_KEY=$(APP_SIGNING_KEY)
 
-BOOTIMAGE_CORE_ID_r5fss0-0 = 4
-BOOTIMAGE_CORE_ID_r5fss0-1 = 5
-BOOTIMAGE_CORE_ID_r5fss1-0 = 6
-BOOTIMAGE_CORE_ID_r5fss1-1 = 7
-BOOTIMAGE_CORE_ID_m4fss0-0 = 14
-SBL_RUN_ADDRESS=0x70000000
+BOOTIMAGE_CORE_ID_r5fss0-0 = 0
+BOOTIMAGE_CORE_ID_r5fss0-1 = 1
+BOOTIMAGE_CORE_ID_r5fss1-0 = 2
+BOOTIMAGE_CORE_ID_r5fss1-1 = 3
+SBL_RUN_ADDRESS=0x70002000
 SBL_DEV_ID=55
 
-MULTI_CORE_IMAGE_GEN = $(SYSCFG_NODE) $(MCU_PLUS_SDK_PATH)/tools/boot/multicoreImageGen/multicoreImageGen.js
-OUTRPRC_CMD = $(SYSCFG_NODE) $(MCU_PLUS_SDK_PATH)/tools/boot/out2rprc/elf2rprc.js
-APP_IMAGE_SIGN_CMD = $(MCU_PLUS_SDK_PATH)/source/security/security_common/tools/boot/signing/appimage_x509_cert_gen.py
-
-ifeq ($(OS),Windows_NT)
-  XIPGEN_CMD=$(MCU_PLUS_SDK_PATH)/tools/boot/xipGen/xipGen.exe
-else
-  UNAME_S = $(shell uname -s)
-  ifeq ($(UNAME_S), Darwin)
-    XIPGEN_CMD=$(MCU_PLUS_SDK_PATH)/tools/boot/xipGen/xipGen.out.mac
-  else
-    XIPGEN_CMD=$(MCU_PLUS_SDK_PATH)/tools/boot/xipGen/xipGen.out
-endif
-endif
-
-MULTI_CORE_IMAGE_PARAMS = \
-	$(BOOTIMAGE_RPRC_NAME)@$(BOOTIMAGE_CORE_ID_r5fss0-0) \
+APP_IMAGE_SIGN_CMD = $(MCU_PLUS_SDK_PATH)/source/security/security_common/tools/boot/signing/mcu_appimage_x509_cert_gen.py
+MCELF_IMAGE_GEN = $(MCU_PLUS_SDK_PATH)/tools/boot/multicore-elf/genimage.py
 
-MULTI_CORE_IMAGE_PARAMS_XIP = \
-	$(BOOTIMAGE_RPRC_NAME_XIP)@$(BOOTIMAGE_CORE_ID_r5fss0-0) \
+$(BOOTIMAGE_NAME_MCELF): $(OUTNAME)
+	@echo  Boot MulticoreELF image: $(BOOTIMAGE_PATH)/$(BOOTIMAGE_NAME_MCELF) ...
+	$(PYTHON) $(MCELF_IMAGE_GEN) --core-img=$(BOOTIMAGE_CORE_ID_r5fss0-0):$(OUTNAME) --output=$(BOOTIMAGE_NAME_MCELF) --merge-segments=$(MCELF_MERGE_SEGMENTS_FLAG) --tolerance-limit=$(MCELF_MERGE_SEGMENTS_TOLERANCE_LIMIT) --ignore-context=$(MCELF_IGNORE_CONTEXT_FLAG) --xip=$(MCELF_XIP_RANGE) --xlat=$(MCELF_ADDR_TRANSLATION_PATH) --max-segment-size=$(MCELF_MAX_SEGMENT_SIZE) $(if $(oeconfig),--otfaConfigFile=$(oeconfig))
+	@echo  Boot MulticoreELF image: $(BOOTIMAGE_PATH)/$(BOOTIMAGE_NAME_MCELF) Done !!!
+	@echo  .
 
-$(BOOTIMAGE_NAME): $(OUTNAME)
-	@echo  Boot image: am261x:r5fss0-0:freertos:ti-arm-clang $(BOOTIMAGE_PATH)/$@ ...
-ifneq ($(OS),Windows_NT)
-	$(CHMOD) a+x $(XIPGEN_CMD)
-endif
-	$(OUTRPRC_CMD) $(OUTNAME) >> $(BOOTIMAGE_TEMP_OUT_FILE)
-	$(COPY) $(BOOTIMAGE_RPRC_NAME) $(BOOTIMAGE_RPRC_NAME_TMP)
-	$(RM) $(BOOTIMAGE_RPRC_NAME)
-	$(XIPGEN_CMD) -i $(BOOTIMAGE_RPRC_NAME_TMP) -o $(BOOTIMAGE_RPRC_NAME) -x $(BOOTIMAGE_RPRC_NAME_XIP) --flash-start-addr 0x60000000 -v > $(BOOTIMAGE_TEMP_OUT_FILE)
-	$(MULTI_CORE_IMAGE_GEN) --devID $(SBL_DEV_ID) --out $(BOOTIMAGE_NAME) $(MULTI_CORE_IMAGE_PARAMS) >> $(BOOTIMAGE_TEMP_OUT_FILE)
-	$(MULTI_CORE_IMAGE_GEN) --devID $(SBL_DEV_ID) --out $(BOOTIMAGE_NAME_XIP) $(MULTI_CORE_IMAGE_PARAMS_XIP) >> $(BOOTIMAGE_TEMP_OUT_FILE)
-	$(RM) $(BOOTIMAGE_RPRC_NAME_TMP)
-	$(RM) $(BOOTIMAGE_TEMP_OUT_FILE)
+$(BOOTIMAGE_NAME_MCELF_HS): $(BOOTIMAGE_NAME_MCELF)
 ifeq ($(DEVICE_TYPE), HS)
 # Sign the appimage using appimage signing script
 ifeq ($(ENC_ENABLED),no)
+ifeq ($(RSASSAPSS_ENABLED),no)
 	@echo Boot image signing: Encryption is disabled.
-	$(PYTHON) $(APP_IMAGE_SIGN_CMD) --bin $(BOOTIMAGE_NAME) --authtype 1 --key $(APP_SIGNING_KEY) --output $(BOOTIMAGE_NAME_HS)
+	$(PYTHON) $(APP_IMAGE_SIGN_CMD) --bin $(BOOTIMAGE_NAME_MCELF) --key $(APP_SIGNING_KEY) --sign_key_id $(APP_SIGNING_KEY_KEYRING_ID) --hash_algo $(APP_SIGNING_HASH_ALGO) --output $(BOOTIMAGE_NAME_MCELF_HS)
 else
-	@echo Boot image signing: Encryption is enabled.
-	$(PYTHON) $(APP_IMAGE_SIGN_CMD) --bin $(BOOTIMAGE_NAME) --authtype 1 --key $(APP_SIGNING_KEY) --enc y --enckey $(APP_ENCRYPTION_KEY) --output $(BOOTIMAGE_NAME_HS)
-	$(RM) $(BOOTIMAGE_NAME)-enc
+	@echo Boot image signing: Encryption is disabled. RSASSAPSS is enabled.
+	$(PYTHON) $(APP_IMAGE_SIGN_CMD) --bin $(BOOTIMAGE_NAME_MCELF) --key $(APP_SIGNING_KEY) --sign_key_id $(APP_SIGNING_KEY_KEYRING_ID) --hash_algo $(APP_SIGNING_HASH_ALGO) --pss_saltlen $(APP_SIGNING_SALT_LENGTH) --output $(BOOTIMAGE_NAME_MCELF_HS) --rsassa_pss
 endif
-	$(RM) $(BOOTIMAGE_NAME)
-	@echo  Boot image: am261x:r5fss0-0:freertos:ti-arm-clang $(BOOTIMAGE_PATH)/$(BOOTIMAGE_NAME_HS) Done !!!
-	@echo  .
 else
-# Sign the appimage for HS-FS using appimage signing script
-	$(PYTHON) $(APP_IMAGE_SIGN_CMD) --bin $(BOOTIMAGE_NAME) --authtype 1 --key $(APP_SIGNING_KEY) --output $(BOOTIMAGE_NAME_HS_FS)
-	$(RM) $(BOOTIMAGE_NAME)
-	@echo  Boot image: am261x:r5fss0-0:freertos:ti-arm-clang $(BOOTIMAGE_PATH)/$(BOOTIMAGE_NAME_HS_FS) Done !!!
+ifeq ($(RSASSAPSS_ENABLED),no)
+	@echo Boot image signing: Encryption is enabled.
+	$(PYTHON) $(APP_IMAGE_SIGN_CMD) --bin $(BOOTIMAGE_NAME_MCELF) --key $(APP_SIGNING_KEY) --enc y --enckey $(APP_ENCRYPTION_KEY) --kd-salt $(KD_SALT) --sign_key_id $(APP_SIGNING_KEY_KEYRING_ID) --enc_key_id $(APP_ENCRYPTION_KEY_KEYRING_ID) --hash_algo $(APP_SIGNING_HASH_ALGO) --output $(BOOTIMAGE_NAME_MCELF_HS)
+	$(RM) $(BOOTIMAGE_NAME_MCELF)-enc
+else
+	@echo Boot image signing: Encryption is enabled. RSASSAPSS is enabled.
+	$(PYTHON) $(APP_IMAGE_SIGN_CMD) --bin $(BOOTIMAGE_NAME_MCELF) --key $(APP_SIGNING_KEY) --enc y --enckey $(APP_ENCRYPTION_KEY) --kd-salt $(KD_SALT) --sign_key_id $(APP_SIGNING_KEY_KEYRING_ID) --enc_key_id $(APP_ENCRYPTION_KEY_KEYRING_ID) --hash_algo $(APP_SIGNING_HASH_ALGO) --pss_saltlen $(APP_SIGNING_SALT_LENGTH) --output $(BOOTIMAGE_NAME_MCELF_HS) --rsassa_pss
+	$(RM) $(BOOTIMAGE_NAME_MCELF)-enc
+endif
+endif
+	@echo  Boot image: am261x:r5fss0-0:freertos:ti-arm-clang $(BOOTIMAGE_PATH)/$(BOOTIMAGE_NAME_MCELF_HS) Done !!!
 	@echo  .
 endif
 
diff --git a/examples/conditional/mcuplus/am261x-lp/r5fss0-0_freertos/ti-arm-clang/makefile.defs b/examples/conditional/mcuplus/am261x-lp/r5fss0-0_freertos/ti-arm-clang/makefile.defs
new file mode 100644
index 0000000..4f41ac3
--- /dev/null
+++ b/examples/conditional/mcuplus/am261x-lp/r5fss0-0_freertos/ti-arm-clang/makefile.defs
@@ -0,0 +1,14 @@
+GEN_FILES__QUOTED += \
+*.appimage* \
+*.appimage_xip \
+*.rprc* \
+*.rprc_xip \
+*.tiimage* \
+*.bin \
+*.lnkxml \
+*.map \
+*.ossr
+
+GEN_FILES__QUOTED += \
+*.mcelf* \
+*.mcelf_xip
diff --git a/examples/conditional/mcuplus/am261x-lp/r5fss0-0_freertos/ti-arm-clang/makefile_ccs_bootimage_gen b/examples/conditional/mcuplus/am261x-lp/r5fss0-0_freertos/ti-arm-clang/makefile_ccs_bootimage_gen
index 9c2450e..fe5c5f6 100644
--- a/examples/conditional/mcuplus/am261x-lp/r5fss0-0_freertos/ti-arm-clang/makefile_ccs_bootimage_gen
+++ b/examples/conditional/mcuplus/am261x-lp/r5fss0-0_freertos/ti-arm-clang/makefile_ccs_bootimage_gen
@@ -25,12 +25,13 @@ endif
 
 OUTFILE=$(PROFILE)/$(OUTNAME).out
 BOOTIMAGE_PATH=$(abspath ${PROFILE})
-BOOTIMAGE_NAME:=$(BOOTIMAGE_PATH)/$(OUTNAME).appimage
-BOOTIMAGE_NAME_XIP:=$(BOOTIMAGE_PATH)/$(OUTNAME).appimage_xip
-BOOTIMAGE_NAME_SIGNED:=$(BOOTIMAGE_PATH)/$(OUTNAME).appimage.signed
-BOOTIMAGE_RPRC_NAME:=$(BOOTIMAGE_PATH)/$(OUTNAME).rprc
-BOOTIMAGE_RPRC_NAME_XIP:=$(BOOTIMAGE_PATH)/$(OUTNAME).rprc_xip
-BOOTIMAGE_RPRC_NAME_TMP:=$(BOOTIMAGE_PATH)/$(OUTNAME).rprc_tmp
+BOOTIMAGE_NAME_MCELF:=$(BOOTIMAGE_PATH)/$(OUTNAME).mcelf
+BOOTIMAGE_NAME_MCELF_HS:=$(BOOTIMAGE_PATH)/$(OUTNAME).mcelf.hs
+TARGETS += $(BOOTIMAGE_NAME_MCELF)
+TARGETS += $(BOOTIMAGE_NAME_MCELF_HS)
+ifeq ($(DEVICE_TYPE), HS)
+   TARGETS += $(BOOTIMAGE_NAME_MCELF_HS)
+endif
 
 #
 # Generation of boot image which can be loaded by Secondary Boot Loader (SBL)
@@ -45,69 +46,50 @@ else
 endif
 BOOTIMAGE_TEMP_OUT_FILE=$(PROFILE)/temp_stdout_$(PROFILE).txt
 
-BOOTIMAGE_CORE_ID_r5fss0-0 = 4
-BOOTIMAGE_CORE_ID_r5fss0-1 = 5
-BOOTIMAGE_CORE_ID_r5fss1-0 = 6
-BOOTIMAGE_CORE_ID_r5fss1-1 = 7
-BOOTIMAGE_CORE_ID_m4fss0-0 = 14
-SBL_RUN_ADDRESS=0x70000000
+BOOTIMAGE_CORE_ID_r5fss0-0 = 0
+BOOTIMAGE_CORE_ID_r5fss0-1 = 1
+BOOTIMAGE_CORE_ID_r5fss1-0 = 2
+BOOTIMAGE_CORE_ID_r5fss1-1 = 3
+SBL_RUN_ADDRESS=0x70002000
 SBL_DEV_ID=55
 
-MULTI_CORE_IMAGE_GEN = $(CCS_NODE) $(MCU_PLUS_SDK_PATH)/tools/boot/multicoreImageGen/multicoreImageGen.js
-OUTRPRC_CMD = $(CCS_NODE) $(MCU_PLUS_SDK_PATH)/tools/boot/out2rprc/elf2rprc.js
-APP_IMAGE_SIGN_CMD = $(MCU_PLUS_SDK_PATH)/source/security/security_common/tools/boot/signing/appimage_x509_cert_gen.py
-
-ifeq ($(OS),Windows_NT)
-  XIPGEN_CMD=$(MCU_PLUS_SDK_PATH)/tools/boot/xipGen/xipGen.exe
-else
-  UNAME_S = $(shell uname -s)
-  ifeq ($(UNAME_S), Darwin)
-    XIPGEN_CMD=$(MCU_PLUS_SDK_PATH)/tools/boot/xipGen/xipGen.out.mac
-  else
-    XIPGEN_CMD=$(MCU_PLUS_SDK_PATH)/tools/boot/xipGen/xipGen.out
-endif
-endif
-
-MULTI_CORE_IMAGE_PARAMS = \
-	$(BOOTIMAGE_RPRC_NAME)@$(BOOTIMAGE_CORE_ID_r5fss0-0) \
-
-MULTI_CORE_IMAGE_PARAMS_XIP = \
-	$(BOOTIMAGE_RPRC_NAME_XIP)@$(BOOTIMAGE_CORE_ID_r5fss0-0)  \
+APP_IMAGE_SIGN_CMD = $(MCU_PLUS_SDK_PATH)/source/security/security_common/tools/boot/signing/mcu_appimage_x509_cert_gen.py
+MCELF_IMAGE_GEN = $(MCU_PLUS_SDK_PATH)/tools/boot/multicore-elf/genimage.py
 
 all:
 ifeq ($(CCS_IDE_MODE),cloud)
 #	No post build steps
 else
-	@echo  Boot image: am261x:r5fss0-0:freertos:ti-arm-clang $(BOOTIMAGE_NAME)  ...
-	$(OUTRPRC_CMD) $(OUTFILE) >> $(BOOTIMAGE_TEMP_OUT_FILE)
-	$(COPY) $(OUTNAME).rprc $(BOOTIMAGE_RPRC_NAME)
-	$(COPY) $(BOOTIMAGE_RPRC_NAME) $(BOOTIMAGE_RPRC_NAME_TMP)
-	$(RM) $(BOOTIMAGE_RPRC_NAME)
-	$(XIPGEN_CMD) -i $(BOOTIMAGE_RPRC_NAME_TMP) -o $(BOOTIMAGE_RPRC_NAME) -x $(BOOTIMAGE_RPRC_NAME_XIP) --flash-start-addr 0x60000000 -v > $(BOOTIMAGE_TEMP_OUT_FILE)
-	$(MULTI_CORE_IMAGE_GEN) --devID $(SBL_DEV_ID) --out $(BOOTIMAGE_NAME) $(MULTI_CORE_IMAGE_PARAMS) >> $(BOOTIMAGE_TEMP_OUT_FILE)
-	$(MULTI_CORE_IMAGE_GEN) --devID $(SBL_DEV_ID) --out $(BOOTIMAGE_NAME_XIP) $(MULTI_CORE_IMAGE_PARAMS_XIP) >> $(BOOTIMAGE_TEMP_OUT_FILE)
-ifeq ($(DEVICE_TYPE),HS)
+
+	@echo  Boot multi-core ELF image: am261x:r5fss0-0:freertos:ti-arm-clang $(BOOTIMAGE_NAME_MCELF) ...
+
+	$(PYTHON) $(MCELF_IMAGE_GEN) --core-img=$(BOOTIMAGE_CORE_ID_r5fss0-0):$(OUTFILE) --output=$(BOOTIMAGE_NAME_MCELF) --merge-segments=$(MCELF_MERGE_SEGMENTS_FLAG) --tolerance-limit=$(MCELF_MERGE_SEGMENTS_TOLERANCE_LIMIT) --ignore-context=$(MCELF_IGNORE_CONTEXT_FLAG) --xip=$(MCELF_XIP_RANGE) --xlat=$(MCELF_ADDR_TRANSLATION_PATH) --max-segment-size=$(MCELF_MAX_SEGMENT_SIZE)
+
+	@echo  Boot multi-core ELF image: $(BOOTIMAGE_NAME_MCELF) Done !!!
+	@echo  .
+
+ifeq ($(DEVICE_TYPE), HS)
 # Sign the appimage using appimage signing script
 ifeq ($(ENC_ENABLED),no)
+ifeq ($(RSASSAPSS_ENABLED),no)
 	@echo Boot image signing: Encryption is disabled.
-	$(PYTHON) $(APP_IMAGE_SIGN_CMD) --bin $(BOOTIMAGE_NAME) --authtype 1 --key $(APP_SIGNING_KEY) --output $(BOOTIMAGE_NAME).hs
-	$(RM) $(BOOTIMAGE_NAME)
+	$(PYTHON) $(APP_IMAGE_SIGN_CMD) --bin $(BOOTIMAGE_NAME_MCELF) --key $(APP_SIGNING_KEY) --sign_key_id $(APP_SIGNING_KEY_KEYRING_ID) --hash_algo $(APP_SIGNING_HASH_ALGO) --output $(BOOTIMAGE_NAME_MCELF_HS)
 else
-	@echo Boot image signing: Encryption is enabled.
-	$(PYTHON) $(APP_IMAGE_SIGN_CMD) --bin $(BOOTIMAGE_NAME) --authtype 1 --key $(APP_SIGNING_KEY) --enc y --enckey $(APP_ENCRYPTION_KEY) --output $(BOOTIMAGE_NAME).hs
-	$(RM) $(BOOTIMAGE_NAME)-enc
+	@echo Boot image signing: Encryption is disabled. RSASSA-PSS is enabled.
+	$(PYTHON) $(APP_IMAGE_SIGN_CMD) --bin $(BOOTIMAGE_NAME_MCELF) --key $(APP_SIGNING_KEY) --sign_key_id $(APP_SIGNING_KEY_KEYRING_ID) --hash_algo $(APP_SIGNING_HASH_ALGO) --pss_saltlen $(APP_SIGNING_SALT_LENGTH) --output $(BOOTIMAGE_NAME_MCELF_HS) --rsassa_pss
 endif
 else
-# Sign the appimage for HS-FS using appimage signing script
-	$(PYTHON) $(APP_IMAGE_SIGN_CMD) --bin $(BOOTIMAGE_NAME) --authtype 1 --key $(APP_SIGNING_KEY) --output $(BOOTIMAGE_NAME).hs_fs
-	$(RM) $(BOOTIMAGE_NAME)
-endif
-	$(RM) $(BOOTIMAGE_RPRC_NAME_TMP)
-ifeq ($(DEVICE_TYPE),HS)
-	@echo  Boot image: am261x:r5fss0-0:freertos:ti-arm-clang $(BOOTIMAGE_NAME).hs Done !!!
-	@echo  .
+ifeq ($(RSASSAPSS_ENABLED),no)
+	@echo Boot image signing: Encryption is enabled.
+	$(PYTHON) $(APP_IMAGE_SIGN_CMD) --bin $(BOOTIMAGE_NAME_MCELF) --key $(APP_SIGNING_KEY) --enc y --enckey $(APP_ENCRYPTION_KEY) --kd-salt $(KD_SALT) --sign_key_id $(APP_SIGNING_KEY_KEYRING_ID) --enc_key_id $(APP_ENCRYPTION_KEY_KEYRING_ID) --hash_algo $(APP_SIGNING_HASH_ALGO) --output $(BOOTIMAGE_NAME_MCELF_HS)
+	$(RM) $(BOOTIMAGE_NAME_MCELF)-enc
 else
-	@echo  Boot image: am261x:r5fss0-0:freertos:ti-arm-clang $(BOOTIMAGE_NAME).hs_fs Done !!!
+	@echo Boot image signing: Encryption is enabled. RSASSA-PSS is enabled.
+	$(PYTHON) $(APP_IMAGE_SIGN_CMD) --bin $(BOOTIMAGE_NAME_MCELF) --key $(APP_SIGNING_KEY) --enc y --enckey $(APP_ENCRYPTION_KEY) --kd-salt $(KD_SALT) --sign_key_id $(APP_SIGNING_KEY_KEYRING_ID) --enc_key_id $(APP_ENCRYPTION_KEY_KEYRING_ID) --hash_algo $(APP_SIGNING_HASH_ALGO) --pss_saltlen $(APP_SIGNING_SALT_LENGTH) --output $(BOOTIMAGE_NAME_MCELF_HS) --rsassa_pss
+	$(RM) $(BOOTIMAGE_NAME_MCELF)-enc
+endif
+endif
+	@echo  Boot image: am261x:r5fss0-0:freertos:ti-arm-clang $(BOOTIMAGE_PATH)/$(BOOTIMAGE_NAME_MCELF_HS) Done !!!
 	@echo  .
 endif
 endif
diff --git a/examples/empty/firmware/am64x-evm/icss_g0_pru0_fw/ti-pru-cgt/makefile b/examples/empty/firmware/am64x-evm/icss_g0_pru0_fw/ti-pru-cgt/makefile
index 0136c96..1afca01 100644
--- a/examples/empty/firmware/am64x-evm/icss_g0_pru0_fw/ti-pru-cgt/makefile
+++ b/examples/empty/firmware/am64x-evm/icss_g0_pru0_fw/ti-pru-cgt/makefile
@@ -35,6 +35,7 @@ include $(PRU_NO_CODE_TOOL_PATH)/pru_rules.mak
 # Append values to INCLUDE, CFLAGS, or LFLAGS here.
 # Values can be appended like this:
 # INCLUDE += --include_path=<value>
+INCLUDE += --include_path=syscfg
 
 # Defines (pass instance specific definitions to the program)
 # see --define or -D in 'PRU Optimizing C/C++ Compiler User's Guide'
diff --git a/examples/empty/firmware/am64x-evm/icss_g0_pru1_fw/ti-pru-cgt/makefile b/examples/empty/firmware/am64x-evm/icss_g0_pru1_fw/ti-pru-cgt/makefile
index c74cf28..60690f6 100644
--- a/examples/empty/firmware/am64x-evm/icss_g0_pru1_fw/ti-pru-cgt/makefile
+++ b/examples/empty/firmware/am64x-evm/icss_g0_pru1_fw/ti-pru-cgt/makefile
@@ -35,6 +35,7 @@ include $(PRU_NO_CODE_TOOL_PATH)/pru_rules.mak
 # Append values to INCLUDE, CFLAGS, or LFLAGS here.
 # Values can be appended like this:
 # INCLUDE += --include_path=<value>
+INCLUDE += --include_path=syscfg
 
 # Defines (pass instance specific definitions to the program)
 # see --define or -D in 'PRU Optimizing C/C++ Compiler User's Guide'
diff --git a/examples/empty/firmware/am64x-evm/icss_g0_rtu_pru0_fw/ti-pru-cgt/makefile b/examples/empty/firmware/am64x-evm/icss_g0_rtu_pru0_fw/ti-pru-cgt/makefile
index c4b7358..59f8002 100644
--- a/examples/empty/firmware/am64x-evm/icss_g0_rtu_pru0_fw/ti-pru-cgt/makefile
+++ b/examples/empty/firmware/am64x-evm/icss_g0_rtu_pru0_fw/ti-pru-cgt/makefile
@@ -35,6 +35,7 @@ include $(PRU_NO_CODE_TOOL_PATH)/pru_rules.mak
 # Append values to INCLUDE, CFLAGS, or LFLAGS here.
 # Values can be appended like this:
 # INCLUDE += --include_path=<value>
+INCLUDE += --include_path=syscfg
 
 # Defines (pass instance specific definitions to the program)
 # see --define or -D in 'PRU Optimizing C/C++ Compiler User's Guide'
diff --git a/examples/empty/firmware/am64x-evm/icss_g0_rtu_pru1_fw/ti-pru-cgt/makefile b/examples/empty/firmware/am64x-evm/icss_g0_rtu_pru1_fw/ti-pru-cgt/makefile
index 1dc7327..4abb9ba 100644
--- a/examples/empty/firmware/am64x-evm/icss_g0_rtu_pru1_fw/ti-pru-cgt/makefile
+++ b/examples/empty/firmware/am64x-evm/icss_g0_rtu_pru1_fw/ti-pru-cgt/makefile
@@ -35,6 +35,7 @@ include $(PRU_NO_CODE_TOOL_PATH)/pru_rules.mak
 # Append values to INCLUDE, CFLAGS, or LFLAGS here.
 # Values can be appended like this:
 # INCLUDE += --include_path=<value>
+INCLUDE += --include_path=syscfg
 
 # Defines (pass instance specific definitions to the program)
 # see --define or -D in 'PRU Optimizing C/C++ Compiler User's Guide'
diff --git a/examples/empty/firmware/am64x-evm/icss_g0_tx_pru0_fw/ti-pru-cgt/makefile b/examples/empty/firmware/am64x-evm/icss_g0_tx_pru0_fw/ti-pru-cgt/makefile
index 444656a..aa7ba75 100644
--- a/examples/empty/firmware/am64x-evm/icss_g0_tx_pru0_fw/ti-pru-cgt/makefile
+++ b/examples/empty/firmware/am64x-evm/icss_g0_tx_pru0_fw/ti-pru-cgt/makefile
@@ -35,6 +35,7 @@ include $(PRU_NO_CODE_TOOL_PATH)/pru_rules.mak
 # Append values to INCLUDE, CFLAGS, or LFLAGS here.
 # Values can be appended like this:
 # INCLUDE += --include_path=<value>
+INCLUDE += --include_path=syscfg
 
 # Defines (pass instance specific definitions to the program)
 # see --define or -D in 'PRU Optimizing C/C++ Compiler User's Guide'
diff --git a/examples/empty/firmware/am64x-evm/icss_g0_tx_pru1_fw/ti-pru-cgt/makefile b/examples/empty/firmware/am64x-evm/icss_g0_tx_pru1_fw/ti-pru-cgt/makefile
index 4960282..e279d44 100644
--- a/examples/empty/firmware/am64x-evm/icss_g0_tx_pru1_fw/ti-pru-cgt/makefile
+++ b/examples/empty/firmware/am64x-evm/icss_g0_tx_pru1_fw/ti-pru-cgt/makefile
@@ -35,6 +35,7 @@ include $(PRU_NO_CODE_TOOL_PATH)/pru_rules.mak
 # Append values to INCLUDE, CFLAGS, or LFLAGS here.
 # Values can be appended like this:
 # INCLUDE += --include_path=<value>
+INCLUDE += --include_path=syscfg
 
 # Defines (pass instance specific definitions to the program)
 # see --define or -D in 'PRU Optimizing C/C++ Compiler User's Guide'
diff --git a/examples/empty/mcuplus/am261x-lp/r5fss0-0_freertos/ti-arm-clang/example.projectspec b/examples/empty/mcuplus/am261x-lp/r5fss0-0_freertos/ti-arm-clang/example.projectspec
index 8ea7132..0b4c32c 100644
--- a/examples/empty/mcuplus/am261x-lp/r5fss0-0_freertos/ti-arm-clang/example.projectspec
+++ b/examples/empty/mcuplus/am261x-lp/r5fss0-0_freertos/ti-arm-clang/example.projectspec
@@ -84,8 +84,8 @@
             "
             linkerBuildOptions="
                 -lfreertos.am261x.r5f.ti-arm-clang.debug.lib
-                -ldrivers.am261x.r5f.ti-arm-clang.debug.lib
-                -lboard.am261x.r5f.ti-arm-clang.debug.lib
+                -ldrivers.am261x.r5f.ti-arm-clang.freertos.debug.lib
+                -lboard.am261x.r5f.ti-arm-clang.freertos.debug.lib
                 -llibc.a
                 -llibsysbm.a
             "
@@ -96,8 +96,8 @@
             "
             linkerBuildOptions="
                 -lfreertos.am261x.r5f.ti-arm-clang.release.lib
-                -ldrivers.am261x.r5f.ti-arm-clang.release.lib
-                -lboard.am261x.r5f.ti-arm-clang.release.lib
+                -ldrivers.am261x.r5f.ti-arm-clang.freertos.release.lib
+                -lboard.am261x.r5f.ti-arm-clang.freertos.release.lib
                 -llibc.a
                 -llibsysbm.a
             "
diff --git a/examples/empty/mcuplus/am261x-lp/r5fss0-0_freertos/ti-arm-clang/makefile b/examples/empty/mcuplus/am261x-lp/r5fss0-0_freertos/ti-arm-clang/makefile
index 2222519..34d6a83 100644
--- a/examples/empty/mcuplus/am261x-lp/r5fss0-0_freertos/ti-arm-clang/makefile
+++ b/examples/empty/mcuplus/am261x-lp/r5fss0-0_freertos/ti-arm-clang/makefile
@@ -29,15 +29,15 @@ OUTNAME:=empty.$(PROFILE).out
 COREOUTNAME:=empty.$(PROFILE).optishare.out
 
 BOOTIMAGE_PATH=$(abspath .)
-BOOTIMAGE_NAME:=empty.$(PROFILE).appimage
-BOOTIMAGE_NAME_XIP:=empty.$(PROFILE).appimage_xip
-BOOTIMAGE_NAME_SIGNED:=empty.$(PROFILE).appimage.signed
-BOOTIMAGE_RPRC_NAME:=empty.$(PROFILE).rprc
-BOOTIMAGE_RPRC_NAME_XIP:=empty.$(PROFILE).rprc_xip
-BOOTIMAGE_RPRC_NAME_TMP:=empty.$(PROFILE).rprc_tmp
-BOOTIMAGE_NAME_HS:=empty.$(PROFILE).appimage.hs
-BOOTIMAGE_NAME_HS_FS:=empty.$(PROFILE).appimage.hs_fs
-TARGETS := $(BOOTIMAGE_NAME)
+oeconfig?=
+
+BOOTIMAGE_NAME_MCELF:=empty.$(PROFILE).mcelf
+BOOTIMAGE_NAME_MCELF_HS:=empty.$(PROFILE).mcelf.hs
+TARGETS := $(BOOTIMAGE_NAME_MCELF)
+
+ifeq ($(DEVICE_TYPE), HS)
+   TARGETS += $(BOOTIMAGE_NAME_MCELF_HS)
+endif
 
 
 FILES_common := \
@@ -112,8 +112,8 @@ LIBS_PATH_common = \
 
 LIBS_common = \
 	-lfreertos.am261x.r5f.ti-arm-clang.${ConfigName}.lib \
-	-ldrivers.am261x.r5f.ti-arm-clang.${ConfigName}.lib \
-	-lboard.am261x.r5f.ti-arm-clang.${ConfigName}.lib \
+	-ldrivers.am261x.r5f.ti-arm-clang.freertos.${ConfigName}.lib \
+	-lboard.am261x.r5f.ti-arm-clang.freertos.${ConfigName}.lib \
 	-llibc.a \
 	-llibsysbm.a \
 
@@ -126,8 +126,8 @@ LFLAGS_common = \
 
 LIBS_NAME = \
 	freertos.am261x.r5f.ti-arm-clang.${ConfigName}.lib \
-	drivers.am261x.r5f.ti-arm-clang.${ConfigName}.lib \
-	board.am261x.r5f.ti-arm-clang.${ConfigName}.lib \
+	drivers.am261x.r5f.ti-arm-clang.freertos.${ConfigName}.lib \
+	board.am261x.r5f.ti-arm-clang.freertos.${ConfigName}.lib \
 	libc.a \
 	libsysbm.a \
 
@@ -208,13 +208,8 @@ clean:
 	@echo  Cleaning: am261x:r5fss0-0:freertos:ti-arm-clang $(OUTNAME) ...
 	$(RMDIR) $(OBJDIR)
 	$(RM) $(OUTNAME)
-	$(RM) $(BOOTIMAGE_NAME)
-	$(RM) $(BOOTIMAGE_NAME_XIP)
-	$(RM) $(BOOTIMAGE_NAME_SIGNED)
-	$(RM) $(BOOTIMAGE_NAME_HS)
-	$(RM) $(BOOTIMAGE_NAME_HS_FS)
-	$(RM) $(BOOTIMAGE_RPRC_NAME)
-	$(RM) $(BOOTIMAGE_RPRC_NAME_XIP)
+	$(RM) $(BOOTIMAGE_NAME_MCELF)
+	$(RM) $(BOOTIMAGE_NAME_MCELF_HS)
 	$(RMDIR) generated/
 
 scrub:
@@ -229,6 +224,10 @@ ifeq ($(OS),Windows_NT)
 	$(RM) \*.bin
 	$(RM) \*.lnkxml
 	$(RM) \*.ossr
+	$(RM) \*.mcelf
+	$(RM) \*.mcelf_xip
+	$(RM) \*.mcelf-enc
+	$(RM) \*.mcelf.hs
 else
 	$(RM) *.out
 	$(RM) *.map
@@ -238,6 +237,10 @@ else
 	$(RM) *.bin
 	$(RM) *.lnkxml
 	$(RM) *.ossr
+	$(RM) *.mcelf
+	$(RM) *.mcelf_xip
+	$(RM) *.mcelf-enc
+	$(RM) *.mcelf.hs
 endif
 	$(RMDIR) generated
 
@@ -274,68 +277,45 @@ else
 endif
 BOOTIMAGE_TEMP_OUT_FILE=temp_stdout_$(PROFILE).txt
 
-BOOTIMAGE_CERT_KEY=$(APP_SIGNING_KEY)
-
-BOOTIMAGE_CORE_ID_r5fss0-0 = 4
-BOOTIMAGE_CORE_ID_r5fss0-1 = 5
-BOOTIMAGE_CORE_ID_r5fss1-0 = 6
-BOOTIMAGE_CORE_ID_r5fss1-1 = 7
-BOOTIMAGE_CORE_ID_m4fss0-0 = 14
-SBL_RUN_ADDRESS=0x70000000
+BOOTIMAGE_CORE_ID_r5fss0-0 = 0
+BOOTIMAGE_CORE_ID_r5fss0-1 = 1
+BOOTIMAGE_CORE_ID_r5fss1-0 = 2
+BOOTIMAGE_CORE_ID_r5fss1-1 = 3
+SBL_RUN_ADDRESS=0x70002000
 SBL_DEV_ID=55
 
-MULTI_CORE_IMAGE_GEN = $(SYSCFG_NODE) $(MCU_PLUS_SDK_PATH)/tools/boot/multicoreImageGen/multicoreImageGen.js
-OUTRPRC_CMD = $(SYSCFG_NODE) $(MCU_PLUS_SDK_PATH)/tools/boot/out2rprc/elf2rprc.js
-APP_IMAGE_SIGN_CMD = $(MCU_PLUS_SDK_PATH)/source/security/security_common/tools/boot/signing/appimage_x509_cert_gen.py
-
-ifeq ($(OS),Windows_NT)
-  XIPGEN_CMD=$(MCU_PLUS_SDK_PATH)/tools/boot/xipGen/xipGen.exe
-else
-  UNAME_S = $(shell uname -s)
-  ifeq ($(UNAME_S), Darwin)
-    XIPGEN_CMD=$(MCU_PLUS_SDK_PATH)/tools/boot/xipGen/xipGen.out.mac
-  else
-    XIPGEN_CMD=$(MCU_PLUS_SDK_PATH)/tools/boot/xipGen/xipGen.out
-endif
-endif
+APP_IMAGE_SIGN_CMD = $(MCU_PLUS_SDK_PATH)/source/security/security_common/tools/boot/signing/mcu_appimage_x509_cert_gen.py
+MCELF_IMAGE_GEN = $(MCU_PLUS_SDK_PATH)/tools/boot/multicore-elf/genimage.py
 
-MULTI_CORE_IMAGE_PARAMS = \
-	$(BOOTIMAGE_RPRC_NAME)@$(BOOTIMAGE_CORE_ID_r5fss0-0) \
-
-MULTI_CORE_IMAGE_PARAMS_XIP = \
-	$(BOOTIMAGE_RPRC_NAME_XIP)@$(BOOTIMAGE_CORE_ID_r5fss0-0) \
+$(BOOTIMAGE_NAME_MCELF): $(OUTNAME)
+	@echo  Boot MulticoreELF image: $(BOOTIMAGE_PATH)/$(BOOTIMAGE_NAME_MCELF) ...
+	$(PYTHON) $(MCELF_IMAGE_GEN) --core-img=$(BOOTIMAGE_CORE_ID_r5fss0-0):$(OUTNAME) --output=$(BOOTIMAGE_NAME_MCELF) --merge-segments=$(MCELF_MERGE_SEGMENTS_FLAG) --tolerance-limit=$(MCELF_MERGE_SEGMENTS_TOLERANCE_LIMIT) --ignore-context=$(MCELF_IGNORE_CONTEXT_FLAG) --xip=$(MCELF_XIP_RANGE) --xlat=$(MCELF_ADDR_TRANSLATION_PATH) --max-segment-size=$(MCELF_MAX_SEGMENT_SIZE) $(if $(oeconfig),--otfaConfigFile=$(oeconfig))
+	@echo  Boot MulticoreELF image: $(BOOTIMAGE_PATH)/$(BOOTIMAGE_NAME_MCELF) Done !!!
+	@echo  .
 
-$(BOOTIMAGE_NAME): $(OUTNAME)
-	@echo  Boot image: am261x:r5fss0-0:freertos:ti-arm-clang $(BOOTIMAGE_PATH)/$@ ...
-ifneq ($(OS),Windows_NT)
-	$(CHMOD) a+x $(XIPGEN_CMD)
-endif
-	$(OUTRPRC_CMD) $(OUTNAME) >> $(BOOTIMAGE_TEMP_OUT_FILE)
-	$(COPY) $(BOOTIMAGE_RPRC_NAME) $(BOOTIMAGE_RPRC_NAME_TMP)
-	$(RM) $(BOOTIMAGE_RPRC_NAME)
-	$(XIPGEN_CMD) -i $(BOOTIMAGE_RPRC_NAME_TMP) -o $(BOOTIMAGE_RPRC_NAME) -x $(BOOTIMAGE_RPRC_NAME_XIP) --flash-start-addr 0x60000000 -v > $(BOOTIMAGE_TEMP_OUT_FILE)
-	$(MULTI_CORE_IMAGE_GEN) --devID $(SBL_DEV_ID) --out $(BOOTIMAGE_NAME) $(MULTI_CORE_IMAGE_PARAMS) >> $(BOOTIMAGE_TEMP_OUT_FILE)
-	$(MULTI_CORE_IMAGE_GEN) --devID $(SBL_DEV_ID) --out $(BOOTIMAGE_NAME_XIP) $(MULTI_CORE_IMAGE_PARAMS_XIP) >> $(BOOTIMAGE_TEMP_OUT_FILE)
-	$(RM) $(BOOTIMAGE_RPRC_NAME_TMP)
-	$(RM) $(BOOTIMAGE_TEMP_OUT_FILE)
+$(BOOTIMAGE_NAME_MCELF_HS): $(BOOTIMAGE_NAME_MCELF)
 ifeq ($(DEVICE_TYPE), HS)
 # Sign the appimage using appimage signing script
 ifeq ($(ENC_ENABLED),no)
+ifeq ($(RSASSAPSS_ENABLED),no)
 	@echo Boot image signing: Encryption is disabled.
-	$(PYTHON) $(APP_IMAGE_SIGN_CMD) --bin $(BOOTIMAGE_NAME) --authtype 1 --key $(APP_SIGNING_KEY) --output $(BOOTIMAGE_NAME_HS)
+	$(PYTHON) $(APP_IMAGE_SIGN_CMD) --bin $(BOOTIMAGE_NAME_MCELF) --key $(APP_SIGNING_KEY) --sign_key_id $(APP_SIGNING_KEY_KEYRING_ID) --hash_algo $(APP_SIGNING_HASH_ALGO) --output $(BOOTIMAGE_NAME_MCELF_HS)
 else
-	@echo Boot image signing: Encryption is enabled.
-	$(PYTHON) $(APP_IMAGE_SIGN_CMD) --bin $(BOOTIMAGE_NAME) --authtype 1 --key $(APP_SIGNING_KEY) --enc y --enckey $(APP_ENCRYPTION_KEY) --output $(BOOTIMAGE_NAME_HS)
-	$(RM) $(BOOTIMAGE_NAME)-enc
+	@echo Boot image signing: Encryption is disabled. RSASSAPSS is enabled.
+	$(PYTHON) $(APP_IMAGE_SIGN_CMD) --bin $(BOOTIMAGE_NAME_MCELF) --key $(APP_SIGNING_KEY) --sign_key_id $(APP_SIGNING_KEY_KEYRING_ID) --hash_algo $(APP_SIGNING_HASH_ALGO) --pss_saltlen $(APP_SIGNING_SALT_LENGTH) --output $(BOOTIMAGE_NAME_MCELF_HS) --rsassa_pss
 endif
-	$(RM) $(BOOTIMAGE_NAME)
-	@echo  Boot image: am261x:r5fss0-0:freertos:ti-arm-clang $(BOOTIMAGE_PATH)/$(BOOTIMAGE_NAME_HS) Done !!!
-	@echo  .
 else
-# Sign the appimage for HS-FS using appimage signing script
-	$(PYTHON) $(APP_IMAGE_SIGN_CMD) --bin $(BOOTIMAGE_NAME) --authtype 1 --key $(APP_SIGNING_KEY) --output $(BOOTIMAGE_NAME_HS_FS)
-	$(RM) $(BOOTIMAGE_NAME)
-	@echo  Boot image: am261x:r5fss0-0:freertos:ti-arm-clang $(BOOTIMAGE_PATH)/$(BOOTIMAGE_NAME_HS_FS) Done !!!
+ifeq ($(RSASSAPSS_ENABLED),no)
+	@echo Boot image signing: Encryption is enabled.
+	$(PYTHON) $(APP_IMAGE_SIGN_CMD) --bin $(BOOTIMAGE_NAME_MCELF) --key $(APP_SIGNING_KEY) --enc y --enckey $(APP_ENCRYPTION_KEY) --kd-salt $(KD_SALT) --sign_key_id $(APP_SIGNING_KEY_KEYRING_ID) --enc_key_id $(APP_ENCRYPTION_KEY_KEYRING_ID) --hash_algo $(APP_SIGNING_HASH_ALGO) --output $(BOOTIMAGE_NAME_MCELF_HS)
+	$(RM) $(BOOTIMAGE_NAME_MCELF)-enc
+else
+	@echo Boot image signing: Encryption is enabled. RSASSAPSS is enabled.
+	$(PYTHON) $(APP_IMAGE_SIGN_CMD) --bin $(BOOTIMAGE_NAME_MCELF) --key $(APP_SIGNING_KEY) --enc y --enckey $(APP_ENCRYPTION_KEY) --kd-salt $(KD_SALT) --sign_key_id $(APP_SIGNING_KEY_KEYRING_ID) --enc_key_id $(APP_ENCRYPTION_KEY_KEYRING_ID) --hash_algo $(APP_SIGNING_HASH_ALGO) --pss_saltlen $(APP_SIGNING_SALT_LENGTH) --output $(BOOTIMAGE_NAME_MCELF_HS) --rsassa_pss
+	$(RM) $(BOOTIMAGE_NAME_MCELF)-enc
+endif
+endif
+	@echo  Boot image: am261x:r5fss0-0:freertos:ti-arm-clang $(BOOTIMAGE_PATH)/$(BOOTIMAGE_NAME_MCELF_HS) Done !!!
 	@echo  .
 endif
 
diff --git a/examples/empty/mcuplus/am261x-lp/r5fss0-0_freertos/ti-arm-clang/makefile.defs b/examples/empty/mcuplus/am261x-lp/r5fss0-0_freertos/ti-arm-clang/makefile.defs
new file mode 100644
index 0000000..4f41ac3
--- /dev/null
+++ b/examples/empty/mcuplus/am261x-lp/r5fss0-0_freertos/ti-arm-clang/makefile.defs
@@ -0,0 +1,14 @@
+GEN_FILES__QUOTED += \
+*.appimage* \
+*.appimage_xip \
+*.rprc* \
+*.rprc_xip \
+*.tiimage* \
+*.bin \
+*.lnkxml \
+*.map \
+*.ossr
+
+GEN_FILES__QUOTED += \
+*.mcelf* \
+*.mcelf_xip
diff --git a/examples/empty/mcuplus/am261x-lp/r5fss0-0_freertos/ti-arm-clang/makefile_ccs_bootimage_gen b/examples/empty/mcuplus/am261x-lp/r5fss0-0_freertos/ti-arm-clang/makefile_ccs_bootimage_gen
index 9c2450e..20a8093 100644
--- a/examples/empty/mcuplus/am261x-lp/r5fss0-0_freertos/ti-arm-clang/makefile_ccs_bootimage_gen
+++ b/examples/empty/mcuplus/am261x-lp/r5fss0-0_freertos/ti-arm-clang/makefile_ccs_bootimage_gen
@@ -3,7 +3,6 @@
 #
 
 # Below variables need to be defined outside this file or via command line
-# - PRU_NO_CODE_TOOL_PATH
 # - MCU_PLUS_SDK_PATH
 # - PROFILE
 # - CG_TOOL_ROOT
@@ -25,12 +24,13 @@ endif
 
 OUTFILE=$(PROFILE)/$(OUTNAME).out
 BOOTIMAGE_PATH=$(abspath ${PROFILE})
-BOOTIMAGE_NAME:=$(BOOTIMAGE_PATH)/$(OUTNAME).appimage
-BOOTIMAGE_NAME_XIP:=$(BOOTIMAGE_PATH)/$(OUTNAME).appimage_xip
-BOOTIMAGE_NAME_SIGNED:=$(BOOTIMAGE_PATH)/$(OUTNAME).appimage.signed
-BOOTIMAGE_RPRC_NAME:=$(BOOTIMAGE_PATH)/$(OUTNAME).rprc
-BOOTIMAGE_RPRC_NAME_XIP:=$(BOOTIMAGE_PATH)/$(OUTNAME).rprc_xip
-BOOTIMAGE_RPRC_NAME_TMP:=$(BOOTIMAGE_PATH)/$(OUTNAME).rprc_tmp
+BOOTIMAGE_NAME_MCELF:=$(BOOTIMAGE_PATH)/$(OUTNAME).mcelf
+BOOTIMAGE_NAME_MCELF_HS:=$(BOOTIMAGE_PATH)/$(OUTNAME).mcelf.hs
+TARGETS += $(BOOTIMAGE_NAME_MCELF)
+TARGETS += $(BOOTIMAGE_NAME_MCELF_HS)
+ifeq ($(DEVICE_TYPE), HS)
+   TARGETS += $(BOOTIMAGE_NAME_MCELF_HS)
+endif
 
 #
 # Generation of boot image which can be loaded by Secondary Boot Loader (SBL)
@@ -45,69 +45,50 @@ else
 endif
 BOOTIMAGE_TEMP_OUT_FILE=$(PROFILE)/temp_stdout_$(PROFILE).txt
 
-BOOTIMAGE_CORE_ID_r5fss0-0 = 4
-BOOTIMAGE_CORE_ID_r5fss0-1 = 5
-BOOTIMAGE_CORE_ID_r5fss1-0 = 6
-BOOTIMAGE_CORE_ID_r5fss1-1 = 7
-BOOTIMAGE_CORE_ID_m4fss0-0 = 14
-SBL_RUN_ADDRESS=0x70000000
+BOOTIMAGE_CORE_ID_r5fss0-0 = 0
+BOOTIMAGE_CORE_ID_r5fss0-1 = 1
+BOOTIMAGE_CORE_ID_r5fss1-0 = 2
+BOOTIMAGE_CORE_ID_r5fss1-1 = 3
+SBL_RUN_ADDRESS=0x70002000
 SBL_DEV_ID=55
 
-MULTI_CORE_IMAGE_GEN = $(CCS_NODE) $(MCU_PLUS_SDK_PATH)/tools/boot/multicoreImageGen/multicoreImageGen.js
-OUTRPRC_CMD = $(CCS_NODE) $(MCU_PLUS_SDK_PATH)/tools/boot/out2rprc/elf2rprc.js
-APP_IMAGE_SIGN_CMD = $(MCU_PLUS_SDK_PATH)/source/security/security_common/tools/boot/signing/appimage_x509_cert_gen.py
-
-ifeq ($(OS),Windows_NT)
-  XIPGEN_CMD=$(MCU_PLUS_SDK_PATH)/tools/boot/xipGen/xipGen.exe
-else
-  UNAME_S = $(shell uname -s)
-  ifeq ($(UNAME_S), Darwin)
-    XIPGEN_CMD=$(MCU_PLUS_SDK_PATH)/tools/boot/xipGen/xipGen.out.mac
-  else
-    XIPGEN_CMD=$(MCU_PLUS_SDK_PATH)/tools/boot/xipGen/xipGen.out
-endif
-endif
-
-MULTI_CORE_IMAGE_PARAMS = \
-	$(BOOTIMAGE_RPRC_NAME)@$(BOOTIMAGE_CORE_ID_r5fss0-0) \
-
-MULTI_CORE_IMAGE_PARAMS_XIP = \
-	$(BOOTIMAGE_RPRC_NAME_XIP)@$(BOOTIMAGE_CORE_ID_r5fss0-0)  \
+APP_IMAGE_SIGN_CMD = $(MCU_PLUS_SDK_PATH)/source/security/security_common/tools/boot/signing/mcu_appimage_x509_cert_gen.py
+MCELF_IMAGE_GEN = $(MCU_PLUS_SDK_PATH)/tools/boot/multicore-elf/genimage.py
 
 all:
 ifeq ($(CCS_IDE_MODE),cloud)
 #	No post build steps
 else
-	@echo  Boot image: am261x:r5fss0-0:freertos:ti-arm-clang $(BOOTIMAGE_NAME)  ...
-	$(OUTRPRC_CMD) $(OUTFILE) >> $(BOOTIMAGE_TEMP_OUT_FILE)
-	$(COPY) $(OUTNAME).rprc $(BOOTIMAGE_RPRC_NAME)
-	$(COPY) $(BOOTIMAGE_RPRC_NAME) $(BOOTIMAGE_RPRC_NAME_TMP)
-	$(RM) $(BOOTIMAGE_RPRC_NAME)
-	$(XIPGEN_CMD) -i $(BOOTIMAGE_RPRC_NAME_TMP) -o $(BOOTIMAGE_RPRC_NAME) -x $(BOOTIMAGE_RPRC_NAME_XIP) --flash-start-addr 0x60000000 -v > $(BOOTIMAGE_TEMP_OUT_FILE)
-	$(MULTI_CORE_IMAGE_GEN) --devID $(SBL_DEV_ID) --out $(BOOTIMAGE_NAME) $(MULTI_CORE_IMAGE_PARAMS) >> $(BOOTIMAGE_TEMP_OUT_FILE)
-	$(MULTI_CORE_IMAGE_GEN) --devID $(SBL_DEV_ID) --out $(BOOTIMAGE_NAME_XIP) $(MULTI_CORE_IMAGE_PARAMS_XIP) >> $(BOOTIMAGE_TEMP_OUT_FILE)
-ifeq ($(DEVICE_TYPE),HS)
+
+	@echo  Boot multi-core ELF image: am261x:r5fss0-0:freertos:ti-arm-clang $(BOOTIMAGE_NAME_MCELF) ...
+
+	$(PYTHON) $(MCELF_IMAGE_GEN) --core-img=$(BOOTIMAGE_CORE_ID_r5fss0-0):$(OUTFILE) --output=$(BOOTIMAGE_NAME_MCELF) --merge-segments=$(MCELF_MERGE_SEGMENTS_FLAG) --tolerance-limit=$(MCELF_MERGE_SEGMENTS_TOLERANCE_LIMIT) --ignore-context=$(MCELF_IGNORE_CONTEXT_FLAG) --xip=$(MCELF_XIP_RANGE) --xlat=$(MCELF_ADDR_TRANSLATION_PATH) --max-segment-size=$(MCELF_MAX_SEGMENT_SIZE)
+
+	@echo  Boot multi-core ELF image: $(BOOTIMAGE_NAME_MCELF) Done !!!
+	@echo  .
+
+ifeq ($(DEVICE_TYPE), HS)
 # Sign the appimage using appimage signing script
 ifeq ($(ENC_ENABLED),no)
+ifeq ($(RSASSAPSS_ENABLED),no)
 	@echo Boot image signing: Encryption is disabled.
-	$(PYTHON) $(APP_IMAGE_SIGN_CMD) --bin $(BOOTIMAGE_NAME) --authtype 1 --key $(APP_SIGNING_KEY) --output $(BOOTIMAGE_NAME).hs
-	$(RM) $(BOOTIMAGE_NAME)
+	$(PYTHON) $(APP_IMAGE_SIGN_CMD) --bin $(BOOTIMAGE_NAME_MCELF) --key $(APP_SIGNING_KEY) --sign_key_id $(APP_SIGNING_KEY_KEYRING_ID) --hash_algo $(APP_SIGNING_HASH_ALGO) --output $(BOOTIMAGE_NAME_MCELF_HS)
 else
-	@echo Boot image signing: Encryption is enabled.
-	$(PYTHON) $(APP_IMAGE_SIGN_CMD) --bin $(BOOTIMAGE_NAME) --authtype 1 --key $(APP_SIGNING_KEY) --enc y --enckey $(APP_ENCRYPTION_KEY) --output $(BOOTIMAGE_NAME).hs
-	$(RM) $(BOOTIMAGE_NAME)-enc
+	@echo Boot image signing: Encryption is disabled. RSASSA-PSS is enabled.
+	$(PYTHON) $(APP_IMAGE_SIGN_CMD) --bin $(BOOTIMAGE_NAME_MCELF) --key $(APP_SIGNING_KEY) --sign_key_id $(APP_SIGNING_KEY_KEYRING_ID) --hash_algo $(APP_SIGNING_HASH_ALGO) --pss_saltlen $(APP_SIGNING_SALT_LENGTH) --output $(BOOTIMAGE_NAME_MCELF_HS) --rsassa_pss
 endif
 else
-# Sign the appimage for HS-FS using appimage signing script
-	$(PYTHON) $(APP_IMAGE_SIGN_CMD) --bin $(BOOTIMAGE_NAME) --authtype 1 --key $(APP_SIGNING_KEY) --output $(BOOTIMAGE_NAME).hs_fs
-	$(RM) $(BOOTIMAGE_NAME)
-endif
-	$(RM) $(BOOTIMAGE_RPRC_NAME_TMP)
-ifeq ($(DEVICE_TYPE),HS)
-	@echo  Boot image: am261x:r5fss0-0:freertos:ti-arm-clang $(BOOTIMAGE_NAME).hs Done !!!
-	@echo  .
+ifeq ($(RSASSAPSS_ENABLED),no)
+	@echo Boot image signing: Encryption is enabled.
+	$(PYTHON) $(APP_IMAGE_SIGN_CMD) --bin $(BOOTIMAGE_NAME_MCELF) --key $(APP_SIGNING_KEY) --enc y --enckey $(APP_ENCRYPTION_KEY) --kd-salt $(KD_SALT) --sign_key_id $(APP_SIGNING_KEY_KEYRING_ID) --enc_key_id $(APP_ENCRYPTION_KEY_KEYRING_ID) --hash_algo $(APP_SIGNING_HASH_ALGO) --output $(BOOTIMAGE_NAME_MCELF_HS)
+	$(RM) $(BOOTIMAGE_NAME_MCELF)-enc
 else
-	@echo  Boot image: am261x:r5fss0-0:freertos:ti-arm-clang $(BOOTIMAGE_NAME).hs_fs Done !!!
+	@echo Boot image signing: Encryption is enabled. RSASSA-PSS is enabled.
+	$(PYTHON) $(APP_IMAGE_SIGN_CMD) --bin $(BOOTIMAGE_NAME_MCELF) --key $(APP_SIGNING_KEY) --enc y --enckey $(APP_ENCRYPTION_KEY) --kd-salt $(KD_SALT) --sign_key_id $(APP_SIGNING_KEY_KEYRING_ID) --enc_key_id $(APP_ENCRYPTION_KEY_KEYRING_ID) --hash_algo $(APP_SIGNING_HASH_ALGO) --pss_saltlen $(APP_SIGNING_SALT_LENGTH) --output $(BOOTIMAGE_NAME_MCELF_HS) --rsassa_pss
+	$(RM) $(BOOTIMAGE_NAME_MCELF)-enc
+endif
+endif
+	@echo  Boot image: am261x:r5fss0-0:freertos:ti-arm-clang $(BOOTIMAGE_PATH)/$(BOOTIMAGE_NAME_MCELF_HS) Done !!!
 	@echo  .
 endif
 endif
diff --git a/examples/gray_encoder_4_bit/mcuplus/am261x-lp/r5fss0-0_freertos/ti-arm-clang/example.projectspec b/examples/gray_encoder_4_bit/mcuplus/am261x-lp/r5fss0-0_freertos/ti-arm-clang/example.projectspec
index 94dc7c4..f64e4ca 100644
--- a/examples/gray_encoder_4_bit/mcuplus/am261x-lp/r5fss0-0_freertos/ti-arm-clang/example.projectspec
+++ b/examples/gray_encoder_4_bit/mcuplus/am261x-lp/r5fss0-0_freertos/ti-arm-clang/example.projectspec
@@ -81,8 +81,8 @@
             "
             linkerBuildOptions="
                 -lfreertos.am261x.r5f.ti-arm-clang.debug.lib
-                -ldrivers.am261x.r5f.ti-arm-clang.debug.lib
-                -lboard.am261x.r5f.ti-arm-clang.debug.lib
+                -ldrivers.am261x.r5f.ti-arm-clang.freertos.debug.lib
+                -lboard.am261x.r5f.ti-arm-clang.freertos.debug.lib
                 -llibc.a
                 -llibsysbm.a
             "
@@ -93,8 +93,8 @@
             "
             linkerBuildOptions="
                 -lfreertos.am261x.r5f.ti-arm-clang.release.lib
-                -ldrivers.am261x.r5f.ti-arm-clang.release.lib
-                -lboard.am261x.r5f.ti-arm-clang.release.lib
+                -ldrivers.am261x.r5f.ti-arm-clang.freertos.release.lib
+                -lboard.am261x.r5f.ti-arm-clang.freertos.release.lib
                 -llibc.a
                 -llibsysbm.a
             "
diff --git a/examples/gray_encoder_4_bit/mcuplus/am261x-lp/r5fss0-0_freertos/ti-arm-clang/makefile b/examples/gray_encoder_4_bit/mcuplus/am261x-lp/r5fss0-0_freertos/ti-arm-clang/makefile
index c87c037..5189296 100644
--- a/examples/gray_encoder_4_bit/mcuplus/am261x-lp/r5fss0-0_freertos/ti-arm-clang/makefile
+++ b/examples/gray_encoder_4_bit/mcuplus/am261x-lp/r5fss0-0_freertos/ti-arm-clang/makefile
@@ -29,15 +29,15 @@ OUTNAME:=gray_encoder_4_bit.$(PROFILE).out
 COREOUTNAME:=gray_encoder_4_bit.$(PROFILE).optishare.out
 
 BOOTIMAGE_PATH=$(abspath .)
-BOOTIMAGE_NAME:=gray_encoder_4_bit.$(PROFILE).appimage
-BOOTIMAGE_NAME_XIP:=gray_encoder_4_bit.$(PROFILE).appimage_xip
-BOOTIMAGE_NAME_SIGNED:=gray_encoder_4_bit.$(PROFILE).appimage.signed
-BOOTIMAGE_RPRC_NAME:=gray_encoder_4_bit.$(PROFILE).rprc
-BOOTIMAGE_RPRC_NAME_XIP:=gray_encoder_4_bit.$(PROFILE).rprc_xip
-BOOTIMAGE_RPRC_NAME_TMP:=gray_encoder_4_bit.$(PROFILE).rprc_tmp
-BOOTIMAGE_NAME_HS:=gray_encoder_4_bit.$(PROFILE).appimage.hs
-BOOTIMAGE_NAME_HS_FS:=gray_encoder_4_bit.$(PROFILE).appimage.hs_fs
-TARGETS := $(BOOTIMAGE_NAME)
+oeconfig?=
+
+BOOTIMAGE_NAME_MCELF:=gray_encoder_4_bit.$(PROFILE).mcelf
+BOOTIMAGE_NAME_MCELF_HS:=gray_encoder_4_bit.$(PROFILE).mcelf.hs
+TARGETS := $(BOOTIMAGE_NAME_MCELF)
+
+ifeq ($(DEVICE_TYPE), HS)
+   TARGETS += $(BOOTIMAGE_NAME_MCELF_HS)
+endif
 
 
 FILES_common := \
@@ -112,8 +112,8 @@ LIBS_PATH_common = \
 
 LIBS_common = \
 	-lfreertos.am261x.r5f.ti-arm-clang.${ConfigName}.lib \
-	-ldrivers.am261x.r5f.ti-arm-clang.${ConfigName}.lib \
-	-lboard.am261x.r5f.ti-arm-clang.${ConfigName}.lib \
+	-ldrivers.am261x.r5f.ti-arm-clang.freertos.${ConfigName}.lib \
+	-lboard.am261x.r5f.ti-arm-clang.freertos.${ConfigName}.lib \
 	-llibc.a \
 	-llibsysbm.a \
 
@@ -126,8 +126,8 @@ LFLAGS_common = \
 
 LIBS_NAME = \
 	freertos.am261x.r5f.ti-arm-clang.${ConfigName}.lib \
-	drivers.am261x.r5f.ti-arm-clang.${ConfigName}.lib \
-	board.am261x.r5f.ti-arm-clang.${ConfigName}.lib \
+	drivers.am261x.r5f.ti-arm-clang.freertos.${ConfigName}.lib \
+	board.am261x.r5f.ti-arm-clang.freertos.${ConfigName}.lib \
 	libc.a \
 	libsysbm.a \
 
@@ -208,13 +208,8 @@ clean:
 	@echo  Cleaning: am261x:r5fss0-0:freertos:ti-arm-clang $(OUTNAME) ...
 	$(RMDIR) $(OBJDIR)
 	$(RM) $(OUTNAME)
-	$(RM) $(BOOTIMAGE_NAME)
-	$(RM) $(BOOTIMAGE_NAME_XIP)
-	$(RM) $(BOOTIMAGE_NAME_SIGNED)
-	$(RM) $(BOOTIMAGE_NAME_HS)
-	$(RM) $(BOOTIMAGE_NAME_HS_FS)
-	$(RM) $(BOOTIMAGE_RPRC_NAME)
-	$(RM) $(BOOTIMAGE_RPRC_NAME_XIP)
+	$(RM) $(BOOTIMAGE_NAME_MCELF)
+	$(RM) $(BOOTIMAGE_NAME_MCELF_HS)
 	$(RMDIR) generated/
 
 scrub:
@@ -229,6 +224,10 @@ ifeq ($(OS),Windows_NT)
 	$(RM) \*.bin
 	$(RM) \*.lnkxml
 	$(RM) \*.ossr
+	$(RM) \*.mcelf
+	$(RM) \*.mcelf_xip
+	$(RM) \*.mcelf-enc
+	$(RM) \*.mcelf.hs
 else
 	$(RM) *.out
 	$(RM) *.map
@@ -238,6 +237,10 @@ else
 	$(RM) *.bin
 	$(RM) *.lnkxml
 	$(RM) *.ossr
+	$(RM) *.mcelf
+	$(RM) *.mcelf_xip
+	$(RM) *.mcelf-enc
+	$(RM) *.mcelf.hs
 endif
 	$(RMDIR) generated
 
@@ -276,66 +279,45 @@ BOOTIMAGE_TEMP_OUT_FILE=temp_stdout_$(PROFILE).txt
 
 BOOTIMAGE_CERT_KEY=$(APP_SIGNING_KEY)
 
-BOOTIMAGE_CORE_ID_r5fss0-0 = 4
-BOOTIMAGE_CORE_ID_r5fss0-1 = 5
-BOOTIMAGE_CORE_ID_r5fss1-0 = 6
-BOOTIMAGE_CORE_ID_r5fss1-1 = 7
-BOOTIMAGE_CORE_ID_m4fss0-0 = 14
-SBL_RUN_ADDRESS=0x70000000
+BOOTIMAGE_CORE_ID_r5fss0-0 = 0
+BOOTIMAGE_CORE_ID_r5fss0-1 = 1
+BOOTIMAGE_CORE_ID_r5fss1-0 = 2
+BOOTIMAGE_CORE_ID_r5fss1-1 = 3
+SBL_RUN_ADDRESS=0x70002000
 SBL_DEV_ID=55
 
-MULTI_CORE_IMAGE_GEN = $(SYSCFG_NODE) $(MCU_PLUS_SDK_PATH)/tools/boot/multicoreImageGen/multicoreImageGen.js
-OUTRPRC_CMD = $(SYSCFG_NODE) $(MCU_PLUS_SDK_PATH)/tools/boot/out2rprc/elf2rprc.js
-APP_IMAGE_SIGN_CMD = $(MCU_PLUS_SDK_PATH)/source/security/security_common/tools/boot/signing/appimage_x509_cert_gen.py
-
-ifeq ($(OS),Windows_NT)
-  XIPGEN_CMD=$(MCU_PLUS_SDK_PATH)/tools/boot/xipGen/xipGen.exe
-else
-  UNAME_S = $(shell uname -s)
-  ifeq ($(UNAME_S), Darwin)
-    XIPGEN_CMD=$(MCU_PLUS_SDK_PATH)/tools/boot/xipGen/xipGen.out.mac
-  else
-    XIPGEN_CMD=$(MCU_PLUS_SDK_PATH)/tools/boot/xipGen/xipGen.out
-endif
-endif
-
-MULTI_CORE_IMAGE_PARAMS = \
-	$(BOOTIMAGE_RPRC_NAME)@$(BOOTIMAGE_CORE_ID_r5fss0-0) \
+APP_IMAGE_SIGN_CMD = $(MCU_PLUS_SDK_PATH)/source/security/security_common/tools/boot/signing/mcu_appimage_x509_cert_gen.py
+MCELF_IMAGE_GEN = $(MCU_PLUS_SDK_PATH)/tools/boot/multicore-elf/genimage.py
 
-MULTI_CORE_IMAGE_PARAMS_XIP = \
-	$(BOOTIMAGE_RPRC_NAME_XIP)@$(BOOTIMAGE_CORE_ID_r5fss0-0) \
+$(BOOTIMAGE_NAME_MCELF): $(OUTNAME)
+	@echo  Boot MulticoreELF image: $(BOOTIMAGE_PATH)/$(BOOTIMAGE_NAME_MCELF) ...
+	$(PYTHON) $(MCELF_IMAGE_GEN) --core-img=$(BOOTIMAGE_CORE_ID_r5fss0-0):$(OUTNAME) --output=$(BOOTIMAGE_NAME_MCELF) --merge-segments=$(MCELF_MERGE_SEGMENTS_FLAG) --tolerance-limit=$(MCELF_MERGE_SEGMENTS_TOLERANCE_LIMIT) --ignore-context=$(MCELF_IGNORE_CONTEXT_FLAG) --xip=$(MCELF_XIP_RANGE) --xlat=$(MCELF_ADDR_TRANSLATION_PATH) --max-segment-size=$(MCELF_MAX_SEGMENT_SIZE) $(if $(oeconfig),--otfaConfigFile=$(oeconfig))
+	@echo  Boot MulticoreELF image: $(BOOTIMAGE_PATH)/$(BOOTIMAGE_NAME_MCELF) Done !!!
+	@echo  .
 
-$(BOOTIMAGE_NAME): $(OUTNAME)
-	@echo  Boot image: am261x:r5fss0-0:freertos:ti-arm-clang $(BOOTIMAGE_PATH)/$@ ...
-ifneq ($(OS),Windows_NT)
-	$(CHMOD) a+x $(XIPGEN_CMD)
-endif
-	$(OUTRPRC_CMD) $(OUTNAME) >> $(BOOTIMAGE_TEMP_OUT_FILE)
-	$(COPY) $(BOOTIMAGE_RPRC_NAME) $(BOOTIMAGE_RPRC_NAME_TMP)
-	$(RM) $(BOOTIMAGE_RPRC_NAME)
-	$(XIPGEN_CMD) -i $(BOOTIMAGE_RPRC_NAME_TMP) -o $(BOOTIMAGE_RPRC_NAME) -x $(BOOTIMAGE_RPRC_NAME_XIP) --flash-start-addr 0x60000000 -v > $(BOOTIMAGE_TEMP_OUT_FILE)
-	$(MULTI_CORE_IMAGE_GEN) --devID $(SBL_DEV_ID) --out $(BOOTIMAGE_NAME) $(MULTI_CORE_IMAGE_PARAMS) >> $(BOOTIMAGE_TEMP_OUT_FILE)
-	$(MULTI_CORE_IMAGE_GEN) --devID $(SBL_DEV_ID) --out $(BOOTIMAGE_NAME_XIP) $(MULTI_CORE_IMAGE_PARAMS_XIP) >> $(BOOTIMAGE_TEMP_OUT_FILE)
-	$(RM) $(BOOTIMAGE_RPRC_NAME_TMP)
-	$(RM) $(BOOTIMAGE_TEMP_OUT_FILE)
+$(BOOTIMAGE_NAME_MCELF_HS): $(BOOTIMAGE_NAME_MCELF)
 ifeq ($(DEVICE_TYPE), HS)
 # Sign the appimage using appimage signing script
 ifeq ($(ENC_ENABLED),no)
+ifeq ($(RSASSAPSS_ENABLED),no)
 	@echo Boot image signing: Encryption is disabled.
-	$(PYTHON) $(APP_IMAGE_SIGN_CMD) --bin $(BOOTIMAGE_NAME) --authtype 1 --key $(APP_SIGNING_KEY) --output $(BOOTIMAGE_NAME_HS)
+	$(PYTHON) $(APP_IMAGE_SIGN_CMD) --bin $(BOOTIMAGE_NAME_MCELF) --key $(APP_SIGNING_KEY) --sign_key_id $(APP_SIGNING_KEY_KEYRING_ID) --hash_algo $(APP_SIGNING_HASH_ALGO) --output $(BOOTIMAGE_NAME_MCELF_HS)
 else
-	@echo Boot image signing: Encryption is enabled.
-	$(PYTHON) $(APP_IMAGE_SIGN_CMD) --bin $(BOOTIMAGE_NAME) --authtype 1 --key $(APP_SIGNING_KEY) --enc y --enckey $(APP_ENCRYPTION_KEY) --output $(BOOTIMAGE_NAME_HS)
-	$(RM) $(BOOTIMAGE_NAME)-enc
+	@echo Boot image signing: Encryption is disabled. RSASSAPSS is enabled.
+	$(PYTHON) $(APP_IMAGE_SIGN_CMD) --bin $(BOOTIMAGE_NAME_MCELF) --key $(APP_SIGNING_KEY) --sign_key_id $(APP_SIGNING_KEY_KEYRING_ID) --hash_algo $(APP_SIGNING_HASH_ALGO) --pss_saltlen $(APP_SIGNING_SALT_LENGTH) --output $(BOOTIMAGE_NAME_MCELF_HS) --rsassa_pss
 endif
-	$(RM) $(BOOTIMAGE_NAME)
-	@echo  Boot image: am261x:r5fss0-0:freertos:ti-arm-clang $(BOOTIMAGE_PATH)/$(BOOTIMAGE_NAME_HS) Done !!!
-	@echo  .
 else
-# Sign the appimage for HS-FS using appimage signing script
-	$(PYTHON) $(APP_IMAGE_SIGN_CMD) --bin $(BOOTIMAGE_NAME) --authtype 1 --key $(APP_SIGNING_KEY) --output $(BOOTIMAGE_NAME_HS_FS)
-	$(RM) $(BOOTIMAGE_NAME)
-	@echo  Boot image: am261x:r5fss0-0:freertos:ti-arm-clang $(BOOTIMAGE_PATH)/$(BOOTIMAGE_NAME_HS_FS) Done !!!
+ifeq ($(RSASSAPSS_ENABLED),no)
+	@echo Boot image signing: Encryption is enabled.
+	$(PYTHON) $(APP_IMAGE_SIGN_CMD) --bin $(BOOTIMAGE_NAME_MCELF) --key $(APP_SIGNING_KEY) --enc y --enckey $(APP_ENCRYPTION_KEY) --kd-salt $(KD_SALT) --sign_key_id $(APP_SIGNING_KEY_KEYRING_ID) --enc_key_id $(APP_ENCRYPTION_KEY_KEYRING_ID) --hash_algo $(APP_SIGNING_HASH_ALGO) --output $(BOOTIMAGE_NAME_MCELF_HS)
+	$(RM) $(BOOTIMAGE_NAME_MCELF)-enc
+else
+	@echo Boot image signing: Encryption is enabled. RSASSAPSS is enabled.
+	$(PYTHON) $(APP_IMAGE_SIGN_CMD) --bin $(BOOTIMAGE_NAME_MCELF) --key $(APP_SIGNING_KEY) --enc y --enckey $(APP_ENCRYPTION_KEY) --kd-salt $(KD_SALT) --sign_key_id $(APP_SIGNING_KEY_KEYRING_ID) --enc_key_id $(APP_ENCRYPTION_KEY_KEYRING_ID) --hash_algo $(APP_SIGNING_HASH_ALGO) --pss_saltlen $(APP_SIGNING_SALT_LENGTH) --output $(BOOTIMAGE_NAME_MCELF_HS) --rsassa_pss
+	$(RM) $(BOOTIMAGE_NAME_MCELF)-enc
+endif
+endif
+	@echo  Boot image: am261x:r5fss0-0:freertos:ti-arm-clang $(BOOTIMAGE_PATH)/$(BOOTIMAGE_NAME_MCELF_HS) Done !!!
 	@echo  .
 endif
 
diff --git a/examples/gray_encoder_4_bit/mcuplus/am261x-lp/r5fss0-0_freertos/ti-arm-clang/makefile.defs b/examples/gray_encoder_4_bit/mcuplus/am261x-lp/r5fss0-0_freertos/ti-arm-clang/makefile.defs
new file mode 100644
index 0000000..4f41ac3
--- /dev/null
+++ b/examples/gray_encoder_4_bit/mcuplus/am261x-lp/r5fss0-0_freertos/ti-arm-clang/makefile.defs
@@ -0,0 +1,14 @@
+GEN_FILES__QUOTED += \
+*.appimage* \
+*.appimage_xip \
+*.rprc* \
+*.rprc_xip \
+*.tiimage* \
+*.bin \
+*.lnkxml \
+*.map \
+*.ossr
+
+GEN_FILES__QUOTED += \
+*.mcelf* \
+*.mcelf_xip
diff --git a/examples/gray_encoder_4_bit/mcuplus/am261x-lp/r5fss0-0_freertos/ti-arm-clang/makefile_ccs_bootimage_gen b/examples/gray_encoder_4_bit/mcuplus/am261x-lp/r5fss0-0_freertos/ti-arm-clang/makefile_ccs_bootimage_gen
index 9c2450e..fe5c5f6 100644
--- a/examples/gray_encoder_4_bit/mcuplus/am261x-lp/r5fss0-0_freertos/ti-arm-clang/makefile_ccs_bootimage_gen
+++ b/examples/gray_encoder_4_bit/mcuplus/am261x-lp/r5fss0-0_freertos/ti-arm-clang/makefile_ccs_bootimage_gen
@@ -25,12 +25,13 @@ endif
 
 OUTFILE=$(PROFILE)/$(OUTNAME).out
 BOOTIMAGE_PATH=$(abspath ${PROFILE})
-BOOTIMAGE_NAME:=$(BOOTIMAGE_PATH)/$(OUTNAME).appimage
-BOOTIMAGE_NAME_XIP:=$(BOOTIMAGE_PATH)/$(OUTNAME).appimage_xip
-BOOTIMAGE_NAME_SIGNED:=$(BOOTIMAGE_PATH)/$(OUTNAME).appimage.signed
-BOOTIMAGE_RPRC_NAME:=$(BOOTIMAGE_PATH)/$(OUTNAME).rprc
-BOOTIMAGE_RPRC_NAME_XIP:=$(BOOTIMAGE_PATH)/$(OUTNAME).rprc_xip
-BOOTIMAGE_RPRC_NAME_TMP:=$(BOOTIMAGE_PATH)/$(OUTNAME).rprc_tmp
+BOOTIMAGE_NAME_MCELF:=$(BOOTIMAGE_PATH)/$(OUTNAME).mcelf
+BOOTIMAGE_NAME_MCELF_HS:=$(BOOTIMAGE_PATH)/$(OUTNAME).mcelf.hs
+TARGETS += $(BOOTIMAGE_NAME_MCELF)
+TARGETS += $(BOOTIMAGE_NAME_MCELF_HS)
+ifeq ($(DEVICE_TYPE), HS)
+   TARGETS += $(BOOTIMAGE_NAME_MCELF_HS)
+endif
 
 #
 # Generation of boot image which can be loaded by Secondary Boot Loader (SBL)
@@ -45,69 +46,50 @@ else
 endif
 BOOTIMAGE_TEMP_OUT_FILE=$(PROFILE)/temp_stdout_$(PROFILE).txt
 
-BOOTIMAGE_CORE_ID_r5fss0-0 = 4
-BOOTIMAGE_CORE_ID_r5fss0-1 = 5
-BOOTIMAGE_CORE_ID_r5fss1-0 = 6
-BOOTIMAGE_CORE_ID_r5fss1-1 = 7
-BOOTIMAGE_CORE_ID_m4fss0-0 = 14
-SBL_RUN_ADDRESS=0x70000000
+BOOTIMAGE_CORE_ID_r5fss0-0 = 0
+BOOTIMAGE_CORE_ID_r5fss0-1 = 1
+BOOTIMAGE_CORE_ID_r5fss1-0 = 2
+BOOTIMAGE_CORE_ID_r5fss1-1 = 3
+SBL_RUN_ADDRESS=0x70002000
 SBL_DEV_ID=55
 
-MULTI_CORE_IMAGE_GEN = $(CCS_NODE) $(MCU_PLUS_SDK_PATH)/tools/boot/multicoreImageGen/multicoreImageGen.js
-OUTRPRC_CMD = $(CCS_NODE) $(MCU_PLUS_SDK_PATH)/tools/boot/out2rprc/elf2rprc.js
-APP_IMAGE_SIGN_CMD = $(MCU_PLUS_SDK_PATH)/source/security/security_common/tools/boot/signing/appimage_x509_cert_gen.py
-
-ifeq ($(OS),Windows_NT)
-  XIPGEN_CMD=$(MCU_PLUS_SDK_PATH)/tools/boot/xipGen/xipGen.exe
-else
-  UNAME_S = $(shell uname -s)
-  ifeq ($(UNAME_S), Darwin)
-    XIPGEN_CMD=$(MCU_PLUS_SDK_PATH)/tools/boot/xipGen/xipGen.out.mac
-  else
-    XIPGEN_CMD=$(MCU_PLUS_SDK_PATH)/tools/boot/xipGen/xipGen.out
-endif
-endif
-
-MULTI_CORE_IMAGE_PARAMS = \
-	$(BOOTIMAGE_RPRC_NAME)@$(BOOTIMAGE_CORE_ID_r5fss0-0) \
-
-MULTI_CORE_IMAGE_PARAMS_XIP = \
-	$(BOOTIMAGE_RPRC_NAME_XIP)@$(BOOTIMAGE_CORE_ID_r5fss0-0)  \
+APP_IMAGE_SIGN_CMD = $(MCU_PLUS_SDK_PATH)/source/security/security_common/tools/boot/signing/mcu_appimage_x509_cert_gen.py
+MCELF_IMAGE_GEN = $(MCU_PLUS_SDK_PATH)/tools/boot/multicore-elf/genimage.py
 
 all:
 ifeq ($(CCS_IDE_MODE),cloud)
 #	No post build steps
 else
-	@echo  Boot image: am261x:r5fss0-0:freertos:ti-arm-clang $(BOOTIMAGE_NAME)  ...
-	$(OUTRPRC_CMD) $(OUTFILE) >> $(BOOTIMAGE_TEMP_OUT_FILE)
-	$(COPY) $(OUTNAME).rprc $(BOOTIMAGE_RPRC_NAME)
-	$(COPY) $(BOOTIMAGE_RPRC_NAME) $(BOOTIMAGE_RPRC_NAME_TMP)
-	$(RM) $(BOOTIMAGE_RPRC_NAME)
-	$(XIPGEN_CMD) -i $(BOOTIMAGE_RPRC_NAME_TMP) -o $(BOOTIMAGE_RPRC_NAME) -x $(BOOTIMAGE_RPRC_NAME_XIP) --flash-start-addr 0x60000000 -v > $(BOOTIMAGE_TEMP_OUT_FILE)
-	$(MULTI_CORE_IMAGE_GEN) --devID $(SBL_DEV_ID) --out $(BOOTIMAGE_NAME) $(MULTI_CORE_IMAGE_PARAMS) >> $(BOOTIMAGE_TEMP_OUT_FILE)
-	$(MULTI_CORE_IMAGE_GEN) --devID $(SBL_DEV_ID) --out $(BOOTIMAGE_NAME_XIP) $(MULTI_CORE_IMAGE_PARAMS_XIP) >> $(BOOTIMAGE_TEMP_OUT_FILE)
-ifeq ($(DEVICE_TYPE),HS)
+
+	@echo  Boot multi-core ELF image: am261x:r5fss0-0:freertos:ti-arm-clang $(BOOTIMAGE_NAME_MCELF) ...
+
+	$(PYTHON) $(MCELF_IMAGE_GEN) --core-img=$(BOOTIMAGE_CORE_ID_r5fss0-0):$(OUTFILE) --output=$(BOOTIMAGE_NAME_MCELF) --merge-segments=$(MCELF_MERGE_SEGMENTS_FLAG) --tolerance-limit=$(MCELF_MERGE_SEGMENTS_TOLERANCE_LIMIT) --ignore-context=$(MCELF_IGNORE_CONTEXT_FLAG) --xip=$(MCELF_XIP_RANGE) --xlat=$(MCELF_ADDR_TRANSLATION_PATH) --max-segment-size=$(MCELF_MAX_SEGMENT_SIZE)
+
+	@echo  Boot multi-core ELF image: $(BOOTIMAGE_NAME_MCELF) Done !!!
+	@echo  .
+
+ifeq ($(DEVICE_TYPE), HS)
 # Sign the appimage using appimage signing script
 ifeq ($(ENC_ENABLED),no)
+ifeq ($(RSASSAPSS_ENABLED),no)
 	@echo Boot image signing: Encryption is disabled.
-	$(PYTHON) $(APP_IMAGE_SIGN_CMD) --bin $(BOOTIMAGE_NAME) --authtype 1 --key $(APP_SIGNING_KEY) --output $(BOOTIMAGE_NAME).hs
-	$(RM) $(BOOTIMAGE_NAME)
+	$(PYTHON) $(APP_IMAGE_SIGN_CMD) --bin $(BOOTIMAGE_NAME_MCELF) --key $(APP_SIGNING_KEY) --sign_key_id $(APP_SIGNING_KEY_KEYRING_ID) --hash_algo $(APP_SIGNING_HASH_ALGO) --output $(BOOTIMAGE_NAME_MCELF_HS)
 else
-	@echo Boot image signing: Encryption is enabled.
-	$(PYTHON) $(APP_IMAGE_SIGN_CMD) --bin $(BOOTIMAGE_NAME) --authtype 1 --key $(APP_SIGNING_KEY) --enc y --enckey $(APP_ENCRYPTION_KEY) --output $(BOOTIMAGE_NAME).hs
-	$(RM) $(BOOTIMAGE_NAME)-enc
+	@echo Boot image signing: Encryption is disabled. RSASSA-PSS is enabled.
+	$(PYTHON) $(APP_IMAGE_SIGN_CMD) --bin $(BOOTIMAGE_NAME_MCELF) --key $(APP_SIGNING_KEY) --sign_key_id $(APP_SIGNING_KEY_KEYRING_ID) --hash_algo $(APP_SIGNING_HASH_ALGO) --pss_saltlen $(APP_SIGNING_SALT_LENGTH) --output $(BOOTIMAGE_NAME_MCELF_HS) --rsassa_pss
 endif
 else
-# Sign the appimage for HS-FS using appimage signing script
-	$(PYTHON) $(APP_IMAGE_SIGN_CMD) --bin $(BOOTIMAGE_NAME) --authtype 1 --key $(APP_SIGNING_KEY) --output $(BOOTIMAGE_NAME).hs_fs
-	$(RM) $(BOOTIMAGE_NAME)
-endif
-	$(RM) $(BOOTIMAGE_RPRC_NAME_TMP)
-ifeq ($(DEVICE_TYPE),HS)
-	@echo  Boot image: am261x:r5fss0-0:freertos:ti-arm-clang $(BOOTIMAGE_NAME).hs Done !!!
-	@echo  .
+ifeq ($(RSASSAPSS_ENABLED),no)
+	@echo Boot image signing: Encryption is enabled.
+	$(PYTHON) $(APP_IMAGE_SIGN_CMD) --bin $(BOOTIMAGE_NAME_MCELF) --key $(APP_SIGNING_KEY) --enc y --enckey $(APP_ENCRYPTION_KEY) --kd-salt $(KD_SALT) --sign_key_id $(APP_SIGNING_KEY_KEYRING_ID) --enc_key_id $(APP_ENCRYPTION_KEY_KEYRING_ID) --hash_algo $(APP_SIGNING_HASH_ALGO) --output $(BOOTIMAGE_NAME_MCELF_HS)
+	$(RM) $(BOOTIMAGE_NAME_MCELF)-enc
 else
-	@echo  Boot image: am261x:r5fss0-0:freertos:ti-arm-clang $(BOOTIMAGE_NAME).hs_fs Done !!!
+	@echo Boot image signing: Encryption is enabled. RSASSA-PSS is enabled.
+	$(PYTHON) $(APP_IMAGE_SIGN_CMD) --bin $(BOOTIMAGE_NAME_MCELF) --key $(APP_SIGNING_KEY) --enc y --enckey $(APP_ENCRYPTION_KEY) --kd-salt $(KD_SALT) --sign_key_id $(APP_SIGNING_KEY_KEYRING_ID) --enc_key_id $(APP_ENCRYPTION_KEY_KEYRING_ID) --hash_algo $(APP_SIGNING_HASH_ALGO) --pss_saltlen $(APP_SIGNING_SALT_LENGTH) --output $(BOOTIMAGE_NAME_MCELF_HS) --rsassa_pss
+	$(RM) $(BOOTIMAGE_NAME_MCELF)-enc
+endif
+endif
+	@echo  Boot image: am261x:r5fss0-0:freertos:ti-arm-clang $(BOOTIMAGE_PATH)/$(BOOTIMAGE_NAME_MCELF_HS) Done !!!
 	@echo  .
 endif
 endif
diff --git a/examples/incremental_spi/mcuplus/am261x-lp/r5fss0-0_freertos/ti-arm-clang/example.projectspec b/examples/incremental_spi/mcuplus/am261x-lp/r5fss0-0_freertos/ti-arm-clang/example.projectspec
index 3c09af3..c0ca4d7 100644
--- a/examples/incremental_spi/mcuplus/am261x-lp/r5fss0-0_freertos/ti-arm-clang/example.projectspec
+++ b/examples/incremental_spi/mcuplus/am261x-lp/r5fss0-0_freertos/ti-arm-clang/example.projectspec
@@ -81,8 +81,8 @@
             "
             linkerBuildOptions="
                 -lfreertos.am261x.r5f.ti-arm-clang.debug.lib
-                -ldrivers.am261x.r5f.ti-arm-clang.debug.lib
-                -lboard.am261x.r5f.ti-arm-clang.debug.lib
+                -ldrivers.am261x.r5f.ti-arm-clang.freertos.debug.lib
+                -lboard.am261x.r5f.ti-arm-clang.freertos.debug.lib
                 -llibc.a
                 -llibsysbm.a
             "
@@ -93,8 +93,8 @@
             "
             linkerBuildOptions="
                 -lfreertos.am261x.r5f.ti-arm-clang.release.lib
-                -ldrivers.am261x.r5f.ti-arm-clang.release.lib
-                -lboard.am261x.r5f.ti-arm-clang.release.lib
+                -ldrivers.am261x.r5f.ti-arm-clang.freertos.release.lib
+                -lboard.am261x.r5f.ti-arm-clang.freertos.release.lib
                 -llibc.a
                 -llibsysbm.a
             "
diff --git a/examples/incremental_spi/mcuplus/am261x-lp/r5fss0-0_freertos/ti-arm-clang/makefile b/examples/incremental_spi/mcuplus/am261x-lp/r5fss0-0_freertos/ti-arm-clang/makefile
index 3075676..bc4a582 100644
--- a/examples/incremental_spi/mcuplus/am261x-lp/r5fss0-0_freertos/ti-arm-clang/makefile
+++ b/examples/incremental_spi/mcuplus/am261x-lp/r5fss0-0_freertos/ti-arm-clang/makefile
@@ -29,15 +29,15 @@ OUTNAME:=incremental_spi.$(PROFILE).out
 COREOUTNAME:=incremental_spi.$(PROFILE).optishare.out
 
 BOOTIMAGE_PATH=$(abspath .)
-BOOTIMAGE_NAME:=incremental_spi.$(PROFILE).appimage
-BOOTIMAGE_NAME_XIP:=incremental_spi.$(PROFILE).appimage_xip
-BOOTIMAGE_NAME_SIGNED:=incremental_spi.$(PROFILE).appimage.signed
-BOOTIMAGE_RPRC_NAME:=incremental_spi.$(PROFILE).rprc
-BOOTIMAGE_RPRC_NAME_XIP:=incremental_spi.$(PROFILE).rprc_xip
-BOOTIMAGE_RPRC_NAME_TMP:=incremental_spi.$(PROFILE).rprc_tmp
-BOOTIMAGE_NAME_HS:=incremental_spi.$(PROFILE).appimage.hs
-BOOTIMAGE_NAME_HS_FS:=incremental_spi.$(PROFILE).appimage.hs_fs
-TARGETS := $(BOOTIMAGE_NAME)
+oeconfig?=
+
+BOOTIMAGE_NAME_MCELF:=incremental_spi.$(PROFILE).mcelf
+BOOTIMAGE_NAME_MCELF_HS:=incremental_spi.$(PROFILE).mcelf.hs
+TARGETS := $(BOOTIMAGE_NAME_MCELF)
+
+ifeq ($(DEVICE_TYPE), HS)
+   TARGETS += $(BOOTIMAGE_NAME_MCELF_HS)
+endif
 
 
 FILES_common := \
@@ -112,8 +112,8 @@ LIBS_PATH_common = \
 
 LIBS_common = \
 	-lfreertos.am261x.r5f.ti-arm-clang.${ConfigName}.lib \
-	-ldrivers.am261x.r5f.ti-arm-clang.${ConfigName}.lib \
-	-lboard.am261x.r5f.ti-arm-clang.${ConfigName}.lib \
+	-ldrivers.am261x.r5f.ti-arm-clang.freertos.${ConfigName}.lib \
+	-lboard.am261x.r5f.ti-arm-clang.freertos.${ConfigName}.lib \
 	-llibc.a \
 	-llibsysbm.a \
 
@@ -126,8 +126,8 @@ LFLAGS_common = \
 
 LIBS_NAME = \
 	freertos.am261x.r5f.ti-arm-clang.${ConfigName}.lib \
-	drivers.am261x.r5f.ti-arm-clang.${ConfigName}.lib \
-	board.am261x.r5f.ti-arm-clang.${ConfigName}.lib \
+	drivers.am261x.r5f.ti-arm-clang.freertos.${ConfigName}.lib \
+	board.am261x.r5f.ti-arm-clang.freertos.${ConfigName}.lib \
 	libc.a \
 	libsysbm.a \
 
@@ -208,13 +208,8 @@ clean:
 	@echo  Cleaning: am261x:r5fss0-0:freertos:ti-arm-clang $(OUTNAME) ...
 	$(RMDIR) $(OBJDIR)
 	$(RM) $(OUTNAME)
-	$(RM) $(BOOTIMAGE_NAME)
-	$(RM) $(BOOTIMAGE_NAME_XIP)
-	$(RM) $(BOOTIMAGE_NAME_SIGNED)
-	$(RM) $(BOOTIMAGE_NAME_HS)
-	$(RM) $(BOOTIMAGE_NAME_HS_FS)
-	$(RM) $(BOOTIMAGE_RPRC_NAME)
-	$(RM) $(BOOTIMAGE_RPRC_NAME_XIP)
+	$(RM) $(BOOTIMAGE_NAME_MCELF)
+	$(RM) $(BOOTIMAGE_NAME_MCELF_HS)
 	$(RMDIR) generated/
 
 scrub:
@@ -229,6 +224,10 @@ ifeq ($(OS),Windows_NT)
 	$(RM) \*.bin
 	$(RM) \*.lnkxml
 	$(RM) \*.ossr
+	$(RM) \*.mcelf
+	$(RM) \*.mcelf_xip
+	$(RM) \*.mcelf-enc
+	$(RM) \*.mcelf.hs
 else
 	$(RM) *.out
 	$(RM) *.map
@@ -238,6 +237,10 @@ else
 	$(RM) *.bin
 	$(RM) *.lnkxml
 	$(RM) *.ossr
+	$(RM) *.mcelf
+	$(RM) *.mcelf_xip
+	$(RM) *.mcelf-enc
+	$(RM) *.mcelf.hs
 endif
 	$(RMDIR) generated
 
@@ -276,66 +279,45 @@ BOOTIMAGE_TEMP_OUT_FILE=temp_stdout_$(PROFILE).txt
 
 BOOTIMAGE_CERT_KEY=$(APP_SIGNING_KEY)
 
-BOOTIMAGE_CORE_ID_r5fss0-0 = 4
-BOOTIMAGE_CORE_ID_r5fss0-1 = 5
-BOOTIMAGE_CORE_ID_r5fss1-0 = 6
-BOOTIMAGE_CORE_ID_r5fss1-1 = 7
-BOOTIMAGE_CORE_ID_m4fss0-0 = 14
-SBL_RUN_ADDRESS=0x70000000
+BOOTIMAGE_CORE_ID_r5fss0-0 = 0
+BOOTIMAGE_CORE_ID_r5fss0-1 = 1
+BOOTIMAGE_CORE_ID_r5fss1-0 = 2
+BOOTIMAGE_CORE_ID_r5fss1-1 = 3
+SBL_RUN_ADDRESS=0x70002000
 SBL_DEV_ID=55
 
-MULTI_CORE_IMAGE_GEN = $(SYSCFG_NODE) $(MCU_PLUS_SDK_PATH)/tools/boot/multicoreImageGen/multicoreImageGen.js
-OUTRPRC_CMD = $(SYSCFG_NODE) $(MCU_PLUS_SDK_PATH)/tools/boot/out2rprc/elf2rprc.js
-APP_IMAGE_SIGN_CMD = $(MCU_PLUS_SDK_PATH)/source/security/security_common/tools/boot/signing/appimage_x509_cert_gen.py
-
-ifeq ($(OS),Windows_NT)
-  XIPGEN_CMD=$(MCU_PLUS_SDK_PATH)/tools/boot/xipGen/xipGen.exe
-else
-  UNAME_S = $(shell uname -s)
-  ifeq ($(UNAME_S), Darwin)
-    XIPGEN_CMD=$(MCU_PLUS_SDK_PATH)/tools/boot/xipGen/xipGen.out.mac
-  else
-    XIPGEN_CMD=$(MCU_PLUS_SDK_PATH)/tools/boot/xipGen/xipGen.out
-endif
-endif
-
-MULTI_CORE_IMAGE_PARAMS = \
-	$(BOOTIMAGE_RPRC_NAME)@$(BOOTIMAGE_CORE_ID_r5fss0-0) \
+APP_IMAGE_SIGN_CMD = $(MCU_PLUS_SDK_PATH)/source/security/security_common/tools/boot/signing/mcu_appimage_x509_cert_gen.py
+MCELF_IMAGE_GEN = $(MCU_PLUS_SDK_PATH)/tools/boot/multicore-elf/genimage.py
 
-MULTI_CORE_IMAGE_PARAMS_XIP = \
-	$(BOOTIMAGE_RPRC_NAME_XIP)@$(BOOTIMAGE_CORE_ID_r5fss0-0) \
+$(BOOTIMAGE_NAME_MCELF): $(OUTNAME)
+	@echo  Boot MulticoreELF image: $(BOOTIMAGE_PATH)/$(BOOTIMAGE_NAME_MCELF) ...
+	$(PYTHON) $(MCELF_IMAGE_GEN) --core-img=$(BOOTIMAGE_CORE_ID_r5fss0-0):$(OUTNAME) --output=$(BOOTIMAGE_NAME_MCELF) --merge-segments=$(MCELF_MERGE_SEGMENTS_FLAG) --tolerance-limit=$(MCELF_MERGE_SEGMENTS_TOLERANCE_LIMIT) --ignore-context=$(MCELF_IGNORE_CONTEXT_FLAG) --xip=$(MCELF_XIP_RANGE) --xlat=$(MCELF_ADDR_TRANSLATION_PATH) --max-segment-size=$(MCELF_MAX_SEGMENT_SIZE) $(if $(oeconfig),--otfaConfigFile=$(oeconfig))
+	@echo  Boot MulticoreELF image: $(BOOTIMAGE_PATH)/$(BOOTIMAGE_NAME_MCELF) Done !!!
+	@echo  .
 
-$(BOOTIMAGE_NAME): $(OUTNAME)
-	@echo  Boot image: am261x:r5fss0-0:freertos:ti-arm-clang $(BOOTIMAGE_PATH)/$@ ...
-ifneq ($(OS),Windows_NT)
-	$(CHMOD) a+x $(XIPGEN_CMD)
-endif
-	$(OUTRPRC_CMD) $(OUTNAME) >> $(BOOTIMAGE_TEMP_OUT_FILE)
-	$(COPY) $(BOOTIMAGE_RPRC_NAME) $(BOOTIMAGE_RPRC_NAME_TMP)
-	$(RM) $(BOOTIMAGE_RPRC_NAME)
-	$(XIPGEN_CMD) -i $(BOOTIMAGE_RPRC_NAME_TMP) -o $(BOOTIMAGE_RPRC_NAME) -x $(BOOTIMAGE_RPRC_NAME_XIP) --flash-start-addr 0x60000000 -v > $(BOOTIMAGE_TEMP_OUT_FILE)
-	$(MULTI_CORE_IMAGE_GEN) --devID $(SBL_DEV_ID) --out $(BOOTIMAGE_NAME) $(MULTI_CORE_IMAGE_PARAMS) >> $(BOOTIMAGE_TEMP_OUT_FILE)
-	$(MULTI_CORE_IMAGE_GEN) --devID $(SBL_DEV_ID) --out $(BOOTIMAGE_NAME_XIP) $(MULTI_CORE_IMAGE_PARAMS_XIP) >> $(BOOTIMAGE_TEMP_OUT_FILE)
-	$(RM) $(BOOTIMAGE_RPRC_NAME_TMP)
-	$(RM) $(BOOTIMAGE_TEMP_OUT_FILE)
+$(BOOTIMAGE_NAME_MCELF_HS): $(BOOTIMAGE_NAME_MCELF)
 ifeq ($(DEVICE_TYPE), HS)
 # Sign the appimage using appimage signing script
 ifeq ($(ENC_ENABLED),no)
+ifeq ($(RSASSAPSS_ENABLED),no)
 	@echo Boot image signing: Encryption is disabled.
-	$(PYTHON) $(APP_IMAGE_SIGN_CMD) --bin $(BOOTIMAGE_NAME) --authtype 1 --key $(APP_SIGNING_KEY) --output $(BOOTIMAGE_NAME_HS)
+	$(PYTHON) $(APP_IMAGE_SIGN_CMD) --bin $(BOOTIMAGE_NAME_MCELF) --key $(APP_SIGNING_KEY) --sign_key_id $(APP_SIGNING_KEY_KEYRING_ID) --hash_algo $(APP_SIGNING_HASH_ALGO) --output $(BOOTIMAGE_NAME_MCELF_HS)
 else
-	@echo Boot image signing: Encryption is enabled.
-	$(PYTHON) $(APP_IMAGE_SIGN_CMD) --bin $(BOOTIMAGE_NAME) --authtype 1 --key $(APP_SIGNING_KEY) --enc y --enckey $(APP_ENCRYPTION_KEY) --output $(BOOTIMAGE_NAME_HS)
-	$(RM) $(BOOTIMAGE_NAME)-enc
+	@echo Boot image signing: Encryption is disabled. RSASSAPSS is enabled.
+	$(PYTHON) $(APP_IMAGE_SIGN_CMD) --bin $(BOOTIMAGE_NAME_MCELF) --key $(APP_SIGNING_KEY) --sign_key_id $(APP_SIGNING_KEY_KEYRING_ID) --hash_algo $(APP_SIGNING_HASH_ALGO) --pss_saltlen $(APP_SIGNING_SALT_LENGTH) --output $(BOOTIMAGE_NAME_MCELF_HS) --rsassa_pss
 endif
-	$(RM) $(BOOTIMAGE_NAME)
-	@echo  Boot image: am261x:r5fss0-0:freertos:ti-arm-clang $(BOOTIMAGE_PATH)/$(BOOTIMAGE_NAME_HS) Done !!!
-	@echo  .
 else
-# Sign the appimage for HS-FS using appimage signing script
-	$(PYTHON) $(APP_IMAGE_SIGN_CMD) --bin $(BOOTIMAGE_NAME) --authtype 1 --key $(APP_SIGNING_KEY) --output $(BOOTIMAGE_NAME_HS_FS)
-	$(RM) $(BOOTIMAGE_NAME)
-	@echo  Boot image: am261x:r5fss0-0:freertos:ti-arm-clang $(BOOTIMAGE_PATH)/$(BOOTIMAGE_NAME_HS_FS) Done !!!
+ifeq ($(RSASSAPSS_ENABLED),no)
+	@echo Boot image signing: Encryption is enabled.
+	$(PYTHON) $(APP_IMAGE_SIGN_CMD) --bin $(BOOTIMAGE_NAME_MCELF) --key $(APP_SIGNING_KEY) --enc y --enckey $(APP_ENCRYPTION_KEY) --kd-salt $(KD_SALT) --sign_key_id $(APP_SIGNING_KEY_KEYRING_ID) --enc_key_id $(APP_ENCRYPTION_KEY_KEYRING_ID) --hash_algo $(APP_SIGNING_HASH_ALGO) --output $(BOOTIMAGE_NAME_MCELF_HS)
+	$(RM) $(BOOTIMAGE_NAME_MCELF)-enc
+else
+	@echo Boot image signing: Encryption is enabled. RSASSAPSS is enabled.
+	$(PYTHON) $(APP_IMAGE_SIGN_CMD) --bin $(BOOTIMAGE_NAME_MCELF) --key $(APP_SIGNING_KEY) --enc y --enckey $(APP_ENCRYPTION_KEY) --kd-salt $(KD_SALT) --sign_key_id $(APP_SIGNING_KEY_KEYRING_ID) --enc_key_id $(APP_ENCRYPTION_KEY_KEYRING_ID) --hash_algo $(APP_SIGNING_HASH_ALGO) --pss_saltlen $(APP_SIGNING_SALT_LENGTH) --output $(BOOTIMAGE_NAME_MCELF_HS) --rsassa_pss
+	$(RM) $(BOOTIMAGE_NAME_MCELF)-enc
+endif
+endif
+	@echo  Boot image: am261x:r5fss0-0:freertos:ti-arm-clang $(BOOTIMAGE_PATH)/$(BOOTIMAGE_NAME_MCELF_HS) Done !!!
 	@echo  .
 endif
 
diff --git a/examples/incremental_spi/mcuplus/am261x-lp/r5fss0-0_freertos/ti-arm-clang/makefile.defs b/examples/incremental_spi/mcuplus/am261x-lp/r5fss0-0_freertos/ti-arm-clang/makefile.defs
new file mode 100644
index 0000000..4f41ac3
--- /dev/null
+++ b/examples/incremental_spi/mcuplus/am261x-lp/r5fss0-0_freertos/ti-arm-clang/makefile.defs
@@ -0,0 +1,14 @@
+GEN_FILES__QUOTED += \
+*.appimage* \
+*.appimage_xip \
+*.rprc* \
+*.rprc_xip \
+*.tiimage* \
+*.bin \
+*.lnkxml \
+*.map \
+*.ossr
+
+GEN_FILES__QUOTED += \
+*.mcelf* \
+*.mcelf_xip
diff --git a/examples/incremental_spi/mcuplus/am261x-lp/r5fss0-0_freertos/ti-arm-clang/makefile_ccs_bootimage_gen b/examples/incremental_spi/mcuplus/am261x-lp/r5fss0-0_freertos/ti-arm-clang/makefile_ccs_bootimage_gen
index 9c2450e..fe5c5f6 100644
--- a/examples/incremental_spi/mcuplus/am261x-lp/r5fss0-0_freertos/ti-arm-clang/makefile_ccs_bootimage_gen
+++ b/examples/incremental_spi/mcuplus/am261x-lp/r5fss0-0_freertos/ti-arm-clang/makefile_ccs_bootimage_gen
@@ -25,12 +25,13 @@ endif
 
 OUTFILE=$(PROFILE)/$(OUTNAME).out
 BOOTIMAGE_PATH=$(abspath ${PROFILE})
-BOOTIMAGE_NAME:=$(BOOTIMAGE_PATH)/$(OUTNAME).appimage
-BOOTIMAGE_NAME_XIP:=$(BOOTIMAGE_PATH)/$(OUTNAME).appimage_xip
-BOOTIMAGE_NAME_SIGNED:=$(BOOTIMAGE_PATH)/$(OUTNAME).appimage.signed
-BOOTIMAGE_RPRC_NAME:=$(BOOTIMAGE_PATH)/$(OUTNAME).rprc
-BOOTIMAGE_RPRC_NAME_XIP:=$(BOOTIMAGE_PATH)/$(OUTNAME).rprc_xip
-BOOTIMAGE_RPRC_NAME_TMP:=$(BOOTIMAGE_PATH)/$(OUTNAME).rprc_tmp
+BOOTIMAGE_NAME_MCELF:=$(BOOTIMAGE_PATH)/$(OUTNAME).mcelf
+BOOTIMAGE_NAME_MCELF_HS:=$(BOOTIMAGE_PATH)/$(OUTNAME).mcelf.hs
+TARGETS += $(BOOTIMAGE_NAME_MCELF)
+TARGETS += $(BOOTIMAGE_NAME_MCELF_HS)
+ifeq ($(DEVICE_TYPE), HS)
+   TARGETS += $(BOOTIMAGE_NAME_MCELF_HS)
+endif
 
 #
 # Generation of boot image which can be loaded by Secondary Boot Loader (SBL)
@@ -45,69 +46,50 @@ else
 endif
 BOOTIMAGE_TEMP_OUT_FILE=$(PROFILE)/temp_stdout_$(PROFILE).txt
 
-BOOTIMAGE_CORE_ID_r5fss0-0 = 4
-BOOTIMAGE_CORE_ID_r5fss0-1 = 5
-BOOTIMAGE_CORE_ID_r5fss1-0 = 6
-BOOTIMAGE_CORE_ID_r5fss1-1 = 7
-BOOTIMAGE_CORE_ID_m4fss0-0 = 14
-SBL_RUN_ADDRESS=0x70000000
+BOOTIMAGE_CORE_ID_r5fss0-0 = 0
+BOOTIMAGE_CORE_ID_r5fss0-1 = 1
+BOOTIMAGE_CORE_ID_r5fss1-0 = 2
+BOOTIMAGE_CORE_ID_r5fss1-1 = 3
+SBL_RUN_ADDRESS=0x70002000
 SBL_DEV_ID=55
 
-MULTI_CORE_IMAGE_GEN = $(CCS_NODE) $(MCU_PLUS_SDK_PATH)/tools/boot/multicoreImageGen/multicoreImageGen.js
-OUTRPRC_CMD = $(CCS_NODE) $(MCU_PLUS_SDK_PATH)/tools/boot/out2rprc/elf2rprc.js
-APP_IMAGE_SIGN_CMD = $(MCU_PLUS_SDK_PATH)/source/security/security_common/tools/boot/signing/appimage_x509_cert_gen.py
-
-ifeq ($(OS),Windows_NT)
-  XIPGEN_CMD=$(MCU_PLUS_SDK_PATH)/tools/boot/xipGen/xipGen.exe
-else
-  UNAME_S = $(shell uname -s)
-  ifeq ($(UNAME_S), Darwin)
-    XIPGEN_CMD=$(MCU_PLUS_SDK_PATH)/tools/boot/xipGen/xipGen.out.mac
-  else
-    XIPGEN_CMD=$(MCU_PLUS_SDK_PATH)/tools/boot/xipGen/xipGen.out
-endif
-endif
-
-MULTI_CORE_IMAGE_PARAMS = \
-	$(BOOTIMAGE_RPRC_NAME)@$(BOOTIMAGE_CORE_ID_r5fss0-0) \
-
-MULTI_CORE_IMAGE_PARAMS_XIP = \
-	$(BOOTIMAGE_RPRC_NAME_XIP)@$(BOOTIMAGE_CORE_ID_r5fss0-0)  \
+APP_IMAGE_SIGN_CMD = $(MCU_PLUS_SDK_PATH)/source/security/security_common/tools/boot/signing/mcu_appimage_x509_cert_gen.py
+MCELF_IMAGE_GEN = $(MCU_PLUS_SDK_PATH)/tools/boot/multicore-elf/genimage.py
 
 all:
 ifeq ($(CCS_IDE_MODE),cloud)
 #	No post build steps
 else
-	@echo  Boot image: am261x:r5fss0-0:freertos:ti-arm-clang $(BOOTIMAGE_NAME)  ...
-	$(OUTRPRC_CMD) $(OUTFILE) >> $(BOOTIMAGE_TEMP_OUT_FILE)
-	$(COPY) $(OUTNAME).rprc $(BOOTIMAGE_RPRC_NAME)
-	$(COPY) $(BOOTIMAGE_RPRC_NAME) $(BOOTIMAGE_RPRC_NAME_TMP)
-	$(RM) $(BOOTIMAGE_RPRC_NAME)
-	$(XIPGEN_CMD) -i $(BOOTIMAGE_RPRC_NAME_TMP) -o $(BOOTIMAGE_RPRC_NAME) -x $(BOOTIMAGE_RPRC_NAME_XIP) --flash-start-addr 0x60000000 -v > $(BOOTIMAGE_TEMP_OUT_FILE)
-	$(MULTI_CORE_IMAGE_GEN) --devID $(SBL_DEV_ID) --out $(BOOTIMAGE_NAME) $(MULTI_CORE_IMAGE_PARAMS) >> $(BOOTIMAGE_TEMP_OUT_FILE)
-	$(MULTI_CORE_IMAGE_GEN) --devID $(SBL_DEV_ID) --out $(BOOTIMAGE_NAME_XIP) $(MULTI_CORE_IMAGE_PARAMS_XIP) >> $(BOOTIMAGE_TEMP_OUT_FILE)
-ifeq ($(DEVICE_TYPE),HS)
+
+	@echo  Boot multi-core ELF image: am261x:r5fss0-0:freertos:ti-arm-clang $(BOOTIMAGE_NAME_MCELF) ...
+
+	$(PYTHON) $(MCELF_IMAGE_GEN) --core-img=$(BOOTIMAGE_CORE_ID_r5fss0-0):$(OUTFILE) --output=$(BOOTIMAGE_NAME_MCELF) --merge-segments=$(MCELF_MERGE_SEGMENTS_FLAG) --tolerance-limit=$(MCELF_MERGE_SEGMENTS_TOLERANCE_LIMIT) --ignore-context=$(MCELF_IGNORE_CONTEXT_FLAG) --xip=$(MCELF_XIP_RANGE) --xlat=$(MCELF_ADDR_TRANSLATION_PATH) --max-segment-size=$(MCELF_MAX_SEGMENT_SIZE)
+
+	@echo  Boot multi-core ELF image: $(BOOTIMAGE_NAME_MCELF) Done !!!
+	@echo  .
+
+ifeq ($(DEVICE_TYPE), HS)
 # Sign the appimage using appimage signing script
 ifeq ($(ENC_ENABLED),no)
+ifeq ($(RSASSAPSS_ENABLED),no)
 	@echo Boot image signing: Encryption is disabled.
-	$(PYTHON) $(APP_IMAGE_SIGN_CMD) --bin $(BOOTIMAGE_NAME) --authtype 1 --key $(APP_SIGNING_KEY) --output $(BOOTIMAGE_NAME).hs
-	$(RM) $(BOOTIMAGE_NAME)
+	$(PYTHON) $(APP_IMAGE_SIGN_CMD) --bin $(BOOTIMAGE_NAME_MCELF) --key $(APP_SIGNING_KEY) --sign_key_id $(APP_SIGNING_KEY_KEYRING_ID) --hash_algo $(APP_SIGNING_HASH_ALGO) --output $(BOOTIMAGE_NAME_MCELF_HS)
 else
-	@echo Boot image signing: Encryption is enabled.
-	$(PYTHON) $(APP_IMAGE_SIGN_CMD) --bin $(BOOTIMAGE_NAME) --authtype 1 --key $(APP_SIGNING_KEY) --enc y --enckey $(APP_ENCRYPTION_KEY) --output $(BOOTIMAGE_NAME).hs
-	$(RM) $(BOOTIMAGE_NAME)-enc
+	@echo Boot image signing: Encryption is disabled. RSASSA-PSS is enabled.
+	$(PYTHON) $(APP_IMAGE_SIGN_CMD) --bin $(BOOTIMAGE_NAME_MCELF) --key $(APP_SIGNING_KEY) --sign_key_id $(APP_SIGNING_KEY_KEYRING_ID) --hash_algo $(APP_SIGNING_HASH_ALGO) --pss_saltlen $(APP_SIGNING_SALT_LENGTH) --output $(BOOTIMAGE_NAME_MCELF_HS) --rsassa_pss
 endif
 else
-# Sign the appimage for HS-FS using appimage signing script
-	$(PYTHON) $(APP_IMAGE_SIGN_CMD) --bin $(BOOTIMAGE_NAME) --authtype 1 --key $(APP_SIGNING_KEY) --output $(BOOTIMAGE_NAME).hs_fs
-	$(RM) $(BOOTIMAGE_NAME)
-endif
-	$(RM) $(BOOTIMAGE_RPRC_NAME_TMP)
-ifeq ($(DEVICE_TYPE),HS)
-	@echo  Boot image: am261x:r5fss0-0:freertos:ti-arm-clang $(BOOTIMAGE_NAME).hs Done !!!
-	@echo  .
+ifeq ($(RSASSAPSS_ENABLED),no)
+	@echo Boot image signing: Encryption is enabled.
+	$(PYTHON) $(APP_IMAGE_SIGN_CMD) --bin $(BOOTIMAGE_NAME_MCELF) --key $(APP_SIGNING_KEY) --enc y --enckey $(APP_ENCRYPTION_KEY) --kd-salt $(KD_SALT) --sign_key_id $(APP_SIGNING_KEY_KEYRING_ID) --enc_key_id $(APP_ENCRYPTION_KEY_KEYRING_ID) --hash_algo $(APP_SIGNING_HASH_ALGO) --output $(BOOTIMAGE_NAME_MCELF_HS)
+	$(RM) $(BOOTIMAGE_NAME_MCELF)-enc
 else
-	@echo  Boot image: am261x:r5fss0-0:freertos:ti-arm-clang $(BOOTIMAGE_NAME).hs_fs Done !!!
+	@echo Boot image signing: Encryption is enabled. RSASSA-PSS is enabled.
+	$(PYTHON) $(APP_IMAGE_SIGN_CMD) --bin $(BOOTIMAGE_NAME_MCELF) --key $(APP_SIGNING_KEY) --enc y --enckey $(APP_ENCRYPTION_KEY) --kd-salt $(KD_SALT) --sign_key_id $(APP_SIGNING_KEY_KEYRING_ID) --enc_key_id $(APP_ENCRYPTION_KEY_KEYRING_ID) --hash_algo $(APP_SIGNING_HASH_ALGO) --pss_saltlen $(APP_SIGNING_SALT_LENGTH) --output $(BOOTIMAGE_NAME_MCELF_HS) --rsassa_pss
+	$(RM) $(BOOTIMAGE_NAME_MCELF)-enc
+endif
+endif
+	@echo  Boot image: am261x:r5fss0-0:freertos:ti-arm-clang $(BOOTIMAGE_PATH)/$(BOOTIMAGE_NAME_MCELF_HS) Done !!!
 	@echo  .
 endif
 endif
diff --git a/examples/spi_10mhz/mcuplus/am261x-lp/r5fss0-0_freertos/ti-arm-clang/example.projectspec b/examples/spi_10mhz/mcuplus/am261x-lp/r5fss0-0_freertos/ti-arm-clang/example.projectspec
index b5a26d0..9aadbbb 100644
--- a/examples/spi_10mhz/mcuplus/am261x-lp/r5fss0-0_freertos/ti-arm-clang/example.projectspec
+++ b/examples/spi_10mhz/mcuplus/am261x-lp/r5fss0-0_freertos/ti-arm-clang/example.projectspec
@@ -12,7 +12,7 @@
     <project
         title="spi_10mhz Pru"
         name = "spi_10mhz_am261x-lp_r5fss0-0_freertos_ti-arm-clang"
-        products="sysconfig;MCU-PLUS-SDK-AM261X"
+        products="sysconfig;com.ti.PRU_NO_CODE_TOOL;MCU-PLUS-SDK-AM261X"
         configurations="
                 Debug,
                 Release,
diff --git a/examples/spi_10mhz/mcuplus/am261x-lp/r5fss0-0_freertos/ti-arm-clang/makefile b/examples/spi_10mhz/mcuplus/am261x-lp/r5fss0-0_freertos/ti-arm-clang/makefile
index fbca04d..c2f94bd 100644
--- a/examples/spi_10mhz/mcuplus/am261x-lp/r5fss0-0_freertos/ti-arm-clang/makefile
+++ b/examples/spi_10mhz/mcuplus/am261x-lp/r5fss0-0_freertos/ti-arm-clang/makefile
@@ -29,7 +29,7 @@ OUTNAME:=spi_10mhz.$(PROFILE).out
 COREOUTNAME:=spi_10mhz.$(PROFILE).optishare.out
 
 BOOTIMAGE_PATH=$(abspath .)
-oeconfig?=None
+oeconfig?=
 
 BOOTIMAGE_NAME_MCELF:=spi_10mhz.$(PROFILE).mcelf
 BOOTIMAGE_NAME_MCELF_HS:=spi_10mhz.$(PROFILE).mcelf.hs
@@ -291,7 +291,7 @@ MCELF_IMAGE_GEN = $(MCU_PLUS_SDK_PATH)/tools/boot/multicore-elf/genimage.py
 
 $(BOOTIMAGE_NAME_MCELF): $(OUTNAME)
 	@echo  Boot MulticoreELF image: $(BOOTIMAGE_PATH)/$(BOOTIMAGE_NAME_MCELF) ...
-	$(PYTHON) $(MCELF_IMAGE_GEN) --core-img=$(BOOTIMAGE_CORE_ID_r5fss0-0):$(OUTNAME) --output=$(BOOTIMAGE_NAME_MCELF) --merge-segments=$(MCELF_MERGE_SEGMENTS_FLAG) --tolerance-limit=$(MCELF_MERGE_SEGMENTS_TOLERANCE_LIMIT) --ignore-context=$(MCELF_IGNORE_CONTEXT_FLAG) --xip=$(MCELF_XIP_RANGE) --xlat=$(MCELF_ADDR_TRANSLATION_PATH) --max-segment-size=$(MCELF_MAX_SEGMENT_SIZE) --otfaConfigFile=$(oeconfig)
+	$(PYTHON) $(MCELF_IMAGE_GEN) --core-img=$(BOOTIMAGE_CORE_ID_r5fss0-0):$(OUTNAME) --output=$(BOOTIMAGE_NAME_MCELF) --merge-segments=$(MCELF_MERGE_SEGMENTS_FLAG) --tolerance-limit=$(MCELF_MERGE_SEGMENTS_TOLERANCE_LIMIT) --ignore-context=$(MCELF_IGNORE_CONTEXT_FLAG) --xip=$(MCELF_XIP_RANGE) --xlat=$(MCELF_ADDR_TRANSLATION_PATH) --max-segment-size=$(MCELF_MAX_SEGMENT_SIZE) $(if $(oeconfig),--otfaConfigFile=$(oeconfig))
 	@echo  Boot MulticoreELF image: $(BOOTIMAGE_PATH)/$(BOOTIMAGE_NAME_MCELF) Done !!!
 	@echo  .
 
diff --git a/examples/spi_10mhz/mcuplus/am261x-lp/r5fss0-0_freertos/ti-arm-clang/makefile_ccs_bootimage_gen b/examples/spi_10mhz/mcuplus/am261x-lp/r5fss0-0_freertos/ti-arm-clang/makefile_ccs_bootimage_gen
index 93f08ca..fe5c5f6 100644
--- a/examples/spi_10mhz/mcuplus/am261x-lp/r5fss0-0_freertos/ti-arm-clang/makefile_ccs_bootimage_gen
+++ b/examples/spi_10mhz/mcuplus/am261x-lp/r5fss0-0_freertos/ti-arm-clang/makefile_ccs_bootimage_gen
@@ -12,7 +12,7 @@
 # - CCS_IDE_MODE
 
 CCS_PATH=$(CCS_INSTALL_DIR)
-include $(MCU_PLUS_SDK_PATH)/imports.mak
+include $(PRU_NO_CODE_TOOL_PATH)/imports.mak
 include $(MCU_PLUS_SDK_PATH)/devconfig/devconfig.mak
 
 STRIP=$(CG_TOOL_ROOT)/bin/tiarmstrip
diff --git a/examples/spi_loopback/mcuplus/am261x-lp/r5fss0-0_freertos/ti-arm-clang/example.projectspec b/examples/spi_loopback/mcuplus/am261x-lp/r5fss0-0_freertos/ti-arm-clang/example.projectspec
index f72f75b..2d5cae5 100644
--- a/examples/spi_loopback/mcuplus/am261x-lp/r5fss0-0_freertos/ti-arm-clang/example.projectspec
+++ b/examples/spi_loopback/mcuplus/am261x-lp/r5fss0-0_freertos/ti-arm-clang/example.projectspec
@@ -82,8 +82,8 @@
             "
             linkerBuildOptions="
                 -lfreertos.am261x.r5f.ti-arm-clang.debug.lib
-                -ldrivers.am261x.r5f.ti-arm-clang.debug.lib
-                -lboard.am261x.r5f.ti-arm-clang.debug.lib
+                -ldrivers.am261x.r5f.ti-arm-clang.freertos.debug.lib
+                -lboard.am261x.r5f.ti-arm-clang.freertos.debug.lib
                 -llibc.a
                 -llibsysbm.a
             "
@@ -94,8 +94,8 @@
             "
             linkerBuildOptions="
                 -lfreertos.am261x.r5f.ti-arm-clang.release.lib
-                -ldrivers.am261x.r5f.ti-arm-clang.release.lib
-                -lboard.am261x.r5f.ti-arm-clang.release.lib
+                -ldrivers.am261x.r5f.ti-arm-clang.freertos.release.lib
+                -lboard.am261x.r5f.ti-arm-clang.freertos.release.lib
                 -llibc.a
                 -llibsysbm.a
             "
diff --git a/examples/spi_loopback/mcuplus/am261x-lp/r5fss0-0_freertos/ti-arm-clang/makefile b/examples/spi_loopback/mcuplus/am261x-lp/r5fss0-0_freertos/ti-arm-clang/makefile
index 94dacd2..b97612b 100644
--- a/examples/spi_loopback/mcuplus/am261x-lp/r5fss0-0_freertos/ti-arm-clang/makefile
+++ b/examples/spi_loopback/mcuplus/am261x-lp/r5fss0-0_freertos/ti-arm-clang/makefile
@@ -29,15 +29,15 @@ OUTNAME:=spi_loopback.$(PROFILE).out
 COREOUTNAME:=spi_loopback.$(PROFILE).optishare.out
 
 BOOTIMAGE_PATH=$(abspath .)
-BOOTIMAGE_NAME:=spi_loopback.$(PROFILE).appimage
-BOOTIMAGE_NAME_XIP:=spi_loopback.$(PROFILE).appimage_xip
-BOOTIMAGE_NAME_SIGNED:=spi_loopback.$(PROFILE).appimage.signed
-BOOTIMAGE_RPRC_NAME:=spi_loopback.$(PROFILE).rprc
-BOOTIMAGE_RPRC_NAME_XIP:=spi_loopback.$(PROFILE).rprc_xip
-BOOTIMAGE_RPRC_NAME_TMP:=spi_loopback.$(PROFILE).rprc_tmp
-BOOTIMAGE_NAME_HS:=spi_loopback.$(PROFILE).appimage.hs
-BOOTIMAGE_NAME_HS_FS:=spi_loopback.$(PROFILE).appimage.hs_fs
-TARGETS := $(BOOTIMAGE_NAME)
+oeconfig?=
+
+BOOTIMAGE_NAME_MCELF:=spi_loopback.$(PROFILE).mcelf
+BOOTIMAGE_NAME_MCELF_HS:=spi_loopback.$(PROFILE).mcelf.hs
+TARGETS := $(BOOTIMAGE_NAME_MCELF)
+
+ifeq ($(DEVICE_TYPE), HS)
+   TARGETS += $(BOOTIMAGE_NAME_MCELF_HS)
+endif
 
 
 FILES_common := \
@@ -112,8 +112,8 @@ LIBS_PATH_common = \
 
 LIBS_common = \
 	-lfreertos.am261x.r5f.ti-arm-clang.${ConfigName}.lib \
-	-ldrivers.am261x.r5f.ti-arm-clang.${ConfigName}.lib \
-	-lboard.am261x.r5f.ti-arm-clang.${ConfigName}.lib \
+	-ldrivers.am261x.r5f.ti-arm-clang.freertos.${ConfigName}.lib \
+	-lboard.am261x.r5f.ti-arm-clang.freertos.${ConfigName}.lib \
 	-llibc.a \
 	-llibsysbm.a \
 
@@ -126,8 +126,8 @@ LFLAGS_common = \
 
 LIBS_NAME = \
 	freertos.am261x.r5f.ti-arm-clang.${ConfigName}.lib \
-	drivers.am261x.r5f.ti-arm-clang.${ConfigName}.lib \
-	board.am261x.r5f.ti-arm-clang.${ConfigName}.lib \
+	drivers.am261x.r5f.ti-arm-clang.freertos.${ConfigName}.lib \
+	board.am261x.r5f.ti-arm-clang.freertos.${ConfigName}.lib \
 	libc.a \
 	libsysbm.a \
 
@@ -208,13 +208,8 @@ clean:
 	@echo  Cleaning: am261x:r5fss0-0:freertos:ti-arm-clang $(OUTNAME) ...
 	$(RMDIR) $(OBJDIR)
 	$(RM) $(OUTNAME)
-	$(RM) $(BOOTIMAGE_NAME)
-	$(RM) $(BOOTIMAGE_NAME_XIP)
-	$(RM) $(BOOTIMAGE_NAME_SIGNED)
-	$(RM) $(BOOTIMAGE_NAME_HS)
-	$(RM) $(BOOTIMAGE_NAME_HS_FS)
-	$(RM) $(BOOTIMAGE_RPRC_NAME)
-	$(RM) $(BOOTIMAGE_RPRC_NAME_XIP)
+	$(RM) $(BOOTIMAGE_NAME_MCELF)
+	$(RM) $(BOOTIMAGE_NAME_MCELF_HS)
 	$(RMDIR) generated/
 
 scrub:
@@ -229,6 +224,10 @@ ifeq ($(OS),Windows_NT)
 	$(RM) \*.bin
 	$(RM) \*.lnkxml
 	$(RM) \*.ossr
+	$(RM) \*.mcelf
+	$(RM) \*.mcelf_xip
+	$(RM) \*.mcelf-enc
+	$(RM) \*.mcelf.hs
 else
 	$(RM) *.out
 	$(RM) *.map
@@ -238,6 +237,10 @@ else
 	$(RM) *.bin
 	$(RM) *.lnkxml
 	$(RM) *.ossr
+	$(RM) *.mcelf
+	$(RM) *.mcelf_xip
+	$(RM) *.mcelf-enc
+	$(RM) *.mcelf.hs
 endif
 	$(RMDIR) generated
 
@@ -276,66 +279,45 @@ BOOTIMAGE_TEMP_OUT_FILE=temp_stdout_$(PROFILE).txt
 
 BOOTIMAGE_CERT_KEY=$(APP_SIGNING_KEY)
 
-BOOTIMAGE_CORE_ID_r5fss0-0 = 4
-BOOTIMAGE_CORE_ID_r5fss0-1 = 5
-BOOTIMAGE_CORE_ID_r5fss1-0 = 6
-BOOTIMAGE_CORE_ID_r5fss1-1 = 7
-BOOTIMAGE_CORE_ID_m4fss0-0 = 14
-SBL_RUN_ADDRESS=0x70000000
+BOOTIMAGE_CORE_ID_r5fss0-0 = 0
+BOOTIMAGE_CORE_ID_r5fss0-1 = 1
+BOOTIMAGE_CORE_ID_r5fss1-0 = 2
+BOOTIMAGE_CORE_ID_r5fss1-1 = 3
+SBL_RUN_ADDRESS=0x70002000
 SBL_DEV_ID=55
 
-MULTI_CORE_IMAGE_GEN = $(SYSCFG_NODE) $(MCU_PLUS_SDK_PATH)/tools/boot/multicoreImageGen/multicoreImageGen.js
-OUTRPRC_CMD = $(SYSCFG_NODE) $(MCU_PLUS_SDK_PATH)/tools/boot/out2rprc/elf2rprc.js
-APP_IMAGE_SIGN_CMD = $(MCU_PLUS_SDK_PATH)/source/security/security_common/tools/boot/signing/appimage_x509_cert_gen.py
-
-ifeq ($(OS),Windows_NT)
-  XIPGEN_CMD=$(MCU_PLUS_SDK_PATH)/tools/boot/xipGen/xipGen.exe
-else
-  UNAME_S = $(shell uname -s)
-  ifeq ($(UNAME_S), Darwin)
-    XIPGEN_CMD=$(MCU_PLUS_SDK_PATH)/tools/boot/xipGen/xipGen.out.mac
-  else
-    XIPGEN_CMD=$(MCU_PLUS_SDK_PATH)/tools/boot/xipGen/xipGen.out
-endif
-endif
-
-MULTI_CORE_IMAGE_PARAMS = \
-	$(BOOTIMAGE_RPRC_NAME)@$(BOOTIMAGE_CORE_ID_r5fss0-0) \
+APP_IMAGE_SIGN_CMD = $(MCU_PLUS_SDK_PATH)/source/security/security_common/tools/boot/signing/mcu_appimage_x509_cert_gen.py
+MCELF_IMAGE_GEN = $(MCU_PLUS_SDK_PATH)/tools/boot/multicore-elf/genimage.py
 
-MULTI_CORE_IMAGE_PARAMS_XIP = \
-	$(BOOTIMAGE_RPRC_NAME_XIP)@$(BOOTIMAGE_CORE_ID_r5fss0-0) \
+$(BOOTIMAGE_NAME_MCELF): $(OUTNAME)
+	@echo  Boot MulticoreELF image: $(BOOTIMAGE_PATH)/$(BOOTIMAGE_NAME_MCELF) ...
+	$(PYTHON) $(MCELF_IMAGE_GEN) --core-img=$(BOOTIMAGE_CORE_ID_r5fss0-0):$(OUTNAME) --output=$(BOOTIMAGE_NAME_MCELF) --merge-segments=$(MCELF_MERGE_SEGMENTS_FLAG) --tolerance-limit=$(MCELF_MERGE_SEGMENTS_TOLERANCE_LIMIT) --ignore-context=$(MCELF_IGNORE_CONTEXT_FLAG) --xip=$(MCELF_XIP_RANGE) --xlat=$(MCELF_ADDR_TRANSLATION_PATH) --max-segment-size=$(MCELF_MAX_SEGMENT_SIZE) $(if $(oeconfig),--otfaConfigFile=$(oeconfig))
+	@echo  Boot MulticoreELF image: $(BOOTIMAGE_PATH)/$(BOOTIMAGE_NAME_MCELF) Done !!!
+	@echo  .
 
-$(BOOTIMAGE_NAME): $(OUTNAME)
-	@echo  Boot image: am261x:r5fss0-0:freertos:ti-arm-clang $(BOOTIMAGE_PATH)/$@ ...
-ifneq ($(OS),Windows_NT)
-	$(CHMOD) a+x $(XIPGEN_CMD)
-endif
-	$(OUTRPRC_CMD) $(OUTNAME) >> $(BOOTIMAGE_TEMP_OUT_FILE)
-	$(COPY) $(BOOTIMAGE_RPRC_NAME) $(BOOTIMAGE_RPRC_NAME_TMP)
-	$(RM) $(BOOTIMAGE_RPRC_NAME)
-	$(XIPGEN_CMD) -i $(BOOTIMAGE_RPRC_NAME_TMP) -o $(BOOTIMAGE_RPRC_NAME) -x $(BOOTIMAGE_RPRC_NAME_XIP) --flash-start-addr 0x60000000 -v > $(BOOTIMAGE_TEMP_OUT_FILE)
-	$(MULTI_CORE_IMAGE_GEN) --devID $(SBL_DEV_ID) --out $(BOOTIMAGE_NAME) $(MULTI_CORE_IMAGE_PARAMS) >> $(BOOTIMAGE_TEMP_OUT_FILE)
-	$(MULTI_CORE_IMAGE_GEN) --devID $(SBL_DEV_ID) --out $(BOOTIMAGE_NAME_XIP) $(MULTI_CORE_IMAGE_PARAMS_XIP) >> $(BOOTIMAGE_TEMP_OUT_FILE)
-	$(RM) $(BOOTIMAGE_RPRC_NAME_TMP)
-	$(RM) $(BOOTIMAGE_TEMP_OUT_FILE)
+$(BOOTIMAGE_NAME_MCELF_HS): $(BOOTIMAGE_NAME_MCELF)
 ifeq ($(DEVICE_TYPE), HS)
 # Sign the appimage using appimage signing script
 ifeq ($(ENC_ENABLED),no)
+ifeq ($(RSASSAPSS_ENABLED),no)
 	@echo Boot image signing: Encryption is disabled.
-	$(PYTHON) $(APP_IMAGE_SIGN_CMD) --bin $(BOOTIMAGE_NAME) --authtype 1 --key $(APP_SIGNING_KEY) --output $(BOOTIMAGE_NAME_HS)
+	$(PYTHON) $(APP_IMAGE_SIGN_CMD) --bin $(BOOTIMAGE_NAME_MCELF) --key $(APP_SIGNING_KEY) --sign_key_id $(APP_SIGNING_KEY_KEYRING_ID) --hash_algo $(APP_SIGNING_HASH_ALGO) --output $(BOOTIMAGE_NAME_MCELF_HS)
 else
-	@echo Boot image signing: Encryption is enabled.
-	$(PYTHON) $(APP_IMAGE_SIGN_CMD) --bin $(BOOTIMAGE_NAME) --authtype 1 --key $(APP_SIGNING_KEY) --enc y --enckey $(APP_ENCRYPTION_KEY) --output $(BOOTIMAGE_NAME_HS)
-	$(RM) $(BOOTIMAGE_NAME)-enc
+	@echo Boot image signing: Encryption is disabled. RSASSAPSS is enabled.
+	$(PYTHON) $(APP_IMAGE_SIGN_CMD) --bin $(BOOTIMAGE_NAME_MCELF) --key $(APP_SIGNING_KEY) --sign_key_id $(APP_SIGNING_KEY_KEYRING_ID) --hash_algo $(APP_SIGNING_HASH_ALGO) --pss_saltlen $(APP_SIGNING_SALT_LENGTH) --output $(BOOTIMAGE_NAME_MCELF_HS) --rsassa_pss
 endif
-	$(RM) $(BOOTIMAGE_NAME)
-	@echo  Boot image: am261x:r5fss0-0:freertos:ti-arm-clang $(BOOTIMAGE_PATH)/$(BOOTIMAGE_NAME_HS) Done !!!
-	@echo  .
 else
-# Sign the appimage for HS-FS using appimage signing script
-	$(PYTHON) $(APP_IMAGE_SIGN_CMD) --bin $(BOOTIMAGE_NAME) --authtype 1 --key $(APP_SIGNING_KEY) --output $(BOOTIMAGE_NAME_HS_FS)
-	$(RM) $(BOOTIMAGE_NAME)
-	@echo  Boot image: am261x:r5fss0-0:freertos:ti-arm-clang $(BOOTIMAGE_PATH)/$(BOOTIMAGE_NAME_HS_FS) Done !!!
+ifeq ($(RSASSAPSS_ENABLED),no)
+	@echo Boot image signing: Encryption is enabled.
+	$(PYTHON) $(APP_IMAGE_SIGN_CMD) --bin $(BOOTIMAGE_NAME_MCELF) --key $(APP_SIGNING_KEY) --enc y --enckey $(APP_ENCRYPTION_KEY) --kd-salt $(KD_SALT) --sign_key_id $(APP_SIGNING_KEY_KEYRING_ID) --enc_key_id $(APP_ENCRYPTION_KEY_KEYRING_ID) --hash_algo $(APP_SIGNING_HASH_ALGO) --output $(BOOTIMAGE_NAME_MCELF_HS)
+	$(RM) $(BOOTIMAGE_NAME_MCELF)-enc
+else
+	@echo Boot image signing: Encryption is enabled. RSASSAPSS is enabled.
+	$(PYTHON) $(APP_IMAGE_SIGN_CMD) --bin $(BOOTIMAGE_NAME_MCELF) --key $(APP_SIGNING_KEY) --enc y --enckey $(APP_ENCRYPTION_KEY) --kd-salt $(KD_SALT) --sign_key_id $(APP_SIGNING_KEY_KEYRING_ID) --enc_key_id $(APP_ENCRYPTION_KEY_KEYRING_ID) --hash_algo $(APP_SIGNING_HASH_ALGO) --pss_saltlen $(APP_SIGNING_SALT_LENGTH) --output $(BOOTIMAGE_NAME_MCELF_HS) --rsassa_pss
+	$(RM) $(BOOTIMAGE_NAME_MCELF)-enc
+endif
+endif
+	@echo  Boot image: am261x:r5fss0-0:freertos:ti-arm-clang $(BOOTIMAGE_PATH)/$(BOOTIMAGE_NAME_MCELF_HS) Done !!!
 	@echo  .
 endif
 
diff --git a/examples/spi_loopback/mcuplus/am261x-lp/r5fss0-0_freertos/ti-arm-clang/makefile.defs b/examples/spi_loopback/mcuplus/am261x-lp/r5fss0-0_freertos/ti-arm-clang/makefile.defs
new file mode 100644
index 0000000..4f41ac3
--- /dev/null
+++ b/examples/spi_loopback/mcuplus/am261x-lp/r5fss0-0_freertos/ti-arm-clang/makefile.defs
@@ -0,0 +1,14 @@
+GEN_FILES__QUOTED += \
+*.appimage* \
+*.appimage_xip \
+*.rprc* \
+*.rprc_xip \
+*.tiimage* \
+*.bin \
+*.lnkxml \
+*.map \
+*.ossr
+
+GEN_FILES__QUOTED += \
+*.mcelf* \
+*.mcelf_xip
diff --git a/examples/spi_loopback/mcuplus/am261x-lp/r5fss0-0_freertos/ti-arm-clang/makefile_ccs_bootimage_gen b/examples/spi_loopback/mcuplus/am261x-lp/r5fss0-0_freertos/ti-arm-clang/makefile_ccs_bootimage_gen
index 9c2450e..fe5c5f6 100644
--- a/examples/spi_loopback/mcuplus/am261x-lp/r5fss0-0_freertos/ti-arm-clang/makefile_ccs_bootimage_gen
+++ b/examples/spi_loopback/mcuplus/am261x-lp/r5fss0-0_freertos/ti-arm-clang/makefile_ccs_bootimage_gen
@@ -25,12 +25,13 @@ endif
 
 OUTFILE=$(PROFILE)/$(OUTNAME).out
 BOOTIMAGE_PATH=$(abspath ${PROFILE})
-BOOTIMAGE_NAME:=$(BOOTIMAGE_PATH)/$(OUTNAME).appimage
-BOOTIMAGE_NAME_XIP:=$(BOOTIMAGE_PATH)/$(OUTNAME).appimage_xip
-BOOTIMAGE_NAME_SIGNED:=$(BOOTIMAGE_PATH)/$(OUTNAME).appimage.signed
-BOOTIMAGE_RPRC_NAME:=$(BOOTIMAGE_PATH)/$(OUTNAME).rprc
-BOOTIMAGE_RPRC_NAME_XIP:=$(BOOTIMAGE_PATH)/$(OUTNAME).rprc_xip
-BOOTIMAGE_RPRC_NAME_TMP:=$(BOOTIMAGE_PATH)/$(OUTNAME).rprc_tmp
+BOOTIMAGE_NAME_MCELF:=$(BOOTIMAGE_PATH)/$(OUTNAME).mcelf
+BOOTIMAGE_NAME_MCELF_HS:=$(BOOTIMAGE_PATH)/$(OUTNAME).mcelf.hs
+TARGETS += $(BOOTIMAGE_NAME_MCELF)
+TARGETS += $(BOOTIMAGE_NAME_MCELF_HS)
+ifeq ($(DEVICE_TYPE), HS)
+   TARGETS += $(BOOTIMAGE_NAME_MCELF_HS)
+endif
 
 #
 # Generation of boot image which can be loaded by Secondary Boot Loader (SBL)
@@ -45,69 +46,50 @@ else
 endif
 BOOTIMAGE_TEMP_OUT_FILE=$(PROFILE)/temp_stdout_$(PROFILE).txt
 
-BOOTIMAGE_CORE_ID_r5fss0-0 = 4
-BOOTIMAGE_CORE_ID_r5fss0-1 = 5
-BOOTIMAGE_CORE_ID_r5fss1-0 = 6
-BOOTIMAGE_CORE_ID_r5fss1-1 = 7
-BOOTIMAGE_CORE_ID_m4fss0-0 = 14
-SBL_RUN_ADDRESS=0x70000000
+BOOTIMAGE_CORE_ID_r5fss0-0 = 0
+BOOTIMAGE_CORE_ID_r5fss0-1 = 1
+BOOTIMAGE_CORE_ID_r5fss1-0 = 2
+BOOTIMAGE_CORE_ID_r5fss1-1 = 3
+SBL_RUN_ADDRESS=0x70002000
 SBL_DEV_ID=55
 
-MULTI_CORE_IMAGE_GEN = $(CCS_NODE) $(MCU_PLUS_SDK_PATH)/tools/boot/multicoreImageGen/multicoreImageGen.js
-OUTRPRC_CMD = $(CCS_NODE) $(MCU_PLUS_SDK_PATH)/tools/boot/out2rprc/elf2rprc.js
-APP_IMAGE_SIGN_CMD = $(MCU_PLUS_SDK_PATH)/source/security/security_common/tools/boot/signing/appimage_x509_cert_gen.py
-
-ifeq ($(OS),Windows_NT)
-  XIPGEN_CMD=$(MCU_PLUS_SDK_PATH)/tools/boot/xipGen/xipGen.exe
-else
-  UNAME_S = $(shell uname -s)
-  ifeq ($(UNAME_S), Darwin)
-    XIPGEN_CMD=$(MCU_PLUS_SDK_PATH)/tools/boot/xipGen/xipGen.out.mac
-  else
-    XIPGEN_CMD=$(MCU_PLUS_SDK_PATH)/tools/boot/xipGen/xipGen.out
-endif
-endif
-
-MULTI_CORE_IMAGE_PARAMS = \
-	$(BOOTIMAGE_RPRC_NAME)@$(BOOTIMAGE_CORE_ID_r5fss0-0) \
-
-MULTI_CORE_IMAGE_PARAMS_XIP = \
-	$(BOOTIMAGE_RPRC_NAME_XIP)@$(BOOTIMAGE_CORE_ID_r5fss0-0)  \
+APP_IMAGE_SIGN_CMD = $(MCU_PLUS_SDK_PATH)/source/security/security_common/tools/boot/signing/mcu_appimage_x509_cert_gen.py
+MCELF_IMAGE_GEN = $(MCU_PLUS_SDK_PATH)/tools/boot/multicore-elf/genimage.py
 
 all:
 ifeq ($(CCS_IDE_MODE),cloud)
 #	No post build steps
 else
-	@echo  Boot image: am261x:r5fss0-0:freertos:ti-arm-clang $(BOOTIMAGE_NAME)  ...
-	$(OUTRPRC_CMD) $(OUTFILE) >> $(BOOTIMAGE_TEMP_OUT_FILE)
-	$(COPY) $(OUTNAME).rprc $(BOOTIMAGE_RPRC_NAME)
-	$(COPY) $(BOOTIMAGE_RPRC_NAME) $(BOOTIMAGE_RPRC_NAME_TMP)
-	$(RM) $(BOOTIMAGE_RPRC_NAME)
-	$(XIPGEN_CMD) -i $(BOOTIMAGE_RPRC_NAME_TMP) -o $(BOOTIMAGE_RPRC_NAME) -x $(BOOTIMAGE_RPRC_NAME_XIP) --flash-start-addr 0x60000000 -v > $(BOOTIMAGE_TEMP_OUT_FILE)
-	$(MULTI_CORE_IMAGE_GEN) --devID $(SBL_DEV_ID) --out $(BOOTIMAGE_NAME) $(MULTI_CORE_IMAGE_PARAMS) >> $(BOOTIMAGE_TEMP_OUT_FILE)
-	$(MULTI_CORE_IMAGE_GEN) --devID $(SBL_DEV_ID) --out $(BOOTIMAGE_NAME_XIP) $(MULTI_CORE_IMAGE_PARAMS_XIP) >> $(BOOTIMAGE_TEMP_OUT_FILE)
-ifeq ($(DEVICE_TYPE),HS)
+
+	@echo  Boot multi-core ELF image: am261x:r5fss0-0:freertos:ti-arm-clang $(BOOTIMAGE_NAME_MCELF) ...
+
+	$(PYTHON) $(MCELF_IMAGE_GEN) --core-img=$(BOOTIMAGE_CORE_ID_r5fss0-0):$(OUTFILE) --output=$(BOOTIMAGE_NAME_MCELF) --merge-segments=$(MCELF_MERGE_SEGMENTS_FLAG) --tolerance-limit=$(MCELF_MERGE_SEGMENTS_TOLERANCE_LIMIT) --ignore-context=$(MCELF_IGNORE_CONTEXT_FLAG) --xip=$(MCELF_XIP_RANGE) --xlat=$(MCELF_ADDR_TRANSLATION_PATH) --max-segment-size=$(MCELF_MAX_SEGMENT_SIZE)
+
+	@echo  Boot multi-core ELF image: $(BOOTIMAGE_NAME_MCELF) Done !!!
+	@echo  .
+
+ifeq ($(DEVICE_TYPE), HS)
 # Sign the appimage using appimage signing script
 ifeq ($(ENC_ENABLED),no)
+ifeq ($(RSASSAPSS_ENABLED),no)
 	@echo Boot image signing: Encryption is disabled.
-	$(PYTHON) $(APP_IMAGE_SIGN_CMD) --bin $(BOOTIMAGE_NAME) --authtype 1 --key $(APP_SIGNING_KEY) --output $(BOOTIMAGE_NAME).hs
-	$(RM) $(BOOTIMAGE_NAME)
+	$(PYTHON) $(APP_IMAGE_SIGN_CMD) --bin $(BOOTIMAGE_NAME_MCELF) --key $(APP_SIGNING_KEY) --sign_key_id $(APP_SIGNING_KEY_KEYRING_ID) --hash_algo $(APP_SIGNING_HASH_ALGO) --output $(BOOTIMAGE_NAME_MCELF_HS)
 else
-	@echo Boot image signing: Encryption is enabled.
-	$(PYTHON) $(APP_IMAGE_SIGN_CMD) --bin $(BOOTIMAGE_NAME) --authtype 1 --key $(APP_SIGNING_KEY) --enc y --enckey $(APP_ENCRYPTION_KEY) --output $(BOOTIMAGE_NAME).hs
-	$(RM) $(BOOTIMAGE_NAME)-enc
+	@echo Boot image signing: Encryption is disabled. RSASSA-PSS is enabled.
+	$(PYTHON) $(APP_IMAGE_SIGN_CMD) --bin $(BOOTIMAGE_NAME_MCELF) --key $(APP_SIGNING_KEY) --sign_key_id $(APP_SIGNING_KEY_KEYRING_ID) --hash_algo $(APP_SIGNING_HASH_ALGO) --pss_saltlen $(APP_SIGNING_SALT_LENGTH) --output $(BOOTIMAGE_NAME_MCELF_HS) --rsassa_pss
 endif
 else
-# Sign the appimage for HS-FS using appimage signing script
-	$(PYTHON) $(APP_IMAGE_SIGN_CMD) --bin $(BOOTIMAGE_NAME) --authtype 1 --key $(APP_SIGNING_KEY) --output $(BOOTIMAGE_NAME).hs_fs
-	$(RM) $(BOOTIMAGE_NAME)
-endif
-	$(RM) $(BOOTIMAGE_RPRC_NAME_TMP)
-ifeq ($(DEVICE_TYPE),HS)
-	@echo  Boot image: am261x:r5fss0-0:freertos:ti-arm-clang $(BOOTIMAGE_NAME).hs Done !!!
-	@echo  .
+ifeq ($(RSASSAPSS_ENABLED),no)
+	@echo Boot image signing: Encryption is enabled.
+	$(PYTHON) $(APP_IMAGE_SIGN_CMD) --bin $(BOOTIMAGE_NAME_MCELF) --key $(APP_SIGNING_KEY) --enc y --enckey $(APP_ENCRYPTION_KEY) --kd-salt $(KD_SALT) --sign_key_id $(APP_SIGNING_KEY_KEYRING_ID) --enc_key_id $(APP_ENCRYPTION_KEY_KEYRING_ID) --hash_algo $(APP_SIGNING_HASH_ALGO) --output $(BOOTIMAGE_NAME_MCELF_HS)
+	$(RM) $(BOOTIMAGE_NAME_MCELF)-enc
 else
-	@echo  Boot image: am261x:r5fss0-0:freertos:ti-arm-clang $(BOOTIMAGE_NAME).hs_fs Done !!!
+	@echo Boot image signing: Encryption is enabled. RSASSA-PSS is enabled.
+	$(PYTHON) $(APP_IMAGE_SIGN_CMD) --bin $(BOOTIMAGE_NAME_MCELF) --key $(APP_SIGNING_KEY) --enc y --enckey $(APP_ENCRYPTION_KEY) --kd-salt $(KD_SALT) --sign_key_id $(APP_SIGNING_KEY_KEYRING_ID) --enc_key_id $(APP_ENCRYPTION_KEY_KEYRING_ID) --hash_algo $(APP_SIGNING_HASH_ALGO) --pss_saltlen $(APP_SIGNING_SALT_LENGTH) --output $(BOOTIMAGE_NAME_MCELF_HS) --rsassa_pss
+	$(RM) $(BOOTIMAGE_NAME_MCELF)-enc
+endif
+endif
+	@echo  Boot image: am261x:r5fss0-0:freertos:ti-arm-clang $(BOOTIMAGE_PATH)/$(BOOTIMAGE_NAME_MCELF_HS) Done !!!
 	@echo  .
 endif
 endif
diff --git a/examples/uart_crc/mcuplus/am261x-lp/r5fss0-0_freertos/ti-arm-clang/example.projectspec b/examples/uart_crc/mcuplus/am261x-lp/r5fss0-0_freertos/ti-arm-clang/example.projectspec
index 7d97362..21f292e 100644
--- a/examples/uart_crc/mcuplus/am261x-lp/r5fss0-0_freertos/ti-arm-clang/example.projectspec
+++ b/examples/uart_crc/mcuplus/am261x-lp/r5fss0-0_freertos/ti-arm-clang/example.projectspec
@@ -82,8 +82,8 @@
             "
             linkerBuildOptions="
                 -lfreertos.am261x.r5f.ti-arm-clang.debug.lib
-                -ldrivers.am261x.r5f.ti-arm-clang.debug.lib
-                -lboard.am261x.r5f.ti-arm-clang.debug.lib
+                -ldrivers.am261x.r5f.ti-arm-clang.freertos.debug.lib
+                -lboard.am261x.r5f.ti-arm-clang.freertos.debug.lib
                 -llibc.a
                 -llibsysbm.a
             "
@@ -94,8 +94,8 @@
             "
             linkerBuildOptions="
                 -lfreertos.am261x.r5f.ti-arm-clang.release.lib
-                -ldrivers.am261x.r5f.ti-arm-clang.release.lib
-                -lboard.am261x.r5f.ti-arm-clang.release.lib
+                -ldrivers.am261x.r5f.ti-arm-clang.freertos.release.lib
+                -lboard.am261x.r5f.ti-arm-clang.freertos.release.lib
                 -llibc.a
                 -llibsysbm.a
             "
diff --git a/examples/uart_crc/mcuplus/am261x-lp/r5fss0-0_freertos/ti-arm-clang/makefile b/examples/uart_crc/mcuplus/am261x-lp/r5fss0-0_freertos/ti-arm-clang/makefile
index 7436170..64e5ca0 100644
--- a/examples/uart_crc/mcuplus/am261x-lp/r5fss0-0_freertos/ti-arm-clang/makefile
+++ b/examples/uart_crc/mcuplus/am261x-lp/r5fss0-0_freertos/ti-arm-clang/makefile
@@ -29,15 +29,15 @@ OUTNAME:=uart_crc.$(PROFILE).out
 COREOUTNAME:=uart_crc.$(PROFILE).optishare.out
 
 BOOTIMAGE_PATH=$(abspath .)
-BOOTIMAGE_NAME:=uart_crc.$(PROFILE).appimage
-BOOTIMAGE_NAME_XIP:=uart_crc.$(PROFILE).appimage_xip
-BOOTIMAGE_NAME_SIGNED:=uart_crc.$(PROFILE).appimage.signed
-BOOTIMAGE_RPRC_NAME:=uart_crc.$(PROFILE).rprc
-BOOTIMAGE_RPRC_NAME_XIP:=uart_crc.$(PROFILE).rprc_xip
-BOOTIMAGE_RPRC_NAME_TMP:=uart_crc.$(PROFILE).rprc_tmp
-BOOTIMAGE_NAME_HS:=uart_crc.$(PROFILE).appimage.hs
-BOOTIMAGE_NAME_HS_FS:=uart_crc.$(PROFILE).appimage.hs_fs
-TARGETS := $(BOOTIMAGE_NAME)
+oeconfig?=
+
+BOOTIMAGE_NAME_MCELF:=uart_crc.$(PROFILE).mcelf
+BOOTIMAGE_NAME_MCELF_HS:=uart_crc.$(PROFILE).mcelf.hs
+TARGETS := $(BOOTIMAGE_NAME_MCELF)
+
+ifeq ($(DEVICE_TYPE), HS)
+   TARGETS += $(BOOTIMAGE_NAME_MCELF_HS)
+endif
 
 
 FILES_common := \
@@ -112,8 +112,8 @@ LIBS_PATH_common = \
 
 LIBS_common = \
 	-lfreertos.am261x.r5f.ti-arm-clang.${ConfigName}.lib \
-	-ldrivers.am261x.r5f.ti-arm-clang.${ConfigName}.lib \
-	-lboard.am261x.r5f.ti-arm-clang.${ConfigName}.lib \
+	-ldrivers.am261x.r5f.ti-arm-clang.freertos.${ConfigName}.lib \
+	-lboard.am261x.r5f.ti-arm-clang.freertos.${ConfigName}.lib \
 	-llibc.a \
 	-llibsysbm.a \
 
@@ -126,8 +126,8 @@ LFLAGS_common = \
 
 LIBS_NAME = \
 	freertos.am261x.r5f.ti-arm-clang.${ConfigName}.lib \
-	drivers.am261x.r5f.ti-arm-clang.${ConfigName}.lib \
-	board.am261x.r5f.ti-arm-clang.${ConfigName}.lib \
+	drivers.am261x.r5f.ti-arm-clang.freertos.${ConfigName}.lib \
+	board.am261x.r5f.ti-arm-clang.freertos.${ConfigName}.lib \
 	libc.a \
 	libsysbm.a \
 
@@ -208,13 +208,8 @@ clean:
 	@echo  Cleaning: am261x:r5fss0-0:freertos:ti-arm-clang $(OUTNAME) ...
 	$(RMDIR) $(OBJDIR)
 	$(RM) $(OUTNAME)
-	$(RM) $(BOOTIMAGE_NAME)
-	$(RM) $(BOOTIMAGE_NAME_XIP)
-	$(RM) $(BOOTIMAGE_NAME_SIGNED)
-	$(RM) $(BOOTIMAGE_NAME_HS)
-	$(RM) $(BOOTIMAGE_NAME_HS_FS)
-	$(RM) $(BOOTIMAGE_RPRC_NAME)
-	$(RM) $(BOOTIMAGE_RPRC_NAME_XIP)
+	$(RM) $(BOOTIMAGE_NAME_MCELF)
+	$(RM) $(BOOTIMAGE_NAME_MCELF_HS)
 	$(RMDIR) generated/
 
 scrub:
@@ -229,6 +224,10 @@ ifeq ($(OS),Windows_NT)
 	$(RM) \*.bin
 	$(RM) \*.lnkxml
 	$(RM) \*.ossr
+	$(RM) \*.mcelf
+	$(RM) \*.mcelf_xip
+	$(RM) \*.mcelf-enc
+	$(RM) \*.mcelf.hs
 else
 	$(RM) *.out
 	$(RM) *.map
@@ -238,6 +237,10 @@ else
 	$(RM) *.bin
 	$(RM) *.lnkxml
 	$(RM) *.ossr
+	$(RM) *.mcelf
+	$(RM) *.mcelf_xip
+	$(RM) *.mcelf-enc
+	$(RM) *.mcelf.hs
 endif
 	$(RMDIR) generated
 
@@ -276,66 +279,45 @@ BOOTIMAGE_TEMP_OUT_FILE=temp_stdout_$(PROFILE).txt
 
 BOOTIMAGE_CERT_KEY=$(APP_SIGNING_KEY)
 
-BOOTIMAGE_CORE_ID_r5fss0-0 = 4
-BOOTIMAGE_CORE_ID_r5fss0-1 = 5
-BOOTIMAGE_CORE_ID_r5fss1-0 = 6
-BOOTIMAGE_CORE_ID_r5fss1-1 = 7
-BOOTIMAGE_CORE_ID_m4fss0-0 = 14
-SBL_RUN_ADDRESS=0x70000000
+BOOTIMAGE_CORE_ID_r5fss0-0 = 0
+BOOTIMAGE_CORE_ID_r5fss0-1 = 1
+BOOTIMAGE_CORE_ID_r5fss1-0 = 2
+BOOTIMAGE_CORE_ID_r5fss1-1 = 3
+SBL_RUN_ADDRESS=0x70002000
 SBL_DEV_ID=55
 
-MULTI_CORE_IMAGE_GEN = $(SYSCFG_NODE) $(MCU_PLUS_SDK_PATH)/tools/boot/multicoreImageGen/multicoreImageGen.js
-OUTRPRC_CMD = $(SYSCFG_NODE) $(MCU_PLUS_SDK_PATH)/tools/boot/out2rprc/elf2rprc.js
-APP_IMAGE_SIGN_CMD = $(MCU_PLUS_SDK_PATH)/source/security/security_common/tools/boot/signing/appimage_x509_cert_gen.py
-
-ifeq ($(OS),Windows_NT)
-  XIPGEN_CMD=$(MCU_PLUS_SDK_PATH)/tools/boot/xipGen/xipGen.exe
-else
-  UNAME_S = $(shell uname -s)
-  ifeq ($(UNAME_S), Darwin)
-    XIPGEN_CMD=$(MCU_PLUS_SDK_PATH)/tools/boot/xipGen/xipGen.out.mac
-  else
-    XIPGEN_CMD=$(MCU_PLUS_SDK_PATH)/tools/boot/xipGen/xipGen.out
-endif
-endif
-
-MULTI_CORE_IMAGE_PARAMS = \
-	$(BOOTIMAGE_RPRC_NAME)@$(BOOTIMAGE_CORE_ID_r5fss0-0) \
+APP_IMAGE_SIGN_CMD = $(MCU_PLUS_SDK_PATH)/source/security/security_common/tools/boot/signing/mcu_appimage_x509_cert_gen.py
+MCELF_IMAGE_GEN = $(MCU_PLUS_SDK_PATH)/tools/boot/multicore-elf/genimage.py
 
-MULTI_CORE_IMAGE_PARAMS_XIP = \
-	$(BOOTIMAGE_RPRC_NAME_XIP)@$(BOOTIMAGE_CORE_ID_r5fss0-0) \
+$(BOOTIMAGE_NAME_MCELF): $(OUTNAME)
+	@echo  Boot MulticoreELF image: $(BOOTIMAGE_PATH)/$(BOOTIMAGE_NAME_MCELF) ...
+	$(PYTHON) $(MCELF_IMAGE_GEN) --core-img=$(BOOTIMAGE_CORE_ID_r5fss0-0):$(OUTNAME) --output=$(BOOTIMAGE_NAME_MCELF) --merge-segments=$(MCELF_MERGE_SEGMENTS_FLAG) --tolerance-limit=$(MCELF_MERGE_SEGMENTS_TOLERANCE_LIMIT) --ignore-context=$(MCELF_IGNORE_CONTEXT_FLAG) --xip=$(MCELF_XIP_RANGE) --xlat=$(MCELF_ADDR_TRANSLATION_PATH) --max-segment-size=$(MCELF_MAX_SEGMENT_SIZE) $(if $(oeconfig),--otfaConfigFile=$(oeconfig))
+	@echo  Boot MulticoreELF image: $(BOOTIMAGE_PATH)/$(BOOTIMAGE_NAME_MCELF) Done !!!
+	@echo  .
 
-$(BOOTIMAGE_NAME): $(OUTNAME)
-	@echo  Boot image: am261x:r5fss0-0:freertos:ti-arm-clang $(BOOTIMAGE_PATH)/$@ ...
-ifneq ($(OS),Windows_NT)
-	$(CHMOD) a+x $(XIPGEN_CMD)
-endif
-	$(OUTRPRC_CMD) $(OUTNAME) >> $(BOOTIMAGE_TEMP_OUT_FILE)
-	$(COPY) $(BOOTIMAGE_RPRC_NAME) $(BOOTIMAGE_RPRC_NAME_TMP)
-	$(RM) $(BOOTIMAGE_RPRC_NAME)
-	$(XIPGEN_CMD) -i $(BOOTIMAGE_RPRC_NAME_TMP) -o $(BOOTIMAGE_RPRC_NAME) -x $(BOOTIMAGE_RPRC_NAME_XIP) --flash-start-addr 0x60000000 -v > $(BOOTIMAGE_TEMP_OUT_FILE)
-	$(MULTI_CORE_IMAGE_GEN) --devID $(SBL_DEV_ID) --out $(BOOTIMAGE_NAME) $(MULTI_CORE_IMAGE_PARAMS) >> $(BOOTIMAGE_TEMP_OUT_FILE)
-	$(MULTI_CORE_IMAGE_GEN) --devID $(SBL_DEV_ID) --out $(BOOTIMAGE_NAME_XIP) $(MULTI_CORE_IMAGE_PARAMS_XIP) >> $(BOOTIMAGE_TEMP_OUT_FILE)
-	$(RM) $(BOOTIMAGE_RPRC_NAME_TMP)
-	$(RM) $(BOOTIMAGE_TEMP_OUT_FILE)
+$(BOOTIMAGE_NAME_MCELF_HS): $(BOOTIMAGE_NAME_MCELF)
 ifeq ($(DEVICE_TYPE), HS)
 # Sign the appimage using appimage signing script
 ifeq ($(ENC_ENABLED),no)
+ifeq ($(RSASSAPSS_ENABLED),no)
 	@echo Boot image signing: Encryption is disabled.
-	$(PYTHON) $(APP_IMAGE_SIGN_CMD) --bin $(BOOTIMAGE_NAME) --authtype 1 --key $(APP_SIGNING_KEY) --output $(BOOTIMAGE_NAME_HS)
+	$(PYTHON) $(APP_IMAGE_SIGN_CMD) --bin $(BOOTIMAGE_NAME_MCELF) --key $(APP_SIGNING_KEY) --sign_key_id $(APP_SIGNING_KEY_KEYRING_ID) --hash_algo $(APP_SIGNING_HASH_ALGO) --output $(BOOTIMAGE_NAME_MCELF_HS)
 else
-	@echo Boot image signing: Encryption is enabled.
-	$(PYTHON) $(APP_IMAGE_SIGN_CMD) --bin $(BOOTIMAGE_NAME) --authtype 1 --key $(APP_SIGNING_KEY) --enc y --enckey $(APP_ENCRYPTION_KEY) --output $(BOOTIMAGE_NAME_HS)
-	$(RM) $(BOOTIMAGE_NAME)-enc
+	@echo Boot image signing: Encryption is disabled. RSASSAPSS is enabled.
+	$(PYTHON) $(APP_IMAGE_SIGN_CMD) --bin $(BOOTIMAGE_NAME_MCELF) --key $(APP_SIGNING_KEY) --sign_key_id $(APP_SIGNING_KEY_KEYRING_ID) --hash_algo $(APP_SIGNING_HASH_ALGO) --pss_saltlen $(APP_SIGNING_SALT_LENGTH) --output $(BOOTIMAGE_NAME_MCELF_HS) --rsassa_pss
 endif
-	$(RM) $(BOOTIMAGE_NAME)
-	@echo  Boot image: am261x:r5fss0-0:freertos:ti-arm-clang $(BOOTIMAGE_PATH)/$(BOOTIMAGE_NAME_HS) Done !!!
-	@echo  .
 else
-# Sign the appimage for HS-FS using appimage signing script
-	$(PYTHON) $(APP_IMAGE_SIGN_CMD) --bin $(BOOTIMAGE_NAME) --authtype 1 --key $(APP_SIGNING_KEY) --output $(BOOTIMAGE_NAME_HS_FS)
-	$(RM) $(BOOTIMAGE_NAME)
-	@echo  Boot image: am261x:r5fss0-0:freertos:ti-arm-clang $(BOOTIMAGE_PATH)/$(BOOTIMAGE_NAME_HS_FS) Done !!!
+ifeq ($(RSASSAPSS_ENABLED),no)
+	@echo Boot image signing: Encryption is enabled.
+	$(PYTHON) $(APP_IMAGE_SIGN_CMD) --bin $(BOOTIMAGE_NAME_MCELF) --key $(APP_SIGNING_KEY) --enc y --enckey $(APP_ENCRYPTION_KEY) --kd-salt $(KD_SALT) --sign_key_id $(APP_SIGNING_KEY_KEYRING_ID) --enc_key_id $(APP_ENCRYPTION_KEY_KEYRING_ID) --hash_algo $(APP_SIGNING_HASH_ALGO) --output $(BOOTIMAGE_NAME_MCELF_HS)
+	$(RM) $(BOOTIMAGE_NAME_MCELF)-enc
+else
+	@echo Boot image signing: Encryption is enabled. RSASSAPSS is enabled.
+	$(PYTHON) $(APP_IMAGE_SIGN_CMD) --bin $(BOOTIMAGE_NAME_MCELF) --key $(APP_SIGNING_KEY) --enc y --enckey $(APP_ENCRYPTION_KEY) --kd-salt $(KD_SALT) --sign_key_id $(APP_SIGNING_KEY_KEYRING_ID) --enc_key_id $(APP_ENCRYPTION_KEY_KEYRING_ID) --hash_algo $(APP_SIGNING_HASH_ALGO) --pss_saltlen $(APP_SIGNING_SALT_LENGTH) --output $(BOOTIMAGE_NAME_MCELF_HS) --rsassa_pss
+	$(RM) $(BOOTIMAGE_NAME_MCELF)-enc
+endif
+endif
+	@echo  Boot image: am261x:r5fss0-0:freertos:ti-arm-clang $(BOOTIMAGE_PATH)/$(BOOTIMAGE_NAME_MCELF_HS) Done !!!
 	@echo  .
 endif
 
diff --git a/examples/uart_crc/mcuplus/am261x-lp/r5fss0-0_freertos/ti-arm-clang/makefile.defs b/examples/uart_crc/mcuplus/am261x-lp/r5fss0-0_freertos/ti-arm-clang/makefile.defs
new file mode 100644
index 0000000..4f41ac3
--- /dev/null
+++ b/examples/uart_crc/mcuplus/am261x-lp/r5fss0-0_freertos/ti-arm-clang/makefile.defs
@@ -0,0 +1,14 @@
+GEN_FILES__QUOTED += \
+*.appimage* \
+*.appimage_xip \
+*.rprc* \
+*.rprc_xip \
+*.tiimage* \
+*.bin \
+*.lnkxml \
+*.map \
+*.ossr
+
+GEN_FILES__QUOTED += \
+*.mcelf* \
+*.mcelf_xip
diff --git a/examples/uart_crc/mcuplus/am261x-lp/r5fss0-0_freertos/ti-arm-clang/makefile_ccs_bootimage_gen b/examples/uart_crc/mcuplus/am261x-lp/r5fss0-0_freertos/ti-arm-clang/makefile_ccs_bootimage_gen
index 9c2450e..fe5c5f6 100644
--- a/examples/uart_crc/mcuplus/am261x-lp/r5fss0-0_freertos/ti-arm-clang/makefile_ccs_bootimage_gen
+++ b/examples/uart_crc/mcuplus/am261x-lp/r5fss0-0_freertos/ti-arm-clang/makefile_ccs_bootimage_gen
@@ -25,12 +25,13 @@ endif
 
 OUTFILE=$(PROFILE)/$(OUTNAME).out
 BOOTIMAGE_PATH=$(abspath ${PROFILE})
-BOOTIMAGE_NAME:=$(BOOTIMAGE_PATH)/$(OUTNAME).appimage
-BOOTIMAGE_NAME_XIP:=$(BOOTIMAGE_PATH)/$(OUTNAME).appimage_xip
-BOOTIMAGE_NAME_SIGNED:=$(BOOTIMAGE_PATH)/$(OUTNAME).appimage.signed
-BOOTIMAGE_RPRC_NAME:=$(BOOTIMAGE_PATH)/$(OUTNAME).rprc
-BOOTIMAGE_RPRC_NAME_XIP:=$(BOOTIMAGE_PATH)/$(OUTNAME).rprc_xip
-BOOTIMAGE_RPRC_NAME_TMP:=$(BOOTIMAGE_PATH)/$(OUTNAME).rprc_tmp
+BOOTIMAGE_NAME_MCELF:=$(BOOTIMAGE_PATH)/$(OUTNAME).mcelf
+BOOTIMAGE_NAME_MCELF_HS:=$(BOOTIMAGE_PATH)/$(OUTNAME).mcelf.hs
+TARGETS += $(BOOTIMAGE_NAME_MCELF)
+TARGETS += $(BOOTIMAGE_NAME_MCELF_HS)
+ifeq ($(DEVICE_TYPE), HS)
+   TARGETS += $(BOOTIMAGE_NAME_MCELF_HS)
+endif
 
 #
 # Generation of boot image which can be loaded by Secondary Boot Loader (SBL)
@@ -45,69 +46,50 @@ else
 endif
 BOOTIMAGE_TEMP_OUT_FILE=$(PROFILE)/temp_stdout_$(PROFILE).txt
 
-BOOTIMAGE_CORE_ID_r5fss0-0 = 4
-BOOTIMAGE_CORE_ID_r5fss0-1 = 5
-BOOTIMAGE_CORE_ID_r5fss1-0 = 6
-BOOTIMAGE_CORE_ID_r5fss1-1 = 7
-BOOTIMAGE_CORE_ID_m4fss0-0 = 14
-SBL_RUN_ADDRESS=0x70000000
+BOOTIMAGE_CORE_ID_r5fss0-0 = 0
+BOOTIMAGE_CORE_ID_r5fss0-1 = 1
+BOOTIMAGE_CORE_ID_r5fss1-0 = 2
+BOOTIMAGE_CORE_ID_r5fss1-1 = 3
+SBL_RUN_ADDRESS=0x70002000
 SBL_DEV_ID=55
 
-MULTI_CORE_IMAGE_GEN = $(CCS_NODE) $(MCU_PLUS_SDK_PATH)/tools/boot/multicoreImageGen/multicoreImageGen.js
-OUTRPRC_CMD = $(CCS_NODE) $(MCU_PLUS_SDK_PATH)/tools/boot/out2rprc/elf2rprc.js
-APP_IMAGE_SIGN_CMD = $(MCU_PLUS_SDK_PATH)/source/security/security_common/tools/boot/signing/appimage_x509_cert_gen.py
-
-ifeq ($(OS),Windows_NT)
-  XIPGEN_CMD=$(MCU_PLUS_SDK_PATH)/tools/boot/xipGen/xipGen.exe
-else
-  UNAME_S = $(shell uname -s)
-  ifeq ($(UNAME_S), Darwin)
-    XIPGEN_CMD=$(MCU_PLUS_SDK_PATH)/tools/boot/xipGen/xipGen.out.mac
-  else
-    XIPGEN_CMD=$(MCU_PLUS_SDK_PATH)/tools/boot/xipGen/xipGen.out
-endif
-endif
-
-MULTI_CORE_IMAGE_PARAMS = \
-	$(BOOTIMAGE_RPRC_NAME)@$(BOOTIMAGE_CORE_ID_r5fss0-0) \
-
-MULTI_CORE_IMAGE_PARAMS_XIP = \
-	$(BOOTIMAGE_RPRC_NAME_XIP)@$(BOOTIMAGE_CORE_ID_r5fss0-0)  \
+APP_IMAGE_SIGN_CMD = $(MCU_PLUS_SDK_PATH)/source/security/security_common/tools/boot/signing/mcu_appimage_x509_cert_gen.py
+MCELF_IMAGE_GEN = $(MCU_PLUS_SDK_PATH)/tools/boot/multicore-elf/genimage.py
 
 all:
 ifeq ($(CCS_IDE_MODE),cloud)
 #	No post build steps
 else
-	@echo  Boot image: am261x:r5fss0-0:freertos:ti-arm-clang $(BOOTIMAGE_NAME)  ...
-	$(OUTRPRC_CMD) $(OUTFILE) >> $(BOOTIMAGE_TEMP_OUT_FILE)
-	$(COPY) $(OUTNAME).rprc $(BOOTIMAGE_RPRC_NAME)
-	$(COPY) $(BOOTIMAGE_RPRC_NAME) $(BOOTIMAGE_RPRC_NAME_TMP)
-	$(RM) $(BOOTIMAGE_RPRC_NAME)
-	$(XIPGEN_CMD) -i $(BOOTIMAGE_RPRC_NAME_TMP) -o $(BOOTIMAGE_RPRC_NAME) -x $(BOOTIMAGE_RPRC_NAME_XIP) --flash-start-addr 0x60000000 -v > $(BOOTIMAGE_TEMP_OUT_FILE)
-	$(MULTI_CORE_IMAGE_GEN) --devID $(SBL_DEV_ID) --out $(BOOTIMAGE_NAME) $(MULTI_CORE_IMAGE_PARAMS) >> $(BOOTIMAGE_TEMP_OUT_FILE)
-	$(MULTI_CORE_IMAGE_GEN) --devID $(SBL_DEV_ID) --out $(BOOTIMAGE_NAME_XIP) $(MULTI_CORE_IMAGE_PARAMS_XIP) >> $(BOOTIMAGE_TEMP_OUT_FILE)
-ifeq ($(DEVICE_TYPE),HS)
+
+	@echo  Boot multi-core ELF image: am261x:r5fss0-0:freertos:ti-arm-clang $(BOOTIMAGE_NAME_MCELF) ...
+
+	$(PYTHON) $(MCELF_IMAGE_GEN) --core-img=$(BOOTIMAGE_CORE_ID_r5fss0-0):$(OUTFILE) --output=$(BOOTIMAGE_NAME_MCELF) --merge-segments=$(MCELF_MERGE_SEGMENTS_FLAG) --tolerance-limit=$(MCELF_MERGE_SEGMENTS_TOLERANCE_LIMIT) --ignore-context=$(MCELF_IGNORE_CONTEXT_FLAG) --xip=$(MCELF_XIP_RANGE) --xlat=$(MCELF_ADDR_TRANSLATION_PATH) --max-segment-size=$(MCELF_MAX_SEGMENT_SIZE)
+
+	@echo  Boot multi-core ELF image: $(BOOTIMAGE_NAME_MCELF) Done !!!
+	@echo  .
+
+ifeq ($(DEVICE_TYPE), HS)
 # Sign the appimage using appimage signing script
 ifeq ($(ENC_ENABLED),no)
+ifeq ($(RSASSAPSS_ENABLED),no)
 	@echo Boot image signing: Encryption is disabled.
-	$(PYTHON) $(APP_IMAGE_SIGN_CMD) --bin $(BOOTIMAGE_NAME) --authtype 1 --key $(APP_SIGNING_KEY) --output $(BOOTIMAGE_NAME).hs
-	$(RM) $(BOOTIMAGE_NAME)
+	$(PYTHON) $(APP_IMAGE_SIGN_CMD) --bin $(BOOTIMAGE_NAME_MCELF) --key $(APP_SIGNING_KEY) --sign_key_id $(APP_SIGNING_KEY_KEYRING_ID) --hash_algo $(APP_SIGNING_HASH_ALGO) --output $(BOOTIMAGE_NAME_MCELF_HS)
 else
-	@echo Boot image signing: Encryption is enabled.
-	$(PYTHON) $(APP_IMAGE_SIGN_CMD) --bin $(BOOTIMAGE_NAME) --authtype 1 --key $(APP_SIGNING_KEY) --enc y --enckey $(APP_ENCRYPTION_KEY) --output $(BOOTIMAGE_NAME).hs
-	$(RM) $(BOOTIMAGE_NAME)-enc
+	@echo Boot image signing: Encryption is disabled. RSASSA-PSS is enabled.
+	$(PYTHON) $(APP_IMAGE_SIGN_CMD) --bin $(BOOTIMAGE_NAME_MCELF) --key $(APP_SIGNING_KEY) --sign_key_id $(APP_SIGNING_KEY_KEYRING_ID) --hash_algo $(APP_SIGNING_HASH_ALGO) --pss_saltlen $(APP_SIGNING_SALT_LENGTH) --output $(BOOTIMAGE_NAME_MCELF_HS) --rsassa_pss
 endif
 else
-# Sign the appimage for HS-FS using appimage signing script
-	$(PYTHON) $(APP_IMAGE_SIGN_CMD) --bin $(BOOTIMAGE_NAME) --authtype 1 --key $(APP_SIGNING_KEY) --output $(BOOTIMAGE_NAME).hs_fs
-	$(RM) $(BOOTIMAGE_NAME)
-endif
-	$(RM) $(BOOTIMAGE_RPRC_NAME_TMP)
-ifeq ($(DEVICE_TYPE),HS)
-	@echo  Boot image: am261x:r5fss0-0:freertos:ti-arm-clang $(BOOTIMAGE_NAME).hs Done !!!
-	@echo  .
+ifeq ($(RSASSAPSS_ENABLED),no)
+	@echo Boot image signing: Encryption is enabled.
+	$(PYTHON) $(APP_IMAGE_SIGN_CMD) --bin $(BOOTIMAGE_NAME_MCELF) --key $(APP_SIGNING_KEY) --enc y --enckey $(APP_ENCRYPTION_KEY) --kd-salt $(KD_SALT) --sign_key_id $(APP_SIGNING_KEY_KEYRING_ID) --enc_key_id $(APP_ENCRYPTION_KEY_KEYRING_ID) --hash_algo $(APP_SIGNING_HASH_ALGO) --output $(BOOTIMAGE_NAME_MCELF_HS)
+	$(RM) $(BOOTIMAGE_NAME_MCELF)-enc
 else
-	@echo  Boot image: am261x:r5fss0-0:freertos:ti-arm-clang $(BOOTIMAGE_NAME).hs_fs Done !!!
+	@echo Boot image signing: Encryption is enabled. RSASSA-PSS is enabled.
+	$(PYTHON) $(APP_IMAGE_SIGN_CMD) --bin $(BOOTIMAGE_NAME_MCELF) --key $(APP_SIGNING_KEY) --enc y --enckey $(APP_ENCRYPTION_KEY) --kd-salt $(KD_SALT) --sign_key_id $(APP_SIGNING_KEY_KEYRING_ID) --enc_key_id $(APP_ENCRYPTION_KEY_KEYRING_ID) --hash_algo $(APP_SIGNING_HASH_ALGO) --pss_saltlen $(APP_SIGNING_SALT_LENGTH) --output $(BOOTIMAGE_NAME_MCELF_HS) --rsassa_pss
+	$(RM) $(BOOTIMAGE_NAME_MCELF)-enc
+endif
+endif
+	@echo  Boot image: am261x:r5fss0-0:freertos:ti-arm-clang $(BOOTIMAGE_PATH)/$(BOOTIMAGE_NAME_MCELF_HS) Done !!!
 	@echo  .
 endif
 endif