diff --git a/designs/gt2n/snitch_cluster/BUILD.bazel b/designs/gt2n/snitch_cluster/BUILD.bazel
new file mode 100644
index 00000000..f7058166
--- /dev/null
+++ b/designs/gt2n/snitch_cluster/BUILD.bazel
@@ -0,0 +1,40 @@
+load("//:defs.bzl", "hightide_design")
+
+filegroup(
+    name = "sram_lefs",
+    srcs = glob(["sram/lef/*.lef"]),
+)
+
+filegroup(
+    name = "sram_libs",
+    srcs = glob(["sram/lib/*.lib"]),
+)
+
+hightide_design(
+    name = "snitch_cluster",
+    top = "snitch_cluster_wrapper",
+    platform = "gt2n",
+    verilog_files = ["//designs/src/snitch_cluster:rtl"],
+    sources = {
+        "SDC_FILE": [":constraint.sdc"],
+        "IO_CONSTRAINTS": [":io.tcl"],
+        "FOOTPRINT_TCL": [":io.tcl"],
+        "ADDITIONAL_LEFS": [":sram_lefs"],
+        "ADDITIONAL_LIBS": [":sram_libs"],
+    },
+    stage_data = {"synth": ["//designs/src/snitch_cluster:rtl_data"]},
+    arguments = {
+        "SYNTH_HDL_FRONTEND": "slang",
+        "VERILOG_INCLUDE_DIRS": "external/+_repo_rules+snitch_common_cells_src/include external/+_repo_rules+pulp_apb_src/include external/+_repo_rules+snitch_axi_src/include external/+_repo_rules+pulp_axi_stream_src/include external/+_repo_rules+pulp_obi_src/include external/+_repo_rules+pulp_register_interface_src/include external/+_repo_rules+pulp_idma_src/src/include external/+_repo_rules+pulp_idma_src/target/rtl/include external/+_repo_rules+snitch_cluster_src/hw/dca_interface/include external/+_repo_rules+snitch_cluster_src/hw/mem_interface/include external/+_repo_rules+snitch_cluster_src/hw/reqrsp_interface/include external/+_repo_rules+snitch_cluster_src/hw/snitch/include external/+_repo_rules+snitch_cluster_src/hw/snitch_fp_ss/include external/+_repo_rules+snitch_cluster_src/hw/snitch_ssr/include external/+_repo_rules+snitch_cluster_src/hw/tcdm_interface/include",
+        "VERILOG_DEFINES": "-D VERILATOR",
+        "SYNTH_MEMORY_MAX_BITS": "8193",
+        "SYNTH_HIERARCHICAL": "1",
+        "SYNTH_ARGS": "-noshare",
+        "CORE_UTILIZATION": "55",
+        "PLACE_DENSITY": "0.67",
+        "MACRO_PLACE_HALO": "8 8",
+        "TNS_END_PERCENT": "100",
+        "MIN_CLK_ROUTING_LAYER" : "M4",
+        "MAX_ROUTING_LAYER" : "M11",
+    },
+)
diff --git a/designs/gt2n/snitch_cluster/constraint.sdc b/designs/gt2n/snitch_cluster/constraint.sdc
new file mode 100644
index 00000000..82ffb7a7
--- /dev/null
+++ b/designs/gt2n/snitch_cluster/constraint.sdc
@@ -0,0 +1,20 @@
+current_design snitch_cluster_wrapper
+
+set clk_name  clk
+set clk_port_name clk_i
+set clk_period 6000
+
+set clk_port [get_ports $clk_port_name]
+
+create_clock -name $clk_name -period $clk_period $clk_port
+
+set non_clock_inputs [all_inputs -no_clocks]
+# Split -min/-max input delay: same reasoning as the asap7/nangate45 SDCs
+# (see their constraint.sdc). Basically simulating launch side network latency for IO paths.
+
+set_input_delay -max 10   -clock $clk_name $non_clock_inputs
+set_input_delay -min 1500 -clock $clk_name $non_clock_inputs
+set_output_delay 10 -clock $clk_name [all_outputs]
+
+# Async reset: exclude recovery/removal checks on rst_ni.
+set_false_path -from [get_ports rst_ni]
diff --git a/designs/gt2n/snitch_cluster/io.tcl b/designs/gt2n/snitch_cluster/io.tcl
new file mode 100644
index 00000000..1c5db05b
--- /dev/null
+++ b/designs/gt2n/snitch_cluster/io.tcl
@@ -0,0 +1,106 @@
+# IO pin placement for snitch_cluster_wrapper (gt2n)
+# Distributes all pins evenly across all four die edges in port order.
+# Same generic approach as the asap7/nangate45 io.tcl (query the design for
+# ports rather than hardcoding names), retargeted to gt2n's IO placer layers
+# and pitch. Uses edge_margin inward from the die boundary rather than
+# -force_to_die_boundary -- see designs/gt2n/floonoc/io.tcl and
+# designs/gt2n/gemmini/io.tcl, which hit GRT-0209 "pin completely outside
+# die" with the boundary-forced form.
+#
+# ── gt2n layer config (from platforms/gt2n/config.mk + lef/gt2_tech.lef) ──
+# IO_PLACER_H = M2 (HORIZONTAL layer -> left/right edge pins), pitch 0.024, width 0.012
+# IO_PLACER_V = M3 (VERTICAL layer -> top/bottom edge pins), pitch 0.028, width 0.014
+
+set hor_layer  M2
+set ver_layer  M3
+set hor_offset 0.006
+set hor_pitch  0.024
+set ver_offset 0.007
+set ver_pitch  0.028
+
+set edge_margin 5.0  ;# distance inward from die edge (avoids GRT-0209)
+set end_margin  2.0  ;# distance from corner along the edge
+
+proc snap_track {val offset pitch} {
+    set n [expr {round(($val - $offset) / $pitch)}]
+    return [expr {$offset + $n * $pitch}]
+}
+
+# ── Place pins evenly along an edge, edge_margin inside the die boundary ──
+proc place_edge {edge layer pins} {
+    upvar edge_margin em end_margin sm
+    upvar hor_offset ho hor_pitch hp ver_offset vo ver_pitch vp
+
+    set n [llength $pins]
+    if {$n == 0} return
+    lassign [ord::get_die_area] lx ly ux uy
+
+    switch $edge {
+        left - right {
+            set fixed_x [expr {$edge eq "left" ? $lx + $em : $ux - $em}]
+            set lo [expr {$ly + $sm}]
+            set hi [expr {$uy - $sm}]
+            for {set i 0} {$i < $n} {incr i} {
+                set frac [expr {($i + 0.5) / double($n)}]
+                set raw_y [expr {$lo + $frac * ($hi - $lo)}]
+                set y [snap_track $raw_y $ho $hp]
+                place_pin -pin_name [lindex $pins $i] -layer $layer \
+                    -location [list $fixed_x $y]
+            }
+        }
+        top - bottom {
+            set fixed_y [expr {$edge eq "top" ? $uy - $em : $ly + $em}]
+            set lo [expr {$lx + $sm}]
+            set hi [expr {$ux - $sm}]
+            for {set i 0} {$i < $n} {incr i} {
+                set frac [expr {($i + 0.5) / double($n)}]
+                set raw_x [expr {$lo + $frac * ($hi - $lo)}]
+                set x [snap_track $raw_x $vo $vp]
+                place_pin -pin_name [lindex $pins $i] -layer $layer \
+                    -location [list $x $fixed_y]
+            }
+        }
+    }
+}
+
+# ── Collect all pins by querying the design ──
+set all_inputs {}
+set all_outputs {}
+
+foreach pin [lsort [get_ports -filter "direction == input"]] {
+    set name [get_name $pin]
+    if {$name eq "clk_i" || $name eq "rst_ni"} continue
+    lappend all_inputs $name
+}
+
+foreach pin [lsort [get_ports -filter "direction == output"]] {
+    lappend all_outputs [get_name $pin]
+}
+
+# ── Distribute pins across 4 edges ──
+# Strategy: inputs on left + bottom, outputs on right + top, clock/reset on top.
+set n_in [llength $all_inputs]
+set n_out [llength $all_outputs]
+
+set in_half [expr {$n_in / 2}]
+set left_pins [lrange $all_inputs 0 [expr {$in_half - 1}]]
+set bottom_pins [lrange $all_inputs $in_half end]
+
+set out_half [expr {$n_out / 2}]
+set right_pins [lrange $all_outputs 0 [expr {$out_half - 1}]]
+set top_pins [concat [lrange $all_outputs $out_half end] {clk_i rst_ni}]
+
+puts "Placing [llength $left_pins] pins on LEFT edge ($hor_layer)"
+place_edge left $hor_layer $left_pins
+
+puts "Placing [llength $right_pins] pins on RIGHT edge ($hor_layer)"
+place_edge right $hor_layer $right_pins
+
+puts "Placing [llength $top_pins] pins on TOP edge ($ver_layer)"
+place_edge top $ver_layer $top_pins
+
+puts "Placing [llength $bottom_pins] pins on BOTTOM edge ($ver_layer)"
+place_edge bottom $ver_layer $bottom_pins
+
+set total [expr {[llength $left_pins] + [llength $right_pins] + [llength $top_pins] + [llength $bottom_pins]}]
+puts "Total pins placed: $total"
diff --git a/designs/gt2n/snitch_cluster/sram/lef/fakeram7_128x48.lef b/designs/gt2n/snitch_cluster/sram/lef/fakeram7_128x48.lef
new file mode 100644
index 00000000..8f61c75a
--- /dev/null
+++ b/designs/gt2n/snitch_cluster/sram/lef/fakeram7_128x48.lef
@@ -0,0 +1,1179 @@
+VERSION 5.7 ;
+BUSBITCHARS "[]" ;
+MACRO fakeram7_128x48
+  FOREIGN fakeram7_128x48 0 0 ;
+  SYMMETRY X Y R90 ;
+  SIZE 22.050 BY 36.720 ;
+  CLASS BLOCK ;
+  PIN rw0_wd_in[0]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M2 ;
+      RECT 0.000 0.138 0.036 0.150 ;
+    END
+  END rw0_wd_in[0]
+  PIN rw0_wd_in[1]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M2 ;
+      RECT 0.000 2.394 0.036 2.406 ;
+    END
+  END rw0_wd_in[1]
+  PIN rw0_wd_in[2]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M2 ;
+      RECT 0.000 4.650 0.036 4.662 ;
+    END
+  END rw0_wd_in[2]
+  PIN rw0_wd_in[3]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M2 ;
+      RECT 0.000 6.906 0.036 6.918 ;
+    END
+  END rw0_wd_in[3]
+  PIN rw0_wd_in[4]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M2 ;
+      RECT 0.000 9.162 0.036 9.174 ;
+    END
+  END rw0_wd_in[4]
+  PIN rw0_wd_in[5]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M2 ;
+      RECT 0.000 11.418 0.036 11.430 ;
+    END
+  END rw0_wd_in[5]
+  PIN rw0_wd_in[6]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M2 ;
+      RECT 0.000 13.674 0.036 13.686 ;
+    END
+  END rw0_wd_in[6]
+  PIN rw0_wd_in[7]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M2 ;
+      RECT 0.000 15.930 0.036 15.942 ;
+    END
+  END rw0_wd_in[7]
+  PIN rw0_wd_in[8]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M2 ;
+      RECT 0.000 18.186 0.036 18.198 ;
+    END
+  END rw0_wd_in[8]
+  PIN rw0_wd_in[9]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M2 ;
+      RECT 0.000 20.442 0.036 20.454 ;
+    END
+  END rw0_wd_in[9]
+  PIN rw0_wd_in[10]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M2 ;
+      RECT 0.000 22.698 0.036 22.710 ;
+    END
+  END rw0_wd_in[10]
+  PIN rw0_wd_in[11]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M2 ;
+      RECT 0.000 24.954 0.036 24.966 ;
+    END
+  END rw0_wd_in[11]
+  PIN rw0_wd_in[12]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M2 ;
+      RECT 22.014 0.138 22.050 0.150 ;
+    END
+  END rw0_wd_in[12]
+  PIN rw0_wd_in[13]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M2 ;
+      RECT 22.014 2.394 22.050 2.406 ;
+    END
+  END rw0_wd_in[13]
+  PIN rw0_wd_in[14]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M2 ;
+      RECT 22.014 4.650 22.050 4.662 ;
+    END
+  END rw0_wd_in[14]
+  PIN rw0_wd_in[15]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M2 ;
+      RECT 22.014 6.906 22.050 6.918 ;
+    END
+  END rw0_wd_in[15]
+  PIN rw0_wd_in[16]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M2 ;
+      RECT 22.014 9.162 22.050 9.174 ;
+    END
+  END rw0_wd_in[16]
+  PIN rw0_wd_in[17]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M2 ;
+      RECT 22.014 11.418 22.050 11.430 ;
+    END
+  END rw0_wd_in[17]
+  PIN rw0_wd_in[18]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M2 ;
+      RECT 22.014 13.674 22.050 13.686 ;
+    END
+  END rw0_wd_in[18]
+  PIN rw0_wd_in[19]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M2 ;
+      RECT 22.014 15.930 22.050 15.942 ;
+    END
+  END rw0_wd_in[19]
+  PIN rw0_wd_in[20]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M2 ;
+      RECT 22.014 18.186 22.050 18.198 ;
+    END
+  END rw0_wd_in[20]
+  PIN rw0_wd_in[21]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M2 ;
+      RECT 22.014 20.442 22.050 20.454 ;
+    END
+  END rw0_wd_in[21]
+  PIN rw0_wd_in[22]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M2 ;
+      RECT 22.014 22.698 22.050 22.710 ;
+    END
+  END rw0_wd_in[22]
+  PIN rw0_wd_in[23]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M2 ;
+      RECT 22.014 24.954 22.050 24.966 ;
+    END
+  END rw0_wd_in[23]
+  PIN rw0_wd_in[24]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 0.161 0.000 0.175 0.042 ;
+    END
+  END rw0_wd_in[24]
+  PIN rw0_wd_in[25]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 0.609 0.000 0.623 0.042 ;
+    END
+  END rw0_wd_in[25]
+  PIN rw0_wd_in[26]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 1.057 0.000 1.071 0.042 ;
+    END
+  END rw0_wd_in[26]
+  PIN rw0_wd_in[27]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 1.505 0.000 1.519 0.042 ;
+    END
+  END rw0_wd_in[27]
+  PIN rw0_wd_in[28]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 1.953 0.000 1.967 0.042 ;
+    END
+  END rw0_wd_in[28]
+  PIN rw0_wd_in[29]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 2.401 0.000 2.415 0.042 ;
+    END
+  END rw0_wd_in[29]
+  PIN rw0_wd_in[30]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 2.849 0.000 2.863 0.042 ;
+    END
+  END rw0_wd_in[30]
+  PIN rw0_wd_in[31]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 3.297 0.000 3.311 0.042 ;
+    END
+  END rw0_wd_in[31]
+  PIN rw0_wd_in[32]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 3.745 0.000 3.759 0.042 ;
+    END
+  END rw0_wd_in[32]
+  PIN rw0_wd_in[33]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 4.193 0.000 4.207 0.042 ;
+    END
+  END rw0_wd_in[33]
+  PIN rw0_wd_in[34]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 4.641 0.000 4.655 0.042 ;
+    END
+  END rw0_wd_in[34]
+  PIN rw0_wd_in[35]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 5.089 0.000 5.103 0.042 ;
+    END
+  END rw0_wd_in[35]
+  PIN rw0_wd_in[36]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 5.537 0.000 5.551 0.042 ;
+    END
+  END rw0_wd_in[36]
+  PIN rw0_wd_in[37]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 5.985 0.000 5.999 0.042 ;
+    END
+  END rw0_wd_in[37]
+  PIN rw0_wd_in[38]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 6.433 0.000 6.447 0.042 ;
+    END
+  END rw0_wd_in[38]
+  PIN rw0_wd_in[39]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 6.881 0.000 6.895 0.042 ;
+    END
+  END rw0_wd_in[39]
+  PIN rw0_wd_in[40]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 7.329 0.000 7.343 0.042 ;
+    END
+  END rw0_wd_in[40]
+  PIN rw0_wd_in[41]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 7.777 0.000 7.791 0.042 ;
+    END
+  END rw0_wd_in[41]
+  PIN rw0_wd_in[42]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 8.225 0.000 8.239 0.042 ;
+    END
+  END rw0_wd_in[42]
+  PIN rw0_wd_in[43]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 8.673 0.000 8.687 0.042 ;
+    END
+  END rw0_wd_in[43]
+  PIN rw0_wd_in[44]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 9.121 0.000 9.135 0.042 ;
+    END
+  END rw0_wd_in[44]
+  PIN rw0_wd_in[45]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 9.569 0.000 9.583 0.042 ;
+    END
+  END rw0_wd_in[45]
+  PIN rw0_wd_in[46]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 10.017 0.000 10.031 0.042 ;
+    END
+  END rw0_wd_in[46]
+  PIN rw0_wd_in[47]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 10.465 0.000 10.479 0.042 ;
+    END
+  END rw0_wd_in[47]
+  PIN rw0_rd_out[0]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 10.913 0.000 10.927 0.042 ;
+    END
+  END rw0_rd_out[0]
+  PIN rw0_rd_out[1]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 11.361 0.000 11.375 0.042 ;
+    END
+  END rw0_rd_out[1]
+  PIN rw0_rd_out[2]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 11.809 0.000 11.823 0.042 ;
+    END
+  END rw0_rd_out[2]
+  PIN rw0_rd_out[3]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 12.257 0.000 12.271 0.042 ;
+    END
+  END rw0_rd_out[3]
+  PIN rw0_rd_out[4]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 12.705 0.000 12.719 0.042 ;
+    END
+  END rw0_rd_out[4]
+  PIN rw0_rd_out[5]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 13.153 0.000 13.167 0.042 ;
+    END
+  END rw0_rd_out[5]
+  PIN rw0_rd_out[6]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 13.601 0.000 13.615 0.042 ;
+    END
+  END rw0_rd_out[6]
+  PIN rw0_rd_out[7]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 14.049 0.000 14.063 0.042 ;
+    END
+  END rw0_rd_out[7]
+  PIN rw0_rd_out[8]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 14.497 0.000 14.511 0.042 ;
+    END
+  END rw0_rd_out[8]
+  PIN rw0_rd_out[9]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 14.945 0.000 14.959 0.042 ;
+    END
+  END rw0_rd_out[9]
+  PIN rw0_rd_out[10]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 15.393 0.000 15.407 0.042 ;
+    END
+  END rw0_rd_out[10]
+  PIN rw0_rd_out[11]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 15.841 0.000 15.855 0.042 ;
+    END
+  END rw0_rd_out[11]
+  PIN rw0_rd_out[12]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 16.289 0.000 16.303 0.042 ;
+    END
+  END rw0_rd_out[12]
+  PIN rw0_rd_out[13]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 16.737 0.000 16.751 0.042 ;
+    END
+  END rw0_rd_out[13]
+  PIN rw0_rd_out[14]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 17.185 0.000 17.199 0.042 ;
+    END
+  END rw0_rd_out[14]
+  PIN rw0_rd_out[15]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 17.633 0.000 17.647 0.042 ;
+    END
+  END rw0_rd_out[15]
+  PIN rw0_rd_out[16]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 18.081 0.000 18.095 0.042 ;
+    END
+  END rw0_rd_out[16]
+  PIN rw0_rd_out[17]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 18.529 0.000 18.543 0.042 ;
+    END
+  END rw0_rd_out[17]
+  PIN rw0_rd_out[18]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 18.977 0.000 18.991 0.042 ;
+    END
+  END rw0_rd_out[18]
+  PIN rw0_rd_out[19]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 19.425 0.000 19.439 0.042 ;
+    END
+  END rw0_rd_out[19]
+  PIN rw0_rd_out[20]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 19.873 0.000 19.887 0.042 ;
+    END
+  END rw0_rd_out[20]
+  PIN rw0_rd_out[21]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 20.321 0.000 20.335 0.042 ;
+    END
+  END rw0_rd_out[21]
+  PIN rw0_rd_out[22]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 20.769 0.000 20.783 0.042 ;
+    END
+  END rw0_rd_out[22]
+  PIN rw0_rd_out[23]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 21.217 0.000 21.231 0.042 ;
+    END
+  END rw0_rd_out[23]
+  PIN rw0_rd_out[24]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 0.161 36.678 0.175 36.720 ;
+    END
+  END rw0_rd_out[24]
+  PIN rw0_rd_out[25]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 0.945 36.678 0.959 36.720 ;
+    END
+  END rw0_rd_out[25]
+  PIN rw0_rd_out[26]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 1.729 36.678 1.743 36.720 ;
+    END
+  END rw0_rd_out[26]
+  PIN rw0_rd_out[27]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 2.513 36.678 2.527 36.720 ;
+    END
+  END rw0_rd_out[27]
+  PIN rw0_rd_out[28]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 3.297 36.678 3.311 36.720 ;
+    END
+  END rw0_rd_out[28]
+  PIN rw0_rd_out[29]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 4.081 36.678 4.095 36.720 ;
+    END
+  END rw0_rd_out[29]
+  PIN rw0_rd_out[30]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 4.865 36.678 4.879 36.720 ;
+    END
+  END rw0_rd_out[30]
+  PIN rw0_rd_out[31]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 5.649 36.678 5.663 36.720 ;
+    END
+  END rw0_rd_out[31]
+  PIN rw0_rd_out[32]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 6.433 36.678 6.447 36.720 ;
+    END
+  END rw0_rd_out[32]
+  PIN rw0_rd_out[33]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 7.217 36.678 7.231 36.720 ;
+    END
+  END rw0_rd_out[33]
+  PIN rw0_rd_out[34]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 8.001 36.678 8.015 36.720 ;
+    END
+  END rw0_rd_out[34]
+  PIN rw0_rd_out[35]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 8.785 36.678 8.799 36.720 ;
+    END
+  END rw0_rd_out[35]
+  PIN rw0_rd_out[36]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 9.569 36.678 9.583 36.720 ;
+    END
+  END rw0_rd_out[36]
+  PIN rw0_rd_out[37]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 10.353 36.678 10.367 36.720 ;
+    END
+  END rw0_rd_out[37]
+  PIN rw0_rd_out[38]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 11.137 36.678 11.151 36.720 ;
+    END
+  END rw0_rd_out[38]
+  PIN rw0_rd_out[39]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 11.921 36.678 11.935 36.720 ;
+    END
+  END rw0_rd_out[39]
+  PIN rw0_rd_out[40]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 12.705 36.678 12.719 36.720 ;
+    END
+  END rw0_rd_out[40]
+  PIN rw0_rd_out[41]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 13.489 36.678 13.503 36.720 ;
+    END
+  END rw0_rd_out[41]
+  PIN rw0_rd_out[42]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 14.273 36.678 14.287 36.720 ;
+    END
+  END rw0_rd_out[42]
+  PIN rw0_rd_out[43]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 15.057 36.678 15.071 36.720 ;
+    END
+  END rw0_rd_out[43]
+  PIN rw0_rd_out[44]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 15.841 36.678 15.855 36.720 ;
+    END
+  END rw0_rd_out[44]
+  PIN rw0_rd_out[45]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 16.625 36.678 16.639 36.720 ;
+    END
+  END rw0_rd_out[45]
+  PIN rw0_rd_out[46]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 17.409 36.678 17.423 36.720 ;
+    END
+  END rw0_rd_out[46]
+  PIN rw0_rd_out[47]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 18.193 36.678 18.207 36.720 ;
+    END
+  END rw0_rd_out[47]
+  PIN rw0_addr_in[0]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M2 ;
+      RECT 0.000 27.210 0.036 27.222 ;
+    END
+  END rw0_addr_in[0]
+  PIN rw0_addr_in[1]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M2 ;
+      RECT 0.000 29.466 0.036 29.478 ;
+    END
+  END rw0_addr_in[1]
+  PIN rw0_addr_in[2]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M2 ;
+      RECT 0.000 31.722 0.036 31.734 ;
+    END
+  END rw0_addr_in[2]
+  PIN rw0_addr_in[3]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M2 ;
+      RECT 0.000 33.978 0.036 33.990 ;
+    END
+  END rw0_addr_in[3]
+  PIN rw0_addr_in[4]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M2 ;
+      RECT 22.014 27.210 22.050 27.222 ;
+    END
+  END rw0_addr_in[4]
+  PIN rw0_addr_in[5]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M2 ;
+      RECT 22.014 29.466 22.050 29.478 ;
+    END
+  END rw0_addr_in[5]
+  PIN rw0_addr_in[6]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M2 ;
+      RECT 22.014 31.722 22.050 31.734 ;
+    END
+  END rw0_addr_in[6]
+  PIN rw0_we_in
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 18.977 36.678 18.991 36.720 ;
+    END
+  END rw0_we_in
+  PIN rw0_ce_in
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 19.761 36.678 19.775 36.720 ;
+    END
+  END rw0_ce_in
+  PIN rw0_clk
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 20.545 36.678 20.559 36.720 ;
+    END
+  END rw0_clk
+  PIN VSS
+    DIRECTION INOUT ;
+    USE GROUND ;
+    PORT
+      LAYER M4 ;
+      RECT 0.168 0.120 21.882 0.168 ;
+      RECT 0.168 0.504 21.882 0.552 ;
+      RECT 0.168 0.888 21.882 0.936 ;
+      RECT 0.168 1.272 21.882 1.320 ;
+      RECT 0.168 1.656 21.882 1.704 ;
+      RECT 0.168 2.040 21.882 2.088 ;
+      RECT 0.168 2.424 21.882 2.472 ;
+      RECT 0.168 2.808 21.882 2.856 ;
+      RECT 0.168 3.192 21.882 3.240 ;
+      RECT 0.168 3.576 21.882 3.624 ;
+      RECT 0.168 3.960 21.882 4.008 ;
+      RECT 0.168 4.344 21.882 4.392 ;
+      RECT 0.168 4.728 21.882 4.776 ;
+      RECT 0.168 5.112 21.882 5.160 ;
+      RECT 0.168 5.496 21.882 5.544 ;
+      RECT 0.168 5.880 21.882 5.928 ;
+      RECT 0.168 6.264 21.882 6.312 ;
+      RECT 0.168 6.648 21.882 6.696 ;
+      RECT 0.168 7.032 21.882 7.080 ;
+      RECT 0.168 7.416 21.882 7.464 ;
+      RECT 0.168 7.800 21.882 7.848 ;
+      RECT 0.168 8.184 21.882 8.232 ;
+      RECT 0.168 8.568 21.882 8.616 ;
+      RECT 0.168 8.952 21.882 9.000 ;
+      RECT 0.168 9.336 21.882 9.384 ;
+      RECT 0.168 9.720 21.882 9.768 ;
+      RECT 0.168 10.104 21.882 10.152 ;
+      RECT 0.168 10.488 21.882 10.536 ;
+      RECT 0.168 10.872 21.882 10.920 ;
+      RECT 0.168 11.256 21.882 11.304 ;
+      RECT 0.168 11.640 21.882 11.688 ;
+      RECT 0.168 12.024 21.882 12.072 ;
+      RECT 0.168 12.408 21.882 12.456 ;
+      RECT 0.168 12.792 21.882 12.840 ;
+      RECT 0.168 13.176 21.882 13.224 ;
+      RECT 0.168 13.560 21.882 13.608 ;
+      RECT 0.168 13.944 21.882 13.992 ;
+      RECT 0.168 14.328 21.882 14.376 ;
+      RECT 0.168 14.712 21.882 14.760 ;
+      RECT 0.168 15.096 21.882 15.144 ;
+      RECT 0.168 15.480 21.882 15.528 ;
+      RECT 0.168 15.864 21.882 15.912 ;
+      RECT 0.168 16.248 21.882 16.296 ;
+      RECT 0.168 16.632 21.882 16.680 ;
+      RECT 0.168 17.016 21.882 17.064 ;
+      RECT 0.168 17.400 21.882 17.448 ;
+      RECT 0.168 17.784 21.882 17.832 ;
+      RECT 0.168 18.168 21.882 18.216 ;
+      RECT 0.168 18.552 21.882 18.600 ;
+      RECT 0.168 18.936 21.882 18.984 ;
+      RECT 0.168 19.320 21.882 19.368 ;
+      RECT 0.168 19.704 21.882 19.752 ;
+      RECT 0.168 20.088 21.882 20.136 ;
+      RECT 0.168 20.472 21.882 20.520 ;
+      RECT 0.168 20.856 21.882 20.904 ;
+      RECT 0.168 21.240 21.882 21.288 ;
+      RECT 0.168 21.624 21.882 21.672 ;
+      RECT 0.168 22.008 21.882 22.056 ;
+      RECT 0.168 22.392 21.882 22.440 ;
+      RECT 0.168 22.776 21.882 22.824 ;
+      RECT 0.168 23.160 21.882 23.208 ;
+      RECT 0.168 23.544 21.882 23.592 ;
+      RECT 0.168 23.928 21.882 23.976 ;
+      RECT 0.168 24.312 21.882 24.360 ;
+      RECT 0.168 24.696 21.882 24.744 ;
+      RECT 0.168 25.080 21.882 25.128 ;
+      RECT 0.168 25.464 21.882 25.512 ;
+      RECT 0.168 25.848 21.882 25.896 ;
+      RECT 0.168 26.232 21.882 26.280 ;
+      RECT 0.168 26.616 21.882 26.664 ;
+      RECT 0.168 27.000 21.882 27.048 ;
+      RECT 0.168 27.384 21.882 27.432 ;
+      RECT 0.168 27.768 21.882 27.816 ;
+      RECT 0.168 28.152 21.882 28.200 ;
+      RECT 0.168 28.536 21.882 28.584 ;
+      RECT 0.168 28.920 21.882 28.968 ;
+      RECT 0.168 29.304 21.882 29.352 ;
+      RECT 0.168 29.688 21.882 29.736 ;
+      RECT 0.168 30.072 21.882 30.120 ;
+      RECT 0.168 30.456 21.882 30.504 ;
+      RECT 0.168 30.840 21.882 30.888 ;
+      RECT 0.168 31.224 21.882 31.272 ;
+      RECT 0.168 31.608 21.882 31.656 ;
+      RECT 0.168 31.992 21.882 32.040 ;
+      RECT 0.168 32.376 21.882 32.424 ;
+      RECT 0.168 32.760 21.882 32.808 ;
+      RECT 0.168 33.144 21.882 33.192 ;
+      RECT 0.168 33.528 21.882 33.576 ;
+      RECT 0.168 33.912 21.882 33.960 ;
+      RECT 0.168 34.296 21.882 34.344 ;
+      RECT 0.168 34.680 21.882 34.728 ;
+      RECT 0.168 35.064 21.882 35.112 ;
+      RECT 0.168 35.448 21.882 35.496 ;
+      RECT 0.168 35.832 21.882 35.880 ;
+      RECT 0.168 36.216 21.882 36.264 ;
+      RECT 0.168 36.600 21.882 36.648 ;
+    END
+  END VSS
+  PIN VDD
+    DIRECTION INOUT ;
+    USE POWER ;
+    PORT
+      LAYER M4 ;
+      RECT 0.168 0.312 21.882 0.360 ;
+      RECT 0.168 0.696 21.882 0.744 ;
+      RECT 0.168 1.080 21.882 1.128 ;
+      RECT 0.168 1.464 21.882 1.512 ;
+      RECT 0.168 1.848 21.882 1.896 ;
+      RECT 0.168 2.232 21.882 2.280 ;
+      RECT 0.168 2.616 21.882 2.664 ;
+      RECT 0.168 3.000 21.882 3.048 ;
+      RECT 0.168 3.384 21.882 3.432 ;
+      RECT 0.168 3.768 21.882 3.816 ;
+      RECT 0.168 4.152 21.882 4.200 ;
+      RECT 0.168 4.536 21.882 4.584 ;
+      RECT 0.168 4.920 21.882 4.968 ;
+      RECT 0.168 5.304 21.882 5.352 ;
+      RECT 0.168 5.688 21.882 5.736 ;
+      RECT 0.168 6.072 21.882 6.120 ;
+      RECT 0.168 6.456 21.882 6.504 ;
+      RECT 0.168 6.840 21.882 6.888 ;
+      RECT 0.168 7.224 21.882 7.272 ;
+      RECT 0.168 7.608 21.882 7.656 ;
+      RECT 0.168 7.992 21.882 8.040 ;
+      RECT 0.168 8.376 21.882 8.424 ;
+      RECT 0.168 8.760 21.882 8.808 ;
+      RECT 0.168 9.144 21.882 9.192 ;
+      RECT 0.168 9.528 21.882 9.576 ;
+      RECT 0.168 9.912 21.882 9.960 ;
+      RECT 0.168 10.296 21.882 10.344 ;
+      RECT 0.168 10.680 21.882 10.728 ;
+      RECT 0.168 11.064 21.882 11.112 ;
+      RECT 0.168 11.448 21.882 11.496 ;
+      RECT 0.168 11.832 21.882 11.880 ;
+      RECT 0.168 12.216 21.882 12.264 ;
+      RECT 0.168 12.600 21.882 12.648 ;
+      RECT 0.168 12.984 21.882 13.032 ;
+      RECT 0.168 13.368 21.882 13.416 ;
+      RECT 0.168 13.752 21.882 13.800 ;
+      RECT 0.168 14.136 21.882 14.184 ;
+      RECT 0.168 14.520 21.882 14.568 ;
+      RECT 0.168 14.904 21.882 14.952 ;
+      RECT 0.168 15.288 21.882 15.336 ;
+      RECT 0.168 15.672 21.882 15.720 ;
+      RECT 0.168 16.056 21.882 16.104 ;
+      RECT 0.168 16.440 21.882 16.488 ;
+      RECT 0.168 16.824 21.882 16.872 ;
+      RECT 0.168 17.208 21.882 17.256 ;
+      RECT 0.168 17.592 21.882 17.640 ;
+      RECT 0.168 17.976 21.882 18.024 ;
+      RECT 0.168 18.360 21.882 18.408 ;
+      RECT 0.168 18.744 21.882 18.792 ;
+      RECT 0.168 19.128 21.882 19.176 ;
+      RECT 0.168 19.512 21.882 19.560 ;
+      RECT 0.168 19.896 21.882 19.944 ;
+      RECT 0.168 20.280 21.882 20.328 ;
+      RECT 0.168 20.664 21.882 20.712 ;
+      RECT 0.168 21.048 21.882 21.096 ;
+      RECT 0.168 21.432 21.882 21.480 ;
+      RECT 0.168 21.816 21.882 21.864 ;
+      RECT 0.168 22.200 21.882 22.248 ;
+      RECT 0.168 22.584 21.882 22.632 ;
+      RECT 0.168 22.968 21.882 23.016 ;
+      RECT 0.168 23.352 21.882 23.400 ;
+      RECT 0.168 23.736 21.882 23.784 ;
+      RECT 0.168 24.120 21.882 24.168 ;
+      RECT 0.168 24.504 21.882 24.552 ;
+      RECT 0.168 24.888 21.882 24.936 ;
+      RECT 0.168 25.272 21.882 25.320 ;
+      RECT 0.168 25.656 21.882 25.704 ;
+      RECT 0.168 26.040 21.882 26.088 ;
+      RECT 0.168 26.424 21.882 26.472 ;
+      RECT 0.168 26.808 21.882 26.856 ;
+      RECT 0.168 27.192 21.882 27.240 ;
+      RECT 0.168 27.576 21.882 27.624 ;
+      RECT 0.168 27.960 21.882 28.008 ;
+      RECT 0.168 28.344 21.882 28.392 ;
+      RECT 0.168 28.728 21.882 28.776 ;
+      RECT 0.168 29.112 21.882 29.160 ;
+      RECT 0.168 29.496 21.882 29.544 ;
+      RECT 0.168 29.880 21.882 29.928 ;
+      RECT 0.168 30.264 21.882 30.312 ;
+      RECT 0.168 30.648 21.882 30.696 ;
+      RECT 0.168 31.032 21.882 31.080 ;
+      RECT 0.168 31.416 21.882 31.464 ;
+      RECT 0.168 31.800 21.882 31.848 ;
+      RECT 0.168 32.184 21.882 32.232 ;
+      RECT 0.168 32.568 21.882 32.616 ;
+      RECT 0.168 32.952 21.882 33.000 ;
+      RECT 0.168 33.336 21.882 33.384 ;
+      RECT 0.168 33.720 21.882 33.768 ;
+      RECT 0.168 34.104 21.882 34.152 ;
+      RECT 0.168 34.488 21.882 34.536 ;
+      RECT 0.168 34.872 21.882 34.920 ;
+      RECT 0.168 35.256 21.882 35.304 ;
+      RECT 0.168 35.640 21.882 35.688 ;
+      RECT 0.168 36.024 21.882 36.072 ;
+      RECT 0.168 36.408 21.882 36.456 ;
+    END
+  END VDD
+  OBS
+    LAYER M1 ;
+    RECT 0 0 22.050 36.720 ;
+    LAYER M2 ;
+    RECT 0 0 22.050 36.720 ;
+    LAYER M3 ;
+    RECT 0 0 22.050 36.720 ;
+    LAYER M4 ;
+    RECT 0 0 22.050 36.720 ;
+  END
+END fakeram7_128x48
+
+END LIBRARY
diff --git a/designs/gt2n/snitch_cluster/sram/lef/fakeram7_256x256.lef b/designs/gt2n/snitch_cluster/sram/lef/fakeram7_256x256.lef
new file mode 100644
index 00000000..52eacbf9
--- /dev/null
+++ b/designs/gt2n/snitch_cluster/sram/lef/fakeram7_256x256.lef
@@ -0,0 +1,5123 @@
+VERSION 5.7 ;
+BUSBITCHARS "[]" ;
+MACRO fakeram7_256x256
+  FOREIGN fakeram7_256x256 0 0 ;
+  SYMMETRY X Y R90 ;
+  SIZE 117.390 BY 73.440 ;
+  CLASS BLOCK ;
+  PIN rw0_wd_in[0]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M2 ;
+      RECT 0.000 0.138 0.036 0.150 ;
+    END
+  END rw0_wd_in[0]
+  PIN rw0_wd_in[1]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M2 ;
+      RECT 0.000 1.194 0.036 1.206 ;
+    END
+  END rw0_wd_in[1]
+  PIN rw0_wd_in[2]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M2 ;
+      RECT 0.000 2.250 0.036 2.262 ;
+    END
+  END rw0_wd_in[2]
+  PIN rw0_wd_in[3]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M2 ;
+      RECT 0.000 3.306 0.036 3.318 ;
+    END
+  END rw0_wd_in[3]
+  PIN rw0_wd_in[4]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M2 ;
+      RECT 0.000 4.362 0.036 4.374 ;
+    END
+  END rw0_wd_in[4]
+  PIN rw0_wd_in[5]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M2 ;
+      RECT 0.000 5.418 0.036 5.430 ;
+    END
+  END rw0_wd_in[5]
+  PIN rw0_wd_in[6]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M2 ;
+      RECT 0.000 6.474 0.036 6.486 ;
+    END
+  END rw0_wd_in[6]
+  PIN rw0_wd_in[7]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M2 ;
+      RECT 0.000 7.530 0.036 7.542 ;
+    END
+  END rw0_wd_in[7]
+  PIN rw0_wd_in[8]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M2 ;
+      RECT 0.000 8.586 0.036 8.598 ;
+    END
+  END rw0_wd_in[8]
+  PIN rw0_wd_in[9]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M2 ;
+      RECT 0.000 9.642 0.036 9.654 ;
+    END
+  END rw0_wd_in[9]
+  PIN rw0_wd_in[10]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M2 ;
+      RECT 0.000 10.698 0.036 10.710 ;
+    END
+  END rw0_wd_in[10]
+  PIN rw0_wd_in[11]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M2 ;
+      RECT 0.000 11.754 0.036 11.766 ;
+    END
+  END rw0_wd_in[11]
+  PIN rw0_wd_in[12]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M2 ;
+      RECT 0.000 12.810 0.036 12.822 ;
+    END
+  END rw0_wd_in[12]
+  PIN rw0_wd_in[13]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M2 ;
+      RECT 0.000 13.866 0.036 13.878 ;
+    END
+  END rw0_wd_in[13]
+  PIN rw0_wd_in[14]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M2 ;
+      RECT 0.000 14.922 0.036 14.934 ;
+    END
+  END rw0_wd_in[14]
+  PIN rw0_wd_in[15]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M2 ;
+      RECT 0.000 15.978 0.036 15.990 ;
+    END
+  END rw0_wd_in[15]
+  PIN rw0_wd_in[16]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M2 ;
+      RECT 0.000 17.034 0.036 17.046 ;
+    END
+  END rw0_wd_in[16]
+  PIN rw0_wd_in[17]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M2 ;
+      RECT 0.000 18.090 0.036 18.102 ;
+    END
+  END rw0_wd_in[17]
+  PIN rw0_wd_in[18]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M2 ;
+      RECT 0.000 19.146 0.036 19.158 ;
+    END
+  END rw0_wd_in[18]
+  PIN rw0_wd_in[19]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M2 ;
+      RECT 0.000 20.202 0.036 20.214 ;
+    END
+  END rw0_wd_in[19]
+  PIN rw0_wd_in[20]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M2 ;
+      RECT 0.000 21.258 0.036 21.270 ;
+    END
+  END rw0_wd_in[20]
+  PIN rw0_wd_in[21]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M2 ;
+      RECT 0.000 22.314 0.036 22.326 ;
+    END
+  END rw0_wd_in[21]
+  PIN rw0_wd_in[22]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M2 ;
+      RECT 0.000 23.370 0.036 23.382 ;
+    END
+  END rw0_wd_in[22]
+  PIN rw0_wd_in[23]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M2 ;
+      RECT 0.000 24.426 0.036 24.438 ;
+    END
+  END rw0_wd_in[23]
+  PIN rw0_wd_in[24]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M2 ;
+      RECT 0.000 25.482 0.036 25.494 ;
+    END
+  END rw0_wd_in[24]
+  PIN rw0_wd_in[25]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M2 ;
+      RECT 0.000 26.538 0.036 26.550 ;
+    END
+  END rw0_wd_in[25]
+  PIN rw0_wd_in[26]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M2 ;
+      RECT 0.000 27.594 0.036 27.606 ;
+    END
+  END rw0_wd_in[26]
+  PIN rw0_wd_in[27]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M2 ;
+      RECT 0.000 28.650 0.036 28.662 ;
+    END
+  END rw0_wd_in[27]
+  PIN rw0_wd_in[28]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M2 ;
+      RECT 0.000 29.706 0.036 29.718 ;
+    END
+  END rw0_wd_in[28]
+  PIN rw0_wd_in[29]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M2 ;
+      RECT 0.000 30.762 0.036 30.774 ;
+    END
+  END rw0_wd_in[29]
+  PIN rw0_wd_in[30]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M2 ;
+      RECT 0.000 31.818 0.036 31.830 ;
+    END
+  END rw0_wd_in[30]
+  PIN rw0_wd_in[31]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M2 ;
+      RECT 0.000 32.874 0.036 32.886 ;
+    END
+  END rw0_wd_in[31]
+  PIN rw0_wd_in[32]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M2 ;
+      RECT 0.000 33.930 0.036 33.942 ;
+    END
+  END rw0_wd_in[32]
+  PIN rw0_wd_in[33]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M2 ;
+      RECT 0.000 34.986 0.036 34.998 ;
+    END
+  END rw0_wd_in[33]
+  PIN rw0_wd_in[34]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M2 ;
+      RECT 0.000 36.042 0.036 36.054 ;
+    END
+  END rw0_wd_in[34]
+  PIN rw0_wd_in[35]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M2 ;
+      RECT 0.000 37.098 0.036 37.110 ;
+    END
+  END rw0_wd_in[35]
+  PIN rw0_wd_in[36]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M2 ;
+      RECT 0.000 38.154 0.036 38.166 ;
+    END
+  END rw0_wd_in[36]
+  PIN rw0_wd_in[37]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M2 ;
+      RECT 0.000 39.210 0.036 39.222 ;
+    END
+  END rw0_wd_in[37]
+  PIN rw0_wd_in[38]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M2 ;
+      RECT 0.000 40.266 0.036 40.278 ;
+    END
+  END rw0_wd_in[38]
+  PIN rw0_wd_in[39]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M2 ;
+      RECT 0.000 41.322 0.036 41.334 ;
+    END
+  END rw0_wd_in[39]
+  PIN rw0_wd_in[40]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M2 ;
+      RECT 0.000 42.378 0.036 42.390 ;
+    END
+  END rw0_wd_in[40]
+  PIN rw0_wd_in[41]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M2 ;
+      RECT 0.000 43.434 0.036 43.446 ;
+    END
+  END rw0_wd_in[41]
+  PIN rw0_wd_in[42]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M2 ;
+      RECT 0.000 44.490 0.036 44.502 ;
+    END
+  END rw0_wd_in[42]
+  PIN rw0_wd_in[43]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M2 ;
+      RECT 0.000 45.546 0.036 45.558 ;
+    END
+  END rw0_wd_in[43]
+  PIN rw0_wd_in[44]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M2 ;
+      RECT 0.000 46.602 0.036 46.614 ;
+    END
+  END rw0_wd_in[44]
+  PIN rw0_wd_in[45]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M2 ;
+      RECT 0.000 47.658 0.036 47.670 ;
+    END
+  END rw0_wd_in[45]
+  PIN rw0_wd_in[46]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M2 ;
+      RECT 0.000 48.714 0.036 48.726 ;
+    END
+  END rw0_wd_in[46]
+  PIN rw0_wd_in[47]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M2 ;
+      RECT 0.000 49.770 0.036 49.782 ;
+    END
+  END rw0_wd_in[47]
+  PIN rw0_wd_in[48]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M2 ;
+      RECT 0.000 50.826 0.036 50.838 ;
+    END
+  END rw0_wd_in[48]
+  PIN rw0_wd_in[49]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M2 ;
+      RECT 0.000 51.882 0.036 51.894 ;
+    END
+  END rw0_wd_in[49]
+  PIN rw0_wd_in[50]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M2 ;
+      RECT 0.000 52.938 0.036 52.950 ;
+    END
+  END rw0_wd_in[50]
+  PIN rw0_wd_in[51]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M2 ;
+      RECT 0.000 53.994 0.036 54.006 ;
+    END
+  END rw0_wd_in[51]
+  PIN rw0_wd_in[52]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M2 ;
+      RECT 0.000 55.050 0.036 55.062 ;
+    END
+  END rw0_wd_in[52]
+  PIN rw0_wd_in[53]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M2 ;
+      RECT 0.000 56.106 0.036 56.118 ;
+    END
+  END rw0_wd_in[53]
+  PIN rw0_wd_in[54]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M2 ;
+      RECT 0.000 57.162 0.036 57.174 ;
+    END
+  END rw0_wd_in[54]
+  PIN rw0_wd_in[55]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M2 ;
+      RECT 0.000 58.218 0.036 58.230 ;
+    END
+  END rw0_wd_in[55]
+  PIN rw0_wd_in[56]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M2 ;
+      RECT 0.000 59.274 0.036 59.286 ;
+    END
+  END rw0_wd_in[56]
+  PIN rw0_wd_in[57]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M2 ;
+      RECT 0.000 60.330 0.036 60.342 ;
+    END
+  END rw0_wd_in[57]
+  PIN rw0_wd_in[58]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M2 ;
+      RECT 0.000 61.386 0.036 61.398 ;
+    END
+  END rw0_wd_in[58]
+  PIN rw0_wd_in[59]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M2 ;
+      RECT 0.000 62.442 0.036 62.454 ;
+    END
+  END rw0_wd_in[59]
+  PIN rw0_wd_in[60]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M2 ;
+      RECT 0.000 63.498 0.036 63.510 ;
+    END
+  END rw0_wd_in[60]
+  PIN rw0_wd_in[61]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M2 ;
+      RECT 0.000 64.554 0.036 64.566 ;
+    END
+  END rw0_wd_in[61]
+  PIN rw0_wd_in[62]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M2 ;
+      RECT 0.000 65.610 0.036 65.622 ;
+    END
+  END rw0_wd_in[62]
+  PIN rw0_wd_in[63]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M2 ;
+      RECT 0.000 66.666 0.036 66.678 ;
+    END
+  END rw0_wd_in[63]
+  PIN rw0_wd_in[64]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M2 ;
+      RECT 117.354 0.138 117.390 0.150 ;
+    END
+  END rw0_wd_in[64]
+  PIN rw0_wd_in[65]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M2 ;
+      RECT 117.354 1.194 117.390 1.206 ;
+    END
+  END rw0_wd_in[65]
+  PIN rw0_wd_in[66]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M2 ;
+      RECT 117.354 2.250 117.390 2.262 ;
+    END
+  END rw0_wd_in[66]
+  PIN rw0_wd_in[67]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M2 ;
+      RECT 117.354 3.306 117.390 3.318 ;
+    END
+  END rw0_wd_in[67]
+  PIN rw0_wd_in[68]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M2 ;
+      RECT 117.354 4.362 117.390 4.374 ;
+    END
+  END rw0_wd_in[68]
+  PIN rw0_wd_in[69]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M2 ;
+      RECT 117.354 5.418 117.390 5.430 ;
+    END
+  END rw0_wd_in[69]
+  PIN rw0_wd_in[70]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M2 ;
+      RECT 117.354 6.474 117.390 6.486 ;
+    END
+  END rw0_wd_in[70]
+  PIN rw0_wd_in[71]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M2 ;
+      RECT 117.354 7.530 117.390 7.542 ;
+    END
+  END rw0_wd_in[71]
+  PIN rw0_wd_in[72]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M2 ;
+      RECT 117.354 8.586 117.390 8.598 ;
+    END
+  END rw0_wd_in[72]
+  PIN rw0_wd_in[73]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M2 ;
+      RECT 117.354 9.642 117.390 9.654 ;
+    END
+  END rw0_wd_in[73]
+  PIN rw0_wd_in[74]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M2 ;
+      RECT 117.354 10.698 117.390 10.710 ;
+    END
+  END rw0_wd_in[74]
+  PIN rw0_wd_in[75]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M2 ;
+      RECT 117.354 11.754 117.390 11.766 ;
+    END
+  END rw0_wd_in[75]
+  PIN rw0_wd_in[76]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M2 ;
+      RECT 117.354 12.810 117.390 12.822 ;
+    END
+  END rw0_wd_in[76]
+  PIN rw0_wd_in[77]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M2 ;
+      RECT 117.354 13.866 117.390 13.878 ;
+    END
+  END rw0_wd_in[77]
+  PIN rw0_wd_in[78]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M2 ;
+      RECT 117.354 14.922 117.390 14.934 ;
+    END
+  END rw0_wd_in[78]
+  PIN rw0_wd_in[79]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M2 ;
+      RECT 117.354 15.978 117.390 15.990 ;
+    END
+  END rw0_wd_in[79]
+  PIN rw0_wd_in[80]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M2 ;
+      RECT 117.354 17.034 117.390 17.046 ;
+    END
+  END rw0_wd_in[80]
+  PIN rw0_wd_in[81]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M2 ;
+      RECT 117.354 18.090 117.390 18.102 ;
+    END
+  END rw0_wd_in[81]
+  PIN rw0_wd_in[82]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M2 ;
+      RECT 117.354 19.146 117.390 19.158 ;
+    END
+  END rw0_wd_in[82]
+  PIN rw0_wd_in[83]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M2 ;
+      RECT 117.354 20.202 117.390 20.214 ;
+    END
+  END rw0_wd_in[83]
+  PIN rw0_wd_in[84]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M2 ;
+      RECT 117.354 21.258 117.390 21.270 ;
+    END
+  END rw0_wd_in[84]
+  PIN rw0_wd_in[85]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M2 ;
+      RECT 117.354 22.314 117.390 22.326 ;
+    END
+  END rw0_wd_in[85]
+  PIN rw0_wd_in[86]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M2 ;
+      RECT 117.354 23.370 117.390 23.382 ;
+    END
+  END rw0_wd_in[86]
+  PIN rw0_wd_in[87]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M2 ;
+      RECT 117.354 24.426 117.390 24.438 ;
+    END
+  END rw0_wd_in[87]
+  PIN rw0_wd_in[88]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M2 ;
+      RECT 117.354 25.482 117.390 25.494 ;
+    END
+  END rw0_wd_in[88]
+  PIN rw0_wd_in[89]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M2 ;
+      RECT 117.354 26.538 117.390 26.550 ;
+    END
+  END rw0_wd_in[89]
+  PIN rw0_wd_in[90]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M2 ;
+      RECT 117.354 27.594 117.390 27.606 ;
+    END
+  END rw0_wd_in[90]
+  PIN rw0_wd_in[91]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M2 ;
+      RECT 117.354 28.650 117.390 28.662 ;
+    END
+  END rw0_wd_in[91]
+  PIN rw0_wd_in[92]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M2 ;
+      RECT 117.354 29.706 117.390 29.718 ;
+    END
+  END rw0_wd_in[92]
+  PIN rw0_wd_in[93]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M2 ;
+      RECT 117.354 30.762 117.390 30.774 ;
+    END
+  END rw0_wd_in[93]
+  PIN rw0_wd_in[94]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M2 ;
+      RECT 117.354 31.818 117.390 31.830 ;
+    END
+  END rw0_wd_in[94]
+  PIN rw0_wd_in[95]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M2 ;
+      RECT 117.354 32.874 117.390 32.886 ;
+    END
+  END rw0_wd_in[95]
+  PIN rw0_wd_in[96]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M2 ;
+      RECT 117.354 33.930 117.390 33.942 ;
+    END
+  END rw0_wd_in[96]
+  PIN rw0_wd_in[97]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M2 ;
+      RECT 117.354 34.986 117.390 34.998 ;
+    END
+  END rw0_wd_in[97]
+  PIN rw0_wd_in[98]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M2 ;
+      RECT 117.354 36.042 117.390 36.054 ;
+    END
+  END rw0_wd_in[98]
+  PIN rw0_wd_in[99]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M2 ;
+      RECT 117.354 37.098 117.390 37.110 ;
+    END
+  END rw0_wd_in[99]
+  PIN rw0_wd_in[100]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M2 ;
+      RECT 117.354 38.154 117.390 38.166 ;
+    END
+  END rw0_wd_in[100]
+  PIN rw0_wd_in[101]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M2 ;
+      RECT 117.354 39.210 117.390 39.222 ;
+    END
+  END rw0_wd_in[101]
+  PIN rw0_wd_in[102]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M2 ;
+      RECT 117.354 40.266 117.390 40.278 ;
+    END
+  END rw0_wd_in[102]
+  PIN rw0_wd_in[103]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M2 ;
+      RECT 117.354 41.322 117.390 41.334 ;
+    END
+  END rw0_wd_in[103]
+  PIN rw0_wd_in[104]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M2 ;
+      RECT 117.354 42.378 117.390 42.390 ;
+    END
+  END rw0_wd_in[104]
+  PIN rw0_wd_in[105]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M2 ;
+      RECT 117.354 43.434 117.390 43.446 ;
+    END
+  END rw0_wd_in[105]
+  PIN rw0_wd_in[106]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M2 ;
+      RECT 117.354 44.490 117.390 44.502 ;
+    END
+  END rw0_wd_in[106]
+  PIN rw0_wd_in[107]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M2 ;
+      RECT 117.354 45.546 117.390 45.558 ;
+    END
+  END rw0_wd_in[107]
+  PIN rw0_wd_in[108]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M2 ;
+      RECT 117.354 46.602 117.390 46.614 ;
+    END
+  END rw0_wd_in[108]
+  PIN rw0_wd_in[109]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M2 ;
+      RECT 117.354 47.658 117.390 47.670 ;
+    END
+  END rw0_wd_in[109]
+  PIN rw0_wd_in[110]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M2 ;
+      RECT 117.354 48.714 117.390 48.726 ;
+    END
+  END rw0_wd_in[110]
+  PIN rw0_wd_in[111]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M2 ;
+      RECT 117.354 49.770 117.390 49.782 ;
+    END
+  END rw0_wd_in[111]
+  PIN rw0_wd_in[112]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M2 ;
+      RECT 117.354 50.826 117.390 50.838 ;
+    END
+  END rw0_wd_in[112]
+  PIN rw0_wd_in[113]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M2 ;
+      RECT 117.354 51.882 117.390 51.894 ;
+    END
+  END rw0_wd_in[113]
+  PIN rw0_wd_in[114]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M2 ;
+      RECT 117.354 52.938 117.390 52.950 ;
+    END
+  END rw0_wd_in[114]
+  PIN rw0_wd_in[115]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M2 ;
+      RECT 117.354 53.994 117.390 54.006 ;
+    END
+  END rw0_wd_in[115]
+  PIN rw0_wd_in[116]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M2 ;
+      RECT 117.354 55.050 117.390 55.062 ;
+    END
+  END rw0_wd_in[116]
+  PIN rw0_wd_in[117]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M2 ;
+      RECT 117.354 56.106 117.390 56.118 ;
+    END
+  END rw0_wd_in[117]
+  PIN rw0_wd_in[118]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M2 ;
+      RECT 117.354 57.162 117.390 57.174 ;
+    END
+  END rw0_wd_in[118]
+  PIN rw0_wd_in[119]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M2 ;
+      RECT 117.354 58.218 117.390 58.230 ;
+    END
+  END rw0_wd_in[119]
+  PIN rw0_wd_in[120]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M2 ;
+      RECT 117.354 59.274 117.390 59.286 ;
+    END
+  END rw0_wd_in[120]
+  PIN rw0_wd_in[121]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M2 ;
+      RECT 117.354 60.330 117.390 60.342 ;
+    END
+  END rw0_wd_in[121]
+  PIN rw0_wd_in[122]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M2 ;
+      RECT 117.354 61.386 117.390 61.398 ;
+    END
+  END rw0_wd_in[122]
+  PIN rw0_wd_in[123]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M2 ;
+      RECT 117.354 62.442 117.390 62.454 ;
+    END
+  END rw0_wd_in[123]
+  PIN rw0_wd_in[124]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M2 ;
+      RECT 117.354 63.498 117.390 63.510 ;
+    END
+  END rw0_wd_in[124]
+  PIN rw0_wd_in[125]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M2 ;
+      RECT 117.354 64.554 117.390 64.566 ;
+    END
+  END rw0_wd_in[125]
+  PIN rw0_wd_in[126]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M2 ;
+      RECT 117.354 65.610 117.390 65.622 ;
+    END
+  END rw0_wd_in[126]
+  PIN rw0_wd_in[127]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M2 ;
+      RECT 117.354 66.666 117.390 66.678 ;
+    END
+  END rw0_wd_in[127]
+  PIN rw0_wd_in[128]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 0.161 0.000 0.175 0.042 ;
+    END
+  END rw0_wd_in[128]
+  PIN rw0_wd_in[129]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 0.609 0.000 0.623 0.042 ;
+    END
+  END rw0_wd_in[129]
+  PIN rw0_wd_in[130]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 1.057 0.000 1.071 0.042 ;
+    END
+  END rw0_wd_in[130]
+  PIN rw0_wd_in[131]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 1.505 0.000 1.519 0.042 ;
+    END
+  END rw0_wd_in[131]
+  PIN rw0_wd_in[132]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 1.953 0.000 1.967 0.042 ;
+    END
+  END rw0_wd_in[132]
+  PIN rw0_wd_in[133]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 2.401 0.000 2.415 0.042 ;
+    END
+  END rw0_wd_in[133]
+  PIN rw0_wd_in[134]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 2.849 0.000 2.863 0.042 ;
+    END
+  END rw0_wd_in[134]
+  PIN rw0_wd_in[135]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 3.297 0.000 3.311 0.042 ;
+    END
+  END rw0_wd_in[135]
+  PIN rw0_wd_in[136]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 3.745 0.000 3.759 0.042 ;
+    END
+  END rw0_wd_in[136]
+  PIN rw0_wd_in[137]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 4.193 0.000 4.207 0.042 ;
+    END
+  END rw0_wd_in[137]
+  PIN rw0_wd_in[138]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 4.641 0.000 4.655 0.042 ;
+    END
+  END rw0_wd_in[138]
+  PIN rw0_wd_in[139]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 5.089 0.000 5.103 0.042 ;
+    END
+  END rw0_wd_in[139]
+  PIN rw0_wd_in[140]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 5.537 0.000 5.551 0.042 ;
+    END
+  END rw0_wd_in[140]
+  PIN rw0_wd_in[141]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 5.985 0.000 5.999 0.042 ;
+    END
+  END rw0_wd_in[141]
+  PIN rw0_wd_in[142]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 6.433 0.000 6.447 0.042 ;
+    END
+  END rw0_wd_in[142]
+  PIN rw0_wd_in[143]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 6.881 0.000 6.895 0.042 ;
+    END
+  END rw0_wd_in[143]
+  PIN rw0_wd_in[144]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 7.329 0.000 7.343 0.042 ;
+    END
+  END rw0_wd_in[144]
+  PIN rw0_wd_in[145]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 7.777 0.000 7.791 0.042 ;
+    END
+  END rw0_wd_in[145]
+  PIN rw0_wd_in[146]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 8.225 0.000 8.239 0.042 ;
+    END
+  END rw0_wd_in[146]
+  PIN rw0_wd_in[147]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 8.673 0.000 8.687 0.042 ;
+    END
+  END rw0_wd_in[147]
+  PIN rw0_wd_in[148]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 9.121 0.000 9.135 0.042 ;
+    END
+  END rw0_wd_in[148]
+  PIN rw0_wd_in[149]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 9.569 0.000 9.583 0.042 ;
+    END
+  END rw0_wd_in[149]
+  PIN rw0_wd_in[150]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 10.017 0.000 10.031 0.042 ;
+    END
+  END rw0_wd_in[150]
+  PIN rw0_wd_in[151]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 10.465 0.000 10.479 0.042 ;
+    END
+  END rw0_wd_in[151]
+  PIN rw0_wd_in[152]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 10.913 0.000 10.927 0.042 ;
+    END
+  END rw0_wd_in[152]
+  PIN rw0_wd_in[153]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 11.361 0.000 11.375 0.042 ;
+    END
+  END rw0_wd_in[153]
+  PIN rw0_wd_in[154]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 11.809 0.000 11.823 0.042 ;
+    END
+  END rw0_wd_in[154]
+  PIN rw0_wd_in[155]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 12.257 0.000 12.271 0.042 ;
+    END
+  END rw0_wd_in[155]
+  PIN rw0_wd_in[156]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 12.705 0.000 12.719 0.042 ;
+    END
+  END rw0_wd_in[156]
+  PIN rw0_wd_in[157]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 13.153 0.000 13.167 0.042 ;
+    END
+  END rw0_wd_in[157]
+  PIN rw0_wd_in[158]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 13.601 0.000 13.615 0.042 ;
+    END
+  END rw0_wd_in[158]
+  PIN rw0_wd_in[159]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 14.049 0.000 14.063 0.042 ;
+    END
+  END rw0_wd_in[159]
+  PIN rw0_wd_in[160]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 14.497 0.000 14.511 0.042 ;
+    END
+  END rw0_wd_in[160]
+  PIN rw0_wd_in[161]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 14.945 0.000 14.959 0.042 ;
+    END
+  END rw0_wd_in[161]
+  PIN rw0_wd_in[162]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 15.393 0.000 15.407 0.042 ;
+    END
+  END rw0_wd_in[162]
+  PIN rw0_wd_in[163]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 15.841 0.000 15.855 0.042 ;
+    END
+  END rw0_wd_in[163]
+  PIN rw0_wd_in[164]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 16.289 0.000 16.303 0.042 ;
+    END
+  END rw0_wd_in[164]
+  PIN rw0_wd_in[165]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 16.737 0.000 16.751 0.042 ;
+    END
+  END rw0_wd_in[165]
+  PIN rw0_wd_in[166]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 17.185 0.000 17.199 0.042 ;
+    END
+  END rw0_wd_in[166]
+  PIN rw0_wd_in[167]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 17.633 0.000 17.647 0.042 ;
+    END
+  END rw0_wd_in[167]
+  PIN rw0_wd_in[168]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 18.081 0.000 18.095 0.042 ;
+    END
+  END rw0_wd_in[168]
+  PIN rw0_wd_in[169]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 18.529 0.000 18.543 0.042 ;
+    END
+  END rw0_wd_in[169]
+  PIN rw0_wd_in[170]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 18.977 0.000 18.991 0.042 ;
+    END
+  END rw0_wd_in[170]
+  PIN rw0_wd_in[171]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 19.425 0.000 19.439 0.042 ;
+    END
+  END rw0_wd_in[171]
+  PIN rw0_wd_in[172]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 19.873 0.000 19.887 0.042 ;
+    END
+  END rw0_wd_in[172]
+  PIN rw0_wd_in[173]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 20.321 0.000 20.335 0.042 ;
+    END
+  END rw0_wd_in[173]
+  PIN rw0_wd_in[174]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 20.769 0.000 20.783 0.042 ;
+    END
+  END rw0_wd_in[174]
+  PIN rw0_wd_in[175]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 21.217 0.000 21.231 0.042 ;
+    END
+  END rw0_wd_in[175]
+  PIN rw0_wd_in[176]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 21.665 0.000 21.679 0.042 ;
+    END
+  END rw0_wd_in[176]
+  PIN rw0_wd_in[177]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 22.113 0.000 22.127 0.042 ;
+    END
+  END rw0_wd_in[177]
+  PIN rw0_wd_in[178]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 22.561 0.000 22.575 0.042 ;
+    END
+  END rw0_wd_in[178]
+  PIN rw0_wd_in[179]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 23.009 0.000 23.023 0.042 ;
+    END
+  END rw0_wd_in[179]
+  PIN rw0_wd_in[180]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 23.457 0.000 23.471 0.042 ;
+    END
+  END rw0_wd_in[180]
+  PIN rw0_wd_in[181]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 23.905 0.000 23.919 0.042 ;
+    END
+  END rw0_wd_in[181]
+  PIN rw0_wd_in[182]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 24.353 0.000 24.367 0.042 ;
+    END
+  END rw0_wd_in[182]
+  PIN rw0_wd_in[183]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 24.801 0.000 24.815 0.042 ;
+    END
+  END rw0_wd_in[183]
+  PIN rw0_wd_in[184]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 25.249 0.000 25.263 0.042 ;
+    END
+  END rw0_wd_in[184]
+  PIN rw0_wd_in[185]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 25.697 0.000 25.711 0.042 ;
+    END
+  END rw0_wd_in[185]
+  PIN rw0_wd_in[186]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 26.145 0.000 26.159 0.042 ;
+    END
+  END rw0_wd_in[186]
+  PIN rw0_wd_in[187]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 26.593 0.000 26.607 0.042 ;
+    END
+  END rw0_wd_in[187]
+  PIN rw0_wd_in[188]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 27.041 0.000 27.055 0.042 ;
+    END
+  END rw0_wd_in[188]
+  PIN rw0_wd_in[189]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 27.489 0.000 27.503 0.042 ;
+    END
+  END rw0_wd_in[189]
+  PIN rw0_wd_in[190]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 27.937 0.000 27.951 0.042 ;
+    END
+  END rw0_wd_in[190]
+  PIN rw0_wd_in[191]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 28.385 0.000 28.399 0.042 ;
+    END
+  END rw0_wd_in[191]
+  PIN rw0_wd_in[192]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 28.833 0.000 28.847 0.042 ;
+    END
+  END rw0_wd_in[192]
+  PIN rw0_wd_in[193]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 29.281 0.000 29.295 0.042 ;
+    END
+  END rw0_wd_in[193]
+  PIN rw0_wd_in[194]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 29.729 0.000 29.743 0.042 ;
+    END
+  END rw0_wd_in[194]
+  PIN rw0_wd_in[195]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 30.177 0.000 30.191 0.042 ;
+    END
+  END rw0_wd_in[195]
+  PIN rw0_wd_in[196]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 30.625 0.000 30.639 0.042 ;
+    END
+  END rw0_wd_in[196]
+  PIN rw0_wd_in[197]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 31.073 0.000 31.087 0.042 ;
+    END
+  END rw0_wd_in[197]
+  PIN rw0_wd_in[198]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 31.521 0.000 31.535 0.042 ;
+    END
+  END rw0_wd_in[198]
+  PIN rw0_wd_in[199]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 31.969 0.000 31.983 0.042 ;
+    END
+  END rw0_wd_in[199]
+  PIN rw0_wd_in[200]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 32.417 0.000 32.431 0.042 ;
+    END
+  END rw0_wd_in[200]
+  PIN rw0_wd_in[201]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 32.865 0.000 32.879 0.042 ;
+    END
+  END rw0_wd_in[201]
+  PIN rw0_wd_in[202]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 33.313 0.000 33.327 0.042 ;
+    END
+  END rw0_wd_in[202]
+  PIN rw0_wd_in[203]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 33.761 0.000 33.775 0.042 ;
+    END
+  END rw0_wd_in[203]
+  PIN rw0_wd_in[204]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 34.209 0.000 34.223 0.042 ;
+    END
+  END rw0_wd_in[204]
+  PIN rw0_wd_in[205]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 34.657 0.000 34.671 0.042 ;
+    END
+  END rw0_wd_in[205]
+  PIN rw0_wd_in[206]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 35.105 0.000 35.119 0.042 ;
+    END
+  END rw0_wd_in[206]
+  PIN rw0_wd_in[207]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 35.553 0.000 35.567 0.042 ;
+    END
+  END rw0_wd_in[207]
+  PIN rw0_wd_in[208]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 36.001 0.000 36.015 0.042 ;
+    END
+  END rw0_wd_in[208]
+  PIN rw0_wd_in[209]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 36.449 0.000 36.463 0.042 ;
+    END
+  END rw0_wd_in[209]
+  PIN rw0_wd_in[210]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 36.897 0.000 36.911 0.042 ;
+    END
+  END rw0_wd_in[210]
+  PIN rw0_wd_in[211]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 37.345 0.000 37.359 0.042 ;
+    END
+  END rw0_wd_in[211]
+  PIN rw0_wd_in[212]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 37.793 0.000 37.807 0.042 ;
+    END
+  END rw0_wd_in[212]
+  PIN rw0_wd_in[213]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 38.241 0.000 38.255 0.042 ;
+    END
+  END rw0_wd_in[213]
+  PIN rw0_wd_in[214]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 38.689 0.000 38.703 0.042 ;
+    END
+  END rw0_wd_in[214]
+  PIN rw0_wd_in[215]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 39.137 0.000 39.151 0.042 ;
+    END
+  END rw0_wd_in[215]
+  PIN rw0_wd_in[216]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 39.585 0.000 39.599 0.042 ;
+    END
+  END rw0_wd_in[216]
+  PIN rw0_wd_in[217]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 40.033 0.000 40.047 0.042 ;
+    END
+  END rw0_wd_in[217]
+  PIN rw0_wd_in[218]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 40.481 0.000 40.495 0.042 ;
+    END
+  END rw0_wd_in[218]
+  PIN rw0_wd_in[219]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 40.929 0.000 40.943 0.042 ;
+    END
+  END rw0_wd_in[219]
+  PIN rw0_wd_in[220]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 41.377 0.000 41.391 0.042 ;
+    END
+  END rw0_wd_in[220]
+  PIN rw0_wd_in[221]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 41.825 0.000 41.839 0.042 ;
+    END
+  END rw0_wd_in[221]
+  PIN rw0_wd_in[222]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 42.273 0.000 42.287 0.042 ;
+    END
+  END rw0_wd_in[222]
+  PIN rw0_wd_in[223]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 42.721 0.000 42.735 0.042 ;
+    END
+  END rw0_wd_in[223]
+  PIN rw0_wd_in[224]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 43.169 0.000 43.183 0.042 ;
+    END
+  END rw0_wd_in[224]
+  PIN rw0_wd_in[225]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 43.617 0.000 43.631 0.042 ;
+    END
+  END rw0_wd_in[225]
+  PIN rw0_wd_in[226]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 44.065 0.000 44.079 0.042 ;
+    END
+  END rw0_wd_in[226]
+  PIN rw0_wd_in[227]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 44.513 0.000 44.527 0.042 ;
+    END
+  END rw0_wd_in[227]
+  PIN rw0_wd_in[228]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 44.961 0.000 44.975 0.042 ;
+    END
+  END rw0_wd_in[228]
+  PIN rw0_wd_in[229]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 45.409 0.000 45.423 0.042 ;
+    END
+  END rw0_wd_in[229]
+  PIN rw0_wd_in[230]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 45.857 0.000 45.871 0.042 ;
+    END
+  END rw0_wd_in[230]
+  PIN rw0_wd_in[231]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 46.305 0.000 46.319 0.042 ;
+    END
+  END rw0_wd_in[231]
+  PIN rw0_wd_in[232]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 46.753 0.000 46.767 0.042 ;
+    END
+  END rw0_wd_in[232]
+  PIN rw0_wd_in[233]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 47.201 0.000 47.215 0.042 ;
+    END
+  END rw0_wd_in[233]
+  PIN rw0_wd_in[234]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 47.649 0.000 47.663 0.042 ;
+    END
+  END rw0_wd_in[234]
+  PIN rw0_wd_in[235]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 48.097 0.000 48.111 0.042 ;
+    END
+  END rw0_wd_in[235]
+  PIN rw0_wd_in[236]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 48.545 0.000 48.559 0.042 ;
+    END
+  END rw0_wd_in[236]
+  PIN rw0_wd_in[237]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 48.993 0.000 49.007 0.042 ;
+    END
+  END rw0_wd_in[237]
+  PIN rw0_wd_in[238]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 49.441 0.000 49.455 0.042 ;
+    END
+  END rw0_wd_in[238]
+  PIN rw0_wd_in[239]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 49.889 0.000 49.903 0.042 ;
+    END
+  END rw0_wd_in[239]
+  PIN rw0_wd_in[240]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 50.337 0.000 50.351 0.042 ;
+    END
+  END rw0_wd_in[240]
+  PIN rw0_wd_in[241]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 50.785 0.000 50.799 0.042 ;
+    END
+  END rw0_wd_in[241]
+  PIN rw0_wd_in[242]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 51.233 0.000 51.247 0.042 ;
+    END
+  END rw0_wd_in[242]
+  PIN rw0_wd_in[243]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 51.681 0.000 51.695 0.042 ;
+    END
+  END rw0_wd_in[243]
+  PIN rw0_wd_in[244]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 52.129 0.000 52.143 0.042 ;
+    END
+  END rw0_wd_in[244]
+  PIN rw0_wd_in[245]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 52.577 0.000 52.591 0.042 ;
+    END
+  END rw0_wd_in[245]
+  PIN rw0_wd_in[246]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 53.025 0.000 53.039 0.042 ;
+    END
+  END rw0_wd_in[246]
+  PIN rw0_wd_in[247]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 53.473 0.000 53.487 0.042 ;
+    END
+  END rw0_wd_in[247]
+  PIN rw0_wd_in[248]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 53.921 0.000 53.935 0.042 ;
+    END
+  END rw0_wd_in[248]
+  PIN rw0_wd_in[249]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 54.369 0.000 54.383 0.042 ;
+    END
+  END rw0_wd_in[249]
+  PIN rw0_wd_in[250]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 54.817 0.000 54.831 0.042 ;
+    END
+  END rw0_wd_in[250]
+  PIN rw0_wd_in[251]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 55.265 0.000 55.279 0.042 ;
+    END
+  END rw0_wd_in[251]
+  PIN rw0_wd_in[252]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 55.713 0.000 55.727 0.042 ;
+    END
+  END rw0_wd_in[252]
+  PIN rw0_wd_in[253]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 56.161 0.000 56.175 0.042 ;
+    END
+  END rw0_wd_in[253]
+  PIN rw0_wd_in[254]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 56.609 0.000 56.623 0.042 ;
+    END
+  END rw0_wd_in[254]
+  PIN rw0_wd_in[255]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 57.057 0.000 57.071 0.042 ;
+    END
+  END rw0_wd_in[255]
+  PIN rw0_rd_out[0]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 57.505 0.000 57.519 0.042 ;
+    END
+  END rw0_rd_out[0]
+  PIN rw0_rd_out[1]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 57.953 0.000 57.967 0.042 ;
+    END
+  END rw0_rd_out[1]
+  PIN rw0_rd_out[2]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 58.401 0.000 58.415 0.042 ;
+    END
+  END rw0_rd_out[2]
+  PIN rw0_rd_out[3]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 58.849 0.000 58.863 0.042 ;
+    END
+  END rw0_rd_out[3]
+  PIN rw0_rd_out[4]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 59.297 0.000 59.311 0.042 ;
+    END
+  END rw0_rd_out[4]
+  PIN rw0_rd_out[5]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 59.745 0.000 59.759 0.042 ;
+    END
+  END rw0_rd_out[5]
+  PIN rw0_rd_out[6]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 60.193 0.000 60.207 0.042 ;
+    END
+  END rw0_rd_out[6]
+  PIN rw0_rd_out[7]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 60.641 0.000 60.655 0.042 ;
+    END
+  END rw0_rd_out[7]
+  PIN rw0_rd_out[8]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 61.089 0.000 61.103 0.042 ;
+    END
+  END rw0_rd_out[8]
+  PIN rw0_rd_out[9]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 61.537 0.000 61.551 0.042 ;
+    END
+  END rw0_rd_out[9]
+  PIN rw0_rd_out[10]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 61.985 0.000 61.999 0.042 ;
+    END
+  END rw0_rd_out[10]
+  PIN rw0_rd_out[11]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 62.433 0.000 62.447 0.042 ;
+    END
+  END rw0_rd_out[11]
+  PIN rw0_rd_out[12]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 62.881 0.000 62.895 0.042 ;
+    END
+  END rw0_rd_out[12]
+  PIN rw0_rd_out[13]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 63.329 0.000 63.343 0.042 ;
+    END
+  END rw0_rd_out[13]
+  PIN rw0_rd_out[14]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 63.777 0.000 63.791 0.042 ;
+    END
+  END rw0_rd_out[14]
+  PIN rw0_rd_out[15]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 64.225 0.000 64.239 0.042 ;
+    END
+  END rw0_rd_out[15]
+  PIN rw0_rd_out[16]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 64.673 0.000 64.687 0.042 ;
+    END
+  END rw0_rd_out[16]
+  PIN rw0_rd_out[17]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 65.121 0.000 65.135 0.042 ;
+    END
+  END rw0_rd_out[17]
+  PIN rw0_rd_out[18]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 65.569 0.000 65.583 0.042 ;
+    END
+  END rw0_rd_out[18]
+  PIN rw0_rd_out[19]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 66.017 0.000 66.031 0.042 ;
+    END
+  END rw0_rd_out[19]
+  PIN rw0_rd_out[20]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 66.465 0.000 66.479 0.042 ;
+    END
+  END rw0_rd_out[20]
+  PIN rw0_rd_out[21]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 66.913 0.000 66.927 0.042 ;
+    END
+  END rw0_rd_out[21]
+  PIN rw0_rd_out[22]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 67.361 0.000 67.375 0.042 ;
+    END
+  END rw0_rd_out[22]
+  PIN rw0_rd_out[23]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 67.809 0.000 67.823 0.042 ;
+    END
+  END rw0_rd_out[23]
+  PIN rw0_rd_out[24]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 68.257 0.000 68.271 0.042 ;
+    END
+  END rw0_rd_out[24]
+  PIN rw0_rd_out[25]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 68.705 0.000 68.719 0.042 ;
+    END
+  END rw0_rd_out[25]
+  PIN rw0_rd_out[26]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 69.153 0.000 69.167 0.042 ;
+    END
+  END rw0_rd_out[26]
+  PIN rw0_rd_out[27]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 69.601 0.000 69.615 0.042 ;
+    END
+  END rw0_rd_out[27]
+  PIN rw0_rd_out[28]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 70.049 0.000 70.063 0.042 ;
+    END
+  END rw0_rd_out[28]
+  PIN rw0_rd_out[29]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 70.497 0.000 70.511 0.042 ;
+    END
+  END rw0_rd_out[29]
+  PIN rw0_rd_out[30]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 70.945 0.000 70.959 0.042 ;
+    END
+  END rw0_rd_out[30]
+  PIN rw0_rd_out[31]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 71.393 0.000 71.407 0.042 ;
+    END
+  END rw0_rd_out[31]
+  PIN rw0_rd_out[32]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 71.841 0.000 71.855 0.042 ;
+    END
+  END rw0_rd_out[32]
+  PIN rw0_rd_out[33]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 72.289 0.000 72.303 0.042 ;
+    END
+  END rw0_rd_out[33]
+  PIN rw0_rd_out[34]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 72.737 0.000 72.751 0.042 ;
+    END
+  END rw0_rd_out[34]
+  PIN rw0_rd_out[35]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 73.185 0.000 73.199 0.042 ;
+    END
+  END rw0_rd_out[35]
+  PIN rw0_rd_out[36]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 73.633 0.000 73.647 0.042 ;
+    END
+  END rw0_rd_out[36]
+  PIN rw0_rd_out[37]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 74.081 0.000 74.095 0.042 ;
+    END
+  END rw0_rd_out[37]
+  PIN rw0_rd_out[38]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 74.529 0.000 74.543 0.042 ;
+    END
+  END rw0_rd_out[38]
+  PIN rw0_rd_out[39]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 74.977 0.000 74.991 0.042 ;
+    END
+  END rw0_rd_out[39]
+  PIN rw0_rd_out[40]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 75.425 0.000 75.439 0.042 ;
+    END
+  END rw0_rd_out[40]
+  PIN rw0_rd_out[41]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 75.873 0.000 75.887 0.042 ;
+    END
+  END rw0_rd_out[41]
+  PIN rw0_rd_out[42]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 76.321 0.000 76.335 0.042 ;
+    END
+  END rw0_rd_out[42]
+  PIN rw0_rd_out[43]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 76.769 0.000 76.783 0.042 ;
+    END
+  END rw0_rd_out[43]
+  PIN rw0_rd_out[44]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 77.217 0.000 77.231 0.042 ;
+    END
+  END rw0_rd_out[44]
+  PIN rw0_rd_out[45]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 77.665 0.000 77.679 0.042 ;
+    END
+  END rw0_rd_out[45]
+  PIN rw0_rd_out[46]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 78.113 0.000 78.127 0.042 ;
+    END
+  END rw0_rd_out[46]
+  PIN rw0_rd_out[47]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 78.561 0.000 78.575 0.042 ;
+    END
+  END rw0_rd_out[47]
+  PIN rw0_rd_out[48]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 79.009 0.000 79.023 0.042 ;
+    END
+  END rw0_rd_out[48]
+  PIN rw0_rd_out[49]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 79.457 0.000 79.471 0.042 ;
+    END
+  END rw0_rd_out[49]
+  PIN rw0_rd_out[50]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 79.905 0.000 79.919 0.042 ;
+    END
+  END rw0_rd_out[50]
+  PIN rw0_rd_out[51]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 80.353 0.000 80.367 0.042 ;
+    END
+  END rw0_rd_out[51]
+  PIN rw0_rd_out[52]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 80.801 0.000 80.815 0.042 ;
+    END
+  END rw0_rd_out[52]
+  PIN rw0_rd_out[53]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 81.249 0.000 81.263 0.042 ;
+    END
+  END rw0_rd_out[53]
+  PIN rw0_rd_out[54]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 81.697 0.000 81.711 0.042 ;
+    END
+  END rw0_rd_out[54]
+  PIN rw0_rd_out[55]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 82.145 0.000 82.159 0.042 ;
+    END
+  END rw0_rd_out[55]
+  PIN rw0_rd_out[56]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 82.593 0.000 82.607 0.042 ;
+    END
+  END rw0_rd_out[56]
+  PIN rw0_rd_out[57]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 83.041 0.000 83.055 0.042 ;
+    END
+  END rw0_rd_out[57]
+  PIN rw0_rd_out[58]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 83.489 0.000 83.503 0.042 ;
+    END
+  END rw0_rd_out[58]
+  PIN rw0_rd_out[59]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 83.937 0.000 83.951 0.042 ;
+    END
+  END rw0_rd_out[59]
+  PIN rw0_rd_out[60]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 84.385 0.000 84.399 0.042 ;
+    END
+  END rw0_rd_out[60]
+  PIN rw0_rd_out[61]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 84.833 0.000 84.847 0.042 ;
+    END
+  END rw0_rd_out[61]
+  PIN rw0_rd_out[62]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 85.281 0.000 85.295 0.042 ;
+    END
+  END rw0_rd_out[62]
+  PIN rw0_rd_out[63]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 85.729 0.000 85.743 0.042 ;
+    END
+  END rw0_rd_out[63]
+  PIN rw0_rd_out[64]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 86.177 0.000 86.191 0.042 ;
+    END
+  END rw0_rd_out[64]
+  PIN rw0_rd_out[65]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 86.625 0.000 86.639 0.042 ;
+    END
+  END rw0_rd_out[65]
+  PIN rw0_rd_out[66]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 87.073 0.000 87.087 0.042 ;
+    END
+  END rw0_rd_out[66]
+  PIN rw0_rd_out[67]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 87.521 0.000 87.535 0.042 ;
+    END
+  END rw0_rd_out[67]
+  PIN rw0_rd_out[68]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 87.969 0.000 87.983 0.042 ;
+    END
+  END rw0_rd_out[68]
+  PIN rw0_rd_out[69]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 88.417 0.000 88.431 0.042 ;
+    END
+  END rw0_rd_out[69]
+  PIN rw0_rd_out[70]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 88.865 0.000 88.879 0.042 ;
+    END
+  END rw0_rd_out[70]
+  PIN rw0_rd_out[71]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 89.313 0.000 89.327 0.042 ;
+    END
+  END rw0_rd_out[71]
+  PIN rw0_rd_out[72]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 89.761 0.000 89.775 0.042 ;
+    END
+  END rw0_rd_out[72]
+  PIN rw0_rd_out[73]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 90.209 0.000 90.223 0.042 ;
+    END
+  END rw0_rd_out[73]
+  PIN rw0_rd_out[74]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 90.657 0.000 90.671 0.042 ;
+    END
+  END rw0_rd_out[74]
+  PIN rw0_rd_out[75]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 91.105 0.000 91.119 0.042 ;
+    END
+  END rw0_rd_out[75]
+  PIN rw0_rd_out[76]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 91.553 0.000 91.567 0.042 ;
+    END
+  END rw0_rd_out[76]
+  PIN rw0_rd_out[77]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 92.001 0.000 92.015 0.042 ;
+    END
+  END rw0_rd_out[77]
+  PIN rw0_rd_out[78]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 92.449 0.000 92.463 0.042 ;
+    END
+  END rw0_rd_out[78]
+  PIN rw0_rd_out[79]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 92.897 0.000 92.911 0.042 ;
+    END
+  END rw0_rd_out[79]
+  PIN rw0_rd_out[80]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 93.345 0.000 93.359 0.042 ;
+    END
+  END rw0_rd_out[80]
+  PIN rw0_rd_out[81]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 93.793 0.000 93.807 0.042 ;
+    END
+  END rw0_rd_out[81]
+  PIN rw0_rd_out[82]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 94.241 0.000 94.255 0.042 ;
+    END
+  END rw0_rd_out[82]
+  PIN rw0_rd_out[83]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 94.689 0.000 94.703 0.042 ;
+    END
+  END rw0_rd_out[83]
+  PIN rw0_rd_out[84]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 95.137 0.000 95.151 0.042 ;
+    END
+  END rw0_rd_out[84]
+  PIN rw0_rd_out[85]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 95.585 0.000 95.599 0.042 ;
+    END
+  END rw0_rd_out[85]
+  PIN rw0_rd_out[86]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 96.033 0.000 96.047 0.042 ;
+    END
+  END rw0_rd_out[86]
+  PIN rw0_rd_out[87]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 96.481 0.000 96.495 0.042 ;
+    END
+  END rw0_rd_out[87]
+  PIN rw0_rd_out[88]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 96.929 0.000 96.943 0.042 ;
+    END
+  END rw0_rd_out[88]
+  PIN rw0_rd_out[89]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 97.377 0.000 97.391 0.042 ;
+    END
+  END rw0_rd_out[89]
+  PIN rw0_rd_out[90]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 97.825 0.000 97.839 0.042 ;
+    END
+  END rw0_rd_out[90]
+  PIN rw0_rd_out[91]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 98.273 0.000 98.287 0.042 ;
+    END
+  END rw0_rd_out[91]
+  PIN rw0_rd_out[92]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 98.721 0.000 98.735 0.042 ;
+    END
+  END rw0_rd_out[92]
+  PIN rw0_rd_out[93]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 99.169 0.000 99.183 0.042 ;
+    END
+  END rw0_rd_out[93]
+  PIN rw0_rd_out[94]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 99.617 0.000 99.631 0.042 ;
+    END
+  END rw0_rd_out[94]
+  PIN rw0_rd_out[95]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 100.065 0.000 100.079 0.042 ;
+    END
+  END rw0_rd_out[95]
+  PIN rw0_rd_out[96]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 100.513 0.000 100.527 0.042 ;
+    END
+  END rw0_rd_out[96]
+  PIN rw0_rd_out[97]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 100.961 0.000 100.975 0.042 ;
+    END
+  END rw0_rd_out[97]
+  PIN rw0_rd_out[98]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 101.409 0.000 101.423 0.042 ;
+    END
+  END rw0_rd_out[98]
+  PIN rw0_rd_out[99]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 101.857 0.000 101.871 0.042 ;
+    END
+  END rw0_rd_out[99]
+  PIN rw0_rd_out[100]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 102.305 0.000 102.319 0.042 ;
+    END
+  END rw0_rd_out[100]
+  PIN rw0_rd_out[101]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 102.753 0.000 102.767 0.042 ;
+    END
+  END rw0_rd_out[101]
+  PIN rw0_rd_out[102]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 103.201 0.000 103.215 0.042 ;
+    END
+  END rw0_rd_out[102]
+  PIN rw0_rd_out[103]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 103.649 0.000 103.663 0.042 ;
+    END
+  END rw0_rd_out[103]
+  PIN rw0_rd_out[104]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 104.097 0.000 104.111 0.042 ;
+    END
+  END rw0_rd_out[104]
+  PIN rw0_rd_out[105]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 104.545 0.000 104.559 0.042 ;
+    END
+  END rw0_rd_out[105]
+  PIN rw0_rd_out[106]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 104.993 0.000 105.007 0.042 ;
+    END
+  END rw0_rd_out[106]
+  PIN rw0_rd_out[107]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 105.441 0.000 105.455 0.042 ;
+    END
+  END rw0_rd_out[107]
+  PIN rw0_rd_out[108]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 105.889 0.000 105.903 0.042 ;
+    END
+  END rw0_rd_out[108]
+  PIN rw0_rd_out[109]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 106.337 0.000 106.351 0.042 ;
+    END
+  END rw0_rd_out[109]
+  PIN rw0_rd_out[110]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 106.785 0.000 106.799 0.042 ;
+    END
+  END rw0_rd_out[110]
+  PIN rw0_rd_out[111]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 107.233 0.000 107.247 0.042 ;
+    END
+  END rw0_rd_out[111]
+  PIN rw0_rd_out[112]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 107.681 0.000 107.695 0.042 ;
+    END
+  END rw0_rd_out[112]
+  PIN rw0_rd_out[113]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 108.129 0.000 108.143 0.042 ;
+    END
+  END rw0_rd_out[113]
+  PIN rw0_rd_out[114]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 108.577 0.000 108.591 0.042 ;
+    END
+  END rw0_rd_out[114]
+  PIN rw0_rd_out[115]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 109.025 0.000 109.039 0.042 ;
+    END
+  END rw0_rd_out[115]
+  PIN rw0_rd_out[116]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 109.473 0.000 109.487 0.042 ;
+    END
+  END rw0_rd_out[116]
+  PIN rw0_rd_out[117]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 109.921 0.000 109.935 0.042 ;
+    END
+  END rw0_rd_out[117]
+  PIN rw0_rd_out[118]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 110.369 0.000 110.383 0.042 ;
+    END
+  END rw0_rd_out[118]
+  PIN rw0_rd_out[119]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 110.817 0.000 110.831 0.042 ;
+    END
+  END rw0_rd_out[119]
+  PIN rw0_rd_out[120]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 111.265 0.000 111.279 0.042 ;
+    END
+  END rw0_rd_out[120]
+  PIN rw0_rd_out[121]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 111.713 0.000 111.727 0.042 ;
+    END
+  END rw0_rd_out[121]
+  PIN rw0_rd_out[122]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 112.161 0.000 112.175 0.042 ;
+    END
+  END rw0_rd_out[122]
+  PIN rw0_rd_out[123]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 112.609 0.000 112.623 0.042 ;
+    END
+  END rw0_rd_out[123]
+  PIN rw0_rd_out[124]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 113.057 0.000 113.071 0.042 ;
+    END
+  END rw0_rd_out[124]
+  PIN rw0_rd_out[125]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 113.505 0.000 113.519 0.042 ;
+    END
+  END rw0_rd_out[125]
+  PIN rw0_rd_out[126]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 113.953 0.000 113.967 0.042 ;
+    END
+  END rw0_rd_out[126]
+  PIN rw0_rd_out[127]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 114.401 0.000 114.415 0.042 ;
+    END
+  END rw0_rd_out[127]
+  PIN rw0_rd_out[128]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 0.161 73.398 0.175 73.440 ;
+    END
+  END rw0_rd_out[128]
+  PIN rw0_rd_out[129]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 1.029 73.398 1.043 73.440 ;
+    END
+  END rw0_rd_out[129]
+  PIN rw0_rd_out[130]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 1.897 73.398 1.911 73.440 ;
+    END
+  END rw0_rd_out[130]
+  PIN rw0_rd_out[131]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 2.765 73.398 2.779 73.440 ;
+    END
+  END rw0_rd_out[131]
+  PIN rw0_rd_out[132]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 3.633 73.398 3.647 73.440 ;
+    END
+  END rw0_rd_out[132]
+  PIN rw0_rd_out[133]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 4.501 73.398 4.515 73.440 ;
+    END
+  END rw0_rd_out[133]
+  PIN rw0_rd_out[134]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 5.369 73.398 5.383 73.440 ;
+    END
+  END rw0_rd_out[134]
+  PIN rw0_rd_out[135]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 6.237 73.398 6.251 73.440 ;
+    END
+  END rw0_rd_out[135]
+  PIN rw0_rd_out[136]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 7.105 73.398 7.119 73.440 ;
+    END
+  END rw0_rd_out[136]
+  PIN rw0_rd_out[137]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 7.973 73.398 7.987 73.440 ;
+    END
+  END rw0_rd_out[137]
+  PIN rw0_rd_out[138]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 8.841 73.398 8.855 73.440 ;
+    END
+  END rw0_rd_out[138]
+  PIN rw0_rd_out[139]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 9.709 73.398 9.723 73.440 ;
+    END
+  END rw0_rd_out[139]
+  PIN rw0_rd_out[140]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 10.577 73.398 10.591 73.440 ;
+    END
+  END rw0_rd_out[140]
+  PIN rw0_rd_out[141]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 11.445 73.398 11.459 73.440 ;
+    END
+  END rw0_rd_out[141]
+  PIN rw0_rd_out[142]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 12.313 73.398 12.327 73.440 ;
+    END
+  END rw0_rd_out[142]
+  PIN rw0_rd_out[143]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 13.181 73.398 13.195 73.440 ;
+    END
+  END rw0_rd_out[143]
+  PIN rw0_rd_out[144]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 14.049 73.398 14.063 73.440 ;
+    END
+  END rw0_rd_out[144]
+  PIN rw0_rd_out[145]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 14.917 73.398 14.931 73.440 ;
+    END
+  END rw0_rd_out[145]
+  PIN rw0_rd_out[146]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 15.785 73.398 15.799 73.440 ;
+    END
+  END rw0_rd_out[146]
+  PIN rw0_rd_out[147]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 16.653 73.398 16.667 73.440 ;
+    END
+  END rw0_rd_out[147]
+  PIN rw0_rd_out[148]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 17.521 73.398 17.535 73.440 ;
+    END
+  END rw0_rd_out[148]
+  PIN rw0_rd_out[149]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 18.389 73.398 18.403 73.440 ;
+    END
+  END rw0_rd_out[149]
+  PIN rw0_rd_out[150]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 19.257 73.398 19.271 73.440 ;
+    END
+  END rw0_rd_out[150]
+  PIN rw0_rd_out[151]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 20.125 73.398 20.139 73.440 ;
+    END
+  END rw0_rd_out[151]
+  PIN rw0_rd_out[152]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 20.993 73.398 21.007 73.440 ;
+    END
+  END rw0_rd_out[152]
+  PIN rw0_rd_out[153]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 21.861 73.398 21.875 73.440 ;
+    END
+  END rw0_rd_out[153]
+  PIN rw0_rd_out[154]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 22.729 73.398 22.743 73.440 ;
+    END
+  END rw0_rd_out[154]
+  PIN rw0_rd_out[155]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 23.597 73.398 23.611 73.440 ;
+    END
+  END rw0_rd_out[155]
+  PIN rw0_rd_out[156]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 24.465 73.398 24.479 73.440 ;
+    END
+  END rw0_rd_out[156]
+  PIN rw0_rd_out[157]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 25.333 73.398 25.347 73.440 ;
+    END
+  END rw0_rd_out[157]
+  PIN rw0_rd_out[158]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 26.201 73.398 26.215 73.440 ;
+    END
+  END rw0_rd_out[158]
+  PIN rw0_rd_out[159]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 27.069 73.398 27.083 73.440 ;
+    END
+  END rw0_rd_out[159]
+  PIN rw0_rd_out[160]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 27.937 73.398 27.951 73.440 ;
+    END
+  END rw0_rd_out[160]
+  PIN rw0_rd_out[161]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 28.805 73.398 28.819 73.440 ;
+    END
+  END rw0_rd_out[161]
+  PIN rw0_rd_out[162]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 29.673 73.398 29.687 73.440 ;
+    END
+  END rw0_rd_out[162]
+  PIN rw0_rd_out[163]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 30.541 73.398 30.555 73.440 ;
+    END
+  END rw0_rd_out[163]
+  PIN rw0_rd_out[164]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 31.409 73.398 31.423 73.440 ;
+    END
+  END rw0_rd_out[164]
+  PIN rw0_rd_out[165]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 32.277 73.398 32.291 73.440 ;
+    END
+  END rw0_rd_out[165]
+  PIN rw0_rd_out[166]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 33.145 73.398 33.159 73.440 ;
+    END
+  END rw0_rd_out[166]
+  PIN rw0_rd_out[167]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 34.013 73.398 34.027 73.440 ;
+    END
+  END rw0_rd_out[167]
+  PIN rw0_rd_out[168]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 34.881 73.398 34.895 73.440 ;
+    END
+  END rw0_rd_out[168]
+  PIN rw0_rd_out[169]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 35.749 73.398 35.763 73.440 ;
+    END
+  END rw0_rd_out[169]
+  PIN rw0_rd_out[170]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 36.617 73.398 36.631 73.440 ;
+    END
+  END rw0_rd_out[170]
+  PIN rw0_rd_out[171]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 37.485 73.398 37.499 73.440 ;
+    END
+  END rw0_rd_out[171]
+  PIN rw0_rd_out[172]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 38.353 73.398 38.367 73.440 ;
+    END
+  END rw0_rd_out[172]
+  PIN rw0_rd_out[173]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 39.221 73.398 39.235 73.440 ;
+    END
+  END rw0_rd_out[173]
+  PIN rw0_rd_out[174]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 40.089 73.398 40.103 73.440 ;
+    END
+  END rw0_rd_out[174]
+  PIN rw0_rd_out[175]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 40.957 73.398 40.971 73.440 ;
+    END
+  END rw0_rd_out[175]
+  PIN rw0_rd_out[176]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 41.825 73.398 41.839 73.440 ;
+    END
+  END rw0_rd_out[176]
+  PIN rw0_rd_out[177]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 42.693 73.398 42.707 73.440 ;
+    END
+  END rw0_rd_out[177]
+  PIN rw0_rd_out[178]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 43.561 73.398 43.575 73.440 ;
+    END
+  END rw0_rd_out[178]
+  PIN rw0_rd_out[179]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 44.429 73.398 44.443 73.440 ;
+    END
+  END rw0_rd_out[179]
+  PIN rw0_rd_out[180]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 45.297 73.398 45.311 73.440 ;
+    END
+  END rw0_rd_out[180]
+  PIN rw0_rd_out[181]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 46.165 73.398 46.179 73.440 ;
+    END
+  END rw0_rd_out[181]
+  PIN rw0_rd_out[182]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 47.033 73.398 47.047 73.440 ;
+    END
+  END rw0_rd_out[182]
+  PIN rw0_rd_out[183]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 47.901 73.398 47.915 73.440 ;
+    END
+  END rw0_rd_out[183]
+  PIN rw0_rd_out[184]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 48.769 73.398 48.783 73.440 ;
+    END
+  END rw0_rd_out[184]
+  PIN rw0_rd_out[185]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 49.637 73.398 49.651 73.440 ;
+    END
+  END rw0_rd_out[185]
+  PIN rw0_rd_out[186]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 50.505 73.398 50.519 73.440 ;
+    END
+  END rw0_rd_out[186]
+  PIN rw0_rd_out[187]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 51.373 73.398 51.387 73.440 ;
+    END
+  END rw0_rd_out[187]
+  PIN rw0_rd_out[188]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 52.241 73.398 52.255 73.440 ;
+    END
+  END rw0_rd_out[188]
+  PIN rw0_rd_out[189]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 53.109 73.398 53.123 73.440 ;
+    END
+  END rw0_rd_out[189]
+  PIN rw0_rd_out[190]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 53.977 73.398 53.991 73.440 ;
+    END
+  END rw0_rd_out[190]
+  PIN rw0_rd_out[191]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 54.845 73.398 54.859 73.440 ;
+    END
+  END rw0_rd_out[191]
+  PIN rw0_rd_out[192]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 55.713 73.398 55.727 73.440 ;
+    END
+  END rw0_rd_out[192]
+  PIN rw0_rd_out[193]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 56.581 73.398 56.595 73.440 ;
+    END
+  END rw0_rd_out[193]
+  PIN rw0_rd_out[194]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 57.449 73.398 57.463 73.440 ;
+    END
+  END rw0_rd_out[194]
+  PIN rw0_rd_out[195]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 58.317 73.398 58.331 73.440 ;
+    END
+  END rw0_rd_out[195]
+  PIN rw0_rd_out[196]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 59.185 73.398 59.199 73.440 ;
+    END
+  END rw0_rd_out[196]
+  PIN rw0_rd_out[197]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 60.053 73.398 60.067 73.440 ;
+    END
+  END rw0_rd_out[197]
+  PIN rw0_rd_out[198]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 60.921 73.398 60.935 73.440 ;
+    END
+  END rw0_rd_out[198]
+  PIN rw0_rd_out[199]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 61.789 73.398 61.803 73.440 ;
+    END
+  END rw0_rd_out[199]
+  PIN rw0_rd_out[200]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 62.657 73.398 62.671 73.440 ;
+    END
+  END rw0_rd_out[200]
+  PIN rw0_rd_out[201]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 63.525 73.398 63.539 73.440 ;
+    END
+  END rw0_rd_out[201]
+  PIN rw0_rd_out[202]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 64.393 73.398 64.407 73.440 ;
+    END
+  END rw0_rd_out[202]
+  PIN rw0_rd_out[203]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 65.261 73.398 65.275 73.440 ;
+    END
+  END rw0_rd_out[203]
+  PIN rw0_rd_out[204]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 66.129 73.398 66.143 73.440 ;
+    END
+  END rw0_rd_out[204]
+  PIN rw0_rd_out[205]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 66.997 73.398 67.011 73.440 ;
+    END
+  END rw0_rd_out[205]
+  PIN rw0_rd_out[206]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 67.865 73.398 67.879 73.440 ;
+    END
+  END rw0_rd_out[206]
+  PIN rw0_rd_out[207]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 68.733 73.398 68.747 73.440 ;
+    END
+  END rw0_rd_out[207]
+  PIN rw0_rd_out[208]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 69.601 73.398 69.615 73.440 ;
+    END
+  END rw0_rd_out[208]
+  PIN rw0_rd_out[209]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 70.469 73.398 70.483 73.440 ;
+    END
+  END rw0_rd_out[209]
+  PIN rw0_rd_out[210]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 71.337 73.398 71.351 73.440 ;
+    END
+  END rw0_rd_out[210]
+  PIN rw0_rd_out[211]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 72.205 73.398 72.219 73.440 ;
+    END
+  END rw0_rd_out[211]
+  PIN rw0_rd_out[212]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 73.073 73.398 73.087 73.440 ;
+    END
+  END rw0_rd_out[212]
+  PIN rw0_rd_out[213]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 73.941 73.398 73.955 73.440 ;
+    END
+  END rw0_rd_out[213]
+  PIN rw0_rd_out[214]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 74.809 73.398 74.823 73.440 ;
+    END
+  END rw0_rd_out[214]
+  PIN rw0_rd_out[215]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 75.677 73.398 75.691 73.440 ;
+    END
+  END rw0_rd_out[215]
+  PIN rw0_rd_out[216]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 76.545 73.398 76.559 73.440 ;
+    END
+  END rw0_rd_out[216]
+  PIN rw0_rd_out[217]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 77.413 73.398 77.427 73.440 ;
+    END
+  END rw0_rd_out[217]
+  PIN rw0_rd_out[218]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 78.281 73.398 78.295 73.440 ;
+    END
+  END rw0_rd_out[218]
+  PIN rw0_rd_out[219]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 79.149 73.398 79.163 73.440 ;
+    END
+  END rw0_rd_out[219]
+  PIN rw0_rd_out[220]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 80.017 73.398 80.031 73.440 ;
+    END
+  END rw0_rd_out[220]
+  PIN rw0_rd_out[221]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 80.885 73.398 80.899 73.440 ;
+    END
+  END rw0_rd_out[221]
+  PIN rw0_rd_out[222]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 81.753 73.398 81.767 73.440 ;
+    END
+  END rw0_rd_out[222]
+  PIN rw0_rd_out[223]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 82.621 73.398 82.635 73.440 ;
+    END
+  END rw0_rd_out[223]
+  PIN rw0_rd_out[224]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 83.489 73.398 83.503 73.440 ;
+    END
+  END rw0_rd_out[224]
+  PIN rw0_rd_out[225]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 84.357 73.398 84.371 73.440 ;
+    END
+  END rw0_rd_out[225]
+  PIN rw0_rd_out[226]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 85.225 73.398 85.239 73.440 ;
+    END
+  END rw0_rd_out[226]
+  PIN rw0_rd_out[227]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 86.093 73.398 86.107 73.440 ;
+    END
+  END rw0_rd_out[227]
+  PIN rw0_rd_out[228]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 86.961 73.398 86.975 73.440 ;
+    END
+  END rw0_rd_out[228]
+  PIN rw0_rd_out[229]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 87.829 73.398 87.843 73.440 ;
+    END
+  END rw0_rd_out[229]
+  PIN rw0_rd_out[230]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 88.697 73.398 88.711 73.440 ;
+    END
+  END rw0_rd_out[230]
+  PIN rw0_rd_out[231]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 89.565 73.398 89.579 73.440 ;
+    END
+  END rw0_rd_out[231]
+  PIN rw0_rd_out[232]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 90.433 73.398 90.447 73.440 ;
+    END
+  END rw0_rd_out[232]
+  PIN rw0_rd_out[233]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 91.301 73.398 91.315 73.440 ;
+    END
+  END rw0_rd_out[233]
+  PIN rw0_rd_out[234]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 92.169 73.398 92.183 73.440 ;
+    END
+  END rw0_rd_out[234]
+  PIN rw0_rd_out[235]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 93.037 73.398 93.051 73.440 ;
+    END
+  END rw0_rd_out[235]
+  PIN rw0_rd_out[236]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 93.905 73.398 93.919 73.440 ;
+    END
+  END rw0_rd_out[236]
+  PIN rw0_rd_out[237]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 94.773 73.398 94.787 73.440 ;
+    END
+  END rw0_rd_out[237]
+  PIN rw0_rd_out[238]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 95.641 73.398 95.655 73.440 ;
+    END
+  END rw0_rd_out[238]
+  PIN rw0_rd_out[239]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 96.509 73.398 96.523 73.440 ;
+    END
+  END rw0_rd_out[239]
+  PIN rw0_rd_out[240]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 97.377 73.398 97.391 73.440 ;
+    END
+  END rw0_rd_out[240]
+  PIN rw0_rd_out[241]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 98.245 73.398 98.259 73.440 ;
+    END
+  END rw0_rd_out[241]
+  PIN rw0_rd_out[242]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 99.113 73.398 99.127 73.440 ;
+    END
+  END rw0_rd_out[242]
+  PIN rw0_rd_out[243]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 99.981 73.398 99.995 73.440 ;
+    END
+  END rw0_rd_out[243]
+  PIN rw0_rd_out[244]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 100.849 73.398 100.863 73.440 ;
+    END
+  END rw0_rd_out[244]
+  PIN rw0_rd_out[245]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 101.717 73.398 101.731 73.440 ;
+    END
+  END rw0_rd_out[245]
+  PIN rw0_rd_out[246]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 102.585 73.398 102.599 73.440 ;
+    END
+  END rw0_rd_out[246]
+  PIN rw0_rd_out[247]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 103.453 73.398 103.467 73.440 ;
+    END
+  END rw0_rd_out[247]
+  PIN rw0_rd_out[248]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
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+      RECT 0.168 60.216 117.222 60.264 ;
+      RECT 0.168 60.600 117.222 60.648 ;
+      RECT 0.168 60.984 117.222 61.032 ;
+      RECT 0.168 61.368 117.222 61.416 ;
+      RECT 0.168 61.752 117.222 61.800 ;
+      RECT 0.168 62.136 117.222 62.184 ;
+      RECT 0.168 62.520 117.222 62.568 ;
+      RECT 0.168 62.904 117.222 62.952 ;
+      RECT 0.168 63.288 117.222 63.336 ;
+      RECT 0.168 63.672 117.222 63.720 ;
+      RECT 0.168 64.056 117.222 64.104 ;
+      RECT 0.168 64.440 117.222 64.488 ;
+      RECT 0.168 64.824 117.222 64.872 ;
+      RECT 0.168 65.208 117.222 65.256 ;
+      RECT 0.168 65.592 117.222 65.640 ;
+      RECT 0.168 65.976 117.222 66.024 ;
+      RECT 0.168 66.360 117.222 66.408 ;
+      RECT 0.168 66.744 117.222 66.792 ;
+      RECT 0.168 67.128 117.222 67.176 ;
+      RECT 0.168 67.512 117.222 67.560 ;
+      RECT 0.168 67.896 117.222 67.944 ;
+      RECT 0.168 68.280 117.222 68.328 ;
+      RECT 0.168 68.664 117.222 68.712 ;
+      RECT 0.168 69.048 117.222 69.096 ;
+      RECT 0.168 69.432 117.222 69.480 ;
+      RECT 0.168 69.816 117.222 69.864 ;
+      RECT 0.168 70.200 117.222 70.248 ;
+      RECT 0.168 70.584 117.222 70.632 ;
+      RECT 0.168 70.968 117.222 71.016 ;
+      RECT 0.168 71.352 117.222 71.400 ;
+      RECT 0.168 71.736 117.222 71.784 ;
+      RECT 0.168 72.120 117.222 72.168 ;
+      RECT 0.168 72.504 117.222 72.552 ;
+      RECT 0.168 72.888 117.222 72.936 ;
+      RECT 0.168 73.272 117.222 73.320 ;
+    END
+  END VDD
+  OBS
+    LAYER M1 ;
+    RECT 0 0 117.390 73.440 ;
+    LAYER M2 ;
+    RECT 0 0 117.390 73.440 ;
+    LAYER M3 ;
+    RECT 0 0 117.390 73.440 ;
+    LAYER M4 ;
+    RECT 0 0 117.390 73.440 ;
+  END
+END fakeram7_256x256
+
+END LIBRARY
diff --git a/designs/gt2n/snitch_cluster/sram/lef/fakeram7_256x64.lef b/designs/gt2n/snitch_cluster/sram/lef/fakeram7_256x64.lef
new file mode 100644
index 00000000..3168bd27
--- /dev/null
+++ b/designs/gt2n/snitch_cluster/sram/lef/fakeram7_256x64.lef
@@ -0,0 +1,1476 @@
+VERSION 5.7 ;
+BUSBITCHARS "[]" ;
+MACRO fakeram7_256x64
+  FOREIGN fakeram7_256x64 0 0 ;
+  SYMMETRY X Y R90 ;
+  SIZE 58.716 BY 36.720 ;
+  CLASS BLOCK ;
+  PIN rw0_wd_in[0]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M2 ;
+      RECT 0.000 0.138 0.036 0.150 ;
+    END
+  END rw0_wd_in[0]
+  PIN rw0_wd_in[1]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M2 ;
+      RECT 0.000 1.938 0.036 1.950 ;
+    END
+  END rw0_wd_in[1]
+  PIN rw0_wd_in[2]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M2 ;
+      RECT 0.000 3.738 0.036 3.750 ;
+    END
+  END rw0_wd_in[2]
+  PIN rw0_wd_in[3]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M2 ;
+      RECT 0.000 5.538 0.036 5.550 ;
+    END
+  END rw0_wd_in[3]
+  PIN rw0_wd_in[4]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M2 ;
+      RECT 0.000 7.338 0.036 7.350 ;
+    END
+  END rw0_wd_in[4]
+  PIN rw0_wd_in[5]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M2 ;
+      RECT 0.000 9.138 0.036 9.150 ;
+    END
+  END rw0_wd_in[5]
+  PIN rw0_wd_in[6]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M2 ;
+      RECT 0.000 10.938 0.036 10.950 ;
+    END
+  END rw0_wd_in[6]
+  PIN rw0_wd_in[7]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M2 ;
+      RECT 0.000 12.738 0.036 12.750 ;
+    END
+  END rw0_wd_in[7]
+  PIN rw0_wd_in[8]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M2 ;
+      RECT 0.000 14.538 0.036 14.550 ;
+    END
+  END rw0_wd_in[8]
+  PIN rw0_wd_in[9]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M2 ;
+      RECT 0.000 16.338 0.036 16.350 ;
+    END
+  END rw0_wd_in[9]
+  PIN rw0_wd_in[10]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M2 ;
+      RECT 0.000 18.138 0.036 18.150 ;
+    END
+  END rw0_wd_in[10]
+  PIN rw0_wd_in[11]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M2 ;
+      RECT 0.000 19.938 0.036 19.950 ;
+    END
+  END rw0_wd_in[11]
+  PIN rw0_wd_in[12]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M2 ;
+      RECT 0.000 21.738 0.036 21.750 ;
+    END
+  END rw0_wd_in[12]
+  PIN rw0_wd_in[13]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M2 ;
+      RECT 0.000 23.538 0.036 23.550 ;
+    END
+  END rw0_wd_in[13]
+  PIN rw0_wd_in[14]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M2 ;
+      RECT 0.000 25.338 0.036 25.350 ;
+    END
+  END rw0_wd_in[14]
+  PIN rw0_wd_in[15]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M2 ;
+      RECT 0.000 27.138 0.036 27.150 ;
+    END
+  END rw0_wd_in[15]
+  PIN rw0_wd_in[16]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M2 ;
+      RECT 58.680 0.138 58.716 0.150 ;
+    END
+  END rw0_wd_in[16]
+  PIN rw0_wd_in[17]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M2 ;
+      RECT 58.680 1.938 58.716 1.950 ;
+    END
+  END rw0_wd_in[17]
+  PIN rw0_wd_in[18]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M2 ;
+      RECT 58.680 3.738 58.716 3.750 ;
+    END
+  END rw0_wd_in[18]
+  PIN rw0_wd_in[19]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M2 ;
+      RECT 58.680 5.538 58.716 5.550 ;
+    END
+  END rw0_wd_in[19]
+  PIN rw0_wd_in[20]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M2 ;
+      RECT 58.680 7.338 58.716 7.350 ;
+    END
+  END rw0_wd_in[20]
+  PIN rw0_wd_in[21]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M2 ;
+      RECT 58.680 9.138 58.716 9.150 ;
+    END
+  END rw0_wd_in[21]
+  PIN rw0_wd_in[22]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M2 ;
+      RECT 58.680 10.938 58.716 10.950 ;
+    END
+  END rw0_wd_in[22]
+  PIN rw0_wd_in[23]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M2 ;
+      RECT 58.680 12.738 58.716 12.750 ;
+    END
+  END rw0_wd_in[23]
+  PIN rw0_wd_in[24]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M2 ;
+      RECT 58.680 14.538 58.716 14.550 ;
+    END
+  END rw0_wd_in[24]
+  PIN rw0_wd_in[25]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M2 ;
+      RECT 58.680 16.338 58.716 16.350 ;
+    END
+  END rw0_wd_in[25]
+  PIN rw0_wd_in[26]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M2 ;
+      RECT 58.680 18.138 58.716 18.150 ;
+    END
+  END rw0_wd_in[26]
+  PIN rw0_wd_in[27]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M2 ;
+      RECT 58.680 19.938 58.716 19.950 ;
+    END
+  END rw0_wd_in[27]
+  PIN rw0_wd_in[28]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M2 ;
+      RECT 58.680 21.738 58.716 21.750 ;
+    END
+  END rw0_wd_in[28]
+  PIN rw0_wd_in[29]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M2 ;
+      RECT 58.680 23.538 58.716 23.550 ;
+    END
+  END rw0_wd_in[29]
+  PIN rw0_wd_in[30]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M2 ;
+      RECT 58.680 25.338 58.716 25.350 ;
+    END
+  END rw0_wd_in[30]
+  PIN rw0_wd_in[31]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M2 ;
+      RECT 58.680 27.138 58.716 27.150 ;
+    END
+  END rw0_wd_in[31]
+  PIN rw0_wd_in[32]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 0.161 0.000 0.175 0.042 ;
+    END
+  END rw0_wd_in[32]
+  PIN rw0_wd_in[33]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 1.057 0.000 1.071 0.042 ;
+    END
+  END rw0_wd_in[33]
+  PIN rw0_wd_in[34]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 1.953 0.000 1.967 0.042 ;
+    END
+  END rw0_wd_in[34]
+  PIN rw0_wd_in[35]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 2.849 0.000 2.863 0.042 ;
+    END
+  END rw0_wd_in[35]
+  PIN rw0_wd_in[36]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 3.745 0.000 3.759 0.042 ;
+    END
+  END rw0_wd_in[36]
+  PIN rw0_wd_in[37]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 4.641 0.000 4.655 0.042 ;
+    END
+  END rw0_wd_in[37]
+  PIN rw0_wd_in[38]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 5.537 0.000 5.551 0.042 ;
+    END
+  END rw0_wd_in[38]
+  PIN rw0_wd_in[39]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 6.433 0.000 6.447 0.042 ;
+    END
+  END rw0_wd_in[39]
+  PIN rw0_wd_in[40]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 7.329 0.000 7.343 0.042 ;
+    END
+  END rw0_wd_in[40]
+  PIN rw0_wd_in[41]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 8.225 0.000 8.239 0.042 ;
+    END
+  END rw0_wd_in[41]
+  PIN rw0_wd_in[42]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 9.121 0.000 9.135 0.042 ;
+    END
+  END rw0_wd_in[42]
+  PIN rw0_wd_in[43]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 10.017 0.000 10.031 0.042 ;
+    END
+  END rw0_wd_in[43]
+  PIN rw0_wd_in[44]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 10.913 0.000 10.927 0.042 ;
+    END
+  END rw0_wd_in[44]
+  PIN rw0_wd_in[45]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 11.809 0.000 11.823 0.042 ;
+    END
+  END rw0_wd_in[45]
+  PIN rw0_wd_in[46]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 12.705 0.000 12.719 0.042 ;
+    END
+  END rw0_wd_in[46]
+  PIN rw0_wd_in[47]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 13.601 0.000 13.615 0.042 ;
+    END
+  END rw0_wd_in[47]
+  PIN rw0_wd_in[48]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 14.497 0.000 14.511 0.042 ;
+    END
+  END rw0_wd_in[48]
+  PIN rw0_wd_in[49]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 15.393 0.000 15.407 0.042 ;
+    END
+  END rw0_wd_in[49]
+  PIN rw0_wd_in[50]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 16.289 0.000 16.303 0.042 ;
+    END
+  END rw0_wd_in[50]
+  PIN rw0_wd_in[51]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 17.185 0.000 17.199 0.042 ;
+    END
+  END rw0_wd_in[51]
+  PIN rw0_wd_in[52]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 18.081 0.000 18.095 0.042 ;
+    END
+  END rw0_wd_in[52]
+  PIN rw0_wd_in[53]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 18.977 0.000 18.991 0.042 ;
+    END
+  END rw0_wd_in[53]
+  PIN rw0_wd_in[54]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 19.873 0.000 19.887 0.042 ;
+    END
+  END rw0_wd_in[54]
+  PIN rw0_wd_in[55]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 20.769 0.000 20.783 0.042 ;
+    END
+  END rw0_wd_in[55]
+  PIN rw0_wd_in[56]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 21.665 0.000 21.679 0.042 ;
+    END
+  END rw0_wd_in[56]
+  PIN rw0_wd_in[57]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 22.561 0.000 22.575 0.042 ;
+    END
+  END rw0_wd_in[57]
+  PIN rw0_wd_in[58]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 23.457 0.000 23.471 0.042 ;
+    END
+  END rw0_wd_in[58]
+  PIN rw0_wd_in[59]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 24.353 0.000 24.367 0.042 ;
+    END
+  END rw0_wd_in[59]
+  PIN rw0_wd_in[60]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 25.249 0.000 25.263 0.042 ;
+    END
+  END rw0_wd_in[60]
+  PIN rw0_wd_in[61]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 26.145 0.000 26.159 0.042 ;
+    END
+  END rw0_wd_in[61]
+  PIN rw0_wd_in[62]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 27.041 0.000 27.055 0.042 ;
+    END
+  END rw0_wd_in[62]
+  PIN rw0_wd_in[63]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 27.937 0.000 27.951 0.042 ;
+    END
+  END rw0_wd_in[63]
+  PIN rw0_rd_out[0]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 28.833 0.000 28.847 0.042 ;
+    END
+  END rw0_rd_out[0]
+  PIN rw0_rd_out[1]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 29.729 0.000 29.743 0.042 ;
+    END
+  END rw0_rd_out[1]
+  PIN rw0_rd_out[2]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 30.625 0.000 30.639 0.042 ;
+    END
+  END rw0_rd_out[2]
+  PIN rw0_rd_out[3]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 31.521 0.000 31.535 0.042 ;
+    END
+  END rw0_rd_out[3]
+  PIN rw0_rd_out[4]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 32.417 0.000 32.431 0.042 ;
+    END
+  END rw0_rd_out[4]
+  PIN rw0_rd_out[5]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 33.313 0.000 33.327 0.042 ;
+    END
+  END rw0_rd_out[5]
+  PIN rw0_rd_out[6]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 34.209 0.000 34.223 0.042 ;
+    END
+  END rw0_rd_out[6]
+  PIN rw0_rd_out[7]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 35.105 0.000 35.119 0.042 ;
+    END
+  END rw0_rd_out[7]
+  PIN rw0_rd_out[8]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 36.001 0.000 36.015 0.042 ;
+    END
+  END rw0_rd_out[8]
+  PIN rw0_rd_out[9]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 36.897 0.000 36.911 0.042 ;
+    END
+  END rw0_rd_out[9]
+  PIN rw0_rd_out[10]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 37.793 0.000 37.807 0.042 ;
+    END
+  END rw0_rd_out[10]
+  PIN rw0_rd_out[11]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 38.689 0.000 38.703 0.042 ;
+    END
+  END rw0_rd_out[11]
+  PIN rw0_rd_out[12]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 39.585 0.000 39.599 0.042 ;
+    END
+  END rw0_rd_out[12]
+  PIN rw0_rd_out[13]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 40.481 0.000 40.495 0.042 ;
+    END
+  END rw0_rd_out[13]
+  PIN rw0_rd_out[14]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 41.377 0.000 41.391 0.042 ;
+    END
+  END rw0_rd_out[14]
+  PIN rw0_rd_out[15]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 42.273 0.000 42.287 0.042 ;
+    END
+  END rw0_rd_out[15]
+  PIN rw0_rd_out[16]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 43.169 0.000 43.183 0.042 ;
+    END
+  END rw0_rd_out[16]
+  PIN rw0_rd_out[17]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 44.065 0.000 44.079 0.042 ;
+    END
+  END rw0_rd_out[17]
+  PIN rw0_rd_out[18]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 44.961 0.000 44.975 0.042 ;
+    END
+  END rw0_rd_out[18]
+  PIN rw0_rd_out[19]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 45.857 0.000 45.871 0.042 ;
+    END
+  END rw0_rd_out[19]
+  PIN rw0_rd_out[20]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 46.753 0.000 46.767 0.042 ;
+    END
+  END rw0_rd_out[20]
+  PIN rw0_rd_out[21]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 47.649 0.000 47.663 0.042 ;
+    END
+  END rw0_rd_out[21]
+  PIN rw0_rd_out[22]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 48.545 0.000 48.559 0.042 ;
+    END
+  END rw0_rd_out[22]
+  PIN rw0_rd_out[23]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 49.441 0.000 49.455 0.042 ;
+    END
+  END rw0_rd_out[23]
+  PIN rw0_rd_out[24]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 50.337 0.000 50.351 0.042 ;
+    END
+  END rw0_rd_out[24]
+  PIN rw0_rd_out[25]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 51.233 0.000 51.247 0.042 ;
+    END
+  END rw0_rd_out[25]
+  PIN rw0_rd_out[26]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 52.129 0.000 52.143 0.042 ;
+    END
+  END rw0_rd_out[26]
+  PIN rw0_rd_out[27]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 53.025 0.000 53.039 0.042 ;
+    END
+  END rw0_rd_out[27]
+  PIN rw0_rd_out[28]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 53.921 0.000 53.935 0.042 ;
+    END
+  END rw0_rd_out[28]
+  PIN rw0_rd_out[29]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 54.817 0.000 54.831 0.042 ;
+    END
+  END rw0_rd_out[29]
+  PIN rw0_rd_out[30]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 55.713 0.000 55.727 0.042 ;
+    END
+  END rw0_rd_out[30]
+  PIN rw0_rd_out[31]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 56.609 0.000 56.623 0.042 ;
+    END
+  END rw0_rd_out[31]
+  PIN rw0_rd_out[32]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 0.161 36.678 0.175 36.720 ;
+    END
+  END rw0_rd_out[32]
+  PIN rw0_rd_out[33]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 1.813 36.678 1.827 36.720 ;
+    END
+  END rw0_rd_out[33]
+  PIN rw0_rd_out[34]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 3.465 36.678 3.479 36.720 ;
+    END
+  END rw0_rd_out[34]
+  PIN rw0_rd_out[35]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 5.117 36.678 5.131 36.720 ;
+    END
+  END rw0_rd_out[35]
+  PIN rw0_rd_out[36]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 6.769 36.678 6.783 36.720 ;
+    END
+  END rw0_rd_out[36]
+  PIN rw0_rd_out[37]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 8.421 36.678 8.435 36.720 ;
+    END
+  END rw0_rd_out[37]
+  PIN rw0_rd_out[38]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 10.073 36.678 10.087 36.720 ;
+    END
+  END rw0_rd_out[38]
+  PIN rw0_rd_out[39]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 11.725 36.678 11.739 36.720 ;
+    END
+  END rw0_rd_out[39]
+  PIN rw0_rd_out[40]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 13.377 36.678 13.391 36.720 ;
+    END
+  END rw0_rd_out[40]
+  PIN rw0_rd_out[41]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 15.029 36.678 15.043 36.720 ;
+    END
+  END rw0_rd_out[41]
+  PIN rw0_rd_out[42]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 16.681 36.678 16.695 36.720 ;
+    END
+  END rw0_rd_out[42]
+  PIN rw0_rd_out[43]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 18.333 36.678 18.347 36.720 ;
+    END
+  END rw0_rd_out[43]
+  PIN rw0_rd_out[44]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 19.985 36.678 19.999 36.720 ;
+    END
+  END rw0_rd_out[44]
+  PIN rw0_rd_out[45]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 21.637 36.678 21.651 36.720 ;
+    END
+  END rw0_rd_out[45]
+  PIN rw0_rd_out[46]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 23.289 36.678 23.303 36.720 ;
+    END
+  END rw0_rd_out[46]
+  PIN rw0_rd_out[47]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 24.941 36.678 24.955 36.720 ;
+    END
+  END rw0_rd_out[47]
+  PIN rw0_rd_out[48]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 26.593 36.678 26.607 36.720 ;
+    END
+  END rw0_rd_out[48]
+  PIN rw0_rd_out[49]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 28.245 36.678 28.259 36.720 ;
+    END
+  END rw0_rd_out[49]
+  PIN rw0_rd_out[50]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 29.897 36.678 29.911 36.720 ;
+    END
+  END rw0_rd_out[50]
+  PIN rw0_rd_out[51]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 31.549 36.678 31.563 36.720 ;
+    END
+  END rw0_rd_out[51]
+  PIN rw0_rd_out[52]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 33.201 36.678 33.215 36.720 ;
+    END
+  END rw0_rd_out[52]
+  PIN rw0_rd_out[53]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 34.853 36.678 34.867 36.720 ;
+    END
+  END rw0_rd_out[53]
+  PIN rw0_rd_out[54]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 36.505 36.678 36.519 36.720 ;
+    END
+  END rw0_rd_out[54]
+  PIN rw0_rd_out[55]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 38.157 36.678 38.171 36.720 ;
+    END
+  END rw0_rd_out[55]
+  PIN rw0_rd_out[56]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 39.809 36.678 39.823 36.720 ;
+    END
+  END rw0_rd_out[56]
+  PIN rw0_rd_out[57]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 41.461 36.678 41.475 36.720 ;
+    END
+  END rw0_rd_out[57]
+  PIN rw0_rd_out[58]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 43.113 36.678 43.127 36.720 ;
+    END
+  END rw0_rd_out[58]
+  PIN rw0_rd_out[59]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 44.765 36.678 44.779 36.720 ;
+    END
+  END rw0_rd_out[59]
+  PIN rw0_rd_out[60]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 46.417 36.678 46.431 36.720 ;
+    END
+  END rw0_rd_out[60]
+  PIN rw0_rd_out[61]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 48.069 36.678 48.083 36.720 ;
+    END
+  END rw0_rd_out[61]
+  PIN rw0_rd_out[62]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 49.721 36.678 49.735 36.720 ;
+    END
+  END rw0_rd_out[62]
+  PIN rw0_rd_out[63]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 51.373 36.678 51.387 36.720 ;
+    END
+  END rw0_rd_out[63]
+  PIN rw0_addr_in[0]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M2 ;
+      RECT 0.000 28.938 0.036 28.950 ;
+    END
+  END rw0_addr_in[0]
+  PIN rw0_addr_in[1]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M2 ;
+      RECT 0.000 30.738 0.036 30.750 ;
+    END
+  END rw0_addr_in[1]
+  PIN rw0_addr_in[2]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M2 ;
+      RECT 0.000 32.538 0.036 32.550 ;
+    END
+  END rw0_addr_in[2]
+  PIN rw0_addr_in[3]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M2 ;
+      RECT 0.000 34.338 0.036 34.350 ;
+    END
+  END rw0_addr_in[3]
+  PIN rw0_addr_in[4]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M2 ;
+      RECT 58.680 28.938 58.716 28.950 ;
+    END
+  END rw0_addr_in[4]
+  PIN rw0_addr_in[5]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M2 ;
+      RECT 58.680 30.738 58.716 30.750 ;
+    END
+  END rw0_addr_in[5]
+  PIN rw0_addr_in[6]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M2 ;
+      RECT 58.680 32.538 58.716 32.550 ;
+    END
+  END rw0_addr_in[6]
+  PIN rw0_addr_in[7]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M2 ;
+      RECT 58.680 34.338 58.716 34.350 ;
+    END
+  END rw0_addr_in[7]
+  PIN rw0_we_in
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 53.025 36.678 53.039 36.720 ;
+    END
+  END rw0_we_in
+  PIN rw0_ce_in
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 54.677 36.678 54.691 36.720 ;
+    END
+  END rw0_ce_in
+  PIN rw0_clk
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 56.329 36.678 56.343 36.720 ;
+    END
+  END rw0_clk
+  PIN VSS
+    DIRECTION INOUT ;
+    USE GROUND ;
+    PORT
+      LAYER M4 ;
+      RECT 0.168 0.120 58.548 0.168 ;
+      RECT 0.168 0.504 58.548 0.552 ;
+      RECT 0.168 0.888 58.548 0.936 ;
+      RECT 0.168 1.272 58.548 1.320 ;
+      RECT 0.168 1.656 58.548 1.704 ;
+      RECT 0.168 2.040 58.548 2.088 ;
+      RECT 0.168 2.424 58.548 2.472 ;
+      RECT 0.168 2.808 58.548 2.856 ;
+      RECT 0.168 3.192 58.548 3.240 ;
+      RECT 0.168 3.576 58.548 3.624 ;
+      RECT 0.168 3.960 58.548 4.008 ;
+      RECT 0.168 4.344 58.548 4.392 ;
+      RECT 0.168 4.728 58.548 4.776 ;
+      RECT 0.168 5.112 58.548 5.160 ;
+      RECT 0.168 5.496 58.548 5.544 ;
+      RECT 0.168 5.880 58.548 5.928 ;
+      RECT 0.168 6.264 58.548 6.312 ;
+      RECT 0.168 6.648 58.548 6.696 ;
+      RECT 0.168 7.032 58.548 7.080 ;
+      RECT 0.168 7.416 58.548 7.464 ;
+      RECT 0.168 7.800 58.548 7.848 ;
+      RECT 0.168 8.184 58.548 8.232 ;
+      RECT 0.168 8.568 58.548 8.616 ;
+      RECT 0.168 8.952 58.548 9.000 ;
+      RECT 0.168 9.336 58.548 9.384 ;
+      RECT 0.168 9.720 58.548 9.768 ;
+      RECT 0.168 10.104 58.548 10.152 ;
+      RECT 0.168 10.488 58.548 10.536 ;
+      RECT 0.168 10.872 58.548 10.920 ;
+      RECT 0.168 11.256 58.548 11.304 ;
+      RECT 0.168 11.640 58.548 11.688 ;
+      RECT 0.168 12.024 58.548 12.072 ;
+      RECT 0.168 12.408 58.548 12.456 ;
+      RECT 0.168 12.792 58.548 12.840 ;
+      RECT 0.168 13.176 58.548 13.224 ;
+      RECT 0.168 13.560 58.548 13.608 ;
+      RECT 0.168 13.944 58.548 13.992 ;
+      RECT 0.168 14.328 58.548 14.376 ;
+      RECT 0.168 14.712 58.548 14.760 ;
+      RECT 0.168 15.096 58.548 15.144 ;
+      RECT 0.168 15.480 58.548 15.528 ;
+      RECT 0.168 15.864 58.548 15.912 ;
+      RECT 0.168 16.248 58.548 16.296 ;
+      RECT 0.168 16.632 58.548 16.680 ;
+      RECT 0.168 17.016 58.548 17.064 ;
+      RECT 0.168 17.400 58.548 17.448 ;
+      RECT 0.168 17.784 58.548 17.832 ;
+      RECT 0.168 18.168 58.548 18.216 ;
+      RECT 0.168 18.552 58.548 18.600 ;
+      RECT 0.168 18.936 58.548 18.984 ;
+      RECT 0.168 19.320 58.548 19.368 ;
+      RECT 0.168 19.704 58.548 19.752 ;
+      RECT 0.168 20.088 58.548 20.136 ;
+      RECT 0.168 20.472 58.548 20.520 ;
+      RECT 0.168 20.856 58.548 20.904 ;
+      RECT 0.168 21.240 58.548 21.288 ;
+      RECT 0.168 21.624 58.548 21.672 ;
+      RECT 0.168 22.008 58.548 22.056 ;
+      RECT 0.168 22.392 58.548 22.440 ;
+      RECT 0.168 22.776 58.548 22.824 ;
+      RECT 0.168 23.160 58.548 23.208 ;
+      RECT 0.168 23.544 58.548 23.592 ;
+      RECT 0.168 23.928 58.548 23.976 ;
+      RECT 0.168 24.312 58.548 24.360 ;
+      RECT 0.168 24.696 58.548 24.744 ;
+      RECT 0.168 25.080 58.548 25.128 ;
+      RECT 0.168 25.464 58.548 25.512 ;
+      RECT 0.168 25.848 58.548 25.896 ;
+      RECT 0.168 26.232 58.548 26.280 ;
+      RECT 0.168 26.616 58.548 26.664 ;
+      RECT 0.168 27.000 58.548 27.048 ;
+      RECT 0.168 27.384 58.548 27.432 ;
+      RECT 0.168 27.768 58.548 27.816 ;
+      RECT 0.168 28.152 58.548 28.200 ;
+      RECT 0.168 28.536 58.548 28.584 ;
+      RECT 0.168 28.920 58.548 28.968 ;
+      RECT 0.168 29.304 58.548 29.352 ;
+      RECT 0.168 29.688 58.548 29.736 ;
+      RECT 0.168 30.072 58.548 30.120 ;
+      RECT 0.168 30.456 58.548 30.504 ;
+      RECT 0.168 30.840 58.548 30.888 ;
+      RECT 0.168 31.224 58.548 31.272 ;
+      RECT 0.168 31.608 58.548 31.656 ;
+      RECT 0.168 31.992 58.548 32.040 ;
+      RECT 0.168 32.376 58.548 32.424 ;
+      RECT 0.168 32.760 58.548 32.808 ;
+      RECT 0.168 33.144 58.548 33.192 ;
+      RECT 0.168 33.528 58.548 33.576 ;
+      RECT 0.168 33.912 58.548 33.960 ;
+      RECT 0.168 34.296 58.548 34.344 ;
+      RECT 0.168 34.680 58.548 34.728 ;
+      RECT 0.168 35.064 58.548 35.112 ;
+      RECT 0.168 35.448 58.548 35.496 ;
+      RECT 0.168 35.832 58.548 35.880 ;
+      RECT 0.168 36.216 58.548 36.264 ;
+      RECT 0.168 36.600 58.548 36.648 ;
+    END
+  END VSS
+  PIN VDD
+    DIRECTION INOUT ;
+    USE POWER ;
+    PORT
+      LAYER M4 ;
+      RECT 0.168 0.312 58.548 0.360 ;
+      RECT 0.168 0.696 58.548 0.744 ;
+      RECT 0.168 1.080 58.548 1.128 ;
+      RECT 0.168 1.464 58.548 1.512 ;
+      RECT 0.168 1.848 58.548 1.896 ;
+      RECT 0.168 2.232 58.548 2.280 ;
+      RECT 0.168 2.616 58.548 2.664 ;
+      RECT 0.168 3.000 58.548 3.048 ;
+      RECT 0.168 3.384 58.548 3.432 ;
+      RECT 0.168 3.768 58.548 3.816 ;
+      RECT 0.168 4.152 58.548 4.200 ;
+      RECT 0.168 4.536 58.548 4.584 ;
+      RECT 0.168 4.920 58.548 4.968 ;
+      RECT 0.168 5.304 58.548 5.352 ;
+      RECT 0.168 5.688 58.548 5.736 ;
+      RECT 0.168 6.072 58.548 6.120 ;
+      RECT 0.168 6.456 58.548 6.504 ;
+      RECT 0.168 6.840 58.548 6.888 ;
+      RECT 0.168 7.224 58.548 7.272 ;
+      RECT 0.168 7.608 58.548 7.656 ;
+      RECT 0.168 7.992 58.548 8.040 ;
+      RECT 0.168 8.376 58.548 8.424 ;
+      RECT 0.168 8.760 58.548 8.808 ;
+      RECT 0.168 9.144 58.548 9.192 ;
+      RECT 0.168 9.528 58.548 9.576 ;
+      RECT 0.168 9.912 58.548 9.960 ;
+      RECT 0.168 10.296 58.548 10.344 ;
+      RECT 0.168 10.680 58.548 10.728 ;
+      RECT 0.168 11.064 58.548 11.112 ;
+      RECT 0.168 11.448 58.548 11.496 ;
+      RECT 0.168 11.832 58.548 11.880 ;
+      RECT 0.168 12.216 58.548 12.264 ;
+      RECT 0.168 12.600 58.548 12.648 ;
+      RECT 0.168 12.984 58.548 13.032 ;
+      RECT 0.168 13.368 58.548 13.416 ;
+      RECT 0.168 13.752 58.548 13.800 ;
+      RECT 0.168 14.136 58.548 14.184 ;
+      RECT 0.168 14.520 58.548 14.568 ;
+      RECT 0.168 14.904 58.548 14.952 ;
+      RECT 0.168 15.288 58.548 15.336 ;
+      RECT 0.168 15.672 58.548 15.720 ;
+      RECT 0.168 16.056 58.548 16.104 ;
+      RECT 0.168 16.440 58.548 16.488 ;
+      RECT 0.168 16.824 58.548 16.872 ;
+      RECT 0.168 17.208 58.548 17.256 ;
+      RECT 0.168 17.592 58.548 17.640 ;
+      RECT 0.168 17.976 58.548 18.024 ;
+      RECT 0.168 18.360 58.548 18.408 ;
+      RECT 0.168 18.744 58.548 18.792 ;
+      RECT 0.168 19.128 58.548 19.176 ;
+      RECT 0.168 19.512 58.548 19.560 ;
+      RECT 0.168 19.896 58.548 19.944 ;
+      RECT 0.168 20.280 58.548 20.328 ;
+      RECT 0.168 20.664 58.548 20.712 ;
+      RECT 0.168 21.048 58.548 21.096 ;
+      RECT 0.168 21.432 58.548 21.480 ;
+      RECT 0.168 21.816 58.548 21.864 ;
+      RECT 0.168 22.200 58.548 22.248 ;
+      RECT 0.168 22.584 58.548 22.632 ;
+      RECT 0.168 22.968 58.548 23.016 ;
+      RECT 0.168 23.352 58.548 23.400 ;
+      RECT 0.168 23.736 58.548 23.784 ;
+      RECT 0.168 24.120 58.548 24.168 ;
+      RECT 0.168 24.504 58.548 24.552 ;
+      RECT 0.168 24.888 58.548 24.936 ;
+      RECT 0.168 25.272 58.548 25.320 ;
+      RECT 0.168 25.656 58.548 25.704 ;
+      RECT 0.168 26.040 58.548 26.088 ;
+      RECT 0.168 26.424 58.548 26.472 ;
+      RECT 0.168 26.808 58.548 26.856 ;
+      RECT 0.168 27.192 58.548 27.240 ;
+      RECT 0.168 27.576 58.548 27.624 ;
+      RECT 0.168 27.960 58.548 28.008 ;
+      RECT 0.168 28.344 58.548 28.392 ;
+      RECT 0.168 28.728 58.548 28.776 ;
+      RECT 0.168 29.112 58.548 29.160 ;
+      RECT 0.168 29.496 58.548 29.544 ;
+      RECT 0.168 29.880 58.548 29.928 ;
+      RECT 0.168 30.264 58.548 30.312 ;
+      RECT 0.168 30.648 58.548 30.696 ;
+      RECT 0.168 31.032 58.548 31.080 ;
+      RECT 0.168 31.416 58.548 31.464 ;
+      RECT 0.168 31.800 58.548 31.848 ;
+      RECT 0.168 32.184 58.548 32.232 ;
+      RECT 0.168 32.568 58.548 32.616 ;
+      RECT 0.168 32.952 58.548 33.000 ;
+      RECT 0.168 33.336 58.548 33.384 ;
+      RECT 0.168 33.720 58.548 33.768 ;
+      RECT 0.168 34.104 58.548 34.152 ;
+      RECT 0.168 34.488 58.548 34.536 ;
+      RECT 0.168 34.872 58.548 34.920 ;
+      RECT 0.168 35.256 58.548 35.304 ;
+      RECT 0.168 35.640 58.548 35.688 ;
+      RECT 0.168 36.024 58.548 36.072 ;
+      RECT 0.168 36.408 58.548 36.456 ;
+    END
+  END VDD
+  OBS
+    LAYER M1 ;
+    RECT 0 0 58.716 36.720 ;
+    LAYER M2 ;
+    RECT 0 0 58.716 36.720 ;
+    LAYER M3 ;
+    RECT 0 0 58.716 36.720 ;
+    LAYER M4 ;
+    RECT 0 0 58.716 36.720 ;
+  END
+END fakeram7_256x64
+
+END LIBRARY
diff --git a/designs/gt2n/snitch_cluster/sram/lef/fakeram7_64x512.lef b/designs/gt2n/snitch_cluster/sram/lef/fakeram7_64x512.lef
new file mode 100644
index 00000000..0dcebd71
--- /dev/null
+++ b/designs/gt2n/snitch_cluster/sram/lef/fakeram7_64x512.lef
@@ -0,0 +1,9522 @@
+VERSION 5.7 ;
+BUSBITCHARS "[]" ;
+MACRO fakeram7_64x512
+  FOREIGN fakeram7_64x512 0 0 ;
+  SYMMETRY X Y R90 ;
+  SIZE 117.390 BY 36.720 ;
+  CLASS BLOCK ;
+  PIN rw0_wd_in[0]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M2 ;
+      RECT 0.000 0.138 0.036 0.150 ;
+    END
+  END rw0_wd_in[0]
+  PIN rw0_wd_in[1]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M2 ;
+      RECT 0.000 0.402 0.036 0.414 ;
+    END
+  END rw0_wd_in[1]
+  PIN rw0_wd_in[2]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M2 ;
+      RECT 0.000 0.666 0.036 0.678 ;
+    END
+  END rw0_wd_in[2]
+  PIN rw0_wd_in[3]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M2 ;
+      RECT 0.000 0.930 0.036 0.942 ;
+    END
+  END rw0_wd_in[3]
+  PIN rw0_wd_in[4]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M2 ;
+      RECT 0.000 1.194 0.036 1.206 ;
+    END
+  END rw0_wd_in[4]
+  PIN rw0_wd_in[5]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M2 ;
+      RECT 0.000 1.458 0.036 1.470 ;
+    END
+  END rw0_wd_in[5]
+  PIN rw0_wd_in[6]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M2 ;
+      RECT 0.000 1.722 0.036 1.734 ;
+    END
+  END rw0_wd_in[6]
+  PIN rw0_wd_in[7]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M2 ;
+      RECT 0.000 1.986 0.036 1.998 ;
+    END
+  END rw0_wd_in[7]
+  PIN rw0_wd_in[8]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M2 ;
+      RECT 0.000 2.250 0.036 2.262 ;
+    END
+  END rw0_wd_in[8]
+  PIN rw0_wd_in[9]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M2 ;
+      RECT 0.000 2.514 0.036 2.526 ;
+    END
+  END rw0_wd_in[9]
+  PIN rw0_wd_in[10]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M2 ;
+      RECT 0.000 2.778 0.036 2.790 ;
+    END
+  END rw0_wd_in[10]
+  PIN rw0_wd_in[11]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M2 ;
+      RECT 0.000 3.042 0.036 3.054 ;
+    END
+  END rw0_wd_in[11]
+  PIN rw0_wd_in[12]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M2 ;
+      RECT 0.000 3.306 0.036 3.318 ;
+    END
+  END rw0_wd_in[12]
+  PIN rw0_wd_in[13]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M2 ;
+      RECT 0.000 3.570 0.036 3.582 ;
+    END
+  END rw0_wd_in[13]
+  PIN rw0_wd_in[14]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M2 ;
+      RECT 0.000 3.834 0.036 3.846 ;
+    END
+  END rw0_wd_in[14]
+  PIN rw0_wd_in[15]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M2 ;
+      RECT 0.000 4.098 0.036 4.110 ;
+    END
+  END rw0_wd_in[15]
+  PIN rw0_wd_in[16]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M2 ;
+      RECT 0.000 4.362 0.036 4.374 ;
+    END
+  END rw0_wd_in[16]
+  PIN rw0_wd_in[17]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M2 ;
+      RECT 0.000 4.626 0.036 4.638 ;
+    END
+  END rw0_wd_in[17]
+  PIN rw0_wd_in[18]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M2 ;
+      RECT 0.000 4.890 0.036 4.902 ;
+    END
+  END rw0_wd_in[18]
+  PIN rw0_wd_in[19]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M2 ;
+      RECT 0.000 5.154 0.036 5.166 ;
+    END
+  END rw0_wd_in[19]
+  PIN rw0_wd_in[20]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M2 ;
+      RECT 0.000 5.418 0.036 5.430 ;
+    END
+  END rw0_wd_in[20]
+  PIN rw0_wd_in[21]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M2 ;
+      RECT 0.000 5.682 0.036 5.694 ;
+    END
+  END rw0_wd_in[21]
+  PIN rw0_wd_in[22]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M2 ;
+      RECT 0.000 5.946 0.036 5.958 ;
+    END
+  END rw0_wd_in[22]
+  PIN rw0_wd_in[23]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M2 ;
+      RECT 0.000 6.210 0.036 6.222 ;
+    END
+  END rw0_wd_in[23]
+  PIN rw0_wd_in[24]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M2 ;
+      RECT 0.000 6.474 0.036 6.486 ;
+    END
+  END rw0_wd_in[24]
+  PIN rw0_wd_in[25]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M2 ;
+      RECT 0.000 6.738 0.036 6.750 ;
+    END
+  END rw0_wd_in[25]
+  PIN rw0_wd_in[26]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M2 ;
+      RECT 0.000 7.002 0.036 7.014 ;
+    END
+  END rw0_wd_in[26]
+  PIN rw0_wd_in[27]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M2 ;
+      RECT 0.000 7.266 0.036 7.278 ;
+    END
+  END rw0_wd_in[27]
+  PIN rw0_wd_in[28]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M2 ;
+      RECT 0.000 7.530 0.036 7.542 ;
+    END
+  END rw0_wd_in[28]
+  PIN rw0_wd_in[29]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M2 ;
+      RECT 0.000 7.794 0.036 7.806 ;
+    END
+  END rw0_wd_in[29]
+  PIN rw0_wd_in[30]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M2 ;
+      RECT 0.000 8.058 0.036 8.070 ;
+    END
+  END rw0_wd_in[30]
+  PIN rw0_wd_in[31]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M2 ;
+      RECT 0.000 8.322 0.036 8.334 ;
+    END
+  END rw0_wd_in[31]
+  PIN rw0_wd_in[32]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M2 ;
+      RECT 0.000 8.586 0.036 8.598 ;
+    END
+  END rw0_wd_in[32]
+  PIN rw0_wd_in[33]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M2 ;
+      RECT 0.000 8.850 0.036 8.862 ;
+    END
+  END rw0_wd_in[33]
+  PIN rw0_wd_in[34]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M2 ;
+      RECT 0.000 9.114 0.036 9.126 ;
+    END
+  END rw0_wd_in[34]
+  PIN rw0_wd_in[35]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M2 ;
+      RECT 0.000 9.378 0.036 9.390 ;
+    END
+  END rw0_wd_in[35]
+  PIN rw0_wd_in[36]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M2 ;
+      RECT 0.000 9.642 0.036 9.654 ;
+    END
+  END rw0_wd_in[36]
+  PIN rw0_wd_in[37]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M2 ;
+      RECT 0.000 9.906 0.036 9.918 ;
+    END
+  END rw0_wd_in[37]
+  PIN rw0_wd_in[38]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M2 ;
+      RECT 0.000 10.170 0.036 10.182 ;
+    END
+  END rw0_wd_in[38]
+  PIN rw0_wd_in[39]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M2 ;
+      RECT 0.000 10.434 0.036 10.446 ;
+    END
+  END rw0_wd_in[39]
+  PIN rw0_wd_in[40]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M2 ;
+      RECT 0.000 10.698 0.036 10.710 ;
+    END
+  END rw0_wd_in[40]
+  PIN rw0_wd_in[41]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M2 ;
+      RECT 0.000 10.962 0.036 10.974 ;
+    END
+  END rw0_wd_in[41]
+  PIN rw0_wd_in[42]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M2 ;
+      RECT 0.000 11.226 0.036 11.238 ;
+    END
+  END rw0_wd_in[42]
+  PIN rw0_wd_in[43]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M2 ;
+      RECT 0.000 11.490 0.036 11.502 ;
+    END
+  END rw0_wd_in[43]
+  PIN rw0_wd_in[44]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M2 ;
+      RECT 0.000 11.754 0.036 11.766 ;
+    END
+  END rw0_wd_in[44]
+  PIN rw0_wd_in[45]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M2 ;
+      RECT 0.000 12.018 0.036 12.030 ;
+    END
+  END rw0_wd_in[45]
+  PIN rw0_wd_in[46]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M2 ;
+      RECT 0.000 12.282 0.036 12.294 ;
+    END
+  END rw0_wd_in[46]
+  PIN rw0_wd_in[47]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M2 ;
+      RECT 0.000 12.546 0.036 12.558 ;
+    END
+  END rw0_wd_in[47]
+  PIN rw0_wd_in[48]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M2 ;
+      RECT 0.000 12.810 0.036 12.822 ;
+    END
+  END rw0_wd_in[48]
+  PIN rw0_wd_in[49]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M2 ;
+      RECT 0.000 13.074 0.036 13.086 ;
+    END
+  END rw0_wd_in[49]
+  PIN rw0_wd_in[50]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M2 ;
+      RECT 0.000 13.338 0.036 13.350 ;
+    END
+  END rw0_wd_in[50]
+  PIN rw0_wd_in[51]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M2 ;
+      RECT 0.000 13.602 0.036 13.614 ;
+    END
+  END rw0_wd_in[51]
+  PIN rw0_wd_in[52]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M2 ;
+      RECT 0.000 13.866 0.036 13.878 ;
+    END
+  END rw0_wd_in[52]
+  PIN rw0_wd_in[53]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M2 ;
+      RECT 0.000 14.130 0.036 14.142 ;
+    END
+  END rw0_wd_in[53]
+  PIN rw0_wd_in[54]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M2 ;
+      RECT 0.000 14.394 0.036 14.406 ;
+    END
+  END rw0_wd_in[54]
+  PIN rw0_wd_in[55]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M2 ;
+      RECT 0.000 14.658 0.036 14.670 ;
+    END
+  END rw0_wd_in[55]
+  PIN rw0_wd_in[56]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M2 ;
+      RECT 0.000 14.922 0.036 14.934 ;
+    END
+  END rw0_wd_in[56]
+  PIN rw0_wd_in[57]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M2 ;
+      RECT 0.000 15.186 0.036 15.198 ;
+    END
+  END rw0_wd_in[57]
+  PIN rw0_wd_in[58]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M2 ;
+      RECT 0.000 15.450 0.036 15.462 ;
+    END
+  END rw0_wd_in[58]
+  PIN rw0_wd_in[59]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M2 ;
+      RECT 0.000 15.714 0.036 15.726 ;
+    END
+  END rw0_wd_in[59]
+  PIN rw0_wd_in[60]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M2 ;
+      RECT 0.000 15.978 0.036 15.990 ;
+    END
+  END rw0_wd_in[60]
+  PIN rw0_wd_in[61]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M2 ;
+      RECT 0.000 16.242 0.036 16.254 ;
+    END
+  END rw0_wd_in[61]
+  PIN rw0_wd_in[62]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M2 ;
+      RECT 0.000 16.506 0.036 16.518 ;
+    END
+  END rw0_wd_in[62]
+  PIN rw0_wd_in[63]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M2 ;
+      RECT 0.000 16.770 0.036 16.782 ;
+    END
+  END rw0_wd_in[63]
+  PIN rw0_wd_in[64]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M2 ;
+      RECT 0.000 17.034 0.036 17.046 ;
+    END
+  END rw0_wd_in[64]
+  PIN rw0_wd_in[65]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M2 ;
+      RECT 0.000 17.298 0.036 17.310 ;
+    END
+  END rw0_wd_in[65]
+  PIN rw0_wd_in[66]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M2 ;
+      RECT 0.000 17.562 0.036 17.574 ;
+    END
+  END rw0_wd_in[66]
+  PIN rw0_wd_in[67]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M2 ;
+      RECT 0.000 17.826 0.036 17.838 ;
+    END
+  END rw0_wd_in[67]
+  PIN rw0_wd_in[68]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M2 ;
+      RECT 0.000 18.090 0.036 18.102 ;
+    END
+  END rw0_wd_in[68]
+  PIN rw0_wd_in[69]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M2 ;
+      RECT 0.000 18.354 0.036 18.366 ;
+    END
+  END rw0_wd_in[69]
+  PIN rw0_wd_in[70]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M2 ;
+      RECT 0.000 18.618 0.036 18.630 ;
+    END
+  END rw0_wd_in[70]
+  PIN rw0_wd_in[71]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M2 ;
+      RECT 0.000 18.882 0.036 18.894 ;
+    END
+  END rw0_wd_in[71]
+  PIN rw0_wd_in[72]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M2 ;
+      RECT 0.000 19.146 0.036 19.158 ;
+    END
+  END rw0_wd_in[72]
+  PIN rw0_wd_in[73]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M2 ;
+      RECT 0.000 19.410 0.036 19.422 ;
+    END
+  END rw0_wd_in[73]
+  PIN rw0_wd_in[74]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M2 ;
+      RECT 0.000 19.674 0.036 19.686 ;
+    END
+  END rw0_wd_in[74]
+  PIN rw0_wd_in[75]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M2 ;
+      RECT 0.000 19.938 0.036 19.950 ;
+    END
+  END rw0_wd_in[75]
+  PIN rw0_wd_in[76]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M2 ;
+      RECT 0.000 20.202 0.036 20.214 ;
+    END
+  END rw0_wd_in[76]
+  PIN rw0_wd_in[77]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M2 ;
+      RECT 0.000 20.466 0.036 20.478 ;
+    END
+  END rw0_wd_in[77]
+  PIN rw0_wd_in[78]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M2 ;
+      RECT 0.000 20.730 0.036 20.742 ;
+    END
+  END rw0_wd_in[78]
+  PIN rw0_wd_in[79]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M2 ;
+      RECT 0.000 20.994 0.036 21.006 ;
+    END
+  END rw0_wd_in[79]
+  PIN rw0_wd_in[80]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M2 ;
+      RECT 0.000 21.258 0.036 21.270 ;
+    END
+  END rw0_wd_in[80]
+  PIN rw0_wd_in[81]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M2 ;
+      RECT 0.000 21.522 0.036 21.534 ;
+    END
+  END rw0_wd_in[81]
+  PIN rw0_wd_in[82]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M2 ;
+      RECT 0.000 21.786 0.036 21.798 ;
+    END
+  END rw0_wd_in[82]
+  PIN rw0_wd_in[83]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M2 ;
+      RECT 0.000 22.050 0.036 22.062 ;
+    END
+  END rw0_wd_in[83]
+  PIN rw0_wd_in[84]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M2 ;
+      RECT 0.000 22.314 0.036 22.326 ;
+    END
+  END rw0_wd_in[84]
+  PIN rw0_wd_in[85]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M2 ;
+      RECT 0.000 22.578 0.036 22.590 ;
+    END
+  END rw0_wd_in[85]
+  PIN rw0_wd_in[86]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M2 ;
+      RECT 0.000 22.842 0.036 22.854 ;
+    END
+  END rw0_wd_in[86]
+  PIN rw0_wd_in[87]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M2 ;
+      RECT 0.000 23.106 0.036 23.118 ;
+    END
+  END rw0_wd_in[87]
+  PIN rw0_wd_in[88]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M2 ;
+      RECT 0.000 23.370 0.036 23.382 ;
+    END
+  END rw0_wd_in[88]
+  PIN rw0_wd_in[89]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M2 ;
+      RECT 0.000 23.634 0.036 23.646 ;
+    END
+  END rw0_wd_in[89]
+  PIN rw0_wd_in[90]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M2 ;
+      RECT 0.000 23.898 0.036 23.910 ;
+    END
+  END rw0_wd_in[90]
+  PIN rw0_wd_in[91]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M2 ;
+      RECT 0.000 24.162 0.036 24.174 ;
+    END
+  END rw0_wd_in[91]
+  PIN rw0_wd_in[92]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M2 ;
+      RECT 0.000 24.426 0.036 24.438 ;
+    END
+  END rw0_wd_in[92]
+  PIN rw0_wd_in[93]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M2 ;
+      RECT 0.000 24.690 0.036 24.702 ;
+    END
+  END rw0_wd_in[93]
+  PIN rw0_wd_in[94]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M2 ;
+      RECT 0.000 24.954 0.036 24.966 ;
+    END
+  END rw0_wd_in[94]
+  PIN rw0_wd_in[95]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M2 ;
+      RECT 0.000 25.218 0.036 25.230 ;
+    END
+  END rw0_wd_in[95]
+  PIN rw0_wd_in[96]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M2 ;
+      RECT 0.000 25.482 0.036 25.494 ;
+    END
+  END rw0_wd_in[96]
+  PIN rw0_wd_in[97]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M2 ;
+      RECT 0.000 25.746 0.036 25.758 ;
+    END
+  END rw0_wd_in[97]
+  PIN rw0_wd_in[98]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M2 ;
+      RECT 0.000 26.010 0.036 26.022 ;
+    END
+  END rw0_wd_in[98]
+  PIN rw0_wd_in[99]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M2 ;
+      RECT 0.000 26.274 0.036 26.286 ;
+    END
+  END rw0_wd_in[99]
+  PIN rw0_wd_in[100]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M2 ;
+      RECT 0.000 26.538 0.036 26.550 ;
+    END
+  END rw0_wd_in[100]
+  PIN rw0_wd_in[101]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M2 ;
+      RECT 0.000 26.802 0.036 26.814 ;
+    END
+  END rw0_wd_in[101]
+  PIN rw0_wd_in[102]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M2 ;
+      RECT 0.000 27.066 0.036 27.078 ;
+    END
+  END rw0_wd_in[102]
+  PIN rw0_wd_in[103]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M2 ;
+      RECT 0.000 27.330 0.036 27.342 ;
+    END
+  END rw0_wd_in[103]
+  PIN rw0_wd_in[104]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M2 ;
+      RECT 0.000 27.594 0.036 27.606 ;
+    END
+  END rw0_wd_in[104]
+  PIN rw0_wd_in[105]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M2 ;
+      RECT 0.000 27.858 0.036 27.870 ;
+    END
+  END rw0_wd_in[105]
+  PIN rw0_wd_in[106]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M2 ;
+      RECT 0.000 28.122 0.036 28.134 ;
+    END
+  END rw0_wd_in[106]
+  PIN rw0_wd_in[107]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M2 ;
+      RECT 0.000 28.386 0.036 28.398 ;
+    END
+  END rw0_wd_in[107]
+  PIN rw0_wd_in[108]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M2 ;
+      RECT 0.000 28.650 0.036 28.662 ;
+    END
+  END rw0_wd_in[108]
+  PIN rw0_wd_in[109]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M2 ;
+      RECT 0.000 28.914 0.036 28.926 ;
+    END
+  END rw0_wd_in[109]
+  PIN rw0_wd_in[110]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M2 ;
+      RECT 0.000 29.178 0.036 29.190 ;
+    END
+  END rw0_wd_in[110]
+  PIN rw0_wd_in[111]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M2 ;
+      RECT 0.000 29.442 0.036 29.454 ;
+    END
+  END rw0_wd_in[111]
+  PIN rw0_wd_in[112]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M2 ;
+      RECT 0.000 29.706 0.036 29.718 ;
+    END
+  END rw0_wd_in[112]
+  PIN rw0_wd_in[113]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M2 ;
+      RECT 0.000 29.970 0.036 29.982 ;
+    END
+  END rw0_wd_in[113]
+  PIN rw0_wd_in[114]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M2 ;
+      RECT 0.000 30.234 0.036 30.246 ;
+    END
+  END rw0_wd_in[114]
+  PIN rw0_wd_in[115]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M2 ;
+      RECT 0.000 30.498 0.036 30.510 ;
+    END
+  END rw0_wd_in[115]
+  PIN rw0_wd_in[116]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M2 ;
+      RECT 0.000 30.762 0.036 30.774 ;
+    END
+  END rw0_wd_in[116]
+  PIN rw0_wd_in[117]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M2 ;
+      RECT 0.000 31.026 0.036 31.038 ;
+    END
+  END rw0_wd_in[117]
+  PIN rw0_wd_in[118]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M2 ;
+      RECT 0.000 31.290 0.036 31.302 ;
+    END
+  END rw0_wd_in[118]
+  PIN rw0_wd_in[119]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M2 ;
+      RECT 0.000 31.554 0.036 31.566 ;
+    END
+  END rw0_wd_in[119]
+  PIN rw0_wd_in[120]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M2 ;
+      RECT 0.000 31.818 0.036 31.830 ;
+    END
+  END rw0_wd_in[120]
+  PIN rw0_wd_in[121]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M2 ;
+      RECT 0.000 32.082 0.036 32.094 ;
+    END
+  END rw0_wd_in[121]
+  PIN rw0_wd_in[122]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M2 ;
+      RECT 0.000 32.346 0.036 32.358 ;
+    END
+  END rw0_wd_in[122]
+  PIN rw0_wd_in[123]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M2 ;
+      RECT 0.000 32.610 0.036 32.622 ;
+    END
+  END rw0_wd_in[123]
+  PIN rw0_wd_in[124]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M2 ;
+      RECT 0.000 32.874 0.036 32.886 ;
+    END
+  END rw0_wd_in[124]
+  PIN rw0_wd_in[125]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M2 ;
+      RECT 0.000 33.138 0.036 33.150 ;
+    END
+  END rw0_wd_in[125]
+  PIN rw0_wd_in[126]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M2 ;
+      RECT 0.000 33.402 0.036 33.414 ;
+    END
+  END rw0_wd_in[126]
+  PIN rw0_wd_in[127]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M2 ;
+      RECT 0.000 33.666 0.036 33.678 ;
+    END
+  END rw0_wd_in[127]
+  PIN rw0_wd_in[128]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M2 ;
+      RECT 117.354 0.138 117.390 0.150 ;
+    END
+  END rw0_wd_in[128]
+  PIN rw0_wd_in[129]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M2 ;
+      RECT 117.354 0.402 117.390 0.414 ;
+    END
+  END rw0_wd_in[129]
+  PIN rw0_wd_in[130]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M2 ;
+      RECT 117.354 0.666 117.390 0.678 ;
+    END
+  END rw0_wd_in[130]
+  PIN rw0_wd_in[131]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M2 ;
+      RECT 117.354 0.930 117.390 0.942 ;
+    END
+  END rw0_wd_in[131]
+  PIN rw0_wd_in[132]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M2 ;
+      RECT 117.354 1.194 117.390 1.206 ;
+    END
+  END rw0_wd_in[132]
+  PIN rw0_wd_in[133]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M2 ;
+      RECT 117.354 1.458 117.390 1.470 ;
+    END
+  END rw0_wd_in[133]
+  PIN rw0_wd_in[134]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M2 ;
+      RECT 117.354 1.722 117.390 1.734 ;
+    END
+  END rw0_wd_in[134]
+  PIN rw0_wd_in[135]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M2 ;
+      RECT 117.354 1.986 117.390 1.998 ;
+    END
+  END rw0_wd_in[135]
+  PIN rw0_wd_in[136]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M2 ;
+      RECT 117.354 2.250 117.390 2.262 ;
+    END
+  END rw0_wd_in[136]
+  PIN rw0_wd_in[137]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M2 ;
+      RECT 117.354 2.514 117.390 2.526 ;
+    END
+  END rw0_wd_in[137]
+  PIN rw0_wd_in[138]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M2 ;
+      RECT 117.354 2.778 117.390 2.790 ;
+    END
+  END rw0_wd_in[138]
+  PIN rw0_wd_in[139]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M2 ;
+      RECT 117.354 3.042 117.390 3.054 ;
+    END
+  END rw0_wd_in[139]
+  PIN rw0_wd_in[140]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M2 ;
+      RECT 117.354 3.306 117.390 3.318 ;
+    END
+  END rw0_wd_in[140]
+  PIN rw0_wd_in[141]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M2 ;
+      RECT 117.354 3.570 117.390 3.582 ;
+    END
+  END rw0_wd_in[141]
+  PIN rw0_wd_in[142]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M2 ;
+      RECT 117.354 3.834 117.390 3.846 ;
+    END
+  END rw0_wd_in[142]
+  PIN rw0_wd_in[143]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M2 ;
+      RECT 117.354 4.098 117.390 4.110 ;
+    END
+  END rw0_wd_in[143]
+  PIN rw0_wd_in[144]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M2 ;
+      RECT 117.354 4.362 117.390 4.374 ;
+    END
+  END rw0_wd_in[144]
+  PIN rw0_wd_in[145]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M2 ;
+      RECT 117.354 4.626 117.390 4.638 ;
+    END
+  END rw0_wd_in[145]
+  PIN rw0_wd_in[146]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M2 ;
+      RECT 117.354 4.890 117.390 4.902 ;
+    END
+  END rw0_wd_in[146]
+  PIN rw0_wd_in[147]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M2 ;
+      RECT 117.354 5.154 117.390 5.166 ;
+    END
+  END rw0_wd_in[147]
+  PIN rw0_wd_in[148]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M2 ;
+      RECT 117.354 5.418 117.390 5.430 ;
+    END
+  END rw0_wd_in[148]
+  PIN rw0_wd_in[149]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M2 ;
+      RECT 117.354 5.682 117.390 5.694 ;
+    END
+  END rw0_wd_in[149]
+  PIN rw0_wd_in[150]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M2 ;
+      RECT 117.354 5.946 117.390 5.958 ;
+    END
+  END rw0_wd_in[150]
+  PIN rw0_wd_in[151]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M2 ;
+      RECT 117.354 6.210 117.390 6.222 ;
+    END
+  END rw0_wd_in[151]
+  PIN rw0_wd_in[152]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M2 ;
+      RECT 117.354 6.474 117.390 6.486 ;
+    END
+  END rw0_wd_in[152]
+  PIN rw0_wd_in[153]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M2 ;
+      RECT 117.354 6.738 117.390 6.750 ;
+    END
+  END rw0_wd_in[153]
+  PIN rw0_wd_in[154]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M2 ;
+      RECT 117.354 7.002 117.390 7.014 ;
+    END
+  END rw0_wd_in[154]
+  PIN rw0_wd_in[155]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M2 ;
+      RECT 117.354 7.266 117.390 7.278 ;
+    END
+  END rw0_wd_in[155]
+  PIN rw0_wd_in[156]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M2 ;
+      RECT 117.354 7.530 117.390 7.542 ;
+    END
+  END rw0_wd_in[156]
+  PIN rw0_wd_in[157]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M2 ;
+      RECT 117.354 7.794 117.390 7.806 ;
+    END
+  END rw0_wd_in[157]
+  PIN rw0_wd_in[158]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M2 ;
+      RECT 117.354 8.058 117.390 8.070 ;
+    END
+  END rw0_wd_in[158]
+  PIN rw0_wd_in[159]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M2 ;
+      RECT 117.354 8.322 117.390 8.334 ;
+    END
+  END rw0_wd_in[159]
+  PIN rw0_wd_in[160]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M2 ;
+      RECT 117.354 8.586 117.390 8.598 ;
+    END
+  END rw0_wd_in[160]
+  PIN rw0_wd_in[161]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M2 ;
+      RECT 117.354 8.850 117.390 8.862 ;
+    END
+  END rw0_wd_in[161]
+  PIN rw0_wd_in[162]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M2 ;
+      RECT 117.354 9.114 117.390 9.126 ;
+    END
+  END rw0_wd_in[162]
+  PIN rw0_wd_in[163]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M2 ;
+      RECT 117.354 9.378 117.390 9.390 ;
+    END
+  END rw0_wd_in[163]
+  PIN rw0_wd_in[164]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M2 ;
+      RECT 117.354 9.642 117.390 9.654 ;
+    END
+  END rw0_wd_in[164]
+  PIN rw0_wd_in[165]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M2 ;
+      RECT 117.354 9.906 117.390 9.918 ;
+    END
+  END rw0_wd_in[165]
+  PIN rw0_wd_in[166]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M2 ;
+      RECT 117.354 10.170 117.390 10.182 ;
+    END
+  END rw0_wd_in[166]
+  PIN rw0_wd_in[167]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M2 ;
+      RECT 117.354 10.434 117.390 10.446 ;
+    END
+  END rw0_wd_in[167]
+  PIN rw0_wd_in[168]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M2 ;
+      RECT 117.354 10.698 117.390 10.710 ;
+    END
+  END rw0_wd_in[168]
+  PIN rw0_wd_in[169]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M2 ;
+      RECT 117.354 10.962 117.390 10.974 ;
+    END
+  END rw0_wd_in[169]
+  PIN rw0_wd_in[170]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M2 ;
+      RECT 117.354 11.226 117.390 11.238 ;
+    END
+  END rw0_wd_in[170]
+  PIN rw0_wd_in[171]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M2 ;
+      RECT 117.354 11.490 117.390 11.502 ;
+    END
+  END rw0_wd_in[171]
+  PIN rw0_wd_in[172]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M2 ;
+      RECT 117.354 11.754 117.390 11.766 ;
+    END
+  END rw0_wd_in[172]
+  PIN rw0_wd_in[173]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M2 ;
+      RECT 117.354 12.018 117.390 12.030 ;
+    END
+  END rw0_wd_in[173]
+  PIN rw0_wd_in[174]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M2 ;
+      RECT 117.354 12.282 117.390 12.294 ;
+    END
+  END rw0_wd_in[174]
+  PIN rw0_wd_in[175]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M2 ;
+      RECT 117.354 12.546 117.390 12.558 ;
+    END
+  END rw0_wd_in[175]
+  PIN rw0_wd_in[176]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M2 ;
+      RECT 117.354 12.810 117.390 12.822 ;
+    END
+  END rw0_wd_in[176]
+  PIN rw0_wd_in[177]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M2 ;
+      RECT 117.354 13.074 117.390 13.086 ;
+    END
+  END rw0_wd_in[177]
+  PIN rw0_wd_in[178]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M2 ;
+      RECT 117.354 13.338 117.390 13.350 ;
+    END
+  END rw0_wd_in[178]
+  PIN rw0_wd_in[179]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M2 ;
+      RECT 117.354 13.602 117.390 13.614 ;
+    END
+  END rw0_wd_in[179]
+  PIN rw0_wd_in[180]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M2 ;
+      RECT 117.354 13.866 117.390 13.878 ;
+    END
+  END rw0_wd_in[180]
+  PIN rw0_wd_in[181]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M2 ;
+      RECT 117.354 14.130 117.390 14.142 ;
+    END
+  END rw0_wd_in[181]
+  PIN rw0_wd_in[182]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M2 ;
+      RECT 117.354 14.394 117.390 14.406 ;
+    END
+  END rw0_wd_in[182]
+  PIN rw0_wd_in[183]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M2 ;
+      RECT 117.354 14.658 117.390 14.670 ;
+    END
+  END rw0_wd_in[183]
+  PIN rw0_wd_in[184]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M2 ;
+      RECT 117.354 14.922 117.390 14.934 ;
+    END
+  END rw0_wd_in[184]
+  PIN rw0_wd_in[185]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M2 ;
+      RECT 117.354 15.186 117.390 15.198 ;
+    END
+  END rw0_wd_in[185]
+  PIN rw0_wd_in[186]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M2 ;
+      RECT 117.354 15.450 117.390 15.462 ;
+    END
+  END rw0_wd_in[186]
+  PIN rw0_wd_in[187]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M2 ;
+      RECT 117.354 15.714 117.390 15.726 ;
+    END
+  END rw0_wd_in[187]
+  PIN rw0_wd_in[188]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M2 ;
+      RECT 117.354 15.978 117.390 15.990 ;
+    END
+  END rw0_wd_in[188]
+  PIN rw0_wd_in[189]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M2 ;
+      RECT 117.354 16.242 117.390 16.254 ;
+    END
+  END rw0_wd_in[189]
+  PIN rw0_wd_in[190]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M2 ;
+      RECT 117.354 16.506 117.390 16.518 ;
+    END
+  END rw0_wd_in[190]
+  PIN rw0_wd_in[191]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M2 ;
+      RECT 117.354 16.770 117.390 16.782 ;
+    END
+  END rw0_wd_in[191]
+  PIN rw0_wd_in[192]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M2 ;
+      RECT 117.354 17.034 117.390 17.046 ;
+    END
+  END rw0_wd_in[192]
+  PIN rw0_wd_in[193]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M2 ;
+      RECT 117.354 17.298 117.390 17.310 ;
+    END
+  END rw0_wd_in[193]
+  PIN rw0_wd_in[194]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M2 ;
+      RECT 117.354 17.562 117.390 17.574 ;
+    END
+  END rw0_wd_in[194]
+  PIN rw0_wd_in[195]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M2 ;
+      RECT 117.354 17.826 117.390 17.838 ;
+    END
+  END rw0_wd_in[195]
+  PIN rw0_wd_in[196]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M2 ;
+      RECT 117.354 18.090 117.390 18.102 ;
+    END
+  END rw0_wd_in[196]
+  PIN rw0_wd_in[197]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M2 ;
+      RECT 117.354 18.354 117.390 18.366 ;
+    END
+  END rw0_wd_in[197]
+  PIN rw0_wd_in[198]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M2 ;
+      RECT 117.354 18.618 117.390 18.630 ;
+    END
+  END rw0_wd_in[198]
+  PIN rw0_wd_in[199]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M2 ;
+      RECT 117.354 18.882 117.390 18.894 ;
+    END
+  END rw0_wd_in[199]
+  PIN rw0_wd_in[200]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M2 ;
+      RECT 117.354 19.146 117.390 19.158 ;
+    END
+  END rw0_wd_in[200]
+  PIN rw0_wd_in[201]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M2 ;
+      RECT 117.354 19.410 117.390 19.422 ;
+    END
+  END rw0_wd_in[201]
+  PIN rw0_wd_in[202]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M2 ;
+      RECT 117.354 19.674 117.390 19.686 ;
+    END
+  END rw0_wd_in[202]
+  PIN rw0_wd_in[203]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M2 ;
+      RECT 117.354 19.938 117.390 19.950 ;
+    END
+  END rw0_wd_in[203]
+  PIN rw0_wd_in[204]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M2 ;
+      RECT 117.354 20.202 117.390 20.214 ;
+    END
+  END rw0_wd_in[204]
+  PIN rw0_wd_in[205]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M2 ;
+      RECT 117.354 20.466 117.390 20.478 ;
+    END
+  END rw0_wd_in[205]
+  PIN rw0_wd_in[206]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M2 ;
+      RECT 117.354 20.730 117.390 20.742 ;
+    END
+  END rw0_wd_in[206]
+  PIN rw0_wd_in[207]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M2 ;
+      RECT 117.354 20.994 117.390 21.006 ;
+    END
+  END rw0_wd_in[207]
+  PIN rw0_wd_in[208]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M2 ;
+      RECT 117.354 21.258 117.390 21.270 ;
+    END
+  END rw0_wd_in[208]
+  PIN rw0_wd_in[209]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M2 ;
+      RECT 117.354 21.522 117.390 21.534 ;
+    END
+  END rw0_wd_in[209]
+  PIN rw0_wd_in[210]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M2 ;
+      RECT 117.354 21.786 117.390 21.798 ;
+    END
+  END rw0_wd_in[210]
+  PIN rw0_wd_in[211]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M2 ;
+      RECT 117.354 22.050 117.390 22.062 ;
+    END
+  END rw0_wd_in[211]
+  PIN rw0_wd_in[212]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M2 ;
+      RECT 117.354 22.314 117.390 22.326 ;
+    END
+  END rw0_wd_in[212]
+  PIN rw0_wd_in[213]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M2 ;
+      RECT 117.354 22.578 117.390 22.590 ;
+    END
+  END rw0_wd_in[213]
+  PIN rw0_wd_in[214]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M2 ;
+      RECT 117.354 22.842 117.390 22.854 ;
+    END
+  END rw0_wd_in[214]
+  PIN rw0_wd_in[215]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M2 ;
+      RECT 117.354 23.106 117.390 23.118 ;
+    END
+  END rw0_wd_in[215]
+  PIN rw0_wd_in[216]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M2 ;
+      RECT 117.354 23.370 117.390 23.382 ;
+    END
+  END rw0_wd_in[216]
+  PIN rw0_wd_in[217]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M2 ;
+      RECT 117.354 23.634 117.390 23.646 ;
+    END
+  END rw0_wd_in[217]
+  PIN rw0_wd_in[218]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M2 ;
+      RECT 117.354 23.898 117.390 23.910 ;
+    END
+  END rw0_wd_in[218]
+  PIN rw0_wd_in[219]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M2 ;
+      RECT 117.354 24.162 117.390 24.174 ;
+    END
+  END rw0_wd_in[219]
+  PIN rw0_wd_in[220]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M2 ;
+      RECT 117.354 24.426 117.390 24.438 ;
+    END
+  END rw0_wd_in[220]
+  PIN rw0_wd_in[221]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M2 ;
+      RECT 117.354 24.690 117.390 24.702 ;
+    END
+  END rw0_wd_in[221]
+  PIN rw0_wd_in[222]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M2 ;
+      RECT 117.354 24.954 117.390 24.966 ;
+    END
+  END rw0_wd_in[222]
+  PIN rw0_wd_in[223]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M2 ;
+      RECT 117.354 25.218 117.390 25.230 ;
+    END
+  END rw0_wd_in[223]
+  PIN rw0_wd_in[224]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M2 ;
+      RECT 117.354 25.482 117.390 25.494 ;
+    END
+  END rw0_wd_in[224]
+  PIN rw0_wd_in[225]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M2 ;
+      RECT 117.354 25.746 117.390 25.758 ;
+    END
+  END rw0_wd_in[225]
+  PIN rw0_wd_in[226]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M2 ;
+      RECT 117.354 26.010 117.390 26.022 ;
+    END
+  END rw0_wd_in[226]
+  PIN rw0_wd_in[227]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M2 ;
+      RECT 117.354 26.274 117.390 26.286 ;
+    END
+  END rw0_wd_in[227]
+  PIN rw0_wd_in[228]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M2 ;
+      RECT 117.354 26.538 117.390 26.550 ;
+    END
+  END rw0_wd_in[228]
+  PIN rw0_wd_in[229]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M2 ;
+      RECT 117.354 26.802 117.390 26.814 ;
+    END
+  END rw0_wd_in[229]
+  PIN rw0_wd_in[230]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M2 ;
+      RECT 117.354 27.066 117.390 27.078 ;
+    END
+  END rw0_wd_in[230]
+  PIN rw0_wd_in[231]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M2 ;
+      RECT 117.354 27.330 117.390 27.342 ;
+    END
+  END rw0_wd_in[231]
+  PIN rw0_wd_in[232]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M2 ;
+      RECT 117.354 27.594 117.390 27.606 ;
+    END
+  END rw0_wd_in[232]
+  PIN rw0_wd_in[233]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M2 ;
+      RECT 117.354 27.858 117.390 27.870 ;
+    END
+  END rw0_wd_in[233]
+  PIN rw0_wd_in[234]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M2 ;
+      RECT 117.354 28.122 117.390 28.134 ;
+    END
+  END rw0_wd_in[234]
+  PIN rw0_wd_in[235]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M2 ;
+      RECT 117.354 28.386 117.390 28.398 ;
+    END
+  END rw0_wd_in[235]
+  PIN rw0_wd_in[236]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M2 ;
+      RECT 117.354 28.650 117.390 28.662 ;
+    END
+  END rw0_wd_in[236]
+  PIN rw0_wd_in[237]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M2 ;
+      RECT 117.354 28.914 117.390 28.926 ;
+    END
+  END rw0_wd_in[237]
+  PIN rw0_wd_in[238]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M2 ;
+      RECT 117.354 29.178 117.390 29.190 ;
+    END
+  END rw0_wd_in[238]
+  PIN rw0_wd_in[239]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M2 ;
+      RECT 117.354 29.442 117.390 29.454 ;
+    END
+  END rw0_wd_in[239]
+  PIN rw0_wd_in[240]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M2 ;
+      RECT 117.354 29.706 117.390 29.718 ;
+    END
+  END rw0_wd_in[240]
+  PIN rw0_wd_in[241]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M2 ;
+      RECT 117.354 29.970 117.390 29.982 ;
+    END
+  END rw0_wd_in[241]
+  PIN rw0_wd_in[242]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M2 ;
+      RECT 117.354 30.234 117.390 30.246 ;
+    END
+  END rw0_wd_in[242]
+  PIN rw0_wd_in[243]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M2 ;
+      RECT 117.354 30.498 117.390 30.510 ;
+    END
+  END rw0_wd_in[243]
+  PIN rw0_wd_in[244]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M2 ;
+      RECT 117.354 30.762 117.390 30.774 ;
+    END
+  END rw0_wd_in[244]
+  PIN rw0_wd_in[245]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M2 ;
+      RECT 117.354 31.026 117.390 31.038 ;
+    END
+  END rw0_wd_in[245]
+  PIN rw0_wd_in[246]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M2 ;
+      RECT 117.354 31.290 117.390 31.302 ;
+    END
+  END rw0_wd_in[246]
+  PIN rw0_wd_in[247]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M2 ;
+      RECT 117.354 31.554 117.390 31.566 ;
+    END
+  END rw0_wd_in[247]
+  PIN rw0_wd_in[248]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M2 ;
+      RECT 117.354 31.818 117.390 31.830 ;
+    END
+  END rw0_wd_in[248]
+  PIN rw0_wd_in[249]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M2 ;
+      RECT 117.354 32.082 117.390 32.094 ;
+    END
+  END rw0_wd_in[249]
+  PIN rw0_wd_in[250]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M2 ;
+      RECT 117.354 32.346 117.390 32.358 ;
+    END
+  END rw0_wd_in[250]
+  PIN rw0_wd_in[251]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M2 ;
+      RECT 117.354 32.610 117.390 32.622 ;
+    END
+  END rw0_wd_in[251]
+  PIN rw0_wd_in[252]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M2 ;
+      RECT 117.354 32.874 117.390 32.886 ;
+    END
+  END rw0_wd_in[252]
+  PIN rw0_wd_in[253]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M2 ;
+      RECT 117.354 33.138 117.390 33.150 ;
+    END
+  END rw0_wd_in[253]
+  PIN rw0_wd_in[254]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M2 ;
+      RECT 117.354 33.402 117.390 33.414 ;
+    END
+  END rw0_wd_in[254]
+  PIN rw0_wd_in[255]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M2 ;
+      RECT 117.354 33.666 117.390 33.678 ;
+    END
+  END rw0_wd_in[255]
+  PIN rw0_wd_in[256]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 0.161 0.000 0.175 0.042 ;
+    END
+  END rw0_wd_in[256]
+  PIN rw0_wd_in[257]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 0.385 0.000 0.399 0.042 ;
+    END
+  END rw0_wd_in[257]
+  PIN rw0_wd_in[258]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 0.609 0.000 0.623 0.042 ;
+    END
+  END rw0_wd_in[258]
+  PIN rw0_wd_in[259]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 0.833 0.000 0.847 0.042 ;
+    END
+  END rw0_wd_in[259]
+  PIN rw0_wd_in[260]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 1.057 0.000 1.071 0.042 ;
+    END
+  END rw0_wd_in[260]
+  PIN rw0_wd_in[261]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 1.281 0.000 1.295 0.042 ;
+    END
+  END rw0_wd_in[261]
+  PIN rw0_wd_in[262]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 1.505 0.000 1.519 0.042 ;
+    END
+  END rw0_wd_in[262]
+  PIN rw0_wd_in[263]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 1.729 0.000 1.743 0.042 ;
+    END
+  END rw0_wd_in[263]
+  PIN rw0_wd_in[264]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 1.953 0.000 1.967 0.042 ;
+    END
+  END rw0_wd_in[264]
+  PIN rw0_wd_in[265]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 2.177 0.000 2.191 0.042 ;
+    END
+  END rw0_wd_in[265]
+  PIN rw0_wd_in[266]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 2.401 0.000 2.415 0.042 ;
+    END
+  END rw0_wd_in[266]
+  PIN rw0_wd_in[267]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 2.625 0.000 2.639 0.042 ;
+    END
+  END rw0_wd_in[267]
+  PIN rw0_wd_in[268]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 2.849 0.000 2.863 0.042 ;
+    END
+  END rw0_wd_in[268]
+  PIN rw0_wd_in[269]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 3.073 0.000 3.087 0.042 ;
+    END
+  END rw0_wd_in[269]
+  PIN rw0_wd_in[270]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 3.297 0.000 3.311 0.042 ;
+    END
+  END rw0_wd_in[270]
+  PIN rw0_wd_in[271]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 3.521 0.000 3.535 0.042 ;
+    END
+  END rw0_wd_in[271]
+  PIN rw0_wd_in[272]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 3.745 0.000 3.759 0.042 ;
+    END
+  END rw0_wd_in[272]
+  PIN rw0_wd_in[273]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 3.969 0.000 3.983 0.042 ;
+    END
+  END rw0_wd_in[273]
+  PIN rw0_wd_in[274]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 4.193 0.000 4.207 0.042 ;
+    END
+  END rw0_wd_in[274]
+  PIN rw0_wd_in[275]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 4.417 0.000 4.431 0.042 ;
+    END
+  END rw0_wd_in[275]
+  PIN rw0_wd_in[276]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 4.641 0.000 4.655 0.042 ;
+    END
+  END rw0_wd_in[276]
+  PIN rw0_wd_in[277]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 4.865 0.000 4.879 0.042 ;
+    END
+  END rw0_wd_in[277]
+  PIN rw0_wd_in[278]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 5.089 0.000 5.103 0.042 ;
+    END
+  END rw0_wd_in[278]
+  PIN rw0_wd_in[279]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 5.313 0.000 5.327 0.042 ;
+    END
+  END rw0_wd_in[279]
+  PIN rw0_wd_in[280]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 5.537 0.000 5.551 0.042 ;
+    END
+  END rw0_wd_in[280]
+  PIN rw0_wd_in[281]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 5.761 0.000 5.775 0.042 ;
+    END
+  END rw0_wd_in[281]
+  PIN rw0_wd_in[282]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 5.985 0.000 5.999 0.042 ;
+    END
+  END rw0_wd_in[282]
+  PIN rw0_wd_in[283]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 6.209 0.000 6.223 0.042 ;
+    END
+  END rw0_wd_in[283]
+  PIN rw0_wd_in[284]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 6.433 0.000 6.447 0.042 ;
+    END
+  END rw0_wd_in[284]
+  PIN rw0_wd_in[285]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 6.657 0.000 6.671 0.042 ;
+    END
+  END rw0_wd_in[285]
+  PIN rw0_wd_in[286]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 6.881 0.000 6.895 0.042 ;
+    END
+  END rw0_wd_in[286]
+  PIN rw0_wd_in[287]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 7.105 0.000 7.119 0.042 ;
+    END
+  END rw0_wd_in[287]
+  PIN rw0_wd_in[288]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 7.329 0.000 7.343 0.042 ;
+    END
+  END rw0_wd_in[288]
+  PIN rw0_wd_in[289]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 7.553 0.000 7.567 0.042 ;
+    END
+  END rw0_wd_in[289]
+  PIN rw0_wd_in[290]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 7.777 0.000 7.791 0.042 ;
+    END
+  END rw0_wd_in[290]
+  PIN rw0_wd_in[291]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 8.001 0.000 8.015 0.042 ;
+    END
+  END rw0_wd_in[291]
+  PIN rw0_wd_in[292]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 8.225 0.000 8.239 0.042 ;
+    END
+  END rw0_wd_in[292]
+  PIN rw0_wd_in[293]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 8.449 0.000 8.463 0.042 ;
+    END
+  END rw0_wd_in[293]
+  PIN rw0_wd_in[294]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 8.673 0.000 8.687 0.042 ;
+    END
+  END rw0_wd_in[294]
+  PIN rw0_wd_in[295]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 8.897 0.000 8.911 0.042 ;
+    END
+  END rw0_wd_in[295]
+  PIN rw0_wd_in[296]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 9.121 0.000 9.135 0.042 ;
+    END
+  END rw0_wd_in[296]
+  PIN rw0_wd_in[297]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 9.345 0.000 9.359 0.042 ;
+    END
+  END rw0_wd_in[297]
+  PIN rw0_wd_in[298]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 9.569 0.000 9.583 0.042 ;
+    END
+  END rw0_wd_in[298]
+  PIN rw0_wd_in[299]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 9.793 0.000 9.807 0.042 ;
+    END
+  END rw0_wd_in[299]
+  PIN rw0_wd_in[300]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 10.017 0.000 10.031 0.042 ;
+    END
+  END rw0_wd_in[300]
+  PIN rw0_wd_in[301]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 10.241 0.000 10.255 0.042 ;
+    END
+  END rw0_wd_in[301]
+  PIN rw0_wd_in[302]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 10.465 0.000 10.479 0.042 ;
+    END
+  END rw0_wd_in[302]
+  PIN rw0_wd_in[303]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 10.689 0.000 10.703 0.042 ;
+    END
+  END rw0_wd_in[303]
+  PIN rw0_wd_in[304]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 10.913 0.000 10.927 0.042 ;
+    END
+  END rw0_wd_in[304]
+  PIN rw0_wd_in[305]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 11.137 0.000 11.151 0.042 ;
+    END
+  END rw0_wd_in[305]
+  PIN rw0_wd_in[306]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 11.361 0.000 11.375 0.042 ;
+    END
+  END rw0_wd_in[306]
+  PIN rw0_wd_in[307]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 11.585 0.000 11.599 0.042 ;
+    END
+  END rw0_wd_in[307]
+  PIN rw0_wd_in[308]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 11.809 0.000 11.823 0.042 ;
+    END
+  END rw0_wd_in[308]
+  PIN rw0_wd_in[309]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 12.033 0.000 12.047 0.042 ;
+    END
+  END rw0_wd_in[309]
+  PIN rw0_wd_in[310]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 12.257 0.000 12.271 0.042 ;
+    END
+  END rw0_wd_in[310]
+  PIN rw0_wd_in[311]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 12.481 0.000 12.495 0.042 ;
+    END
+  END rw0_wd_in[311]
+  PIN rw0_wd_in[312]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 12.705 0.000 12.719 0.042 ;
+    END
+  END rw0_wd_in[312]
+  PIN rw0_wd_in[313]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 12.929 0.000 12.943 0.042 ;
+    END
+  END rw0_wd_in[313]
+  PIN rw0_wd_in[314]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 13.153 0.000 13.167 0.042 ;
+    END
+  END rw0_wd_in[314]
+  PIN rw0_wd_in[315]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 13.377 0.000 13.391 0.042 ;
+    END
+  END rw0_wd_in[315]
+  PIN rw0_wd_in[316]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 13.601 0.000 13.615 0.042 ;
+    END
+  END rw0_wd_in[316]
+  PIN rw0_wd_in[317]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 13.825 0.000 13.839 0.042 ;
+    END
+  END rw0_wd_in[317]
+  PIN rw0_wd_in[318]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 14.049 0.000 14.063 0.042 ;
+    END
+  END rw0_wd_in[318]
+  PIN rw0_wd_in[319]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 14.273 0.000 14.287 0.042 ;
+    END
+  END rw0_wd_in[319]
+  PIN rw0_wd_in[320]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 14.497 0.000 14.511 0.042 ;
+    END
+  END rw0_wd_in[320]
+  PIN rw0_wd_in[321]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 14.721 0.000 14.735 0.042 ;
+    END
+  END rw0_wd_in[321]
+  PIN rw0_wd_in[322]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 14.945 0.000 14.959 0.042 ;
+    END
+  END rw0_wd_in[322]
+  PIN rw0_wd_in[323]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 15.169 0.000 15.183 0.042 ;
+    END
+  END rw0_wd_in[323]
+  PIN rw0_wd_in[324]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 15.393 0.000 15.407 0.042 ;
+    END
+  END rw0_wd_in[324]
+  PIN rw0_wd_in[325]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 15.617 0.000 15.631 0.042 ;
+    END
+  END rw0_wd_in[325]
+  PIN rw0_wd_in[326]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 15.841 0.000 15.855 0.042 ;
+    END
+  END rw0_wd_in[326]
+  PIN rw0_wd_in[327]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 16.065 0.000 16.079 0.042 ;
+    END
+  END rw0_wd_in[327]
+  PIN rw0_wd_in[328]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 16.289 0.000 16.303 0.042 ;
+    END
+  END rw0_wd_in[328]
+  PIN rw0_wd_in[329]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 16.513 0.000 16.527 0.042 ;
+    END
+  END rw0_wd_in[329]
+  PIN rw0_wd_in[330]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 16.737 0.000 16.751 0.042 ;
+    END
+  END rw0_wd_in[330]
+  PIN rw0_wd_in[331]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 16.961 0.000 16.975 0.042 ;
+    END
+  END rw0_wd_in[331]
+  PIN rw0_wd_in[332]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 17.185 0.000 17.199 0.042 ;
+    END
+  END rw0_wd_in[332]
+  PIN rw0_wd_in[333]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 17.409 0.000 17.423 0.042 ;
+    END
+  END rw0_wd_in[333]
+  PIN rw0_wd_in[334]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 17.633 0.000 17.647 0.042 ;
+    END
+  END rw0_wd_in[334]
+  PIN rw0_wd_in[335]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 17.857 0.000 17.871 0.042 ;
+    END
+  END rw0_wd_in[335]
+  PIN rw0_wd_in[336]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 18.081 0.000 18.095 0.042 ;
+    END
+  END rw0_wd_in[336]
+  PIN rw0_wd_in[337]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 18.305 0.000 18.319 0.042 ;
+    END
+  END rw0_wd_in[337]
+  PIN rw0_wd_in[338]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 18.529 0.000 18.543 0.042 ;
+    END
+  END rw0_wd_in[338]
+  PIN rw0_wd_in[339]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 18.753 0.000 18.767 0.042 ;
+    END
+  END rw0_wd_in[339]
+  PIN rw0_wd_in[340]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 18.977 0.000 18.991 0.042 ;
+    END
+  END rw0_wd_in[340]
+  PIN rw0_wd_in[341]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 19.201 0.000 19.215 0.042 ;
+    END
+  END rw0_wd_in[341]
+  PIN rw0_wd_in[342]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 19.425 0.000 19.439 0.042 ;
+    END
+  END rw0_wd_in[342]
+  PIN rw0_wd_in[343]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 19.649 0.000 19.663 0.042 ;
+    END
+  END rw0_wd_in[343]
+  PIN rw0_wd_in[344]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 19.873 0.000 19.887 0.042 ;
+    END
+  END rw0_wd_in[344]
+  PIN rw0_wd_in[345]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 20.097 0.000 20.111 0.042 ;
+    END
+  END rw0_wd_in[345]
+  PIN rw0_wd_in[346]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 20.321 0.000 20.335 0.042 ;
+    END
+  END rw0_wd_in[346]
+  PIN rw0_wd_in[347]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 20.545 0.000 20.559 0.042 ;
+    END
+  END rw0_wd_in[347]
+  PIN rw0_wd_in[348]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 20.769 0.000 20.783 0.042 ;
+    END
+  END rw0_wd_in[348]
+  PIN rw0_wd_in[349]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 20.993 0.000 21.007 0.042 ;
+    END
+  END rw0_wd_in[349]
+  PIN rw0_wd_in[350]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 21.217 0.000 21.231 0.042 ;
+    END
+  END rw0_wd_in[350]
+  PIN rw0_wd_in[351]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 21.441 0.000 21.455 0.042 ;
+    END
+  END rw0_wd_in[351]
+  PIN rw0_wd_in[352]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 21.665 0.000 21.679 0.042 ;
+    END
+  END rw0_wd_in[352]
+  PIN rw0_wd_in[353]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 21.889 0.000 21.903 0.042 ;
+    END
+  END rw0_wd_in[353]
+  PIN rw0_wd_in[354]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 22.113 0.000 22.127 0.042 ;
+    END
+  END rw0_wd_in[354]
+  PIN rw0_wd_in[355]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 22.337 0.000 22.351 0.042 ;
+    END
+  END rw0_wd_in[355]
+  PIN rw0_wd_in[356]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 22.561 0.000 22.575 0.042 ;
+    END
+  END rw0_wd_in[356]
+  PIN rw0_wd_in[357]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 22.785 0.000 22.799 0.042 ;
+    END
+  END rw0_wd_in[357]
+  PIN rw0_wd_in[358]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 23.009 0.000 23.023 0.042 ;
+    END
+  END rw0_wd_in[358]
+  PIN rw0_wd_in[359]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 23.233 0.000 23.247 0.042 ;
+    END
+  END rw0_wd_in[359]
+  PIN rw0_wd_in[360]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 23.457 0.000 23.471 0.042 ;
+    END
+  END rw0_wd_in[360]
+  PIN rw0_wd_in[361]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 23.681 0.000 23.695 0.042 ;
+    END
+  END rw0_wd_in[361]
+  PIN rw0_wd_in[362]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 23.905 0.000 23.919 0.042 ;
+    END
+  END rw0_wd_in[362]
+  PIN rw0_wd_in[363]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 24.129 0.000 24.143 0.042 ;
+    END
+  END rw0_wd_in[363]
+  PIN rw0_wd_in[364]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 24.353 0.000 24.367 0.042 ;
+    END
+  END rw0_wd_in[364]
+  PIN rw0_wd_in[365]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 24.577 0.000 24.591 0.042 ;
+    END
+  END rw0_wd_in[365]
+  PIN rw0_wd_in[366]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 24.801 0.000 24.815 0.042 ;
+    END
+  END rw0_wd_in[366]
+  PIN rw0_wd_in[367]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 25.025 0.000 25.039 0.042 ;
+    END
+  END rw0_wd_in[367]
+  PIN rw0_wd_in[368]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 25.249 0.000 25.263 0.042 ;
+    END
+  END rw0_wd_in[368]
+  PIN rw0_wd_in[369]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 25.473 0.000 25.487 0.042 ;
+    END
+  END rw0_wd_in[369]
+  PIN rw0_wd_in[370]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 25.697 0.000 25.711 0.042 ;
+    END
+  END rw0_wd_in[370]
+  PIN rw0_wd_in[371]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 25.921 0.000 25.935 0.042 ;
+    END
+  END rw0_wd_in[371]
+  PIN rw0_wd_in[372]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 26.145 0.000 26.159 0.042 ;
+    END
+  END rw0_wd_in[372]
+  PIN rw0_wd_in[373]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 26.369 0.000 26.383 0.042 ;
+    END
+  END rw0_wd_in[373]
+  PIN rw0_wd_in[374]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 26.593 0.000 26.607 0.042 ;
+    END
+  END rw0_wd_in[374]
+  PIN rw0_wd_in[375]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 26.817 0.000 26.831 0.042 ;
+    END
+  END rw0_wd_in[375]
+  PIN rw0_wd_in[376]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 27.041 0.000 27.055 0.042 ;
+    END
+  END rw0_wd_in[376]
+  PIN rw0_wd_in[377]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 27.265 0.000 27.279 0.042 ;
+    END
+  END rw0_wd_in[377]
+  PIN rw0_wd_in[378]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 27.489 0.000 27.503 0.042 ;
+    END
+  END rw0_wd_in[378]
+  PIN rw0_wd_in[379]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 27.713 0.000 27.727 0.042 ;
+    END
+  END rw0_wd_in[379]
+  PIN rw0_wd_in[380]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 27.937 0.000 27.951 0.042 ;
+    END
+  END rw0_wd_in[380]
+  PIN rw0_wd_in[381]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 28.161 0.000 28.175 0.042 ;
+    END
+  END rw0_wd_in[381]
+  PIN rw0_wd_in[382]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 28.385 0.000 28.399 0.042 ;
+    END
+  END rw0_wd_in[382]
+  PIN rw0_wd_in[383]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 28.609 0.000 28.623 0.042 ;
+    END
+  END rw0_wd_in[383]
+  PIN rw0_wd_in[384]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 28.833 0.000 28.847 0.042 ;
+    END
+  END rw0_wd_in[384]
+  PIN rw0_wd_in[385]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 29.057 0.000 29.071 0.042 ;
+    END
+  END rw0_wd_in[385]
+  PIN rw0_wd_in[386]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 29.281 0.000 29.295 0.042 ;
+    END
+  END rw0_wd_in[386]
+  PIN rw0_wd_in[387]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 29.505 0.000 29.519 0.042 ;
+    END
+  END rw0_wd_in[387]
+  PIN rw0_wd_in[388]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 29.729 0.000 29.743 0.042 ;
+    END
+  END rw0_wd_in[388]
+  PIN rw0_wd_in[389]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 29.953 0.000 29.967 0.042 ;
+    END
+  END rw0_wd_in[389]
+  PIN rw0_wd_in[390]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 30.177 0.000 30.191 0.042 ;
+    END
+  END rw0_wd_in[390]
+  PIN rw0_wd_in[391]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 30.401 0.000 30.415 0.042 ;
+    END
+  END rw0_wd_in[391]
+  PIN rw0_wd_in[392]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 30.625 0.000 30.639 0.042 ;
+    END
+  END rw0_wd_in[392]
+  PIN rw0_wd_in[393]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 30.849 0.000 30.863 0.042 ;
+    END
+  END rw0_wd_in[393]
+  PIN rw0_wd_in[394]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 31.073 0.000 31.087 0.042 ;
+    END
+  END rw0_wd_in[394]
+  PIN rw0_wd_in[395]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 31.297 0.000 31.311 0.042 ;
+    END
+  END rw0_wd_in[395]
+  PIN rw0_wd_in[396]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 31.521 0.000 31.535 0.042 ;
+    END
+  END rw0_wd_in[396]
+  PIN rw0_wd_in[397]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 31.745 0.000 31.759 0.042 ;
+    END
+  END rw0_wd_in[397]
+  PIN rw0_wd_in[398]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 31.969 0.000 31.983 0.042 ;
+    END
+  END rw0_wd_in[398]
+  PIN rw0_wd_in[399]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 32.193 0.000 32.207 0.042 ;
+    END
+  END rw0_wd_in[399]
+  PIN rw0_wd_in[400]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 32.417 0.000 32.431 0.042 ;
+    END
+  END rw0_wd_in[400]
+  PIN rw0_wd_in[401]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 32.641 0.000 32.655 0.042 ;
+    END
+  END rw0_wd_in[401]
+  PIN rw0_wd_in[402]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 32.865 0.000 32.879 0.042 ;
+    END
+  END rw0_wd_in[402]
+  PIN rw0_wd_in[403]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 33.089 0.000 33.103 0.042 ;
+    END
+  END rw0_wd_in[403]
+  PIN rw0_wd_in[404]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 33.313 0.000 33.327 0.042 ;
+    END
+  END rw0_wd_in[404]
+  PIN rw0_wd_in[405]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 33.537 0.000 33.551 0.042 ;
+    END
+  END rw0_wd_in[405]
+  PIN rw0_wd_in[406]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 33.761 0.000 33.775 0.042 ;
+    END
+  END rw0_wd_in[406]
+  PIN rw0_wd_in[407]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 33.985 0.000 33.999 0.042 ;
+    END
+  END rw0_wd_in[407]
+  PIN rw0_wd_in[408]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 34.209 0.000 34.223 0.042 ;
+    END
+  END rw0_wd_in[408]
+  PIN rw0_wd_in[409]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 34.433 0.000 34.447 0.042 ;
+    END
+  END rw0_wd_in[409]
+  PIN rw0_wd_in[410]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 34.657 0.000 34.671 0.042 ;
+    END
+  END rw0_wd_in[410]
+  PIN rw0_wd_in[411]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 34.881 0.000 34.895 0.042 ;
+    END
+  END rw0_wd_in[411]
+  PIN rw0_wd_in[412]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 35.105 0.000 35.119 0.042 ;
+    END
+  END rw0_wd_in[412]
+  PIN rw0_wd_in[413]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 35.329 0.000 35.343 0.042 ;
+    END
+  END rw0_wd_in[413]
+  PIN rw0_wd_in[414]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 35.553 0.000 35.567 0.042 ;
+    END
+  END rw0_wd_in[414]
+  PIN rw0_wd_in[415]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 35.777 0.000 35.791 0.042 ;
+    END
+  END rw0_wd_in[415]
+  PIN rw0_wd_in[416]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 36.001 0.000 36.015 0.042 ;
+    END
+  END rw0_wd_in[416]
+  PIN rw0_wd_in[417]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 36.225 0.000 36.239 0.042 ;
+    END
+  END rw0_wd_in[417]
+  PIN rw0_wd_in[418]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 36.449 0.000 36.463 0.042 ;
+    END
+  END rw0_wd_in[418]
+  PIN rw0_wd_in[419]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 36.673 0.000 36.687 0.042 ;
+    END
+  END rw0_wd_in[419]
+  PIN rw0_wd_in[420]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 36.897 0.000 36.911 0.042 ;
+    END
+  END rw0_wd_in[420]
+  PIN rw0_wd_in[421]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 37.121 0.000 37.135 0.042 ;
+    END
+  END rw0_wd_in[421]
+  PIN rw0_wd_in[422]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 37.345 0.000 37.359 0.042 ;
+    END
+  END rw0_wd_in[422]
+  PIN rw0_wd_in[423]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 37.569 0.000 37.583 0.042 ;
+    END
+  END rw0_wd_in[423]
+  PIN rw0_wd_in[424]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 37.793 0.000 37.807 0.042 ;
+    END
+  END rw0_wd_in[424]
+  PIN rw0_wd_in[425]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 38.017 0.000 38.031 0.042 ;
+    END
+  END rw0_wd_in[425]
+  PIN rw0_wd_in[426]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 38.241 0.000 38.255 0.042 ;
+    END
+  END rw0_wd_in[426]
+  PIN rw0_wd_in[427]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 38.465 0.000 38.479 0.042 ;
+    END
+  END rw0_wd_in[427]
+  PIN rw0_wd_in[428]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 38.689 0.000 38.703 0.042 ;
+    END
+  END rw0_wd_in[428]
+  PIN rw0_wd_in[429]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 38.913 0.000 38.927 0.042 ;
+    END
+  END rw0_wd_in[429]
+  PIN rw0_wd_in[430]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 39.137 0.000 39.151 0.042 ;
+    END
+  END rw0_wd_in[430]
+  PIN rw0_wd_in[431]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 39.361 0.000 39.375 0.042 ;
+    END
+  END rw0_wd_in[431]
+  PIN rw0_wd_in[432]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 39.585 0.000 39.599 0.042 ;
+    END
+  END rw0_wd_in[432]
+  PIN rw0_wd_in[433]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 39.809 0.000 39.823 0.042 ;
+    END
+  END rw0_wd_in[433]
+  PIN rw0_wd_in[434]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 40.033 0.000 40.047 0.042 ;
+    END
+  END rw0_wd_in[434]
+  PIN rw0_wd_in[435]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 40.257 0.000 40.271 0.042 ;
+    END
+  END rw0_wd_in[435]
+  PIN rw0_wd_in[436]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 40.481 0.000 40.495 0.042 ;
+    END
+  END rw0_wd_in[436]
+  PIN rw0_wd_in[437]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 40.705 0.000 40.719 0.042 ;
+    END
+  END rw0_wd_in[437]
+  PIN rw0_wd_in[438]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 40.929 0.000 40.943 0.042 ;
+    END
+  END rw0_wd_in[438]
+  PIN rw0_wd_in[439]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 41.153 0.000 41.167 0.042 ;
+    END
+  END rw0_wd_in[439]
+  PIN rw0_wd_in[440]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 41.377 0.000 41.391 0.042 ;
+    END
+  END rw0_wd_in[440]
+  PIN rw0_wd_in[441]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 41.601 0.000 41.615 0.042 ;
+    END
+  END rw0_wd_in[441]
+  PIN rw0_wd_in[442]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 41.825 0.000 41.839 0.042 ;
+    END
+  END rw0_wd_in[442]
+  PIN rw0_wd_in[443]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 42.049 0.000 42.063 0.042 ;
+    END
+  END rw0_wd_in[443]
+  PIN rw0_wd_in[444]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 42.273 0.000 42.287 0.042 ;
+    END
+  END rw0_wd_in[444]
+  PIN rw0_wd_in[445]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 42.497 0.000 42.511 0.042 ;
+    END
+  END rw0_wd_in[445]
+  PIN rw0_wd_in[446]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 42.721 0.000 42.735 0.042 ;
+    END
+  END rw0_wd_in[446]
+  PIN rw0_wd_in[447]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 42.945 0.000 42.959 0.042 ;
+    END
+  END rw0_wd_in[447]
+  PIN rw0_wd_in[448]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 43.169 0.000 43.183 0.042 ;
+    END
+  END rw0_wd_in[448]
+  PIN rw0_wd_in[449]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 43.393 0.000 43.407 0.042 ;
+    END
+  END rw0_wd_in[449]
+  PIN rw0_wd_in[450]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 43.617 0.000 43.631 0.042 ;
+    END
+  END rw0_wd_in[450]
+  PIN rw0_wd_in[451]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 43.841 0.000 43.855 0.042 ;
+    END
+  END rw0_wd_in[451]
+  PIN rw0_wd_in[452]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 44.065 0.000 44.079 0.042 ;
+    END
+  END rw0_wd_in[452]
+  PIN rw0_wd_in[453]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 44.289 0.000 44.303 0.042 ;
+    END
+  END rw0_wd_in[453]
+  PIN rw0_wd_in[454]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 44.513 0.000 44.527 0.042 ;
+    END
+  END rw0_wd_in[454]
+  PIN rw0_wd_in[455]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 44.737 0.000 44.751 0.042 ;
+    END
+  END rw0_wd_in[455]
+  PIN rw0_wd_in[456]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 44.961 0.000 44.975 0.042 ;
+    END
+  END rw0_wd_in[456]
+  PIN rw0_wd_in[457]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 45.185 0.000 45.199 0.042 ;
+    END
+  END rw0_wd_in[457]
+  PIN rw0_wd_in[458]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 45.409 0.000 45.423 0.042 ;
+    END
+  END rw0_wd_in[458]
+  PIN rw0_wd_in[459]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 45.633 0.000 45.647 0.042 ;
+    END
+  END rw0_wd_in[459]
+  PIN rw0_wd_in[460]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 45.857 0.000 45.871 0.042 ;
+    END
+  END rw0_wd_in[460]
+  PIN rw0_wd_in[461]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 46.081 0.000 46.095 0.042 ;
+    END
+  END rw0_wd_in[461]
+  PIN rw0_wd_in[462]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 46.305 0.000 46.319 0.042 ;
+    END
+  END rw0_wd_in[462]
+  PIN rw0_wd_in[463]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 46.529 0.000 46.543 0.042 ;
+    END
+  END rw0_wd_in[463]
+  PIN rw0_wd_in[464]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 46.753 0.000 46.767 0.042 ;
+    END
+  END rw0_wd_in[464]
+  PIN rw0_wd_in[465]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 46.977 0.000 46.991 0.042 ;
+    END
+  END rw0_wd_in[465]
+  PIN rw0_wd_in[466]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 47.201 0.000 47.215 0.042 ;
+    END
+  END rw0_wd_in[466]
+  PIN rw0_wd_in[467]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 47.425 0.000 47.439 0.042 ;
+    END
+  END rw0_wd_in[467]
+  PIN rw0_wd_in[468]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 47.649 0.000 47.663 0.042 ;
+    END
+  END rw0_wd_in[468]
+  PIN rw0_wd_in[469]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 47.873 0.000 47.887 0.042 ;
+    END
+  END rw0_wd_in[469]
+  PIN rw0_wd_in[470]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 48.097 0.000 48.111 0.042 ;
+    END
+  END rw0_wd_in[470]
+  PIN rw0_wd_in[471]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 48.321 0.000 48.335 0.042 ;
+    END
+  END rw0_wd_in[471]
+  PIN rw0_wd_in[472]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 48.545 0.000 48.559 0.042 ;
+    END
+  END rw0_wd_in[472]
+  PIN rw0_wd_in[473]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 48.769 0.000 48.783 0.042 ;
+    END
+  END rw0_wd_in[473]
+  PIN rw0_wd_in[474]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 48.993 0.000 49.007 0.042 ;
+    END
+  END rw0_wd_in[474]
+  PIN rw0_wd_in[475]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 49.217 0.000 49.231 0.042 ;
+    END
+  END rw0_wd_in[475]
+  PIN rw0_wd_in[476]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 49.441 0.000 49.455 0.042 ;
+    END
+  END rw0_wd_in[476]
+  PIN rw0_wd_in[477]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 49.665 0.000 49.679 0.042 ;
+    END
+  END rw0_wd_in[477]
+  PIN rw0_wd_in[478]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 49.889 0.000 49.903 0.042 ;
+    END
+  END rw0_wd_in[478]
+  PIN rw0_wd_in[479]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 50.113 0.000 50.127 0.042 ;
+    END
+  END rw0_wd_in[479]
+  PIN rw0_wd_in[480]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 50.337 0.000 50.351 0.042 ;
+    END
+  END rw0_wd_in[480]
+  PIN rw0_wd_in[481]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 50.561 0.000 50.575 0.042 ;
+    END
+  END rw0_wd_in[481]
+  PIN rw0_wd_in[482]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 50.785 0.000 50.799 0.042 ;
+    END
+  END rw0_wd_in[482]
+  PIN rw0_wd_in[483]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 51.009 0.000 51.023 0.042 ;
+    END
+  END rw0_wd_in[483]
+  PIN rw0_wd_in[484]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 51.233 0.000 51.247 0.042 ;
+    END
+  END rw0_wd_in[484]
+  PIN rw0_wd_in[485]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 51.457 0.000 51.471 0.042 ;
+    END
+  END rw0_wd_in[485]
+  PIN rw0_wd_in[486]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 51.681 0.000 51.695 0.042 ;
+    END
+  END rw0_wd_in[486]
+  PIN rw0_wd_in[487]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 51.905 0.000 51.919 0.042 ;
+    END
+  END rw0_wd_in[487]
+  PIN rw0_wd_in[488]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 52.129 0.000 52.143 0.042 ;
+    END
+  END rw0_wd_in[488]
+  PIN rw0_wd_in[489]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 52.353 0.000 52.367 0.042 ;
+    END
+  END rw0_wd_in[489]
+  PIN rw0_wd_in[490]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 52.577 0.000 52.591 0.042 ;
+    END
+  END rw0_wd_in[490]
+  PIN rw0_wd_in[491]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 52.801 0.000 52.815 0.042 ;
+    END
+  END rw0_wd_in[491]
+  PIN rw0_wd_in[492]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 53.025 0.000 53.039 0.042 ;
+    END
+  END rw0_wd_in[492]
+  PIN rw0_wd_in[493]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 53.249 0.000 53.263 0.042 ;
+    END
+  END rw0_wd_in[493]
+  PIN rw0_wd_in[494]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 53.473 0.000 53.487 0.042 ;
+    END
+  END rw0_wd_in[494]
+  PIN rw0_wd_in[495]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 53.697 0.000 53.711 0.042 ;
+    END
+  END rw0_wd_in[495]
+  PIN rw0_wd_in[496]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 53.921 0.000 53.935 0.042 ;
+    END
+  END rw0_wd_in[496]
+  PIN rw0_wd_in[497]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 54.145 0.000 54.159 0.042 ;
+    END
+  END rw0_wd_in[497]
+  PIN rw0_wd_in[498]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 54.369 0.000 54.383 0.042 ;
+    END
+  END rw0_wd_in[498]
+  PIN rw0_wd_in[499]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 54.593 0.000 54.607 0.042 ;
+    END
+  END rw0_wd_in[499]
+  PIN rw0_wd_in[500]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 54.817 0.000 54.831 0.042 ;
+    END
+  END rw0_wd_in[500]
+  PIN rw0_wd_in[501]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 55.041 0.000 55.055 0.042 ;
+    END
+  END rw0_wd_in[501]
+  PIN rw0_wd_in[502]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 55.265 0.000 55.279 0.042 ;
+    END
+  END rw0_wd_in[502]
+  PIN rw0_wd_in[503]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 55.489 0.000 55.503 0.042 ;
+    END
+  END rw0_wd_in[503]
+  PIN rw0_wd_in[504]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 55.713 0.000 55.727 0.042 ;
+    END
+  END rw0_wd_in[504]
+  PIN rw0_wd_in[505]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 55.937 0.000 55.951 0.042 ;
+    END
+  END rw0_wd_in[505]
+  PIN rw0_wd_in[506]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 56.161 0.000 56.175 0.042 ;
+    END
+  END rw0_wd_in[506]
+  PIN rw0_wd_in[507]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 56.385 0.000 56.399 0.042 ;
+    END
+  END rw0_wd_in[507]
+  PIN rw0_wd_in[508]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 56.609 0.000 56.623 0.042 ;
+    END
+  END rw0_wd_in[508]
+  PIN rw0_wd_in[509]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 56.833 0.000 56.847 0.042 ;
+    END
+  END rw0_wd_in[509]
+  PIN rw0_wd_in[510]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 57.057 0.000 57.071 0.042 ;
+    END
+  END rw0_wd_in[510]
+  PIN rw0_wd_in[511]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 57.281 0.000 57.295 0.042 ;
+    END
+  END rw0_wd_in[511]
+  PIN rw0_rd_out[0]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 57.505 0.000 57.519 0.042 ;
+    END
+  END rw0_rd_out[0]
+  PIN rw0_rd_out[1]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 57.729 0.000 57.743 0.042 ;
+    END
+  END rw0_rd_out[1]
+  PIN rw0_rd_out[2]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 57.953 0.000 57.967 0.042 ;
+    END
+  END rw0_rd_out[2]
+  PIN rw0_rd_out[3]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 58.177 0.000 58.191 0.042 ;
+    END
+  END rw0_rd_out[3]
+  PIN rw0_rd_out[4]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 58.401 0.000 58.415 0.042 ;
+    END
+  END rw0_rd_out[4]
+  PIN rw0_rd_out[5]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 58.625 0.000 58.639 0.042 ;
+    END
+  END rw0_rd_out[5]
+  PIN rw0_rd_out[6]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 58.849 0.000 58.863 0.042 ;
+    END
+  END rw0_rd_out[6]
+  PIN rw0_rd_out[7]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 59.073 0.000 59.087 0.042 ;
+    END
+  END rw0_rd_out[7]
+  PIN rw0_rd_out[8]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 59.297 0.000 59.311 0.042 ;
+    END
+  END rw0_rd_out[8]
+  PIN rw0_rd_out[9]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 59.521 0.000 59.535 0.042 ;
+    END
+  END rw0_rd_out[9]
+  PIN rw0_rd_out[10]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 59.745 0.000 59.759 0.042 ;
+    END
+  END rw0_rd_out[10]
+  PIN rw0_rd_out[11]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 59.969 0.000 59.983 0.042 ;
+    END
+  END rw0_rd_out[11]
+  PIN rw0_rd_out[12]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 60.193 0.000 60.207 0.042 ;
+    END
+  END rw0_rd_out[12]
+  PIN rw0_rd_out[13]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 60.417 0.000 60.431 0.042 ;
+    END
+  END rw0_rd_out[13]
+  PIN rw0_rd_out[14]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 60.641 0.000 60.655 0.042 ;
+    END
+  END rw0_rd_out[14]
+  PIN rw0_rd_out[15]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 60.865 0.000 60.879 0.042 ;
+    END
+  END rw0_rd_out[15]
+  PIN rw0_rd_out[16]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 61.089 0.000 61.103 0.042 ;
+    END
+  END rw0_rd_out[16]
+  PIN rw0_rd_out[17]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 61.313 0.000 61.327 0.042 ;
+    END
+  END rw0_rd_out[17]
+  PIN rw0_rd_out[18]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 61.537 0.000 61.551 0.042 ;
+    END
+  END rw0_rd_out[18]
+  PIN rw0_rd_out[19]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 61.761 0.000 61.775 0.042 ;
+    END
+  END rw0_rd_out[19]
+  PIN rw0_rd_out[20]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 61.985 0.000 61.999 0.042 ;
+    END
+  END rw0_rd_out[20]
+  PIN rw0_rd_out[21]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 62.209 0.000 62.223 0.042 ;
+    END
+  END rw0_rd_out[21]
+  PIN rw0_rd_out[22]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 62.433 0.000 62.447 0.042 ;
+    END
+  END rw0_rd_out[22]
+  PIN rw0_rd_out[23]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 62.657 0.000 62.671 0.042 ;
+    END
+  END rw0_rd_out[23]
+  PIN rw0_rd_out[24]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 62.881 0.000 62.895 0.042 ;
+    END
+  END rw0_rd_out[24]
+  PIN rw0_rd_out[25]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 63.105 0.000 63.119 0.042 ;
+    END
+  END rw0_rd_out[25]
+  PIN rw0_rd_out[26]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 63.329 0.000 63.343 0.042 ;
+    END
+  END rw0_rd_out[26]
+  PIN rw0_rd_out[27]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 63.553 0.000 63.567 0.042 ;
+    END
+  END rw0_rd_out[27]
+  PIN rw0_rd_out[28]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 63.777 0.000 63.791 0.042 ;
+    END
+  END rw0_rd_out[28]
+  PIN rw0_rd_out[29]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 64.001 0.000 64.015 0.042 ;
+    END
+  END rw0_rd_out[29]
+  PIN rw0_rd_out[30]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 64.225 0.000 64.239 0.042 ;
+    END
+  END rw0_rd_out[30]
+  PIN rw0_rd_out[31]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 64.449 0.000 64.463 0.042 ;
+    END
+  END rw0_rd_out[31]
+  PIN rw0_rd_out[32]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 64.673 0.000 64.687 0.042 ;
+    END
+  END rw0_rd_out[32]
+  PIN rw0_rd_out[33]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 64.897 0.000 64.911 0.042 ;
+    END
+  END rw0_rd_out[33]
+  PIN rw0_rd_out[34]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 65.121 0.000 65.135 0.042 ;
+    END
+  END rw0_rd_out[34]
+  PIN rw0_rd_out[35]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 65.345 0.000 65.359 0.042 ;
+    END
+  END rw0_rd_out[35]
+  PIN rw0_rd_out[36]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 65.569 0.000 65.583 0.042 ;
+    END
+  END rw0_rd_out[36]
+  PIN rw0_rd_out[37]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 65.793 0.000 65.807 0.042 ;
+    END
+  END rw0_rd_out[37]
+  PIN rw0_rd_out[38]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 66.017 0.000 66.031 0.042 ;
+    END
+  END rw0_rd_out[38]
+  PIN rw0_rd_out[39]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 66.241 0.000 66.255 0.042 ;
+    END
+  END rw0_rd_out[39]
+  PIN rw0_rd_out[40]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 66.465 0.000 66.479 0.042 ;
+    END
+  END rw0_rd_out[40]
+  PIN rw0_rd_out[41]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 66.689 0.000 66.703 0.042 ;
+    END
+  END rw0_rd_out[41]
+  PIN rw0_rd_out[42]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 66.913 0.000 66.927 0.042 ;
+    END
+  END rw0_rd_out[42]
+  PIN rw0_rd_out[43]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 67.137 0.000 67.151 0.042 ;
+    END
+  END rw0_rd_out[43]
+  PIN rw0_rd_out[44]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 67.361 0.000 67.375 0.042 ;
+    END
+  END rw0_rd_out[44]
+  PIN rw0_rd_out[45]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 67.585 0.000 67.599 0.042 ;
+    END
+  END rw0_rd_out[45]
+  PIN rw0_rd_out[46]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 67.809 0.000 67.823 0.042 ;
+    END
+  END rw0_rd_out[46]
+  PIN rw0_rd_out[47]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 68.033 0.000 68.047 0.042 ;
+    END
+  END rw0_rd_out[47]
+  PIN rw0_rd_out[48]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 68.257 0.000 68.271 0.042 ;
+    END
+  END rw0_rd_out[48]
+  PIN rw0_rd_out[49]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 68.481 0.000 68.495 0.042 ;
+    END
+  END rw0_rd_out[49]
+  PIN rw0_rd_out[50]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 68.705 0.000 68.719 0.042 ;
+    END
+  END rw0_rd_out[50]
+  PIN rw0_rd_out[51]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 68.929 0.000 68.943 0.042 ;
+    END
+  END rw0_rd_out[51]
+  PIN rw0_rd_out[52]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 69.153 0.000 69.167 0.042 ;
+    END
+  END rw0_rd_out[52]
+  PIN rw0_rd_out[53]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 69.377 0.000 69.391 0.042 ;
+    END
+  END rw0_rd_out[53]
+  PIN rw0_rd_out[54]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 69.601 0.000 69.615 0.042 ;
+    END
+  END rw0_rd_out[54]
+  PIN rw0_rd_out[55]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 69.825 0.000 69.839 0.042 ;
+    END
+  END rw0_rd_out[55]
+  PIN rw0_rd_out[56]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 70.049 0.000 70.063 0.042 ;
+    END
+  END rw0_rd_out[56]
+  PIN rw0_rd_out[57]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 70.273 0.000 70.287 0.042 ;
+    END
+  END rw0_rd_out[57]
+  PIN rw0_rd_out[58]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 70.497 0.000 70.511 0.042 ;
+    END
+  END rw0_rd_out[58]
+  PIN rw0_rd_out[59]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 70.721 0.000 70.735 0.042 ;
+    END
+  END rw0_rd_out[59]
+  PIN rw0_rd_out[60]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 70.945 0.000 70.959 0.042 ;
+    END
+  END rw0_rd_out[60]
+  PIN rw0_rd_out[61]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 71.169 0.000 71.183 0.042 ;
+    END
+  END rw0_rd_out[61]
+  PIN rw0_rd_out[62]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 71.393 0.000 71.407 0.042 ;
+    END
+  END rw0_rd_out[62]
+  PIN rw0_rd_out[63]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 71.617 0.000 71.631 0.042 ;
+    END
+  END rw0_rd_out[63]
+  PIN rw0_rd_out[64]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 71.841 0.000 71.855 0.042 ;
+    END
+  END rw0_rd_out[64]
+  PIN rw0_rd_out[65]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 72.065 0.000 72.079 0.042 ;
+    END
+  END rw0_rd_out[65]
+  PIN rw0_rd_out[66]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 72.289 0.000 72.303 0.042 ;
+    END
+  END rw0_rd_out[66]
+  PIN rw0_rd_out[67]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 72.513 0.000 72.527 0.042 ;
+    END
+  END rw0_rd_out[67]
+  PIN rw0_rd_out[68]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 72.737 0.000 72.751 0.042 ;
+    END
+  END rw0_rd_out[68]
+  PIN rw0_rd_out[69]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 72.961 0.000 72.975 0.042 ;
+    END
+  END rw0_rd_out[69]
+  PIN rw0_rd_out[70]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 73.185 0.000 73.199 0.042 ;
+    END
+  END rw0_rd_out[70]
+  PIN rw0_rd_out[71]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 73.409 0.000 73.423 0.042 ;
+    END
+  END rw0_rd_out[71]
+  PIN rw0_rd_out[72]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 73.633 0.000 73.647 0.042 ;
+    END
+  END rw0_rd_out[72]
+  PIN rw0_rd_out[73]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 73.857 0.000 73.871 0.042 ;
+    END
+  END rw0_rd_out[73]
+  PIN rw0_rd_out[74]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 74.081 0.000 74.095 0.042 ;
+    END
+  END rw0_rd_out[74]
+  PIN rw0_rd_out[75]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 74.305 0.000 74.319 0.042 ;
+    END
+  END rw0_rd_out[75]
+  PIN rw0_rd_out[76]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 74.529 0.000 74.543 0.042 ;
+    END
+  END rw0_rd_out[76]
+  PIN rw0_rd_out[77]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 74.753 0.000 74.767 0.042 ;
+    END
+  END rw0_rd_out[77]
+  PIN rw0_rd_out[78]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 74.977 0.000 74.991 0.042 ;
+    END
+  END rw0_rd_out[78]
+  PIN rw0_rd_out[79]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 75.201 0.000 75.215 0.042 ;
+    END
+  END rw0_rd_out[79]
+  PIN rw0_rd_out[80]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 75.425 0.000 75.439 0.042 ;
+    END
+  END rw0_rd_out[80]
+  PIN rw0_rd_out[81]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 75.649 0.000 75.663 0.042 ;
+    END
+  END rw0_rd_out[81]
+  PIN rw0_rd_out[82]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 75.873 0.000 75.887 0.042 ;
+    END
+  END rw0_rd_out[82]
+  PIN rw0_rd_out[83]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 76.097 0.000 76.111 0.042 ;
+    END
+  END rw0_rd_out[83]
+  PIN rw0_rd_out[84]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 76.321 0.000 76.335 0.042 ;
+    END
+  END rw0_rd_out[84]
+  PIN rw0_rd_out[85]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 76.545 0.000 76.559 0.042 ;
+    END
+  END rw0_rd_out[85]
+  PIN rw0_rd_out[86]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 76.769 0.000 76.783 0.042 ;
+    END
+  END rw0_rd_out[86]
+  PIN rw0_rd_out[87]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 76.993 0.000 77.007 0.042 ;
+    END
+  END rw0_rd_out[87]
+  PIN rw0_rd_out[88]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 77.217 0.000 77.231 0.042 ;
+    END
+  END rw0_rd_out[88]
+  PIN rw0_rd_out[89]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 77.441 0.000 77.455 0.042 ;
+    END
+  END rw0_rd_out[89]
+  PIN rw0_rd_out[90]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 77.665 0.000 77.679 0.042 ;
+    END
+  END rw0_rd_out[90]
+  PIN rw0_rd_out[91]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 77.889 0.000 77.903 0.042 ;
+    END
+  END rw0_rd_out[91]
+  PIN rw0_rd_out[92]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 78.113 0.000 78.127 0.042 ;
+    END
+  END rw0_rd_out[92]
+  PIN rw0_rd_out[93]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 78.337 0.000 78.351 0.042 ;
+    END
+  END rw0_rd_out[93]
+  PIN rw0_rd_out[94]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 78.561 0.000 78.575 0.042 ;
+    END
+  END rw0_rd_out[94]
+  PIN rw0_rd_out[95]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 78.785 0.000 78.799 0.042 ;
+    END
+  END rw0_rd_out[95]
+  PIN rw0_rd_out[96]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 79.009 0.000 79.023 0.042 ;
+    END
+  END rw0_rd_out[96]
+  PIN rw0_rd_out[97]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 79.233 0.000 79.247 0.042 ;
+    END
+  END rw0_rd_out[97]
+  PIN rw0_rd_out[98]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 79.457 0.000 79.471 0.042 ;
+    END
+  END rw0_rd_out[98]
+  PIN rw0_rd_out[99]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 79.681 0.000 79.695 0.042 ;
+    END
+  END rw0_rd_out[99]
+  PIN rw0_rd_out[100]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 79.905 0.000 79.919 0.042 ;
+    END
+  END rw0_rd_out[100]
+  PIN rw0_rd_out[101]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 80.129 0.000 80.143 0.042 ;
+    END
+  END rw0_rd_out[101]
+  PIN rw0_rd_out[102]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 80.353 0.000 80.367 0.042 ;
+    END
+  END rw0_rd_out[102]
+  PIN rw0_rd_out[103]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 80.577 0.000 80.591 0.042 ;
+    END
+  END rw0_rd_out[103]
+  PIN rw0_rd_out[104]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 80.801 0.000 80.815 0.042 ;
+    END
+  END rw0_rd_out[104]
+  PIN rw0_rd_out[105]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 81.025 0.000 81.039 0.042 ;
+    END
+  END rw0_rd_out[105]
+  PIN rw0_rd_out[106]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 81.249 0.000 81.263 0.042 ;
+    END
+  END rw0_rd_out[106]
+  PIN rw0_rd_out[107]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 81.473 0.000 81.487 0.042 ;
+    END
+  END rw0_rd_out[107]
+  PIN rw0_rd_out[108]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 81.697 0.000 81.711 0.042 ;
+    END
+  END rw0_rd_out[108]
+  PIN rw0_rd_out[109]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 81.921 0.000 81.935 0.042 ;
+    END
+  END rw0_rd_out[109]
+  PIN rw0_rd_out[110]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 82.145 0.000 82.159 0.042 ;
+    END
+  END rw0_rd_out[110]
+  PIN rw0_rd_out[111]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 82.369 0.000 82.383 0.042 ;
+    END
+  END rw0_rd_out[111]
+  PIN rw0_rd_out[112]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 82.593 0.000 82.607 0.042 ;
+    END
+  END rw0_rd_out[112]
+  PIN rw0_rd_out[113]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 82.817 0.000 82.831 0.042 ;
+    END
+  END rw0_rd_out[113]
+  PIN rw0_rd_out[114]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 83.041 0.000 83.055 0.042 ;
+    END
+  END rw0_rd_out[114]
+  PIN rw0_rd_out[115]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 83.265 0.000 83.279 0.042 ;
+    END
+  END rw0_rd_out[115]
+  PIN rw0_rd_out[116]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 83.489 0.000 83.503 0.042 ;
+    END
+  END rw0_rd_out[116]
+  PIN rw0_rd_out[117]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 83.713 0.000 83.727 0.042 ;
+    END
+  END rw0_rd_out[117]
+  PIN rw0_rd_out[118]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 83.937 0.000 83.951 0.042 ;
+    END
+  END rw0_rd_out[118]
+  PIN rw0_rd_out[119]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 84.161 0.000 84.175 0.042 ;
+    END
+  END rw0_rd_out[119]
+  PIN rw0_rd_out[120]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 84.385 0.000 84.399 0.042 ;
+    END
+  END rw0_rd_out[120]
+  PIN rw0_rd_out[121]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 84.609 0.000 84.623 0.042 ;
+    END
+  END rw0_rd_out[121]
+  PIN rw0_rd_out[122]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 84.833 0.000 84.847 0.042 ;
+    END
+  END rw0_rd_out[122]
+  PIN rw0_rd_out[123]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 85.057 0.000 85.071 0.042 ;
+    END
+  END rw0_rd_out[123]
+  PIN rw0_rd_out[124]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 85.281 0.000 85.295 0.042 ;
+    END
+  END rw0_rd_out[124]
+  PIN rw0_rd_out[125]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 85.505 0.000 85.519 0.042 ;
+    END
+  END rw0_rd_out[125]
+  PIN rw0_rd_out[126]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 85.729 0.000 85.743 0.042 ;
+    END
+  END rw0_rd_out[126]
+  PIN rw0_rd_out[127]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 85.953 0.000 85.967 0.042 ;
+    END
+  END rw0_rd_out[127]
+  PIN rw0_rd_out[128]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 86.177 0.000 86.191 0.042 ;
+    END
+  END rw0_rd_out[128]
+  PIN rw0_rd_out[129]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 86.401 0.000 86.415 0.042 ;
+    END
+  END rw0_rd_out[129]
+  PIN rw0_rd_out[130]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 86.625 0.000 86.639 0.042 ;
+    END
+  END rw0_rd_out[130]
+  PIN rw0_rd_out[131]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 86.849 0.000 86.863 0.042 ;
+    END
+  END rw0_rd_out[131]
+  PIN rw0_rd_out[132]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 87.073 0.000 87.087 0.042 ;
+    END
+  END rw0_rd_out[132]
+  PIN rw0_rd_out[133]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 87.297 0.000 87.311 0.042 ;
+    END
+  END rw0_rd_out[133]
+  PIN rw0_rd_out[134]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 87.521 0.000 87.535 0.042 ;
+    END
+  END rw0_rd_out[134]
+  PIN rw0_rd_out[135]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 87.745 0.000 87.759 0.042 ;
+    END
+  END rw0_rd_out[135]
+  PIN rw0_rd_out[136]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 87.969 0.000 87.983 0.042 ;
+    END
+  END rw0_rd_out[136]
+  PIN rw0_rd_out[137]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 88.193 0.000 88.207 0.042 ;
+    END
+  END rw0_rd_out[137]
+  PIN rw0_rd_out[138]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 88.417 0.000 88.431 0.042 ;
+    END
+  END rw0_rd_out[138]
+  PIN rw0_rd_out[139]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 88.641 0.000 88.655 0.042 ;
+    END
+  END rw0_rd_out[139]
+  PIN rw0_rd_out[140]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 88.865 0.000 88.879 0.042 ;
+    END
+  END rw0_rd_out[140]
+  PIN rw0_rd_out[141]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 89.089 0.000 89.103 0.042 ;
+    END
+  END rw0_rd_out[141]
+  PIN rw0_rd_out[142]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 89.313 0.000 89.327 0.042 ;
+    END
+  END rw0_rd_out[142]
+  PIN rw0_rd_out[143]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 89.537 0.000 89.551 0.042 ;
+    END
+  END rw0_rd_out[143]
+  PIN rw0_rd_out[144]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 89.761 0.000 89.775 0.042 ;
+    END
+  END rw0_rd_out[144]
+  PIN rw0_rd_out[145]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 89.985 0.000 89.999 0.042 ;
+    END
+  END rw0_rd_out[145]
+  PIN rw0_rd_out[146]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 90.209 0.000 90.223 0.042 ;
+    END
+  END rw0_rd_out[146]
+  PIN rw0_rd_out[147]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 90.433 0.000 90.447 0.042 ;
+    END
+  END rw0_rd_out[147]
+  PIN rw0_rd_out[148]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 90.657 0.000 90.671 0.042 ;
+    END
+  END rw0_rd_out[148]
+  PIN rw0_rd_out[149]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 90.881 0.000 90.895 0.042 ;
+    END
+  END rw0_rd_out[149]
+  PIN rw0_rd_out[150]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 91.105 0.000 91.119 0.042 ;
+    END
+  END rw0_rd_out[150]
+  PIN rw0_rd_out[151]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 91.329 0.000 91.343 0.042 ;
+    END
+  END rw0_rd_out[151]
+  PIN rw0_rd_out[152]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 91.553 0.000 91.567 0.042 ;
+    END
+  END rw0_rd_out[152]
+  PIN rw0_rd_out[153]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 91.777 0.000 91.791 0.042 ;
+    END
+  END rw0_rd_out[153]
+  PIN rw0_rd_out[154]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 92.001 0.000 92.015 0.042 ;
+    END
+  END rw0_rd_out[154]
+  PIN rw0_rd_out[155]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 92.225 0.000 92.239 0.042 ;
+    END
+  END rw0_rd_out[155]
+  PIN rw0_rd_out[156]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 92.449 0.000 92.463 0.042 ;
+    END
+  END rw0_rd_out[156]
+  PIN rw0_rd_out[157]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 92.673 0.000 92.687 0.042 ;
+    END
+  END rw0_rd_out[157]
+  PIN rw0_rd_out[158]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 92.897 0.000 92.911 0.042 ;
+    END
+  END rw0_rd_out[158]
+  PIN rw0_rd_out[159]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 93.121 0.000 93.135 0.042 ;
+    END
+  END rw0_rd_out[159]
+  PIN rw0_rd_out[160]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 93.345 0.000 93.359 0.042 ;
+    END
+  END rw0_rd_out[160]
+  PIN rw0_rd_out[161]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 93.569 0.000 93.583 0.042 ;
+    END
+  END rw0_rd_out[161]
+  PIN rw0_rd_out[162]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 93.793 0.000 93.807 0.042 ;
+    END
+  END rw0_rd_out[162]
+  PIN rw0_rd_out[163]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 94.017 0.000 94.031 0.042 ;
+    END
+  END rw0_rd_out[163]
+  PIN rw0_rd_out[164]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 94.241 0.000 94.255 0.042 ;
+    END
+  END rw0_rd_out[164]
+  PIN rw0_rd_out[165]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 94.465 0.000 94.479 0.042 ;
+    END
+  END rw0_rd_out[165]
+  PIN rw0_rd_out[166]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 94.689 0.000 94.703 0.042 ;
+    END
+  END rw0_rd_out[166]
+  PIN rw0_rd_out[167]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 94.913 0.000 94.927 0.042 ;
+    END
+  END rw0_rd_out[167]
+  PIN rw0_rd_out[168]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 95.137 0.000 95.151 0.042 ;
+    END
+  END rw0_rd_out[168]
+  PIN rw0_rd_out[169]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 95.361 0.000 95.375 0.042 ;
+    END
+  END rw0_rd_out[169]
+  PIN rw0_rd_out[170]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 95.585 0.000 95.599 0.042 ;
+    END
+  END rw0_rd_out[170]
+  PIN rw0_rd_out[171]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 95.809 0.000 95.823 0.042 ;
+    END
+  END rw0_rd_out[171]
+  PIN rw0_rd_out[172]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 96.033 0.000 96.047 0.042 ;
+    END
+  END rw0_rd_out[172]
+  PIN rw0_rd_out[173]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 96.257 0.000 96.271 0.042 ;
+    END
+  END rw0_rd_out[173]
+  PIN rw0_rd_out[174]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 96.481 0.000 96.495 0.042 ;
+    END
+  END rw0_rd_out[174]
+  PIN rw0_rd_out[175]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 96.705 0.000 96.719 0.042 ;
+    END
+  END rw0_rd_out[175]
+  PIN rw0_rd_out[176]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 96.929 0.000 96.943 0.042 ;
+    END
+  END rw0_rd_out[176]
+  PIN rw0_rd_out[177]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 97.153 0.000 97.167 0.042 ;
+    END
+  END rw0_rd_out[177]
+  PIN rw0_rd_out[178]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 97.377 0.000 97.391 0.042 ;
+    END
+  END rw0_rd_out[178]
+  PIN rw0_rd_out[179]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 97.601 0.000 97.615 0.042 ;
+    END
+  END rw0_rd_out[179]
+  PIN rw0_rd_out[180]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 97.825 0.000 97.839 0.042 ;
+    END
+  END rw0_rd_out[180]
+  PIN rw0_rd_out[181]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 98.049 0.000 98.063 0.042 ;
+    END
+  END rw0_rd_out[181]
+  PIN rw0_rd_out[182]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 98.273 0.000 98.287 0.042 ;
+    END
+  END rw0_rd_out[182]
+  PIN rw0_rd_out[183]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 98.497 0.000 98.511 0.042 ;
+    END
+  END rw0_rd_out[183]
+  PIN rw0_rd_out[184]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 98.721 0.000 98.735 0.042 ;
+    END
+  END rw0_rd_out[184]
+  PIN rw0_rd_out[185]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 98.945 0.000 98.959 0.042 ;
+    END
+  END rw0_rd_out[185]
+  PIN rw0_rd_out[186]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 99.169 0.000 99.183 0.042 ;
+    END
+  END rw0_rd_out[186]
+  PIN rw0_rd_out[187]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 99.393 0.000 99.407 0.042 ;
+    END
+  END rw0_rd_out[187]
+  PIN rw0_rd_out[188]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 99.617 0.000 99.631 0.042 ;
+    END
+  END rw0_rd_out[188]
+  PIN rw0_rd_out[189]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 99.841 0.000 99.855 0.042 ;
+    END
+  END rw0_rd_out[189]
+  PIN rw0_rd_out[190]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 100.065 0.000 100.079 0.042 ;
+    END
+  END rw0_rd_out[190]
+  PIN rw0_rd_out[191]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 100.289 0.000 100.303 0.042 ;
+    END
+  END rw0_rd_out[191]
+  PIN rw0_rd_out[192]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 100.513 0.000 100.527 0.042 ;
+    END
+  END rw0_rd_out[192]
+  PIN rw0_rd_out[193]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 100.737 0.000 100.751 0.042 ;
+    END
+  END rw0_rd_out[193]
+  PIN rw0_rd_out[194]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 100.961 0.000 100.975 0.042 ;
+    END
+  END rw0_rd_out[194]
+  PIN rw0_rd_out[195]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 101.185 0.000 101.199 0.042 ;
+    END
+  END rw0_rd_out[195]
+  PIN rw0_rd_out[196]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 101.409 0.000 101.423 0.042 ;
+    END
+  END rw0_rd_out[196]
+  PIN rw0_rd_out[197]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 101.633 0.000 101.647 0.042 ;
+    END
+  END rw0_rd_out[197]
+  PIN rw0_rd_out[198]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 101.857 0.000 101.871 0.042 ;
+    END
+  END rw0_rd_out[198]
+  PIN rw0_rd_out[199]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 102.081 0.000 102.095 0.042 ;
+    END
+  END rw0_rd_out[199]
+  PIN rw0_rd_out[200]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 102.305 0.000 102.319 0.042 ;
+    END
+  END rw0_rd_out[200]
+  PIN rw0_rd_out[201]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 102.529 0.000 102.543 0.042 ;
+    END
+  END rw0_rd_out[201]
+  PIN rw0_rd_out[202]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 102.753 0.000 102.767 0.042 ;
+    END
+  END rw0_rd_out[202]
+  PIN rw0_rd_out[203]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 102.977 0.000 102.991 0.042 ;
+    END
+  END rw0_rd_out[203]
+  PIN rw0_rd_out[204]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 103.201 0.000 103.215 0.042 ;
+    END
+  END rw0_rd_out[204]
+  PIN rw0_rd_out[205]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 103.425 0.000 103.439 0.042 ;
+    END
+  END rw0_rd_out[205]
+  PIN rw0_rd_out[206]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 103.649 0.000 103.663 0.042 ;
+    END
+  END rw0_rd_out[206]
+  PIN rw0_rd_out[207]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 103.873 0.000 103.887 0.042 ;
+    END
+  END rw0_rd_out[207]
+  PIN rw0_rd_out[208]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 104.097 0.000 104.111 0.042 ;
+    END
+  END rw0_rd_out[208]
+  PIN rw0_rd_out[209]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 104.321 0.000 104.335 0.042 ;
+    END
+  END rw0_rd_out[209]
+  PIN rw0_rd_out[210]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 104.545 0.000 104.559 0.042 ;
+    END
+  END rw0_rd_out[210]
+  PIN rw0_rd_out[211]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 104.769 0.000 104.783 0.042 ;
+    END
+  END rw0_rd_out[211]
+  PIN rw0_rd_out[212]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 104.993 0.000 105.007 0.042 ;
+    END
+  END rw0_rd_out[212]
+  PIN rw0_rd_out[213]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 105.217 0.000 105.231 0.042 ;
+    END
+  END rw0_rd_out[213]
+  PIN rw0_rd_out[214]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 105.441 0.000 105.455 0.042 ;
+    END
+  END rw0_rd_out[214]
+  PIN rw0_rd_out[215]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 105.665 0.000 105.679 0.042 ;
+    END
+  END rw0_rd_out[215]
+  PIN rw0_rd_out[216]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 105.889 0.000 105.903 0.042 ;
+    END
+  END rw0_rd_out[216]
+  PIN rw0_rd_out[217]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 106.113 0.000 106.127 0.042 ;
+    END
+  END rw0_rd_out[217]
+  PIN rw0_rd_out[218]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 106.337 0.000 106.351 0.042 ;
+    END
+  END rw0_rd_out[218]
+  PIN rw0_rd_out[219]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 106.561 0.000 106.575 0.042 ;
+    END
+  END rw0_rd_out[219]
+  PIN rw0_rd_out[220]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 106.785 0.000 106.799 0.042 ;
+    END
+  END rw0_rd_out[220]
+  PIN rw0_rd_out[221]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 107.009 0.000 107.023 0.042 ;
+    END
+  END rw0_rd_out[221]
+  PIN rw0_rd_out[222]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 107.233 0.000 107.247 0.042 ;
+    END
+  END rw0_rd_out[222]
+  PIN rw0_rd_out[223]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 107.457 0.000 107.471 0.042 ;
+    END
+  END rw0_rd_out[223]
+  PIN rw0_rd_out[224]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 107.681 0.000 107.695 0.042 ;
+    END
+  END rw0_rd_out[224]
+  PIN rw0_rd_out[225]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 107.905 0.000 107.919 0.042 ;
+    END
+  END rw0_rd_out[225]
+  PIN rw0_rd_out[226]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 108.129 0.000 108.143 0.042 ;
+    END
+  END rw0_rd_out[226]
+  PIN rw0_rd_out[227]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 108.353 0.000 108.367 0.042 ;
+    END
+  END rw0_rd_out[227]
+  PIN rw0_rd_out[228]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 108.577 0.000 108.591 0.042 ;
+    END
+  END rw0_rd_out[228]
+  PIN rw0_rd_out[229]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 108.801 0.000 108.815 0.042 ;
+    END
+  END rw0_rd_out[229]
+  PIN rw0_rd_out[230]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 109.025 0.000 109.039 0.042 ;
+    END
+  END rw0_rd_out[230]
+  PIN rw0_rd_out[231]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 109.249 0.000 109.263 0.042 ;
+    END
+  END rw0_rd_out[231]
+  PIN rw0_rd_out[232]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 109.473 0.000 109.487 0.042 ;
+    END
+  END rw0_rd_out[232]
+  PIN rw0_rd_out[233]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 109.697 0.000 109.711 0.042 ;
+    END
+  END rw0_rd_out[233]
+  PIN rw0_rd_out[234]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 109.921 0.000 109.935 0.042 ;
+    END
+  END rw0_rd_out[234]
+  PIN rw0_rd_out[235]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 110.145 0.000 110.159 0.042 ;
+    END
+  END rw0_rd_out[235]
+  PIN rw0_rd_out[236]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 110.369 0.000 110.383 0.042 ;
+    END
+  END rw0_rd_out[236]
+  PIN rw0_rd_out[237]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 110.593 0.000 110.607 0.042 ;
+    END
+  END rw0_rd_out[237]
+  PIN rw0_rd_out[238]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 110.817 0.000 110.831 0.042 ;
+    END
+  END rw0_rd_out[238]
+  PIN rw0_rd_out[239]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 111.041 0.000 111.055 0.042 ;
+    END
+  END rw0_rd_out[239]
+  PIN rw0_rd_out[240]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 111.265 0.000 111.279 0.042 ;
+    END
+  END rw0_rd_out[240]
+  PIN rw0_rd_out[241]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 111.489 0.000 111.503 0.042 ;
+    END
+  END rw0_rd_out[241]
+  PIN rw0_rd_out[242]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 111.713 0.000 111.727 0.042 ;
+    END
+  END rw0_rd_out[242]
+  PIN rw0_rd_out[243]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 111.937 0.000 111.951 0.042 ;
+    END
+  END rw0_rd_out[243]
+  PIN rw0_rd_out[244]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 112.161 0.000 112.175 0.042 ;
+    END
+  END rw0_rd_out[244]
+  PIN rw0_rd_out[245]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 112.385 0.000 112.399 0.042 ;
+    END
+  END rw0_rd_out[245]
+  PIN rw0_rd_out[246]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 112.609 0.000 112.623 0.042 ;
+    END
+  END rw0_rd_out[246]
+  PIN rw0_rd_out[247]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 112.833 0.000 112.847 0.042 ;
+    END
+  END rw0_rd_out[247]
+  PIN rw0_rd_out[248]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 113.057 0.000 113.071 0.042 ;
+    END
+  END rw0_rd_out[248]
+  PIN rw0_rd_out[249]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 113.281 0.000 113.295 0.042 ;
+    END
+  END rw0_rd_out[249]
+  PIN rw0_rd_out[250]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 113.505 0.000 113.519 0.042 ;
+    END
+  END rw0_rd_out[250]
+  PIN rw0_rd_out[251]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 113.729 0.000 113.743 0.042 ;
+    END
+  END rw0_rd_out[251]
+  PIN rw0_rd_out[252]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 113.953 0.000 113.967 0.042 ;
+    END
+  END rw0_rd_out[252]
+  PIN rw0_rd_out[253]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 114.177 0.000 114.191 0.042 ;
+    END
+  END rw0_rd_out[253]
+  PIN rw0_rd_out[254]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 114.401 0.000 114.415 0.042 ;
+    END
+  END rw0_rd_out[254]
+  PIN rw0_rd_out[255]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 114.625 0.000 114.639 0.042 ;
+    END
+  END rw0_rd_out[255]
+  PIN rw0_rd_out[256]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 0.161 36.678 0.175 36.720 ;
+    END
+  END rw0_rd_out[256]
+  PIN rw0_rd_out[257]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 0.609 36.678 0.623 36.720 ;
+    END
+  END rw0_rd_out[257]
+  PIN rw0_rd_out[258]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 1.057 36.678 1.071 36.720 ;
+    END
+  END rw0_rd_out[258]
+  PIN rw0_rd_out[259]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 1.505 36.678 1.519 36.720 ;
+    END
+  END rw0_rd_out[259]
+  PIN rw0_rd_out[260]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 1.953 36.678 1.967 36.720 ;
+    END
+  END rw0_rd_out[260]
+  PIN rw0_rd_out[261]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 2.401 36.678 2.415 36.720 ;
+    END
+  END rw0_rd_out[261]
+  PIN rw0_rd_out[262]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 2.849 36.678 2.863 36.720 ;
+    END
+  END rw0_rd_out[262]
+  PIN rw0_rd_out[263]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 3.297 36.678 3.311 36.720 ;
+    END
+  END rw0_rd_out[263]
+  PIN rw0_rd_out[264]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 3.745 36.678 3.759 36.720 ;
+    END
+  END rw0_rd_out[264]
+  PIN rw0_rd_out[265]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 4.193 36.678 4.207 36.720 ;
+    END
+  END rw0_rd_out[265]
+  PIN rw0_rd_out[266]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 4.641 36.678 4.655 36.720 ;
+    END
+  END rw0_rd_out[266]
+  PIN rw0_rd_out[267]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 5.089 36.678 5.103 36.720 ;
+    END
+  END rw0_rd_out[267]
+  PIN rw0_rd_out[268]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 5.537 36.678 5.551 36.720 ;
+    END
+  END rw0_rd_out[268]
+  PIN rw0_rd_out[269]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 5.985 36.678 5.999 36.720 ;
+    END
+  END rw0_rd_out[269]
+  PIN rw0_rd_out[270]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 6.433 36.678 6.447 36.720 ;
+    END
+  END rw0_rd_out[270]
+  PIN rw0_rd_out[271]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 6.881 36.678 6.895 36.720 ;
+    END
+  END rw0_rd_out[271]
+  PIN rw0_rd_out[272]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 7.329 36.678 7.343 36.720 ;
+    END
+  END rw0_rd_out[272]
+  PIN rw0_rd_out[273]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 7.777 36.678 7.791 36.720 ;
+    END
+  END rw0_rd_out[273]
+  PIN rw0_rd_out[274]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 8.225 36.678 8.239 36.720 ;
+    END
+  END rw0_rd_out[274]
+  PIN rw0_rd_out[275]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 8.673 36.678 8.687 36.720 ;
+    END
+  END rw0_rd_out[275]
+  PIN rw0_rd_out[276]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 9.121 36.678 9.135 36.720 ;
+    END
+  END rw0_rd_out[276]
+  PIN rw0_rd_out[277]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 9.569 36.678 9.583 36.720 ;
+    END
+  END rw0_rd_out[277]
+  PIN rw0_rd_out[278]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 10.017 36.678 10.031 36.720 ;
+    END
+  END rw0_rd_out[278]
+  PIN rw0_rd_out[279]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 10.465 36.678 10.479 36.720 ;
+    END
+  END rw0_rd_out[279]
+  PIN rw0_rd_out[280]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 10.913 36.678 10.927 36.720 ;
+    END
+  END rw0_rd_out[280]
+  PIN rw0_rd_out[281]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 11.361 36.678 11.375 36.720 ;
+    END
+  END rw0_rd_out[281]
+  PIN rw0_rd_out[282]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 11.809 36.678 11.823 36.720 ;
+    END
+  END rw0_rd_out[282]
+  PIN rw0_rd_out[283]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 12.257 36.678 12.271 36.720 ;
+    END
+  END rw0_rd_out[283]
+  PIN rw0_rd_out[284]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 12.705 36.678 12.719 36.720 ;
+    END
+  END rw0_rd_out[284]
+  PIN rw0_rd_out[285]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 13.153 36.678 13.167 36.720 ;
+    END
+  END rw0_rd_out[285]
+  PIN rw0_rd_out[286]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 13.601 36.678 13.615 36.720 ;
+    END
+  END rw0_rd_out[286]
+  PIN rw0_rd_out[287]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 14.049 36.678 14.063 36.720 ;
+    END
+  END rw0_rd_out[287]
+  PIN rw0_rd_out[288]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 14.497 36.678 14.511 36.720 ;
+    END
+  END rw0_rd_out[288]
+  PIN rw0_rd_out[289]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 14.945 36.678 14.959 36.720 ;
+    END
+  END rw0_rd_out[289]
+  PIN rw0_rd_out[290]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 15.393 36.678 15.407 36.720 ;
+    END
+  END rw0_rd_out[290]
+  PIN rw0_rd_out[291]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 15.841 36.678 15.855 36.720 ;
+    END
+  END rw0_rd_out[291]
+  PIN rw0_rd_out[292]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 16.289 36.678 16.303 36.720 ;
+    END
+  END rw0_rd_out[292]
+  PIN rw0_rd_out[293]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 16.737 36.678 16.751 36.720 ;
+    END
+  END rw0_rd_out[293]
+  PIN rw0_rd_out[294]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 17.185 36.678 17.199 36.720 ;
+    END
+  END rw0_rd_out[294]
+  PIN rw0_rd_out[295]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 17.633 36.678 17.647 36.720 ;
+    END
+  END rw0_rd_out[295]
+  PIN rw0_rd_out[296]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 18.081 36.678 18.095 36.720 ;
+    END
+  END rw0_rd_out[296]
+  PIN rw0_rd_out[297]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 18.529 36.678 18.543 36.720 ;
+    END
+  END rw0_rd_out[297]
+  PIN rw0_rd_out[298]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 18.977 36.678 18.991 36.720 ;
+    END
+  END rw0_rd_out[298]
+  PIN rw0_rd_out[299]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 19.425 36.678 19.439 36.720 ;
+    END
+  END rw0_rd_out[299]
+  PIN rw0_rd_out[300]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 19.873 36.678 19.887 36.720 ;
+    END
+  END rw0_rd_out[300]
+  PIN rw0_rd_out[301]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 20.321 36.678 20.335 36.720 ;
+    END
+  END rw0_rd_out[301]
+  PIN rw0_rd_out[302]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 20.769 36.678 20.783 36.720 ;
+    END
+  END rw0_rd_out[302]
+  PIN rw0_rd_out[303]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 21.217 36.678 21.231 36.720 ;
+    END
+  END rw0_rd_out[303]
+  PIN rw0_rd_out[304]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 21.665 36.678 21.679 36.720 ;
+    END
+  END rw0_rd_out[304]
+  PIN rw0_rd_out[305]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 22.113 36.678 22.127 36.720 ;
+    END
+  END rw0_rd_out[305]
+  PIN rw0_rd_out[306]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 22.561 36.678 22.575 36.720 ;
+    END
+  END rw0_rd_out[306]
+  PIN rw0_rd_out[307]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 23.009 36.678 23.023 36.720 ;
+    END
+  END rw0_rd_out[307]
+  PIN rw0_rd_out[308]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 23.457 36.678 23.471 36.720 ;
+    END
+  END rw0_rd_out[308]
+  PIN rw0_rd_out[309]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 23.905 36.678 23.919 36.720 ;
+    END
+  END rw0_rd_out[309]
+  PIN rw0_rd_out[310]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 24.353 36.678 24.367 36.720 ;
+    END
+  END rw0_rd_out[310]
+  PIN rw0_rd_out[311]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 24.801 36.678 24.815 36.720 ;
+    END
+  END rw0_rd_out[311]
+  PIN rw0_rd_out[312]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 25.249 36.678 25.263 36.720 ;
+    END
+  END rw0_rd_out[312]
+  PIN rw0_rd_out[313]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 25.697 36.678 25.711 36.720 ;
+    END
+  END rw0_rd_out[313]
+  PIN rw0_rd_out[314]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 26.145 36.678 26.159 36.720 ;
+    END
+  END rw0_rd_out[314]
+  PIN rw0_rd_out[315]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 26.593 36.678 26.607 36.720 ;
+    END
+  END rw0_rd_out[315]
+  PIN rw0_rd_out[316]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 27.041 36.678 27.055 36.720 ;
+    END
+  END rw0_rd_out[316]
+  PIN rw0_rd_out[317]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 27.489 36.678 27.503 36.720 ;
+    END
+  END rw0_rd_out[317]
+  PIN rw0_rd_out[318]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 27.937 36.678 27.951 36.720 ;
+    END
+  END rw0_rd_out[318]
+  PIN rw0_rd_out[319]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 28.385 36.678 28.399 36.720 ;
+    END
+  END rw0_rd_out[319]
+  PIN rw0_rd_out[320]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 28.833 36.678 28.847 36.720 ;
+    END
+  END rw0_rd_out[320]
+  PIN rw0_rd_out[321]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 29.281 36.678 29.295 36.720 ;
+    END
+  END rw0_rd_out[321]
+  PIN rw0_rd_out[322]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 29.729 36.678 29.743 36.720 ;
+    END
+  END rw0_rd_out[322]
+  PIN rw0_rd_out[323]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 30.177 36.678 30.191 36.720 ;
+    END
+  END rw0_rd_out[323]
+  PIN rw0_rd_out[324]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 30.625 36.678 30.639 36.720 ;
+    END
+  END rw0_rd_out[324]
+  PIN rw0_rd_out[325]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 31.073 36.678 31.087 36.720 ;
+    END
+  END rw0_rd_out[325]
+  PIN rw0_rd_out[326]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 31.521 36.678 31.535 36.720 ;
+    END
+  END rw0_rd_out[326]
+  PIN rw0_rd_out[327]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 31.969 36.678 31.983 36.720 ;
+    END
+  END rw0_rd_out[327]
+  PIN rw0_rd_out[328]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 32.417 36.678 32.431 36.720 ;
+    END
+  END rw0_rd_out[328]
+  PIN rw0_rd_out[329]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 32.865 36.678 32.879 36.720 ;
+    END
+  END rw0_rd_out[329]
+  PIN rw0_rd_out[330]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 33.313 36.678 33.327 36.720 ;
+    END
+  END rw0_rd_out[330]
+  PIN rw0_rd_out[331]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 33.761 36.678 33.775 36.720 ;
+    END
+  END rw0_rd_out[331]
+  PIN rw0_rd_out[332]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 34.209 36.678 34.223 36.720 ;
+    END
+  END rw0_rd_out[332]
+  PIN rw0_rd_out[333]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 34.657 36.678 34.671 36.720 ;
+    END
+  END rw0_rd_out[333]
+  PIN rw0_rd_out[334]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 35.105 36.678 35.119 36.720 ;
+    END
+  END rw0_rd_out[334]
+  PIN rw0_rd_out[335]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 35.553 36.678 35.567 36.720 ;
+    END
+  END rw0_rd_out[335]
+  PIN rw0_rd_out[336]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 36.001 36.678 36.015 36.720 ;
+    END
+  END rw0_rd_out[336]
+  PIN rw0_rd_out[337]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 36.449 36.678 36.463 36.720 ;
+    END
+  END rw0_rd_out[337]
+  PIN rw0_rd_out[338]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 36.897 36.678 36.911 36.720 ;
+    END
+  END rw0_rd_out[338]
+  PIN rw0_rd_out[339]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 37.345 36.678 37.359 36.720 ;
+    END
+  END rw0_rd_out[339]
+  PIN rw0_rd_out[340]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 37.793 36.678 37.807 36.720 ;
+    END
+  END rw0_rd_out[340]
+  PIN rw0_rd_out[341]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 38.241 36.678 38.255 36.720 ;
+    END
+  END rw0_rd_out[341]
+  PIN rw0_rd_out[342]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 38.689 36.678 38.703 36.720 ;
+    END
+  END rw0_rd_out[342]
+  PIN rw0_rd_out[343]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 39.137 36.678 39.151 36.720 ;
+    END
+  END rw0_rd_out[343]
+  PIN rw0_rd_out[344]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 39.585 36.678 39.599 36.720 ;
+    END
+  END rw0_rd_out[344]
+  PIN rw0_rd_out[345]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 40.033 36.678 40.047 36.720 ;
+    END
+  END rw0_rd_out[345]
+  PIN rw0_rd_out[346]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 40.481 36.678 40.495 36.720 ;
+    END
+  END rw0_rd_out[346]
+  PIN rw0_rd_out[347]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 40.929 36.678 40.943 36.720 ;
+    END
+  END rw0_rd_out[347]
+  PIN rw0_rd_out[348]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 41.377 36.678 41.391 36.720 ;
+    END
+  END rw0_rd_out[348]
+  PIN rw0_rd_out[349]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 41.825 36.678 41.839 36.720 ;
+    END
+  END rw0_rd_out[349]
+  PIN rw0_rd_out[350]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 42.273 36.678 42.287 36.720 ;
+    END
+  END rw0_rd_out[350]
+  PIN rw0_rd_out[351]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 42.721 36.678 42.735 36.720 ;
+    END
+  END rw0_rd_out[351]
+  PIN rw0_rd_out[352]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 43.169 36.678 43.183 36.720 ;
+    END
+  END rw0_rd_out[352]
+  PIN rw0_rd_out[353]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 43.617 36.678 43.631 36.720 ;
+    END
+  END rw0_rd_out[353]
+  PIN rw0_rd_out[354]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 44.065 36.678 44.079 36.720 ;
+    END
+  END rw0_rd_out[354]
+  PIN rw0_rd_out[355]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 44.513 36.678 44.527 36.720 ;
+    END
+  END rw0_rd_out[355]
+  PIN rw0_rd_out[356]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 44.961 36.678 44.975 36.720 ;
+    END
+  END rw0_rd_out[356]
+  PIN rw0_rd_out[357]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 45.409 36.678 45.423 36.720 ;
+    END
+  END rw0_rd_out[357]
+  PIN rw0_rd_out[358]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 45.857 36.678 45.871 36.720 ;
+    END
+  END rw0_rd_out[358]
+  PIN rw0_rd_out[359]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 46.305 36.678 46.319 36.720 ;
+    END
+  END rw0_rd_out[359]
+  PIN rw0_rd_out[360]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 46.753 36.678 46.767 36.720 ;
+    END
+  END rw0_rd_out[360]
+  PIN rw0_rd_out[361]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 47.201 36.678 47.215 36.720 ;
+    END
+  END rw0_rd_out[361]
+  PIN rw0_rd_out[362]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 47.649 36.678 47.663 36.720 ;
+    END
+  END rw0_rd_out[362]
+  PIN rw0_rd_out[363]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 48.097 36.678 48.111 36.720 ;
+    END
+  END rw0_rd_out[363]
+  PIN rw0_rd_out[364]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 48.545 36.678 48.559 36.720 ;
+    END
+  END rw0_rd_out[364]
+  PIN rw0_rd_out[365]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 48.993 36.678 49.007 36.720 ;
+    END
+  END rw0_rd_out[365]
+  PIN rw0_rd_out[366]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 49.441 36.678 49.455 36.720 ;
+    END
+  END rw0_rd_out[366]
+  PIN rw0_rd_out[367]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 49.889 36.678 49.903 36.720 ;
+    END
+  END rw0_rd_out[367]
+  PIN rw0_rd_out[368]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 50.337 36.678 50.351 36.720 ;
+    END
+  END rw0_rd_out[368]
+  PIN rw0_rd_out[369]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 50.785 36.678 50.799 36.720 ;
+    END
+  END rw0_rd_out[369]
+  PIN rw0_rd_out[370]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 51.233 36.678 51.247 36.720 ;
+    END
+  END rw0_rd_out[370]
+  PIN rw0_rd_out[371]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 51.681 36.678 51.695 36.720 ;
+    END
+  END rw0_rd_out[371]
+  PIN rw0_rd_out[372]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 52.129 36.678 52.143 36.720 ;
+    END
+  END rw0_rd_out[372]
+  PIN rw0_rd_out[373]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 52.577 36.678 52.591 36.720 ;
+    END
+  END rw0_rd_out[373]
+  PIN rw0_rd_out[374]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 53.025 36.678 53.039 36.720 ;
+    END
+  END rw0_rd_out[374]
+  PIN rw0_rd_out[375]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 53.473 36.678 53.487 36.720 ;
+    END
+  END rw0_rd_out[375]
+  PIN rw0_rd_out[376]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 53.921 36.678 53.935 36.720 ;
+    END
+  END rw0_rd_out[376]
+  PIN rw0_rd_out[377]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 54.369 36.678 54.383 36.720 ;
+    END
+  END rw0_rd_out[377]
+  PIN rw0_rd_out[378]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 54.817 36.678 54.831 36.720 ;
+    END
+  END rw0_rd_out[378]
+  PIN rw0_rd_out[379]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 55.265 36.678 55.279 36.720 ;
+    END
+  END rw0_rd_out[379]
+  PIN rw0_rd_out[380]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 55.713 36.678 55.727 36.720 ;
+    END
+  END rw0_rd_out[380]
+  PIN rw0_rd_out[381]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 56.161 36.678 56.175 36.720 ;
+    END
+  END rw0_rd_out[381]
+  PIN rw0_rd_out[382]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 56.609 36.678 56.623 36.720 ;
+    END
+  END rw0_rd_out[382]
+  PIN rw0_rd_out[383]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 57.057 36.678 57.071 36.720 ;
+    END
+  END rw0_rd_out[383]
+  PIN rw0_rd_out[384]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 57.505 36.678 57.519 36.720 ;
+    END
+  END rw0_rd_out[384]
+  PIN rw0_rd_out[385]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 57.953 36.678 57.967 36.720 ;
+    END
+  END rw0_rd_out[385]
+  PIN rw0_rd_out[386]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 58.401 36.678 58.415 36.720 ;
+    END
+  END rw0_rd_out[386]
+  PIN rw0_rd_out[387]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 58.849 36.678 58.863 36.720 ;
+    END
+  END rw0_rd_out[387]
+  PIN rw0_rd_out[388]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 59.297 36.678 59.311 36.720 ;
+    END
+  END rw0_rd_out[388]
+  PIN rw0_rd_out[389]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 59.745 36.678 59.759 36.720 ;
+    END
+  END rw0_rd_out[389]
+  PIN rw0_rd_out[390]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 60.193 36.678 60.207 36.720 ;
+    END
+  END rw0_rd_out[390]
+  PIN rw0_rd_out[391]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 60.641 36.678 60.655 36.720 ;
+    END
+  END rw0_rd_out[391]
+  PIN rw0_rd_out[392]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 61.089 36.678 61.103 36.720 ;
+    END
+  END rw0_rd_out[392]
+  PIN rw0_rd_out[393]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 61.537 36.678 61.551 36.720 ;
+    END
+  END rw0_rd_out[393]
+  PIN rw0_rd_out[394]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 61.985 36.678 61.999 36.720 ;
+    END
+  END rw0_rd_out[394]
+  PIN rw0_rd_out[395]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 62.433 36.678 62.447 36.720 ;
+    END
+  END rw0_rd_out[395]
+  PIN rw0_rd_out[396]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 62.881 36.678 62.895 36.720 ;
+    END
+  END rw0_rd_out[396]
+  PIN rw0_rd_out[397]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 63.329 36.678 63.343 36.720 ;
+    END
+  END rw0_rd_out[397]
+  PIN rw0_rd_out[398]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 63.777 36.678 63.791 36.720 ;
+    END
+  END rw0_rd_out[398]
+  PIN rw0_rd_out[399]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 64.225 36.678 64.239 36.720 ;
+    END
+  END rw0_rd_out[399]
+  PIN rw0_rd_out[400]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 64.673 36.678 64.687 36.720 ;
+    END
+  END rw0_rd_out[400]
+  PIN rw0_rd_out[401]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 65.121 36.678 65.135 36.720 ;
+    END
+  END rw0_rd_out[401]
+  PIN rw0_rd_out[402]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 65.569 36.678 65.583 36.720 ;
+    END
+  END rw0_rd_out[402]
+  PIN rw0_rd_out[403]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 66.017 36.678 66.031 36.720 ;
+    END
+  END rw0_rd_out[403]
+  PIN rw0_rd_out[404]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 66.465 36.678 66.479 36.720 ;
+    END
+  END rw0_rd_out[404]
+  PIN rw0_rd_out[405]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 66.913 36.678 66.927 36.720 ;
+    END
+  END rw0_rd_out[405]
+  PIN rw0_rd_out[406]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 67.361 36.678 67.375 36.720 ;
+    END
+  END rw0_rd_out[406]
+  PIN rw0_rd_out[407]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 67.809 36.678 67.823 36.720 ;
+    END
+  END rw0_rd_out[407]
+  PIN rw0_rd_out[408]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 68.257 36.678 68.271 36.720 ;
+    END
+  END rw0_rd_out[408]
+  PIN rw0_rd_out[409]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 68.705 36.678 68.719 36.720 ;
+    END
+  END rw0_rd_out[409]
+  PIN rw0_rd_out[410]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 69.153 36.678 69.167 36.720 ;
+    END
+  END rw0_rd_out[410]
+  PIN rw0_rd_out[411]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 69.601 36.678 69.615 36.720 ;
+    END
+  END rw0_rd_out[411]
+  PIN rw0_rd_out[412]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 70.049 36.678 70.063 36.720 ;
+    END
+  END rw0_rd_out[412]
+  PIN rw0_rd_out[413]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 70.497 36.678 70.511 36.720 ;
+    END
+  END rw0_rd_out[413]
+  PIN rw0_rd_out[414]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 70.945 36.678 70.959 36.720 ;
+    END
+  END rw0_rd_out[414]
+  PIN rw0_rd_out[415]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 71.393 36.678 71.407 36.720 ;
+    END
+  END rw0_rd_out[415]
+  PIN rw0_rd_out[416]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 71.841 36.678 71.855 36.720 ;
+    END
+  END rw0_rd_out[416]
+  PIN rw0_rd_out[417]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 72.289 36.678 72.303 36.720 ;
+    END
+  END rw0_rd_out[417]
+  PIN rw0_rd_out[418]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 72.737 36.678 72.751 36.720 ;
+    END
+  END rw0_rd_out[418]
+  PIN rw0_rd_out[419]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 73.185 36.678 73.199 36.720 ;
+    END
+  END rw0_rd_out[419]
+  PIN rw0_rd_out[420]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 73.633 36.678 73.647 36.720 ;
+    END
+  END rw0_rd_out[420]
+  PIN rw0_rd_out[421]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 74.081 36.678 74.095 36.720 ;
+    END
+  END rw0_rd_out[421]
+  PIN rw0_rd_out[422]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 74.529 36.678 74.543 36.720 ;
+    END
+  END rw0_rd_out[422]
+  PIN rw0_rd_out[423]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 74.977 36.678 74.991 36.720 ;
+    END
+  END rw0_rd_out[423]
+  PIN rw0_rd_out[424]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 75.425 36.678 75.439 36.720 ;
+    END
+  END rw0_rd_out[424]
+  PIN rw0_rd_out[425]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 75.873 36.678 75.887 36.720 ;
+    END
+  END rw0_rd_out[425]
+  PIN rw0_rd_out[426]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 76.321 36.678 76.335 36.720 ;
+    END
+  END rw0_rd_out[426]
+  PIN rw0_rd_out[427]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 76.769 36.678 76.783 36.720 ;
+    END
+  END rw0_rd_out[427]
+  PIN rw0_rd_out[428]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 77.217 36.678 77.231 36.720 ;
+    END
+  END rw0_rd_out[428]
+  PIN rw0_rd_out[429]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 77.665 36.678 77.679 36.720 ;
+    END
+  END rw0_rd_out[429]
+  PIN rw0_rd_out[430]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 78.113 36.678 78.127 36.720 ;
+    END
+  END rw0_rd_out[430]
+  PIN rw0_rd_out[431]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 78.561 36.678 78.575 36.720 ;
+    END
+  END rw0_rd_out[431]
+  PIN rw0_rd_out[432]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 79.009 36.678 79.023 36.720 ;
+    END
+  END rw0_rd_out[432]
+  PIN rw0_rd_out[433]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 79.457 36.678 79.471 36.720 ;
+    END
+  END rw0_rd_out[433]
+  PIN rw0_rd_out[434]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 79.905 36.678 79.919 36.720 ;
+    END
+  END rw0_rd_out[434]
+  PIN rw0_rd_out[435]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 80.353 36.678 80.367 36.720 ;
+    END
+  END rw0_rd_out[435]
+  PIN rw0_rd_out[436]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 80.801 36.678 80.815 36.720 ;
+    END
+  END rw0_rd_out[436]
+  PIN rw0_rd_out[437]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 81.249 36.678 81.263 36.720 ;
+    END
+  END rw0_rd_out[437]
+  PIN rw0_rd_out[438]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 81.697 36.678 81.711 36.720 ;
+    END
+  END rw0_rd_out[438]
+  PIN rw0_rd_out[439]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 82.145 36.678 82.159 36.720 ;
+    END
+  END rw0_rd_out[439]
+  PIN rw0_rd_out[440]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 82.593 36.678 82.607 36.720 ;
+    END
+  END rw0_rd_out[440]
+  PIN rw0_rd_out[441]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 83.041 36.678 83.055 36.720 ;
+    END
+  END rw0_rd_out[441]
+  PIN rw0_rd_out[442]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 83.489 36.678 83.503 36.720 ;
+    END
+  END rw0_rd_out[442]
+  PIN rw0_rd_out[443]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 83.937 36.678 83.951 36.720 ;
+    END
+  END rw0_rd_out[443]
+  PIN rw0_rd_out[444]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 84.385 36.678 84.399 36.720 ;
+    END
+  END rw0_rd_out[444]
+  PIN rw0_rd_out[445]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 84.833 36.678 84.847 36.720 ;
+    END
+  END rw0_rd_out[445]
+  PIN rw0_rd_out[446]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 85.281 36.678 85.295 36.720 ;
+    END
+  END rw0_rd_out[446]
+  PIN rw0_rd_out[447]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 85.729 36.678 85.743 36.720 ;
+    END
+  END rw0_rd_out[447]
+  PIN rw0_rd_out[448]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 86.177 36.678 86.191 36.720 ;
+    END
+  END rw0_rd_out[448]
+  PIN rw0_rd_out[449]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 86.625 36.678 86.639 36.720 ;
+    END
+  END rw0_rd_out[449]
+  PIN rw0_rd_out[450]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 87.073 36.678 87.087 36.720 ;
+    END
+  END rw0_rd_out[450]
+  PIN rw0_rd_out[451]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 87.521 36.678 87.535 36.720 ;
+    END
+  END rw0_rd_out[451]
+  PIN rw0_rd_out[452]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 87.969 36.678 87.983 36.720 ;
+    END
+  END rw0_rd_out[452]
+  PIN rw0_rd_out[453]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 88.417 36.678 88.431 36.720 ;
+    END
+  END rw0_rd_out[453]
+  PIN rw0_rd_out[454]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 88.865 36.678 88.879 36.720 ;
+    END
+  END rw0_rd_out[454]
+  PIN rw0_rd_out[455]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 89.313 36.678 89.327 36.720 ;
+    END
+  END rw0_rd_out[455]
+  PIN rw0_rd_out[456]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 89.761 36.678 89.775 36.720 ;
+    END
+  END rw0_rd_out[456]
+  PIN rw0_rd_out[457]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 90.209 36.678 90.223 36.720 ;
+    END
+  END rw0_rd_out[457]
+  PIN rw0_rd_out[458]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 90.657 36.678 90.671 36.720 ;
+    END
+  END rw0_rd_out[458]
+  PIN rw0_rd_out[459]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 91.105 36.678 91.119 36.720 ;
+    END
+  END rw0_rd_out[459]
+  PIN rw0_rd_out[460]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 91.553 36.678 91.567 36.720 ;
+    END
+  END rw0_rd_out[460]
+  PIN rw0_rd_out[461]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 92.001 36.678 92.015 36.720 ;
+    END
+  END rw0_rd_out[461]
+  PIN rw0_rd_out[462]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 92.449 36.678 92.463 36.720 ;
+    END
+  END rw0_rd_out[462]
+  PIN rw0_rd_out[463]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 92.897 36.678 92.911 36.720 ;
+    END
+  END rw0_rd_out[463]
+  PIN rw0_rd_out[464]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 93.345 36.678 93.359 36.720 ;
+    END
+  END rw0_rd_out[464]
+  PIN rw0_rd_out[465]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 93.793 36.678 93.807 36.720 ;
+    END
+  END rw0_rd_out[465]
+  PIN rw0_rd_out[466]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 94.241 36.678 94.255 36.720 ;
+    END
+  END rw0_rd_out[466]
+  PIN rw0_rd_out[467]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 94.689 36.678 94.703 36.720 ;
+    END
+  END rw0_rd_out[467]
+  PIN rw0_rd_out[468]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 95.137 36.678 95.151 36.720 ;
+    END
+  END rw0_rd_out[468]
+  PIN rw0_rd_out[469]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 95.585 36.678 95.599 36.720 ;
+    END
+  END rw0_rd_out[469]
+  PIN rw0_rd_out[470]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 96.033 36.678 96.047 36.720 ;
+    END
+  END rw0_rd_out[470]
+  PIN rw0_rd_out[471]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 96.481 36.678 96.495 36.720 ;
+    END
+  END rw0_rd_out[471]
+  PIN rw0_rd_out[472]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 96.929 36.678 96.943 36.720 ;
+    END
+  END rw0_rd_out[472]
+  PIN rw0_rd_out[473]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 97.377 36.678 97.391 36.720 ;
+    END
+  END rw0_rd_out[473]
+  PIN rw0_rd_out[474]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 97.825 36.678 97.839 36.720 ;
+    END
+  END rw0_rd_out[474]
+  PIN rw0_rd_out[475]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 98.273 36.678 98.287 36.720 ;
+    END
+  END rw0_rd_out[475]
+  PIN rw0_rd_out[476]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 98.721 36.678 98.735 36.720 ;
+    END
+  END rw0_rd_out[476]
+  PIN rw0_rd_out[477]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 99.169 36.678 99.183 36.720 ;
+    END
+  END rw0_rd_out[477]
+  PIN rw0_rd_out[478]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 99.617 36.678 99.631 36.720 ;
+    END
+  END rw0_rd_out[478]
+  PIN rw0_rd_out[479]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 100.065 36.678 100.079 36.720 ;
+    END
+  END rw0_rd_out[479]
+  PIN rw0_rd_out[480]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 100.513 36.678 100.527 36.720 ;
+    END
+  END rw0_rd_out[480]
+  PIN rw0_rd_out[481]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 100.961 36.678 100.975 36.720 ;
+    END
+  END rw0_rd_out[481]
+  PIN rw0_rd_out[482]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 101.409 36.678 101.423 36.720 ;
+    END
+  END rw0_rd_out[482]
+  PIN rw0_rd_out[483]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 101.857 36.678 101.871 36.720 ;
+    END
+  END rw0_rd_out[483]
+  PIN rw0_rd_out[484]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 102.305 36.678 102.319 36.720 ;
+    END
+  END rw0_rd_out[484]
+  PIN rw0_rd_out[485]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 102.753 36.678 102.767 36.720 ;
+    END
+  END rw0_rd_out[485]
+  PIN rw0_rd_out[486]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 103.201 36.678 103.215 36.720 ;
+    END
+  END rw0_rd_out[486]
+  PIN rw0_rd_out[487]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 103.649 36.678 103.663 36.720 ;
+    END
+  END rw0_rd_out[487]
+  PIN rw0_rd_out[488]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 104.097 36.678 104.111 36.720 ;
+    END
+  END rw0_rd_out[488]
+  PIN rw0_rd_out[489]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 104.545 36.678 104.559 36.720 ;
+    END
+  END rw0_rd_out[489]
+  PIN rw0_rd_out[490]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 104.993 36.678 105.007 36.720 ;
+    END
+  END rw0_rd_out[490]
+  PIN rw0_rd_out[491]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 105.441 36.678 105.455 36.720 ;
+    END
+  END rw0_rd_out[491]
+  PIN rw0_rd_out[492]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 105.889 36.678 105.903 36.720 ;
+    END
+  END rw0_rd_out[492]
+  PIN rw0_rd_out[493]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 106.337 36.678 106.351 36.720 ;
+    END
+  END rw0_rd_out[493]
+  PIN rw0_rd_out[494]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 106.785 36.678 106.799 36.720 ;
+    END
+  END rw0_rd_out[494]
+  PIN rw0_rd_out[495]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 107.233 36.678 107.247 36.720 ;
+    END
+  END rw0_rd_out[495]
+  PIN rw0_rd_out[496]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 107.681 36.678 107.695 36.720 ;
+    END
+  END rw0_rd_out[496]
+  PIN rw0_rd_out[497]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 108.129 36.678 108.143 36.720 ;
+    END
+  END rw0_rd_out[497]
+  PIN rw0_rd_out[498]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 108.577 36.678 108.591 36.720 ;
+    END
+  END rw0_rd_out[498]
+  PIN rw0_rd_out[499]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 109.025 36.678 109.039 36.720 ;
+    END
+  END rw0_rd_out[499]
+  PIN rw0_rd_out[500]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 109.473 36.678 109.487 36.720 ;
+    END
+  END rw0_rd_out[500]
+  PIN rw0_rd_out[501]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 109.921 36.678 109.935 36.720 ;
+    END
+  END rw0_rd_out[501]
+  PIN rw0_rd_out[502]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 110.369 36.678 110.383 36.720 ;
+    END
+  END rw0_rd_out[502]
+  PIN rw0_rd_out[503]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 110.817 36.678 110.831 36.720 ;
+    END
+  END rw0_rd_out[503]
+  PIN rw0_rd_out[504]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 111.265 36.678 111.279 36.720 ;
+    END
+  END rw0_rd_out[504]
+  PIN rw0_rd_out[505]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 111.713 36.678 111.727 36.720 ;
+    END
+  END rw0_rd_out[505]
+  PIN rw0_rd_out[506]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 112.161 36.678 112.175 36.720 ;
+    END
+  END rw0_rd_out[506]
+  PIN rw0_rd_out[507]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 112.609 36.678 112.623 36.720 ;
+    END
+  END rw0_rd_out[507]
+  PIN rw0_rd_out[508]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 113.057 36.678 113.071 36.720 ;
+    END
+  END rw0_rd_out[508]
+  PIN rw0_rd_out[509]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 113.505 36.678 113.519 36.720 ;
+    END
+  END rw0_rd_out[509]
+  PIN rw0_rd_out[510]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 113.953 36.678 113.967 36.720 ;
+    END
+  END rw0_rd_out[510]
+  PIN rw0_rd_out[511]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 114.401 36.678 114.415 36.720 ;
+    END
+  END rw0_rd_out[511]
+  PIN rw0_addr_in[0]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M2 ;
+      RECT 0.000 33.930 0.036 33.942 ;
+    END
+  END rw0_addr_in[0]
+  PIN rw0_addr_in[1]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M2 ;
+      RECT 0.000 34.194 0.036 34.206 ;
+    END
+  END rw0_addr_in[1]
+  PIN rw0_addr_in[2]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M2 ;
+      RECT 0.000 34.458 0.036 34.470 ;
+    END
+  END rw0_addr_in[2]
+  PIN rw0_addr_in[3]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M2 ;
+      RECT 117.354 33.930 117.390 33.942 ;
+    END
+  END rw0_addr_in[3]
+  PIN rw0_addr_in[4]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M2 ;
+      RECT 117.354 34.194 117.390 34.206 ;
+    END
+  END rw0_addr_in[4]
+  PIN rw0_addr_in[5]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M2 ;
+      RECT 117.354 34.458 117.390 34.470 ;
+    END
+  END rw0_addr_in[5]
+  PIN rw0_we_in
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 114.849 36.678 114.863 36.720 ;
+    END
+  END rw0_we_in
+  PIN rw0_ce_in
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 115.297 36.678 115.311 36.720 ;
+    END
+  END rw0_ce_in
+  PIN rw0_clk
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M3 ;
+      RECT 115.745 36.678 115.759 36.720 ;
+    END
+  END rw0_clk
+  PIN VSS
+    DIRECTION INOUT ;
+    USE GROUND ;
+    PORT
+      LAYER M4 ;
+      RECT 0.168 0.120 117.222 0.168 ;
+      RECT 0.168 0.504 117.222 0.552 ;
+      RECT 0.168 0.888 117.222 0.936 ;
+      RECT 0.168 1.272 117.222 1.320 ;
+      RECT 0.168 1.656 117.222 1.704 ;
+      RECT 0.168 2.040 117.222 2.088 ;
+      RECT 0.168 2.424 117.222 2.472 ;
+      RECT 0.168 2.808 117.222 2.856 ;
+      RECT 0.168 3.192 117.222 3.240 ;
+      RECT 0.168 3.576 117.222 3.624 ;
+      RECT 0.168 3.960 117.222 4.008 ;
+      RECT 0.168 4.344 117.222 4.392 ;
+      RECT 0.168 4.728 117.222 4.776 ;
+      RECT 0.168 5.112 117.222 5.160 ;
+      RECT 0.168 5.496 117.222 5.544 ;
+      RECT 0.168 5.880 117.222 5.928 ;
+      RECT 0.168 6.264 117.222 6.312 ;
+      RECT 0.168 6.648 117.222 6.696 ;
+      RECT 0.168 7.032 117.222 7.080 ;
+      RECT 0.168 7.416 117.222 7.464 ;
+      RECT 0.168 7.800 117.222 7.848 ;
+      RECT 0.168 8.184 117.222 8.232 ;
+      RECT 0.168 8.568 117.222 8.616 ;
+      RECT 0.168 8.952 117.222 9.000 ;
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+      RECT 0.168 9.720 117.222 9.768 ;
+      RECT 0.168 10.104 117.222 10.152 ;
+      RECT 0.168 10.488 117.222 10.536 ;
+      RECT 0.168 10.872 117.222 10.920 ;
+      RECT 0.168 11.256 117.222 11.304 ;
+      RECT 0.168 11.640 117.222 11.688 ;
+      RECT 0.168 12.024 117.222 12.072 ;
+      RECT 0.168 12.408 117.222 12.456 ;
+      RECT 0.168 12.792 117.222 12.840 ;
+      RECT 0.168 13.176 117.222 13.224 ;
+      RECT 0.168 13.560 117.222 13.608 ;
+      RECT 0.168 13.944 117.222 13.992 ;
+      RECT 0.168 14.328 117.222 14.376 ;
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+      RECT 0.168 16.248 117.222 16.296 ;
+      RECT 0.168 16.632 117.222 16.680 ;
+      RECT 0.168 17.016 117.222 17.064 ;
+      RECT 0.168 17.400 117.222 17.448 ;
+      RECT 0.168 17.784 117.222 17.832 ;
+      RECT 0.168 18.168 117.222 18.216 ;
+      RECT 0.168 18.552 117.222 18.600 ;
+      RECT 0.168 18.936 117.222 18.984 ;
+      RECT 0.168 19.320 117.222 19.368 ;
+      RECT 0.168 19.704 117.222 19.752 ;
+      RECT 0.168 20.088 117.222 20.136 ;
+      RECT 0.168 20.472 117.222 20.520 ;
+      RECT 0.168 20.856 117.222 20.904 ;
+      RECT 0.168 21.240 117.222 21.288 ;
+      RECT 0.168 21.624 117.222 21.672 ;
+      RECT 0.168 22.008 117.222 22.056 ;
+      RECT 0.168 22.392 117.222 22.440 ;
+      RECT 0.168 22.776 117.222 22.824 ;
+      RECT 0.168 23.160 117.222 23.208 ;
+      RECT 0.168 23.544 117.222 23.592 ;
+      RECT 0.168 23.928 117.222 23.976 ;
+      RECT 0.168 24.312 117.222 24.360 ;
+      RECT 0.168 24.696 117.222 24.744 ;
+      RECT 0.168 25.080 117.222 25.128 ;
+      RECT 0.168 25.464 117.222 25.512 ;
+      RECT 0.168 25.848 117.222 25.896 ;
+      RECT 0.168 26.232 117.222 26.280 ;
+      RECT 0.168 26.616 117.222 26.664 ;
+      RECT 0.168 27.000 117.222 27.048 ;
+      RECT 0.168 27.384 117.222 27.432 ;
+      RECT 0.168 27.768 117.222 27.816 ;
+      RECT 0.168 28.152 117.222 28.200 ;
+      RECT 0.168 28.536 117.222 28.584 ;
+      RECT 0.168 28.920 117.222 28.968 ;
+      RECT 0.168 29.304 117.222 29.352 ;
+      RECT 0.168 29.688 117.222 29.736 ;
+      RECT 0.168 30.072 117.222 30.120 ;
+      RECT 0.168 30.456 117.222 30.504 ;
+      RECT 0.168 30.840 117.222 30.888 ;
+      RECT 0.168 31.224 117.222 31.272 ;
+      RECT 0.168 31.608 117.222 31.656 ;
+      RECT 0.168 31.992 117.222 32.040 ;
+      RECT 0.168 32.376 117.222 32.424 ;
+      RECT 0.168 32.760 117.222 32.808 ;
+      RECT 0.168 33.144 117.222 33.192 ;
+      RECT 0.168 33.528 117.222 33.576 ;
+      RECT 0.168 33.912 117.222 33.960 ;
+      RECT 0.168 34.296 117.222 34.344 ;
+      RECT 0.168 34.680 117.222 34.728 ;
+      RECT 0.168 35.064 117.222 35.112 ;
+      RECT 0.168 35.448 117.222 35.496 ;
+      RECT 0.168 35.832 117.222 35.880 ;
+      RECT 0.168 36.216 117.222 36.264 ;
+      RECT 0.168 36.600 117.222 36.648 ;
+    END
+  END VSS
+  PIN VDD
+    DIRECTION INOUT ;
+    USE POWER ;
+    PORT
+      LAYER M4 ;
+      RECT 0.168 0.312 117.222 0.360 ;
+      RECT 0.168 0.696 117.222 0.744 ;
+      RECT 0.168 1.080 117.222 1.128 ;
+      RECT 0.168 1.464 117.222 1.512 ;
+      RECT 0.168 1.848 117.222 1.896 ;
+      RECT 0.168 2.232 117.222 2.280 ;
+      RECT 0.168 2.616 117.222 2.664 ;
+      RECT 0.168 3.000 117.222 3.048 ;
+      RECT 0.168 3.384 117.222 3.432 ;
+      RECT 0.168 3.768 117.222 3.816 ;
+      RECT 0.168 4.152 117.222 4.200 ;
+      RECT 0.168 4.536 117.222 4.584 ;
+      RECT 0.168 4.920 117.222 4.968 ;
+      RECT 0.168 5.304 117.222 5.352 ;
+      RECT 0.168 5.688 117.222 5.736 ;
+      RECT 0.168 6.072 117.222 6.120 ;
+      RECT 0.168 6.456 117.222 6.504 ;
+      RECT 0.168 6.840 117.222 6.888 ;
+      RECT 0.168 7.224 117.222 7.272 ;
+      RECT 0.168 7.608 117.222 7.656 ;
+      RECT 0.168 7.992 117.222 8.040 ;
+      RECT 0.168 8.376 117.222 8.424 ;
+      RECT 0.168 8.760 117.222 8.808 ;
+      RECT 0.168 9.144 117.222 9.192 ;
+      RECT 0.168 9.528 117.222 9.576 ;
+      RECT 0.168 9.912 117.222 9.960 ;
+      RECT 0.168 10.296 117.222 10.344 ;
+      RECT 0.168 10.680 117.222 10.728 ;
+      RECT 0.168 11.064 117.222 11.112 ;
+      RECT 0.168 11.448 117.222 11.496 ;
+      RECT 0.168 11.832 117.222 11.880 ;
+      RECT 0.168 12.216 117.222 12.264 ;
+      RECT 0.168 12.600 117.222 12.648 ;
+      RECT 0.168 12.984 117.222 13.032 ;
+      RECT 0.168 13.368 117.222 13.416 ;
+      RECT 0.168 13.752 117.222 13.800 ;
+      RECT 0.168 14.136 117.222 14.184 ;
+      RECT 0.168 14.520 117.222 14.568 ;
+      RECT 0.168 14.904 117.222 14.952 ;
+      RECT 0.168 15.288 117.222 15.336 ;
+      RECT 0.168 15.672 117.222 15.720 ;
+      RECT 0.168 16.056 117.222 16.104 ;
+      RECT 0.168 16.440 117.222 16.488 ;
+      RECT 0.168 16.824 117.222 16.872 ;
+      RECT 0.168 17.208 117.222 17.256 ;
+      RECT 0.168 17.592 117.222 17.640 ;
+      RECT 0.168 17.976 117.222 18.024 ;
+      RECT 0.168 18.360 117.222 18.408 ;
+      RECT 0.168 18.744 117.222 18.792 ;
+      RECT 0.168 19.128 117.222 19.176 ;
+      RECT 0.168 19.512 117.222 19.560 ;
+      RECT 0.168 19.896 117.222 19.944 ;
+      RECT 0.168 20.280 117.222 20.328 ;
+      RECT 0.168 20.664 117.222 20.712 ;
+      RECT 0.168 21.048 117.222 21.096 ;
+      RECT 0.168 21.432 117.222 21.480 ;
+      RECT 0.168 21.816 117.222 21.864 ;
+      RECT 0.168 22.200 117.222 22.248 ;
+      RECT 0.168 22.584 117.222 22.632 ;
+      RECT 0.168 22.968 117.222 23.016 ;
+      RECT 0.168 23.352 117.222 23.400 ;
+      RECT 0.168 23.736 117.222 23.784 ;
+      RECT 0.168 24.120 117.222 24.168 ;
+      RECT 0.168 24.504 117.222 24.552 ;
+      RECT 0.168 24.888 117.222 24.936 ;
+      RECT 0.168 25.272 117.222 25.320 ;
+      RECT 0.168 25.656 117.222 25.704 ;
+      RECT 0.168 26.040 117.222 26.088 ;
+      RECT 0.168 26.424 117.222 26.472 ;
+      RECT 0.168 26.808 117.222 26.856 ;
+      RECT 0.168 27.192 117.222 27.240 ;
+      RECT 0.168 27.576 117.222 27.624 ;
+      RECT 0.168 27.960 117.222 28.008 ;
+      RECT 0.168 28.344 117.222 28.392 ;
+      RECT 0.168 28.728 117.222 28.776 ;
+      RECT 0.168 29.112 117.222 29.160 ;
+      RECT 0.168 29.496 117.222 29.544 ;
+      RECT 0.168 29.880 117.222 29.928 ;
+      RECT 0.168 30.264 117.222 30.312 ;
+      RECT 0.168 30.648 117.222 30.696 ;
+      RECT 0.168 31.032 117.222 31.080 ;
+      RECT 0.168 31.416 117.222 31.464 ;
+      RECT 0.168 31.800 117.222 31.848 ;
+      RECT 0.168 32.184 117.222 32.232 ;
+      RECT 0.168 32.568 117.222 32.616 ;
+      RECT 0.168 32.952 117.222 33.000 ;
+      RECT 0.168 33.336 117.222 33.384 ;
+      RECT 0.168 33.720 117.222 33.768 ;
+      RECT 0.168 34.104 117.222 34.152 ;
+      RECT 0.168 34.488 117.222 34.536 ;
+      RECT 0.168 34.872 117.222 34.920 ;
+      RECT 0.168 35.256 117.222 35.304 ;
+      RECT 0.168 35.640 117.222 35.688 ;
+      RECT 0.168 36.024 117.222 36.072 ;
+      RECT 0.168 36.408 117.222 36.456 ;
+    END
+  END VDD
+  OBS
+    LAYER M1 ;
+    RECT 0 0 117.390 36.720 ;
+    LAYER M2 ;
+    RECT 0 0 117.390 36.720 ;
+    LAYER M3 ;
+    RECT 0 0 117.390 36.720 ;
+    LAYER M4 ;
+    RECT 0 0 117.390 36.720 ;
+  END
+END fakeram7_64x512
+
+END LIBRARY
diff --git a/designs/gt2n/snitch_cluster/sram/lib/fakeram7_128x48.lib b/designs/gt2n/snitch_cluster/sram/lib/fakeram7_128x48.lib
new file mode 100644
index 00000000..83cd893a
--- /dev/null
+++ b/designs/gt2n/snitch_cluster/sram/lib/fakeram7_128x48.lib
@@ -0,0 +1,389 @@
+library(fakeram7_128x48) {
+    technology (cmos);
+    delay_model : table_lookup;
+    revision : 1.0;
+    date : "2026-08-30 08:30:01Z";
+    comment : "SRAM";
+    time_unit : "1ns";
+    voltage_unit : "1V";
+    current_unit : "1uA";
+    leakage_power_unit : "1uW";
+    nom_process : 1;
+    nom_temperature : 25.000;
+    nom_voltage : 0.7;
+    capacitive_load_unit (1,pf);
+
+    pulling_resistance_unit : "1kohm";
+
+    operating_conditions(tt_1.0_25.0) {
+        process : 1;
+        temperature : 25.000;
+        voltage : 0.7;
+        tree_type : balanced_tree;
+    }
+
+    /* default attributes */
+    default_cell_leakage_power : 0;
+    default_fanout_load : 1;
+    default_inout_pin_cap : 0.0;
+    default_input_pin_cap : 0.0;
+    default_output_pin_cap : 0.0;
+    default_input_pin_cap : 0.0;
+    default_max_transition : 0.125;
+
+    default_operating_conditions : tt_1.0_25.0;
+    default_leakage_power_density : 0.0;
+
+    /* additional header data */
+    slew_derate_from_library : 1.000;
+    slew_lower_threshold_pct_fall : 20.000;
+    slew_upper_threshold_pct_fall : 80.000;
+    slew_lower_threshold_pct_rise : 20.000;
+    slew_upper_threshold_pct_rise : 80.000;
+    input_threshold_pct_fall : 50.000;
+    input_threshold_pct_rise : 50.000;
+    output_threshold_pct_fall : 50.000;
+    output_threshold_pct_rise : 50.000;
+
+
+    lu_table_template(fakeram7_128x48_mem_out_delay_template) {
+        variable_1 : input_net_transition;
+        variable_2 : total_output_net_capacitance;
+            index_1 ("1000, 1001");
+            index_2 ("1000, 1001");
+    }
+    lu_table_template(fakeram7_128x48_mem_out_slew_template) {
+        variable_1 : total_output_net_capacitance;
+            index_1 ("1000, 1001");
+    }
+    lu_table_template(fakeram7_128x48_constraint_template) {
+        variable_1 : related_pin_transition;
+        variable_2 : constrained_pin_transition;
+            index_1 ("1000, 1001");
+            index_2 ("1000, 1001");
+    }
+    power_lut_template(fakeram7_128x48_energy_template_clkslew) {
+        variable_1 : input_transition_time;
+            index_1 ("1000, 1001");
+    }
+    power_lut_template(fakeram7_128x48_energy_template_sigslew) {
+        variable_1 : input_transition_time;
+            index_1 ("1000, 1001");
+    }
+    library_features(report_delay_calculation);
+    type (fakeram7_128x48_DATA) {
+        base_type : array ;
+        data_type : bit ;
+        bit_width : 48;
+        bit_from : 47;
+        bit_to : 0 ;
+        downto : true ;
+    }
+    type (fakeram7_128x48_ADDRESS) {
+        base_type : array ;
+        data_type : bit ;
+        bit_width : 7;
+        bit_from : 6;
+        bit_to : 0 ;
+        downto : true ;
+    }
+cell(fakeram7_128x48) {
+    area : 809.676;
+    interface_timing : true;
+    memory() {
+        type : ram;
+        address_width : 7;
+        word_width : 48;
+    }
+    pin(rw0_clk)   {
+        direction : input;
+        capacitance : 0.00244;
+        clock : true;
+        min_period           : 0.143 ;
+        internal_power(){
+            rise_power(fakeram7_128x48_energy_template_clkslew) {
+                index_1 ("0.005, 0.125");
+                values ("1.000, 1.000")
+            }
+            fall_power(fakeram7_128x48_energy_template_clkslew) {
+                index_1 ("0.005, 0.125");
+                values ("1.000, 1.000")
+            }
+        }
+    }
+
+    bus(rw0_rd_out)   {
+        bus_type : fakeram7_128x48_DATA;
+        direction : output;
+        max_capacitance : 0.0488;
+        memory_read() {
+            address : r0_addr_in;
+        }
+        timing() {
+            related_pin : "rw0_clk" ;
+            timing_type : rising_edge;
+            timing_sense : non_unate;
+            cell_rise(fakeram7_128x48_mem_out_delay_template) {
+                index_1 ("0.005, 0.125");
+                index_2 ("0.000488, 0.0488");
+                values ( \
+                  "0.200, 0.200", \
+                  "0.200, 0.200" \
+                )
+            }
+            cell_fall(fakeram7_128x48_mem_out_delay_template) {
+                index_1 ("0.005, 0.125");
+                index_2 ("0.000488, 0.0488");
+                values ( \
+                  "0.200, 0.200", \
+                  "0.200, 0.200" \
+                )
+            }
+            rise_transition(fakeram7_128x48_mem_out_slew_template) {
+                index_1 ("0.000488, 0.0488");
+                values ("0.005, 0.125")
+            }
+            fall_transition(fakeram7_128x48_mem_out_slew_template) {
+                index_1 ("0.000488, 0.0488");
+                values ("0.005, 0.125")
+            }
+        }
+    }
+    pin(rw0_we_in)   {
+        direction : input;
+        capacitance : 0.000488;
+        timing() {
+            related_pin : rw0_clk;
+            timing_type : setup_rising ;
+            rise_constraint(fakeram7_128x48_constraint_template) {
+                index_1 ("0.005, 0.125");
+                index_2 ("0.005, 0.125");
+                values ( \
+                  "0.007, 0.007", \
+                  "0.007, 0.007" \
+                )
+            }
+            fall_constraint(fakeram7_128x48_constraint_template) {
+                index_1 ("0.005, 0.125");
+                index_2 ("0.005, 0.125");
+                values ( \
+                  "0.007, 0.007", \
+                  "0.007, 0.007" \
+                )
+            }
+        } 
+        timing() {
+            related_pin : rw0_clk;
+            timing_type : hold_rising ;
+            rise_constraint(fakeram7_128x48_constraint_template) {
+                index_1 ("0.005, 0.125");
+                index_2 ("0.005, 0.125");
+                values ( \
+                  "0.007, 0.007", \
+                  "0.007, 0.007" \
+                )
+            }
+            fall_constraint(fakeram7_128x48_constraint_template) {
+                index_1 ("0.005, 0.125");
+                index_2 ("0.005, 0.125");
+                values ( \
+                  "0.007, 0.007", \
+                  "0.007, 0.007" \
+                )
+            }
+        }
+        internal_power(){
+            rise_power(fakeram7_128x48_energy_template_sigslew) {
+                index_1 ("0.005, 0.125");
+                values ("0.010, 0.010")
+            }
+            fall_power(fakeram7_128x48_energy_template_sigslew) {
+                index_1 ("0.005, 0.125");
+                values ("0.010, 0.010")
+            }
+        }
+    }
+    pin(rw0_ce_in)   {
+        direction : input;
+        capacitance : 0.000488;
+        timing() {
+            related_pin : rw0_clk;
+            timing_type : setup_rising ;
+            rise_constraint(fakeram7_128x48_constraint_template) {
+                index_1 ("0.005, 0.125");
+                index_2 ("0.005, 0.125");
+                values ( \
+                  "0.007, 0.007", \
+                  "0.007, 0.007" \
+                )
+            }
+            fall_constraint(fakeram7_128x48_constraint_template) {
+                index_1 ("0.005, 0.125");
+                index_2 ("0.005, 0.125");
+                values ( \
+                  "0.007, 0.007", \
+                  "0.007, 0.007" \
+                )
+            }
+        } 
+        timing() {
+            related_pin : rw0_clk;
+            timing_type : hold_rising ;
+            rise_constraint(fakeram7_128x48_constraint_template) {
+                index_1 ("0.005, 0.125");
+                index_2 ("0.005, 0.125");
+                values ( \
+                  "0.007, 0.007", \
+                  "0.007, 0.007" \
+                )
+            }
+            fall_constraint(fakeram7_128x48_constraint_template) {
+                index_1 ("0.005, 0.125");
+                index_2 ("0.005, 0.125");
+                values ( \
+                  "0.007, 0.007", \
+                  "0.007, 0.007" \
+                )
+            }
+        }
+        internal_power(){
+            rise_power(fakeram7_128x48_energy_template_sigslew) {
+                index_1 ("0.005, 0.125");
+                values ("0.010, 0.010")
+            }
+            fall_power(fakeram7_128x48_energy_template_sigslew) {
+                index_1 ("0.005, 0.125");
+                values ("0.010, 0.010")
+            }
+        }
+    }
+    bus(rw0_addr_in)   {
+        bus_type : fakeram7_128x48_ADDRESS;
+        direction : input;
+        capacitance : 0.000488;
+        timing() {
+            related_pin : rw0_clk;
+            timing_type : setup_rising ;
+            rise_constraint(fakeram7_128x48_constraint_template) {
+                index_1 ("0.005, 0.125");
+                index_2 ("0.005, 0.125");
+                values ( \
+                  "0.007, 0.007", \
+                  "0.007, 0.007" \
+                )
+            }
+            fall_constraint(fakeram7_128x48_constraint_template) {
+                index_1 ("0.005, 0.125");
+                index_2 ("0.005, 0.125");
+                values ( \
+                  "0.007, 0.007", \
+                  "0.007, 0.007" \
+                )
+            }
+        } 
+        timing() {
+            related_pin : rw0_clk;
+            timing_type : hold_rising ;
+            rise_constraint(fakeram7_128x48_constraint_template) {
+                index_1 ("0.005, 0.125");
+                index_2 ("0.005, 0.125");
+                values ( \
+                  "0.007, 0.007", \
+                  "0.007, 0.007" \
+                )
+            }
+            fall_constraint(fakeram7_128x48_constraint_template) {
+                index_1 ("0.005, 0.125");
+                index_2 ("0.005, 0.125");
+                values ( \
+                  "0.007, 0.007", \
+                  "0.007, 0.007" \
+                )
+            }
+        }
+        internal_power(){
+            rise_power(fakeram7_128x48_energy_template_sigslew) {
+                index_1 ("0.005, 0.125");
+                values ("0.010, 0.010")
+            }
+            fall_power(fakeram7_128x48_energy_template_sigslew) {
+                index_1 ("0.005, 0.125");
+                values ("0.010, 0.010")
+            }
+        }
+    }
+    bus(rw0_wd_in)   {
+        bus_type : fakeram7_128x48_DATA;
+        memory_write() {
+            address : rw0_addr_in;
+            clocked_on : "rw0_clk";
+        }
+        direction : input;
+        capacitance : 0.000488;
+        timing() {
+            related_pin     : rw0_clk;
+            timing_type     : setup_rising ;
+            rise_constraint(fakeram7_128x48_constraint_template) {
+                index_1 ("0.005, 0.125");
+                index_2 ("0.005, 0.125");
+                values ( \
+                  "0.007, 0.007", \
+                  "0.007, 0.007" \
+                )
+            }
+            fall_constraint(fakeram7_128x48_constraint_template) {
+                index_1 ("0.005, 0.125");
+                index_2 ("0.005, 0.125");
+                values ( \
+                  "0.007, 0.007", \
+                  "0.007, 0.007" \
+                )
+            }
+        } 
+        timing() {
+            related_pin     : rw0_clk;
+            timing_type     : hold_rising ;
+            rise_constraint(fakeram7_128x48_constraint_template) {
+                index_1 ("0.005, 0.125");
+                index_2 ("0.005, 0.125");
+                values ( \
+                  "0.007, 0.007", \
+                  "0.007, 0.007" \
+                )
+            }
+            fall_constraint(fakeram7_128x48_constraint_template) {
+                index_1 ("0.005, 0.125");
+                index_2 ("0.005, 0.125");
+                values ( \
+                  "0.007, 0.007", \
+                  "0.007, 0.007" \
+                )
+            }
+        }
+        internal_power(){
+            when : "(! (rw0_we_in) )";
+            rise_power(fakeram7_128x48_energy_template_sigslew) {
+                index_1 ("0.005, 0.125");
+                values ("0.010, 0.010")
+            }
+            fall_power(fakeram7_128x48_energy_template_sigslew) {
+                index_1 ("0.005, 0.125");
+                values ("0.010, 0.010")
+            }
+        }
+        internal_power(){
+            when : "(rw0_we_in)";
+            rise_power(fakeram7_128x48_energy_template_sigslew) {
+                index_1 ("0.005, 0.125");
+                values ("0.010, 0.010")
+            }
+            fall_power(fakeram7_128x48_energy_template_sigslew) {
+                index_1 ("0.005, 0.125");
+                values ("0.010, 0.010")
+            }
+        }
+    }
+    cell_leakage_power : 100.000;
+}
+
+}
diff --git a/designs/gt2n/snitch_cluster/sram/lib/fakeram7_256x256.lib b/designs/gt2n/snitch_cluster/sram/lib/fakeram7_256x256.lib
new file mode 100644
index 00000000..f7ec9a83
--- /dev/null
+++ b/designs/gt2n/snitch_cluster/sram/lib/fakeram7_256x256.lib
@@ -0,0 +1,389 @@
+library(fakeram7_256x256) {
+    technology (cmos);
+    delay_model : table_lookup;
+    revision : 1.0;
+    date : "2026-08-30 08:30:01Z";
+    comment : "SRAM";
+    time_unit : "1ns";
+    voltage_unit : "1V";
+    current_unit : "1uA";
+    leakage_power_unit : "1uW";
+    nom_process : 1;
+    nom_temperature : 25.000;
+    nom_voltage : 0.7;
+    capacitive_load_unit (1,pf);
+
+    pulling_resistance_unit : "1kohm";
+
+    operating_conditions(tt_1.0_25.0) {
+        process : 1;
+        temperature : 25.000;
+        voltage : 0.7;
+        tree_type : balanced_tree;
+    }
+
+    /* default attributes */
+    default_cell_leakage_power : 0;
+    default_fanout_load : 1;
+    default_inout_pin_cap : 0.0;
+    default_input_pin_cap : 0.0;
+    default_output_pin_cap : 0.0;
+    default_input_pin_cap : 0.0;
+    default_max_transition : 0.125;
+
+    default_operating_conditions : tt_1.0_25.0;
+    default_leakage_power_density : 0.0;
+
+    /* additional header data */
+    slew_derate_from_library : 1.000;
+    slew_lower_threshold_pct_fall : 20.000;
+    slew_upper_threshold_pct_fall : 80.000;
+    slew_lower_threshold_pct_rise : 20.000;
+    slew_upper_threshold_pct_rise : 80.000;
+    input_threshold_pct_fall : 50.000;
+    input_threshold_pct_rise : 50.000;
+    output_threshold_pct_fall : 50.000;
+    output_threshold_pct_rise : 50.000;
+
+
+    lu_table_template(fakeram7_256x256_mem_out_delay_template) {
+        variable_1 : input_net_transition;
+        variable_2 : total_output_net_capacitance;
+            index_1 ("1000, 1001");
+            index_2 ("1000, 1001");
+    }
+    lu_table_template(fakeram7_256x256_mem_out_slew_template) {
+        variable_1 : total_output_net_capacitance;
+            index_1 ("1000, 1001");
+    }
+    lu_table_template(fakeram7_256x256_constraint_template) {
+        variable_1 : related_pin_transition;
+        variable_2 : constrained_pin_transition;
+            index_1 ("1000, 1001");
+            index_2 ("1000, 1001");
+    }
+    power_lut_template(fakeram7_256x256_energy_template_clkslew) {
+        variable_1 : input_transition_time;
+            index_1 ("1000, 1001");
+    }
+    power_lut_template(fakeram7_256x256_energy_template_sigslew) {
+        variable_1 : input_transition_time;
+            index_1 ("1000, 1001");
+    }
+    library_features(report_delay_calculation);
+    type (fakeram7_256x256_DATA) {
+        base_type : array ;
+        data_type : bit ;
+        bit_width : 256;
+        bit_from : 255;
+        bit_to : 0 ;
+        downto : true ;
+    }
+    type (fakeram7_256x256_ADDRESS) {
+        base_type : array ;
+        data_type : bit ;
+        bit_width : 8;
+        bit_from : 7;
+        bit_to : 0 ;
+        downto : true ;
+    }
+cell(fakeram7_256x256) {
+    area : 8621.122;
+    interface_timing : true;
+    memory() {
+        type : ram;
+        address_width : 8;
+        word_width : 256;
+    }
+    pin(rw0_clk)   {
+        direction : input;
+        capacitance : 0.00244;
+        clock : true;
+        min_period           : 0.143 ;
+        internal_power(){
+            rise_power(fakeram7_256x256_energy_template_clkslew) {
+                index_1 ("0.005, 0.125");
+                values ("1.000, 1.000")
+            }
+            fall_power(fakeram7_256x256_energy_template_clkslew) {
+                index_1 ("0.005, 0.125");
+                values ("1.000, 1.000")
+            }
+        }
+    }
+
+    bus(rw0_rd_out)   {
+        bus_type : fakeram7_256x256_DATA;
+        direction : output;
+        max_capacitance : 0.0488;
+        memory_read() {
+            address : r0_addr_in;
+        }
+        timing() {
+            related_pin : "rw0_clk" ;
+            timing_type : rising_edge;
+            timing_sense : non_unate;
+            cell_rise(fakeram7_256x256_mem_out_delay_template) {
+                index_1 ("0.005, 0.125");
+                index_2 ("0.000488, 0.0488");
+                values ( \
+                  "0.200, 0.200", \
+                  "0.200, 0.200" \
+                )
+            }
+            cell_fall(fakeram7_256x256_mem_out_delay_template) {
+                index_1 ("0.005, 0.125");
+                index_2 ("0.000488, 0.0488");
+                values ( \
+                  "0.200, 0.200", \
+                  "0.200, 0.200" \
+                )
+            }
+            rise_transition(fakeram7_256x256_mem_out_slew_template) {
+                index_1 ("0.000488, 0.0488");
+                values ("0.005, 0.125")
+            }
+            fall_transition(fakeram7_256x256_mem_out_slew_template) {
+                index_1 ("0.000488, 0.0488");
+                values ("0.005, 0.125")
+            }
+        }
+    }
+    pin(rw0_we_in)   {
+        direction : input;
+        capacitance : 0.000488;
+        timing() {
+            related_pin : rw0_clk;
+            timing_type : setup_rising ;
+            rise_constraint(fakeram7_256x256_constraint_template) {
+                index_1 ("0.005, 0.125");
+                index_2 ("0.005, 0.125");
+                values ( \
+                  "0.007, 0.007", \
+                  "0.007, 0.007" \
+                )
+            }
+            fall_constraint(fakeram7_256x256_constraint_template) {
+                index_1 ("0.005, 0.125");
+                index_2 ("0.005, 0.125");
+                values ( \
+                  "0.007, 0.007", \
+                  "0.007, 0.007" \
+                )
+            }
+        } 
+        timing() {
+            related_pin : rw0_clk;
+            timing_type : hold_rising ;
+            rise_constraint(fakeram7_256x256_constraint_template) {
+                index_1 ("0.005, 0.125");
+                index_2 ("0.005, 0.125");
+                values ( \
+                  "0.007, 0.007", \
+                  "0.007, 0.007" \
+                )
+            }
+            fall_constraint(fakeram7_256x256_constraint_template) {
+                index_1 ("0.005, 0.125");
+                index_2 ("0.005, 0.125");
+                values ( \
+                  "0.007, 0.007", \
+                  "0.007, 0.007" \
+                )
+            }
+        }
+        internal_power(){
+            rise_power(fakeram7_256x256_energy_template_sigslew) {
+                index_1 ("0.005, 0.125");
+                values ("0.010, 0.010")
+            }
+            fall_power(fakeram7_256x256_energy_template_sigslew) {
+                index_1 ("0.005, 0.125");
+                values ("0.010, 0.010")
+            }
+        }
+    }
+    pin(rw0_ce_in)   {
+        direction : input;
+        capacitance : 0.000488;
+        timing() {
+            related_pin : rw0_clk;
+            timing_type : setup_rising ;
+            rise_constraint(fakeram7_256x256_constraint_template) {
+                index_1 ("0.005, 0.125");
+                index_2 ("0.005, 0.125");
+                values ( \
+                  "0.007, 0.007", \
+                  "0.007, 0.007" \
+                )
+            }
+            fall_constraint(fakeram7_256x256_constraint_template) {
+                index_1 ("0.005, 0.125");
+                index_2 ("0.005, 0.125");
+                values ( \
+                  "0.007, 0.007", \
+                  "0.007, 0.007" \
+                )
+            }
+        } 
+        timing() {
+            related_pin : rw0_clk;
+            timing_type : hold_rising ;
+            rise_constraint(fakeram7_256x256_constraint_template) {
+                index_1 ("0.005, 0.125");
+                index_2 ("0.005, 0.125");
+                values ( \
+                  "0.007, 0.007", \
+                  "0.007, 0.007" \
+                )
+            }
+            fall_constraint(fakeram7_256x256_constraint_template) {
+                index_1 ("0.005, 0.125");
+                index_2 ("0.005, 0.125");
+                values ( \
+                  "0.007, 0.007", \
+                  "0.007, 0.007" \
+                )
+            }
+        }
+        internal_power(){
+            rise_power(fakeram7_256x256_energy_template_sigslew) {
+                index_1 ("0.005, 0.125");
+                values ("0.010, 0.010")
+            }
+            fall_power(fakeram7_256x256_energy_template_sigslew) {
+                index_1 ("0.005, 0.125");
+                values ("0.010, 0.010")
+            }
+        }
+    }
+    bus(rw0_addr_in)   {
+        bus_type : fakeram7_256x256_ADDRESS;
+        direction : input;
+        capacitance : 0.000488;
+        timing() {
+            related_pin : rw0_clk;
+            timing_type : setup_rising ;
+            rise_constraint(fakeram7_256x256_constraint_template) {
+                index_1 ("0.005, 0.125");
+                index_2 ("0.005, 0.125");
+                values ( \
+                  "0.007, 0.007", \
+                  "0.007, 0.007" \
+                )
+            }
+            fall_constraint(fakeram7_256x256_constraint_template) {
+                index_1 ("0.005, 0.125");
+                index_2 ("0.005, 0.125");
+                values ( \
+                  "0.007, 0.007", \
+                  "0.007, 0.007" \
+                )
+            }
+        } 
+        timing() {
+            related_pin : rw0_clk;
+            timing_type : hold_rising ;
+            rise_constraint(fakeram7_256x256_constraint_template) {
+                index_1 ("0.005, 0.125");
+                index_2 ("0.005, 0.125");
+                values ( \
+                  "0.007, 0.007", \
+                  "0.007, 0.007" \
+                )
+            }
+            fall_constraint(fakeram7_256x256_constraint_template) {
+                index_1 ("0.005, 0.125");
+                index_2 ("0.005, 0.125");
+                values ( \
+                  "0.007, 0.007", \
+                  "0.007, 0.007" \
+                )
+            }
+        }
+        internal_power(){
+            rise_power(fakeram7_256x256_energy_template_sigslew) {
+                index_1 ("0.005, 0.125");
+                values ("0.010, 0.010")
+            }
+            fall_power(fakeram7_256x256_energy_template_sigslew) {
+                index_1 ("0.005, 0.125");
+                values ("0.010, 0.010")
+            }
+        }
+    }
+    bus(rw0_wd_in)   {
+        bus_type : fakeram7_256x256_DATA;
+        memory_write() {
+            address : rw0_addr_in;
+            clocked_on : "rw0_clk";
+        }
+        direction : input;
+        capacitance : 0.000488;
+        timing() {
+            related_pin     : rw0_clk;
+            timing_type     : setup_rising ;
+            rise_constraint(fakeram7_256x256_constraint_template) {
+                index_1 ("0.005, 0.125");
+                index_2 ("0.005, 0.125");
+                values ( \
+                  "0.007, 0.007", \
+                  "0.007, 0.007" \
+                )
+            }
+            fall_constraint(fakeram7_256x256_constraint_template) {
+                index_1 ("0.005, 0.125");
+                index_2 ("0.005, 0.125");
+                values ( \
+                  "0.007, 0.007", \
+                  "0.007, 0.007" \
+                )
+            }
+        } 
+        timing() {
+            related_pin     : rw0_clk;
+            timing_type     : hold_rising ;
+            rise_constraint(fakeram7_256x256_constraint_template) {
+                index_1 ("0.005, 0.125");
+                index_2 ("0.005, 0.125");
+                values ( \
+                  "0.007, 0.007", \
+                  "0.007, 0.007" \
+                )
+            }
+            fall_constraint(fakeram7_256x256_constraint_template) {
+                index_1 ("0.005, 0.125");
+                index_2 ("0.005, 0.125");
+                values ( \
+                  "0.007, 0.007", \
+                  "0.007, 0.007" \
+                )
+            }
+        }
+        internal_power(){
+            when : "(! (rw0_we_in) )";
+            rise_power(fakeram7_256x256_energy_template_sigslew) {
+                index_1 ("0.005, 0.125");
+                values ("0.010, 0.010")
+            }
+            fall_power(fakeram7_256x256_energy_template_sigslew) {
+                index_1 ("0.005, 0.125");
+                values ("0.010, 0.010")
+            }
+        }
+        internal_power(){
+            when : "(rw0_we_in)";
+            rise_power(fakeram7_256x256_energy_template_sigslew) {
+                index_1 ("0.005, 0.125");
+                values ("0.010, 0.010")
+            }
+            fall_power(fakeram7_256x256_energy_template_sigslew) {
+                index_1 ("0.005, 0.125");
+                values ("0.010, 0.010")
+            }
+        }
+    }
+    cell_leakage_power : 100.000;
+}
+
+}
diff --git a/designs/gt2n/snitch_cluster/sram/lib/fakeram7_256x64.lib b/designs/gt2n/snitch_cluster/sram/lib/fakeram7_256x64.lib
new file mode 100644
index 00000000..8c8be4e5
--- /dev/null
+++ b/designs/gt2n/snitch_cluster/sram/lib/fakeram7_256x64.lib
@@ -0,0 +1,389 @@
+library(fakeram7_256x64) {
+    technology (cmos);
+    delay_model : table_lookup;
+    revision : 1.0;
+    date : "2026-08-30 08:30:01Z";
+    comment : "SRAM";
+    time_unit : "1ns";
+    voltage_unit : "1V";
+    current_unit : "1uA";
+    leakage_power_unit : "1uW";
+    nom_process : 1;
+    nom_temperature : 25.000;
+    nom_voltage : 0.7;
+    capacitive_load_unit (1,pf);
+
+    pulling_resistance_unit : "1kohm";
+
+    operating_conditions(tt_1.0_25.0) {
+        process : 1;
+        temperature : 25.000;
+        voltage : 0.7;
+        tree_type : balanced_tree;
+    }
+
+    /* default attributes */
+    default_cell_leakage_power : 0;
+    default_fanout_load : 1;
+    default_inout_pin_cap : 0.0;
+    default_input_pin_cap : 0.0;
+    default_output_pin_cap : 0.0;
+    default_input_pin_cap : 0.0;
+    default_max_transition : 0.125;
+
+    default_operating_conditions : tt_1.0_25.0;
+    default_leakage_power_density : 0.0;
+
+    /* additional header data */
+    slew_derate_from_library : 1.000;
+    slew_lower_threshold_pct_fall : 20.000;
+    slew_upper_threshold_pct_fall : 80.000;
+    slew_lower_threshold_pct_rise : 20.000;
+    slew_upper_threshold_pct_rise : 80.000;
+    input_threshold_pct_fall : 50.000;
+    input_threshold_pct_rise : 50.000;
+    output_threshold_pct_fall : 50.000;
+    output_threshold_pct_rise : 50.000;
+
+
+    lu_table_template(fakeram7_256x64_mem_out_delay_template) {
+        variable_1 : input_net_transition;
+        variable_2 : total_output_net_capacitance;
+            index_1 ("1000, 1001");
+            index_2 ("1000, 1001");
+    }
+    lu_table_template(fakeram7_256x64_mem_out_slew_template) {
+        variable_1 : total_output_net_capacitance;
+            index_1 ("1000, 1001");
+    }
+    lu_table_template(fakeram7_256x64_constraint_template) {
+        variable_1 : related_pin_transition;
+        variable_2 : constrained_pin_transition;
+            index_1 ("1000, 1001");
+            index_2 ("1000, 1001");
+    }
+    power_lut_template(fakeram7_256x64_energy_template_clkslew) {
+        variable_1 : input_transition_time;
+            index_1 ("1000, 1001");
+    }
+    power_lut_template(fakeram7_256x64_energy_template_sigslew) {
+        variable_1 : input_transition_time;
+            index_1 ("1000, 1001");
+    }
+    library_features(report_delay_calculation);
+    type (fakeram7_256x64_DATA) {
+        base_type : array ;
+        data_type : bit ;
+        bit_width : 64;
+        bit_from : 63;
+        bit_to : 0 ;
+        downto : true ;
+    }
+    type (fakeram7_256x64_ADDRESS) {
+        base_type : array ;
+        data_type : bit ;
+        bit_width : 8;
+        bit_from : 7;
+        bit_to : 0 ;
+        downto : true ;
+    }
+cell(fakeram7_256x64) {
+    area : 2156.052;
+    interface_timing : true;
+    memory() {
+        type : ram;
+        address_width : 8;
+        word_width : 64;
+    }
+    pin(rw0_clk)   {
+        direction : input;
+        capacitance : 0.00244;
+        clock : true;
+        min_period           : 0.143 ;
+        internal_power(){
+            rise_power(fakeram7_256x64_energy_template_clkslew) {
+                index_1 ("0.005, 0.125");
+                values ("1.000, 1.000")
+            }
+            fall_power(fakeram7_256x64_energy_template_clkslew) {
+                index_1 ("0.005, 0.125");
+                values ("1.000, 1.000")
+            }
+        }
+    }
+
+    bus(rw0_rd_out)   {
+        bus_type : fakeram7_256x64_DATA;
+        direction : output;
+        max_capacitance : 0.0488;
+        memory_read() {
+            address : r0_addr_in;
+        }
+        timing() {
+            related_pin : "rw0_clk" ;
+            timing_type : rising_edge;
+            timing_sense : non_unate;
+            cell_rise(fakeram7_256x64_mem_out_delay_template) {
+                index_1 ("0.005, 0.125");
+                index_2 ("0.000488, 0.0488");
+                values ( \
+                  "0.200, 0.200", \
+                  "0.200, 0.200" \
+                )
+            }
+            cell_fall(fakeram7_256x64_mem_out_delay_template) {
+                index_1 ("0.005, 0.125");
+                index_2 ("0.000488, 0.0488");
+                values ( \
+                  "0.200, 0.200", \
+                  "0.200, 0.200" \
+                )
+            }
+            rise_transition(fakeram7_256x64_mem_out_slew_template) {
+                index_1 ("0.000488, 0.0488");
+                values ("0.005, 0.125")
+            }
+            fall_transition(fakeram7_256x64_mem_out_slew_template) {
+                index_1 ("0.000488, 0.0488");
+                values ("0.005, 0.125")
+            }
+        }
+    }
+    pin(rw0_we_in)   {
+        direction : input;
+        capacitance : 0.000488;
+        timing() {
+            related_pin : rw0_clk;
+            timing_type : setup_rising ;
+            rise_constraint(fakeram7_256x64_constraint_template) {
+                index_1 ("0.005, 0.125");
+                index_2 ("0.005, 0.125");
+                values ( \
+                  "0.007, 0.007", \
+                  "0.007, 0.007" \
+                )
+            }
+            fall_constraint(fakeram7_256x64_constraint_template) {
+                index_1 ("0.005, 0.125");
+                index_2 ("0.005, 0.125");
+                values ( \
+                  "0.007, 0.007", \
+                  "0.007, 0.007" \
+                )
+            }
+        } 
+        timing() {
+            related_pin : rw0_clk;
+            timing_type : hold_rising ;
+            rise_constraint(fakeram7_256x64_constraint_template) {
+                index_1 ("0.005, 0.125");
+                index_2 ("0.005, 0.125");
+                values ( \
+                  "0.007, 0.007", \
+                  "0.007, 0.007" \
+                )
+            }
+            fall_constraint(fakeram7_256x64_constraint_template) {
+                index_1 ("0.005, 0.125");
+                index_2 ("0.005, 0.125");
+                values ( \
+                  "0.007, 0.007", \
+                  "0.007, 0.007" \
+                )
+            }
+        }
+        internal_power(){
+            rise_power(fakeram7_256x64_energy_template_sigslew) {
+                index_1 ("0.005, 0.125");
+                values ("0.010, 0.010")
+            }
+            fall_power(fakeram7_256x64_energy_template_sigslew) {
+                index_1 ("0.005, 0.125");
+                values ("0.010, 0.010")
+            }
+        }
+    }
+    pin(rw0_ce_in)   {
+        direction : input;
+        capacitance : 0.000488;
+        timing() {
+            related_pin : rw0_clk;
+            timing_type : setup_rising ;
+            rise_constraint(fakeram7_256x64_constraint_template) {
+                index_1 ("0.005, 0.125");
+                index_2 ("0.005, 0.125");
+                values ( \
+                  "0.007, 0.007", \
+                  "0.007, 0.007" \
+                )
+            }
+            fall_constraint(fakeram7_256x64_constraint_template) {
+                index_1 ("0.005, 0.125");
+                index_2 ("0.005, 0.125");
+                values ( \
+                  "0.007, 0.007", \
+                  "0.007, 0.007" \
+                )
+            }
+        } 
+        timing() {
+            related_pin : rw0_clk;
+            timing_type : hold_rising ;
+            rise_constraint(fakeram7_256x64_constraint_template) {
+                index_1 ("0.005, 0.125");
+                index_2 ("0.005, 0.125");
+                values ( \
+                  "0.007, 0.007", \
+                  "0.007, 0.007" \
+                )
+            }
+            fall_constraint(fakeram7_256x64_constraint_template) {
+                index_1 ("0.005, 0.125");
+                index_2 ("0.005, 0.125");
+                values ( \
+                  "0.007, 0.007", \
+                  "0.007, 0.007" \
+                )
+            }
+        }
+        internal_power(){
+            rise_power(fakeram7_256x64_energy_template_sigslew) {
+                index_1 ("0.005, 0.125");
+                values ("0.010, 0.010")
+            }
+            fall_power(fakeram7_256x64_energy_template_sigslew) {
+                index_1 ("0.005, 0.125");
+                values ("0.010, 0.010")
+            }
+        }
+    }
+    bus(rw0_addr_in)   {
+        bus_type : fakeram7_256x64_ADDRESS;
+        direction : input;
+        capacitance : 0.000488;
+        timing() {
+            related_pin : rw0_clk;
+            timing_type : setup_rising ;
+            rise_constraint(fakeram7_256x64_constraint_template) {
+                index_1 ("0.005, 0.125");
+                index_2 ("0.005, 0.125");
+                values ( \
+                  "0.007, 0.007", \
+                  "0.007, 0.007" \
+                )
+            }
+            fall_constraint(fakeram7_256x64_constraint_template) {
+                index_1 ("0.005, 0.125");
+                index_2 ("0.005, 0.125");
+                values ( \
+                  "0.007, 0.007", \
+                  "0.007, 0.007" \
+                )
+            }
+        } 
+        timing() {
+            related_pin : rw0_clk;
+            timing_type : hold_rising ;
+            rise_constraint(fakeram7_256x64_constraint_template) {
+                index_1 ("0.005, 0.125");
+                index_2 ("0.005, 0.125");
+                values ( \
+                  "0.007, 0.007", \
+                  "0.007, 0.007" \
+                )
+            }
+            fall_constraint(fakeram7_256x64_constraint_template) {
+                index_1 ("0.005, 0.125");
+                index_2 ("0.005, 0.125");
+                values ( \
+                  "0.007, 0.007", \
+                  "0.007, 0.007" \
+                )
+            }
+        }
+        internal_power(){
+            rise_power(fakeram7_256x64_energy_template_sigslew) {
+                index_1 ("0.005, 0.125");
+                values ("0.010, 0.010")
+            }
+            fall_power(fakeram7_256x64_energy_template_sigslew) {
+                index_1 ("0.005, 0.125");
+                values ("0.010, 0.010")
+            }
+        }
+    }
+    bus(rw0_wd_in)   {
+        bus_type : fakeram7_256x64_DATA;
+        memory_write() {
+            address : rw0_addr_in;
+            clocked_on : "rw0_clk";
+        }
+        direction : input;
+        capacitance : 0.000488;
+        timing() {
+            related_pin     : rw0_clk;
+            timing_type     : setup_rising ;
+            rise_constraint(fakeram7_256x64_constraint_template) {
+                index_1 ("0.005, 0.125");
+                index_2 ("0.005, 0.125");
+                values ( \
+                  "0.007, 0.007", \
+                  "0.007, 0.007" \
+                )
+            }
+            fall_constraint(fakeram7_256x64_constraint_template) {
+                index_1 ("0.005, 0.125");
+                index_2 ("0.005, 0.125");
+                values ( \
+                  "0.007, 0.007", \
+                  "0.007, 0.007" \
+                )
+            }
+        } 
+        timing() {
+            related_pin     : rw0_clk;
+            timing_type     : hold_rising ;
+            rise_constraint(fakeram7_256x64_constraint_template) {
+                index_1 ("0.005, 0.125");
+                index_2 ("0.005, 0.125");
+                values ( \
+                  "0.007, 0.007", \
+                  "0.007, 0.007" \
+                )
+            }
+            fall_constraint(fakeram7_256x64_constraint_template) {
+                index_1 ("0.005, 0.125");
+                index_2 ("0.005, 0.125");
+                values ( \
+                  "0.007, 0.007", \
+                  "0.007, 0.007" \
+                )
+            }
+        }
+        internal_power(){
+            when : "(! (rw0_we_in) )";
+            rise_power(fakeram7_256x64_energy_template_sigslew) {
+                index_1 ("0.005, 0.125");
+                values ("0.010, 0.010")
+            }
+            fall_power(fakeram7_256x64_energy_template_sigslew) {
+                index_1 ("0.005, 0.125");
+                values ("0.010, 0.010")
+            }
+        }
+        internal_power(){
+            when : "(rw0_we_in)";
+            rise_power(fakeram7_256x64_energy_template_sigslew) {
+                index_1 ("0.005, 0.125");
+                values ("0.010, 0.010")
+            }
+            fall_power(fakeram7_256x64_energy_template_sigslew) {
+                index_1 ("0.005, 0.125");
+                values ("0.010, 0.010")
+            }
+        }
+    }
+    cell_leakage_power : 100.000;
+}
+
+}
diff --git a/designs/gt2n/snitch_cluster/sram/lib/fakeram7_64x512.lib b/designs/gt2n/snitch_cluster/sram/lib/fakeram7_64x512.lib
new file mode 100644
index 00000000..0223ac74
--- /dev/null
+++ b/designs/gt2n/snitch_cluster/sram/lib/fakeram7_64x512.lib
@@ -0,0 +1,389 @@
+library(fakeram7_64x512) {
+    technology (cmos);
+    delay_model : table_lookup;
+    revision : 1.0;
+    date : "2026-08-30 08:30:01Z";
+    comment : "SRAM";
+    time_unit : "1ns";
+    voltage_unit : "1V";
+    current_unit : "1uA";
+    leakage_power_unit : "1uW";
+    nom_process : 1;
+    nom_temperature : 25.000;
+    nom_voltage : 0.7;
+    capacitive_load_unit (1,pf);
+
+    pulling_resistance_unit : "1kohm";
+
+    operating_conditions(tt_1.0_25.0) {
+        process : 1;
+        temperature : 25.000;
+        voltage : 0.7;
+        tree_type : balanced_tree;
+    }
+
+    /* default attributes */
+    default_cell_leakage_power : 0;
+    default_fanout_load : 1;
+    default_inout_pin_cap : 0.0;
+    default_input_pin_cap : 0.0;
+    default_output_pin_cap : 0.0;
+    default_input_pin_cap : 0.0;
+    default_max_transition : 0.125;
+
+    default_operating_conditions : tt_1.0_25.0;
+    default_leakage_power_density : 0.0;
+
+    /* additional header data */
+    slew_derate_from_library : 1.000;
+    slew_lower_threshold_pct_fall : 20.000;
+    slew_upper_threshold_pct_fall : 80.000;
+    slew_lower_threshold_pct_rise : 20.000;
+    slew_upper_threshold_pct_rise : 80.000;
+    input_threshold_pct_fall : 50.000;
+    input_threshold_pct_rise : 50.000;
+    output_threshold_pct_fall : 50.000;
+    output_threshold_pct_rise : 50.000;
+
+
+    lu_table_template(fakeram7_64x512_mem_out_delay_template) {
+        variable_1 : input_net_transition;
+        variable_2 : total_output_net_capacitance;
+            index_1 ("1000, 1001");
+            index_2 ("1000, 1001");
+    }
+    lu_table_template(fakeram7_64x512_mem_out_slew_template) {
+        variable_1 : total_output_net_capacitance;
+            index_1 ("1000, 1001");
+    }
+    lu_table_template(fakeram7_64x512_constraint_template) {
+        variable_1 : related_pin_transition;
+        variable_2 : constrained_pin_transition;
+            index_1 ("1000, 1001");
+            index_2 ("1000, 1001");
+    }
+    power_lut_template(fakeram7_64x512_energy_template_clkslew) {
+        variable_1 : input_transition_time;
+            index_1 ("1000, 1001");
+    }
+    power_lut_template(fakeram7_64x512_energy_template_sigslew) {
+        variable_1 : input_transition_time;
+            index_1 ("1000, 1001");
+    }
+    library_features(report_delay_calculation);
+    type (fakeram7_64x512_DATA) {
+        base_type : array ;
+        data_type : bit ;
+        bit_width : 512;
+        bit_from : 511;
+        bit_to : 0 ;
+        downto : true ;
+    }
+    type (fakeram7_64x512_ADDRESS) {
+        base_type : array ;
+        data_type : bit ;
+        bit_width : 6;
+        bit_from : 5;
+        bit_to : 0 ;
+        downto : true ;
+    }
+cell(fakeram7_64x512) {
+    area : 4310.561;
+    interface_timing : true;
+    memory() {
+        type : ram;
+        address_width : 6;
+        word_width : 512;
+    }
+    pin(rw0_clk)   {
+        direction : input;
+        capacitance : 0.00244;
+        clock : true;
+        min_period           : 0.143 ;
+        internal_power(){
+            rise_power(fakeram7_64x512_energy_template_clkslew) {
+                index_1 ("0.005, 0.125");
+                values ("1.000, 1.000")
+            }
+            fall_power(fakeram7_64x512_energy_template_clkslew) {
+                index_1 ("0.005, 0.125");
+                values ("1.000, 1.000")
+            }
+        }
+    }
+
+    bus(rw0_rd_out)   {
+        bus_type : fakeram7_64x512_DATA;
+        direction : output;
+        max_capacitance : 0.0488;
+        memory_read() {
+            address : r0_addr_in;
+        }
+        timing() {
+            related_pin : "rw0_clk" ;
+            timing_type : rising_edge;
+            timing_sense : non_unate;
+            cell_rise(fakeram7_64x512_mem_out_delay_template) {
+                index_1 ("0.005, 0.125");
+                index_2 ("0.000488, 0.0488");
+                values ( \
+                  "0.200, 0.200", \
+                  "0.200, 0.200" \
+                )
+            }
+            cell_fall(fakeram7_64x512_mem_out_delay_template) {
+                index_1 ("0.005, 0.125");
+                index_2 ("0.000488, 0.0488");
+                values ( \
+                  "0.200, 0.200", \
+                  "0.200, 0.200" \
+                )
+            }
+            rise_transition(fakeram7_64x512_mem_out_slew_template) {
+                index_1 ("0.000488, 0.0488");
+                values ("0.005, 0.125")
+            }
+            fall_transition(fakeram7_64x512_mem_out_slew_template) {
+                index_1 ("0.000488, 0.0488");
+                values ("0.005, 0.125")
+            }
+        }
+    }
+    pin(rw0_we_in)   {
+        direction : input;
+        capacitance : 0.000488;
+        timing() {
+            related_pin : rw0_clk;
+            timing_type : setup_rising ;
+            rise_constraint(fakeram7_64x512_constraint_template) {
+                index_1 ("0.005, 0.125");
+                index_2 ("0.005, 0.125");
+                values ( \
+                  "0.007, 0.007", \
+                  "0.007, 0.007" \
+                )
+            }
+            fall_constraint(fakeram7_64x512_constraint_template) {
+                index_1 ("0.005, 0.125");
+                index_2 ("0.005, 0.125");
+                values ( \
+                  "0.007, 0.007", \
+                  "0.007, 0.007" \
+                )
+            }
+        } 
+        timing() {
+            related_pin : rw0_clk;
+            timing_type : hold_rising ;
+            rise_constraint(fakeram7_64x512_constraint_template) {
+                index_1 ("0.005, 0.125");
+                index_2 ("0.005, 0.125");
+                values ( \
+                  "0.007, 0.007", \
+                  "0.007, 0.007" \
+                )
+            }
+            fall_constraint(fakeram7_64x512_constraint_template) {
+                index_1 ("0.005, 0.125");
+                index_2 ("0.005, 0.125");
+                values ( \
+                  "0.007, 0.007", \
+                  "0.007, 0.007" \
+                )
+            }
+        }
+        internal_power(){
+            rise_power(fakeram7_64x512_energy_template_sigslew) {
+                index_1 ("0.005, 0.125");
+                values ("0.010, 0.010")
+            }
+            fall_power(fakeram7_64x512_energy_template_sigslew) {
+                index_1 ("0.005, 0.125");
+                values ("0.010, 0.010")
+            }
+        }
+    }
+    pin(rw0_ce_in)   {
+        direction : input;
+        capacitance : 0.000488;
+        timing() {
+            related_pin : rw0_clk;
+            timing_type : setup_rising ;
+            rise_constraint(fakeram7_64x512_constraint_template) {
+                index_1 ("0.005, 0.125");
+                index_2 ("0.005, 0.125");
+                values ( \
+                  "0.007, 0.007", \
+                  "0.007, 0.007" \
+                )
+            }
+            fall_constraint(fakeram7_64x512_constraint_template) {
+                index_1 ("0.005, 0.125");
+                index_2 ("0.005, 0.125");
+                values ( \
+                  "0.007, 0.007", \
+                  "0.007, 0.007" \
+                )
+            }
+        } 
+        timing() {
+            related_pin : rw0_clk;
+            timing_type : hold_rising ;
+            rise_constraint(fakeram7_64x512_constraint_template) {
+                index_1 ("0.005, 0.125");
+                index_2 ("0.005, 0.125");
+                values ( \
+                  "0.007, 0.007", \
+                  "0.007, 0.007" \
+                )
+            }
+            fall_constraint(fakeram7_64x512_constraint_template) {
+                index_1 ("0.005, 0.125");
+                index_2 ("0.005, 0.125");
+                values ( \
+                  "0.007, 0.007", \
+                  "0.007, 0.007" \
+                )
+            }
+        }
+        internal_power(){
+            rise_power(fakeram7_64x512_energy_template_sigslew) {
+                index_1 ("0.005, 0.125");
+                values ("0.010, 0.010")
+            }
+            fall_power(fakeram7_64x512_energy_template_sigslew) {
+                index_1 ("0.005, 0.125");
+                values ("0.010, 0.010")
+            }
+        }
+    }
+    bus(rw0_addr_in)   {
+        bus_type : fakeram7_64x512_ADDRESS;
+        direction : input;
+        capacitance : 0.000488;
+        timing() {
+            related_pin : rw0_clk;
+            timing_type : setup_rising ;
+            rise_constraint(fakeram7_64x512_constraint_template) {
+                index_1 ("0.005, 0.125");
+                index_2 ("0.005, 0.125");
+                values ( \
+                  "0.007, 0.007", \
+                  "0.007, 0.007" \
+                )
+            }
+            fall_constraint(fakeram7_64x512_constraint_template) {
+                index_1 ("0.005, 0.125");
+                index_2 ("0.005, 0.125");
+                values ( \
+                  "0.007, 0.007", \
+                  "0.007, 0.007" \
+                )
+            }
+        } 
+        timing() {
+            related_pin : rw0_clk;
+            timing_type : hold_rising ;
+            rise_constraint(fakeram7_64x512_constraint_template) {
+                index_1 ("0.005, 0.125");
+                index_2 ("0.005, 0.125");
+                values ( \
+                  "0.007, 0.007", \
+                  "0.007, 0.007" \
+                )
+            }
+            fall_constraint(fakeram7_64x512_constraint_template) {
+                index_1 ("0.005, 0.125");
+                index_2 ("0.005, 0.125");
+                values ( \
+                  "0.007, 0.007", \
+                  "0.007, 0.007" \
+                )
+            }
+        }
+        internal_power(){
+            rise_power(fakeram7_64x512_energy_template_sigslew) {
+                index_1 ("0.005, 0.125");
+                values ("0.010, 0.010")
+            }
+            fall_power(fakeram7_64x512_energy_template_sigslew) {
+                index_1 ("0.005, 0.125");
+                values ("0.010, 0.010")
+            }
+        }
+    }
+    bus(rw0_wd_in)   {
+        bus_type : fakeram7_64x512_DATA;
+        memory_write() {
+            address : rw0_addr_in;
+            clocked_on : "rw0_clk";
+        }
+        direction : input;
+        capacitance : 0.000488;
+        timing() {
+            related_pin     : rw0_clk;
+            timing_type     : setup_rising ;
+            rise_constraint(fakeram7_64x512_constraint_template) {
+                index_1 ("0.005, 0.125");
+                index_2 ("0.005, 0.125");
+                values ( \
+                  "0.007, 0.007", \
+                  "0.007, 0.007" \
+                )
+            }
+            fall_constraint(fakeram7_64x512_constraint_template) {
+                index_1 ("0.005, 0.125");
+                index_2 ("0.005, 0.125");
+                values ( \
+                  "0.007, 0.007", \
+                  "0.007, 0.007" \
+                )
+            }
+        } 
+        timing() {
+            related_pin     : rw0_clk;
+            timing_type     : hold_rising ;
+            rise_constraint(fakeram7_64x512_constraint_template) {
+                index_1 ("0.005, 0.125");
+                index_2 ("0.005, 0.125");
+                values ( \
+                  "0.007, 0.007", \
+                  "0.007, 0.007" \
+                )
+            }
+            fall_constraint(fakeram7_64x512_constraint_template) {
+                index_1 ("0.005, 0.125");
+                index_2 ("0.005, 0.125");
+                values ( \
+                  "0.007, 0.007", \
+                  "0.007, 0.007" \
+                )
+            }
+        }
+        internal_power(){
+            when : "(! (rw0_we_in) )";
+            rise_power(fakeram7_64x512_energy_template_sigslew) {
+                index_1 ("0.005, 0.125");
+                values ("0.010, 0.010")
+            }
+            fall_power(fakeram7_64x512_energy_template_sigslew) {
+                index_1 ("0.005, 0.125");
+                values ("0.010, 0.010")
+            }
+        }
+        internal_power(){
+            when : "(rw0_we_in)";
+            rise_power(fakeram7_64x512_energy_template_sigslew) {
+                index_1 ("0.005, 0.125");
+                values ("0.010, 0.010")
+            }
+            fall_power(fakeram7_64x512_energy_template_sigslew) {
+                index_1 ("0.005, 0.125");
+                values ("0.010, 0.010")
+            }
+        }
+    }
+    cell_leakage_power : 100.000;
+}
+
+}
diff --git a/designs/src/snitch_cluster/DECISIONS.md b/designs/src/snitch_cluster/DECISIONS.md
index a5ec05ca..6de9a8b1 100644
--- a/designs/src/snitch_cluster/DECISIONS.md
+++ b/designs/src/snitch_cluster/DECISIONS.md
@@ -6,7 +6,8 @@ Per-platform notes for `snitch_cluster` (PULP Snitch multi-core cluster, top
 Very large logic design (~1.5M std cells), no hard macros on asap7 beyond the 38 the
 wrapper instantiates. Carries `SKIP_CTS_REPAIR_TIMING` + `SKIP_INCREMENTAL_REPAIR`
 (repair non-convergence on the RTL-bounded endpoints) and, on asap7, a DPL-0036
-`PRE_CTS_TCL`. Only asap7 / nangate45 are in scope (no sky130hd port).
+`PRE_CTS_TCL`. asap7 / nangate45 / gt2n are in scope (no sky130hd port). gt2n does
+**not** carry the incremental-repair workaround -- see its `## gt2n` section.
 
 ## Hermetic RTL sourcing (2026-07)
 
@@ -50,3 +51,35 @@ The cluster is assembled hermetically by Bazel — no `dev/repo` submodule, no b
   flow ~14 h. Detail route converged cleanly (0 violations in 4 passes). Result: 1 333 473
   logic cells (+2.1 %), WNS **+5801 ps** (met; base +6035), Fmax 0.082 GHz (+2.5 %),
   power 368 mW. No SDC/RTL/flow change.
+
+## gt2n
+
+**Status**: finishing
+
+- **2026-09-07**: initial gt2n port. `CORE_UTILIZATION = 55` (`PLACE_DENSITY = 0.67`,
+  `MACRO_PLACE_HALO = 8 8`) is the practical ceiling on this platform for this design —
+  57-65% failed in three different ways depending on the exact density/halo combo tried:
+  a `DPL-0033` detailed-placement legalization failure, a one-time OpenROAD `SIGSEGV`
+  crash inside timing-driven global placement (util=57/density=0.64/halo=6 -- not clearly
+  tied to that specific value, cause unknown, may or may not recur), and multi-day
+  (20-36 h) non-convergence in placement/GRT with zero progress and no useful QoR.
+  `MACRO_PLACE_HALO` matters independently of utilization: `4` and `6` both failed at the
+  same ~57% utilization that `8` later succeeded at.
+- Clock period `6000 ps` (period_min 5990.98 ps, ratio 0.998). Input delay split
+  `-max 10 / -min 1500`, same values as asap7's SDC, modeling external launch-side
+  clock-tree latency.
+- **Unlike asap7/nangate45, gt2n does not need `SKIP_INCREMENTAL_REPAIR`.** Leaving
+  incremental repair enabled was the key to closing this design here: the post-GRT
+  `repair_timing` pass ran to completion in ~3.2 h, inserted 1481 hold buffers, and took
+  hold from an estimated -136 ps / 1301 violations down to +0.02 ps / 0 violations
+  pre-route. Do not copy the asap7/nangate45 `SKIP_CTS_REPAIR_TIMING` /
+  `SKIP_INCREMENTAL_REPAIR` pair onto gt2n by default -- it isn't needed and defeats the
+  repair pass that actually closes this design.
+- Setup closes fully clean: WNS +9.02 ps, 0 violations. Hold has 9 residual violations
+  (worst -8.56 ps, TNS -25.89) that appear post-route -- real detail-route parasitics
+  shifted a handful of paths slightly negative after the pre-route repair pass had
+  already gotten them to ~0. A `HOLD_SLACK_MARGIN` retry to chase full closure was
+  considered and not attempted: the residual is already smaller than what other
+  "finishing" gt2n designs in this repo carry (e.g. gemmini's 15 violations / -9.83 ps),
+  and each build attempt on this design costs 20+ hours with a real chance of the same
+  non-monotonic side effects `HOLD_SLACK_MARGIN` produced on gemmini's tuning.
diff --git a/designs/src/snitch_cluster/dev/generated/fakeram_gt2n.cfg b/designs/src/snitch_cluster/dev/generated/fakeram_gt2n.cfg
new file mode 100644
index 00000000..d838fb9d
--- /dev/null
+++ b/designs/src/snitch_cluster/dev/generated/fakeram_gt2n.cfg
@@ -0,0 +1,52 @@
+{
+  "tech_nm": 2,
+  "voltage": 0.7,
+  "metalPrefix": "M",
+
+  "LRpinWidth_nm": 12,
+  "LRpinPitch_nm": 24,
+  "LRpinLayer": "M2",
+
+  "TBpinWidth_nm": 14,
+  "TBpinPitch_nm": 28,
+  "TBpinLayer": "M3",
+
+  "flipPins": false,
+  "snapWidth_nm": 42,
+  "snapHeight_nm": 144,
+
+  "srams": [
+    {
+      "name": "fakeram7_64x512",
+      "width": 512,
+      "depth": 64,
+      "banks": 1,
+      "no_wmask": "true",
+      "ports": {"r": 0, "w": 0, "rw": 1}
+    },
+    {
+      "name": "fakeram7_256x64",
+      "width": 64,
+      "depth": 256,
+      "banks": 1,
+      "no_wmask": "true",
+      "ports": {"r": 0, "w": 0, "rw": 1}
+    },
+    {
+      "name": "fakeram7_256x256",
+      "width": 256,
+      "depth": 256,
+      "banks": 1,
+      "no_wmask": "true",
+      "ports": {"r": 0, "w": 0, "rw": 1}
+    },
+    {
+      "name": "fakeram7_128x48",
+      "width": 48,
+      "depth": 128,
+      "banks": 1,
+      "no_wmask": "true",
+      "ports": {"r": 0, "w": 0, "rw": 1}
+    }
+  ]
+}