From b6803abbacf5beb83469dfa90e8d0b275f52cab1 Mon Sep 17 00:00:00 2001 From: Vladimir Shiryaev Date: Sat, 20 Jun 2026 15:32:38 -0700 Subject: [PATCH 1/2] [mlir][dxsa] Add dadd, ddiv, dmax, dmin, dmul and drcp instructions Example: dxsa.dadd r<0>, r<1>, r<2> dxsa.ddiv r<0>, r<1>, r<2> dxsa.dmax r<0>, r<1>, r<2> dxsa.dmin r<0>, r<1>, r<2> dxsa.dmul r<0>, r<1>, r<2> dxsa.drcp r<0>, r<1> Signed-off-by: Vladimir Shiryaev --- .../Dialect/DXSA/IR/DXSADoubleArithOps.td | 308 ++++++++++++++++++ mlir/include/mlir/Dialect/DXSA/IR/DXSAOps.td | 1 + mlir/lib/Target/DXSA/BinaryParser.cpp | 13 + mlir/test/Target/DXSA/double/dadd.mlir | 15 + mlir/test/Target/DXSA/double/ddiv.mlir | 15 + mlir/test/Target/DXSA/double/dmax.mlir | 15 + mlir/test/Target/DXSA/double/dmin.mlir | 15 + mlir/test/Target/DXSA/double/dmul.mlir | 15 + mlir/test/Target/DXSA/double/drcp.mlir | 15 + 9 files changed, 412 insertions(+) create mode 100644 mlir/include/mlir/Dialect/DXSA/IR/DXSADoubleArithOps.td create mode 100644 mlir/test/Target/DXSA/double/dadd.mlir create mode 100644 mlir/test/Target/DXSA/double/ddiv.mlir create mode 100644 mlir/test/Target/DXSA/double/dmax.mlir create mode 100644 mlir/test/Target/DXSA/double/dmin.mlir create mode 100644 mlir/test/Target/DXSA/double/dmul.mlir create mode 100644 mlir/test/Target/DXSA/double/drcp.mlir diff --git a/mlir/include/mlir/Dialect/DXSA/IR/DXSADoubleArithOps.td b/mlir/include/mlir/Dialect/DXSA/IR/DXSADoubleArithOps.td new file mode 100644 index 000000000000..7c36f2a9a444 --- /dev/null +++ b/mlir/include/mlir/Dialect/DXSA/IR/DXSADoubleArithOps.td @@ -0,0 +1,308 @@ +//===- DXSADoubleArithOps.td - DXSA double arithmetic ops -*- tablegen -*-===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// +// +// Double-precision arithmetic instructions of the DXSA dialect. +// +//===----------------------------------------------------------------------===// + +#ifndef MLIR_DIALECT_DXSA_IR_DXSADOUBLEARITHOPS +#define MLIR_DIALECT_DXSA_IR_DXSADOUBLEARITHOPS + +include "mlir/Dialect/DXSA/IR/DXSAOpBase.td" + +//===----------------------------------------------------------------------===// +// dxsa.dadd +//===----------------------------------------------------------------------===// + +def DXSA_Dadd : DXSA_BinaryOp<"dadd"> { + let summary = "component-wise double-precision add"; + let description = [{ + The `dxsa.dadd` operation computes the component-wise double-precision + sum `$dst = $lhs + $rhs`. Each operand holds a vector of doubles, one + double per `xy` and `zw` component pair. + + Because each double spans a component pair, the destination write mask must + be ``, ``, or ``, and each source swizzle must be + one of ``, ``, ``, or ``. + + Example: + + ```mlir + dxsa.dadd r<0>, r<1>, r<2> + dxsa.dadd r<0, >, r<1, >, -r<2> + ``` + }]; +} + +//===----------------------------------------------------------------------===// +// dxsa.dadd_sat +//===----------------------------------------------------------------------===// + +def DXSA_DaddSat : DXSA_BinaryOp<"dadd_sat"> { + let summary = "component-wise double-precision add, saturated to [0, 1]"; + let description = [{ + The `dxsa.dadd_sat` operation computes the component-wise double-precision + sum of `$lhs` and `$rhs`, clamps each result component to `[0.0, 1.0]`, + and writes it to `$dst`. + + Because each double spans a component pair, the destination write mask must + be ``, ``, or ``, and each source swizzle must be + one of ``, ``, ``, or ``. + + Example: + + ```mlir + dxsa.dadd_sat r<0>, r<1>, r<2> + dxsa.dadd_sat r<0, >, r<1, >, -r<2> + ``` + }]; +} + +//===----------------------------------------------------------------------===// +// dxsa.ddiv +//===----------------------------------------------------------------------===// + +def DXSA_Ddiv : DXSA_BinaryOp<"ddiv"> { + let summary = "component-wise double-precision divide"; + let description = [{ + The `dxsa.ddiv` operation computes the component-wise double-precision + quotient `$dst = $lhs / $rhs`. Each operand holds a vector of doubles, one + double per `xy` and `zw` component pair. + + Because each double spans a component pair, the destination write mask must + be ``, ``, or ``, and each source swizzle must be + one of ``, ``, ``, or ``. + + Example: + + ```mlir + dxsa.ddiv r<0>, r<1>, r<2> + dxsa.ddiv r<0, >, r<1, >, -r<2> + ``` + }]; +} + +//===----------------------------------------------------------------------===// +// dxsa.ddiv_sat +//===----------------------------------------------------------------------===// + +def DXSA_DdivSat : DXSA_BinaryOp<"ddiv_sat"> { + let summary = "component-wise double-precision divide, saturated to [0, 1]"; + let description = [{ + The `dxsa.ddiv_sat` operation computes the component-wise double-precision + quotient of `$lhs` and `$rhs`, clamps each result component to + `[0.0, 1.0]`, and writes it to `$dst`. + + Because each double spans a component pair, the destination write mask must + be ``, ``, or ``, and each source swizzle must be + one of ``, ``, ``, or ``. + + Example: + + ```mlir + dxsa.ddiv_sat r<0>, r<1>, r<2> + dxsa.ddiv_sat r<0, >, r<1, >, -r<2> + ``` + }]; +} + +//===----------------------------------------------------------------------===// +// dxsa.dmax +//===----------------------------------------------------------------------===// + +def DXSA_Dmax : DXSA_BinaryOp<"dmax"> { + let summary = "component-wise double-precision maximum"; + let description = [{ + The `dxsa.dmax` operation computes the component-wise double-precision + maximum `$dst = $lhs >= $rhs ? $lhs : $rhs`. If one source component is + NaN, the other source component is returned. + + Because each double spans a component pair, the destination write mask must + be ``, ``, or ``, and each source swizzle must be + one of ``, ``, ``, or ``. + + Example: + + ```mlir + dxsa.dmax r<0>, r<1>, r<2> + dxsa.dmax r<0, >, r<1, >, -r<2> + ``` + }]; +} + +//===----------------------------------------------------------------------===// +// dxsa.dmax_sat +//===----------------------------------------------------------------------===// + +def DXSA_DmaxSat : DXSA_BinaryOp<"dmax_sat"> { + let summary = "component-wise double-precision maximum, saturated to [0, 1]"; + let description = [{ + The `dxsa.dmax_sat` operation computes the component-wise double-precision + maximum of `$lhs` and `$rhs`, clamps each result component to `[0.0, 1.0]`, + and writes it to `$dst`. If one source component is NaN, the other source + component is used. + + Because each double spans a component pair, the destination write mask must + be ``, ``, or ``, and each source swizzle must be + one of ``, ``, ``, or ``. + + Example: + + ```mlir + dxsa.dmax_sat r<0>, r<1>, r<2> + dxsa.dmax_sat r<0, >, r<1, >, -r<2> + ``` + }]; +} + +//===----------------------------------------------------------------------===// +// dxsa.dmin +//===----------------------------------------------------------------------===// + +def DXSA_Dmin : DXSA_BinaryOp<"dmin"> { + let summary = "component-wise double-precision minimum"; + let description = [{ + The `dxsa.dmin` operation computes the component-wise double-precision + minimum `$dst = $lhs < $rhs ? $lhs : $rhs`. If one source component is + NaN, the other source component is returned. + + Because each double spans a component pair, the destination write mask must + be ``, ``, or ``, and each source swizzle must be + one of ``, ``, ``, or ``. + + Example: + + ```mlir + dxsa.dmin r<0>, r<1>, r<2> + dxsa.dmin r<0, >, r<1, >, -r<2> + ``` + }]; +} + +//===----------------------------------------------------------------------===// +// dxsa.dmin_sat +//===----------------------------------------------------------------------===// + +def DXSA_DminSat : DXSA_BinaryOp<"dmin_sat"> { + let summary = "component-wise double-precision minimum, saturated to [0, 1]"; + let description = [{ + The `dxsa.dmin_sat` operation computes the component-wise double-precision + minimum of `$lhs` and `$rhs`, clamps each result component to `[0.0, 1.0]`, + and writes it to `$dst`. If one source component is NaN, the other source + component is used. + + Because each double spans a component pair, the destination write mask must + be ``, ``, or ``, and each source swizzle must be + one of ``, ``, ``, or ``. + + Example: + + ```mlir + dxsa.dmin_sat r<0>, r<1>, r<2> + dxsa.dmin_sat r<0, >, r<1, >, -r<2> + ``` + }]; +} + +//===----------------------------------------------------------------------===// +// dxsa.dmul +//===----------------------------------------------------------------------===// + +def DXSA_Dmul : DXSA_BinaryOp<"dmul"> { + let summary = "component-wise double-precision multiply"; + let description = [{ + The `dxsa.dmul` operation computes the component-wise double-precision + product `$dst = $lhs * $rhs`. Each operand holds a vector of doubles, one + double per `xy` and `zw` component pair. + + Because each double spans a component pair, the destination write mask must + be ``, ``, or ``, and each source swizzle must be + one of ``, ``, ``, or ``. + + Example: + + ```mlir + dxsa.dmul r<0>, r<1>, r<2> + dxsa.dmul r<0, >, r<1, >, -r<2> + ``` + }]; +} + +//===----------------------------------------------------------------------===// +// dxsa.dmul_sat +//===----------------------------------------------------------------------===// + +def DXSA_DmulSat : DXSA_BinaryOp<"dmul_sat"> { + let summary = "component-wise double-precision multiply, saturated to [0, 1]"; + let description = [{ + The `dxsa.dmul_sat` operation computes the component-wise double-precision + product of `$lhs` and `$rhs`, clamps each result component to `[0.0, 1.0]`, + and writes it to `$dst`. + + Because each double spans a component pair, the destination write mask must + be ``, ``, or ``, and each source swizzle must be + one of ``, ``, ``, or ``. + + Example: + + ```mlir + dxsa.dmul_sat r<0>, r<1>, r<2> + dxsa.dmul_sat r<0, >, r<1, >, -r<2> + ``` + }]; +} + +//===----------------------------------------------------------------------===// +// dxsa.drcp +//===----------------------------------------------------------------------===// + +def DXSA_Drcp : DXSA_UnaryOp<"drcp"> { + let summary = "component-wise double-precision reciprocal"; + let description = [{ + The `dxsa.drcp` operation computes the component-wise double-precision + reciprocal `$dst = 1.0 / $src`. Each operand holds a vector of doubles, one + double per `xy` and `zw` component pair. + + Because each double spans a component pair, the destination write mask must + be ``, ``, or ``, and the source swizzle must be + one of ``, ``, ``, or ``. + + Example: + + ```mlir + dxsa.drcp r<0>, r<1> + dxsa.drcp r<0, >, -r<1, > + ``` + }]; +} + +//===----------------------------------------------------------------------===// +// dxsa.drcp_sat +//===----------------------------------------------------------------------===// + +def DXSA_DrcpSat : DXSA_UnaryOp<"drcp_sat"> { + let summary = "component-wise double-precision reciprocal, saturated to [0, 1]"; + let description = [{ + The `dxsa.drcp_sat` operation computes the component-wise double-precision + reciprocal of `$src`, clamps each result component to `[0.0, 1.0]`, and + writes it to `$dst`. + + Because each double spans a component pair, the destination write mask must + be ``, ``, or ``, and the source swizzle must be + one of ``, ``, ``, or ``. + + Example: + + ```mlir + dxsa.drcp_sat r<0>, r<1> + dxsa.drcp_sat r<0, >, -r<1, > + ``` + }]; +} + +#endif // MLIR_DIALECT_DXSA_IR_DXSADOUBLEARITHOPS diff --git a/mlir/include/mlir/Dialect/DXSA/IR/DXSAOps.td b/mlir/include/mlir/Dialect/DXSA/IR/DXSAOps.td index 54e5b8ed7a33..a0795c98e546 100644 --- a/mlir/include/mlir/Dialect/DXSA/IR/DXSAOps.td +++ b/mlir/include/mlir/Dialect/DXSA/IR/DXSAOps.td @@ -12,6 +12,7 @@ include "mlir/Dialect/DXSA/IR/DXSAOpBase.td" include "mlir/Dialect/DXSA/IR/DXSATypes.td" include "mlir/Dialect/DXSA/IR/DXSAFPArithOps.td" +include "mlir/Dialect/DXSA/IR/DXSADoubleArithOps.td" include "mlir/Dialect/DXSA/IR/DXSAConditionOps.td" include "mlir/Dialect/DXSA/IR/DXSABitwiseOps.td" include "mlir/Dialect/DXSA/IR/DXSATypeConversionOps.td" diff --git a/mlir/lib/Target/DXSA/BinaryParser.cpp b/mlir/lib/Target/DXSA/BinaryParser.cpp index b783e6be85f8..12ef61ab7bf0 100644 --- a/mlir/lib/Target/DXSA/BinaryParser.cpp +++ b/mlir/lib/Target/DXSA/BinaryParser.cpp @@ -2426,6 +2426,19 @@ class Parser { return PLAIN_OP(AtomicUMax, 1, 2, HasPreciseAttr::No); case D3D11_SB_OPCODE_ATOMIC_UMIN: return PLAIN_OP(AtomicUMin, 1, 2, HasPreciseAttr::No); + // Double-precision arithmetic instructions + case D3D11_SB_OPCODE_DADD: + return SATURABLE_OP(Dadd, 1, 2, HasPreciseAttr::Yes); + case D3D11_SB_OPCODE_DMAX: + return SATURABLE_OP(Dmax, 1, 2, HasPreciseAttr::Yes); + case D3D11_SB_OPCODE_DMIN: + return SATURABLE_OP(Dmin, 1, 2, HasPreciseAttr::Yes); + case D3D11_SB_OPCODE_DMUL: + return SATURABLE_OP(Dmul, 1, 2, HasPreciseAttr::Yes); + case D3D11_1_SB_OPCODE_DDIV: + return SATURABLE_OP(Ddiv, 1, 2, HasPreciseAttr::Yes); + case D3D11_1_SB_OPCODE_DRCP: + return SATURABLE_OP(Drcp, 1, 1, HasPreciseAttr::Yes); } #undef SATURABLE_OP #undef PLAIN_OP diff --git a/mlir/test/Target/DXSA/double/dadd.mlir b/mlir/test/Target/DXSA/double/dadd.mlir new file mode 100644 index 000000000000..4e9dc1b9728c --- /dev/null +++ b/mlir/test/Target/DXSA/double/dadd.mlir @@ -0,0 +1,15 @@ +// RUN: mlir-translate --import-dxsa-hex %s | FileCheck %s +// RUN: mlir-translate --import-dxsa-hex %s | mlir-opt --verify-roundtrip + +// CHECK: dxsa.module { + +// CHECK-NEXT: dxsa.dadd r<0>, r<1>, r<2> +0x070000bf, 0x001000f2, 0x00000000, 0x00100e46, 0x00000001, 0x00100e46, 0x00000002 + +// CHECK-NEXT: dxsa.dadd_sat r<0>, r<1>, r<2> +0x070020bf, 0x001000f2, 0x00000000, 0x00100e46, 0x00000001, 0x00100e46, 0x00000002 + +// CHECK-NEXT: dxsa.dadd r<0>, -r<1>, |r<2>| +0x090000bf, 0x001000f2, 0x00000000, 0x80100e46, 0x00000041, 0x00000001, 0x80100e46, 0x00000081, 0x00000002 + +// CHECK-NEXT: } diff --git a/mlir/test/Target/DXSA/double/ddiv.mlir b/mlir/test/Target/DXSA/double/ddiv.mlir new file mode 100644 index 000000000000..ec266edc5a28 --- /dev/null +++ b/mlir/test/Target/DXSA/double/ddiv.mlir @@ -0,0 +1,15 @@ +// RUN: mlir-translate --import-dxsa-hex %s | FileCheck %s +// RUN: mlir-translate --import-dxsa-hex %s | mlir-opt --verify-roundtrip + +// CHECK: dxsa.module { + +// CHECK-NEXT: dxsa.ddiv r<0>, r<1>, r<2> +0x070000d2, 0x001000f2, 0x00000000, 0x00100e46, 0x00000001, 0x00100e46, 0x00000002 + +// CHECK-NEXT: dxsa.ddiv_sat r<0>, r<1>, r<2> +0x070020d2, 0x001000f2, 0x00000000, 0x00100e46, 0x00000001, 0x00100e46, 0x00000002 + +// CHECK-NEXT: dxsa.ddiv r<0>, -r<1>, |r<2>| +0x090000d2, 0x001000f2, 0x00000000, 0x80100e46, 0x00000041, 0x00000001, 0x80100e46, 0x00000081, 0x00000002 + +// CHECK-NEXT: } diff --git a/mlir/test/Target/DXSA/double/dmax.mlir b/mlir/test/Target/DXSA/double/dmax.mlir new file mode 100644 index 000000000000..de49c43220df --- /dev/null +++ b/mlir/test/Target/DXSA/double/dmax.mlir @@ -0,0 +1,15 @@ +// RUN: mlir-translate --import-dxsa-hex %s | FileCheck %s +// RUN: mlir-translate --import-dxsa-hex %s | mlir-opt --verify-roundtrip + +// CHECK: dxsa.module { + +// CHECK-NEXT: dxsa.dmax r<0>, r<1>, r<2> +0x070000c0, 0x001000f2, 0x00000000, 0x00100e46, 0x00000001, 0x00100e46, 0x00000002 + +// CHECK-NEXT: dxsa.dmax_sat r<0>, r<1>, r<2> +0x070020c0, 0x001000f2, 0x00000000, 0x00100e46, 0x00000001, 0x00100e46, 0x00000002 + +// CHECK-NEXT: dxsa.dmax r<0>, -r<1>, |r<2>| +0x090000c0, 0x001000f2, 0x00000000, 0x80100e46, 0x00000041, 0x00000001, 0x80100e46, 0x00000081, 0x00000002 + +// CHECK-NEXT: } diff --git a/mlir/test/Target/DXSA/double/dmin.mlir b/mlir/test/Target/DXSA/double/dmin.mlir new file mode 100644 index 000000000000..05a128d611eb --- /dev/null +++ b/mlir/test/Target/DXSA/double/dmin.mlir @@ -0,0 +1,15 @@ +// RUN: mlir-translate --import-dxsa-hex %s | FileCheck %s +// RUN: mlir-translate --import-dxsa-hex %s | mlir-opt --verify-roundtrip + +// CHECK: dxsa.module { + +// CHECK-NEXT: dxsa.dmin r<0>, r<1>, r<2> +0x070000c1, 0x001000f2, 0x00000000, 0x00100e46, 0x00000001, 0x00100e46, 0x00000002 + +// CHECK-NEXT: dxsa.dmin_sat r<0>, r<1>, r<2> +0x070020c1, 0x001000f2, 0x00000000, 0x00100e46, 0x00000001, 0x00100e46, 0x00000002 + +// CHECK-NEXT: dxsa.dmin r<0>, -r<1>, |r<2>| +0x090000c1, 0x001000f2, 0x00000000, 0x80100e46, 0x00000041, 0x00000001, 0x80100e46, 0x00000081, 0x00000002 + +// CHECK-NEXT: } diff --git a/mlir/test/Target/DXSA/double/dmul.mlir b/mlir/test/Target/DXSA/double/dmul.mlir new file mode 100644 index 000000000000..e2f235961852 --- /dev/null +++ b/mlir/test/Target/DXSA/double/dmul.mlir @@ -0,0 +1,15 @@ +// RUN: mlir-translate --import-dxsa-hex %s | FileCheck %s +// RUN: mlir-translate --import-dxsa-hex %s | mlir-opt --verify-roundtrip + +// CHECK: dxsa.module { + +// CHECK-NEXT: dxsa.dmul r<0>, r<1>, r<2> +0x070000c2, 0x001000f2, 0x00000000, 0x00100e46, 0x00000001, 0x00100e46, 0x00000002 + +// CHECK-NEXT: dxsa.dmul_sat r<0>, r<1>, r<2> +0x070020c2, 0x001000f2, 0x00000000, 0x00100e46, 0x00000001, 0x00100e46, 0x00000002 + +// CHECK-NEXT: dxsa.dmul r<0>, -r<1>, |r<2>| +0x090000c2, 0x001000f2, 0x00000000, 0x80100e46, 0x00000041, 0x00000001, 0x80100e46, 0x00000081, 0x00000002 + +// CHECK-NEXT: } diff --git a/mlir/test/Target/DXSA/double/drcp.mlir b/mlir/test/Target/DXSA/double/drcp.mlir new file mode 100644 index 000000000000..33af7a82261a --- /dev/null +++ b/mlir/test/Target/DXSA/double/drcp.mlir @@ -0,0 +1,15 @@ +// RUN: mlir-translate --import-dxsa-hex %s | FileCheck %s +// RUN: mlir-translate --import-dxsa-hex %s | mlir-opt --verify-roundtrip + +// CHECK: dxsa.module { + +// CHECK-NEXT: dxsa.drcp r<0>, r<1> +0x050000d4, 0x001000f2, 0x00000000, 0x00100e46, 0x00000001 + +// CHECK-NEXT: dxsa.drcp_sat r<0>, r<1> +0x050020d4, 0x001000f2, 0x00000000, 0x00100e46, 0x00000001 + +// CHECK-NEXT: dxsa.drcp r<0>, -|r<1>| +0x060000d4, 0x001000f2, 0x00000000, 0x80100e46, 0x000000c1, 0x00000001 + +// CHECK-NEXT: } From f393bc7cb0450b2c048e58581b478ab777e866c6 Mon Sep 17 00:00:00 2001 From: Vladimir Shiryaev Date: Thu, 25 Jun 2026 13:01:55 -0700 Subject: [PATCH 2/2] [mlir][dxsa][NFC] Consolidate double arithmetic tests into single file with --split-input-file Signed-off-by: Vladimir Shiryaev --- mlir/test/Target/DXSA/double/dadd.mlir | 15 ---- mlir/test/Target/DXSA/double/ddiv.mlir | 15 ---- mlir/test/Target/DXSA/double/dmax.mlir | 15 ---- mlir/test/Target/DXSA/double/dmin.mlir | 15 ---- mlir/test/Target/DXSA/double/dmul.mlir | 15 ---- mlir/test/Target/DXSA/double/drcp.mlir | 15 ---- mlir/test/Target/DXSA/double_arith_ops.test | 84 +++++++++++++++++++++ 7 files changed, 84 insertions(+), 90 deletions(-) delete mode 100644 mlir/test/Target/DXSA/double/dadd.mlir delete mode 100644 mlir/test/Target/DXSA/double/ddiv.mlir delete mode 100644 mlir/test/Target/DXSA/double/dmax.mlir delete mode 100644 mlir/test/Target/DXSA/double/dmin.mlir delete mode 100644 mlir/test/Target/DXSA/double/dmul.mlir delete mode 100644 mlir/test/Target/DXSA/double/drcp.mlir create mode 100644 mlir/test/Target/DXSA/double_arith_ops.test diff --git a/mlir/test/Target/DXSA/double/dadd.mlir b/mlir/test/Target/DXSA/double/dadd.mlir deleted file mode 100644 index 4e9dc1b9728c..000000000000 --- a/mlir/test/Target/DXSA/double/dadd.mlir +++ /dev/null @@ -1,15 +0,0 @@ -// RUN: mlir-translate --import-dxsa-hex %s | FileCheck %s -// RUN: mlir-translate --import-dxsa-hex %s | mlir-opt --verify-roundtrip - -// CHECK: dxsa.module { - -// CHECK-NEXT: dxsa.dadd r<0>, r<1>, r<2> -0x070000bf, 0x001000f2, 0x00000000, 0x00100e46, 0x00000001, 0x00100e46, 0x00000002 - -// CHECK-NEXT: dxsa.dadd_sat r<0>, r<1>, r<2> -0x070020bf, 0x001000f2, 0x00000000, 0x00100e46, 0x00000001, 0x00100e46, 0x00000002 - -// CHECK-NEXT: dxsa.dadd r<0>, -r<1>, |r<2>| -0x090000bf, 0x001000f2, 0x00000000, 0x80100e46, 0x00000041, 0x00000001, 0x80100e46, 0x00000081, 0x00000002 - -// CHECK-NEXT: } diff --git a/mlir/test/Target/DXSA/double/ddiv.mlir b/mlir/test/Target/DXSA/double/ddiv.mlir deleted file mode 100644 index ec266edc5a28..000000000000 --- a/mlir/test/Target/DXSA/double/ddiv.mlir +++ /dev/null @@ -1,15 +0,0 @@ -// RUN: mlir-translate --import-dxsa-hex %s | FileCheck %s -// RUN: mlir-translate --import-dxsa-hex %s | mlir-opt --verify-roundtrip - -// CHECK: dxsa.module { - -// CHECK-NEXT: dxsa.ddiv r<0>, r<1>, r<2> -0x070000d2, 0x001000f2, 0x00000000, 0x00100e46, 0x00000001, 0x00100e46, 0x00000002 - -// CHECK-NEXT: dxsa.ddiv_sat r<0>, r<1>, r<2> -0x070020d2, 0x001000f2, 0x00000000, 0x00100e46, 0x00000001, 0x00100e46, 0x00000002 - -// CHECK-NEXT: dxsa.ddiv r<0>, -r<1>, |r<2>| -0x090000d2, 0x001000f2, 0x00000000, 0x80100e46, 0x00000041, 0x00000001, 0x80100e46, 0x00000081, 0x00000002 - -// CHECK-NEXT: } diff --git a/mlir/test/Target/DXSA/double/dmax.mlir b/mlir/test/Target/DXSA/double/dmax.mlir deleted file mode 100644 index de49c43220df..000000000000 --- a/mlir/test/Target/DXSA/double/dmax.mlir +++ /dev/null @@ -1,15 +0,0 @@ -// RUN: mlir-translate --import-dxsa-hex %s | FileCheck %s -// RUN: mlir-translate --import-dxsa-hex %s | mlir-opt --verify-roundtrip - -// CHECK: dxsa.module { - -// CHECK-NEXT: dxsa.dmax r<0>, r<1>, r<2> -0x070000c0, 0x001000f2, 0x00000000, 0x00100e46, 0x00000001, 0x00100e46, 0x00000002 - -// CHECK-NEXT: dxsa.dmax_sat r<0>, r<1>, r<2> -0x070020c0, 0x001000f2, 0x00000000, 0x00100e46, 0x00000001, 0x00100e46, 0x00000002 - -// CHECK-NEXT: dxsa.dmax r<0>, -r<1>, |r<2>| -0x090000c0, 0x001000f2, 0x00000000, 0x80100e46, 0x00000041, 0x00000001, 0x80100e46, 0x00000081, 0x00000002 - -// CHECK-NEXT: } diff --git a/mlir/test/Target/DXSA/double/dmin.mlir b/mlir/test/Target/DXSA/double/dmin.mlir deleted file mode 100644 index 05a128d611eb..000000000000 --- a/mlir/test/Target/DXSA/double/dmin.mlir +++ /dev/null @@ -1,15 +0,0 @@ -// RUN: mlir-translate --import-dxsa-hex %s | FileCheck %s -// RUN: mlir-translate --import-dxsa-hex %s | mlir-opt --verify-roundtrip - -// CHECK: dxsa.module { - -// CHECK-NEXT: dxsa.dmin r<0>, r<1>, r<2> -0x070000c1, 0x001000f2, 0x00000000, 0x00100e46, 0x00000001, 0x00100e46, 0x00000002 - -// CHECK-NEXT: dxsa.dmin_sat r<0>, r<1>, r<2> -0x070020c1, 0x001000f2, 0x00000000, 0x00100e46, 0x00000001, 0x00100e46, 0x00000002 - -// CHECK-NEXT: dxsa.dmin r<0>, -r<1>, |r<2>| -0x090000c1, 0x001000f2, 0x00000000, 0x80100e46, 0x00000041, 0x00000001, 0x80100e46, 0x00000081, 0x00000002 - -// CHECK-NEXT: } diff --git a/mlir/test/Target/DXSA/double/dmul.mlir b/mlir/test/Target/DXSA/double/dmul.mlir deleted file mode 100644 index e2f235961852..000000000000 --- a/mlir/test/Target/DXSA/double/dmul.mlir +++ /dev/null @@ -1,15 +0,0 @@ -// RUN: mlir-translate --import-dxsa-hex %s | FileCheck %s -// RUN: mlir-translate --import-dxsa-hex %s | mlir-opt --verify-roundtrip - -// CHECK: dxsa.module { - -// CHECK-NEXT: dxsa.dmul r<0>, r<1>, r<2> -0x070000c2, 0x001000f2, 0x00000000, 0x00100e46, 0x00000001, 0x00100e46, 0x00000002 - -// CHECK-NEXT: dxsa.dmul_sat r<0>, r<1>, r<2> -0x070020c2, 0x001000f2, 0x00000000, 0x00100e46, 0x00000001, 0x00100e46, 0x00000002 - -// CHECK-NEXT: dxsa.dmul r<0>, -r<1>, |r<2>| -0x090000c2, 0x001000f2, 0x00000000, 0x80100e46, 0x00000041, 0x00000001, 0x80100e46, 0x00000081, 0x00000002 - -// CHECK-NEXT: } diff --git a/mlir/test/Target/DXSA/double/drcp.mlir b/mlir/test/Target/DXSA/double/drcp.mlir deleted file mode 100644 index 33af7a82261a..000000000000 --- a/mlir/test/Target/DXSA/double/drcp.mlir +++ /dev/null @@ -1,15 +0,0 @@ -// RUN: mlir-translate --import-dxsa-hex %s | FileCheck %s -// RUN: mlir-translate --import-dxsa-hex %s | mlir-opt --verify-roundtrip - -// CHECK: dxsa.module { - -// CHECK-NEXT: dxsa.drcp r<0>, r<1> -0x050000d4, 0x001000f2, 0x00000000, 0x00100e46, 0x00000001 - -// CHECK-NEXT: dxsa.drcp_sat r<0>, r<1> -0x050020d4, 0x001000f2, 0x00000000, 0x00100e46, 0x00000001 - -// CHECK-NEXT: dxsa.drcp r<0>, -|r<1>| -0x060000d4, 0x001000f2, 0x00000000, 0x80100e46, 0x000000c1, 0x00000001 - -// CHECK-NEXT: } diff --git a/mlir/test/Target/DXSA/double_arith_ops.test b/mlir/test/Target/DXSA/double_arith_ops.test new file mode 100644 index 000000000000..030d652d03ee --- /dev/null +++ b/mlir/test/Target/DXSA/double_arith_ops.test @@ -0,0 +1,84 @@ +// RUN: mlir-translate --split-input-file --import-dxsa-hex %s | FileCheck %s +// RUN: mlir-translate --split-input-file --import-dxsa-hex %s | mlir-opt --split-input-file --verify-roundtrip + +// CHECK-LABEL: dxsa.module { +// CHECK-NEXT: dxsa.dadd r<0>, r<1>, r<2> +// CHECK-NEXT: } +0x070000bf, 0x001000f2, 0x00000000, 0x00100e46, 0x00000001, 0x00100e46, 0x00000002 + +// ----- + +// CHECK-LABEL: dxsa.module { +// CHECK-NEXT: dxsa.dadd_sat r<0>, r<1>, r<2> +// CHECK-NEXT: } +0x070020bf, 0x001000f2, 0x00000000, 0x00100e46, 0x00000001, 0x00100e46, 0x00000002 + +// ----- + +// CHECK-LABEL: dxsa.module { +// CHECK-NEXT: dxsa.dmax r<0>, r<1>, r<2> +// CHECK-NEXT: } +0x070000c0, 0x001000f2, 0x00000000, 0x00100e46, 0x00000001, 0x00100e46, 0x00000002 + +// ----- + +// CHECK-LABEL: dxsa.module { +// CHECK-NEXT: dxsa.dmax_sat r<0>, r<1>, r<2> +// CHECK-NEXT: } +0x070020c0, 0x001000f2, 0x00000000, 0x00100e46, 0x00000001, 0x00100e46, 0x00000002 + +// ----- + +// CHECK-LABEL: dxsa.module { +// CHECK-NEXT: dxsa.dmin r<0>, r<1>, r<2> +// CHECK-NEXT: } +0x070000c1, 0x001000f2, 0x00000000, 0x00100e46, 0x00000001, 0x00100e46, 0x00000002 + +// ----- + +// CHECK-LABEL: dxsa.module { +// CHECK-NEXT: dxsa.dmin_sat r<0>, r<1>, r<2> +// CHECK-NEXT: } +0x070020c1, 0x001000f2, 0x00000000, 0x00100e46, 0x00000001, 0x00100e46, 0x00000002 + +// ----- + +// CHECK-LABEL: dxsa.module { +// CHECK-NEXT: dxsa.dmul r<0>, r<1>, r<2> +// CHECK-NEXT: } +0x070000c2, 0x001000f2, 0x00000000, 0x00100e46, 0x00000001, 0x00100e46, 0x00000002 + +// ----- + +// CHECK-LABEL: dxsa.module { +// CHECK-NEXT: dxsa.dmul_sat r<0>, r<1>, r<2> +// CHECK-NEXT: } +0x070020c2, 0x001000f2, 0x00000000, 0x00100e46, 0x00000001, 0x00100e46, 0x00000002 + +// ----- + +// CHECK-LABEL: dxsa.module { +// CHECK-NEXT: dxsa.ddiv r<0>, r<1>, r<2> +// CHECK-NEXT: } +0x070000d2, 0x001000f2, 0x00000000, 0x00100e46, 0x00000001, 0x00100e46, 0x00000002 + +// ----- + +// CHECK-LABEL: dxsa.module { +// CHECK-NEXT: dxsa.ddiv_sat r<0>, r<1>, r<2> +// CHECK-NEXT: } +0x070020d2, 0x001000f2, 0x00000000, 0x00100e46, 0x00000001, 0x00100e46, 0x00000002 + +// ----- + +// CHECK-LABEL: dxsa.module { +// CHECK-NEXT: dxsa.drcp r<0>, r<1> +// CHECK-NEXT: } +0x050000d4, 0x001000f2, 0x00000000, 0x00100e46, 0x00000001 + +// ----- + +// CHECK-LABEL: dxsa.module { +// CHECK-NEXT: dxsa.drcp_sat r<0>, r<1> +// CHECK-NEXT: } +0x050020d4, 0x001000f2, 0x00000000, 0x00100e46, 0x00000001