diff --git a/mlir/include/mlir/Dialect/DXSA/IR/DXSAIntArithOps.td b/mlir/include/mlir/Dialect/DXSA/IR/DXSAIntArithOps.td
new file mode 100644
index 000000000000..667e80b9e508
--- /dev/null
+++ b/mlir/include/mlir/Dialect/DXSA/IR/DXSAIntArithOps.td
@@ -0,0 +1,137 @@
+//===- DXSAIntArithOps.td - DXSA integer arithmetic ops -*- tablegen -*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+//
+// Integer arithmetic instructions of the DXSA dialect.
+//
+//===----------------------------------------------------------------------===//
+
+#ifndef MLIR_DIALECT_DXSA_IR_DXSAINTARITHOPS
+#define MLIR_DIALECT_DXSA_IR_DXSAINTARITHOPS
+
+include "mlir/Dialect/DXSA/IR/DXSAOpBase.td"
+
+//===----------------------------------------------------------------------===//
+// dxsa.iadd
+//===----------------------------------------------------------------------===//
+
+def DXSA_IAdd : DXSA_BinaryOp<"iadd"> {
+  let summary = "component-wise integer add";
+  let description = [{
+    The `dxsa.iadd` operation computes the component-wise sum of two 32-bit
+    integers, `$dst = $lhs + $rhs`. No carry or borrow beyond the 32-bit
+    value of each component is performed, so the result is not sensitive to
+    the signedness of its operands.
+
+    Example:
+
+    ```mlir
+    dxsa.iadd r<0>, r<1>, r<2>
+    dxsa.iadd r<0>, -r<1>, -r<2>
+    dxsa.iadd r<0, <x>>, r<1, <y, z, w, y>>, r<2, <x, x, x, x>>
+    ```
+  }];
+}
+
+//===----------------------------------------------------------------------===//
+// dxsa.imax
+//===----------------------------------------------------------------------===//
+
+def DXSA_IMax : DXSA_BinaryOp<"imax"> {
+  let summary = "component-wise signed integer maximum";
+  let description = [{
+    The `dxsa.imax` operation computes the component-wise maximum of two
+    32-bit signed integers, `$dst = $lhs > $rhs ? $lhs : $rhs`.
+
+    Example:
+
+    ```mlir
+    dxsa.imax r<0>, r<1>, r<2>
+    dxsa.imax r<0>, -r<1>, -r<2>
+    dxsa.imax r<0, <x>>, r<1, <y, z, w, y>>, r<2, <x, x, x, x>>
+    ```
+  }];
+}
+
+//===----------------------------------------------------------------------===//
+// dxsa.imin
+//===----------------------------------------------------------------------===//
+
+def DXSA_IMin : DXSA_BinaryOp<"imin"> {
+  let summary = "component-wise signed integer minimum";
+  let description = [{
+    The `dxsa.imin` operation computes the component-wise minimum of two
+    32-bit signed integers, `$dst = $lhs < $rhs ? $lhs : $rhs`.
+
+    Example:
+
+    ```mlir
+    dxsa.imin r<0>, r<1>, r<2>
+    dxsa.imin r<0>, -r<1>, -r<2>
+    dxsa.imin r<0, <x>>, r<1, <y, z, w, y>>, r<2, <x, x, x, x>>
+    ```
+  }];
+}
+
+//===----------------------------------------------------------------------===//
+// dxsa.ineg
+//===----------------------------------------------------------------------===//
+
+def DXSA_INeg : DXSA_UnaryOp<"ineg"> {
+  let summary = "component-wise integer two's complement";
+  let description = [{
+    The `dxsa.ineg` operation computes the component-wise two's complement of
+    each 32-bit integer in `$src`, `$dst = -$src`.
+
+    Example:
+
+    ```mlir
+    dxsa.ineg r<0>, r<1>
+    dxsa.ineg r<0, <x>>, r<1, <y, z, w, y>>
+    ```
+  }];
+}
+
+//===----------------------------------------------------------------------===//
+// dxsa.umax
+//===----------------------------------------------------------------------===//
+
+def DXSA_UMax : DXSA_BinaryOp<"umax"> {
+  let summary = "component-wise unsigned integer maximum";
+  let description = [{
+    The `dxsa.umax` operation computes the component-wise maximum of two
+    32-bit unsigned integers, `$dst = $lhs > $rhs ? $lhs : $rhs`.
+
+    Example:
+
+    ```mlir
+    dxsa.umax r<0>, r<1>, r<2>
+    dxsa.umax r<0, <x>>, r<1, <y, z, w, y>>, r<2, <x, x, x, x>>
+    ```
+  }];
+}
+
+//===----------------------------------------------------------------------===//
+// dxsa.umin
+//===----------------------------------------------------------------------===//
+
+def DXSA_UMin : DXSA_BinaryOp<"umin"> {
+  let summary = "component-wise unsigned integer minimum";
+  let description = [{
+    The `dxsa.umin` operation computes the component-wise minimum of two
+    32-bit unsigned integers, `$dst = $lhs < $rhs ? $lhs : $rhs`.
+
+    Example:
+
+    ```mlir
+    dxsa.umin r<0>, r<1>, r<2>
+    dxsa.umin r<0, <x>>, r<1, <y, z, w, y>>, r<2, <x, x, x, x>>
+    ```
+  }];
+}
+
+#endif // MLIR_DIALECT_DXSA_IR_DXSAINTARITHOPS
diff --git a/mlir/include/mlir/Dialect/DXSA/IR/DXSAOps.td b/mlir/include/mlir/Dialect/DXSA/IR/DXSAOps.td
index 54e5b8ed7a33..dc72b4f6fc4a 100644
--- a/mlir/include/mlir/Dialect/DXSA/IR/DXSAOps.td
+++ b/mlir/include/mlir/Dialect/DXSA/IR/DXSAOps.td
@@ -12,6 +12,7 @@
 include "mlir/Dialect/DXSA/IR/DXSAOpBase.td"
 include "mlir/Dialect/DXSA/IR/DXSATypes.td"
 include "mlir/Dialect/DXSA/IR/DXSAFPArithOps.td"
+include "mlir/Dialect/DXSA/IR/DXSAIntArithOps.td"
 include "mlir/Dialect/DXSA/IR/DXSAConditionOps.td"
 include "mlir/Dialect/DXSA/IR/DXSABitwiseOps.td"
 include "mlir/Dialect/DXSA/IR/DXSATypeConversionOps.td"
diff --git a/mlir/lib/Target/DXSA/BinaryParser.cpp b/mlir/lib/Target/DXSA/BinaryParser.cpp
index 4087143c5c6d..cf81a908e8d2 100644
--- a/mlir/lib/Target/DXSA/BinaryParser.cpp
+++ b/mlir/lib/Target/DXSA/BinaryParser.cpp
@@ -2392,6 +2392,19 @@ class Parser {
       return PLAIN_OP(Uge, 1, 2, HasPreciseAttr::Yes);
     case D3D10_SB_OPCODE_ULT:
       return PLAIN_OP(Ult, 1, 2, HasPreciseAttr::Yes);
+    // Integer arithmetic instructions
+    case D3D10_SB_OPCODE_IADD:
+      return PLAIN_OP(IAdd, 1, 2, HasPreciseAttr::Yes);
+    case D3D10_SB_OPCODE_IMAX:
+      return PLAIN_OP(IMax, 1, 2, HasPreciseAttr::Yes);
+    case D3D10_SB_OPCODE_IMIN:
+      return PLAIN_OP(IMin, 1, 2, HasPreciseAttr::Yes);
+    case D3D10_SB_OPCODE_INEG:
+      return PLAIN_OP(INeg, 1, 1, HasPreciseAttr::Yes);
+    case D3D10_SB_OPCODE_UMAX:
+      return PLAIN_OP(UMax, 1, 2, HasPreciseAttr::Yes);
+    case D3D10_SB_OPCODE_UMIN:
+      return PLAIN_OP(UMin, 1, 2, HasPreciseAttr::Yes);
     // Bitwise instructions
     case D3D10_SB_OPCODE_AND:
       return PLAIN_OP(And, 1, 2, HasPreciseAttr::Yes);
diff --git a/mlir/test/Target/DXSA/int_arith_ops.test b/mlir/test/Target/DXSA/int_arith_ops.test
new file mode 100644
index 000000000000..69081ad56bf8
--- /dev/null
+++ b/mlir/test/Target/DXSA/int_arith_ops.test
@@ -0,0 +1,105 @@
+// RUN: mlir-translate --split-input-file --import-dxsa-hex %s | FileCheck %s
+// RUN: mlir-translate --split-input-file --import-dxsa-hex %s | mlir-opt --split-input-file --verify-roundtrip
+
+// CHECK-LABEL: dxsa.module {
+// CHECK-NEXT:   dxsa.iadd r<0>, r<1>, r<2>
+// CHECK-NEXT: }
+0x0700001e, 0x001000f2, 0x00000000, 0x00100e46, 0x00000001, 0x00100e46, 0x00000002
+
+// -----
+
+// CHECK-LABEL: dxsa.module {
+// CHECK-NEXT:   dxsa.iadd r<0>, -r<1>, -r<2>
+// CHECK-NEXT: }
+0x0900001e, 0x001000f2, 0x00000000, 0x80100e46, 0x00000041, 0x00000001, 0x80100e46, 0x00000041, 0x00000002
+
+// -----
+
+// CHECK-LABEL: dxsa.module {
+// CHECK-NEXT:   dxsa.iadd r<0, <x>>, r<1, <y, z, w, y>>, r<2, <x, x, x, x>>
+// CHECK-NEXT: }
+0x0700001e, 0x00100012, 0x00000000, 0x00100796, 0x00000001, 0x00100006, 0x00000002
+
+// -----
+
+// CHECK-LABEL: dxsa.module {
+// CHECK-NEXT:   dxsa.imax r<0>, r<1>, r<2>
+// CHECK-NEXT: }
+0x07000024, 0x001000f2, 0x00000000, 0x00100e46, 0x00000001, 0x00100e46, 0x00000002
+
+// -----
+
+// CHECK-LABEL: dxsa.module {
+// CHECK-NEXT:   dxsa.imax r<0>, -r<1>, -r<2>
+// CHECK-NEXT: }
+0x09000024, 0x001000f2, 0x00000000, 0x80100e46, 0x00000041, 0x00000001, 0x80100e46, 0x00000041, 0x00000002
+
+// -----
+
+// CHECK-LABEL: dxsa.module {
+// CHECK-NEXT:   dxsa.imax r<0, <x>>, r<1, <y, z, w, y>>, r<2, <x, x, x, x>>
+// CHECK-NEXT: }
+0x07000024, 0x00100012, 0x00000000, 0x00100796, 0x00000001, 0x00100006, 0x00000002
+
+// -----
+
+// CHECK-LABEL: dxsa.module {
+// CHECK-NEXT:   dxsa.imin r<0>, r<1>, r<2>
+// CHECK-NEXT: }
+0x07000025, 0x001000f2, 0x00000000, 0x00100e46, 0x00000001, 0x00100e46, 0x00000002
+
+// -----
+
+// CHECK-LABEL: dxsa.module {
+// CHECK-NEXT:   dxsa.imin r<0>, -r<1>, -r<2>
+// CHECK-NEXT: }
+0x09000025, 0x001000f2, 0x00000000, 0x80100e46, 0x00000041, 0x00000001, 0x80100e46, 0x00000041, 0x00000002
+
+// -----
+
+// CHECK-LABEL: dxsa.module {
+// CHECK-NEXT:   dxsa.imin r<0, <x>>, r<1, <y, z, w, y>>, r<2, <x, x, x, x>>
+// CHECK-NEXT: }
+0x07000025, 0x00100012, 0x00000000, 0x00100796, 0x00000001, 0x00100006, 0x00000002
+
+// -----
+
+// CHECK-LABEL: dxsa.module {
+// CHECK-NEXT:   dxsa.ineg r<0>, r<1>
+// CHECK-NEXT: }
+0x05000028, 0x001000f2, 0x00000000, 0x00100e46, 0x00000001
+
+// -----
+
+// CHECK-LABEL: dxsa.module {
+// CHECK-NEXT:   dxsa.ineg r<0, <x>>, r<1, <y, z, w, y>>
+// CHECK-NEXT: }
+0x05000028, 0x00100012, 0x00000000, 0x00100796, 0x00000001
+
+// -----
+
+// CHECK-LABEL: dxsa.module {
+// CHECK-NEXT:   dxsa.umax r<0>, r<1>, r<2>
+// CHECK-NEXT: }
+0x07000053, 0x001000f2, 0x00000000, 0x00100e46, 0x00000001, 0x00100e46, 0x00000002
+
+// -----
+
+// CHECK-LABEL: dxsa.module {
+// CHECK-NEXT:   dxsa.umax r<0, <x>>, r<1, <y, z, w, y>>, r<2, <x, x, x, x>>
+// CHECK-NEXT: }
+0x07000053, 0x00100012, 0x00000000, 0x00100796, 0x00000001, 0x00100006, 0x00000002
+
+// -----
+
+// CHECK-LABEL: dxsa.module {
+// CHECK-NEXT:   dxsa.umin r<0>, r<1>, r<2>
+// CHECK-NEXT: }
+0x07000054, 0x001000f2, 0x00000000, 0x00100e46, 0x00000001, 0x00100e46, 0x00000002
+
+// -----
+
+// CHECK-LABEL: dxsa.module {
+// CHECK-NEXT:   dxsa.umin r<0, <x>>, r<1, <y, z, w, y>>, r<2, <x, x, x, x>>
+// CHECK-NEXT: }
+0x07000054, 0x00100012, 0x00000000, 0x00100796, 0x00000001, 0x00100006, 0x00000002