diff --git a/mlir/test/Target/DXSA/asm/call2.test b/mlir/test/Target/DXSA/asm/call2.test new file mode 100644 index 000000000000..3fca3f1e3d23 --- /dev/null +++ b/mlir/test/Target/DXSA/asm/call2.test @@ -0,0 +1,75 @@ +// RUN: mlir-translate --import-dxsa-bin %S/inputs/call2.shex | FileCheck %s +// NOTE: Assertions have been autogenerated by utils/generate-test-checks.py + + +// CHECK-LABEL: dxsa.dcl_global_flags +// CHECK: dxsa.dcl_input_ps linear v<0, > +// CHECK: dxsa.dcl_input_ps constant v<1, > +// CHECK: dxsa.dcl_output o<0, > +// CHECK: dxsa.dcl_temps 1 +// CHECK: %[[INDEX_0:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_0:.*]] = dxsa.operand %[[INDEX_0]] {mask = 112 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_1:.*]] = dxsa.index.imm {imm = 1 : i32} +// CHECK: %[[OPERAND_1:.*]] = dxsa.operand %[[INDEX_1]] {num_components = 4 : i32, swizzle = dense<[0, 1, 2, 2]> : vector<4xi32>, type = 1 : i32} +// CHECK: dxsa.instruction "mov" %[[OPERAND_0]], %[[OPERAND_1]] +// CHECK: %[[INDEX_2:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_2:.*]] = dxsa.operand %[[INDEX_2]] {num_components = 0 : i32, type = 10 : i32} +// CHECK: dxsa.instruction "call" %[[OPERAND_2]] +// CHECK: %[[INDEX_3:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_3:.*]] = dxsa.operand %[[INDEX_3]] {num_components = 4 : i32, one = 0 : i32, type = 0 : i32} +// CHECK: %[[INDEX_4:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_4:.*]] = dxsa.operand %[[INDEX_4]] {num_components = 0 : i32, type = 10 : i32} +// CHECK: dxsa.instruction "callc" %[[OPERAND_3]], %[[OPERAND_4]] +// CHECK: %[[INDEX_5:.*]] = dxsa.index.imm {imm = 1 : i32} +// CHECK: %[[OPERAND_5:.*]] = dxsa.operand %[[INDEX_5]] {num_components = 4 : i32, one = 0 : i32, type = 1 : i32} +// CHECK: dxsa.instruction "switch" %[[OPERAND_5]] +// CHECK: %[[OPERAND_6:.*]] = dxsa.operand.imm {imm = dense<1> : vector<1xi32>} +// CHECK: dxsa.instruction "case" %[[OPERAND_6]] +// CHECK: %[[INDEX_6:.*]] = dxsa.index.imm {imm = 2 : i32} +// CHECK: %[[OPERAND_7:.*]] = dxsa.operand %[[INDEX_6]] {num_components = 0 : i32, type = 10 : i32} +// CHECK: dxsa.instruction "call" %[[OPERAND_7]] +// CHECK: %[[INDEX_7:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_8:.*]] = dxsa.operand %[[INDEX_7]] {num_components = 4 : i32, one = 1 : i32, type = 0 : i32} +// CHECK: %[[INDEX_8:.*]] = dxsa.index.imm {imm = 1 : i32} +// CHECK: %[[OPERAND_9:.*]] = dxsa.operand %[[INDEX_8]] {num_components = 0 : i32, type = 10 : i32} +// CHECK: dxsa.instruction "callc" %[[OPERAND_8]], %[[OPERAND_9]] +// CHECK: dxsa.instruction "break" +// CHECK: dxsa.instruction "default" +// CHECK: %[[INDEX_9:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_10:.*]] = dxsa.operand %[[INDEX_9]] {num_components = 4 : i32, one = 2 : i32, type = 0 : i32} +// CHECK: %[[INDEX_10:.*]] = dxsa.index.imm {imm = 2 : i32} +// CHECK: %[[OPERAND_11:.*]] = dxsa.operand %[[INDEX_10]] {num_components = 0 : i32, type = 10 : i32} +// CHECK: dxsa.instruction "callc" %[[OPERAND_10]], %[[OPERAND_11]] +// CHECK: dxsa.instruction "break" +// CHECK: %[[OPERAND_12:.*]] = dxsa.operand.imm {imm = dense<2> : vector<1xi32>} +// CHECK: dxsa.instruction "case" %[[OPERAND_12]] +// CHECK: dxsa.instruction "break" +// CHECK: dxsa.instruction "endswitch" +// CHECK: dxsa.add o<0, >, r<0, >, l(0x3F800000) +// CHECK: dxsa.instruction "ret" +// CHECK: %[[INDEX_11:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_13:.*]] = dxsa.operand %[[INDEX_11]] {num_components = 0 : i32, type = 10 : i32} +// CHECK: dxsa.instruction "label" %[[OPERAND_13]] +// CHECK: %[[INDEX_12:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_14:.*]] = dxsa.operand %[[INDEX_12]] {mask = 16 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[OPERAND_15:.*]] = dxsa.operand.imm {imm = dense<1084227584> : vector<1xi32>} +// CHECK: dxsa.instruction "mov" %[[OPERAND_14]], %[[OPERAND_15]] +// CHECK: dxsa.instruction "ret" +// CHECK: %[[INDEX_13:.*]] = dxsa.index.imm {imm = 1 : i32} +// CHECK: %[[OPERAND_16:.*]] = dxsa.operand %[[INDEX_13]] {num_components = 0 : i32, type = 10 : i32} +// CHECK: dxsa.instruction "label" %[[OPERAND_16]] +// CHECK: %[[INDEX_14:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_17:.*]] = dxsa.operand %[[INDEX_14]] {mask = 16 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_15:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_18:.*]] = dxsa.operand %[[INDEX_15]] {num_components = 4 : i32, one = 0 : i32, type = 1 : i32} +// CHECK: dxsa.instruction "mov" %[[OPERAND_17]], %[[OPERAND_18]] +// CHECK: dxsa.instruction "ret" +// CHECK: %[[INDEX_16:.*]] = dxsa.index.imm {imm = 2 : i32} +// CHECK: %[[OPERAND_19:.*]] = dxsa.operand %[[INDEX_16]] {num_components = 0 : i32, type = 10 : i32} +// CHECK: dxsa.instruction "label" %[[OPERAND_19]] +// CHECK: %[[INDEX_17:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_20:.*]] = dxsa.operand %[[INDEX_17]] {mask = 16 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[OPERAND_21:.*]] = dxsa.operand.imm {imm = dense<1077936128> : vector<1xi32>} +// CHECK: dxsa.instruction "mov" %[[OPERAND_20]], %[[OPERAND_21]] +// CHECK: dxsa.instruction "ret" + diff --git a/mlir/test/Target/DXSA/asm/cs3.test b/mlir/test/Target/DXSA/asm/cs3.test new file mode 100644 index 000000000000..6c2956b732f8 --- /dev/null +++ b/mlir/test/Target/DXSA/asm/cs3.test @@ -0,0 +1,68 @@ +// RUN: mlir-translate --import-dxsa-bin %S/inputs/cs3.shex | FileCheck %s +// NOTE: Assertions have been autogenerated by utils/generate-test-checks.py + + +// CHECK-LABEL: dxsa.dcl_global_flags +// CHECK: dxsa.dcl_constant_buffer , +// CHECK: dxsa.dcl_input vThreadIDInGroup<> +// CHECK: dxsa.dcl_temps 3 +// CHECK: dxsa.dcl_tgsm_raw g<0>, 1024 +// CHECK: dxsa.dcl_thread_group +// CHECK: dxsa.ishl r<0, >, vThreadIDInGroup<>, l(0x2) +// CHECK: %[[INDEX_0:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_0:.*]] = dxsa.operand %[[INDEX_0]] {mask = 48 : i32, num_components = 4 : i32, type = 31 : i32} +// CHECK: %[[INDEX_1:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_1:.*]] = dxsa.operand %[[INDEX_1]] {num_components = 4 : i32, one = 0 : i32, type = 0 : i32} +// CHECK: %[[INDEX_2:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[INDEX_3:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_2:.*]] = dxsa.operand %[[INDEX_2]], %[[INDEX_3]] {num_components = 4 : i32, swizzle = dense<[3, 2, 1, 0]> : vector<4xi32>, type = 8 : i32} +// CHECK: dxsa.instruction "store_raw" %[[OPERAND_0]], %[[OPERAND_1]], %[[OPERAND_2]] +// CHECK: dxsa.instruction "sync" +// CHECK: dxsa.instruction "sync" +// CHECK: dxsa.instruction "sync" +// CHECK: dxsa.instruction "sync" +// CHECK: dxsa.instruction "sync" +// CHECK: dxsa.instruction "sync" +// CHECK: dxsa.instruction "sync" +// CHECK: dxsa.instruction "sync" +// CHECK: dxsa.instruction "sync" +// CHECK: dxsa.instruction "sync" +// CHECK: %[[INDEX_4:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_3:.*]] = dxsa.operand %[[INDEX_4]] {mask = 80 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_5:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_4:.*]] = dxsa.operand %[[INDEX_5]] {num_components = 4 : i32, one = 0 : i32, type = 0 : i32} +// CHECK: %[[INDEX_6:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_5:.*]] = dxsa.operand %[[INDEX_6]] {num_components = 4 : i32, swizzle = dense<[2, 0, 3, 1]> : vector<4xi32>, type = 31 : i32} +// CHECK: dxsa.instruction "ld_raw" %[[OPERAND_3]], %[[OPERAND_4]], %[[OPERAND_5]] +// CHECK: %[[INDEX_7:.*]] = dxsa.index.imm {imm = 2 : i32} +// CHECK: %[[OPERAND_6:.*]] = dxsa.operand %[[INDEX_7]] {mask = 16 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_8:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_7:.*]] = dxsa.operand %[[INDEX_8]] {num_components = 0 : i32, type = 31 : i32} +// CHECK: %[[INDEX_9:.*]] = dxsa.index.imm {imm = 1 : i32} +// CHECK: %[[OPERAND_8:.*]] = dxsa.operand %[[INDEX_9]] {num_components = 4 : i32, swizzle = dense<[0, 1, 0, 0]> : vector<4xi32>, type = 0 : i32} +// CHECK: %[[OPERAND_9:.*]] = dxsa.operand {num_components = 4 : i32, one = 0 : i32, type = 34 : i32} +// CHECK: dxsa.instruction "imm_atomic_iadd" %[[OPERAND_6]], %[[OPERAND_7]], %[[OPERAND_8]], %[[OPERAND_9]] +// CHECK: %[[INDEX_10:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_10:.*]] = dxsa.operand %[[INDEX_10]] {num_components = 0 : i32, type = 31 : i32} +// CHECK: %[[INDEX_11:.*]] = dxsa.index.imm {imm = 1 : i32} +// CHECK: %[[OPERAND_11:.*]] = dxsa.operand %[[INDEX_11]] {num_components = 4 : i32, swizzle = dense<[0, 1, 0, 0]> : vector<4xi32>, type = 0 : i32} +// CHECK: %[[OPERAND_12:.*]] = dxsa.operand {num_components = 4 : i32, one = 0 : i32, type = 34 : i32} +// CHECK: dxsa.instruction "atomic_or" %[[OPERAND_10]], %[[OPERAND_11]], %[[OPERAND_12]] +// CHECK: %[[INDEX_12:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_13:.*]] = dxsa.operand %[[INDEX_12]] {num_components = 0 : i32, type = 31 : i32} +// CHECK: %[[INDEX_13:.*]] = dxsa.index.imm {imm = 1 : i32} +// CHECK: %[[OPERAND_14:.*]] = dxsa.operand %[[INDEX_13]] {num_components = 4 : i32, swizzle = dense<[0, 1, 0, 0]> : vector<4xi32>, type = 0 : i32} +// CHECK: %[[OPERAND_15:.*]] = dxsa.operand {num_components = 4 : i32, one = 1 : i32, type = 34 : i32} +// CHECK: %[[OPERAND_16:.*]] = dxsa.operand {num_components = 4 : i32, one = 0 : i32, type = 34 : i32} +// CHECK: dxsa.instruction "atomic_cmp_store" %[[OPERAND_13]], %[[OPERAND_14]], %[[OPERAND_15]], %[[OPERAND_16]] +// CHECK: %[[INDEX_14:.*]] = dxsa.index.imm {imm = 1 : i32} +// CHECK: %[[OPERAND_17:.*]] = dxsa.operand %[[INDEX_14]] {mask = 16 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_15:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_18:.*]] = dxsa.operand %[[INDEX_15]] {num_components = 0 : i32, type = 31 : i32} +// CHECK: %[[INDEX_16:.*]] = dxsa.index.imm {imm = 1 : i32} +// CHECK: %[[OPERAND_19:.*]] = dxsa.operand %[[INDEX_16]] {num_components = 4 : i32, swizzle = dense<[0, 1, 0, 0]> : vector<4xi32>, type = 0 : i32} +// CHECK: %[[OPERAND_20:.*]] = dxsa.operand {num_components = 4 : i32, one = 1 : i32, type = 34 : i32} +// CHECK: %[[OPERAND_21:.*]] = dxsa.operand {num_components = 4 : i32, one = 0 : i32, type = 34 : i32} +// CHECK: dxsa.instruction "imm_atomic_cmp_exch" %[[OPERAND_17]], %[[OPERAND_18]], %[[OPERAND_19]], %[[OPERAND_20]], %[[OPERAND_21]] +// CHECK: dxsa.instruction "ret" + diff --git a/mlir/test/Target/DXSA/asm/cyclecounter.test b/mlir/test/Target/DXSA/asm/cyclecounter.test new file mode 100644 index 000000000000..f5d8ffdb90bb --- /dev/null +++ b/mlir/test/Target/DXSA/asm/cyclecounter.test @@ -0,0 +1,21 @@ +// RUN: mlir-translate --import-dxsa-bin %S/inputs/cyclecounter.shex | FileCheck %s +// NOTE: Assertions have been autogenerated by utils/generate-test-checks.py + + +// CHECK-LABEL: dxsa.dcl_temps 1 +// CHECK: dxsa.dcl_output o<0> +// CHECK: dxsa.dcl_input cycleCounter<> +// CHECK: %[[INDEX_0:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_0:.*]] = dxsa.operand %[[INDEX_0]] {mask = 240 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[OPERAND_1:.*]] = dxsa.operand.imm {imm = dense<0> : vector<1xi32>} +// CHECK: dxsa.instruction "mov" %[[OPERAND_0]], %[[OPERAND_1]] +// CHECK: %[[INDEX_1:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_2:.*]] = dxsa.operand %[[INDEX_1]] {mask = 64 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[OPERAND_3:.*]] = dxsa.operand {num_components = 4 : i32, one = 0 : i32, type = 40 : i32} +// CHECK: dxsa.instruction "mov" %[[OPERAND_2]], %[[OPERAND_3]] +// CHECK: %[[INDEX_2:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_4:.*]] = dxsa.operand %[[INDEX_2]] {mask = 240 : i32, num_components = 4 : i32, type = 2 : i32} +// CHECK: %[[INDEX_3:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_5:.*]] = dxsa.operand %[[INDEX_3]] {num_components = 4 : i32, swizzle = dense<[0, 1, 2, 3]> : vector<4xi32>, type = 0 : i32} +// CHECK: dxsa.instruction "mov" %[[OPERAND_4]], %[[OPERAND_5]] + diff --git a/mlir/test/Target/DXSA/asm/hs3.test b/mlir/test/Target/DXSA/asm/hs3.test new file mode 100644 index 000000000000..785a22cc1244 --- /dev/null +++ b/mlir/test/Target/DXSA/asm/hs3.test @@ -0,0 +1,187 @@ +// RUN: mlir-translate --import-dxsa-bin %S/inputs/hs3.shex | FileCheck %s +// NOTE: Assertions have been autogenerated by utils/generate-test-checks.py + + +// CHECK-LABEL: dxsa.instruction "hs_decls" +// CHECK: dxsa.dcl_input_control_point_count 4 +// CHECK: dxsa.dcl_output_control_point_count 32 +// CHECK: dxsa.dcl_tessellator_domain domain_quad +// CHECK: dxsa.dcl_tessellator_partitioning partitioning_fractional_odd +// CHECK: dxsa.dcl_tessellator_output_primitive output_triangle_cw +// CHECK: dxsa.dcl_hs_max_tessfactor 6.400000e+01 +// CHECK: dxsa.instruction "hs_control_point_phase" +// CHECK: dxsa.dcl_input v<[4, 0]> +// CHECK: dxsa.dcl_input v<[4, 1], > +// CHECK: dxsa.dcl_input v<[4, 2], > +// CHECK: dxsa.dcl_input vOutputControlPointID +// CHECK: dxsa.dcl_input vPrim +// CHECK: dxsa.dcl_output o<0> +// CHECK: dxsa.dcl_output o<1, > +// CHECK: dxsa.dcl_output o<2, > +// CHECK: dxsa.dcl_temps 1 +// CHECK: %[[OPERAND_0:.*]] = dxsa.operand {num_components = 0 : i32, type = 13 : i32} +// CHECK: %[[INDEX_0:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_1:.*]] = dxsa.operand %[[INDEX_0]] {mask = 16 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[OPERAND_2:.*]] = dxsa.operand {num_components = 1 : i32, type = 22 : i32} +// CHECK: %[[OPERAND_3:.*]] = dxsa.operand.imm {imm = dense<4> : vector<1xi32>} +// CHECK: dxsa.instruction "udiv" %[[OPERAND_0]], %[[OPERAND_1]], %[[OPERAND_2]], %[[OPERAND_3]] +// CHECK: %[[INDEX_1:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_4:.*]] = dxsa.operand %[[INDEX_1]] {mask = 240 : i32, num_components = 4 : i32, type = 2 : i32} +// CHECK: %[[INDEX_2:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_5:.*]] = dxsa.operand %[[INDEX_2]] {num_components = 4 : i32, one = 0 : i32, type = 0 : i32} +// CHECK: %[[INDEX_3:.*]] = dxsa.index.rel %[[OPERAND_5]] +// CHECK: %[[INDEX_4:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_6:.*]] = dxsa.operand %[[INDEX_3]], %[[INDEX_4]] {num_components = 4 : i32, swizzle = dense<[0, 1, 2, 3]> : vector<4xi32>, type = 1 : i32} +// CHECK: dxsa.instruction "mov" %[[OPERAND_4]], %[[OPERAND_6]] +// CHECK: %[[INDEX_5:.*]] = dxsa.index.imm {imm = 1 : i32} +// CHECK: %[[OPERAND_7:.*]] = dxsa.operand %[[INDEX_5]] {mask = 48 : i32, num_components = 4 : i32, type = 2 : i32} +// CHECK: %[[INDEX_6:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_8:.*]] = dxsa.operand %[[INDEX_6]] {num_components = 4 : i32, one = 0 : i32, type = 0 : i32} +// CHECK: %[[INDEX_7:.*]] = dxsa.index.rel %[[OPERAND_8]] +// CHECK: %[[INDEX_8:.*]] = dxsa.index.imm {imm = 1 : i32} +// CHECK: %[[OPERAND_9:.*]] = dxsa.operand %[[INDEX_7]], %[[INDEX_8]] {num_components = 4 : i32, swizzle = dense<[0, 1, 0, 0]> : vector<4xi32>, type = 1 : i32} +// CHECK: dxsa.instruction "mov" %[[OPERAND_7]], %[[OPERAND_9]] +// CHECK: %[[INDEX_9:.*]] = dxsa.index.imm {imm = 2 : i32} +// CHECK: %[[OPERAND_10:.*]] = dxsa.operand %[[INDEX_9]] {mask = 112 : i32, num_components = 4 : i32, type = 2 : i32} +// CHECK: %[[INDEX_10:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_11:.*]] = dxsa.operand %[[INDEX_10]] {num_components = 4 : i32, one = 0 : i32, type = 0 : i32} +// CHECK: %[[INDEX_11:.*]] = dxsa.index.rel %[[OPERAND_11]] +// CHECK: %[[INDEX_12:.*]] = dxsa.index.imm {imm = 2 : i32} +// CHECK: %[[OPERAND_12:.*]] = dxsa.operand %[[INDEX_11]], %[[INDEX_12]] {num_components = 4 : i32, swizzle = dense<[0, 1, 2, 0]> : vector<4xi32>, type = 1 : i32} +// CHECK: dxsa.instruction "mov" %[[OPERAND_10]], %[[OPERAND_12]] +// CHECK: dxsa.instruction "hs_fork_phase" +// CHECK: dxsa.dcl_input vicp<[4, 0]> +// CHECK: dxsa.dcl_input vicp<[4, 1], > +// CHECK: dxsa.dcl_input vicp<[4, 2], > +// CHECK: dxsa.dcl_input vocp<[32, 0]> +// CHECK: dxsa.dcl_input vocp<[32, 1], > +// CHECK: dxsa.dcl_input vocp<[32, 2], > +// CHECK: dxsa.dcl_hs_fork_phase_instance_count 4 +// CHECK: dxsa.dcl_input vForkInstanceID +// CHECK: dxsa.dcl_input vPrim +// CHECK: dxsa.dcl_index_range o<0>, 4 +// CHECK: dxsa.dcl_temps 1 +// CHECK: dxsa.dcl_indexable_temp x<0>[4], 1 +// CHECK: dxsa.dcl_output_siv o<0, >, +// CHECK: dxsa.dcl_output_siv o<1, >, +// CHECK: dxsa.dcl_output_siv o<2, >, +// CHECK: dxsa.dcl_output_siv o<3, >, +// CHECK: %[[INDEX_13:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[INDEX_14:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_13:.*]] = dxsa.operand %[[INDEX_13]], %[[INDEX_14]] {mask = 16 : i32, num_components = 4 : i32, type = 3 : i32} +// CHECK: %[[OPERAND_14:.*]] = dxsa.operand.imm {imm = dense<1073741824> : vector<1xi32>} +// CHECK: dxsa.instruction "mov" %[[OPERAND_13]], %[[OPERAND_14]] +// CHECK: %[[INDEX_15:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[INDEX_16:.*]] = dxsa.index.imm {imm = 1 : i32} +// CHECK: %[[OPERAND_15:.*]] = dxsa.operand %[[INDEX_15]], %[[INDEX_16]] {mask = 16 : i32, num_components = 4 : i32, type = 3 : i32} +// CHECK: %[[OPERAND_16:.*]] = dxsa.operand.imm {imm = dense<1082130432> : vector<1xi32>} +// CHECK: dxsa.instruction "mov" %[[OPERAND_15]], %[[OPERAND_16]] +// CHECK: %[[INDEX_17:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[INDEX_18:.*]] = dxsa.index.imm {imm = 2 : i32} +// CHECK: %[[OPERAND_17:.*]] = dxsa.operand %[[INDEX_17]], %[[INDEX_18]] {mask = 16 : i32, num_components = 4 : i32, type = 3 : i32} +// CHECK: %[[OPERAND_18:.*]] = dxsa.operand.imm {imm = dense<1097859072> : vector<1xi32>} +// CHECK: dxsa.instruction "mov" %[[OPERAND_17]], %[[OPERAND_18]] +// CHECK: %[[INDEX_19:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[INDEX_20:.*]] = dxsa.index.imm {imm = 3 : i32} +// CHECK: %[[OPERAND_19:.*]] = dxsa.operand %[[INDEX_19]], %[[INDEX_20]] {mask = 16 : i32, num_components = 4 : i32, type = 3 : i32} +// CHECK: %[[OPERAND_20:.*]] = dxsa.operand.imm {imm = dense<1086324736> : vector<1xi32>} +// CHECK: dxsa.instruction "mov" %[[OPERAND_19]], %[[OPERAND_20]] +// CHECK: %[[INDEX_21:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_21:.*]] = dxsa.operand %[[INDEX_21]] {mask = 16 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[OPERAND_22:.*]] = dxsa.operand {num_components = 0 : i32, type = 23 : i32} +// CHECK: dxsa.instruction "mov" %[[OPERAND_21]], %[[OPERAND_22]] +// CHECK: %[[INDEX_22:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_23:.*]] = dxsa.operand %[[INDEX_22]] {num_components = 4 : i32, one = 0 : i32, type = 0 : i32} +// CHECK: %[[INDEX_23:.*]] = dxsa.index.rel %[[OPERAND_23]] +// CHECK: %[[OPERAND_24:.*]] = dxsa.operand %[[INDEX_23]] {mask = 16 : i32, num_components = 4 : i32, type = 2 : i32} +// CHECK: %[[INDEX_24:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[INDEX_25:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_25:.*]] = dxsa.operand %[[INDEX_25]] {num_components = 4 : i32, one = 0 : i32, type = 0 : i32} +// CHECK: %[[INDEX_26:.*]] = dxsa.index.rel %[[OPERAND_25]] +// CHECK: %[[OPERAND_26:.*]] = dxsa.operand %[[INDEX_24]], %[[INDEX_26]] {num_components = 4 : i32, one = 0 : i32, type = 3 : i32} +// CHECK: dxsa.instruction "mov" %[[OPERAND_24]], %[[OPERAND_26]] +// CHECK: dxsa.instruction "hs_fork_phase" +// CHECK: dxsa.dcl_input vicp<[4, 0]> +// CHECK: dxsa.dcl_input vicp<[4, 1], > +// CHECK: dxsa.dcl_input vicp<[4, 2], > +// CHECK: dxsa.dcl_input vocp<[32, 0]> +// CHECK: dxsa.dcl_input vocp<[32, 1], > +// CHECK: dxsa.dcl_input vocp<[32, 2], > +// CHECK: dxsa.dcl_hs_fork_phase_instance_count 4 +// CHECK: dxsa.dcl_input vForkInstanceID +// CHECK: dxsa.dcl_input vPrim +// CHECK: dxsa.dcl_index_range o<0>, 4 +// CHECK: dxsa.dcl_temps 1 +// CHECK: dxsa.dcl_indexable_temp x<0>[4], 1 +// CHECK: dxsa.dcl_output o<0, > +// CHECK: dxsa.dcl_output o<1, > +// CHECK: dxsa.dcl_output o<2, > +// CHECK: dxsa.dcl_output o<3, > +// CHECK: %[[INDEX_27:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[INDEX_28:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_27:.*]] = dxsa.operand %[[INDEX_27]], %[[INDEX_28]] {mask = 16 : i32, num_components = 4 : i32, type = 3 : i32} +// CHECK: %[[OPERAND_28:.*]] = dxsa.operand.imm {imm = dense<1094713344> : vector<1xi32>} +// CHECK: dxsa.instruction "mov" %[[OPERAND_27]], %[[OPERAND_28]] +// CHECK: %[[INDEX_29:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[INDEX_30:.*]] = dxsa.index.imm {imm = 1 : i32} +// CHECK: %[[OPERAND_29:.*]] = dxsa.operand %[[INDEX_29]], %[[INDEX_30]] {mask = 16 : i32, num_components = 4 : i32, type = 3 : i32} +// CHECK: %[[OPERAND_30:.*]] = dxsa.operand.imm {imm = dense<1107296256> : vector<1xi32>} +// CHECK: dxsa.instruction "mov" %[[OPERAND_29]], %[[OPERAND_30]] +// CHECK: %[[INDEX_31:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[INDEX_32:.*]] = dxsa.index.imm {imm = 2 : i32} +// CHECK: %[[OPERAND_31:.*]] = dxsa.operand %[[INDEX_31]], %[[INDEX_32]] {mask = 16 : i32, num_components = 4 : i32, type = 3 : i32} +// CHECK: %[[OPERAND_32:.*]] = dxsa.operand.imm {imm = dense<1097859072> : vector<1xi32>} +// CHECK: dxsa.instruction "mov" %[[OPERAND_31]], %[[OPERAND_32]] +// CHECK: %[[INDEX_33:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[INDEX_34:.*]] = dxsa.index.imm {imm = 3 : i32} +// CHECK: %[[OPERAND_33:.*]] = dxsa.operand %[[INDEX_33]], %[[INDEX_34]] {mask = 16 : i32, num_components = 4 : i32, type = 3 : i32} +// CHECK: %[[OPERAND_34:.*]] = dxsa.operand.imm {imm = dense<1084227584> : vector<1xi32>} +// CHECK: dxsa.instruction "mov" %[[OPERAND_33]], %[[OPERAND_34]] +// CHECK: %[[INDEX_35:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_35:.*]] = dxsa.operand %[[INDEX_35]] {mask = 16 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[OPERAND_36:.*]] = dxsa.operand {num_components = 0 : i32, type = 23 : i32} +// CHECK: dxsa.instruction "mov" %[[OPERAND_35]], %[[OPERAND_36]] +// CHECK: %[[INDEX_36:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_37:.*]] = dxsa.operand %[[INDEX_36]] {num_components = 4 : i32, one = 0 : i32, type = 0 : i32} +// CHECK: %[[INDEX_37:.*]] = dxsa.index.rel %[[OPERAND_37]] +// CHECK: %[[OPERAND_38:.*]] = dxsa.operand %[[INDEX_37]] {mask = 32 : i32, num_components = 4 : i32, type = 2 : i32} +// CHECK: %[[INDEX_38:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[INDEX_39:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_39:.*]] = dxsa.operand %[[INDEX_39]] {num_components = 4 : i32, one = 0 : i32, type = 0 : i32} +// CHECK: %[[INDEX_40:.*]] = dxsa.index.rel %[[OPERAND_39]] +// CHECK: %[[OPERAND_40:.*]] = dxsa.operand %[[INDEX_38]], %[[INDEX_40]] {num_components = 4 : i32, one = 0 : i32, type = 3 : i32} +// CHECK: dxsa.instruction "mov" %[[OPERAND_38]], %[[OPERAND_40]] +// CHECK: dxsa.instruction "hs_join_phase" +// CHECK: dxsa.dcl_input vicp<[4, 0]> +// CHECK: dxsa.dcl_input vicp<[4, 1], > +// CHECK: dxsa.dcl_input vicp<[4, 2], > +// CHECK: dxsa.dcl_input vocp<[32, 0]> +// CHECK: dxsa.dcl_input vocp<[32, 1], > +// CHECK: dxsa.dcl_input vocp<[32, 2], > +// CHECK: dxsa.dcl_input vpc<0, > +// CHECK: dxsa.dcl_input vpc<1, > +// CHECK: dxsa.dcl_input vpc<2, > +// CHECK: dxsa.dcl_input vpc<3, > +// CHECK: dxsa.dcl_index_range vpc<0>, 4 +// CHECK: dxsa.dcl_output_siv o<4, >, +// CHECK: dxsa.dcl_output_siv o<5, >, +// CHECK: dxsa.dcl_output o<4, > +// CHECK: dxsa.dcl_output o<5, > +// CHECK: dxsa.dcl_input vPrim +// CHECK: %[[INDEX_41:.*]] = dxsa.index.imm {imm = 4 : i32} +// CHECK: %[[OPERAND_41:.*]] = dxsa.operand %[[INDEX_41]] {mask = 16 : i32, num_components = 4 : i32, type = 2 : i32} +// CHECK: %[[OPERAND_42:.*]] = dxsa.operand.imm {imm = dense<1094713344> : vector<1xi32>} +// CHECK: dxsa.instruction "mov" %[[OPERAND_41]], %[[OPERAND_42]] +// CHECK: %[[INDEX_42:.*]] = dxsa.index.imm {imm = 5 : i32} +// CHECK: %[[OPERAND_43:.*]] = dxsa.operand %[[INDEX_42]] {mask = 16 : i32, num_components = 4 : i32, type = 2 : i32} +// CHECK: %[[OPERAND_44:.*]] = dxsa.operand.imm {imm = dense<1086324736> : vector<1xi32>} +// CHECK: dxsa.instruction "mov" %[[OPERAND_43]], %[[OPERAND_44]] +// CHECK: %[[INDEX_43:.*]] = dxsa.index.imm {imm = 4 : i32} +// CHECK: %[[OPERAND_45:.*]] = dxsa.operand %[[INDEX_43]] {mask = 32 : i32, num_components = 4 : i32, type = 2 : i32} +// CHECK: %[[OPERAND_46:.*]] = dxsa.operand.imm {imm = dense<0> : vector<1xi32>} +// CHECK: dxsa.instruction "mov" %[[OPERAND_45]], %[[OPERAND_46]] +// CHECK: %[[INDEX_44:.*]] = dxsa.index.imm {imm = 5 : i32} +// CHECK: %[[OPERAND_47:.*]] = dxsa.operand %[[INDEX_44]] {mask = 32 : i32, num_components = 4 : i32, type = 2 : i32} +// CHECK: %[[OPERAND_48:.*]] = dxsa.operand.imm {imm = dense<0> : vector<1xi32>} +// CHECK: dxsa.instruction "mov" %[[OPERAND_47]], %[[OPERAND_48]] + diff --git a/mlir/test/Target/DXSA/asm/indexabletemp4.test b/mlir/test/Target/DXSA/asm/indexabletemp4.test new file mode 100644 index 000000000000..60bb8372393a --- /dev/null +++ b/mlir/test/Target/DXSA/asm/indexabletemp4.test @@ -0,0 +1,56 @@ +// RUN: mlir-translate --import-dxsa-bin %S/inputs/indexabletemp4.shex | FileCheck %s +// NOTE: Assertions have been autogenerated by utils/generate-test-checks.py + + +// CHECK-LABEL: dxsa.dcl_global_flags +// CHECK: dxsa.dcl_constant_buffer , +// CHECK: dxsa.dcl_input_ps constant v<1, > +// CHECK: dxsa.dcl_input_ps constant v<1, > +// CHECK: dxsa.dcl_output o<0, > +// CHECK: dxsa.dcl_temps 1 +// CHECK: dxsa.dcl_indexable_temp x<0>[4], 2 +// CHECK: %[[INDEX_0:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_0:.*]] = dxsa.operand %[[INDEX_0]] {mask = 16 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_1:.*]] = dxsa.index.imm {imm = 1 : i32} +// CHECK: %[[OPERAND_1:.*]] = dxsa.operand %[[INDEX_1]] {num_components = 4 : i32, one = 0 : i32, type = 1 : i32} +// CHECK: dxsa.instruction "mov" %[[OPERAND_0]], %[[OPERAND_1]] +// CHECK: %[[INDEX_2:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[INDEX_3:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_2:.*]] = dxsa.operand %[[INDEX_2]], %[[INDEX_3]] {mask = 16 : i32, num_components = 4 : i32, type = 3 : i32} +// CHECK: %[[INDEX_4:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[INDEX_5:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_3:.*]] = dxsa.operand %[[INDEX_5]] {num_components = 4 : i32, one = 0 : i32, type = 0 : i32} +// CHECK: %[[INDEX_6:.*]] = dxsa.index.rel %[[OPERAND_3]] +// CHECK: %[[OPERAND_4:.*]] = dxsa.operand %[[INDEX_4]], %[[INDEX_6]] {num_components = 4 : i32, one = 0 : i32, type = 8 : i32} +// CHECK: dxsa.instruction "mov" %[[OPERAND_2]], %[[OPERAND_4]] +// CHECK: %[[INDEX_7:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[INDEX_8:.*]] = dxsa.index.imm {imm = 1 : i32} +// CHECK: %[[OPERAND_5:.*]] = dxsa.operand %[[INDEX_7]], %[[INDEX_8]] {mask = 16 : i32, num_components = 4 : i32, type = 3 : i32} +// CHECK: %[[INDEX_9:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[INDEX_10:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_6:.*]] = dxsa.operand %[[INDEX_10]] {num_components = 4 : i32, one = 0 : i32, type = 0 : i32} +// CHECK: %[[INDEX_11:.*]] = dxsa.index.rel.imm %[[OPERAND_6]] {imm = 4 : i32, op = "add"} +// CHECK: %[[OPERAND_7:.*]] = dxsa.operand %[[INDEX_9]], %[[INDEX_11]] {num_components = 4 : i32, one = 0 : i32, type = 8 : i32} +// CHECK: dxsa.instruction "mov" %[[OPERAND_5]], %[[OPERAND_7]] +// CHECK: %[[INDEX_12:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_8:.*]] = dxsa.operand %[[INDEX_12]] {mask = 16 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_13:.*]] = dxsa.index.imm {imm = 1 : i32} +// CHECK: %[[OPERAND_9:.*]] = dxsa.operand %[[INDEX_13]] {num_components = 4 : i32, one = 1 : i32, type = 1 : i32} +// CHECK: dxsa.instruction "mov" %[[OPERAND_8]], %[[OPERAND_9]] +// CHECK: %[[INDEX_14:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[INDEX_15:.*]] = dxsa.index.imm {imm = 1 : i32} +// CHECK: %[[OPERAND_10:.*]] = dxsa.operand %[[INDEX_14]], %[[INDEX_15]] {mask = 32 : i32, num_components = 4 : i32, type = 3 : i32} +// CHECK: %[[INDEX_16:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_11:.*]] = dxsa.operand %[[INDEX_16]] {num_components = 4 : i32, one = 0 : i32, type = 0 : i32} +// CHECK: dxsa.instruction "mov" %[[OPERAND_10]], %[[OPERAND_11]] +// CHECK: %[[INDEX_17:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_12:.*]] = dxsa.operand %[[INDEX_17]] {mask = 16 : i32, num_components = 4 : i32, type = 2 : i32} +// CHECK: %[[INDEX_18:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[INDEX_19:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[INDEX_20:.*]] = dxsa.index.imm {imm = 1 : i32} +// CHECK: %[[OPERAND_13:.*]] = dxsa.operand %[[INDEX_19]], %[[INDEX_20]] {num_components = 4 : i32, one = 1 : i32, type = 3 : i32} +// CHECK: %[[INDEX_21:.*]] = dxsa.index.rel.imm %[[OPERAND_13]] {imm = 77 : i32, op = "add"} +// CHECK: %[[OPERAND_14:.*]] = dxsa.operand %[[INDEX_18]], %[[INDEX_21]] {num_components = 4 : i32, one = 0 : i32, type = 3 : i32} +// CHECK: dxsa.instruction "mov" %[[OPERAND_12]], %[[OPERAND_14]] +// CHECK: dxsa.instruction "ret" + diff --git a/mlir/test/Target/DXSA/asm/indexabletemp6.test b/mlir/test/Target/DXSA/asm/indexabletemp6.test new file mode 100644 index 000000000000..3b3eea3ef872 --- /dev/null +++ b/mlir/test/Target/DXSA/asm/indexabletemp6.test @@ -0,0 +1,65 @@ +// RUN: mlir-translate --import-dxsa-bin %S/inputs/indexabletemp6.shex | FileCheck %s +// NOTE: Assertions have been autogenerated by utils/generate-test-checks.py + + +// CHECK-LABEL: dxsa.dcl_global_flags +// CHECK: dxsa.dcl_constant_buffer , +// CHECK: dxsa.dcl_input_ps constant v<1, > +// CHECK: dxsa.dcl_input_ps constant v<1, > +// CHECK: dxsa.dcl_output o<0, min16f, > +// CHECK: dxsa.dcl_temps 1 +// CHECK: dxsa.dcl_indexable_temp x<0>[4] +// CHECK: %[[INDEX_0:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_0:.*]] = dxsa.operand %[[INDEX_0]] {mask = 16 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_1:.*]] = dxsa.index.imm {imm = 1 : i32} +// CHECK: %[[OPERAND_1:.*]] = dxsa.operand %[[INDEX_1]] {num_components = 4 : i32, one = 0 : i32, type = 1 : i32} +// CHECK: dxsa.instruction "mov" %[[OPERAND_0]], %[[OPERAND_1]] +// CHECK: %[[INDEX_2:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[INDEX_3:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_2:.*]] = dxsa.operand %[[INDEX_2]], %[[INDEX_3]] {mask = 16 : i32, num_components = 4 : i32, type = 3 : i32} +// CHECK: %[[INDEX_4:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[INDEX_5:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_3:.*]] = dxsa.operand %[[INDEX_5]] {num_components = 4 : i32, one = 0 : i32, type = 0 : i32} +// CHECK: %[[INDEX_6:.*]] = dxsa.index.rel.imm %[[OPERAND_3]] {imm = 4 : i32, op = "add"} +// CHECK: %[[OPERAND_4:.*]] = dxsa.operand %[[INDEX_4]], %[[INDEX_6]] {num_components = 4 : i32, one = 0 : i32, type = 8 : i32} +// CHECK: dxsa.instruction "mov" %[[OPERAND_2]], %[[OPERAND_4]] +// CHECK: %[[INDEX_7:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_5:.*]] = dxsa.operand %[[INDEX_7]] {mask = 32 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_8:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[INDEX_9:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_6:.*]] = dxsa.operand %[[INDEX_8]], %[[INDEX_9]] {num_components = 4 : i32, one = 0 : i32, type = 3 : i32} +// CHECK: dxsa.instruction "mov" %[[OPERAND_5]], %[[OPERAND_6]] +// CHECK: %[[INDEX_10:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[INDEX_11:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_7:.*]] = dxsa.operand %[[INDEX_10]], %[[INDEX_11]] {mask = 16 : i32, min_precision = 1 : i32, num_components = 4 : i32, type = 3 : i32} +// CHECK: %[[INDEX_12:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[INDEX_13:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_8:.*]] = dxsa.operand %[[INDEX_13]] {num_components = 4 : i32, one = 0 : i32, type = 0 : i32} +// CHECK: %[[INDEX_14:.*]] = dxsa.index.rel %[[OPERAND_8]] +// CHECK: %[[OPERAND_9:.*]] = dxsa.operand %[[INDEX_12]], %[[INDEX_14]] {min_precision = 1 : i32, num_components = 4 : i32, one = 0 : i32, type = 8 : i32} +// CHECK: dxsa.instruction "mov" %[[OPERAND_7]], %[[OPERAND_9]] +// CHECK: %[[INDEX_15:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[INDEX_16:.*]] = dxsa.index.imm {imm = 1 : i32} +// CHECK: %[[OPERAND_10:.*]] = dxsa.operand %[[INDEX_15]], %[[INDEX_16]] {mask = 16 : i32, min_precision = 1 : i32, num_components = 4 : i32, type = 3 : i32} +// CHECK: %[[INDEX_17:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[INDEX_18:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_11:.*]] = dxsa.operand %[[INDEX_18]] {num_components = 4 : i32, one = 0 : i32, type = 0 : i32} +// CHECK: %[[INDEX_19:.*]] = dxsa.index.rel.imm %[[OPERAND_11]] {imm = 4 : i32, op = "add"} +// CHECK: %[[OPERAND_12:.*]] = dxsa.operand %[[INDEX_17]], %[[INDEX_19]] {min_precision = 1 : i32, num_components = 4 : i32, one = 0 : i32, type = 8 : i32} +// CHECK: dxsa.instruction "mov" %[[OPERAND_10]], %[[OPERAND_12]] +// CHECK: %[[INDEX_20:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_13:.*]] = dxsa.operand %[[INDEX_20]] {mask = 16 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_21:.*]] = dxsa.index.imm {imm = 1 : i32} +// CHECK: %[[OPERAND_14:.*]] = dxsa.operand %[[INDEX_21]] {num_components = 4 : i32, one = 1 : i32, type = 1 : i32} +// CHECK: dxsa.instruction "mov" %[[OPERAND_13]], %[[OPERAND_14]] +// CHECK: dxsa.add x<[0, r<0, >], min16f, >, x<[0, r<0, >], min16f, >, r<0, min16f, > +// CHECK: %[[INDEX_22:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_15:.*]] = dxsa.operand %[[INDEX_22]] {mask = 16 : i32, min_precision = 1 : i32, num_components = 4 : i32, type = 2 : i32} +// CHECK: %[[INDEX_23:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[INDEX_24:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_16:.*]] = dxsa.operand %[[INDEX_24]] {num_components = 4 : i32, one = 0 : i32, type = 0 : i32} +// CHECK: %[[INDEX_25:.*]] = dxsa.index.rel %[[OPERAND_16]] +// CHECK: %[[OPERAND_17:.*]] = dxsa.operand %[[INDEX_23]], %[[INDEX_25]] {min_precision = 1 : i32, num_components = 4 : i32, one = 0 : i32, type = 3 : i32} +// CHECK: dxsa.instruction "mov" %[[OPERAND_15]], %[[OPERAND_17]] +// CHECK: dxsa.instruction "ret" + diff --git a/mlir/test/Target/DXSA/asm/inputs/call2.shex b/mlir/test/Target/DXSA/asm/inputs/call2.shex new file mode 100644 index 000000000000..e0fe124cfbac Binary files /dev/null and b/mlir/test/Target/DXSA/asm/inputs/call2.shex differ diff --git a/mlir/test/Target/DXSA/asm/inputs/cs3.shex b/mlir/test/Target/DXSA/asm/inputs/cs3.shex new file mode 100644 index 000000000000..979c550dcb06 Binary files /dev/null and b/mlir/test/Target/DXSA/asm/inputs/cs3.shex differ diff --git a/mlir/test/Target/DXSA/asm/inputs/cyclecounter.shex b/mlir/test/Target/DXSA/asm/inputs/cyclecounter.shex new file mode 100644 index 000000000000..3f883fb28ba4 Binary files /dev/null and b/mlir/test/Target/DXSA/asm/inputs/cyclecounter.shex differ diff --git a/mlir/test/Target/DXSA/asm/inputs/hs3.shex b/mlir/test/Target/DXSA/asm/inputs/hs3.shex new file mode 100644 index 000000000000..f817cea934d4 Binary files /dev/null and b/mlir/test/Target/DXSA/asm/inputs/hs3.shex differ diff --git a/mlir/test/Target/DXSA/asm/inputs/indexabletemp4.shex b/mlir/test/Target/DXSA/asm/inputs/indexabletemp4.shex new file mode 100644 index 000000000000..a41f3f572dfe Binary files /dev/null and b/mlir/test/Target/DXSA/asm/inputs/indexabletemp4.shex differ diff --git a/mlir/test/Target/DXSA/asm/inputs/indexabletemp6.shex b/mlir/test/Target/DXSA/asm/inputs/indexabletemp6.shex new file mode 100644 index 000000000000..5dd2516fa9fd Binary files /dev/null and b/mlir/test/Target/DXSA/asm/inputs/indexabletemp6.shex differ diff --git a/mlir/test/Target/DXSA/hlsl/abs1.test b/mlir/test/Target/DXSA/hlsl/abs1.test new file mode 100644 index 000000000000..ccb96e5efe5e --- /dev/null +++ b/mlir/test/Target/DXSA/hlsl/abs1.test @@ -0,0 +1,14 @@ +// RUN: mlir-translate --import-dxsa-bin %S/inputs/abs1.shex | FileCheck %s +// NOTE: Assertions have been autogenerated by utils/generate-test-checks.py + + +// CHECK-LABEL: dxsa.dcl_global_flags +// CHECK: dxsa.dcl_input_ps linear v<0, > +// CHECK: dxsa.dcl_output o<0> +// CHECK: %[[INDEX_0:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_0:.*]] = dxsa.operand %[[INDEX_0]] {mask = 240 : i32, num_components = 4 : i32, type = 2 : i32} +// CHECK: %[[INDEX_1:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_1:.*]] = dxsa.operand %[[INDEX_1]] {modifier = 2 : i32, num_components = 4 : i32, swizzle = dense<[1, 0, 0, 0]> : vector<4xi32>, type = 1 : i32} +// CHECK: dxsa.instruction "mov" %[[OPERAND_0]], %[[OPERAND_1]] +// CHECK: dxsa.instruction "ret" + diff --git a/mlir/test/Target/DXSA/hlsl/abs2.test b/mlir/test/Target/DXSA/hlsl/abs2.test new file mode 100644 index 000000000000..c18d477e3056 --- /dev/null +++ b/mlir/test/Target/DXSA/hlsl/abs2.test @@ -0,0 +1,16 @@ +// RUN: mlir-translate --import-dxsa-bin %S/inputs/abs2.shex | FileCheck %s +// NOTE: Assertions have been autogenerated by utils/generate-test-checks.py + + +// CHECK-LABEL: dxsa.dcl_global_flags +// CHECK: dxsa.dcl_input_ps constant v<0, > +// CHECK: dxsa.dcl_output o<0> +// CHECK: %[[INDEX_0:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_0:.*]] = dxsa.operand %[[INDEX_0]] {mask = 240 : i32, num_components = 4 : i32, type = 2 : i32} +// CHECK: %[[INDEX_1:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_1:.*]] = dxsa.operand %[[INDEX_1]] {modifier = 1 : i32, num_components = 4 : i32, swizzle = dense<[1, 0, 0, 0]> : vector<4xi32>, type = 1 : i32} +// CHECK: %[[INDEX_2:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_2:.*]] = dxsa.operand %[[INDEX_2]] {num_components = 4 : i32, swizzle = dense<[1, 0, 0, 0]> : vector<4xi32>, type = 1 : i32} +// CHECK: dxsa.instruction "imax" %[[OPERAND_0]], %[[OPERAND_1]], %[[OPERAND_2]] +// CHECK: dxsa.instruction "ret" + diff --git a/mlir/test/Target/DXSA/hlsl/atomics.test b/mlir/test/Target/DXSA/hlsl/atomics.test new file mode 100644 index 000000000000..7a86e545469f --- /dev/null +++ b/mlir/test/Target/DXSA/hlsl/atomics.test @@ -0,0 +1,251 @@ +// RUN: mlir-translate --import-dxsa-bin %S/inputs/atomics.shex | FileCheck %s +// NOTE: Assertions have been autogenerated by utils/generate-test-checks.py + + +// CHECK-LABEL: dxsa.dcl_global_flags +// CHECK: dxsa.dcl_uav_typed , +// CHECK: dxsa.dcl_uav_raw +// CHECK: dxsa.dcl_uav_raw +// CHECK: dxsa.dcl_uav_typed , +// CHECK: dxsa.dcl_uav_typed , +// CHECK: dxsa.dcl_uav_typed , +// CHECK: dxsa.dcl_uav_typed , +// CHECK: dxsa.dcl_input_ps constant v<0> +// CHECK: dxsa.dcl_output o<0> +// CHECK: dxsa.dcl_temps 2 +// CHECK: %[[INDEX_0:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[INDEX_1:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_0:.*]] = dxsa.operand %[[INDEX_0]], %[[INDEX_1]] {num_components = 0 : i32, type = 30 : i32} +// CHECK: %[[INDEX_2:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_1:.*]] = dxsa.operand %[[INDEX_2]] {num_components = 4 : i32, one = 2 : i32, type = 1 : i32} +// CHECK: %[[INDEX_3:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_2:.*]] = dxsa.operand %[[INDEX_3]] {num_components = 4 : i32, one = 2 : i32, type = 1 : i32} +// CHECK: dxsa.instruction "atomic_iadd" %[[OPERAND_0]], %[[OPERAND_1]], %[[OPERAND_2]] +// CHECK: %[[INDEX_4:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[INDEX_5:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_3:.*]] = dxsa.operand %[[INDEX_4]], %[[INDEX_5]] {num_components = 0 : i32, type = 30 : i32} +// CHECK: %[[INDEX_6:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_4:.*]] = dxsa.operand %[[INDEX_6]] {num_components = 4 : i32, one = 2 : i32, type = 1 : i32} +// CHECK: %[[INDEX_7:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_5:.*]] = dxsa.operand %[[INDEX_7]] {num_components = 4 : i32, one = 2 : i32, type = 1 : i32} +// CHECK: dxsa.instruction "atomic_umin" %[[OPERAND_3]], %[[OPERAND_4]], %[[OPERAND_5]] +// CHECK: %[[INDEX_8:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[INDEX_9:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_6:.*]] = dxsa.operand %[[INDEX_8]], %[[INDEX_9]] {num_components = 0 : i32, type = 30 : i32} +// CHECK: %[[INDEX_10:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_7:.*]] = dxsa.operand %[[INDEX_10]] {num_components = 4 : i32, one = 2 : i32, type = 1 : i32} +// CHECK: %[[INDEX_11:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_8:.*]] = dxsa.operand %[[INDEX_11]] {num_components = 4 : i32, one = 2 : i32, type = 1 : i32} +// CHECK: dxsa.instruction "atomic_umax" %[[OPERAND_6]], %[[OPERAND_7]], %[[OPERAND_8]] +// CHECK: %[[INDEX_12:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[INDEX_13:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_9:.*]] = dxsa.operand %[[INDEX_12]], %[[INDEX_13]] {num_components = 0 : i32, type = 30 : i32} +// CHECK: %[[INDEX_14:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_10:.*]] = dxsa.operand %[[INDEX_14]] {num_components = 4 : i32, one = 2 : i32, type = 1 : i32} +// CHECK: %[[INDEX_15:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_11:.*]] = dxsa.operand %[[INDEX_15]] {num_components = 4 : i32, one = 2 : i32, type = 1 : i32} +// CHECK: dxsa.instruction "atomic_and" %[[OPERAND_9]], %[[OPERAND_10]], %[[OPERAND_11]] +// CHECK: %[[INDEX_16:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[INDEX_17:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_12:.*]] = dxsa.operand %[[INDEX_16]], %[[INDEX_17]] {num_components = 0 : i32, type = 30 : i32} +// CHECK: %[[INDEX_18:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_13:.*]] = dxsa.operand %[[INDEX_18]] {num_components = 4 : i32, one = 2 : i32, type = 1 : i32} +// CHECK: %[[INDEX_19:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_14:.*]] = dxsa.operand %[[INDEX_19]] {num_components = 4 : i32, one = 2 : i32, type = 1 : i32} +// CHECK: dxsa.instruction "atomic_or" %[[OPERAND_12]], %[[OPERAND_13]], %[[OPERAND_14]] +// CHECK: %[[INDEX_20:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[INDEX_21:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_15:.*]] = dxsa.operand %[[INDEX_20]], %[[INDEX_21]] {num_components = 0 : i32, type = 30 : i32} +// CHECK: %[[INDEX_22:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_16:.*]] = dxsa.operand %[[INDEX_22]] {num_components = 4 : i32, one = 2 : i32, type = 1 : i32} +// CHECK: %[[INDEX_23:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_17:.*]] = dxsa.operand %[[INDEX_23]] {num_components = 4 : i32, one = 2 : i32, type = 1 : i32} +// CHECK: dxsa.instruction "atomic_xor" %[[OPERAND_15]], %[[OPERAND_16]], %[[OPERAND_17]] +// CHECK: %[[INDEX_24:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_18:.*]] = dxsa.operand %[[INDEX_24]] {mask = 16 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_25:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[INDEX_26:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_19:.*]] = dxsa.operand %[[INDEX_25]], %[[INDEX_26]] {num_components = 0 : i32, type = 30 : i32} +// CHECK: %[[INDEX_27:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_20:.*]] = dxsa.operand %[[INDEX_27]] {num_components = 4 : i32, one = 2 : i32, type = 1 : i32} +// CHECK: %[[INDEX_28:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_21:.*]] = dxsa.operand %[[INDEX_28]] {num_components = 4 : i32, one = 2 : i32, type = 1 : i32} +// CHECK: dxsa.instruction "imm_atomic_iadd" %[[OPERAND_18]], %[[OPERAND_19]], %[[OPERAND_20]], %[[OPERAND_21]] +// CHECK: %[[INDEX_29:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_22:.*]] = dxsa.operand %[[INDEX_29]] {mask = 16 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_30:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_23:.*]] = dxsa.operand %[[INDEX_30]] {num_components = 4 : i32, one = 0 : i32, type = 0 : i32} +// CHECK: %[[INDEX_31:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_24:.*]] = dxsa.operand %[[INDEX_31]] {num_components = 4 : i32, one = 2 : i32, type = 1 : i32} +// CHECK: dxsa.instruction "iadd" %[[OPERAND_22]], %[[OPERAND_23]], %[[OPERAND_24]] +// CHECK: %[[INDEX_32:.*]] = dxsa.index.imm {imm = 3 : i32} +// CHECK: %[[INDEX_33:.*]] = dxsa.index.imm {imm = 30 : i32} +// CHECK: %[[OPERAND_25:.*]] = dxsa.operand %[[INDEX_32]], %[[INDEX_33]] {num_components = 0 : i32, type = 30 : i32} +// CHECK: %[[INDEX_34:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_26:.*]] = dxsa.operand %[[INDEX_34]] {num_components = 4 : i32, swizzle = dense<[0, 1, 0, 0]> : vector<4xi32>, type = 1 : i32} +// CHECK: %[[INDEX_35:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_27:.*]] = dxsa.operand %[[INDEX_35]] {num_components = 4 : i32, one = 0 : i32, type = 0 : i32} +// CHECK: dxsa.instruction "atomic_iadd" %[[OPERAND_25]], %[[OPERAND_26]], %[[OPERAND_27]] +// CHECK: %[[INDEX_36:.*]] = dxsa.index.imm {imm = 4 : i32} +// CHECK: %[[INDEX_37:.*]] = dxsa.index.imm {imm = 31 : i32} +// CHECK: %[[OPERAND_28:.*]] = dxsa.operand %[[INDEX_36]], %[[INDEX_37]] {num_components = 0 : i32, type = 30 : i32} +// CHECK: %[[INDEX_38:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_29:.*]] = dxsa.operand %[[INDEX_38]] {num_components = 4 : i32, swizzle = dense<[1, 3, 2, 1]> : vector<4xi32>, type = 1 : i32} +// CHECK: %[[INDEX_39:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_30:.*]] = dxsa.operand %[[INDEX_39]] {num_components = 4 : i32, one = 0 : i32, type = 0 : i32} +// CHECK: dxsa.instruction "atomic_iadd" %[[OPERAND_28]], %[[OPERAND_29]], %[[OPERAND_30]] +// CHECK: %[[INDEX_40:.*]] = dxsa.index.imm {imm = 5 : i32} +// CHECK: %[[INDEX_41:.*]] = dxsa.index.imm {imm = 32 : i32} +// CHECK: %[[OPERAND_31:.*]] = dxsa.operand %[[INDEX_40]], %[[INDEX_41]] {num_components = 0 : i32, type = 30 : i32} +// CHECK: %[[INDEX_42:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_32:.*]] = dxsa.operand %[[INDEX_42]] {num_components = 4 : i32, swizzle = dense<[0, 1, 2, 0]> : vector<4xi32>, type = 1 : i32} +// CHECK: %[[INDEX_43:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_33:.*]] = dxsa.operand %[[INDEX_43]] {num_components = 4 : i32, one = 0 : i32, type = 0 : i32} +// CHECK: dxsa.instruction "atomic_iadd" %[[OPERAND_31]], %[[OPERAND_32]], %[[OPERAND_33]] +// CHECK: %[[INDEX_44:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_34:.*]] = dxsa.operand %[[INDEX_44]] {mask = 32 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[OPERAND_35:.*]] = dxsa.operand.imm {imm = dense<30> : vector<1xi32>} +// CHECK: %[[OPERAND_36:.*]] = dxsa.operand.imm {imm = dense<2> : vector<1xi32>} +// CHECK: %[[INDEX_45:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_37:.*]] = dxsa.operand %[[INDEX_45]] {num_components = 4 : i32, one = 0 : i32, type = 1 : i32} +// CHECK: %[[OPERAND_38:.*]] = dxsa.operand.imm {imm = dense<1> : vector<1xi32>} +// CHECK: dxsa.instruction "bfi" %[[OPERAND_34]], %[[OPERAND_35]], %[[OPERAND_36]], %[[OPERAND_37]], %[[OPERAND_38]] +// CHECK: %[[INDEX_46:.*]] = dxsa.index.imm {imm = 6 : i32} +// CHECK: %[[INDEX_47:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_39:.*]] = dxsa.operand %[[INDEX_47]] {num_components = 4 : i32, one = 1 : i32, type = 0 : i32} +// CHECK: %[[INDEX_48:.*]] = dxsa.index.rel.imm %[[OPERAND_39]] {imm = 33 : i32, op = "add"} +// CHECK: %[[OPERAND_40:.*]] = dxsa.operand %[[INDEX_46]], %[[INDEX_48]] {num_components = 0 : i32, type = 30 : i32} +// CHECK: %[[INDEX_49:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_41:.*]] = dxsa.operand %[[INDEX_49]] {num_components = 4 : i32, swizzle = dense<[0, 1, 2, 0]> : vector<4xi32>, type = 1 : i32} +// CHECK: %[[INDEX_50:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_42:.*]] = dxsa.operand %[[INDEX_50]] {num_components = 4 : i32, one = 0 : i32, type = 0 : i32} +// CHECK: dxsa.instruction "atomic_iadd" %[[OPERAND_40]], %[[OPERAND_41]], %[[OPERAND_42]] +// CHECK: %[[INDEX_51:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_43:.*]] = dxsa.operand %[[INDEX_51]] {mask = 16 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_52:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[INDEX_53:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_44:.*]] = dxsa.operand %[[INDEX_52]], %[[INDEX_53]] {num_components = 0 : i32, type = 30 : i32} +// CHECK: %[[INDEX_54:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_45:.*]] = dxsa.operand %[[INDEX_54]] {num_components = 4 : i32, one = 2 : i32, type = 1 : i32} +// CHECK: %[[INDEX_55:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_46:.*]] = dxsa.operand %[[INDEX_55]] {num_components = 4 : i32, one = 3 : i32, type = 1 : i32} +// CHECK: %[[INDEX_56:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_47:.*]] = dxsa.operand %[[INDEX_56]] {num_components = 4 : i32, one = 0 : i32, type = 0 : i32} +// CHECK: dxsa.instruction "imm_atomic_cmp_exch" %[[OPERAND_43]], %[[OPERAND_44]], %[[OPERAND_45]], %[[OPERAND_46]], %[[OPERAND_47]] +// CHECK: %[[INDEX_57:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_48:.*]] = dxsa.operand %[[INDEX_57]] {mask = 16 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_58:.*]] = dxsa.index.imm {imm = 1 : i32} +// CHECK: %[[INDEX_59:.*]] = dxsa.index.imm {imm = 1 : i32} +// CHECK: %[[OPERAND_49:.*]] = dxsa.operand %[[INDEX_58]], %[[INDEX_59]] {num_components = 0 : i32, type = 30 : i32} +// CHECK: %[[INDEX_60:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_50:.*]] = dxsa.operand %[[INDEX_60]] {num_components = 4 : i32, one = 0 : i32, type = 1 : i32} +// CHECK: %[[INDEX_61:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_51:.*]] = dxsa.operand %[[INDEX_61]] {num_components = 4 : i32, one = 2 : i32, type = 1 : i32} +// CHECK: dxsa.instruction "imm_atomic_iadd" %[[OPERAND_48]], %[[OPERAND_49]], %[[OPERAND_50]], %[[OPERAND_51]] +// CHECK: %[[INDEX_62:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_52:.*]] = dxsa.operand %[[INDEX_62]] {mask = 16 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_63:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_53:.*]] = dxsa.operand %[[INDEX_63]] {num_components = 4 : i32, one = 1 : i32, type = 1 : i32} +// CHECK: %[[OPERAND_54:.*]] = dxsa.operand.imm {imm = dense<14> : vector<1xi32>} +// CHECK: dxsa.instruction "iadd" %[[OPERAND_52]], %[[OPERAND_53]], %[[OPERAND_54]] +// CHECK: %[[INDEX_64:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_55:.*]] = dxsa.operand %[[INDEX_64]] {mask = 16 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_65:.*]] = dxsa.index.imm {imm = 2 : i32} +// CHECK: %[[INDEX_66:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_56:.*]] = dxsa.operand %[[INDEX_66]] {num_components = 4 : i32, one = 0 : i32, type = 0 : i32} +// CHECK: %[[INDEX_67:.*]] = dxsa.index.rel.imm %[[OPERAND_56]] {imm = 2 : i32, op = "add"} +// CHECK: %[[OPERAND_57:.*]] = dxsa.operand %[[INDEX_65]], %[[INDEX_67]] {num_components = 0 : i32, type = 30 : i32} +// CHECK: %[[INDEX_68:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_58:.*]] = dxsa.operand %[[INDEX_68]] {num_components = 4 : i32, one = 0 : i32, type = 1 : i32} +// CHECK: %[[INDEX_69:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_59:.*]] = dxsa.operand %[[INDEX_69]] {num_components = 4 : i32, one = 2 : i32, type = 1 : i32} +// CHECK: dxsa.instruction "imm_atomic_iadd" %[[OPERAND_55]], %[[OPERAND_57]], %[[OPERAND_58]], %[[OPERAND_59]] +// CHECK: %[[INDEX_70:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_60:.*]] = dxsa.operand %[[INDEX_70]] {mask = 16 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_71:.*]] = dxsa.index.imm {imm = 1 : i32} +// CHECK: %[[INDEX_72:.*]] = dxsa.index.imm {imm = 1 : i32} +// CHECK: %[[OPERAND_61:.*]] = dxsa.operand %[[INDEX_71]], %[[INDEX_72]] {num_components = 0 : i32, type = 30 : i32} +// CHECK: %[[INDEX_73:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_62:.*]] = dxsa.operand %[[INDEX_73]] {num_components = 4 : i32, one = 0 : i32, type = 1 : i32} +// CHECK: %[[INDEX_74:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_63:.*]] = dxsa.operand %[[INDEX_74]] {num_components = 4 : i32, one = 2 : i32, type = 1 : i32} +// CHECK: dxsa.instruction "imm_atomic_umin" %[[OPERAND_60]], %[[OPERAND_61]], %[[OPERAND_62]], %[[OPERAND_63]] +// CHECK: %[[INDEX_75:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_64:.*]] = dxsa.operand %[[INDEX_75]] {mask = 16 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_76:.*]] = dxsa.index.imm {imm = 1 : i32} +// CHECK: %[[INDEX_77:.*]] = dxsa.index.imm {imm = 1 : i32} +// CHECK: %[[OPERAND_65:.*]] = dxsa.operand %[[INDEX_76]], %[[INDEX_77]] {num_components = 0 : i32, type = 30 : i32} +// CHECK: %[[INDEX_78:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_66:.*]] = dxsa.operand %[[INDEX_78]] {num_components = 4 : i32, one = 0 : i32, type = 1 : i32} +// CHECK: %[[INDEX_79:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_67:.*]] = dxsa.operand %[[INDEX_79]] {num_components = 4 : i32, one = 2 : i32, type = 1 : i32} +// CHECK: dxsa.instruction "imm_atomic_umax" %[[OPERAND_64]], %[[OPERAND_65]], %[[OPERAND_66]], %[[OPERAND_67]] +// CHECK: %[[INDEX_80:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_68:.*]] = dxsa.operand %[[INDEX_80]] {mask = 16 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_81:.*]] = dxsa.index.imm {imm = 1 : i32} +// CHECK: %[[INDEX_82:.*]] = dxsa.index.imm {imm = 1 : i32} +// CHECK: %[[OPERAND_69:.*]] = dxsa.operand %[[INDEX_81]], %[[INDEX_82]] {num_components = 0 : i32, type = 30 : i32} +// CHECK: %[[INDEX_83:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_70:.*]] = dxsa.operand %[[INDEX_83]] {num_components = 4 : i32, one = 0 : i32, type = 1 : i32} +// CHECK: %[[INDEX_84:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_71:.*]] = dxsa.operand %[[INDEX_84]] {num_components = 4 : i32, one = 2 : i32, type = 1 : i32} +// CHECK: dxsa.instruction "imm_atomic_and" %[[OPERAND_68]], %[[OPERAND_69]], %[[OPERAND_70]], %[[OPERAND_71]] +// CHECK: %[[INDEX_85:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_72:.*]] = dxsa.operand %[[INDEX_85]] {mask = 16 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_86:.*]] = dxsa.index.imm {imm = 1 : i32} +// CHECK: %[[INDEX_87:.*]] = dxsa.index.imm {imm = 1 : i32} +// CHECK: %[[OPERAND_73:.*]] = dxsa.operand %[[INDEX_86]], %[[INDEX_87]] {num_components = 0 : i32, type = 30 : i32} +// CHECK: %[[INDEX_88:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_74:.*]] = dxsa.operand %[[INDEX_88]] {num_components = 4 : i32, one = 0 : i32, type = 1 : i32} +// CHECK: %[[INDEX_89:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_75:.*]] = dxsa.operand %[[INDEX_89]] {num_components = 4 : i32, one = 2 : i32, type = 1 : i32} +// CHECK: dxsa.instruction "imm_atomic_or" %[[OPERAND_72]], %[[OPERAND_73]], %[[OPERAND_74]], %[[OPERAND_75]] +// CHECK: %[[INDEX_90:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_76:.*]] = dxsa.operand %[[INDEX_90]] {mask = 16 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_91:.*]] = dxsa.index.imm {imm = 1 : i32} +// CHECK: %[[INDEX_92:.*]] = dxsa.index.imm {imm = 1 : i32} +// CHECK: %[[OPERAND_77:.*]] = dxsa.operand %[[INDEX_91]], %[[INDEX_92]] {num_components = 0 : i32, type = 30 : i32} +// CHECK: %[[INDEX_93:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_78:.*]] = dxsa.operand %[[INDEX_93]] {num_components = 4 : i32, one = 0 : i32, type = 1 : i32} +// CHECK: %[[INDEX_94:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_79:.*]] = dxsa.operand %[[INDEX_94]] {num_components = 4 : i32, one = 2 : i32, type = 1 : i32} +// CHECK: dxsa.instruction "imm_atomic_xor" %[[OPERAND_76]], %[[OPERAND_77]], %[[OPERAND_78]], %[[OPERAND_79]] +// CHECK: %[[INDEX_95:.*]] = dxsa.index.imm {imm = 1 : i32} +// CHECK: %[[OPERAND_80:.*]] = dxsa.operand %[[INDEX_95]] {mask = 16 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_96:.*]] = dxsa.index.imm {imm = 1 : i32} +// CHECK: %[[INDEX_97:.*]] = dxsa.index.imm {imm = 1 : i32} +// CHECK: %[[OPERAND_81:.*]] = dxsa.operand %[[INDEX_96]], %[[INDEX_97]] {num_components = 0 : i32, type = 30 : i32} +// CHECK: %[[INDEX_98:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_82:.*]] = dxsa.operand %[[INDEX_98]] {num_components = 4 : i32, one = 2 : i32, type = 1 : i32} +// CHECK: %[[INDEX_99:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_83:.*]] = dxsa.operand %[[INDEX_99]] {num_components = 4 : i32, one = 0 : i32, type = 0 : i32} +// CHECK: dxsa.instruction "imm_atomic_exch" %[[OPERAND_80]], %[[OPERAND_81]], %[[OPERAND_82]], %[[OPERAND_83]] +// CHECK: %[[INDEX_100:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_84:.*]] = dxsa.operand %[[INDEX_100]] {mask = 16 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_101:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_85:.*]] = dxsa.operand %[[INDEX_101]] {num_components = 4 : i32, one = 0 : i32, type = 0 : i32} +// CHECK: %[[INDEX_102:.*]] = dxsa.index.imm {imm = 1 : i32} +// CHECK: %[[OPERAND_86:.*]] = dxsa.operand %[[INDEX_102]] {num_components = 4 : i32, one = 0 : i32, type = 0 : i32} +// CHECK: dxsa.instruction "iadd" %[[OPERAND_84]], %[[OPERAND_85]], %[[OPERAND_86]] +// CHECK: %[[INDEX_103:.*]] = dxsa.index.imm {imm = 1 : i32} +// CHECK: %[[OPERAND_87:.*]] = dxsa.operand %[[INDEX_103]] {mask = 16 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_104:.*]] = dxsa.index.imm {imm = 1 : i32} +// CHECK: %[[INDEX_105:.*]] = dxsa.index.imm {imm = 1 : i32} +// CHECK: %[[OPERAND_88:.*]] = dxsa.operand %[[INDEX_104]], %[[INDEX_105]] {num_components = 0 : i32, type = 30 : i32} +// CHECK: %[[INDEX_106:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_89:.*]] = dxsa.operand %[[INDEX_106]] {num_components = 4 : i32, one = 2 : i32, type = 1 : i32} +// CHECK: %[[INDEX_107:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_90:.*]] = dxsa.operand %[[INDEX_107]] {num_components = 4 : i32, one = 3 : i32, type = 1 : i32} +// CHECK: %[[INDEX_108:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_91:.*]] = dxsa.operand %[[INDEX_108]] {num_components = 4 : i32, one = 0 : i32, type = 0 : i32} +// CHECK: dxsa.instruction "imm_atomic_cmp_exch" %[[OPERAND_87]], %[[OPERAND_88]], %[[OPERAND_89]], %[[OPERAND_90]], %[[OPERAND_91]] +// CHECK: %[[INDEX_109:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_92:.*]] = dxsa.operand %[[INDEX_109]] {mask = 16 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_110:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_93:.*]] = dxsa.operand %[[INDEX_110]] {num_components = 4 : i32, one = 0 : i32, type = 0 : i32} +// CHECK: %[[INDEX_111:.*]] = dxsa.index.imm {imm = 1 : i32} +// CHECK: %[[OPERAND_94:.*]] = dxsa.operand %[[INDEX_111]] {num_components = 4 : i32, one = 0 : i32, type = 0 : i32} +// CHECK: dxsa.instruction "iadd" %[[OPERAND_92]], %[[OPERAND_93]], %[[OPERAND_94]] +// CHECK: dxsa.utof o<0>, r<0, > +// CHECK: dxsa.instruction "ret" + diff --git a/mlir/test/Target/DXSA/hlsl/bad_ftoi.test b/mlir/test/Target/DXSA/hlsl/bad_ftoi.test new file mode 100644 index 000000000000..730c09e53a99 --- /dev/null +++ b/mlir/test/Target/DXSA/hlsl/bad_ftoi.test @@ -0,0 +1,11 @@ +// RUN: mlir-translate --import-dxsa-bin %S/inputs/bad_ftoi.shex | FileCheck %s +// NOTE: Assertions have been autogenerated by utils/generate-test-checks.py + + +// CHECK-LABEL: dxsa.dcl_global_flags +// CHECK: dxsa.dcl_output o<0> +// CHECK: dxsa.ftou o<0, >, l(0x7F7FFFFF) +// CHECK: dxsa.ftou o<0, >, l(0xFF7FFFFF) +// CHECK: dxsa.ftoi o<0, >, l(0x7F7FFFFF, 0xFF7FFFFF, 0x0, 0x0) +// CHECK: dxsa.instruction "ret" + diff --git a/mlir/test/Target/DXSA/hlsl/binary1.test b/mlir/test/Target/DXSA/hlsl/binary1.test new file mode 100644 index 000000000000..233bc82f6d0d --- /dev/null +++ b/mlir/test/Target/DXSA/hlsl/binary1.test @@ -0,0 +1,17 @@ +// RUN: mlir-translate --import-dxsa-bin %S/inputs/binary1.shex | FileCheck %s +// NOTE: Assertions have been autogenerated by utils/generate-test-checks.py + + +// CHECK-LABEL: dxsa.dcl_global_flags +// CHECK: dxsa.dcl_input_ps linear v<0, > +// CHECK: dxsa.dcl_input_ps linear v<0, > +// CHECK: dxsa.dcl_input_ps linear v<0, > +// CHECK: dxsa.dcl_output o<0, > +// CHECK: dxsa.dcl_temps 1 +// CHECK: dxsa.add r<0, >, v<0, >, v<0, > +// CHECK: dxsa.div r<0, >, r<0, >, v<0, > +// CHECK: dxsa.mul r<0, >, r<0, >, v<0, > +// CHECK: dxsa.max r<0, >, r<0, >, v<0, > +// CHECK: dxsa.min o<0, >, r<0, >, v<0, > +// CHECK: dxsa.instruction "ret" + diff --git a/mlir/test/Target/DXSA/hlsl/bool1.test b/mlir/test/Target/DXSA/hlsl/bool1.test new file mode 100644 index 000000000000..5412f59c8b8e --- /dev/null +++ b/mlir/test/Target/DXSA/hlsl/bool1.test @@ -0,0 +1,29 @@ +// RUN: mlir-translate --import-dxsa-bin %S/inputs/bool1.shex | FileCheck %s +// NOTE: Assertions have been autogenerated by utils/generate-test-checks.py + + +// CHECK-LABEL: dxsa.dcl_global_flags +// CHECK: dxsa.dcl_input_ps constant v<0, > +// CHECK: dxsa.dcl_output o<0, > +// CHECK: dxsa.dcl_temps 1 +// CHECK: %[[INDEX_0:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_0:.*]] = dxsa.operand %[[INDEX_0]] {mask = 16 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_1:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_1:.*]] = dxsa.operand %[[INDEX_1]] {num_components = 4 : i32, one = 0 : i32, type = 1 : i32} +// CHECK: dxsa.instruction "firstbit_hi" %[[OPERAND_0]], %[[OPERAND_1]] +// CHECK: %[[INDEX_2:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_2:.*]] = dxsa.operand %[[INDEX_2]] {mask = 16 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_3:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_3:.*]] = dxsa.operand %[[INDEX_3]] {modifier = 1 : i32, num_components = 4 : i32, one = 0 : i32, type = 0 : i32} +// CHECK: %[[OPERAND_4:.*]] = dxsa.operand.imm {imm = dense<31> : vector<1xi32>} +// CHECK: dxsa.instruction "iadd" %[[OPERAND_2]], %[[OPERAND_3]], %[[OPERAND_4]] +// CHECK: %[[INDEX_4:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_5:.*]] = dxsa.operand %[[INDEX_4]] {mask = 16 : i32, num_components = 4 : i32, type = 2 : i32} +// CHECK: %[[INDEX_5:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_6:.*]] = dxsa.operand %[[INDEX_5]] {num_components = 4 : i32, one = 0 : i32, type = 1 : i32} +// CHECK: %[[INDEX_6:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_7:.*]] = dxsa.operand %[[INDEX_6]] {num_components = 4 : i32, one = 0 : i32, type = 0 : i32} +// CHECK: %[[OPERAND_8:.*]] = dxsa.operand.imm {imm = dense<-1> : vector<1xi32>} +// CHECK: dxsa.instruction "movc" %[[OPERAND_5]], %[[OPERAND_6]], %[[OPERAND_7]], %[[OPERAND_8]] +// CHECK: dxsa.instruction "ret" + diff --git a/mlir/test/Target/DXSA/hlsl/bool2.test b/mlir/test/Target/DXSA/hlsl/bool2.test new file mode 100644 index 000000000000..453b1cf7bd71 --- /dev/null +++ b/mlir/test/Target/DXSA/hlsl/bool2.test @@ -0,0 +1,19 @@ +// RUN: mlir-translate --import-dxsa-bin %S/inputs/bool2.shex | FileCheck %s +// NOTE: Assertions have been autogenerated by utils/generate-test-checks.py + + +// CHECK-LABEL: dxsa.dcl_global_flags +// CHECK: dxsa.dcl_input_ps linear v<0, > +// CHECK: dxsa.dcl_input_ps linear v<0, > +// CHECK: dxsa.dcl_output o<0, > +// CHECK: dxsa.dcl_temps 1 +// CHECK: dxsa.lt r<0, >, v<0, >, v<0, > +// CHECK: %[[INDEX_0:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_0:.*]] = dxsa.operand %[[INDEX_0]] {mask = 16 : i32, num_components = 4 : i32, type = 2 : i32} +// CHECK: %[[INDEX_1:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_1:.*]] = dxsa.operand %[[INDEX_1]] {num_components = 4 : i32, one = 0 : i32, type = 0 : i32} +// CHECK: %[[OPERAND_2:.*]] = dxsa.operand.imm {imm = dense<0> : vector<1xi32>} +// CHECK: %[[OPERAND_3:.*]] = dxsa.operand.imm {imm = dense<1065353216> : vector<1xi32>} +// CHECK: dxsa.instruction "movc" %[[OPERAND_0]], %[[OPERAND_1]], %[[OPERAND_2]], %[[OPERAND_3]] +// CHECK: dxsa.instruction "ret" + diff --git a/mlir/test/Target/DXSA/hlsl/bufinfo.test b/mlir/test/Target/DXSA/hlsl/bufinfo.test new file mode 100644 index 000000000000..791d8f5ba964 --- /dev/null +++ b/mlir/test/Target/DXSA/hlsl/bufinfo.test @@ -0,0 +1,68 @@ +// RUN: mlir-translate --import-dxsa-bin %S/inputs/bufinfo.shex | FileCheck %s +// NOTE: Assertions have been autogenerated by utils/generate-test-checks.py + + +// CHECK-LABEL: dxsa.dcl_global_flags +// CHECK: dxsa.dcl_resource_structured +// CHECK: dxsa.dcl_resource_raw +// CHECK: dxsa.dcl_resource , , +// CHECK: dxsa.dcl_uav_structured +// CHECK: dxsa.dcl_uav_raw +// CHECK: dxsa.dcl_uav_typed , +// CHECK: dxsa.dcl_output o<0, > +// CHECK: dxsa.dcl_temps 1 +// CHECK: dxsa.unknown +// CHECK: %[[INDEX_0:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_0:.*]] = dxsa.operand %[[INDEX_0]] {mask = 16 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_1:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_1:.*]] = dxsa.operand %[[INDEX_1]] {num_components = 4 : i32, one = 0 : i32, type = 0 : i32} +// CHECK: %[[OPERAND_2:.*]] = dxsa.operand.imm {imm = dense<52> : vector<1xi32>} +// CHECK: dxsa.instruction "iadd" %[[OPERAND_0]], %[[OPERAND_1]], %[[OPERAND_2]] +// CHECK: dxsa.unknown +// CHECK: %[[INDEX_2:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_3:.*]] = dxsa.operand %[[INDEX_2]] {mask = 16 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_3:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_4:.*]] = dxsa.operand %[[INDEX_3]] {num_components = 4 : i32, one = 0 : i32, type = 0 : i32} +// CHECK: %[[INDEX_4:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_5:.*]] = dxsa.operand %[[INDEX_4]] {num_components = 4 : i32, one = 1 : i32, type = 0 : i32} +// CHECK: dxsa.instruction "iadd" %[[OPERAND_3]], %[[OPERAND_4]], %[[OPERAND_5]] +// CHECK: %[[INDEX_5:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_6:.*]] = dxsa.operand %[[INDEX_5]] {mask = 16 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_6:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_7:.*]] = dxsa.operand %[[INDEX_6]] {num_components = 4 : i32, one = 0 : i32, type = 0 : i32} +// CHECK: %[[OPERAND_8:.*]] = dxsa.operand.imm {imm = dense<52> : vector<1xi32>} +// CHECK: dxsa.instruction "iadd" %[[OPERAND_6]], %[[OPERAND_7]], %[[OPERAND_8]] +// CHECK: dxsa.unknown +// CHECK: %[[INDEX_7:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_9:.*]] = dxsa.operand %[[INDEX_7]] {mask = 16 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_8:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_10:.*]] = dxsa.operand %[[INDEX_8]] {num_components = 4 : i32, one = 1 : i32, type = 0 : i32} +// CHECK: %[[INDEX_9:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_11:.*]] = dxsa.operand %[[INDEX_9]] {num_components = 4 : i32, one = 0 : i32, type = 0 : i32} +// CHECK: dxsa.instruction "iadd" %[[OPERAND_9]], %[[OPERAND_10]], %[[OPERAND_11]] +// CHECK: dxsa.unknown +// CHECK: %[[INDEX_10:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_12:.*]] = dxsa.operand %[[INDEX_10]] {mask = 16 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_11:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_13:.*]] = dxsa.operand %[[INDEX_11]] {num_components = 4 : i32, one = 1 : i32, type = 0 : i32} +// CHECK: %[[INDEX_12:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_14:.*]] = dxsa.operand %[[INDEX_12]] {num_components = 4 : i32, one = 0 : i32, type = 0 : i32} +// CHECK: dxsa.instruction "iadd" %[[OPERAND_12]], %[[OPERAND_13]], %[[OPERAND_14]] +// CHECK: dxsa.unknown +// CHECK: %[[INDEX_13:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_15:.*]] = dxsa.operand %[[INDEX_13]] {mask = 16 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_14:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_16:.*]] = dxsa.operand %[[INDEX_14]] {num_components = 4 : i32, one = 1 : i32, type = 0 : i32} +// CHECK: %[[INDEX_15:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_17:.*]] = dxsa.operand %[[INDEX_15]] {num_components = 4 : i32, one = 0 : i32, type = 0 : i32} +// CHECK: dxsa.instruction "iadd" %[[OPERAND_15]], %[[OPERAND_16]], %[[OPERAND_17]] +// CHECK: dxsa.unknown +// CHECK: %[[INDEX_16:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_18:.*]] = dxsa.operand %[[INDEX_16]] {mask = 16 : i32, num_components = 4 : i32, type = 2 : i32} +// CHECK: %[[INDEX_17:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_19:.*]] = dxsa.operand %[[INDEX_17]] {num_components = 4 : i32, one = 1 : i32, type = 0 : i32} +// CHECK: %[[INDEX_18:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_20:.*]] = dxsa.operand %[[INDEX_18]] {num_components = 4 : i32, one = 0 : i32, type = 0 : i32} +// CHECK: dxsa.instruction "iadd" %[[OPERAND_18]], %[[OPERAND_19]], %[[OPERAND_20]] +// CHECK: dxsa.instruction "ret" + diff --git a/mlir/test/Target/DXSA/hlsl/calc_lod.test b/mlir/test/Target/DXSA/hlsl/calc_lod.test new file mode 100644 index 000000000000..a732fbcb0c8a --- /dev/null +++ b/mlir/test/Target/DXSA/hlsl/calc_lod.test @@ -0,0 +1,43 @@ +// RUN: mlir-translate --import-dxsa-bin %S/inputs/calc_lod.shex | FileCheck %s +// NOTE: Assertions have been autogenerated by utils/generate-test-checks.py + + +// CHECK-LABEL: dxsa.dcl_global_flags +// CHECK: dxsa.dcl_sampler +// CHECK: dxsa.dcl_resource , , +// CHECK: dxsa.dcl_resource , , +// CHECK: dxsa.dcl_resource , , +// CHECK: dxsa.dcl_input_ps linear v<0, > +// CHECK: dxsa.dcl_output o<0> +// CHECK: dxsa.dcl_temps 1 +// CHECK: %[[INDEX_0:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_0:.*]] = dxsa.operand %[[INDEX_0]] {mask = 16 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_1:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_1:.*]] = dxsa.operand %[[INDEX_1]] {num_components = 4 : i32, swizzle = dense<[0, 1, 0, 0]> : vector<4xi32>, type = 1 : i32} +// CHECK: %[[INDEX_2:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_2:.*]] = dxsa.operand %[[INDEX_2]] {num_components = 4 : i32, one = 0 : i32, type = 7 : i32} +// CHECK: %[[INDEX_3:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_3:.*]] = dxsa.operand %[[INDEX_3]] {num_components = 0 : i32, type = 6 : i32} +// CHECK: dxsa.instruction "lod" %[[OPERAND_0]], %[[OPERAND_1]], %[[OPERAND_2]], %[[OPERAND_3]] +// CHECK: %[[INDEX_4:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_4:.*]] = dxsa.operand %[[INDEX_4]] {mask = 32 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_5:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_5:.*]] = dxsa.operand %[[INDEX_5]] {num_components = 4 : i32, swizzle = dense<[0, 1, 0, 0]> : vector<4xi32>, type = 1 : i32} +// CHECK: %[[INDEX_6:.*]] = dxsa.index.imm {imm = 1 : i32} +// CHECK: %[[OPERAND_6:.*]] = dxsa.operand %[[INDEX_6]] {num_components = 4 : i32, one = 0 : i32, type = 7 : i32} +// CHECK: %[[INDEX_7:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_7:.*]] = dxsa.operand %[[INDEX_7]] {num_components = 0 : i32, type = 6 : i32} +// CHECK: dxsa.instruction "lod" %[[OPERAND_4]], %[[OPERAND_5]], %[[OPERAND_6]], %[[OPERAND_7]] +// CHECK: dxsa.add r<0, >, r<0, >, r<0, > +// CHECK: %[[INDEX_8:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_8:.*]] = dxsa.operand %[[INDEX_8]] {mask = 32 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_9:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_9:.*]] = dxsa.operand %[[INDEX_9]] {num_components = 4 : i32, swizzle = dense<[0, 1, 2, 0]> : vector<4xi32>, type = 1 : i32} +// CHECK: %[[INDEX_10:.*]] = dxsa.index.imm {imm = 2 : i32} +// CHECK: %[[OPERAND_10:.*]] = dxsa.operand %[[INDEX_10]] {num_components = 4 : i32, one = 0 : i32, type = 7 : i32} +// CHECK: %[[INDEX_11:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_11:.*]] = dxsa.operand %[[INDEX_11]] {num_components = 0 : i32, type = 6 : i32} +// CHECK: dxsa.instruction "lod" %[[OPERAND_8]], %[[OPERAND_9]], %[[OPERAND_10]], %[[OPERAND_11]] +// CHECK: dxsa.add o<0>, r<0, >, r<0, > +// CHECK: dxsa.instruction "ret" + diff --git a/mlir/test/Target/DXSA/hlsl/call1.test b/mlir/test/Target/DXSA/hlsl/call1.test new file mode 100644 index 000000000000..5c39a694d183 --- /dev/null +++ b/mlir/test/Target/DXSA/hlsl/call1.test @@ -0,0 +1,62 @@ +// RUN: mlir-translate --import-dxsa-bin %S/inputs/call1.shex | FileCheck %s +// NOTE: Assertions have been autogenerated by utils/generate-test-checks.py + + +// CHECK-LABEL: dxsa.dcl_global_flags +// CHECK: dxsa.dcl_input_ps linear v<0, > +// CHECK: dxsa.dcl_input_ps constant v<1, > +// CHECK: dxsa.dcl_output o<0, > +// CHECK: dxsa.dcl_temps 1 +// CHECK: %[[INDEX_0:.*]] = dxsa.index.imm {imm = 1 : i32} +// CHECK: %[[OPERAND_0:.*]] = dxsa.operand %[[INDEX_0]] {num_components = 4 : i32, one = 0 : i32, type = 1 : i32} +// CHECK: dxsa.instruction "switch" %[[OPERAND_0]] +// CHECK: %[[OPERAND_1:.*]] = dxsa.operand.imm {imm = dense<1> : vector<1xi32>} +// CHECK: dxsa.instruction "case" %[[OPERAND_1]] +// CHECK: %[[INDEX_1:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_2:.*]] = dxsa.operand %[[INDEX_1]] {num_components = 0 : i32, type = 10 : i32} +// CHECK: dxsa.instruction "call" %[[OPERAND_2]] +// CHECK: dxsa.instruction "break" +// CHECK: %[[OPERAND_3:.*]] = dxsa.operand.imm {imm = dense<2> : vector<1xi32>} +// CHECK: dxsa.instruction "case" %[[OPERAND_3]] +// CHECK: %[[INDEX_2:.*]] = dxsa.index.imm {imm = 1 : i32} +// CHECK: %[[OPERAND_4:.*]] = dxsa.operand %[[INDEX_2]] {num_components = 0 : i32, type = 10 : i32} +// CHECK: dxsa.instruction "call" %[[OPERAND_4]] +// CHECK: dxsa.instruction "break" +// CHECK: dxsa.instruction "default" +// CHECK: %[[INDEX_3:.*]] = dxsa.index.imm {imm = 2 : i32} +// CHECK: %[[OPERAND_5:.*]] = dxsa.operand %[[INDEX_3]] {num_components = 0 : i32, type = 10 : i32} +// CHECK: dxsa.instruction "call" %[[OPERAND_5]] +// CHECK: dxsa.instruction "break" +// CHECK: dxsa.instruction "endswitch" +// CHECK: %[[INDEX_4:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_6:.*]] = dxsa.operand %[[INDEX_4]] {mask = 16 : i32, num_components = 4 : i32, type = 2 : i32} +// CHECK: %[[INDEX_5:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_7:.*]] = dxsa.operand %[[INDEX_5]] {num_components = 4 : i32, one = 0 : i32, type = 0 : i32} +// CHECK: dxsa.instruction "mov" %[[OPERAND_6]], %[[OPERAND_7]] +// CHECK: dxsa.instruction "ret" +// CHECK: %[[INDEX_6:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_8:.*]] = dxsa.operand %[[INDEX_6]] {num_components = 0 : i32, type = 10 : i32} +// CHECK: dxsa.instruction "label" %[[OPERAND_8]] +// CHECK: %[[INDEX_7:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_9:.*]] = dxsa.operand %[[INDEX_7]] {mask = 16 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[OPERAND_10:.*]] = dxsa.operand.imm {imm = dense<1084227584> : vector<1xi32>} +// CHECK: dxsa.instruction "mov" %[[OPERAND_9]], %[[OPERAND_10]] +// CHECK: dxsa.instruction "ret" +// CHECK: %[[INDEX_8:.*]] = dxsa.index.imm {imm = 1 : i32} +// CHECK: %[[OPERAND_11:.*]] = dxsa.operand %[[INDEX_8]] {num_components = 0 : i32, type = 10 : i32} +// CHECK: dxsa.instruction "label" %[[OPERAND_11]] +// CHECK: %[[INDEX_9:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_12:.*]] = dxsa.operand %[[INDEX_9]] {mask = 16 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_10:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_13:.*]] = dxsa.operand %[[INDEX_10]] {num_components = 4 : i32, one = 0 : i32, type = 1 : i32} +// CHECK: dxsa.instruction "mov" %[[OPERAND_12]], %[[OPERAND_13]] +// CHECK: dxsa.instruction "ret" +// CHECK: %[[INDEX_11:.*]] = dxsa.index.imm {imm = 2 : i32} +// CHECK: %[[OPERAND_14:.*]] = dxsa.operand %[[INDEX_11]] {num_components = 0 : i32, type = 10 : i32} +// CHECK: dxsa.instruction "label" %[[OPERAND_14]] +// CHECK: %[[INDEX_12:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_15:.*]] = dxsa.operand %[[INDEX_12]] {mask = 16 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[OPERAND_16:.*]] = dxsa.operand.imm {imm = dense<1077936128> : vector<1xi32>} +// CHECK: dxsa.instruction "mov" %[[OPERAND_15]], %[[OPERAND_16]] +// CHECK: dxsa.instruction "ret" + diff --git a/mlir/test/Target/DXSA/hlsl/call3.test b/mlir/test/Target/DXSA/hlsl/call3.test new file mode 100644 index 000000000000..ef7d2ea3965a --- /dev/null +++ b/mlir/test/Target/DXSA/hlsl/call3.test @@ -0,0 +1,98 @@ +// RUN: mlir-translate --import-dxsa-bin %S/inputs/call3.shex | FileCheck %s +// NOTE: Assertions have been autogenerated by utils/generate-test-checks.py + + +// CHECK-LABEL: dxsa.dcl_global_flags +// CHECK: dxsa.dcl_input_ps linear v<0, > +// CHECK: dxsa.dcl_input_ps constant v<1, > +// CHECK: dxsa.dcl_output o<0, > +// CHECK: dxsa.dcl_temps 1 +// CHECK: %[[INDEX_0:.*]] = dxsa.index.imm {imm = 1 : i32} +// CHECK: %[[OPERAND_0:.*]] = dxsa.operand %[[INDEX_0]] {num_components = 4 : i32, one = 1 : i32, type = 1 : i32} +// CHECK: dxsa.instruction "if" %[[OPERAND_0]] +// CHECK: %[[INDEX_1:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_1:.*]] = dxsa.operand %[[INDEX_1]] {mask = 16 : i32, num_components = 4 : i32, type = 2 : i32} +// CHECK: %[[INDEX_2:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_2:.*]] = dxsa.operand %[[INDEX_2]] {num_components = 4 : i32, one = 1 : i32, type = 1 : i32} +// CHECK: dxsa.instruction "mov" %[[OPERAND_1]], %[[OPERAND_2]] +// CHECK: dxsa.instruction "ret" +// CHECK: dxsa.instruction "endif" +// CHECK: %[[INDEX_3:.*]] = dxsa.index.imm {imm = 1 : i32} +// CHECK: %[[OPERAND_3:.*]] = dxsa.operand %[[INDEX_3]] {num_components = 4 : i32, one = 0 : i32, type = 1 : i32} +// CHECK: dxsa.instruction "switch" %[[OPERAND_3]] +// CHECK: %[[OPERAND_4:.*]] = dxsa.operand.imm {imm = dense<1> : vector<1xi32>} +// CHECK: dxsa.instruction "case" %[[OPERAND_4]] +// CHECK: %[[INDEX_4:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_5:.*]] = dxsa.operand %[[INDEX_4]] {num_components = 0 : i32, type = 10 : i32} +// CHECK: dxsa.instruction "call" %[[OPERAND_5]] +// CHECK: dxsa.instruction "break" +// CHECK: %[[OPERAND_6:.*]] = dxsa.operand.imm {imm = dense<2> : vector<1xi32>} +// CHECK: dxsa.instruction "case" %[[OPERAND_6]] +// CHECK: %[[INDEX_5:.*]] = dxsa.index.imm {imm = 1 : i32} +// CHECK: %[[OPERAND_7:.*]] = dxsa.operand %[[INDEX_5]] {num_components = 0 : i32, type = 10 : i32} +// CHECK: dxsa.instruction "call" %[[OPERAND_7]] +// CHECK: dxsa.instruction "break" +// CHECK: dxsa.instruction "default" +// CHECK: %[[INDEX_6:.*]] = dxsa.index.imm {imm = 2 : i32} +// CHECK: %[[OPERAND_8:.*]] = dxsa.operand %[[INDEX_6]] {num_components = 0 : i32, type = 10 : i32} +// CHECK: dxsa.instruction "call" %[[OPERAND_8]] +// CHECK: dxsa.instruction "break" +// CHECK: dxsa.instruction "endswitch" +// CHECK: %[[INDEX_7:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_9:.*]] = dxsa.operand %[[INDEX_7]] {mask = 16 : i32, num_components = 4 : i32, type = 2 : i32} +// CHECK: %[[INDEX_8:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_10:.*]] = dxsa.operand %[[INDEX_8]] {num_components = 4 : i32, one = 0 : i32, type = 0 : i32} +// CHECK: dxsa.instruction "mov" %[[OPERAND_9]], %[[OPERAND_10]] +// CHECK: %[[INDEX_9:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_11:.*]] = dxsa.operand %[[INDEX_9]] {num_components = 4 : i32, one = 2 : i32, type = 0 : i32} +// CHECK: dxsa.instruction "retc" %[[OPERAND_11]] +// CHECK: %[[INDEX_10:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_12:.*]] = dxsa.operand %[[INDEX_10]] {mask = 16 : i32, num_components = 4 : i32, type = 2 : i32} +// CHECK: %[[INDEX_11:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_13:.*]] = dxsa.operand %[[INDEX_11]] {num_components = 4 : i32, one = 1 : i32, type = 0 : i32} +// CHECK: dxsa.instruction "mov" %[[OPERAND_12]], %[[OPERAND_13]] +// CHECK: dxsa.instruction "ret" +// CHECK: %[[INDEX_12:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_14:.*]] = dxsa.operand %[[INDEX_12]] {num_components = 0 : i32, type = 10 : i32} +// CHECK: dxsa.instruction "label" %[[OPERAND_14]] +// CHECK: %[[INDEX_13:.*]] = dxsa.index.imm {imm = 1 : i32} +// CHECK: %[[OPERAND_15:.*]] = dxsa.operand %[[INDEX_13]] {num_components = 4 : i32, one = 1 : i32, type = 1 : i32} +// CHECK: dxsa.instruction "if" %[[OPERAND_15]] +// CHECK: %[[INDEX_14:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_16:.*]] = dxsa.operand %[[INDEX_14]] {mask = 16 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_15:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_17:.*]] = dxsa.operand %[[INDEX_15]] {num_components = 4 : i32, one = 1 : i32, type = 1 : i32} +// CHECK: dxsa.instruction "mov" %[[OPERAND_16]], %[[OPERAND_17]] +// CHECK: %[[INDEX_16:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_18:.*]] = dxsa.operand %[[INDEX_16]] {mask = 64 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[OPERAND_19:.*]] = dxsa.operand.imm {imm = dense<-1> : vector<1xi32>} +// CHECK: dxsa.instruction "mov" %[[OPERAND_18]], %[[OPERAND_19]] +// CHECK: dxsa.instruction "ret" +// CHECK: dxsa.instruction "endif" +// CHECK: %[[INDEX_17:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_20:.*]] = dxsa.operand %[[INDEX_17]] {mask = 96 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[OPERAND_21:.*]] = dxsa.operand.imm {imm = dense<[0, 1084227584, 0, 0]> : vector<4xi32>} +// CHECK: dxsa.instruction "mov" %[[OPERAND_20]], %[[OPERAND_21]] +// CHECK: dxsa.instruction "ret" +// CHECK: %[[INDEX_18:.*]] = dxsa.index.imm {imm = 1 : i32} +// CHECK: %[[OPERAND_22:.*]] = dxsa.operand %[[INDEX_18]] {num_components = 0 : i32, type = 10 : i32} +// CHECK: dxsa.instruction "label" %[[OPERAND_22]] +// CHECK: %[[INDEX_19:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_23:.*]] = dxsa.operand %[[INDEX_19]] {mask = 32 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_20:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_24:.*]] = dxsa.operand %[[INDEX_20]] {num_components = 4 : i32, one = 0 : i32, type = 1 : i32} +// CHECK: dxsa.instruction "mov" %[[OPERAND_23]], %[[OPERAND_24]] +// CHECK: %[[INDEX_21:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_25:.*]] = dxsa.operand %[[INDEX_21]] {mask = 64 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[OPERAND_26:.*]] = dxsa.operand.imm {imm = dense<0> : vector<1xi32>} +// CHECK: dxsa.instruction "mov" %[[OPERAND_25]], %[[OPERAND_26]] +// CHECK: dxsa.instruction "ret" +// CHECK: %[[INDEX_22:.*]] = dxsa.index.imm {imm = 2 : i32} +// CHECK: %[[OPERAND_27:.*]] = dxsa.operand %[[INDEX_22]] {num_components = 0 : i32, type = 10 : i32} +// CHECK: dxsa.instruction "label" %[[OPERAND_27]] +// CHECK: %[[INDEX_23:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_28:.*]] = dxsa.operand %[[INDEX_23]] {mask = 96 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[OPERAND_29:.*]] = dxsa.operand.imm {imm = dense<[0, 1077936128, 0, 0]> : vector<4xi32>} +// CHECK: dxsa.instruction "mov" %[[OPERAND_28]], %[[OPERAND_29]] +// CHECK: dxsa.instruction "ret" + diff --git a/mlir/test/Target/DXSA/hlsl/cast1.test b/mlir/test/Target/DXSA/hlsl/cast1.test new file mode 100644 index 000000000000..1956d71511d3 --- /dev/null +++ b/mlir/test/Target/DXSA/hlsl/cast1.test @@ -0,0 +1,10 @@ +// RUN: mlir-translate --import-dxsa-bin %S/inputs/cast1.shex | FileCheck %s +// NOTE: Assertions have been autogenerated by utils/generate-test-checks.py + + +// CHECK-LABEL: dxsa.dcl_global_flags +// CHECK: dxsa.dcl_input_ps constant v<0, > +// CHECK: dxsa.dcl_output o<0, > +// CHECK: dxsa.itof o<0, >, v<0, > +// CHECK: dxsa.instruction "ret" + diff --git a/mlir/test/Target/DXSA/hlsl/cast2.test b/mlir/test/Target/DXSA/hlsl/cast2.test new file mode 100644 index 000000000000..34f09b816fa7 --- /dev/null +++ b/mlir/test/Target/DXSA/hlsl/cast2.test @@ -0,0 +1,10 @@ +// RUN: mlir-translate --import-dxsa-bin %S/inputs/cast2.shex | FileCheck %s +// NOTE: Assertions have been autogenerated by utils/generate-test-checks.py + + +// CHECK-LABEL: dxsa.dcl_global_flags +// CHECK: dxsa.dcl_input_ps constant v<0, > +// CHECK: dxsa.dcl_output o<0, > +// CHECK: dxsa.utof o<0, >, v<0, > +// CHECK: dxsa.instruction "ret" + diff --git a/mlir/test/Target/DXSA/hlsl/cast3.test b/mlir/test/Target/DXSA/hlsl/cast3.test new file mode 100644 index 000000000000..c3fe4baacf81 --- /dev/null +++ b/mlir/test/Target/DXSA/hlsl/cast3.test @@ -0,0 +1,10 @@ +// RUN: mlir-translate --import-dxsa-bin %S/inputs/cast3.shex | FileCheck %s +// NOTE: Assertions have been autogenerated by utils/generate-test-checks.py + + +// CHECK-LABEL: dxsa.dcl_global_flags +// CHECK: dxsa.dcl_input_ps linear v<0, > +// CHECK: dxsa.dcl_output o<0, > +// CHECK: dxsa.ftoi o<0, >, v<0, > +// CHECK: dxsa.instruction "ret" + diff --git a/mlir/test/Target/DXSA/hlsl/cast4.test b/mlir/test/Target/DXSA/hlsl/cast4.test new file mode 100644 index 000000000000..a6145a6ab167 --- /dev/null +++ b/mlir/test/Target/DXSA/hlsl/cast4.test @@ -0,0 +1,10 @@ +// RUN: mlir-translate --import-dxsa-bin %S/inputs/cast4.shex | FileCheck %s +// NOTE: Assertions have been autogenerated by utils/generate-test-checks.py + + +// CHECK-LABEL: dxsa.dcl_global_flags +// CHECK: dxsa.dcl_input_ps linear v<0, > +// CHECK: dxsa.dcl_output o<0, > +// CHECK: dxsa.ftou o<0, >, v<0, > +// CHECK: dxsa.instruction "ret" + diff --git a/mlir/test/Target/DXSA/hlsl/cast5.test b/mlir/test/Target/DXSA/hlsl/cast5.test new file mode 100644 index 000000000000..eb1abcfc9ff0 --- /dev/null +++ b/mlir/test/Target/DXSA/hlsl/cast5.test @@ -0,0 +1,14 @@ +// RUN: mlir-translate --import-dxsa-bin %S/inputs/cast5.shex | FileCheck %s +// NOTE: Assertions have been autogenerated by utils/generate-test-checks.py + + +// CHECK-LABEL: dxsa.dcl_global_flags +// CHECK: dxsa.dcl_input_ps linear v<0, min16f, > +// CHECK: dxsa.dcl_output o<0, > +// CHECK: %[[INDEX_0:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_0:.*]] = dxsa.operand %[[INDEX_0]] {mask = 16 : i32, num_components = 4 : i32, type = 2 : i32} +// CHECK: %[[INDEX_1:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_1:.*]] = dxsa.operand %[[INDEX_1]] {min_precision = 1 : i32, num_components = 4 : i32, one = 0 : i32, type = 1 : i32} +// CHECK: dxsa.instruction "mov" %[[OPERAND_0]], %[[OPERAND_1]] +// CHECK: dxsa.instruction "ret" + diff --git a/mlir/test/Target/DXSA/hlsl/cast6.test b/mlir/test/Target/DXSA/hlsl/cast6.test new file mode 100644 index 000000000000..f8c764a8ad13 --- /dev/null +++ b/mlir/test/Target/DXSA/hlsl/cast6.test @@ -0,0 +1,14 @@ +// RUN: mlir-translate --import-dxsa-bin %S/inputs/cast6.shex | FileCheck %s +// NOTE: Assertions have been autogenerated by utils/generate-test-checks.py + + +// CHECK-LABEL: dxsa.dcl_global_flags +// CHECK: dxsa.dcl_input_ps linear v<0, > +// CHECK: dxsa.dcl_output o<0, min16f, > +// CHECK: %[[INDEX_0:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_0:.*]] = dxsa.operand %[[INDEX_0]] {mask = 16 : i32, min_precision = 1 : i32, num_components = 4 : i32, type = 2 : i32} +// CHECK: %[[INDEX_1:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_1:.*]] = dxsa.operand %[[INDEX_1]] {num_components = 4 : i32, one = 0 : i32, type = 1 : i32} +// CHECK: dxsa.instruction "mov" %[[OPERAND_0]], %[[OPERAND_1]] +// CHECK: dxsa.instruction "ret" + diff --git a/mlir/test/Target/DXSA/hlsl/cbuffer1.50.test b/mlir/test/Target/DXSA/hlsl/cbuffer1.50.test new file mode 100644 index 000000000000..bb47f9904b5f --- /dev/null +++ b/mlir/test/Target/DXSA/hlsl/cbuffer1.50.test @@ -0,0 +1,15 @@ +// RUN: mlir-translate --import-dxsa-bin %S/inputs/cbuffer1.50.shex | FileCheck %s +// NOTE: Assertions have been autogenerated by utils/generate-test-checks.py + + +// CHECK-LABEL: dxsa.dcl_global_flags +// CHECK: dxsa.dcl_constant_buffer , +// CHECK: dxsa.dcl_output o<0> +// CHECK: %[[INDEX_0:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_0:.*]] = dxsa.operand %[[INDEX_0]] {mask = 240 : i32, num_components = 4 : i32, type = 2 : i32} +// CHECK: %[[INDEX_1:.*]] = dxsa.index.imm {imm = 5 : i32} +// CHECK: %[[INDEX_2:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_1:.*]] = dxsa.operand %[[INDEX_1]], %[[INDEX_2]] {num_components = 4 : i32, swizzle = dense<[0, 1, 2, 3]> : vector<4xi32>, type = 8 : i32} +// CHECK: dxsa.instruction "mov" %[[OPERAND_0]], %[[OPERAND_1]] +// CHECK: dxsa.instruction "ret" + diff --git a/mlir/test/Target/DXSA/hlsl/cbuffer1.51.test b/mlir/test/Target/DXSA/hlsl/cbuffer1.51.test new file mode 100644 index 000000000000..1f03d9b16f87 --- /dev/null +++ b/mlir/test/Target/DXSA/hlsl/cbuffer1.51.test @@ -0,0 +1,16 @@ +// RUN: mlir-translate --import-dxsa-bin %S/inputs/cbuffer1.51.shex | FileCheck %s +// NOTE: Assertions have been autogenerated by utils/generate-test-checks.py + + +// CHECK-LABEL: dxsa.dcl_global_flags +// CHECK: dxsa.dcl_constant_buffer , +// CHECK: dxsa.dcl_output o<0> +// CHECK: %[[INDEX_0:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_0:.*]] = dxsa.operand %[[INDEX_0]] {mask = 240 : i32, num_components = 4 : i32, type = 2 : i32} +// CHECK: %[[INDEX_1:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[INDEX_2:.*]] = dxsa.index.imm {imm = 5 : i32} +// CHECK: %[[INDEX_3:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_1:.*]] = dxsa.operand %[[INDEX_1]], %[[INDEX_2]], %[[INDEX_3]] {num_components = 4 : i32, swizzle = dense<[0, 1, 2, 3]> : vector<4xi32>, type = 8 : i32} +// CHECK: dxsa.instruction "mov" %[[OPERAND_0]], %[[OPERAND_1]] +// CHECK: dxsa.instruction "ret" + diff --git a/mlir/test/Target/DXSA/hlsl/cbuffer2.50.test b/mlir/test/Target/DXSA/hlsl/cbuffer2.50.test new file mode 100644 index 000000000000..6dcc15990f42 --- /dev/null +++ b/mlir/test/Target/DXSA/hlsl/cbuffer2.50.test @@ -0,0 +1,15 @@ +// RUN: mlir-translate --import-dxsa-bin %S/inputs/cbuffer2.50.shex | FileCheck %s +// NOTE: Assertions have been autogenerated by utils/generate-test-checks.py + + +// CHECK-LABEL: dxsa.dcl_global_flags +// CHECK: dxsa.dcl_constant_buffer , +// CHECK: dxsa.dcl_output o<0> +// CHECK: %[[INDEX_0:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_0:.*]] = dxsa.operand %[[INDEX_0]] {mask = 240 : i32, num_components = 4 : i32, type = 2 : i32} +// CHECK: %[[INDEX_1:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[INDEX_2:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_1:.*]] = dxsa.operand %[[INDEX_1]], %[[INDEX_2]] {num_components = 4 : i32, swizzle = dense<[3, 1, 1, 1]> : vector<4xi32>, type = 8 : i32} +// CHECK: dxsa.instruction "mov" %[[OPERAND_0]], %[[OPERAND_1]] +// CHECK: dxsa.instruction "ret" + diff --git a/mlir/test/Target/DXSA/hlsl/cbuffer2.51.test b/mlir/test/Target/DXSA/hlsl/cbuffer2.51.test new file mode 100644 index 000000000000..4bcb8351a9e2 --- /dev/null +++ b/mlir/test/Target/DXSA/hlsl/cbuffer2.51.test @@ -0,0 +1,16 @@ +// RUN: mlir-translate --import-dxsa-bin %S/inputs/cbuffer2.51.shex | FileCheck %s +// NOTE: Assertions have been autogenerated by utils/generate-test-checks.py + + +// CHECK-LABEL: dxsa.dcl_global_flags +// CHECK: dxsa.dcl_constant_buffer , +// CHECK: dxsa.dcl_output o<0> +// CHECK: %[[INDEX_0:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_0:.*]] = dxsa.operand %[[INDEX_0]] {mask = 240 : i32, num_components = 4 : i32, type = 2 : i32} +// CHECK: %[[INDEX_1:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[INDEX_2:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[INDEX_3:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_1:.*]] = dxsa.operand %[[INDEX_1]], %[[INDEX_2]], %[[INDEX_3]] {num_components = 4 : i32, swizzle = dense<[3, 1, 1, 1]> : vector<4xi32>, type = 8 : i32} +// CHECK: dxsa.instruction "mov" %[[OPERAND_0]], %[[OPERAND_1]] +// CHECK: dxsa.instruction "ret" + diff --git a/mlir/test/Target/DXSA/hlsl/cbuffer3.50.test b/mlir/test/Target/DXSA/hlsl/cbuffer3.50.test new file mode 100644 index 000000000000..bc1dd5d73bd6 --- /dev/null +++ b/mlir/test/Target/DXSA/hlsl/cbuffer3.50.test @@ -0,0 +1,33 @@ +// RUN: mlir-translate --import-dxsa-bin %S/inputs/cbuffer3.50.shex | FileCheck %s +// NOTE: Assertions have been autogenerated by utils/generate-test-checks.py + + +// CHECK-LABEL: dxsa.dcl_global_flags +// CHECK: dxsa.dcl_constant_buffer , +// CHECK: dxsa.dcl_constant_buffer , +// CHECK: dxsa.dcl_input_ps constant v<0, > +// CHECK: dxsa.dcl_output o<0> +// CHECK: dxsa.dcl_temps 1 +// CHECK: %[[INDEX_0:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_0:.*]] = dxsa.operand %[[INDEX_0]] {mask = 16 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_1:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_1:.*]] = dxsa.operand %[[INDEX_1]] {num_components = 4 : i32, one = 0 : i32, type = 1 : i32} +// CHECK: dxsa.instruction "mov" %[[OPERAND_0]], %[[OPERAND_1]] +// CHECK: %[[INDEX_2:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_2:.*]] = dxsa.operand %[[INDEX_2]] {mask = 16 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_3:.*]] = dxsa.index.imm {imm = 1 : i32} +// CHECK: %[[INDEX_4:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_3:.*]] = dxsa.operand %[[INDEX_4]] {num_components = 4 : i32, one = 0 : i32, type = 0 : i32} +// CHECK: %[[INDEX_5:.*]] = dxsa.index.rel %[[OPERAND_3]] +// CHECK: %[[OPERAND_4:.*]] = dxsa.operand %[[INDEX_3]], %[[INDEX_5]] {num_components = 4 : i32, one = 2 : i32, type = 8 : i32} +// CHECK: dxsa.instruction "mov" %[[OPERAND_2]], %[[OPERAND_4]] +// CHECK: %[[INDEX_6:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_5:.*]] = dxsa.operand %[[INDEX_6]] {mask = 240 : i32, num_components = 4 : i32, type = 2 : i32} +// CHECK: %[[INDEX_7:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[INDEX_8:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_6:.*]] = dxsa.operand %[[INDEX_8]] {num_components = 4 : i32, one = 0 : i32, type = 0 : i32} +// CHECK: %[[INDEX_9:.*]] = dxsa.index.rel %[[OPERAND_6]] +// CHECK: %[[OPERAND_7:.*]] = dxsa.operand %[[INDEX_7]], %[[INDEX_9]] {num_components = 4 : i32, swizzle = dense<[3, 1, 1, 1]> : vector<4xi32>, type = 8 : i32} +// CHECK: dxsa.instruction "mov" %[[OPERAND_5]], %[[OPERAND_7]] +// CHECK: dxsa.instruction "ret" + diff --git a/mlir/test/Target/DXSA/hlsl/cbuffer3.51.test b/mlir/test/Target/DXSA/hlsl/cbuffer3.51.test new file mode 100644 index 000000000000..2f8c9058af9e --- /dev/null +++ b/mlir/test/Target/DXSA/hlsl/cbuffer3.51.test @@ -0,0 +1,45 @@ +// RUN: mlir-translate --import-dxsa-bin %S/inputs/cbuffer3.51.shex | FileCheck %s +// NOTE: Assertions have been autogenerated by utils/generate-test-checks.py + + +// CHECK-LABEL: dxsa.dcl_global_flags +// CHECK: dxsa.dcl_constant_buffer , +// CHECK: dxsa.dcl_constant_buffer , +// CHECK: dxsa.dcl_input_ps constant v<0, > +// CHECK: dxsa.dcl_output o<0> +// CHECK: dxsa.dcl_temps 1 +// CHECK: %[[INDEX_0:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_0:.*]] = dxsa.operand %[[INDEX_0]] {mask = 16 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_1:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_1:.*]] = dxsa.operand %[[INDEX_1]] {num_components = 4 : i32, one = 2 : i32, type = 1 : i32} +// CHECK: %[[OPERAND_2:.*]] = dxsa.operand.imm {imm = dense<12> : vector<1xi32>} +// CHECK: dxsa.instruction "iadd" %[[OPERAND_0]], %[[OPERAND_1]], %[[OPERAND_2]] +// CHECK: %[[INDEX_2:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_3:.*]] = dxsa.operand %[[INDEX_2]] {mask = 96 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_3:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_4:.*]] = dxsa.operand %[[INDEX_3]] {num_components = 4 : i32, swizzle = dense<[1, 1, 0, 1]> : vector<4xi32>, type = 1 : i32} +// CHECK: dxsa.instruction "mov" %[[OPERAND_3]], %[[OPERAND_4]] +// CHECK: %[[INDEX_4:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_5:.*]] = dxsa.operand %[[INDEX_4]] {mask = 32 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_5:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[INDEX_6:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_6:.*]] = dxsa.operand %[[INDEX_6]] {num_components = 4 : i32, one = 2 : i32, type = 0 : i32} +// CHECK: %[[INDEX_7:.*]] = dxsa.index.rel.imm %[[OPERAND_6]] {imm = 17 : i32, op = "add"} +// CHECK: %[[INDEX_8:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_7:.*]] = dxsa.operand %[[INDEX_8]] {num_components = 4 : i32, one = 1 : i32, type = 0 : i32} +// CHECK: %[[INDEX_9:.*]] = dxsa.index.rel %[[OPERAND_7]] +// CHECK: %[[OPERAND_8:.*]] = dxsa.operand %[[INDEX_5]], %[[INDEX_7]], %[[INDEX_9]] {num_components = 4 : i32, one = 2 : i32, type = 8 : i32} +// CHECK: dxsa.instruction "mov" %[[OPERAND_5]], %[[OPERAND_8]] +// CHECK: %[[INDEX_10:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_9:.*]] = dxsa.operand %[[INDEX_10]] {mask = 240 : i32, num_components = 4 : i32, type = 2 : i32} +// CHECK: %[[INDEX_11:.*]] = dxsa.index.imm {imm = 1 : i32} +// CHECK: %[[INDEX_12:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_10:.*]] = dxsa.operand %[[INDEX_12]] {num_components = 4 : i32, one = 1 : i32, type = 0 : i32} +// CHECK: %[[INDEX_13:.*]] = dxsa.index.rel.imm %[[OPERAND_10]] {imm = 77 : i32, op = "add"} +// CHECK: %[[INDEX_14:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_11:.*]] = dxsa.operand %[[INDEX_14]] {num_components = 4 : i32, one = 0 : i32, type = 0 : i32} +// CHECK: %[[INDEX_15:.*]] = dxsa.index.rel %[[OPERAND_11]] +// CHECK: %[[OPERAND_12:.*]] = dxsa.operand %[[INDEX_11]], %[[INDEX_13]], %[[INDEX_15]] {num_components = 4 : i32, swizzle = dense<[3, 1, 1, 1]> : vector<4xi32>, type = 8 : i32} +// CHECK: dxsa.instruction "mov" %[[OPERAND_9]], %[[OPERAND_12]] +// CHECK: dxsa.instruction "ret" + diff --git a/mlir/test/Target/DXSA/hlsl/cmp1.test b/mlir/test/Target/DXSA/hlsl/cmp1.test new file mode 100644 index 000000000000..2f6548c3084c --- /dev/null +++ b/mlir/test/Target/DXSA/hlsl/cmp1.test @@ -0,0 +1,11 @@ +// RUN: mlir-translate --import-dxsa-bin %S/inputs/cmp1.shex | FileCheck %s +// NOTE: Assertions have been autogenerated by utils/generate-test-checks.py + + +// CHECK-LABEL: dxsa.dcl_global_flags +// CHECK: dxsa.dcl_input_ps linear v<0, > +// CHECK: dxsa.dcl_input_ps linear v<0, > +// CHECK: dxsa.dcl_output o<0, > +// CHECK: dxsa.eq o<0, >, v<0, >, v<0, > +// CHECK: dxsa.instruction "ret" + diff --git a/mlir/test/Target/DXSA/hlsl/constoperand1.test b/mlir/test/Target/DXSA/hlsl/constoperand1.test new file mode 100644 index 000000000000..72fefcdef7b9 --- /dev/null +++ b/mlir/test/Target/DXSA/hlsl/constoperand1.test @@ -0,0 +1,12 @@ +// RUN: mlir-translate --import-dxsa-bin %S/inputs/constoperand1.shex | FileCheck %s +// NOTE: Assertions have been autogenerated by utils/generate-test-checks.py + + +// CHECK-LABEL: dxsa.dcl_global_flags +// CHECK: dxsa.dcl_output_siv o<0>, +// CHECK: %[[INDEX_0:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_0:.*]] = dxsa.operand %[[INDEX_0]] {mask = 240 : i32, num_components = 4 : i32, type = 2 : i32} +// CHECK: %[[OPERAND_1:.*]] = dxsa.operand.imm {imm = dense<[1077936128, 0, 1056964608, 1039979355]> : vector<4xi32>} +// CHECK: dxsa.instruction "mov" %[[OPERAND_0]], %[[OPERAND_1]] +// CHECK: dxsa.instruction "ret" + diff --git a/mlir/test/Target/DXSA/hlsl/cs1.test b/mlir/test/Target/DXSA/hlsl/cs1.test new file mode 100644 index 000000000000..a0421cd28860 --- /dev/null +++ b/mlir/test/Target/DXSA/hlsl/cs1.test @@ -0,0 +1,46 @@ +// RUN: mlir-translate --import-dxsa-bin %S/inputs/cs1.shex | FileCheck %s +// NOTE: Assertions have been autogenerated by utils/generate-test-checks.py + + +// CHECK-LABEL: dxsa.dcl_global_flags +// CHECK: dxsa.dcl_uav_raw +// CHECK: dxsa.dcl_input vThreadIDInGroupFlattened +// CHECK: dxsa.dcl_input vThreadGroupID<> +// CHECK: dxsa.dcl_input vThreadIDInGroup<> +// CHECK: dxsa.dcl_input vThreadID<> +// CHECK: dxsa.dcl_temps 1 +// CHECK: dxsa.dcl_thread_group +// CHECK: dxsa.ishl r<0, >, vThreadID<>, l(0x7) +// CHECK: dxsa.ishl r<0, >, vThreadGroupID<>, l(0xA) +// CHECK: %[[INDEX_0:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_0:.*]] = dxsa.operand %[[INDEX_0]] {mask = 16 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_1:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_1:.*]] = dxsa.operand %[[INDEX_1]] {num_components = 4 : i32, one = 1 : i32, type = 0 : i32} +// CHECK: %[[INDEX_2:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_2:.*]] = dxsa.operand %[[INDEX_2]] {num_components = 4 : i32, one = 0 : i32, type = 0 : i32} +// CHECK: dxsa.instruction "iadd" %[[OPERAND_0]], %[[OPERAND_1]], %[[OPERAND_2]] +// CHECK: %[[INDEX_3:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_3:.*]] = dxsa.operand %[[INDEX_3]] {mask = 16 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_4:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_4:.*]] = dxsa.operand %[[INDEX_4]] {num_components = 4 : i32, one = 0 : i32, type = 0 : i32} +// CHECK: %[[OPERAND_5:.*]] = dxsa.operand {num_components = 4 : i32, one = 2 : i32, type = 34 : i32} +// CHECK: dxsa.instruction "iadd" %[[OPERAND_3]], %[[OPERAND_4]], %[[OPERAND_5]] +// CHECK: %[[INDEX_5:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_6:.*]] = dxsa.operand %[[INDEX_5]] {mask = 16 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_6:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_7:.*]] = dxsa.operand %[[INDEX_6]] {num_components = 4 : i32, one = 0 : i32, type = 0 : i32} +// CHECK: %[[OPERAND_8:.*]] = dxsa.operand {num_components = 4 : i32, one = 0 : i32, type = 36 : i32} +// CHECK: dxsa.instruction "iadd" %[[OPERAND_6]], %[[OPERAND_7]], %[[OPERAND_8]] +// CHECK: dxsa.unknown +// CHECK: dxsa.add r<0, >, r<0, >, l(0x40400000) +// CHECK: dxsa.instruction "sync" +// CHECK: %[[INDEX_7:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_9:.*]] = dxsa.operand %[[INDEX_7]] {mask = 16 : i32, num_components = 4 : i32, type = 30 : i32} +// CHECK: %[[INDEX_8:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_10:.*]] = dxsa.operand %[[INDEX_8]] {num_components = 4 : i32, one = 0 : i32, type = 0 : i32} +// CHECK: %[[INDEX_9:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_11:.*]] = dxsa.operand %[[INDEX_9]] {num_components = 4 : i32, one = 1 : i32, type = 0 : i32} +// CHECK: dxsa.instruction "store_raw" %[[OPERAND_9]], %[[OPERAND_10]], %[[OPERAND_11]] +// CHECK: dxsa.instruction "sync" +// CHECK: dxsa.instruction "ret" + diff --git a/mlir/test/Target/DXSA/hlsl/cs2.test b/mlir/test/Target/DXSA/hlsl/cs2.test new file mode 100644 index 000000000000..03b99ca7eefd --- /dev/null +++ b/mlir/test/Target/DXSA/hlsl/cs2.test @@ -0,0 +1,106 @@ +// RUN: mlir-translate --import-dxsa-bin %S/inputs/cs2.shex | FileCheck %s +// NOTE: Assertions have been autogenerated by utils/generate-test-checks.py + + +// CHECK-LABEL: dxsa.dcl_global_flags +// CHECK: dxsa.dcl_constant_buffer , +// CHECK: dxsa.dcl_uav_raw +// CHECK: dxsa.dcl_input vThreadIDInGroupFlattened +// CHECK: dxsa.dcl_input vThreadGroupID<> +// CHECK: dxsa.dcl_input vThreadIDInGroup<> +// CHECK: dxsa.dcl_input vThreadID<> +// CHECK: dxsa.dcl_temps 3 +// CHECK: dxsa.dcl_tgsm_structured g<0>, 16, 384 +// CHECK: dxsa.dcl_thread_group +// CHECK: dxsa.ishl r<0, >, vThreadID<>, l(0x7) +// CHECK: dxsa.ishl r<0, >, vThreadGroupID<>, l(0xA) +// CHECK: %[[INDEX_0:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_0:.*]] = dxsa.operand %[[INDEX_0]] {mask = 16 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_1:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_1:.*]] = dxsa.operand %[[INDEX_1]] {num_components = 4 : i32, one = 1 : i32, type = 0 : i32} +// CHECK: %[[INDEX_2:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_2:.*]] = dxsa.operand %[[INDEX_2]] {num_components = 4 : i32, one = 0 : i32, type = 0 : i32} +// CHECK: dxsa.instruction "iadd" %[[OPERAND_0]], %[[OPERAND_1]], %[[OPERAND_2]] +// CHECK: %[[INDEX_3:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_3:.*]] = dxsa.operand %[[INDEX_3]] {mask = 16 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_4:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_4:.*]] = dxsa.operand %[[INDEX_4]] {num_components = 4 : i32, one = 0 : i32, type = 0 : i32} +// CHECK: %[[OPERAND_5:.*]] = dxsa.operand {num_components = 4 : i32, one = 2 : i32, type = 34 : i32} +// CHECK: dxsa.instruction "iadd" %[[OPERAND_3]], %[[OPERAND_4]], %[[OPERAND_5]] +// CHECK: %[[INDEX_5:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_6:.*]] = dxsa.operand %[[INDEX_5]] {mask = 16 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_6:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_7:.*]] = dxsa.operand %[[INDEX_6]] {num_components = 4 : i32, one = 0 : i32, type = 0 : i32} +// CHECK: %[[OPERAND_8:.*]] = dxsa.operand {num_components = 4 : i32, one = 0 : i32, type = 36 : i32} +// CHECK: dxsa.instruction "iadd" %[[OPERAND_6]], %[[OPERAND_7]], %[[OPERAND_8]] +// CHECK: dxsa.unknown +// CHECK: dxsa.add r<1, min16f, >, r<0, >, l(0x40000000) +// CHECK: %[[INDEX_7:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_9:.*]] = dxsa.operand %[[INDEX_7]] {mask = 16 : i32, num_components = 4 : i32, type = 31 : i32} +// CHECK: %[[OPERAND_10:.*]] = dxsa.operand {num_components = 4 : i32, one = 0 : i32, type = 36 : i32} +// CHECK: %[[OPERAND_11:.*]] = dxsa.operand.imm {imm = dense<4> : vector<1xi32>} +// CHECK: %[[INDEX_8:.*]] = dxsa.index.imm {imm = 1 : i32} +// CHECK: %[[OPERAND_12:.*]] = dxsa.operand %[[INDEX_8]] {min_precision = 1 : i32, num_components = 4 : i32, one = 0 : i32, type = 0 : i32} +// CHECK: dxsa.instruction "store_structured" %[[OPERAND_9]], %[[OPERAND_10]], %[[OPERAND_11]], %[[OPERAND_12]] +// CHECK: %[[INDEX_9:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_13:.*]] = dxsa.operand %[[INDEX_9]] {mask = 16 : i32, num_components = 4 : i32, type = 31 : i32} +// CHECK: %[[OPERAND_14:.*]] = dxsa.operand {num_components = 4 : i32, one = 0 : i32, type = 36 : i32} +// CHECK: %[[OPERAND_15:.*]] = dxsa.operand.imm {imm = dense<8> : vector<1xi32>} +// CHECK: %[[INDEX_10:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_16:.*]] = dxsa.operand %[[INDEX_10]] {num_components = 4 : i32, one = 1 : i32, type = 0 : i32} +// CHECK: dxsa.instruction "store_structured" %[[OPERAND_13]], %[[OPERAND_14]], %[[OPERAND_15]], %[[OPERAND_16]] +// CHECK: dxsa.ftoi r<2, min16i, >, r<0, > +// CHECK: %[[INDEX_11:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_17:.*]] = dxsa.operand %[[INDEX_11]] {mask = 16 : i32, num_components = 4 : i32, type = 31 : i32} +// CHECK: %[[OPERAND_18:.*]] = dxsa.operand {num_components = 4 : i32, one = 0 : i32, type = 36 : i32} +// CHECK: %[[OPERAND_19:.*]] = dxsa.operand.imm {imm = dense<12> : vector<1xi32>} +// CHECK: %[[INDEX_12:.*]] = dxsa.index.imm {imm = 2 : i32} +// CHECK: %[[OPERAND_20:.*]] = dxsa.operand %[[INDEX_12]] {min_precision = 4 : i32, num_components = 4 : i32, one = 0 : i32, type = 0 : i32} +// CHECK: dxsa.instruction "store_structured" %[[OPERAND_17]], %[[OPERAND_18]], %[[OPERAND_19]], %[[OPERAND_20]] +// CHECK: dxsa.instruction "sync" +// CHECK: %[[INDEX_13:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_21:.*]] = dxsa.operand %[[INDEX_13]] {mask = 64 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[OPERAND_22:.*]] = dxsa.operand {num_components = 4 : i32, one = 0 : i32, type = 36 : i32} +// CHECK: %[[INDEX_14:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[INDEX_15:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_23:.*]] = dxsa.operand %[[INDEX_14]], %[[INDEX_15]] {num_components = 4 : i32, one = 0 : i32, type = 8 : i32} +// CHECK: dxsa.instruction "iadd" %[[OPERAND_21]], %[[OPERAND_22]], %[[OPERAND_23]] +// CHECK: %[[INDEX_16:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_24:.*]] = dxsa.operand %[[INDEX_16]] {mask = 128 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_17:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_25:.*]] = dxsa.operand %[[INDEX_17]] {num_components = 4 : i32, one = 2 : i32, type = 0 : i32} +// CHECK: %[[OPERAND_26:.*]] = dxsa.operand.imm {imm = dense<8> : vector<1xi32>} +// CHECK: %[[INDEX_18:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_27:.*]] = dxsa.operand %[[INDEX_18]] {num_components = 4 : i32, swizzle = dense<0> : vector<4xi32>, type = 31 : i32} +// CHECK: dxsa.instruction "ld_structured" %[[OPERAND_24]], %[[OPERAND_25]], %[[OPERAND_26]], %[[OPERAND_27]] +// CHECK: dxsa.add r<0, >, r<0, >, r<0, > +// CHECK: %[[INDEX_19:.*]] = dxsa.index.imm {imm = 2 : i32} +// CHECK: %[[OPERAND_28:.*]] = dxsa.operand %[[INDEX_19]] {mask = 16 : i32, min_precision = 4 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_20:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_29:.*]] = dxsa.operand %[[INDEX_20]] {num_components = 4 : i32, one = 2 : i32, type = 0 : i32} +// CHECK: %[[OPERAND_30:.*]] = dxsa.operand.imm {imm = dense<12> : vector<1xi32>} +// CHECK: %[[INDEX_21:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_31:.*]] = dxsa.operand %[[INDEX_21]] {num_components = 4 : i32, swizzle = dense<0> : vector<4xi32>, type = 31 : i32} +// CHECK: dxsa.instruction "ld_structured" %[[OPERAND_28]], %[[OPERAND_29]], %[[OPERAND_30]], %[[OPERAND_31]] +// CHECK: dxsa.itof r<0, >, r<2, min16i, > +// CHECK: dxsa.add r<0, >, r<0, >, r<0, > +// CHECK: dxsa.instruction "sync" +// CHECK: dxsa.instruction "sync" +// CHECK: %[[INDEX_22:.*]] = dxsa.index.imm {imm = 1 : i32} +// CHECK: %[[OPERAND_32:.*]] = dxsa.operand %[[INDEX_22]] {mask = 16 : i32, min_precision = 1 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_23:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_33:.*]] = dxsa.operand %[[INDEX_23]] {num_components = 4 : i32, one = 2 : i32, type = 0 : i32} +// CHECK: %[[OPERAND_34:.*]] = dxsa.operand.imm {imm = dense<4> : vector<1xi32>} +// CHECK: %[[INDEX_24:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_35:.*]] = dxsa.operand %[[INDEX_24]] {num_components = 4 : i32, swizzle = dense<0> : vector<4xi32>, type = 31 : i32} +// CHECK: dxsa.instruction "ld_structured" %[[OPERAND_32]], %[[OPERAND_33]], %[[OPERAND_34]], %[[OPERAND_35]] +// CHECK: dxsa.add r<0, >, r<0, >, r<1, min16f, > +// CHECK: %[[INDEX_25:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_36:.*]] = dxsa.operand %[[INDEX_25]] {mask = 16 : i32, num_components = 4 : i32, type = 30 : i32} +// CHECK: %[[INDEX_26:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_37:.*]] = dxsa.operand %[[INDEX_26]] {num_components = 4 : i32, one = 0 : i32, type = 0 : i32} +// CHECK: %[[INDEX_27:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_38:.*]] = dxsa.operand %[[INDEX_27]] {num_components = 4 : i32, one = 1 : i32, type = 0 : i32} +// CHECK: dxsa.instruction "store_raw" %[[OPERAND_36]], %[[OPERAND_37]], %[[OPERAND_38]] +// CHECK: dxsa.instruction "ret" + diff --git a/mlir/test/Target/DXSA/hlsl/cs4.test b/mlir/test/Target/DXSA/hlsl/cs4.test new file mode 100644 index 000000000000..74aea79d045b --- /dev/null +++ b/mlir/test/Target/DXSA/hlsl/cs4.test @@ -0,0 +1,113 @@ +// RUN: mlir-translate --import-dxsa-bin %S/inputs/cs4.shex | FileCheck %s +// NOTE: Assertions have been autogenerated by utils/generate-test-checks.py + + +// CHECK-LABEL: dxsa.dcl_global_flags +// CHECK: dxsa.dcl_constant_buffer , +// CHECK: dxsa.dcl_uav_raw +// CHECK: dxsa.dcl_input vThreadIDInGroupFlattened +// CHECK: dxsa.dcl_input vThreadGroupID<> +// CHECK: dxsa.dcl_input vThreadIDInGroup<> +// CHECK: dxsa.dcl_input vThreadID<> +// CHECK: dxsa.dcl_temps 3 +// CHECK: dxsa.dcl_tgsm_structured g<0>, 20, 384 +// CHECK: dxsa.dcl_thread_group +// CHECK: dxsa.ishl r<0, >, vThreadID<>, l(0x7) +// CHECK: dxsa.ishl r<0, >, vThreadGroupID<>, l(0xA) +// CHECK: %[[INDEX_0:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_0:.*]] = dxsa.operand %[[INDEX_0]] {mask = 16 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_1:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_1:.*]] = dxsa.operand %[[INDEX_1]] {num_components = 4 : i32, one = 1 : i32, type = 0 : i32} +// CHECK: %[[INDEX_2:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_2:.*]] = dxsa.operand %[[INDEX_2]] {num_components = 4 : i32, one = 0 : i32, type = 0 : i32} +// CHECK: dxsa.instruction "iadd" %[[OPERAND_0]], %[[OPERAND_1]], %[[OPERAND_2]] +// CHECK: %[[INDEX_3:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_3:.*]] = dxsa.operand %[[INDEX_3]] {mask = 16 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_4:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_4:.*]] = dxsa.operand %[[INDEX_4]] {num_components = 4 : i32, one = 0 : i32, type = 0 : i32} +// CHECK: %[[OPERAND_5:.*]] = dxsa.operand {num_components = 4 : i32, one = 2 : i32, type = 34 : i32} +// CHECK: dxsa.instruction "iadd" %[[OPERAND_3]], %[[OPERAND_4]], %[[OPERAND_5]] +// CHECK: %[[INDEX_5:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_6:.*]] = dxsa.operand %[[INDEX_5]] {mask = 16 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_6:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_7:.*]] = dxsa.operand %[[INDEX_6]] {num_components = 4 : i32, one = 0 : i32, type = 0 : i32} +// CHECK: %[[OPERAND_8:.*]] = dxsa.operand {num_components = 4 : i32, one = 0 : i32, type = 36 : i32} +// CHECK: dxsa.instruction "iadd" %[[OPERAND_6]], %[[OPERAND_7]], %[[OPERAND_8]] +// CHECK: dxsa.unknown +// CHECK: dxsa.ftou r<0, >, r<0, > +// CHECK: %[[INDEX_7:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_9:.*]] = dxsa.operand %[[INDEX_7]] {mask = 16 : i32, num_components = 4 : i32, type = 31 : i32} +// CHECK: %[[OPERAND_10:.*]] = dxsa.operand {num_components = 4 : i32, one = 0 : i32, type = 36 : i32} +// CHECK: %[[OPERAND_11:.*]] = dxsa.operand.imm {imm = dense<16> : vector<1xi32>} +// CHECK: %[[INDEX_8:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_12:.*]] = dxsa.operand %[[INDEX_8]] {num_components = 4 : i32, one = 2 : i32, type = 0 : i32} +// CHECK: dxsa.instruction "store_structured" %[[OPERAND_9]], %[[OPERAND_10]], %[[OPERAND_11]], %[[OPERAND_12]] +// CHECK: %[[INDEX_9:.*]] = dxsa.index.imm {imm = 1 : i32} +// CHECK: %[[OPERAND_13:.*]] = dxsa.operand %[[INDEX_9]] {mask = 16 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[OPERAND_14:.*]] = dxsa.operand {num_components = 4 : i32, one = 0 : i32, type = 36 : i32} +// CHECK: dxsa.instruction "mov" %[[OPERAND_13]], %[[OPERAND_14]] +// CHECK: %[[INDEX_10:.*]] = dxsa.index.imm {imm = 1 : i32} +// CHECK: %[[OPERAND_15:.*]] = dxsa.operand %[[INDEX_10]] {mask = 32 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[OPERAND_16:.*]] = dxsa.operand.imm {imm = dense<16> : vector<1xi32>} +// CHECK: dxsa.instruction "mov" %[[OPERAND_15]], %[[OPERAND_16]] +// CHECK: %[[INDEX_11:.*]] = dxsa.index.imm {imm = 2 : i32} +// CHECK: %[[OPERAND_17:.*]] = dxsa.operand %[[INDEX_11]] {mask = 16 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_12:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_18:.*]] = dxsa.operand %[[INDEX_12]] {num_components = 0 : i32, type = 31 : i32} +// CHECK: %[[INDEX_13:.*]] = dxsa.index.imm {imm = 1 : i32} +// CHECK: %[[OPERAND_19:.*]] = dxsa.operand %[[INDEX_13]] {num_components = 4 : i32, swizzle = dense<[0, 1, 0, 0]> : vector<4xi32>, type = 0 : i32} +// CHECK: %[[OPERAND_20:.*]] = dxsa.operand {num_components = 4 : i32, one = 0 : i32, type = 32 : i32} +// CHECK: dxsa.instruction "imm_atomic_iadd" %[[OPERAND_17]], %[[OPERAND_18]], %[[OPERAND_19]], %[[OPERAND_20]] +// CHECK: %[[INDEX_14:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_21:.*]] = dxsa.operand %[[INDEX_14]] {num_components = 0 : i32, type = 31 : i32} +// CHECK: %[[INDEX_15:.*]] = dxsa.index.imm {imm = 1 : i32} +// CHECK: %[[OPERAND_22:.*]] = dxsa.operand %[[INDEX_15]] {num_components = 4 : i32, swizzle = dense<[0, 1, 0, 0]> : vector<4xi32>, type = 0 : i32} +// CHECK: %[[OPERAND_23:.*]] = dxsa.operand {num_components = 4 : i32, one = 0 : i32, type = 32 : i32} +// CHECK: dxsa.instruction "atomic_or" %[[OPERAND_21]], %[[OPERAND_22]], %[[OPERAND_23]] +// CHECK: dxsa.utof r<0, >, r<2, > +// CHECK: dxsa.add r<0, >, r<0, >, r<0, > +// CHECK: %[[INDEX_16:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_24:.*]] = dxsa.operand %[[INDEX_16]] {num_components = 0 : i32, type = 31 : i32} +// CHECK: %[[INDEX_17:.*]] = dxsa.index.imm {imm = 1 : i32} +// CHECK: %[[OPERAND_25:.*]] = dxsa.operand %[[INDEX_17]] {num_components = 4 : i32, swizzle = dense<[0, 1, 0, 0]> : vector<4xi32>, type = 0 : i32} +// CHECK: %[[OPERAND_26:.*]] = dxsa.operand {num_components = 4 : i32, one = 1 : i32, type = 33 : i32} +// CHECK: %[[OPERAND_27:.*]] = dxsa.operand {num_components = 4 : i32, one = 0 : i32, type = 32 : i32} +// CHECK: dxsa.instruction "atomic_cmp_store" %[[OPERAND_24]], %[[OPERAND_25]], %[[OPERAND_26]], %[[OPERAND_27]] +// CHECK: %[[INDEX_18:.*]] = dxsa.index.imm {imm = 1 : i32} +// CHECK: %[[OPERAND_28:.*]] = dxsa.operand %[[INDEX_18]] {mask = 16 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_19:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_29:.*]] = dxsa.operand %[[INDEX_19]] {num_components = 0 : i32, type = 31 : i32} +// CHECK: %[[INDEX_20:.*]] = dxsa.index.imm {imm = 1 : i32} +// CHECK: %[[OPERAND_30:.*]] = dxsa.operand %[[INDEX_20]] {num_components = 4 : i32, swizzle = dense<[0, 1, 0, 0]> : vector<4xi32>, type = 0 : i32} +// CHECK: %[[OPERAND_31:.*]] = dxsa.operand {num_components = 4 : i32, one = 1 : i32, type = 33 : i32} +// CHECK: %[[OPERAND_32:.*]] = dxsa.operand {num_components = 4 : i32, one = 0 : i32, type = 32 : i32} +// CHECK: dxsa.instruction "imm_atomic_cmp_exch" %[[OPERAND_28]], %[[OPERAND_29]], %[[OPERAND_30]], %[[OPERAND_31]], %[[OPERAND_32]] +// CHECK: dxsa.instruction "sync" +// CHECK: dxsa.utof r<0, >, r<1, > +// CHECK: dxsa.add r<0, >, r<0, >, r<0, > +// CHECK: %[[INDEX_21:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_33:.*]] = dxsa.operand %[[INDEX_21]] {mask = 64 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[OPERAND_34:.*]] = dxsa.operand {num_components = 4 : i32, one = 0 : i32, type = 36 : i32} +// CHECK: %[[INDEX_22:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[INDEX_23:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_35:.*]] = dxsa.operand %[[INDEX_22]], %[[INDEX_23]] {num_components = 4 : i32, one = 0 : i32, type = 8 : i32} +// CHECK: dxsa.instruction "iadd" %[[OPERAND_33]], %[[OPERAND_34]], %[[OPERAND_35]] +// CHECK: %[[INDEX_24:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_36:.*]] = dxsa.operand %[[INDEX_24]] {mask = 64 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_25:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_37:.*]] = dxsa.operand %[[INDEX_25]] {num_components = 4 : i32, one = 2 : i32, type = 0 : i32} +// CHECK: %[[OPERAND_38:.*]] = dxsa.operand.imm {imm = dense<16> : vector<1xi32>} +// CHECK: %[[INDEX_26:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_39:.*]] = dxsa.operand %[[INDEX_26]] {num_components = 4 : i32, swizzle = dense<0> : vector<4xi32>, type = 31 : i32} +// CHECK: dxsa.instruction "ld_structured" %[[OPERAND_36]], %[[OPERAND_37]], %[[OPERAND_38]], %[[OPERAND_39]] +// CHECK: dxsa.utof r<0, >, r<0, > +// CHECK: dxsa.add r<0, >, r<0, >, r<0, > +// CHECK: %[[INDEX_27:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_40:.*]] = dxsa.operand %[[INDEX_27]] {mask = 16 : i32, num_components = 4 : i32, type = 30 : i32} +// CHECK: %[[INDEX_28:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_41:.*]] = dxsa.operand %[[INDEX_28]] {num_components = 4 : i32, one = 0 : i32, type = 0 : i32} +// CHECK: %[[INDEX_29:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_42:.*]] = dxsa.operand %[[INDEX_29]] {num_components = 4 : i32, one = 1 : i32, type = 0 : i32} +// CHECK: dxsa.instruction "store_raw" %[[OPERAND_40]], %[[OPERAND_41]], %[[OPERAND_42]] +// CHECK: dxsa.instruction "ret" + diff --git a/mlir/test/Target/DXSA/hlsl/cs5.test b/mlir/test/Target/DXSA/hlsl/cs5.test new file mode 100644 index 000000000000..b23cd681146a --- /dev/null +++ b/mlir/test/Target/DXSA/hlsl/cs5.test @@ -0,0 +1,106 @@ +// RUN: mlir-translate --import-dxsa-bin %S/inputs/cs5.shex | FileCheck %s +// NOTE: Assertions have been autogenerated by utils/generate-test-checks.py + + +// CHECK-LABEL: dxsa.dcl_global_flags +// CHECK: dxsa.dcl_constant_buffer , +// CHECK: dxsa.dcl_uav_raw +// CHECK: dxsa.dcl_input vThreadIDInGroupFlattened +// CHECK: dxsa.dcl_input vThreadGroupID<> +// CHECK: dxsa.dcl_input vThreadIDInGroup<> +// CHECK: dxsa.dcl_input vThreadID<> +// CHECK: dxsa.dcl_temps 3 +// CHECK: dxsa.dcl_tgsm_structured g<0>, 16, 384 +// CHECK: dxsa.dcl_thread_group +// CHECK: dxsa.ishl r<0, >, vThreadID<>, l(0x7) +// CHECK: dxsa.ishl r<0, >, vThreadGroupID<>, l(0xA) +// CHECK: %[[INDEX_0:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_0:.*]] = dxsa.operand %[[INDEX_0]] {mask = 16 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_1:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_1:.*]] = dxsa.operand %[[INDEX_1]] {num_components = 4 : i32, one = 1 : i32, type = 0 : i32} +// CHECK: %[[INDEX_2:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_2:.*]] = dxsa.operand %[[INDEX_2]] {num_components = 4 : i32, one = 0 : i32, type = 0 : i32} +// CHECK: dxsa.instruction "iadd" %[[OPERAND_0]], %[[OPERAND_1]], %[[OPERAND_2]] +// CHECK: %[[INDEX_3:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_3:.*]] = dxsa.operand %[[INDEX_3]] {mask = 16 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_4:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_4:.*]] = dxsa.operand %[[INDEX_4]] {num_components = 4 : i32, one = 0 : i32, type = 0 : i32} +// CHECK: %[[OPERAND_5:.*]] = dxsa.operand {num_components = 4 : i32, one = 2 : i32, type = 34 : i32} +// CHECK: dxsa.instruction "iadd" %[[OPERAND_3]], %[[OPERAND_4]], %[[OPERAND_5]] +// CHECK: %[[INDEX_5:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_6:.*]] = dxsa.operand %[[INDEX_5]] {mask = 16 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_6:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_7:.*]] = dxsa.operand %[[INDEX_6]] {num_components = 4 : i32, one = 0 : i32, type = 0 : i32} +// CHECK: %[[OPERAND_8:.*]] = dxsa.operand {num_components = 4 : i32, one = 0 : i32, type = 36 : i32} +// CHECK: dxsa.instruction "iadd" %[[OPERAND_6]], %[[OPERAND_7]], %[[OPERAND_8]] +// CHECK: dxsa.unknown +// CHECK: dxsa.add r<1, min16f, >, r<0, >, l(0x40000000) +// CHECK: %[[INDEX_7:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_9:.*]] = dxsa.operand %[[INDEX_7]] {mask = 16 : i32, num_components = 4 : i32, type = 31 : i32} +// CHECK: %[[OPERAND_10:.*]] = dxsa.operand {num_components = 4 : i32, one = 0 : i32, type = 36 : i32} +// CHECK: %[[OPERAND_11:.*]] = dxsa.operand.imm {imm = dense<4> : vector<1xi32>} +// CHECK: %[[INDEX_8:.*]] = dxsa.index.imm {imm = 1 : i32} +// CHECK: %[[OPERAND_12:.*]] = dxsa.operand %[[INDEX_8]] {min_precision = 1 : i32, num_components = 4 : i32, one = 0 : i32, type = 0 : i32} +// CHECK: dxsa.instruction "store_structured" %[[OPERAND_9]], %[[OPERAND_10]], %[[OPERAND_11]], %[[OPERAND_12]] +// CHECK: %[[INDEX_9:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_13:.*]] = dxsa.operand %[[INDEX_9]] {mask = 16 : i32, num_components = 4 : i32, type = 31 : i32} +// CHECK: %[[OPERAND_14:.*]] = dxsa.operand {num_components = 4 : i32, one = 0 : i32, type = 36 : i32} +// CHECK: %[[OPERAND_15:.*]] = dxsa.operand.imm {imm = dense<8> : vector<1xi32>} +// CHECK: %[[INDEX_10:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_16:.*]] = dxsa.operand %[[INDEX_10]] {num_components = 4 : i32, one = 1 : i32, type = 0 : i32} +// CHECK: dxsa.instruction "store_structured" %[[OPERAND_13]], %[[OPERAND_14]], %[[OPERAND_15]], %[[OPERAND_16]] +// CHECK: dxsa.ftoi r<2, min16i, >, r<0, > +// CHECK: %[[INDEX_11:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_17:.*]] = dxsa.operand %[[INDEX_11]] {mask = 16 : i32, num_components = 4 : i32, type = 31 : i32} +// CHECK: %[[OPERAND_18:.*]] = dxsa.operand {num_components = 4 : i32, one = 0 : i32, type = 36 : i32} +// CHECK: %[[OPERAND_19:.*]] = dxsa.operand.imm {imm = dense<12> : vector<1xi32>} +// CHECK: %[[INDEX_12:.*]] = dxsa.index.imm {imm = 2 : i32} +// CHECK: %[[OPERAND_20:.*]] = dxsa.operand %[[INDEX_12]] {min_precision = 4 : i32, num_components = 4 : i32, one = 0 : i32, type = 0 : i32} +// CHECK: dxsa.instruction "store_structured" %[[OPERAND_17]], %[[OPERAND_18]], %[[OPERAND_19]], %[[OPERAND_20]] +// CHECK: dxsa.instruction "sync" +// CHECK: %[[INDEX_13:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_21:.*]] = dxsa.operand %[[INDEX_13]] {mask = 64 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[OPERAND_22:.*]] = dxsa.operand {num_components = 4 : i32, one = 0 : i32, type = 36 : i32} +// CHECK: %[[INDEX_14:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[INDEX_15:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_23:.*]] = dxsa.operand %[[INDEX_14]], %[[INDEX_15]] {num_components = 4 : i32, one = 0 : i32, type = 8 : i32} +// CHECK: dxsa.instruction "iadd" %[[OPERAND_21]], %[[OPERAND_22]], %[[OPERAND_23]] +// CHECK: %[[INDEX_16:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_24:.*]] = dxsa.operand %[[INDEX_16]] {mask = 128 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_17:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_25:.*]] = dxsa.operand %[[INDEX_17]] {num_components = 4 : i32, one = 2 : i32, type = 0 : i32} +// CHECK: %[[OPERAND_26:.*]] = dxsa.operand.imm {imm = dense<8> : vector<1xi32>} +// CHECK: %[[INDEX_18:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_27:.*]] = dxsa.operand %[[INDEX_18]] {num_components = 4 : i32, swizzle = dense<0> : vector<4xi32>, type = 31 : i32} +// CHECK: dxsa.instruction "ld_structured" %[[OPERAND_24]], %[[OPERAND_25]], %[[OPERAND_26]], %[[OPERAND_27]] +// CHECK: dxsa.add r<0, >, r<0, >, r<0, > +// CHECK: %[[INDEX_19:.*]] = dxsa.index.imm {imm = 2 : i32} +// CHECK: %[[OPERAND_28:.*]] = dxsa.operand %[[INDEX_19]] {mask = 16 : i32, min_precision = 4 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_20:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_29:.*]] = dxsa.operand %[[INDEX_20]] {num_components = 4 : i32, one = 2 : i32, type = 0 : i32} +// CHECK: %[[OPERAND_30:.*]] = dxsa.operand.imm {imm = dense<12> : vector<1xi32>} +// CHECK: %[[INDEX_21:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_31:.*]] = dxsa.operand %[[INDEX_21]] {num_components = 4 : i32, swizzle = dense<0> : vector<4xi32>, type = 31 : i32} +// CHECK: dxsa.instruction "ld_structured" %[[OPERAND_28]], %[[OPERAND_29]], %[[OPERAND_30]], %[[OPERAND_31]] +// CHECK: dxsa.itof r<0, >, r<2, min16i, > +// CHECK: dxsa.add r<0, >, r<0, >, r<0, > +// CHECK: dxsa.instruction "sync" +// CHECK: dxsa.instruction "sync" +// CHECK: %[[INDEX_22:.*]] = dxsa.index.imm {imm = 1 : i32} +// CHECK: %[[OPERAND_32:.*]] = dxsa.operand %[[INDEX_22]] {mask = 16 : i32, min_precision = 1 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_23:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_33:.*]] = dxsa.operand %[[INDEX_23]] {num_components = 4 : i32, one = 2 : i32, type = 0 : i32} +// CHECK: %[[OPERAND_34:.*]] = dxsa.operand.imm {imm = dense<4> : vector<1xi32>} +// CHECK: %[[INDEX_24:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_35:.*]] = dxsa.operand %[[INDEX_24]] {num_components = 4 : i32, swizzle = dense<0> : vector<4xi32>, type = 31 : i32} +// CHECK: dxsa.instruction "ld_structured" %[[OPERAND_32]], %[[OPERAND_33]], %[[OPERAND_34]], %[[OPERAND_35]] +// CHECK: dxsa.add r<0, >, r<0, >, r<1, min16f, > +// CHECK: %[[INDEX_25:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_36:.*]] = dxsa.operand %[[INDEX_25]] {mask = 16 : i32, num_components = 4 : i32, type = 30 : i32} +// CHECK: %[[INDEX_26:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_37:.*]] = dxsa.operand %[[INDEX_26]] {num_components = 4 : i32, one = 0 : i32, type = 0 : i32} +// CHECK: %[[INDEX_27:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_38:.*]] = dxsa.operand %[[INDEX_27]] {num_components = 4 : i32, one = 1 : i32, type = 0 : i32} +// CHECK: dxsa.instruction "store_raw" %[[OPERAND_36]], %[[OPERAND_37]], %[[OPERAND_38]] +// CHECK: dxsa.instruction "ret" + diff --git a/mlir/test/Target/DXSA/hlsl/derivatives.test b/mlir/test/Target/DXSA/hlsl/derivatives.test new file mode 100644 index 000000000000..67f68e01e02d --- /dev/null +++ b/mlir/test/Target/DXSA/hlsl/derivatives.test @@ -0,0 +1,46 @@ +// RUN: mlir-translate --import-dxsa-bin %S/inputs/derivatives.shex | FileCheck %s +// NOTE: Assertions have been autogenerated by utils/generate-test-checks.py + + +// CHECK-LABEL: dxsa.dcl_global_flags +// CHECK: dxsa.dcl_input_ps linear v<0> +// CHECK: dxsa.dcl_input_ps linear v<1> +// CHECK: dxsa.dcl_output o<0> +// CHECK: dxsa.dcl_temps 2 +// CHECK: %[[INDEX_0:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_0:.*]] = dxsa.operand %[[INDEX_0]] {mask = 240 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_1:.*]] = dxsa.index.imm {imm = 1 : i32} +// CHECK: %[[OPERAND_1:.*]] = dxsa.operand %[[INDEX_1]] {num_components = 4 : i32, swizzle = dense<[0, 1, 2, 3]> : vector<4xi32>, type = 1 : i32} +// CHECK: dxsa.instruction "deriv_rtx_coarse" %[[OPERAND_0]], %[[OPERAND_1]] +// CHECK: %[[INDEX_2:.*]] = dxsa.index.imm {imm = 1 : i32} +// CHECK: %[[OPERAND_2:.*]] = dxsa.operand %[[INDEX_2]] {mask = 240 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_3:.*]] = dxsa.index.imm {imm = 1 : i32} +// CHECK: %[[OPERAND_3:.*]] = dxsa.operand %[[INDEX_3]] {num_components = 4 : i32, swizzle = dense<[0, 1, 2, 3]> : vector<4xi32>, type = 1 : i32} +// CHECK: dxsa.instruction "deriv_rty_coarse" %[[OPERAND_2]], %[[OPERAND_3]] +// CHECK: dxsa.add r<0>, r<0>, r<1> +// CHECK: %[[INDEX_4:.*]] = dxsa.index.imm {imm = 1 : i32} +// CHECK: %[[OPERAND_4:.*]] = dxsa.operand %[[INDEX_4]] {mask = 240 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_5:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_5:.*]] = dxsa.operand %[[INDEX_5]] {num_components = 4 : i32, swizzle = dense<[0, 1, 2, 3]> : vector<4xi32>, type = 1 : i32} +// CHECK: dxsa.instruction "deriv_rtx_coarse" %[[OPERAND_4]], %[[OPERAND_5]] +// CHECK: dxsa.add r<0>, r<0>, r<1> +// CHECK: %[[INDEX_6:.*]] = dxsa.index.imm {imm = 1 : i32} +// CHECK: %[[OPERAND_6:.*]] = dxsa.operand %[[INDEX_6]] {mask = 240 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_7:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_7:.*]] = dxsa.operand %[[INDEX_7]] {num_components = 4 : i32, swizzle = dense<[0, 1, 2, 3]> : vector<4xi32>, type = 1 : i32} +// CHECK: dxsa.instruction "deriv_rty_coarse" %[[OPERAND_6]], %[[OPERAND_7]] +// CHECK: dxsa.add r<0>, r<0>, r<1> +// CHECK: %[[INDEX_8:.*]] = dxsa.index.imm {imm = 1 : i32} +// CHECK: %[[OPERAND_8:.*]] = dxsa.operand %[[INDEX_8]] {mask = 240 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_9:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_9:.*]] = dxsa.operand %[[INDEX_9]] {num_components = 4 : i32, swizzle = dense<[0, 1, 2, 3]> : vector<4xi32>, type = 1 : i32} +// CHECK: dxsa.instruction "deriv_rtx_fine" %[[OPERAND_8]], %[[OPERAND_9]] +// CHECK: dxsa.add r<0>, r<0>, r<1> +// CHECK: %[[INDEX_10:.*]] = dxsa.index.imm {imm = 1 : i32} +// CHECK: %[[OPERAND_10:.*]] = dxsa.operand %[[INDEX_10]] {mask = 240 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_11:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_11:.*]] = dxsa.operand %[[INDEX_11]] {num_components = 4 : i32, swizzle = dense<[0, 1, 2, 3]> : vector<4xi32>, type = 1 : i32} +// CHECK: dxsa.instruction "deriv_rty_fine" %[[OPERAND_10]], %[[OPERAND_11]] +// CHECK: dxsa.add o<0>, r<0>, r<1> +// CHECK: dxsa.instruction "ret" + diff --git a/mlir/test/Target/DXSA/hlsl/discard.test b/mlir/test/Target/DXSA/hlsl/discard.test new file mode 100644 index 000000000000..18ae05c61835 --- /dev/null +++ b/mlir/test/Target/DXSA/hlsl/discard.test @@ -0,0 +1,22 @@ +// RUN: mlir-translate --import-dxsa-bin %S/inputs/discard.shex | FileCheck %s +// NOTE: Assertions have been autogenerated by utils/generate-test-checks.py + + +// CHECK-LABEL: dxsa.dcl_global_flags +// CHECK: dxsa.dcl_input_ps linear v<0, > +// CHECK: dxsa.dcl_output o<0> +// CHECK: dxsa.dcl_temps 1 +// CHECK: dxsa.lt r<0, >, l(0x3E99999A), v<0, > +// CHECK: %[[INDEX_0:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_0:.*]] = dxsa.operand %[[INDEX_0]] {num_components = 4 : i32, one = 0 : i32, type = 0 : i32} +// CHECK: dxsa.instruction "discard" %[[OPERAND_0]] +// CHECK: dxsa.ne r<0, >, v<0, >, l(0x0) +// CHECK: %[[INDEX_1:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_1:.*]] = dxsa.operand %[[INDEX_1]] {num_components = 4 : i32, one = 0 : i32, type = 0 : i32} +// CHECK: dxsa.instruction "discard" %[[OPERAND_1]] +// CHECK: %[[INDEX_2:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_2:.*]] = dxsa.operand %[[INDEX_2]] {mask = 240 : i32, num_components = 4 : i32, type = 2 : i32} +// CHECK: %[[OPERAND_3:.*]] = dxsa.operand.imm {imm = dense<0> : vector<4xi32>} +// CHECK: dxsa.instruction "mov" %[[OPERAND_2]], %[[OPERAND_3]] +// CHECK: dxsa.instruction "ret" + diff --git a/mlir/test/Target/DXSA/hlsl/dot1.test b/mlir/test/Target/DXSA/hlsl/dot1.test new file mode 100644 index 000000000000..4bfeac07ab74 --- /dev/null +++ b/mlir/test/Target/DXSA/hlsl/dot1.test @@ -0,0 +1,16 @@ +// RUN: mlir-translate --import-dxsa-bin %S/inputs/dot1.shex | FileCheck %s +// NOTE: Assertions have been autogenerated by utils/generate-test-checks.py + + +// CHECK-LABEL: dxsa.dcl_global_flags +// CHECK: dxsa.dcl_input_ps linear v<0> +// CHECK: dxsa.dcl_input_ps linear v<1> +// CHECK: dxsa.dcl_output o<0, > +// CHECK: dxsa.dcl_temps 1 +// CHECK: dxsa.dp4 r<0, >, v<0>, v<1> +// CHECK: dxsa.dp3 r<0, >, v<0, >, v<1, > +// CHECK: dxsa.add r<0, >, r<0, >, r<0, > +// CHECK: dxsa.dp2 r<0, >, v<0, >, v<1, > +// CHECK: dxsa.add o<0, >, r<0, >, r<0, > +// CHECK: dxsa.instruction "ret" + diff --git a/mlir/test/Target/DXSA/hlsl/double1.test b/mlir/test/Target/DXSA/hlsl/double1.test new file mode 100644 index 000000000000..2c880f6815d5 --- /dev/null +++ b/mlir/test/Target/DXSA/hlsl/double1.test @@ -0,0 +1,52 @@ +// RUN: mlir-translate --import-dxsa-bin %S/inputs/double1.shex | FileCheck %s +// NOTE: Assertions have been autogenerated by utils/generate-test-checks.py + + +// CHECK-LABEL: dxsa.dcl_global_flags +// CHECK: dxsa.dcl_input_ps constant v<0, > +// CHECK: dxsa.dcl_input_ps constant v<0, > +// CHECK: dxsa.dcl_output o<0, > +// CHECK: dxsa.dcl_temps 1 +// CHECK: %[[INDEX_0:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_0:.*]] = dxsa.operand %[[INDEX_0]] {mask = 240 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_1:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_1:.*]] = dxsa.operand %[[INDEX_1]] {num_components = 4 : i32, swizzle = dense<[0, 1, 2, 3]> : vector<4xi32>, type = 1 : i32} +// CHECK: dxsa.instruction "mov" %[[OPERAND_0]], %[[OPERAND_1]] +// CHECK: %[[INDEX_2:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_2:.*]] = dxsa.operand %[[INDEX_2]] {mask = 48 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_3:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_3:.*]] = dxsa.operand %[[INDEX_3]] {num_components = 4 : i32, swizzle = dense<[2, 3, 2, 3]> : vector<4xi32>, type = 0 : i32} +// CHECK: %[[INDEX_4:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_4:.*]] = dxsa.operand %[[INDEX_4]] {num_components = 4 : i32, swizzle = dense<[0, 1, 0, 1]> : vector<4xi32>, type = 0 : i32} +// CHECK: dxsa.instruction "ddiv" %[[OPERAND_2]], %[[OPERAND_3]], %[[OPERAND_4]] +// CHECK: %[[INDEX_5:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_5:.*]] = dxsa.operand %[[INDEX_5]] {mask = 192 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_6:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_6:.*]] = dxsa.operand %[[INDEX_6]] {num_components = 4 : i32, swizzle = dense<[2, 3, 2, 3]> : vector<4xi32>, type = 0 : i32} +// CHECK: %[[OPERAND_7:.*]] = dxsa.operand.imm {imm = dense<[0, 6917529030863447654]> : vector<2xi64>} +// CHECK: dxsa.instruction "dadd" %[[OPERAND_5]], %[[OPERAND_6]], %[[OPERAND_7]] +// CHECK: %[[INDEX_7:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_8:.*]] = dxsa.operand %[[INDEX_7]] {mask = 48 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_8:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_9:.*]] = dxsa.operand %[[INDEX_8]] {num_components = 4 : i32, swizzle = dense<[0, 1, 0, 1]> : vector<4xi32>, type = 0 : i32} +// CHECK: %[[OPERAND_10:.*]] = dxsa.operand.imm {imm = dense<[-9223372035781275157, 0]> : vector<2xi64>} +// CHECK: dxsa.instruction "dmin" %[[OPERAND_8]], %[[OPERAND_9]], %[[OPERAND_10]] +// CHECK: %[[INDEX_9:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_11:.*]] = dxsa.operand %[[INDEX_9]] {mask = 48 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_10:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_12:.*]] = dxsa.operand %[[INDEX_10]] {num_components = 4 : i32, swizzle = dense<[2, 3, 2, 3]> : vector<4xi32>, type = 0 : i32} +// CHECK: %[[INDEX_11:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_13:.*]] = dxsa.operand %[[INDEX_11]] {num_components = 4 : i32, swizzle = dense<[0, 1, 0, 1]> : vector<4xi32>, type = 0 : i32} +// CHECK: dxsa.instruction "dmax" %[[OPERAND_11]], %[[OPERAND_12]], %[[OPERAND_13]] +// CHECK: %[[INDEX_12:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_14:.*]] = dxsa.operand %[[INDEX_12]] {mask = 48 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_13:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_15:.*]] = dxsa.operand %[[INDEX_13]] {modifier = 2 : i32, num_components = 4 : i32, swizzle = dense<[0, 1, 0, 1]> : vector<4xi32>, type = 0 : i32} +// CHECK: dxsa.instruction "dmov" %[[OPERAND_14]], %[[OPERAND_15]] +// CHECK: %[[INDEX_14:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_16:.*]] = dxsa.operand %[[INDEX_14]] {mask = 48 : i32, num_components = 4 : i32, type = 2 : i32} +// CHECK: %[[INDEX_15:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_17:.*]] = dxsa.operand %[[INDEX_15]] {num_components = 4 : i32, swizzle = dense<[0, 1, 0, 0]> : vector<4xi32>, type = 0 : i32} +// CHECK: dxsa.instruction "mov" %[[OPERAND_16]], %[[OPERAND_17]] +// CHECK: dxsa.instruction "ret" + diff --git a/mlir/test/Target/DXSA/hlsl/double2.test b/mlir/test/Target/DXSA/hlsl/double2.test new file mode 100644 index 000000000000..d658176c9e6b --- /dev/null +++ b/mlir/test/Target/DXSA/hlsl/double2.test @@ -0,0 +1,58 @@ +// RUN: mlir-translate --import-dxsa-bin %S/inputs/double2.shex | FileCheck %s +// NOTE: Assertions have been autogenerated by utils/generate-test-checks.py + + +// CHECK-LABEL: dxsa.dcl_global_flags +// CHECK: dxsa.dcl_constant_buffer , +// CHECK: dxsa.dcl_input_ps constant v<0, > +// CHECK: dxsa.dcl_input_ps constant v<0, > +// CHECK: dxsa.dcl_output o<0, > +// CHECK: dxsa.dcl_temps 1 +// CHECK: %[[INDEX_0:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_0:.*]] = dxsa.operand %[[INDEX_0]] {mask = 240 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_1:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_1:.*]] = dxsa.operand %[[INDEX_1]] {num_components = 4 : i32, swizzle = dense<[0, 1, 2, 3]> : vector<4xi32>, type = 1 : i32} +// CHECK: dxsa.instruction "mov" %[[OPERAND_0]], %[[OPERAND_1]] +// CHECK: %[[INDEX_2:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_2:.*]] = dxsa.operand %[[INDEX_2]] {mask = 48 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_3:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_3:.*]] = dxsa.operand %[[INDEX_3]] {num_components = 4 : i32, swizzle = dense<[2, 3, 2, 3]> : vector<4xi32>, type = 0 : i32} +// CHECK: %[[INDEX_4:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_4:.*]] = dxsa.operand %[[INDEX_4]] {num_components = 4 : i32, swizzle = dense<[0, 1, 0, 1]> : vector<4xi32>, type = 0 : i32} +// CHECK: dxsa.instruction "ddiv" %[[OPERAND_2]], %[[OPERAND_3]], %[[OPERAND_4]] +// CHECK: %[[INDEX_5:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_5:.*]] = dxsa.operand %[[INDEX_5]] {mask = 192 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_6:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_6:.*]] = dxsa.operand %[[INDEX_6]] {num_components = 4 : i32, swizzle = dense<[2, 3, 2, 3]> : vector<4xi32>, type = 0 : i32} +// CHECK: %[[OPERAND_7:.*]] = dxsa.operand.imm {imm = dense<[0, 6917529030863447654]> : vector<2xi64>} +// CHECK: dxsa.instruction "dadd" %[[OPERAND_5]], %[[OPERAND_6]], %[[OPERAND_7]] +// CHECK: %[[INDEX_7:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_8:.*]] = dxsa.operand %[[INDEX_7]] {mask = 48 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_8:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_9:.*]] = dxsa.operand %[[INDEX_8]] {num_components = 4 : i32, swizzle = dense<[0, 1, 0, 1]> : vector<4xi32>, type = 0 : i32} +// CHECK: %[[OPERAND_10:.*]] = dxsa.operand.imm {imm = dense<[-9223372035781275157, 0]> : vector<2xi64>} +// CHECK: dxsa.instruction "dmin" %[[OPERAND_8]], %[[OPERAND_9]], %[[OPERAND_10]] +// CHECK: %[[INDEX_9:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_11:.*]] = dxsa.operand %[[INDEX_9]] {mask = 48 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_10:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_12:.*]] = dxsa.operand %[[INDEX_10]] {num_components = 4 : i32, swizzle = dense<[2, 3, 2, 3]> : vector<4xi32>, type = 0 : i32} +// CHECK: %[[INDEX_11:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_13:.*]] = dxsa.operand %[[INDEX_11]] {num_components = 4 : i32, swizzle = dense<[0, 1, 0, 1]> : vector<4xi32>, type = 0 : i32} +// CHECK: dxsa.instruction "dmax" %[[OPERAND_11]], %[[OPERAND_12]], %[[OPERAND_13]] +// CHECK: %[[INDEX_12:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_14:.*]] = dxsa.operand %[[INDEX_12]] {mask = 48 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_13:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[INDEX_14:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_15:.*]] = dxsa.operand %[[INDEX_13]], %[[INDEX_14]] {num_components = 4 : i32, swizzle = dense<0> : vector<4xi32>, type = 8 : i32} +// CHECK: %[[INDEX_15:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_16:.*]] = dxsa.operand %[[INDEX_15]] {modifier = 2 : i32, num_components = 4 : i32, swizzle = dense<[0, 1, 0, 1]> : vector<4xi32>, type = 0 : i32} +// CHECK: %[[INDEX_16:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_17:.*]] = dxsa.operand %[[INDEX_16]] {num_components = 4 : i32, swizzle = dense<[0, 1, 0, 1]> : vector<4xi32>, type = 0 : i32} +// CHECK: dxsa.instruction "dmovc" %[[OPERAND_14]], %[[OPERAND_15]], %[[OPERAND_16]], %[[OPERAND_17]] +// CHECK: %[[INDEX_17:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_18:.*]] = dxsa.operand %[[INDEX_17]] {mask = 48 : i32, num_components = 4 : i32, type = 2 : i32} +// CHECK: %[[INDEX_18:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_19:.*]] = dxsa.operand %[[INDEX_18]] {num_components = 4 : i32, swizzle = dense<[0, 1, 0, 0]> : vector<4xi32>, type = 0 : i32} +// CHECK: dxsa.instruction "mov" %[[OPERAND_18]], %[[OPERAND_19]] +// CHECK: dxsa.instruction "ret" + diff --git a/mlir/test/Target/DXSA/hlsl/double3.test b/mlir/test/Target/DXSA/hlsl/double3.test new file mode 100644 index 000000000000..889c12592b58 --- /dev/null +++ b/mlir/test/Target/DXSA/hlsl/double3.test @@ -0,0 +1,67 @@ +// RUN: mlir-translate --import-dxsa-bin %S/inputs/double3.shex | FileCheck %s +// NOTE: Assertions have been autogenerated by utils/generate-test-checks.py + + +// CHECK-LABEL: dxsa.dcl_global_flags +// CHECK: dxsa.dcl_input_ps constant v<0, > +// CHECK: dxsa.dcl_input_ps constant v<0, > +// CHECK: dxsa.dcl_input_ps constant v<1, > +// CHECK: dxsa.dcl_output o<0, > +// CHECK: dxsa.dcl_temps 2 +// CHECK: %[[INDEX_0:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_0:.*]] = dxsa.operand %[[INDEX_0]] {mask = 240 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_1:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_1:.*]] = dxsa.operand %[[INDEX_1]] {num_components = 4 : i32, swizzle = dense<[0, 1, 2, 3]> : vector<4xi32>, type = 1 : i32} +// CHECK: dxsa.instruction "mov" %[[OPERAND_0]], %[[OPERAND_1]] +// CHECK: %[[INDEX_2:.*]] = dxsa.index.imm {imm = 1 : i32} +// CHECK: %[[OPERAND_2:.*]] = dxsa.operand %[[INDEX_2]] {mask = 16 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_3:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_3:.*]] = dxsa.operand %[[INDEX_3]] {num_components = 4 : i32, swizzle = dense<[2, 3, 2, 3]> : vector<4xi32>, type = 0 : i32} +// CHECK: %[[INDEX_4:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_4:.*]] = dxsa.operand %[[INDEX_4]] {num_components = 4 : i32, swizzle = dense<[0, 1, 0, 1]> : vector<4xi32>, type = 0 : i32} +// CHECK: dxsa.instruction "deq" %[[OPERAND_2]], %[[OPERAND_3]], %[[OPERAND_4]] +// CHECK: %[[INDEX_5:.*]] = dxsa.index.imm {imm = 1 : i32} +// CHECK: %[[OPERAND_5:.*]] = dxsa.operand %[[INDEX_5]] {mask = 192 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_6:.*]] = dxsa.index.imm {imm = 1 : i32} +// CHECK: %[[OPERAND_6:.*]] = dxsa.operand %[[INDEX_6]] {num_components = 4 : i32, swizzle = dense<[0, 0, 0, 1]> : vector<4xi32>, type = 1 : i32} +// CHECK: dxsa.instruction "mov" %[[OPERAND_5]], %[[OPERAND_6]] +// CHECK: %[[INDEX_7:.*]] = dxsa.index.imm {imm = 1 : i32} +// CHECK: %[[OPERAND_7:.*]] = dxsa.operand %[[INDEX_7]] {mask = 32 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_8:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_8:.*]] = dxsa.operand %[[INDEX_8]] {num_components = 4 : i32, swizzle = dense<[0, 1, 0, 1]> : vector<4xi32>, type = 0 : i32} +// CHECK: %[[INDEX_9:.*]] = dxsa.index.imm {imm = 1 : i32} +// CHECK: %[[OPERAND_9:.*]] = dxsa.operand %[[INDEX_9]] {num_components = 4 : i32, swizzle = dense<[2, 3, 2, 3]> : vector<4xi32>, type = 0 : i32} +// CHECK: dxsa.instruction "dne" %[[OPERAND_7]], %[[OPERAND_8]], %[[OPERAND_9]] +// CHECK: dxsa.and r<1, >, r<1, >, r<1, > +// CHECK: %[[INDEX_10:.*]] = dxsa.index.imm {imm = 1 : i32} +// CHECK: %[[OPERAND_10:.*]] = dxsa.operand %[[INDEX_10]] {mask = 32 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_11:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_11:.*]] = dxsa.operand %[[INDEX_11]] {num_components = 4 : i32, swizzle = dense<[2, 3, 2, 3]> : vector<4xi32>, type = 0 : i32} +// CHECK: %[[INDEX_12:.*]] = dxsa.index.imm {imm = 1 : i32} +// CHECK: %[[OPERAND_12:.*]] = dxsa.operand %[[INDEX_12]] {num_components = 4 : i32, swizzle = dense<[2, 3, 2, 3]> : vector<4xi32>, type = 0 : i32} +// CHECK: dxsa.instruction "dlt" %[[OPERAND_10]], %[[OPERAND_11]], %[[OPERAND_12]] +// CHECK: %[[INDEX_13:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_13:.*]] = dxsa.operand %[[INDEX_13]] {mask = 192 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_14:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_14:.*]] = dxsa.operand %[[INDEX_14]] {num_components = 4 : i32, swizzle = dense<[2, 3, 2, 3]> : vector<4xi32>, type = 0 : i32} +// CHECK: %[[INDEX_15:.*]] = dxsa.index.imm {imm = 1 : i32} +// CHECK: %[[OPERAND_15:.*]] = dxsa.operand %[[INDEX_15]] {num_components = 4 : i32, swizzle = dense<[2, 3, 2, 3]> : vector<4xi32>, type = 0 : i32} +// CHECK: dxsa.instruction "dmul" %[[OPERAND_13]], %[[OPERAND_14]], %[[OPERAND_15]] +// CHECK: %[[INDEX_16:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_16:.*]] = dxsa.operand %[[INDEX_16]] {mask = 192 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_17:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_17:.*]] = dxsa.operand %[[INDEX_17]] {num_components = 4 : i32, swizzle = dense<[2, 3, 2, 3]> : vector<4xi32>, type = 0 : i32} +// CHECK: %[[INDEX_18:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_18:.*]] = dxsa.operand %[[INDEX_18]] {num_components = 4 : i32, swizzle = dense<[0, 1, 0, 1]> : vector<4xi32>, type = 0 : i32} +// CHECK: dxsa.instruction "dadd" %[[OPERAND_16]], %[[OPERAND_17]], %[[OPERAND_18]] +// CHECK: %[[INDEX_19:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_19:.*]] = dxsa.operand %[[INDEX_19]] {mask = 16 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_20:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_20:.*]] = dxsa.operand %[[INDEX_20]] {num_components = 4 : i32, swizzle = dense<[0, 1, 0, 1]> : vector<4xi32>, type = 0 : i32} +// CHECK: %[[INDEX_21:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_21:.*]] = dxsa.operand %[[INDEX_21]] {num_components = 4 : i32, swizzle = dense<[2, 3, 2, 3]> : vector<4xi32>, type = 0 : i32} +// CHECK: dxsa.instruction "dlt" %[[OPERAND_19]], %[[OPERAND_20]], %[[OPERAND_21]] +// CHECK: dxsa.and r<0, >, r<1, >, r<1, > +// CHECK: dxsa.and o<0, >, r<0, >, r<0, > +// CHECK: dxsa.instruction "ret" + diff --git a/mlir/test/Target/DXSA/hlsl/double4.test b/mlir/test/Target/DXSA/hlsl/double4.test new file mode 100644 index 000000000000..7f6e6a67aca7 --- /dev/null +++ b/mlir/test/Target/DXSA/hlsl/double4.test @@ -0,0 +1,48 @@ +// RUN: mlir-translate --import-dxsa-bin %S/inputs/double4.shex | FileCheck %s +// NOTE: Assertions have been autogenerated by utils/generate-test-checks.py + + +// CHECK-LABEL: dxsa.dcl_global_flags +// CHECK: dxsa.dcl_input_ps constant v<0> +// CHECK: dxsa.dcl_input_ps constant v<1> +// CHECK: dxsa.dcl_input_ps constant v<2> +// CHECK: dxsa.dcl_output o<0> +// CHECK: dxsa.dcl_temps 3 +// CHECK: %[[INDEX_0:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_0:.*]] = dxsa.operand %[[INDEX_0]] {mask = 240 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_1:.*]] = dxsa.index.imm {imm = 1 : i32} +// CHECK: %[[OPERAND_1:.*]] = dxsa.operand %[[INDEX_1]] {num_components = 4 : i32, swizzle = dense<[0, 1, 2, 3]> : vector<4xi32>, type = 1 : i32} +// CHECK: dxsa.instruction "mov" %[[OPERAND_0]], %[[OPERAND_1]] +// CHECK: %[[INDEX_2:.*]] = dxsa.index.imm {imm = 1 : i32} +// CHECK: %[[OPERAND_2:.*]] = dxsa.operand %[[INDEX_2]] {mask = 240 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_3:.*]] = dxsa.index.imm {imm = 2 : i32} +// CHECK: %[[OPERAND_3:.*]] = dxsa.operand %[[INDEX_3]] {num_components = 4 : i32, swizzle = dense<[0, 1, 2, 3]> : vector<4xi32>, type = 1 : i32} +// CHECK: dxsa.instruction "mov" %[[OPERAND_2]], %[[OPERAND_3]] +// CHECK: %[[INDEX_4:.*]] = dxsa.index.imm {imm = 2 : i32} +// CHECK: %[[OPERAND_4:.*]] = dxsa.operand %[[INDEX_4]] {mask = 240 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_5:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_5:.*]] = dxsa.operand %[[INDEX_5]] {num_components = 4 : i32, swizzle = dense<[0, 1, 2, 3]> : vector<4xi32>, type = 1 : i32} +// CHECK: dxsa.instruction "mov" %[[OPERAND_4]], %[[OPERAND_5]] +// CHECK: %[[INDEX_6:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_6:.*]] = dxsa.operand %[[INDEX_6]] {mask = 240 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_7:.*]] = dxsa.index.imm {imm = 2 : i32} +// CHECK: %[[OPERAND_7:.*]] = dxsa.operand %[[INDEX_7]] {num_components = 4 : i32, swizzle = dense<[0, 1, 2, 3]> : vector<4xi32>, type = 0 : i32} +// CHECK: %[[INDEX_8:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_8:.*]] = dxsa.operand %[[INDEX_8]] {num_components = 4 : i32, swizzle = dense<[0, 1, 2, 3]> : vector<4xi32>, type = 0 : i32} +// CHECK: %[[INDEX_9:.*]] = dxsa.index.imm {imm = 1 : i32} +// CHECK: %[[OPERAND_9:.*]] = dxsa.operand %[[INDEX_9]] {num_components = 4 : i32, swizzle = dense<[0, 1, 2, 3]> : vector<4xi32>, type = 0 : i32} +// CHECK: dxsa.instruction "dfma" %[[OPERAND_6]], %[[OPERAND_7]], %[[OPERAND_8]], %[[OPERAND_9]] +// CHECK: %[[INDEX_10:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_10:.*]] = dxsa.operand %[[INDEX_10]] {mask = 240 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_11:.*]] = dxsa.index.imm {imm = 2 : i32} +// CHECK: %[[OPERAND_11:.*]] = dxsa.operand %[[INDEX_11]] {num_components = 4 : i32, swizzle = dense<[0, 1, 2, 3]> : vector<4xi32>, type = 0 : i32} +// CHECK: %[[INDEX_12:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_12:.*]] = dxsa.operand %[[INDEX_12]] {num_components = 4 : i32, swizzle = dense<[0, 1, 2, 3]> : vector<4xi32>, type = 0 : i32} +// CHECK: dxsa.instruction "dadd" %[[OPERAND_10]], %[[OPERAND_11]], %[[OPERAND_12]] +// CHECK: %[[INDEX_13:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_13:.*]] = dxsa.operand %[[INDEX_13]] {mask = 240 : i32, num_components = 4 : i32, type = 2 : i32} +// CHECK: %[[INDEX_14:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_14:.*]] = dxsa.operand %[[INDEX_14]] {num_components = 4 : i32, swizzle = dense<[0, 3, 0, 3]> : vector<4xi32>, type = 0 : i32} +// CHECK: dxsa.instruction "mov" %[[OPERAND_13]], %[[OPERAND_14]] +// CHECK: dxsa.instruction "ret" + diff --git a/mlir/test/Target/DXSA/hlsl/double5.test b/mlir/test/Target/DXSA/hlsl/double5.test new file mode 100644 index 000000000000..d2300837788a --- /dev/null +++ b/mlir/test/Target/DXSA/hlsl/double5.test @@ -0,0 +1,97 @@ +// RUN: mlir-translate --import-dxsa-bin %S/inputs/double5.shex | FileCheck %s +// NOTE: Assertions have been autogenerated by utils/generate-test-checks.py + + +// CHECK-LABEL: dxsa.dcl_global_flags +// CHECK: dxsa.dcl_input_ps constant v<0, > +// CHECK: dxsa.dcl_input_ps constant v<1, > +// CHECK: dxsa.dcl_input_ps constant v<2, > +// CHECK: dxsa.dcl_output o<0> +// CHECK: dxsa.dcl_temps 2 +// CHECK: %[[INDEX_0:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_0:.*]] = dxsa.operand %[[INDEX_0]] {mask = 48 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_1:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_1:.*]] = dxsa.operand %[[INDEX_1]] {num_components = 4 : i32, swizzle = dense<[0, 1, 0, 0]> : vector<4xi32>, type = 1 : i32} +// CHECK: dxsa.instruction "mov" %[[OPERAND_0]], %[[OPERAND_1]] +// CHECK: %[[INDEX_2:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_2:.*]] = dxsa.operand %[[INDEX_2]] {mask = 16 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_3:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_3:.*]] = dxsa.operand %[[INDEX_3]] {num_components = 4 : i32, swizzle = dense<[0, 1, 0, 1]> : vector<4xi32>, type = 0 : i32} +// CHECK: dxsa.instruction "dtof" %[[OPERAND_2]], %[[OPERAND_3]] +// CHECK: %[[INDEX_4:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_4:.*]] = dxsa.operand %[[INDEX_4]] {mask = 48 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_5:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_5:.*]] = dxsa.operand %[[INDEX_5]] {num_components = 4 : i32, one = 0 : i32, type = 0 : i32} +// CHECK: dxsa.instruction "ftod" %[[OPERAND_4]], %[[OPERAND_5]] +// CHECK: %[[INDEX_6:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_6:.*]] = dxsa.operand %[[INDEX_6]] {mask = 192 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_7:.*]] = dxsa.index.imm {imm = 1 : i32} +// CHECK: %[[OPERAND_7:.*]] = dxsa.operand %[[INDEX_7]] {num_components = 4 : i32, swizzle = dense<[0, 0, 0, 1]> : vector<4xi32>, type = 1 : i32} +// CHECK: dxsa.instruction "mov" %[[OPERAND_6]], %[[OPERAND_7]] +// CHECK: %[[INDEX_8:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_8:.*]] = dxsa.operand %[[INDEX_8]] {mask = 64 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_9:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_9:.*]] = dxsa.operand %[[INDEX_9]] {num_components = 4 : i32, swizzle = dense<[2, 3, 2, 3]> : vector<4xi32>, type = 0 : i32} +// CHECK: dxsa.instruction "dtoi" %[[OPERAND_8]], %[[OPERAND_9]] +// CHECK: %[[INDEX_10:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_10:.*]] = dxsa.operand %[[INDEX_10]] {mask = 192 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_11:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_11:.*]] = dxsa.operand %[[INDEX_11]] {num_components = 4 : i32, one = 2 : i32, type = 0 : i32} +// CHECK: dxsa.instruction "itod" %[[OPERAND_10]], %[[OPERAND_11]] +// CHECK: %[[INDEX_12:.*]] = dxsa.index.imm {imm = 1 : i32} +// CHECK: %[[OPERAND_12:.*]] = dxsa.operand %[[INDEX_12]] {mask = 48 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_13:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_13:.*]] = dxsa.operand %[[INDEX_13]] {num_components = 4 : i32, swizzle = dense<[2, 3, 2, 3]> : vector<4xi32>, type = 0 : i32} +// CHECK: %[[INDEX_14:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_14:.*]] = dxsa.operand %[[INDEX_14]] {num_components = 4 : i32, swizzle = dense<[0, 1, 0, 1]> : vector<4xi32>, type = 0 : i32} +// CHECK: dxsa.instruction "dadd" %[[OPERAND_12]], %[[OPERAND_13]], %[[OPERAND_14]] +// CHECK: %[[INDEX_15:.*]] = dxsa.index.imm {imm = 1 : i32} +// CHECK: %[[OPERAND_15:.*]] = dxsa.operand %[[INDEX_15]] {mask = 48 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_16:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_16:.*]] = dxsa.operand %[[INDEX_16]] {num_components = 4 : i32, swizzle = dense<[2, 3, 2, 3]> : vector<4xi32>, type = 0 : i32} +// CHECK: %[[INDEX_17:.*]] = dxsa.index.imm {imm = 1 : i32} +// CHECK: %[[OPERAND_17:.*]] = dxsa.operand %[[INDEX_17]] {num_components = 4 : i32, swizzle = dense<[0, 1, 0, 1]> : vector<4xi32>, type = 0 : i32} +// CHECK: dxsa.instruction "dadd" %[[OPERAND_15]], %[[OPERAND_16]], %[[OPERAND_17]] +// CHECK: %[[INDEX_18:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_18:.*]] = dxsa.operand %[[INDEX_18]] {mask = 48 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_19:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_19:.*]] = dxsa.operand %[[INDEX_19]] {num_components = 4 : i32, swizzle = dense<[0, 1, 0, 1]> : vector<4xi32>, type = 0 : i32} +// CHECK: %[[INDEX_20:.*]] = dxsa.index.imm {imm = 1 : i32} +// CHECK: %[[OPERAND_20:.*]] = dxsa.operand %[[INDEX_20]] {num_components = 4 : i32, swizzle = dense<[0, 1, 0, 1]> : vector<4xi32>, type = 0 : i32} +// CHECK: dxsa.instruction "dadd" %[[OPERAND_18]], %[[OPERAND_19]], %[[OPERAND_20]] +// CHECK: %[[INDEX_21:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_21:.*]] = dxsa.operand %[[INDEX_21]] {mask = 48 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_22:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_22:.*]] = dxsa.operand %[[INDEX_22]] {num_components = 4 : i32, swizzle = dense<[2, 3, 2, 3]> : vector<4xi32>, type = 0 : i32} +// CHECK: %[[INDEX_23:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_23:.*]] = dxsa.operand %[[INDEX_23]] {num_components = 4 : i32, swizzle = dense<[0, 1, 0, 1]> : vector<4xi32>, type = 0 : i32} +// CHECK: dxsa.instruction "dadd" %[[OPERAND_21]], %[[OPERAND_22]], %[[OPERAND_23]] +// CHECK: %[[INDEX_24:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_24:.*]] = dxsa.operand %[[INDEX_24]] {mask = 192 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_25:.*]] = dxsa.index.imm {imm = 2 : i32} +// CHECK: %[[OPERAND_25:.*]] = dxsa.operand %[[INDEX_25]] {num_components = 4 : i32, swizzle = dense<[0, 0, 0, 1]> : vector<4xi32>, type = 1 : i32} +// CHECK: dxsa.instruction "mov" %[[OPERAND_24]], %[[OPERAND_25]] +// CHECK: %[[INDEX_26:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_26:.*]] = dxsa.operand %[[INDEX_26]] {mask = 64 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_27:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_27:.*]] = dxsa.operand %[[INDEX_27]] {num_components = 4 : i32, swizzle = dense<[2, 3, 2, 3]> : vector<4xi32>, type = 0 : i32} +// CHECK: dxsa.instruction "dtou" %[[OPERAND_26]], %[[OPERAND_27]] +// CHECK: %[[INDEX_28:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_28:.*]] = dxsa.operand %[[INDEX_28]] {mask = 192 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_29:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_29:.*]] = dxsa.operand %[[INDEX_29]] {num_components = 4 : i32, one = 2 : i32, type = 0 : i32} +// CHECK: dxsa.instruction "utod" %[[OPERAND_28]], %[[OPERAND_29]] +// CHECK: %[[INDEX_30:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_30:.*]] = dxsa.operand %[[INDEX_30]] {mask = 48 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_31:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_31:.*]] = dxsa.operand %[[INDEX_31]] {num_components = 4 : i32, swizzle = dense<[2, 3, 2, 3]> : vector<4xi32>, type = 0 : i32} +// CHECK: %[[INDEX_32:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_32:.*]] = dxsa.operand %[[INDEX_32]] {num_components = 4 : i32, swizzle = dense<[0, 1, 0, 1]> : vector<4xi32>, type = 0 : i32} +// CHECK: dxsa.instruction "dadd" %[[OPERAND_30]], %[[OPERAND_31]], %[[OPERAND_32]] +// CHECK: %[[INDEX_33:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_33:.*]] = dxsa.operand %[[INDEX_33]] {mask = 240 : i32, num_components = 4 : i32, type = 2 : i32} +// CHECK: %[[INDEX_34:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_34:.*]] = dxsa.operand %[[INDEX_34]] {num_components = 4 : i32, swizzle = dense<[0, 1, 0, 1]> : vector<4xi32>, type = 0 : i32} +// CHECK: dxsa.instruction "mov" %[[OPERAND_33]], %[[OPERAND_34]] +// CHECK: dxsa.instruction "ret" + diff --git a/mlir/test/Target/DXSA/hlsl/double6.test b/mlir/test/Target/DXSA/hlsl/double6.test new file mode 100644 index 000000000000..91641c7ac8f9 --- /dev/null +++ b/mlir/test/Target/DXSA/hlsl/double6.test @@ -0,0 +1,168 @@ +// RUN: mlir-translate --import-dxsa-bin %S/inputs/double6.shex | FileCheck %s +// NOTE: Assertions have been autogenerated by utils/generate-test-checks.py + + +// CHECK-LABEL: dxsa.dcl_global_flags +// CHECK: dxsa.dcl_constant_buffer , +// CHECK: dxsa.dcl_input_ps constant v<0, > +// CHECK: dxsa.dcl_input_ps constant v<1, > +// CHECK: dxsa.dcl_input_ps constant v<2, > +// CHECK: dxsa.dcl_output o<0> +// CHECK: dxsa.dcl_temps 2 +// CHECK: dxsa.dcl_indexable_temp x<0>[6] +// CHECK: dxsa.dcl_indexable_temp x<1>[4] +// CHECK: %[[INDEX_0:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[INDEX_1:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_0:.*]] = dxsa.operand %[[INDEX_0]], %[[INDEX_1]] {mask = 48 : i32, num_components = 4 : i32, type = 3 : i32} +// CHECK: %[[OPERAND_1:.*]] = dxsa.operand.imm {imm = dense<[1075838976, 0]> : vector<2xi64>} +// CHECK: dxsa.instruction "dmov" %[[OPERAND_0]], %[[OPERAND_1]] +// CHECK: %[[INDEX_2:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[INDEX_3:.*]] = dxsa.index.imm {imm = 1 : i32} +// CHECK: %[[OPERAND_2:.*]] = dxsa.operand %[[INDEX_2]], %[[INDEX_3]] {mask = 48 : i32, num_components = 4 : i32, type = 3 : i32} +// CHECK: %[[OPERAND_3:.*]] = dxsa.operand.imm {imm = dense<[1072693248, 0]> : vector<2xi64>} +// CHECK: dxsa.instruction "dmov" %[[OPERAND_2]], %[[OPERAND_3]] +// CHECK: %[[INDEX_4:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[INDEX_5:.*]] = dxsa.index.imm {imm = 2 : i32} +// CHECK: %[[OPERAND_4:.*]] = dxsa.operand %[[INDEX_4]], %[[INDEX_5]] {mask = 48 : i32, num_components = 4 : i32, type = 3 : i32} +// CHECK: %[[OPERAND_5:.*]] = dxsa.operand.imm {imm = dense<[1073741824, 0]> : vector<2xi64>} +// CHECK: dxsa.instruction "dmov" %[[OPERAND_4]], %[[OPERAND_5]] +// CHECK: %[[INDEX_6:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[INDEX_7:.*]] = dxsa.index.imm {imm = 3 : i32} +// CHECK: %[[OPERAND_6:.*]] = dxsa.operand %[[INDEX_6]], %[[INDEX_7]] {mask = 48 : i32, num_components = 4 : i32, type = 3 : i32} +// CHECK: %[[OPERAND_7:.*]] = dxsa.operand.imm {imm = dense<[4611686019501947617, 0]> : vector<2xi64>} +// CHECK: dxsa.instruction "dmov" %[[OPERAND_6]], %[[OPERAND_7]] +// CHECK: %[[INDEX_8:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[INDEX_9:.*]] = dxsa.index.imm {imm = 4 : i32} +// CHECK: %[[OPERAND_8:.*]] = dxsa.operand %[[INDEX_8]], %[[INDEX_9]] {mask = 48 : i32, num_components = 4 : i32, type = 3 : i32} +// CHECK: %[[OPERAND_9:.*]] = dxsa.operand.imm {imm = dense<[1075576832, 0]> : vector<2xi64>} +// CHECK: dxsa.instruction "dmov" %[[OPERAND_8]], %[[OPERAND_9]] +// CHECK: %[[INDEX_10:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[INDEX_11:.*]] = dxsa.index.imm {imm = 5 : i32} +// CHECK: %[[OPERAND_10:.*]] = dxsa.operand %[[INDEX_10]], %[[INDEX_11]] {mask = 48 : i32, num_components = 4 : i32, type = 3 : i32} +// CHECK: %[[OPERAND_11:.*]] = dxsa.operand.imm {imm = dense<[1077968896, 0]> : vector<2xi64>} +// CHECK: dxsa.instruction "dmov" %[[OPERAND_10]], %[[OPERAND_11]] +// CHECK: %[[INDEX_12:.*]] = dxsa.index.imm {imm = 1 : i32} +// CHECK: %[[INDEX_13:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_12:.*]] = dxsa.operand %[[INDEX_12]], %[[INDEX_13]] {mask = 48 : i32, num_components = 4 : i32, type = 3 : i32} +// CHECK: %[[OPERAND_13:.*]] = dxsa.operand.imm {imm = dense<[1072693248, 0]> : vector<2xi64>} +// CHECK: dxsa.instruction "dmov" %[[OPERAND_12]], %[[OPERAND_13]] +// CHECK: %[[INDEX_14:.*]] = dxsa.index.imm {imm = 1 : i32} +// CHECK: %[[INDEX_15:.*]] = dxsa.index.imm {imm = 1 : i32} +// CHECK: %[[OPERAND_14:.*]] = dxsa.operand %[[INDEX_14]], %[[INDEX_15]] {mask = 48 : i32, num_components = 4 : i32, type = 3 : i32} +// CHECK: %[[OPERAND_15:.*]] = dxsa.operand.imm {imm = dense<[1073741824, 0]> : vector<2xi64>} +// CHECK: dxsa.instruction "dmov" %[[OPERAND_14]], %[[OPERAND_15]] +// CHECK: %[[INDEX_16:.*]] = dxsa.index.imm {imm = 1 : i32} +// CHECK: %[[INDEX_17:.*]] = dxsa.index.imm {imm = 2 : i32} +// CHECK: %[[OPERAND_16:.*]] = dxsa.operand %[[INDEX_16]], %[[INDEX_17]] {mask = 48 : i32, num_components = 4 : i32, type = 3 : i32} +// CHECK: %[[OPERAND_17:.*]] = dxsa.operand.imm {imm = dense<[4611686019501947617, 0]> : vector<2xi64>} +// CHECK: dxsa.instruction "dmov" %[[OPERAND_16]], %[[OPERAND_17]] +// CHECK: %[[INDEX_18:.*]] = dxsa.index.imm {imm = 1 : i32} +// CHECK: %[[INDEX_19:.*]] = dxsa.index.imm {imm = 3 : i32} +// CHECK: %[[OPERAND_18:.*]] = dxsa.operand %[[INDEX_18]], %[[INDEX_19]] {mask = 48 : i32, num_components = 4 : i32, type = 3 : i32} +// CHECK: %[[OPERAND_19:.*]] = dxsa.operand.imm {imm = dense<[1075576832, 0]> : vector<2xi64>} +// CHECK: dxsa.instruction "dmov" %[[OPERAND_18]], %[[OPERAND_19]] +// CHECK: %[[INDEX_20:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_20:.*]] = dxsa.operand %[[INDEX_20]] {mask = 48 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_21:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[INDEX_22:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_21:.*]] = dxsa.operand %[[INDEX_21]], %[[INDEX_22]] {num_components = 4 : i32, swizzle = dense<[0, 1, 0, 0]> : vector<4xi32>, type = 8 : i32} +// CHECK: dxsa.instruction "mov" %[[OPERAND_20]], %[[OPERAND_21]] +// CHECK: %[[INDEX_23:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_22:.*]] = dxsa.operand %[[INDEX_23]] {mask = 192 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_24:.*]] = dxsa.index.imm {imm = 1 : i32} +// CHECK: %[[INDEX_25:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_23:.*]] = dxsa.operand %[[INDEX_25]] {num_components = 4 : i32, one = 0 : i32, type = 0 : i32} +// CHECK: %[[INDEX_26:.*]] = dxsa.index.rel %[[OPERAND_23]] +// CHECK: %[[OPERAND_24:.*]] = dxsa.operand %[[INDEX_24]], %[[INDEX_26]] {num_components = 4 : i32, swizzle = dense<[0, 1, 0, 1]> : vector<4xi32>, type = 3 : i32} +// CHECK: dxsa.instruction "dmov" %[[OPERAND_22]], %[[OPERAND_24]] +// CHECK: %[[INDEX_27:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_25:.*]] = dxsa.operand %[[INDEX_27]] {mask = 192 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_28:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_26:.*]] = dxsa.operand %[[INDEX_28]] {num_components = 4 : i32, swizzle = dense<[2, 3, 2, 3]> : vector<4xi32>, type = 0 : i32} +// CHECK: %[[INDEX_29:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[INDEX_30:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_27:.*]] = dxsa.operand %[[INDEX_30]] {num_components = 4 : i32, one = 0 : i32, type = 0 : i32} +// CHECK: %[[INDEX_31:.*]] = dxsa.index.rel.imm %[[OPERAND_27]] {imm = 1 : i32, op = "add"} +// CHECK: %[[OPERAND_28:.*]] = dxsa.operand %[[INDEX_29]], %[[INDEX_31]] {num_components = 4 : i32, swizzle = dense<[0, 1, 0, 1]> : vector<4xi32>, type = 8 : i32} +// CHECK: dxsa.instruction "dadd" %[[OPERAND_25]], %[[OPERAND_26]], %[[OPERAND_28]] +// CHECK: %[[INDEX_32:.*]] = dxsa.index.imm {imm = 1 : i32} +// CHECK: %[[OPERAND_29:.*]] = dxsa.operand %[[INDEX_32]] {mask = 48 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_33:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[INDEX_34:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_30:.*]] = dxsa.operand %[[INDEX_34]] {num_components = 4 : i32, one = 1 : i32, type = 0 : i32} +// CHECK: %[[INDEX_35:.*]] = dxsa.index.rel %[[OPERAND_30]] +// CHECK: %[[OPERAND_31:.*]] = dxsa.operand %[[INDEX_33]], %[[INDEX_35]] {num_components = 4 : i32, swizzle = dense<[0, 1, 0, 1]> : vector<4xi32>, type = 3 : i32} +// CHECK: dxsa.instruction "dmov" %[[OPERAND_29]], %[[OPERAND_31]] +// CHECK: %[[INDEX_36:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_32:.*]] = dxsa.operand %[[INDEX_36]] {mask = 192 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_37:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_33:.*]] = dxsa.operand %[[INDEX_37]] {num_components = 4 : i32, swizzle = dense<[2, 3, 2, 3]> : vector<4xi32>, type = 0 : i32} +// CHECK: %[[INDEX_38:.*]] = dxsa.index.imm {imm = 1 : i32} +// CHECK: %[[OPERAND_34:.*]] = dxsa.operand %[[INDEX_38]] {num_components = 4 : i32, swizzle = dense<[0, 1, 0, 1]> : vector<4xi32>, type = 0 : i32} +// CHECK: dxsa.instruction "dadd" %[[OPERAND_32]], %[[OPERAND_33]], %[[OPERAND_34]] +// CHECK: %[[INDEX_39:.*]] = dxsa.index.imm {imm = 1 : i32} +// CHECK: %[[OPERAND_35:.*]] = dxsa.operand %[[INDEX_39]] {mask = 48 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_40:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_36:.*]] = dxsa.operand %[[INDEX_40]] {num_components = 4 : i32, swizzle = dense<[0, 1, 0, 0]> : vector<4xi32>, type = 1 : i32} +// CHECK: dxsa.instruction "mov" %[[OPERAND_35]], %[[OPERAND_36]] +// CHECK: %[[INDEX_41:.*]] = dxsa.index.imm {imm = 1 : i32} +// CHECK: %[[OPERAND_37:.*]] = dxsa.operand %[[INDEX_41]] {mask = 192 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_42:.*]] = dxsa.index.imm {imm = 1 : i32} +// CHECK: %[[OPERAND_38:.*]] = dxsa.operand %[[INDEX_42]] {num_components = 4 : i32, swizzle = dense<[0, 0, 0, 1]> : vector<4xi32>, type = 1 : i32} +// CHECK: dxsa.instruction "mov" %[[OPERAND_37]], %[[OPERAND_38]] +// CHECK: %[[INDEX_43:.*]] = dxsa.index.imm {imm = 1 : i32} +// CHECK: %[[OPERAND_39:.*]] = dxsa.operand %[[INDEX_43]] {mask = 48 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_44:.*]] = dxsa.index.imm {imm = 1 : i32} +// CHECK: %[[OPERAND_40:.*]] = dxsa.operand %[[INDEX_44]] {num_components = 4 : i32, swizzle = dense<[2, 3, 2, 3]> : vector<4xi32>, type = 0 : i32} +// CHECK: %[[INDEX_45:.*]] = dxsa.index.imm {imm = 1 : i32} +// CHECK: %[[OPERAND_41:.*]] = dxsa.operand %[[INDEX_45]] {num_components = 4 : i32, swizzle = dense<[0, 1, 0, 1]> : vector<4xi32>, type = 0 : i32} +// CHECK: dxsa.instruction "dadd" %[[OPERAND_39]], %[[OPERAND_40]], %[[OPERAND_41]] +// CHECK: %[[INDEX_46:.*]] = dxsa.index.imm {imm = 1 : i32} +// CHECK: %[[OPERAND_42:.*]] = dxsa.operand %[[INDEX_46]] {mask = 192 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_47:.*]] = dxsa.index.imm {imm = 2 : i32} +// CHECK: %[[OPERAND_43:.*]] = dxsa.operand %[[INDEX_47]] {num_components = 4 : i32, swizzle = dense<[0, 0, 0, 1]> : vector<4xi32>, type = 1 : i32} +// CHECK: dxsa.instruction "mov" %[[OPERAND_42]], %[[OPERAND_43]] +// CHECK: %[[INDEX_48:.*]] = dxsa.index.imm {imm = 1 : i32} +// CHECK: %[[OPERAND_44:.*]] = dxsa.operand %[[INDEX_48]] {mask = 48 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_49:.*]] = dxsa.index.imm {imm = 1 : i32} +// CHECK: %[[OPERAND_45:.*]] = dxsa.operand %[[INDEX_49]] {num_components = 4 : i32, swizzle = dense<[2, 3, 2, 3]> : vector<4xi32>, type = 0 : i32} +// CHECK: %[[INDEX_50:.*]] = dxsa.index.imm {imm = 1 : i32} +// CHECK: %[[OPERAND_46:.*]] = dxsa.operand %[[INDEX_50]] {num_components = 4 : i32, swizzle = dense<[0, 1, 0, 1]> : vector<4xi32>, type = 0 : i32} +// CHECK: dxsa.instruction "dadd" %[[OPERAND_44]], %[[OPERAND_45]], %[[OPERAND_46]] +// CHECK: %[[INDEX_51:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_47:.*]] = dxsa.operand %[[INDEX_51]] {mask = 192 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_52:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_48:.*]] = dxsa.operand %[[INDEX_52]] {num_components = 4 : i32, swizzle = dense<[2, 3, 2, 3]> : vector<4xi32>, type = 0 : i32} +// CHECK: %[[INDEX_53:.*]] = dxsa.index.imm {imm = 1 : i32} +// CHECK: %[[OPERAND_49:.*]] = dxsa.operand %[[INDEX_53]] {num_components = 4 : i32, swizzle = dense<[0, 1, 0, 1]> : vector<4xi32>, type = 0 : i32} +// CHECK: dxsa.instruction "dadd" %[[OPERAND_47]], %[[OPERAND_48]], %[[OPERAND_49]] +// CHECK: %[[INDEX_54:.*]] = dxsa.index.imm {imm = 1 : i32} +// CHECK: %[[INDEX_55:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_50:.*]] = dxsa.operand %[[INDEX_55]] {num_components = 4 : i32, one = 1 : i32, type = 0 : i32} +// CHECK: %[[INDEX_56:.*]] = dxsa.index.rel %[[OPERAND_50]] +// CHECK: %[[OPERAND_51:.*]] = dxsa.operand %[[INDEX_54]], %[[INDEX_56]] {mask = 48 : i32, num_components = 4 : i32, type = 3 : i32} +// CHECK: %[[INDEX_57:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_52:.*]] = dxsa.operand %[[INDEX_57]] {num_components = 4 : i32, swizzle = dense<[2, 3, 2, 3]> : vector<4xi32>, type = 0 : i32} +// CHECK: dxsa.instruction "dmov" %[[OPERAND_51]], %[[OPERAND_52]] +// CHECK: %[[INDEX_58:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_53:.*]] = dxsa.operand %[[INDEX_58]] {mask = 48 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_59:.*]] = dxsa.index.imm {imm = 1 : i32} +// CHECK: %[[INDEX_60:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_54:.*]] = dxsa.operand %[[INDEX_60]] {num_components = 4 : i32, one = 0 : i32, type = 0 : i32} +// CHECK: %[[INDEX_61:.*]] = dxsa.index.rel %[[OPERAND_54]] +// CHECK: %[[OPERAND_55:.*]] = dxsa.operand %[[INDEX_59]], %[[INDEX_61]] {num_components = 4 : i32, swizzle = dense<[0, 1, 0, 1]> : vector<4xi32>, type = 3 : i32} +// CHECK: dxsa.instruction "dmov" %[[OPERAND_53]], %[[OPERAND_55]] +// CHECK: %[[INDEX_62:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_56:.*]] = dxsa.operand %[[INDEX_62]] {mask = 48 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_63:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_57:.*]] = dxsa.operand %[[INDEX_63]] {num_components = 4 : i32, swizzle = dense<[0, 1, 0, 1]> : vector<4xi32>, type = 0 : i32} +// CHECK: %[[INDEX_64:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_58:.*]] = dxsa.operand %[[INDEX_64]] {num_components = 4 : i32, swizzle = dense<[2, 3, 2, 3]> : vector<4xi32>, type = 0 : i32} +// CHECK: dxsa.instruction "dadd" %[[OPERAND_56]], %[[OPERAND_57]], %[[OPERAND_58]] +// CHECK: %[[INDEX_65:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_59:.*]] = dxsa.operand %[[INDEX_65]] {mask = 240 : i32, num_components = 4 : i32, type = 2 : i32} +// CHECK: %[[INDEX_66:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_60:.*]] = dxsa.operand %[[INDEX_66]] {num_components = 4 : i32, swizzle = dense<[0, 1, 0, 1]> : vector<4xi32>, type = 0 : i32} +// CHECK: dxsa.instruction "mov" %[[OPERAND_59]], %[[OPERAND_60]] +// CHECK: dxsa.instruction "ret" + diff --git a/mlir/test/Target/DXSA/hlsl/ds1.test b/mlir/test/Target/DXSA/hlsl/ds1.test new file mode 100644 index 000000000000..ada5176147d3 --- /dev/null +++ b/mlir/test/Target/DXSA/hlsl/ds1.test @@ -0,0 +1,61 @@ +// RUN: mlir-translate --import-dxsa-bin %S/inputs/ds1.shex | FileCheck %s +// NOTE: Assertions have been autogenerated by utils/generate-test-checks.py + + +// CHECK-LABEL: dxsa.dcl_input_control_point_count 16 +// CHECK: dxsa.dcl_tessellator_domain domain_quad +// CHECK: dxsa.dcl_global_flags +// CHECK: dxsa.dcl_constant_buffer , +// CHECK: dxsa.dcl_input_siv vpc<0, >, +// CHECK: dxsa.dcl_input_siv vpc<1, >, +// CHECK: dxsa.dcl_input_siv vpc<2, >, +// CHECK: dxsa.dcl_input_siv vpc<3, >, +// CHECK: dxsa.dcl_input_siv vpc<4, >, +// CHECK: dxsa.dcl_input_siv vpc<5, >, +// CHECK: dxsa.dcl_input vpc<6> +// CHECK: dxsa.dcl_input vpc<7, > +// CHECK: dxsa.dcl_input vpc<8, > +// CHECK: dxsa.dcl_input vpc<9, > +// CHECK: dxsa.dcl_input vDomain<> +// CHECK: dxsa.dcl_input vicp<[16, 0], > +// CHECK: dxsa.dcl_output_siv o<0>, +// CHECK: dxsa.dcl_temps 2 +// CHECK: dxsa.dcl_index_range vpc<7, >, 3 +// CHECK: %[[INDEX_0:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_0:.*]] = dxsa.operand %[[INDEX_0]] {mask = 240 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[OPERAND_1:.*]] = dxsa.operand.imm {imm = dense<0> : vector<4xi32>} +// CHECK: dxsa.instruction "mov" %[[OPERAND_0]], %[[OPERAND_1]] +// CHECK: %[[INDEX_1:.*]] = dxsa.index.imm {imm = 1 : i32} +// CHECK: %[[OPERAND_2:.*]] = dxsa.operand %[[INDEX_1]] {mask = 16 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[OPERAND_3:.*]] = dxsa.operand.imm {imm = dense<0> : vector<1xi32>} +// CHECK: dxsa.instruction "mov" %[[OPERAND_2]], %[[OPERAND_3]] +// CHECK: dxsa.instruction "loop" +// CHECK: dxsa.ige r<1, >, r<1, >, l(0x10) +// CHECK: %[[INDEX_2:.*]] = dxsa.index.imm {imm = 1 : i32} +// CHECK: %[[OPERAND_4:.*]] = dxsa.operand %[[INDEX_2]] {num_components = 4 : i32, one = 1 : i32, type = 0 : i32} +// CHECK: dxsa.instruction "breakc" %[[OPERAND_4]] +// CHECK: dxsa.add r<0>, r<0>, vicp<[r<1, >, 0], > +// CHECK: %[[INDEX_3:.*]] = dxsa.index.imm {imm = 1 : i32} +// CHECK: %[[OPERAND_5:.*]] = dxsa.operand %[[INDEX_3]] {mask = 16 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_4:.*]] = dxsa.index.imm {imm = 1 : i32} +// CHECK: %[[OPERAND_6:.*]] = dxsa.operand %[[INDEX_4]] {num_components = 4 : i32, one = 0 : i32, type = 0 : i32} +// CHECK: %[[OPERAND_7:.*]] = dxsa.operand.imm {imm = dense<1> : vector<1xi32>} +// CHECK: dxsa.instruction "iadd" %[[OPERAND_5]], %[[OPERAND_6]], %[[OPERAND_7]] +// CHECK: dxsa.instruction "endloop" +// CHECK: dxsa.add r<0>, r<0>, vpc<0, > +// CHECK: dxsa.mad r<0>, vpc<1, >, l(0x40000000, 0x40000000, 0x40000000, 0x40000000), r<0> +// CHECK: dxsa.mad r<0>, vpc<2, >, l(0x40400000, 0x40400000, 0x40400000, 0x40400000), r<0> +// CHECK: dxsa.mad r<0>, vpc<3, >, l(0x40800000, 0x40800000, 0x40800000, 0x40800000), r<0> +// CHECK: dxsa.add r<1, >, vpc<4, >, vpc<5, > +// CHECK: dxsa.add r<0>, r<0>, r<1, > +// CHECK: %[[INDEX_5:.*]] = dxsa.index.imm {imm = 1 : i32} +// CHECK: %[[OPERAND_8:.*]] = dxsa.operand %[[INDEX_5]] {mask = 16 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_6:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[INDEX_7:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_9:.*]] = dxsa.operand %[[INDEX_6]], %[[INDEX_7]] {num_components = 4 : i32, one = 0 : i32, type = 8 : i32} +// CHECK: dxsa.instruction "mov" %[[OPERAND_8]], %[[OPERAND_9]] +// CHECK: dxsa.add r<1>, vpc<6, >, vpc<7 + r<1, >, > +// CHECK: dxsa.add r<0>, r<0>, r<1> +// CHECK: dxsa.mul o<0>, r<0>, vDomain<> +// CHECK: dxsa.instruction "ret" + diff --git a/mlir/test/Target/DXSA/hlsl/empty.test b/mlir/test/Target/DXSA/hlsl/empty.test new file mode 100644 index 000000000000..3a2987054899 --- /dev/null +++ b/mlir/test/Target/DXSA/hlsl/empty.test @@ -0,0 +1,7 @@ +// RUN: mlir-translate --import-dxsa-bin %S/inputs/empty.shex | FileCheck %s +// NOTE: Assertions have been autogenerated by utils/generate-test-checks.py + + +// CHECK-LABEL: dxsa.dcl_global_flags +// CHECK: dxsa.instruction "ret" + diff --git a/mlir/test/Target/DXSA/hlsl/eval.test b/mlir/test/Target/DXSA/hlsl/eval.test new file mode 100644 index 000000000000..60ea9de77e92 --- /dev/null +++ b/mlir/test/Target/DXSA/hlsl/eval.test @@ -0,0 +1,82 @@ +// RUN: mlir-translate --import-dxsa-bin %S/inputs/eval.shex | FileCheck %s +// NOTE: Assertions have been autogenerated by utils/generate-test-checks.py + + +// CHECK-LABEL: dxsa.dcl_global_flags +// CHECK: dxsa.dcl_input_ps linear v<0> +// CHECK: dxsa.dcl_input_ps constant v<1, > +// CHECK: dxsa.dcl_input_ps linear v<2> +// CHECK: dxsa.dcl_input_ps linear v<3> +// CHECK: dxsa.dcl_input_ps linear v<4> +// CHECK: dxsa.dcl_input_ps linear v<5> +// CHECK: dxsa.dcl_input_ps linear v<6> +// CHECK: dxsa.dcl_input_ps linear v<7> +// CHECK: dxsa.dcl_output o<0> +// CHECK: dxsa.dcl_temps 3 +// CHECK: dxsa.dcl_index_range v<2>, 6 +// CHECK: %[[INDEX_0:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_0:.*]] = dxsa.operand %[[INDEX_0]] {mask = 240 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_1:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_1:.*]] = dxsa.operand %[[INDEX_1]] {num_components = 4 : i32, swizzle = dense<[0, 1, 2, 3]> : vector<4xi32>, type = 1 : i32} +// CHECK: %[[INDEX_2:.*]] = dxsa.index.imm {imm = 1 : i32} +// CHECK: %[[OPERAND_2:.*]] = dxsa.operand %[[INDEX_2]] {num_components = 4 : i32, one = 0 : i32, type = 1 : i32} +// CHECK: dxsa.instruction "eval_sample_index" %[[OPERAND_0]], %[[OPERAND_1]], %[[OPERAND_2]] +// CHECK: %[[INDEX_3:.*]] = dxsa.index.imm {imm = 1 : i32} +// CHECK: %[[OPERAND_3:.*]] = dxsa.operand %[[INDEX_3]] {mask = 240 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_4:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_4:.*]] = dxsa.operand %[[INDEX_4]] {num_components = 4 : i32, swizzle = dense<[0, 1, 2, 3]> : vector<4xi32>, type = 1 : i32} +// CHECK: %[[OPERAND_5:.*]] = dxsa.operand.imm {imm = dense<3> : vector<1xi32>} +// CHECK: dxsa.instruction "eval_sample_index" %[[OPERAND_3]], %[[OPERAND_4]], %[[OPERAND_5]] +// CHECK: dxsa.add r<0>, r<0>, r<1> +// CHECK: %[[INDEX_5:.*]] = dxsa.index.imm {imm = 1 : i32} +// CHECK: %[[OPERAND_6:.*]] = dxsa.operand %[[INDEX_5]] {mask = 240 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_6:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_7:.*]] = dxsa.operand %[[INDEX_6]] {num_components = 4 : i32, swizzle = dense<[0, 1, 2, 3]> : vector<4xi32>, type = 1 : i32} +// CHECK: dxsa.instruction "eval_centroid" %[[OPERAND_6]], %[[OPERAND_7]] +// CHECK: dxsa.add r<0>, r<0>, r<1> +// CHECK: %[[INDEX_7:.*]] = dxsa.index.imm {imm = 1 : i32} +// CHECK: %[[OPERAND_8:.*]] = dxsa.operand %[[INDEX_7]] {mask = 240 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_8:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_9:.*]] = dxsa.operand %[[INDEX_8]] {num_components = 4 : i32, swizzle = dense<[0, 1, 2, 3]> : vector<4xi32>, type = 1 : i32} +// CHECK: %[[OPERAND_10:.*]] = dxsa.operand.imm {imm = dense<[-2, 5, 0, 0]> : vector<4xi32>} +// CHECK: dxsa.instruction "eval_snapped" %[[OPERAND_8]], %[[OPERAND_9]], %[[OPERAND_10]] +// CHECK: dxsa.add r<0>, r<0>, r<1> +// CHECK: %[[INDEX_9:.*]] = dxsa.index.imm {imm = 1 : i32} +// CHECK: %[[OPERAND_11:.*]] = dxsa.operand %[[INDEX_9]] {mask = 16 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_10:.*]] = dxsa.index.imm {imm = 1 : i32} +// CHECK: %[[OPERAND_12:.*]] = dxsa.operand %[[INDEX_10]] {num_components = 4 : i32, one = 1 : i32, type = 1 : i32} +// CHECK: dxsa.instruction "mov" %[[OPERAND_11]], %[[OPERAND_12]] +// CHECK: %[[INDEX_11:.*]] = dxsa.index.imm {imm = 1 : i32} +// CHECK: %[[OPERAND_13:.*]] = dxsa.operand %[[INDEX_11]] {mask = 240 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_12:.*]] = dxsa.index.imm {imm = 1 : i32} +// CHECK: %[[OPERAND_14:.*]] = dxsa.operand %[[INDEX_12]] {num_components = 4 : i32, one = 0 : i32, type = 0 : i32} +// CHECK: %[[INDEX_13:.*]] = dxsa.index.rel.imm %[[OPERAND_14]] {imm = 2 : i32, op = "add"} +// CHECK: %[[OPERAND_15:.*]] = dxsa.operand %[[INDEX_13]] {num_components = 4 : i32, swizzle = dense<[2, 2, 0, 1]> : vector<4xi32>, type = 1 : i32} +// CHECK: %[[INDEX_14:.*]] = dxsa.index.imm {imm = 1 : i32} +// CHECK: %[[OPERAND_16:.*]] = dxsa.operand %[[INDEX_14]] {num_components = 4 : i32, one = 0 : i32, type = 1 : i32} +// CHECK: dxsa.instruction "eval_sample_index" %[[OPERAND_13]], %[[OPERAND_15]], %[[OPERAND_16]] +// CHECK: dxsa.add r<0>, r<0>, r<1> +// CHECK: %[[INDEX_15:.*]] = dxsa.index.imm {imm = 1 : i32} +// CHECK: %[[OPERAND_17:.*]] = dxsa.operand %[[INDEX_15]] {mask = 16 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_16:.*]] = dxsa.index.imm {imm = 1 : i32} +// CHECK: %[[OPERAND_18:.*]] = dxsa.operand %[[INDEX_16]] {num_components = 4 : i32, one = 2 : i32, type = 1 : i32} +// CHECK: dxsa.instruction "mov" %[[OPERAND_17]], %[[OPERAND_18]] +// CHECK: %[[INDEX_17:.*]] = dxsa.index.imm {imm = 2 : i32} +// CHECK: %[[OPERAND_19:.*]] = dxsa.operand %[[INDEX_17]] {mask = 240 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_18:.*]] = dxsa.index.imm {imm = 1 : i32} +// CHECK: %[[OPERAND_20:.*]] = dxsa.operand %[[INDEX_18]] {num_components = 4 : i32, one = 0 : i32, type = 0 : i32} +// CHECK: %[[INDEX_19:.*]] = dxsa.index.rel.imm %[[OPERAND_20]] {imm = 2 : i32, op = "add"} +// CHECK: %[[OPERAND_21:.*]] = dxsa.operand %[[INDEX_19]] {num_components = 4 : i32, swizzle = dense<[0, 1, 2, 3]> : vector<4xi32>, type = 1 : i32} +// CHECK: dxsa.instruction "eval_centroid" %[[OPERAND_19]], %[[OPERAND_21]] +// CHECK: %[[INDEX_20:.*]] = dxsa.index.imm {imm = 1 : i32} +// CHECK: %[[OPERAND_22:.*]] = dxsa.operand %[[INDEX_20]] {mask = 240 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_21:.*]] = dxsa.index.imm {imm = 1 : i32} +// CHECK: %[[OPERAND_23:.*]] = dxsa.operand %[[INDEX_21]] {num_components = 4 : i32, one = 0 : i32, type = 0 : i32} +// CHECK: %[[INDEX_22:.*]] = dxsa.index.rel.imm %[[OPERAND_23]] {imm = 2 : i32, op = "add"} +// CHECK: %[[OPERAND_24:.*]] = dxsa.operand %[[INDEX_22]] {num_components = 4 : i32, swizzle = dense<[0, 1, 2, 3]> : vector<4xi32>, type = 1 : i32} +// CHECK: %[[OPERAND_25:.*]] = dxsa.operand.imm {imm = dense<[-2, 5, 0, 0]> : vector<4xi32>} +// CHECK: dxsa.instruction "eval_snapped" %[[OPERAND_22]], %[[OPERAND_24]], %[[OPERAND_25]] +// CHECK: dxsa.add r<0>, r<0>, r<2> +// CHECK: dxsa.add o<0>, r<1>, r<0> +// CHECK: dxsa.instruction "ret" + diff --git a/mlir/test/Target/DXSA/hlsl/f32f16.test b/mlir/test/Target/DXSA/hlsl/f32f16.test new file mode 100644 index 000000000000..9b2f52c137d5 --- /dev/null +++ b/mlir/test/Target/DXSA/hlsl/f32f16.test @@ -0,0 +1,15 @@ +// RUN: mlir-translate --import-dxsa-bin %S/inputs/f32f16.shex | FileCheck %s +// NOTE: Assertions have been autogenerated by utils/generate-test-checks.py + + +// CHECK-LABEL: dxsa.dcl_global_flags +// CHECK: dxsa.dcl_input_ps linear v<0, > +// CHECK: dxsa.dcl_input_ps constant v<1, > +// CHECK: dxsa.dcl_output o<0> +// CHECK: dxsa.dcl_temps 2 +// CHECK: dxsa.f32tof16 r<0>, v<0, > +// CHECK: dxsa.utof r<0>, r<0> +// CHECK: dxsa.f16tof32 r<1>, v<1, > +// CHECK: dxsa.add o<0>, r<0>, r<1> +// CHECK: dxsa.instruction "ret" + diff --git a/mlir/test/Target/DXSA/hlsl/gather.test b/mlir/test/Target/DXSA/hlsl/gather.test new file mode 100644 index 000000000000..a7bd7ac5a15f --- /dev/null +++ b/mlir/test/Target/DXSA/hlsl/gather.test @@ -0,0 +1,44 @@ +// RUN: mlir-translate --import-dxsa-bin %S/inputs/gather.shex | FileCheck %s +// NOTE: Assertions have been autogenerated by utils/generate-test-checks.py + + +// CHECK-LABEL: dxsa.dcl_global_flags +// CHECK: dxsa.dcl_sampler +// CHECK: dxsa.dcl_resource , , +// CHECK: dxsa.dcl_resource , , +// CHECK: dxsa.dcl_resource , , +// CHECK: dxsa.dcl_input_ps linear v<0> +// CHECK: dxsa.dcl_output o<0> +// CHECK: dxsa.dcl_temps 3 +// CHECK: dxsa.unknown +// CHECK: dxsa.unknown +// CHECK: dxsa.add r<0>, r<0>, r<1> +// CHECK: dxsa.unknown +// CHECK: dxsa.add r<0>, r<0>, r<1> +// CHECK: %[[INDEX_0:.*]] = dxsa.index.imm {imm = 1 : i32} +// CHECK: %[[OPERAND_0:.*]] = dxsa.operand %[[INDEX_0]] {mask = 16 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_1:.*]] = dxsa.index.imm {imm = 2 : i32} +// CHECK: %[[OPERAND_1:.*]] = dxsa.operand %[[INDEX_1]] {num_components = 4 : i32, one = 0 : i32, type = 0 : i32} +// CHECK: dxsa.instruction "check_access_fully_mapped" %[[OPERAND_0]], %[[OPERAND_1]] +// CHECK: dxsa.utof r<1, >, r<1, > +// CHECK: dxsa.add r<0>, r<0>, r<1, > +// CHECK: dxsa.unknown +// CHECK: dxsa.add r<0>, r<0>, r<1> +// CHECK: %[[INDEX_2:.*]] = dxsa.index.imm {imm = 1 : i32} +// CHECK: %[[OPERAND_2:.*]] = dxsa.operand %[[INDEX_2]] {mask = 16 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_3:.*]] = dxsa.index.imm {imm = 2 : i32} +// CHECK: %[[OPERAND_3:.*]] = dxsa.operand %[[INDEX_3]] {num_components = 4 : i32, one = 0 : i32, type = 0 : i32} +// CHECK: dxsa.instruction "check_access_fully_mapped" %[[OPERAND_2]], %[[OPERAND_3]] +// CHECK: dxsa.utof r<1, >, r<1, > +// CHECK: dxsa.add r<0>, r<0>, r<1, > +// CHECK: dxsa.unknown +// CHECK: dxsa.add r<0>, r<0>, r<1> +// CHECK: %[[INDEX_4:.*]] = dxsa.index.imm {imm = 1 : i32} +// CHECK: %[[OPERAND_4:.*]] = dxsa.operand %[[INDEX_4]] {mask = 16 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_5:.*]] = dxsa.index.imm {imm = 2 : i32} +// CHECK: %[[OPERAND_5:.*]] = dxsa.operand %[[INDEX_5]] {num_components = 4 : i32, one = 0 : i32, type = 0 : i32} +// CHECK: dxsa.instruction "check_access_fully_mapped" %[[OPERAND_4]], %[[OPERAND_5]] +// CHECK: dxsa.utof r<1, >, r<1, > +// CHECK: dxsa.add o<0>, r<0>, r<1, > +// CHECK: dxsa.instruction "ret" + diff --git a/mlir/test/Target/DXSA/hlsl/gather_cmp.test b/mlir/test/Target/DXSA/hlsl/gather_cmp.test new file mode 100644 index 000000000000..6f335842becf --- /dev/null +++ b/mlir/test/Target/DXSA/hlsl/gather_cmp.test @@ -0,0 +1,44 @@ +// RUN: mlir-translate --import-dxsa-bin %S/inputs/gather_cmp.shex | FileCheck %s +// NOTE: Assertions have been autogenerated by utils/generate-test-checks.py + + +// CHECK-LABEL: dxsa.dcl_global_flags +// CHECK: dxsa.dcl_sampler +// CHECK: dxsa.dcl_resource , , +// CHECK: dxsa.dcl_resource , , +// CHECK: dxsa.dcl_resource , , +// CHECK: dxsa.dcl_input_ps linear v<0> +// CHECK: dxsa.dcl_output o<0> +// CHECK: dxsa.dcl_temps 3 +// CHECK: dxsa.unknown +// CHECK: dxsa.unknown +// CHECK: dxsa.add r<0>, r<0>, r<1> +// CHECK: dxsa.unknown +// CHECK: dxsa.add r<0>, r<0>, r<1> +// CHECK: %[[INDEX_0:.*]] = dxsa.index.imm {imm = 1 : i32} +// CHECK: %[[OPERAND_0:.*]] = dxsa.operand %[[INDEX_0]] {mask = 16 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_1:.*]] = dxsa.index.imm {imm = 2 : i32} +// CHECK: %[[OPERAND_1:.*]] = dxsa.operand %[[INDEX_1]] {num_components = 4 : i32, one = 0 : i32, type = 0 : i32} +// CHECK: dxsa.instruction "check_access_fully_mapped" %[[OPERAND_0]], %[[OPERAND_1]] +// CHECK: dxsa.utof r<1, >, r<1, > +// CHECK: dxsa.add r<0>, r<0>, r<1, > +// CHECK: dxsa.unknown +// CHECK: dxsa.add r<0>, r<0>, r<1> +// CHECK: %[[INDEX_2:.*]] = dxsa.index.imm {imm = 1 : i32} +// CHECK: %[[OPERAND_2:.*]] = dxsa.operand %[[INDEX_2]] {mask = 16 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_3:.*]] = dxsa.index.imm {imm = 2 : i32} +// CHECK: %[[OPERAND_3:.*]] = dxsa.operand %[[INDEX_3]] {num_components = 4 : i32, one = 0 : i32, type = 0 : i32} +// CHECK: dxsa.instruction "check_access_fully_mapped" %[[OPERAND_2]], %[[OPERAND_3]] +// CHECK: dxsa.utof r<1, >, r<1, > +// CHECK: dxsa.add r<0>, r<0>, r<1, > +// CHECK: dxsa.unknown +// CHECK: dxsa.add r<0>, r<0>, r<1> +// CHECK: %[[INDEX_4:.*]] = dxsa.index.imm {imm = 1 : i32} +// CHECK: %[[OPERAND_4:.*]] = dxsa.operand %[[INDEX_4]] {mask = 16 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_5:.*]] = dxsa.index.imm {imm = 2 : i32} +// CHECK: %[[OPERAND_5:.*]] = dxsa.operand %[[INDEX_5]] {num_components = 4 : i32, one = 0 : i32, type = 0 : i32} +// CHECK: dxsa.instruction "check_access_fully_mapped" %[[OPERAND_4]], %[[OPERAND_5]] +// CHECK: dxsa.utof r<1, >, r<1, > +// CHECK: dxsa.add o<0>, r<0>, r<1, > +// CHECK: dxsa.instruction "ret" + diff --git a/mlir/test/Target/DXSA/hlsl/gather_po.test b/mlir/test/Target/DXSA/hlsl/gather_po.test new file mode 100644 index 000000000000..f4e283497849 --- /dev/null +++ b/mlir/test/Target/DXSA/hlsl/gather_po.test @@ -0,0 +1,80 @@ +// RUN: mlir-translate --import-dxsa-bin %S/inputs/gather_po.shex | FileCheck %s +// NOTE: Assertions have been autogenerated by utils/generate-test-checks.py + + +// CHECK-LABEL: dxsa.dcl_global_flags +// CHECK: dxsa.dcl_sampler +// CHECK: dxsa.dcl_resource , , +// CHECK: dxsa.dcl_resource , , +// CHECK: dxsa.dcl_input_ps linear v<0> +// CHECK: dxsa.dcl_input_ps linear v<1> +// CHECK: dxsa.dcl_output o<0> +// CHECK: dxsa.dcl_temps 6 +// CHECK: dxsa.ftoi r<0>, v<1> +// CHECK: dxsa.unknown +// CHECK: dxsa.unknown +// CHECK: dxsa.ftoi r<2>, v<0> +// CHECK: dxsa.unknown +// CHECK: dxsa.unknown +// CHECK: dxsa.unknown +// CHECK: %[[INDEX_0:.*]] = dxsa.index.imm {imm = 4 : i32} +// CHECK: %[[OPERAND_0:.*]] = dxsa.operand %[[INDEX_0]] {mask = 16 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_1:.*]] = dxsa.index.imm {imm = 4 : i32} +// CHECK: %[[OPERAND_1:.*]] = dxsa.operand %[[INDEX_1]] {num_components = 4 : i32, one = 0 : i32, type = 0 : i32} +// CHECK: dxsa.instruction "check_access_fully_mapped" %[[OPERAND_0]], %[[OPERAND_1]] +// CHECK: dxsa.unknown +// CHECK: %[[INDEX_2:.*]] = dxsa.index.imm {imm = 4 : i32} +// CHECK: %[[OPERAND_2:.*]] = dxsa.operand %[[INDEX_2]] {mask = 32 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_3:.*]] = dxsa.index.imm {imm = 5 : i32} +// CHECK: %[[OPERAND_3:.*]] = dxsa.operand %[[INDEX_3]] {num_components = 4 : i32, one = 0 : i32, type = 0 : i32} +// CHECK: dxsa.instruction "check_access_fully_mapped" %[[OPERAND_2]], %[[OPERAND_3]] +// CHECK: dxsa.and r<4, >, r<4, >, r<4, > +// CHECK: dxsa.unknown +// CHECK: %[[INDEX_4:.*]] = dxsa.index.imm {imm = 4 : i32} +// CHECK: %[[OPERAND_4:.*]] = dxsa.operand %[[INDEX_4]] {mask = 32 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_5:.*]] = dxsa.index.imm {imm = 5 : i32} +// CHECK: %[[OPERAND_5:.*]] = dxsa.operand %[[INDEX_5]] {num_components = 4 : i32, one = 0 : i32, type = 0 : i32} +// CHECK: dxsa.instruction "check_access_fully_mapped" %[[OPERAND_4]], %[[OPERAND_5]] +// CHECK: dxsa.and r<4, >, r<4, >, r<4, > +// CHECK: dxsa.unknown +// CHECK: %[[INDEX_6:.*]] = dxsa.index.imm {imm = 4 : i32} +// CHECK: %[[OPERAND_6:.*]] = dxsa.operand %[[INDEX_6]] {mask = 32 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_7:.*]] = dxsa.index.imm {imm = 5 : i32} +// CHECK: %[[OPERAND_7:.*]] = dxsa.operand %[[INDEX_7]] {num_components = 4 : i32, one = 0 : i32, type = 0 : i32} +// CHECK: dxsa.instruction "check_access_fully_mapped" %[[OPERAND_6]], %[[OPERAND_7]] +// CHECK: dxsa.and r<4, >, r<4, >, r<4, > +// CHECK: dxsa.utof r<4, >, r<4, > +// CHECK: dxsa.add r<1>, r<1>, r<3> +// CHECK: dxsa.add r<1>, r<4, >, r<1> +// CHECK: dxsa.unknown +// CHECK: dxsa.unknown +// CHECK: %[[INDEX_8:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_8:.*]] = dxsa.operand %[[INDEX_8]] {mask = 16 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_9:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_9:.*]] = dxsa.operand %[[INDEX_9]] {num_components = 4 : i32, one = 0 : i32, type = 0 : i32} +// CHECK: dxsa.instruction "check_access_fully_mapped" %[[OPERAND_8]], %[[OPERAND_9]] +// CHECK: %[[INDEX_10:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_10:.*]] = dxsa.operand %[[INDEX_10]] {mask = 32 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_11:.*]] = dxsa.index.imm {imm = 4 : i32} +// CHECK: %[[OPERAND_11:.*]] = dxsa.operand %[[INDEX_11]] {num_components = 4 : i32, one = 0 : i32, type = 0 : i32} +// CHECK: dxsa.instruction "check_access_fully_mapped" %[[OPERAND_10]], %[[OPERAND_11]] +// CHECK: dxsa.and r<0, >, r<0, >, r<0, > +// CHECK: dxsa.unknown +// CHECK: dxsa.unknown +// CHECK: %[[INDEX_12:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_12:.*]] = dxsa.operand %[[INDEX_12]] {mask = 32 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_13:.*]] = dxsa.index.imm {imm = 2 : i32} +// CHECK: %[[OPERAND_13:.*]] = dxsa.operand %[[INDEX_13]] {num_components = 4 : i32, one = 0 : i32, type = 0 : i32} +// CHECK: dxsa.instruction "check_access_fully_mapped" %[[OPERAND_12]], %[[OPERAND_13]] +// CHECK: dxsa.and r<0, >, r<0, >, r<0, > +// CHECK: %[[INDEX_14:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_14:.*]] = dxsa.operand %[[INDEX_14]] {mask = 32 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_15:.*]] = dxsa.index.imm {imm = 4 : i32} +// CHECK: %[[OPERAND_15:.*]] = dxsa.operand %[[INDEX_15]] {num_components = 4 : i32, one = 0 : i32, type = 0 : i32} +// CHECK: dxsa.instruction "check_access_fully_mapped" %[[OPERAND_14]], %[[OPERAND_15]] +// CHECK: dxsa.and r<0, >, r<0, >, r<0, > +// CHECK: dxsa.utof r<0, >, r<0, > +// CHECK: dxsa.add r<1>, r<1>, r<3> +// CHECK: dxsa.add o<0>, r<0, >, r<1> +// CHECK: dxsa.instruction "ret" + diff --git a/mlir/test/Target/DXSA/hlsl/gather_po_cmp.test b/mlir/test/Target/DXSA/hlsl/gather_po_cmp.test new file mode 100644 index 000000000000..8b78501fe31c --- /dev/null +++ b/mlir/test/Target/DXSA/hlsl/gather_po_cmp.test @@ -0,0 +1,80 @@ +// RUN: mlir-translate --import-dxsa-bin %S/inputs/gather_po_cmp.shex | FileCheck %s +// NOTE: Assertions have been autogenerated by utils/generate-test-checks.py + + +// CHECK-LABEL: dxsa.dcl_global_flags +// CHECK: dxsa.dcl_sampler +// CHECK: dxsa.dcl_resource , , +// CHECK: dxsa.dcl_resource , , +// CHECK: dxsa.dcl_input_ps linear v<0> +// CHECK: dxsa.dcl_input_ps linear v<1> +// CHECK: dxsa.dcl_output o<0> +// CHECK: dxsa.dcl_temps 6 +// CHECK: dxsa.ftoi r<0>, v<1> +// CHECK: dxsa.unknown +// CHECK: dxsa.unknown +// CHECK: dxsa.ftoi r<2>, v<0> +// CHECK: dxsa.unknown +// CHECK: dxsa.unknown +// CHECK: dxsa.unknown +// CHECK: %[[INDEX_0:.*]] = dxsa.index.imm {imm = 4 : i32} +// CHECK: %[[OPERAND_0:.*]] = dxsa.operand %[[INDEX_0]] {mask = 16 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_1:.*]] = dxsa.index.imm {imm = 4 : i32} +// CHECK: %[[OPERAND_1:.*]] = dxsa.operand %[[INDEX_1]] {num_components = 4 : i32, one = 0 : i32, type = 0 : i32} +// CHECK: dxsa.instruction "check_access_fully_mapped" %[[OPERAND_0]], %[[OPERAND_1]] +// CHECK: dxsa.unknown +// CHECK: %[[INDEX_2:.*]] = dxsa.index.imm {imm = 4 : i32} +// CHECK: %[[OPERAND_2:.*]] = dxsa.operand %[[INDEX_2]] {mask = 32 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_3:.*]] = dxsa.index.imm {imm = 5 : i32} +// CHECK: %[[OPERAND_3:.*]] = dxsa.operand %[[INDEX_3]] {num_components = 4 : i32, one = 0 : i32, type = 0 : i32} +// CHECK: dxsa.instruction "check_access_fully_mapped" %[[OPERAND_2]], %[[OPERAND_3]] +// CHECK: dxsa.and r<4, >, r<4, >, r<4, > +// CHECK: dxsa.unknown +// CHECK: %[[INDEX_4:.*]] = dxsa.index.imm {imm = 4 : i32} +// CHECK: %[[OPERAND_4:.*]] = dxsa.operand %[[INDEX_4]] {mask = 32 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_5:.*]] = dxsa.index.imm {imm = 5 : i32} +// CHECK: %[[OPERAND_5:.*]] = dxsa.operand %[[INDEX_5]] {num_components = 4 : i32, one = 0 : i32, type = 0 : i32} +// CHECK: dxsa.instruction "check_access_fully_mapped" %[[OPERAND_4]], %[[OPERAND_5]] +// CHECK: dxsa.and r<4, >, r<4, >, r<4, > +// CHECK: dxsa.unknown +// CHECK: %[[INDEX_6:.*]] = dxsa.index.imm {imm = 4 : i32} +// CHECK: %[[OPERAND_6:.*]] = dxsa.operand %[[INDEX_6]] {mask = 32 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_7:.*]] = dxsa.index.imm {imm = 5 : i32} +// CHECK: %[[OPERAND_7:.*]] = dxsa.operand %[[INDEX_7]] {num_components = 4 : i32, one = 0 : i32, type = 0 : i32} +// CHECK: dxsa.instruction "check_access_fully_mapped" %[[OPERAND_6]], %[[OPERAND_7]] +// CHECK: dxsa.and r<4, >, r<4, >, r<4, > +// CHECK: dxsa.utof r<4, >, r<4, > +// CHECK: dxsa.add r<1>, r<1>, r<3> +// CHECK: dxsa.add r<1>, r<4, >, r<1> +// CHECK: dxsa.unknown +// CHECK: dxsa.unknown +// CHECK: %[[INDEX_8:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_8:.*]] = dxsa.operand %[[INDEX_8]] {mask = 16 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_9:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_9:.*]] = dxsa.operand %[[INDEX_9]] {num_components = 4 : i32, one = 0 : i32, type = 0 : i32} +// CHECK: dxsa.instruction "check_access_fully_mapped" %[[OPERAND_8]], %[[OPERAND_9]] +// CHECK: %[[INDEX_10:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_10:.*]] = dxsa.operand %[[INDEX_10]] {mask = 32 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_11:.*]] = dxsa.index.imm {imm = 4 : i32} +// CHECK: %[[OPERAND_11:.*]] = dxsa.operand %[[INDEX_11]] {num_components = 4 : i32, one = 0 : i32, type = 0 : i32} +// CHECK: dxsa.instruction "check_access_fully_mapped" %[[OPERAND_10]], %[[OPERAND_11]] +// CHECK: dxsa.and r<0, >, r<0, >, r<0, > +// CHECK: dxsa.unknown +// CHECK: dxsa.unknown +// CHECK: %[[INDEX_12:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_12:.*]] = dxsa.operand %[[INDEX_12]] {mask = 32 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_13:.*]] = dxsa.index.imm {imm = 2 : i32} +// CHECK: %[[OPERAND_13:.*]] = dxsa.operand %[[INDEX_13]] {num_components = 4 : i32, one = 0 : i32, type = 0 : i32} +// CHECK: dxsa.instruction "check_access_fully_mapped" %[[OPERAND_12]], %[[OPERAND_13]] +// CHECK: dxsa.and r<0, >, r<0, >, r<0, > +// CHECK: %[[INDEX_14:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_14:.*]] = dxsa.operand %[[INDEX_14]] {mask = 32 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_15:.*]] = dxsa.index.imm {imm = 4 : i32} +// CHECK: %[[OPERAND_15:.*]] = dxsa.operand %[[INDEX_15]] {num_components = 4 : i32, one = 0 : i32, type = 0 : i32} +// CHECK: dxsa.instruction "check_access_fully_mapped" %[[OPERAND_14]], %[[OPERAND_15]] +// CHECK: dxsa.and r<0, >, r<0, >, r<0, > +// CHECK: dxsa.utof r<0, >, r<0, > +// CHECK: dxsa.add r<1>, r<1>, r<3> +// CHECK: dxsa.add o<0>, r<0, >, r<1> +// CHECK: dxsa.instruction "ret" + diff --git a/mlir/test/Target/DXSA/hlsl/getdim.test b/mlir/test/Target/DXSA/hlsl/getdim.test new file mode 100644 index 000000000000..49597c3d3436 --- /dev/null +++ b/mlir/test/Target/DXSA/hlsl/getdim.test @@ -0,0 +1,205 @@ +// RUN: mlir-translate --import-dxsa-bin %S/inputs/getdim.shex | FileCheck %s +// NOTE: Assertions have been autogenerated by utils/generate-test-checks.py + + +// CHECK-LABEL: dxsa.dcl_global_flags +// CHECK: dxsa.dcl_resource , , +// CHECK: dxsa.dcl_resource , , +// CHECK: dxsa.dcl_resource , , +// CHECK: dxsa.unknown +// CHECK: dxsa.dcl_uav_typed , +// CHECK: dxsa.dcl_input_ps linear v<0, > +// CHECK: dxsa.dcl_output o<0> +// CHECK: dxsa.dcl_temps 2 +// CHECK: dxsa.ftou r<0, >, v<0, > +// CHECK: dxsa.unknown +// CHECK: %[[INDEX_0:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_0:.*]] = dxsa.operand %[[INDEX_0]] {mask = 32 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_1:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_1:.*]] = dxsa.operand %[[INDEX_1]] {num_components = 4 : i32, one = 1 : i32, type = 0 : i32} +// CHECK: %[[INDEX_2:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_2:.*]] = dxsa.operand %[[INDEX_2]] {num_components = 4 : i32, one = 0 : i32, type = 0 : i32} +// CHECK: dxsa.instruction "iadd" %[[OPERAND_0]], %[[OPERAND_1]], %[[OPERAND_2]] +// CHECK: %[[INDEX_3:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_3:.*]] = dxsa.operand %[[INDEX_3]] {mask = 32 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_4:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_4:.*]] = dxsa.operand %[[INDEX_4]] {num_components = 4 : i32, one = 2 : i32, type = 0 : i32} +// CHECK: %[[INDEX_5:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_5:.*]] = dxsa.operand %[[INDEX_5]] {num_components = 4 : i32, one = 1 : i32, type = 0 : i32} +// CHECK: dxsa.instruction "iadd" %[[OPERAND_3]], %[[OPERAND_4]], %[[OPERAND_5]] +// CHECK: %[[INDEX_6:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_6:.*]] = dxsa.operand %[[INDEX_6]] {mask = 32 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_7:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_7:.*]] = dxsa.operand %[[INDEX_7]] {num_components = 4 : i32, one = 3 : i32, type = 0 : i32} +// CHECK: %[[INDEX_8:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_8:.*]] = dxsa.operand %[[INDEX_8]] {num_components = 4 : i32, one = 1 : i32, type = 0 : i32} +// CHECK: dxsa.instruction "iadd" %[[OPERAND_6]], %[[OPERAND_7]], %[[OPERAND_8]] +// CHECK: dxsa.unknown +// CHECK: %[[INDEX_9:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_9:.*]] = dxsa.operand %[[INDEX_9]] {mask = 64 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_10:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_10:.*]] = dxsa.operand %[[INDEX_10]] {num_components = 4 : i32, one = 0 : i32, type = 0 : i32} +// CHECK: %[[INDEX_11:.*]] = dxsa.index.imm {imm = 1 : i32} +// CHECK: %[[OPERAND_11:.*]] = dxsa.operand %[[INDEX_11]] {num_components = 4 : i32, one = 0 : i32, type = 0 : i32} +// CHECK: dxsa.instruction "iadd" %[[OPERAND_9]], %[[OPERAND_10]], %[[OPERAND_11]] +// CHECK: %[[INDEX_12:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_12:.*]] = dxsa.operand %[[INDEX_12]] {mask = 64 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_13:.*]] = dxsa.index.imm {imm = 1 : i32} +// CHECK: %[[OPERAND_13:.*]] = dxsa.operand %[[INDEX_13]] {num_components = 4 : i32, one = 1 : i32, type = 0 : i32} +// CHECK: %[[INDEX_14:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_14:.*]] = dxsa.operand %[[INDEX_14]] {num_components = 4 : i32, one = 2 : i32, type = 0 : i32} +// CHECK: dxsa.instruction "iadd" %[[OPERAND_12]], %[[OPERAND_13]], %[[OPERAND_14]] +// CHECK: %[[INDEX_15:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_15:.*]] = dxsa.operand %[[INDEX_15]] {mask = 64 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_16:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_16:.*]] = dxsa.operand %[[INDEX_16]] {num_components = 4 : i32, one = 3 : i32, type = 0 : i32} +// CHECK: %[[INDEX_17:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_17:.*]] = dxsa.operand %[[INDEX_17]] {num_components = 4 : i32, one = 2 : i32, type = 0 : i32} +// CHECK: dxsa.instruction "iadd" %[[OPERAND_15]], %[[OPERAND_16]], %[[OPERAND_17]] +// CHECK: dxsa.utof r<0, >, r<0, > +// CHECK: dxsa.add r<0, >, r<0, >, r<0, > +// CHECK: dxsa.unknown +// CHECK: %[[INDEX_18:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_18:.*]] = dxsa.operand %[[INDEX_18]] {mask = 64 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_19:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_19:.*]] = dxsa.operand %[[INDEX_19]] {num_components = 4 : i32, one = 0 : i32, type = 0 : i32} +// CHECK: %[[INDEX_20:.*]] = dxsa.index.imm {imm = 1 : i32} +// CHECK: %[[OPERAND_20:.*]] = dxsa.operand %[[INDEX_20]] {num_components = 4 : i32, one = 0 : i32, type = 0 : i32} +// CHECK: dxsa.instruction "iadd" %[[OPERAND_18]], %[[OPERAND_19]], %[[OPERAND_20]] +// CHECK: %[[INDEX_21:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_21:.*]] = dxsa.operand %[[INDEX_21]] {mask = 64 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_22:.*]] = dxsa.index.imm {imm = 1 : i32} +// CHECK: %[[OPERAND_22:.*]] = dxsa.operand %[[INDEX_22]] {num_components = 4 : i32, one = 1 : i32, type = 0 : i32} +// CHECK: %[[INDEX_23:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_23:.*]] = dxsa.operand %[[INDEX_23]] {num_components = 4 : i32, one = 2 : i32, type = 0 : i32} +// CHECK: dxsa.instruction "iadd" %[[OPERAND_21]], %[[OPERAND_22]], %[[OPERAND_23]] +// CHECK: %[[INDEX_24:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_24:.*]] = dxsa.operand %[[INDEX_24]] {mask = 64 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_25:.*]] = dxsa.index.imm {imm = 1 : i32} +// CHECK: %[[OPERAND_25:.*]] = dxsa.operand %[[INDEX_25]] {num_components = 4 : i32, one = 2 : i32, type = 0 : i32} +// CHECK: %[[INDEX_26:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_26:.*]] = dxsa.operand %[[INDEX_26]] {num_components = 4 : i32, one = 2 : i32, type = 0 : i32} +// CHECK: dxsa.instruction "iadd" %[[OPERAND_24]], %[[OPERAND_25]], %[[OPERAND_26]] +// CHECK: %[[INDEX_27:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_27:.*]] = dxsa.operand %[[INDEX_27]] {mask = 64 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_28:.*]] = dxsa.index.imm {imm = 1 : i32} +// CHECK: %[[OPERAND_28:.*]] = dxsa.operand %[[INDEX_28]] {num_components = 4 : i32, one = 3 : i32, type = 0 : i32} +// CHECK: %[[INDEX_29:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_29:.*]] = dxsa.operand %[[INDEX_29]] {num_components = 4 : i32, one = 2 : i32, type = 0 : i32} +// CHECK: dxsa.instruction "iadd" %[[OPERAND_27]], %[[OPERAND_28]], %[[OPERAND_29]] +// CHECK: dxsa.utof r<0, >, r<0, > +// CHECK: dxsa.add r<0, >, r<0, >, r<0, > +// CHECK: dxsa.unknown +// CHECK: %[[INDEX_30:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_30:.*]] = dxsa.operand %[[INDEX_30]] {mask = 64 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_31:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_31:.*]] = dxsa.operand %[[INDEX_31]] {num_components = 4 : i32, one = 0 : i32, type = 0 : i32} +// CHECK: %[[INDEX_32:.*]] = dxsa.index.imm {imm = 1 : i32} +// CHECK: %[[OPERAND_32:.*]] = dxsa.operand %[[INDEX_32]] {num_components = 4 : i32, one = 0 : i32, type = 0 : i32} +// CHECK: dxsa.instruction "iadd" %[[OPERAND_30]], %[[OPERAND_31]], %[[OPERAND_32]] +// CHECK: %[[INDEX_33:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_33:.*]] = dxsa.operand %[[INDEX_33]] {mask = 64 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_34:.*]] = dxsa.index.imm {imm = 1 : i32} +// CHECK: %[[OPERAND_34:.*]] = dxsa.operand %[[INDEX_34]] {num_components = 4 : i32, one = 1 : i32, type = 0 : i32} +// CHECK: %[[INDEX_35:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_35:.*]] = dxsa.operand %[[INDEX_35]] {num_components = 4 : i32, one = 2 : i32, type = 0 : i32} +// CHECK: dxsa.instruction "iadd" %[[OPERAND_33]], %[[OPERAND_34]], %[[OPERAND_35]] +// CHECK: %[[INDEX_36:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_36:.*]] = dxsa.operand %[[INDEX_36]] {mask = 64 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_37:.*]] = dxsa.index.imm {imm = 1 : i32} +// CHECK: %[[OPERAND_37:.*]] = dxsa.operand %[[INDEX_37]] {num_components = 4 : i32, one = 2 : i32, type = 0 : i32} +// CHECK: %[[INDEX_38:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_38:.*]] = dxsa.operand %[[INDEX_38]] {num_components = 4 : i32, one = 2 : i32, type = 0 : i32} +// CHECK: dxsa.instruction "iadd" %[[OPERAND_36]], %[[OPERAND_37]], %[[OPERAND_38]] +// CHECK: %[[INDEX_39:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_39:.*]] = dxsa.operand %[[INDEX_39]] {mask = 64 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_40:.*]] = dxsa.index.imm {imm = 1 : i32} +// CHECK: %[[OPERAND_40:.*]] = dxsa.operand %[[INDEX_40]] {num_components = 4 : i32, one = 3 : i32, type = 0 : i32} +// CHECK: %[[INDEX_41:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_41:.*]] = dxsa.operand %[[INDEX_41]] {num_components = 4 : i32, one = 2 : i32, type = 0 : i32} +// CHECK: dxsa.instruction "iadd" %[[OPERAND_39]], %[[OPERAND_40]], %[[OPERAND_41]] +// CHECK: dxsa.utof r<0, >, r<0, > +// CHECK: dxsa.add r<0, >, r<0, >, r<0, > +// CHECK: dxsa.unknown +// CHECK: %[[INDEX_42:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_42:.*]] = dxsa.operand %[[INDEX_42]] {mask = 64 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_43:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_43:.*]] = dxsa.operand %[[INDEX_43]] {num_components = 4 : i32, one = 0 : i32, type = 0 : i32} +// CHECK: %[[INDEX_44:.*]] = dxsa.index.imm {imm = 1 : i32} +// CHECK: %[[OPERAND_44:.*]] = dxsa.operand %[[INDEX_44]] {num_components = 4 : i32, one = 0 : i32, type = 0 : i32} +// CHECK: dxsa.instruction "iadd" %[[OPERAND_42]], %[[OPERAND_43]], %[[OPERAND_44]] +// CHECK: %[[INDEX_45:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_45:.*]] = dxsa.operand %[[INDEX_45]] {mask = 64 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_46:.*]] = dxsa.index.imm {imm = 1 : i32} +// CHECK: %[[OPERAND_46:.*]] = dxsa.operand %[[INDEX_46]] {num_components = 4 : i32, one = 1 : i32, type = 0 : i32} +// CHECK: %[[INDEX_47:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_47:.*]] = dxsa.operand %[[INDEX_47]] {num_components = 4 : i32, one = 2 : i32, type = 0 : i32} +// CHECK: dxsa.instruction "iadd" %[[OPERAND_45]], %[[OPERAND_46]], %[[OPERAND_47]] +// CHECK: %[[INDEX_48:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_48:.*]] = dxsa.operand %[[INDEX_48]] {mask = 64 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_49:.*]] = dxsa.index.imm {imm = 1 : i32} +// CHECK: %[[OPERAND_49:.*]] = dxsa.operand %[[INDEX_49]] {num_components = 4 : i32, one = 2 : i32, type = 0 : i32} +// CHECK: %[[INDEX_50:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_50:.*]] = dxsa.operand %[[INDEX_50]] {num_components = 4 : i32, one = 2 : i32, type = 0 : i32} +// CHECK: dxsa.instruction "iadd" %[[OPERAND_48]], %[[OPERAND_49]], %[[OPERAND_50]] +// CHECK: %[[INDEX_51:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_51:.*]] = dxsa.operand %[[INDEX_51]] {mask = 64 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_52:.*]] = dxsa.index.imm {imm = 1 : i32} +// CHECK: %[[OPERAND_52:.*]] = dxsa.operand %[[INDEX_52]] {num_components = 4 : i32, one = 3 : i32, type = 0 : i32} +// CHECK: %[[INDEX_53:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_53:.*]] = dxsa.operand %[[INDEX_53]] {num_components = 4 : i32, one = 2 : i32, type = 0 : i32} +// CHECK: dxsa.instruction "iadd" %[[OPERAND_51]], %[[OPERAND_52]], %[[OPERAND_53]] +// CHECK: %[[INDEX_54:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_54:.*]] = dxsa.operand %[[INDEX_54]] {mask = 128 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_55:.*]] = dxsa.index.imm {imm = 3 : i32} +// CHECK: %[[OPERAND_55:.*]] = dxsa.operand %[[INDEX_55]] {num_components = 4 : i32, one = 0 : i32, type = 7 : i32} +// CHECK: dxsa.instruction "sampleinfo" %[[OPERAND_54]], %[[OPERAND_55]] +// CHECK: %[[INDEX_56:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_56:.*]] = dxsa.operand %[[INDEX_56]] {mask = 64 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_57:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_57:.*]] = dxsa.operand %[[INDEX_57]] {num_components = 4 : i32, one = 3 : i32, type = 0 : i32} +// CHECK: %[[INDEX_58:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_58:.*]] = dxsa.operand %[[INDEX_58]] {num_components = 4 : i32, one = 2 : i32, type = 0 : i32} +// CHECK: dxsa.instruction "iadd" %[[OPERAND_56]], %[[OPERAND_57]], %[[OPERAND_58]] +// CHECK: dxsa.utof r<0, >, r<0, > +// CHECK: dxsa.add r<0, >, r<0, >, r<0, > +// CHECK: dxsa.unknown +// CHECK: %[[INDEX_59:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_59:.*]] = dxsa.operand %[[INDEX_59]] {mask = 16 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_60:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_60:.*]] = dxsa.operand %[[INDEX_60]] {num_components = 4 : i32, one = 0 : i32, type = 0 : i32} +// CHECK: %[[INDEX_61:.*]] = dxsa.index.imm {imm = 1 : i32} +// CHECK: %[[OPERAND_61:.*]] = dxsa.operand %[[INDEX_61]] {num_components = 4 : i32, one = 0 : i32, type = 0 : i32} +// CHECK: dxsa.instruction "iadd" %[[OPERAND_59]], %[[OPERAND_60]], %[[OPERAND_61]] +// CHECK: %[[INDEX_62:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_62:.*]] = dxsa.operand %[[INDEX_62]] {mask = 16 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_63:.*]] = dxsa.index.imm {imm = 1 : i32} +// CHECK: %[[OPERAND_63:.*]] = dxsa.operand %[[INDEX_63]] {num_components = 4 : i32, one = 1 : i32, type = 0 : i32} +// CHECK: %[[INDEX_64:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_64:.*]] = dxsa.operand %[[INDEX_64]] {num_components = 4 : i32, one = 0 : i32, type = 0 : i32} +// CHECK: dxsa.instruction "iadd" %[[OPERAND_62]], %[[OPERAND_63]], %[[OPERAND_64]] +// CHECK: %[[INDEX_65:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_65:.*]] = dxsa.operand %[[INDEX_65]] {mask = 16 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_66:.*]] = dxsa.index.imm {imm = 1 : i32} +// CHECK: %[[OPERAND_66:.*]] = dxsa.operand %[[INDEX_66]] {num_components = 4 : i32, one = 2 : i32, type = 0 : i32} +// CHECK: %[[INDEX_67:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_67:.*]] = dxsa.operand %[[INDEX_67]] {num_components = 4 : i32, one = 0 : i32, type = 0 : i32} +// CHECK: dxsa.instruction "iadd" %[[OPERAND_65]], %[[OPERAND_66]], %[[OPERAND_67]] +// CHECK: %[[INDEX_68:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_68:.*]] = dxsa.operand %[[INDEX_68]] {mask = 16 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_69:.*]] = dxsa.index.imm {imm = 1 : i32} +// CHECK: %[[OPERAND_69:.*]] = dxsa.operand %[[INDEX_69]] {num_components = 4 : i32, one = 3 : i32, type = 0 : i32} +// CHECK: %[[INDEX_70:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_70:.*]] = dxsa.operand %[[INDEX_70]] {num_components = 4 : i32, one = 0 : i32, type = 0 : i32} +// CHECK: dxsa.instruction "iadd" %[[OPERAND_68]], %[[OPERAND_69]], %[[OPERAND_70]] +// CHECK: %[[INDEX_71:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_71:.*]] = dxsa.operand %[[INDEX_71]] {mask = 16 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_72:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_72:.*]] = dxsa.operand %[[INDEX_72]] {num_components = 4 : i32, one = 3 : i32, type = 0 : i32} +// CHECK: %[[INDEX_73:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_73:.*]] = dxsa.operand %[[INDEX_73]] {num_components = 4 : i32, one = 0 : i32, type = 0 : i32} +// CHECK: dxsa.instruction "iadd" %[[OPERAND_71]], %[[OPERAND_72]], %[[OPERAND_73]] +// CHECK: dxsa.utof r<0, >, r<0, > +// CHECK: dxsa.add o<0>, r<0, >, r<0, > +// CHECK: dxsa.instruction "ret" + diff --git a/mlir/test/Target/DXSA/hlsl/gs1.test b/mlir/test/Target/DXSA/hlsl/gs1.test new file mode 100644 index 000000000000..037318da35ef --- /dev/null +++ b/mlir/test/Target/DXSA/hlsl/gs1.test @@ -0,0 +1,56 @@ +// RUN: mlir-translate --import-dxsa-bin %S/inputs/gs1.shex | FileCheck %s +// NOTE: Assertions have been autogenerated by utils/generate-test-checks.py + + +// CHECK-LABEL: dxsa.dcl_global_flags +// CHECK: dxsa.dcl_input v<[6, 0]> +// CHECK: dxsa.dcl_input v<[6, 1], > +// CHECK: dxsa.dcl_input v<[6, 2], > +// CHECK: dxsa.dcl_input v<[6, 3], > +// CHECK: dxsa.dcl_input v<[6, 4], > +// CHECK: dxsa.dcl_input_siv v<[6, 5]>, +// CHECK: dxsa.dcl_temps 1 +// CHECK: dxsa.dcl_index_range v<[6, 2], >, 3 +// CHECK: dxsa.dcl_input_primitive triangle_adj +// CHECK: dxsa.dcl_stream 0 +// CHECK: dxsa.dcl_output_topology trianglestrip +// CHECK: dxsa.dcl_output_siv o<0>, +// CHECK: dxsa.dcl_output o<1, > +// CHECK: dxsa.dcl_output_siv o<2, >, +// CHECK: dxsa.dcl_max_output_vertex_count 18 +// CHECK: dxsa.add r<0, >, v<[1, 0], >, v<[2, 1], > +// CHECK: dxsa.add r<0, >, r<0, >, v<[3, 5], > +// CHECK: dxsa.ftou r<0, >, r<0, > +// CHECK: dxsa.add r<0, >, r<0, >, v<[r<0, >, 2 + r<0, >], > +// CHECK: dxsa.ftou r<0, >, r<0, > +// CHECK: %[[INDEX_0:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_0:.*]] = dxsa.operand %[[INDEX_0]] {mask = 240 : i32, num_components = 4 : i32, type = 2 : i32} +// CHECK: %[[INDEX_1:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_1:.*]] = dxsa.operand %[[INDEX_1]] {num_components = 4 : i32, one = 0 : i32, type = 0 : i32} +// CHECK: %[[INDEX_2:.*]] = dxsa.index.rel %[[OPERAND_1]] +// CHECK: %[[INDEX_3:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_2:.*]] = dxsa.operand %[[INDEX_2]], %[[INDEX_3]] {num_components = 4 : i32, swizzle = dense<[0, 1, 2, 3]> : vector<4xi32>, type = 1 : i32} +// CHECK: dxsa.instruction "mov" %[[OPERAND_0]], %[[OPERAND_2]] +// CHECK: %[[INDEX_4:.*]] = dxsa.index.imm {imm = 1 : i32} +// CHECK: %[[OPERAND_3:.*]] = dxsa.operand %[[INDEX_4]] {mask = 48 : i32, num_components = 4 : i32, type = 2 : i32} +// CHECK: %[[INDEX_5:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_4:.*]] = dxsa.operand %[[INDEX_5]] {num_components = 4 : i32, one = 1 : i32, type = 0 : i32} +// CHECK: %[[INDEX_6:.*]] = dxsa.index.rel %[[OPERAND_4]] +// CHECK: %[[INDEX_7:.*]] = dxsa.index.imm {imm = 1 : i32} +// CHECK: %[[OPERAND_5:.*]] = dxsa.operand %[[INDEX_6]], %[[INDEX_7]] {num_components = 4 : i32, swizzle = dense<[0, 1, 0, 0]> : vector<4xi32>, type = 1 : i32} +// CHECK: dxsa.instruction "mov" %[[OPERAND_3]], %[[OPERAND_5]] +// CHECK: dxsa.add r<0, >, l(0x40400000), v<[r<0, >, 0], > +// CHECK: dxsa.ftou r<0, >, r<0, > +// CHECK: %[[INDEX_8:.*]] = dxsa.index.imm {imm = 2 : i32} +// CHECK: %[[OPERAND_6:.*]] = dxsa.operand %[[INDEX_8]] {mask = 16 : i32, num_components = 4 : i32, type = 2 : i32} +// CHECK: %[[INDEX_9:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_7:.*]] = dxsa.operand %[[INDEX_9]] {num_components = 4 : i32, one = 0 : i32, type = 0 : i32} +// CHECK: dxsa.instruction "mov" %[[OPERAND_6]], %[[OPERAND_7]] +// CHECK: %[[INDEX_10:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_8:.*]] = dxsa.operand %[[INDEX_10]] {num_components = 0 : i32, type = 16 : i32} +// CHECK: dxsa.instruction "emit_stream" %[[OPERAND_8]] +// CHECK: %[[INDEX_11:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_9:.*]] = dxsa.operand %[[INDEX_11]] {num_components = 0 : i32, type = 16 : i32} +// CHECK: dxsa.instruction "cut_stream" %[[OPERAND_9]] +// CHECK: dxsa.instruction "ret" + diff --git a/mlir/test/Target/DXSA/hlsl/gs2.test b/mlir/test/Target/DXSA/hlsl/gs2.test new file mode 100644 index 000000000000..6f434cbb7ba8 --- /dev/null +++ b/mlir/test/Target/DXSA/hlsl/gs2.test @@ -0,0 +1,145 @@ +// RUN: mlir-translate --import-dxsa-bin %S/inputs/gs2.shex | FileCheck %s +// NOTE: Assertions have been autogenerated by utils/generate-test-checks.py + + +// CHECK-LABEL: dxsa.dcl_global_flags +// CHECK: dxsa.dcl_constant_buffer , +// CHECK: dxsa.dcl_input v<[1, 0]> +// CHECK: dxsa.dcl_temps 2 +// CHECK: dxsa.dcl_input_primitive point +// CHECK: dxsa.dcl_stream 0 +// CHECK: dxsa.dcl_output_topology pointlist +// CHECK: dxsa.dcl_output_siv o<0>, +// CHECK: dxsa.dcl_output o<1, > +// CHECK: dxsa.dcl_stream 1 +// CHECK: dxsa.dcl_output_topology pointlist +// CHECK: dxsa.dcl_output o<0, > +// CHECK: dxsa.dcl_output o<1> +// CHECK: dxsa.dcl_output o<2> +// CHECK: dxsa.dcl_output o<3> +// CHECK: dxsa.dcl_output o<4, > +// CHECK: dxsa.dcl_stream 2 +// CHECK: dxsa.dcl_output_topology pointlist +// CHECK: dxsa.dcl_output_siv o<0>, +// CHECK: dxsa.dcl_output o<1, > +// CHECK: dxsa.dcl_max_output_vertex_count 12 +// CHECK: dxsa.ftou r<0, >, v<[0, 0], > +// CHECK: dxsa.mul r<1>, l(0x42300000, 0x42300000, 0x42300000, 0x42300000), v<[0, 0]> +// CHECK: %[[INDEX_0:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[INDEX_1:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_0:.*]] = dxsa.operand %[[INDEX_0]], %[[INDEX_1]] {num_components = 4 : i32, one = 0 : i32, type = 8 : i32} +// CHECK: dxsa.instruction "if" %[[OPERAND_0]] +// CHECK: %[[INDEX_2:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_1:.*]] = dxsa.operand %[[INDEX_2]] {mask = 240 : i32, num_components = 4 : i32, type = 2 : i32} +// CHECK: %[[INDEX_3:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[INDEX_4:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_2:.*]] = dxsa.operand %[[INDEX_3]], %[[INDEX_4]] {num_components = 4 : i32, swizzle = dense<[0, 1, 2, 3]> : vector<4xi32>, type = 1 : i32} +// CHECK: dxsa.instruction "mov" %[[OPERAND_1]], %[[OPERAND_2]] +// CHECK: %[[INDEX_5:.*]] = dxsa.index.imm {imm = 1 : i32} +// CHECK: %[[OPERAND_3:.*]] = dxsa.operand %[[INDEX_5]] {mask = 48 : i32, num_components = 4 : i32, type = 2 : i32} +// CHECK: %[[INDEX_6:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[INDEX_7:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_4:.*]] = dxsa.operand %[[INDEX_6]], %[[INDEX_7]] {num_components = 4 : i32, swizzle = dense<[0, 1, 0, 0]> : vector<4xi32>, type = 1 : i32} +// CHECK: dxsa.instruction "mov" %[[OPERAND_3]], %[[OPERAND_4]] +// CHECK: %[[INDEX_8:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_5:.*]] = dxsa.operand %[[INDEX_8]] {num_components = 0 : i32, type = 16 : i32} +// CHECK: dxsa.instruction "emit_stream" %[[OPERAND_5]] +// CHECK: %[[INDEX_9:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_6:.*]] = dxsa.operand %[[INDEX_9]] {num_components = 0 : i32, type = 16 : i32} +// CHECK: dxsa.instruction "cut_stream" %[[OPERAND_6]] +// CHECK: %[[INDEX_10:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_7:.*]] = dxsa.operand %[[INDEX_10]] {mask = 128 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_11:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_8:.*]] = dxsa.operand %[[INDEX_11]] {num_components = 4 : i32, one = 0 : i32, type = 0 : i32} +// CHECK: dxsa.instruction "mov" %[[OPERAND_7]], %[[OPERAND_8]] +// CHECK: dxsa.instruction "else" +// CHECK: dxsa.ftou r<0, >, v<[0, 0], > +// CHECK: %[[INDEX_12:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_9:.*]] = dxsa.operand %[[INDEX_12]] {mask = 16 : i32, num_components = 4 : i32, type = 2 : i32} +// CHECK: %[[INDEX_13:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_10:.*]] = dxsa.operand %[[INDEX_13]] {num_components = 4 : i32, one = 3 : i32, type = 0 : i32} +// CHECK: dxsa.instruction "mov" %[[OPERAND_9]], %[[OPERAND_10]] +// CHECK: %[[INDEX_14:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_11:.*]] = dxsa.operand %[[INDEX_14]] {mask = 96 : i32, num_components = 4 : i32, type = 2 : i32} +// CHECK: %[[INDEX_15:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_12:.*]] = dxsa.operand %[[INDEX_15]] {num_components = 4 : i32, swizzle = dense<[1, 1, 2, 1]> : vector<4xi32>, type = 0 : i32} +// CHECK: dxsa.instruction "mov" %[[OPERAND_11]], %[[OPERAND_12]] +// CHECK: %[[INDEX_16:.*]] = dxsa.index.imm {imm = 1 : i32} +// CHECK: %[[OPERAND_13:.*]] = dxsa.operand %[[INDEX_16]] {mask = 240 : i32, num_components = 4 : i32, type = 2 : i32} +// CHECK: %[[OPERAND_14:.*]] = dxsa.operand.imm {imm = dense<0> : vector<4xi32>} +// CHECK: dxsa.instruction "mov" %[[OPERAND_13]], %[[OPERAND_14]] +// CHECK: %[[INDEX_17:.*]] = dxsa.index.imm {imm = 2 : i32} +// CHECK: %[[OPERAND_15:.*]] = dxsa.operand %[[INDEX_17]] {mask = 240 : i32, num_components = 4 : i32, type = 2 : i32} +// CHECK: %[[OPERAND_16:.*]] = dxsa.operand.imm {imm = dense<0> : vector<4xi32>} +// CHECK: dxsa.instruction "mov" %[[OPERAND_15]], %[[OPERAND_16]] +// CHECK: %[[INDEX_18:.*]] = dxsa.index.imm {imm = 3 : i32} +// CHECK: %[[OPERAND_17:.*]] = dxsa.operand %[[INDEX_18]] {mask = 240 : i32, num_components = 4 : i32, type = 2 : i32} +// CHECK: %[[INDEX_19:.*]] = dxsa.index.imm {imm = 1 : i32} +// CHECK: %[[OPERAND_18:.*]] = dxsa.operand %[[INDEX_19]] {num_components = 4 : i32, swizzle = dense<[0, 1, 2, 3]> : vector<4xi32>, type = 0 : i32} +// CHECK: dxsa.instruction "mov" %[[OPERAND_17]], %[[OPERAND_18]] +// CHECK: %[[INDEX_20:.*]] = dxsa.index.imm {imm = 4 : i32} +// CHECK: %[[OPERAND_19:.*]] = dxsa.operand %[[INDEX_20]] {mask = 112 : i32, num_components = 4 : i32, type = 2 : i32} +// CHECK: %[[INDEX_21:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_20:.*]] = dxsa.operand %[[INDEX_21]] {num_components = 4 : i32, swizzle = dense<[0, 1, 2, 0]> : vector<4xi32>, type = 0 : i32} +// CHECK: dxsa.instruction "mov" %[[OPERAND_19]], %[[OPERAND_20]] +// CHECK: %[[INDEX_22:.*]] = dxsa.index.imm {imm = 1 : i32} +// CHECK: %[[OPERAND_21:.*]] = dxsa.operand %[[INDEX_22]] {num_components = 0 : i32, type = 16 : i32} +// CHECK: dxsa.instruction "emit_stream" %[[OPERAND_21]] +// CHECK: %[[INDEX_23:.*]] = dxsa.index.imm {imm = 1 : i32} +// CHECK: %[[OPERAND_22:.*]] = dxsa.operand %[[INDEX_23]] {num_components = 0 : i32, type = 16 : i32} +// CHECK: dxsa.instruction "cut_stream" %[[OPERAND_22]] +// CHECK: dxsa.instruction "endif" +// CHECK: %[[INDEX_24:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_23:.*]] = dxsa.operand %[[INDEX_24]] {mask = 16 : i32, num_components = 4 : i32, type = 2 : i32} +// CHECK: %[[INDEX_25:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_24:.*]] = dxsa.operand %[[INDEX_25]] {num_components = 4 : i32, one = 3 : i32, type = 0 : i32} +// CHECK: dxsa.instruction "mov" %[[OPERAND_23]], %[[OPERAND_24]] +// CHECK: %[[INDEX_26:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_25:.*]] = dxsa.operand %[[INDEX_26]] {mask = 96 : i32, num_components = 4 : i32, type = 2 : i32} +// CHECK: %[[INDEX_27:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_26:.*]] = dxsa.operand %[[INDEX_27]] {num_components = 4 : i32, swizzle = dense<[1, 1, 2, 1]> : vector<4xi32>, type = 0 : i32} +// CHECK: dxsa.instruction "mov" %[[OPERAND_25]], %[[OPERAND_26]] +// CHECK: %[[INDEX_28:.*]] = dxsa.index.imm {imm = 1 : i32} +// CHECK: %[[OPERAND_27:.*]] = dxsa.operand %[[INDEX_28]] {mask = 240 : i32, num_components = 4 : i32, type = 2 : i32} +// CHECK: %[[OPERAND_28:.*]] = dxsa.operand.imm {imm = dense<0> : vector<4xi32>} +// CHECK: dxsa.instruction "mov" %[[OPERAND_27]], %[[OPERAND_28]] +// CHECK: %[[INDEX_29:.*]] = dxsa.index.imm {imm = 2 : i32} +// CHECK: %[[OPERAND_29:.*]] = dxsa.operand %[[INDEX_29]] {mask = 240 : i32, num_components = 4 : i32, type = 2 : i32} +// CHECK: %[[OPERAND_30:.*]] = dxsa.operand.imm {imm = dense<0> : vector<4xi32>} +// CHECK: dxsa.instruction "mov" %[[OPERAND_29]], %[[OPERAND_30]] +// CHECK: %[[INDEX_30:.*]] = dxsa.index.imm {imm = 3 : i32} +// CHECK: %[[OPERAND_31:.*]] = dxsa.operand %[[INDEX_30]] {mask = 240 : i32, num_components = 4 : i32, type = 2 : i32} +// CHECK: %[[INDEX_31:.*]] = dxsa.index.imm {imm = 1 : i32} +// CHECK: %[[OPERAND_32:.*]] = dxsa.operand %[[INDEX_31]] {num_components = 4 : i32, swizzle = dense<[0, 1, 2, 3]> : vector<4xi32>, type = 0 : i32} +// CHECK: dxsa.instruction "mov" %[[OPERAND_31]], %[[OPERAND_32]] +// CHECK: %[[INDEX_32:.*]] = dxsa.index.imm {imm = 4 : i32} +// CHECK: %[[OPERAND_33:.*]] = dxsa.operand %[[INDEX_32]] {mask = 112 : i32, num_components = 4 : i32, type = 2 : i32} +// CHECK: %[[INDEX_33:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_34:.*]] = dxsa.operand %[[INDEX_33]] {num_components = 4 : i32, swizzle = dense<[0, 1, 2, 0]> : vector<4xi32>, type = 0 : i32} +// CHECK: dxsa.instruction "mov" %[[OPERAND_33]], %[[OPERAND_34]] +// CHECK: %[[INDEX_34:.*]] = dxsa.index.imm {imm = 1 : i32} +// CHECK: %[[OPERAND_35:.*]] = dxsa.operand %[[INDEX_34]] {num_components = 0 : i32, type = 16 : i32} +// CHECK: dxsa.instruction "emit_stream" %[[OPERAND_35]] +// CHECK: %[[INDEX_35:.*]] = dxsa.index.imm {imm = 1 : i32} +// CHECK: %[[OPERAND_36:.*]] = dxsa.operand %[[INDEX_35]] {num_components = 0 : i32, type = 16 : i32} +// CHECK: dxsa.instruction "cut_stream" %[[OPERAND_36]] +// CHECK: %[[INDEX_36:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_37:.*]] = dxsa.operand %[[INDEX_36]] {mask = 240 : i32, num_components = 4 : i32, type = 2 : i32} +// CHECK: %[[INDEX_37:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[INDEX_38:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_38:.*]] = dxsa.operand %[[INDEX_37]], %[[INDEX_38]] {num_components = 4 : i32, swizzle = dense<[0, 1, 2, 3]> : vector<4xi32>, type = 1 : i32} +// CHECK: dxsa.instruction "mov" %[[OPERAND_37]], %[[OPERAND_38]] +// CHECK: %[[INDEX_39:.*]] = dxsa.index.imm {imm = 1 : i32} +// CHECK: %[[OPERAND_39:.*]] = dxsa.operand %[[INDEX_39]] {mask = 48 : i32, num_components = 4 : i32, type = 2 : i32} +// CHECK: %[[INDEX_40:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[INDEX_41:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_40:.*]] = dxsa.operand %[[INDEX_40]], %[[INDEX_41]] {num_components = 4 : i32, swizzle = dense<[0, 1, 0, 0]> : vector<4xi32>, type = 1 : i32} +// CHECK: dxsa.instruction "mov" %[[OPERAND_39]], %[[OPERAND_40]] +// CHECK: %[[INDEX_42:.*]] = dxsa.index.imm {imm = 2 : i32} +// CHECK: %[[OPERAND_41:.*]] = dxsa.operand %[[INDEX_42]] {num_components = 0 : i32, type = 16 : i32} +// CHECK: dxsa.instruction "emit_stream" %[[OPERAND_41]] +// CHECK: %[[INDEX_43:.*]] = dxsa.index.imm {imm = 2 : i32} +// CHECK: %[[OPERAND_42:.*]] = dxsa.operand %[[INDEX_43]] {num_components = 0 : i32, type = 16 : i32} +// CHECK: dxsa.instruction "cut_stream" %[[OPERAND_42]] +// CHECK: dxsa.instruction "ret" + diff --git a/mlir/test/Target/DXSA/hlsl/half_rcp.test b/mlir/test/Target/DXSA/hlsl/half_rcp.test new file mode 100644 index 000000000000..1fb35a5b9670 --- /dev/null +++ b/mlir/test/Target/DXSA/hlsl/half_rcp.test @@ -0,0 +1,19 @@ +// RUN: mlir-translate --import-dxsa-bin %S/inputs/half_rcp.shex | FileCheck %s +// NOTE: Assertions have been autogenerated by utils/generate-test-checks.py + + +// CHECK-LABEL: dxsa.dcl_global_flags +// CHECK: dxsa.dcl_output o<0, > +// CHECK: dxsa.dcl_temps 1 +// CHECK: %[[INDEX_0:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_0:.*]] = dxsa.operand %[[INDEX_0]] {mask = 16 : i32, min_precision = 1 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[OPERAND_1:.*]] = dxsa.operand.imm {imm = dense<1056964608> : vector<1xi32>} +// CHECK: dxsa.instruction "mov" %[[OPERAND_0]], %[[OPERAND_1]] +// CHECK: dxsa.rcp r<0, min16f, >, r<0, min16f, > +// CHECK: %[[INDEX_1:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_2:.*]] = dxsa.operand %[[INDEX_1]] {mask = 16 : i32, num_components = 4 : i32, type = 2 : i32} +// CHECK: %[[INDEX_2:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_3:.*]] = dxsa.operand %[[INDEX_2]] {min_precision = 1 : i32, num_components = 4 : i32, one = 0 : i32, type = 0 : i32} +// CHECK: dxsa.instruction "mov" %[[OPERAND_2]], %[[OPERAND_3]] +// CHECK: dxsa.instruction "ret" + diff --git a/mlir/test/Target/DXSA/hlsl/hs1.test b/mlir/test/Target/DXSA/hlsl/hs1.test new file mode 100644 index 000000000000..55bc4c04db4c --- /dev/null +++ b/mlir/test/Target/DXSA/hlsl/hs1.test @@ -0,0 +1,136 @@ +// RUN: mlir-translate --import-dxsa-bin %S/inputs/hs1.shex | FileCheck %s +// NOTE: Assertions have been autogenerated by utils/generate-test-checks.py + + +// CHECK-LABEL: dxsa.instruction "hs_decls" +// CHECK: dxsa.dcl_input_control_point_count 16 +// CHECK: dxsa.dcl_output_control_point_count 16 +// CHECK: dxsa.dcl_tessellator_domain domain_quad +// CHECK: dxsa.dcl_tessellator_partitioning partitioning_fractional_odd +// CHECK: dxsa.dcl_tessellator_output_primitive output_triangle_cw +// CHECK: dxsa.dcl_global_flags +// CHECK: dxsa.dcl_constant_buffer , +// CHECK: dxsa.dcl_constant_buffer , +// CHECK: dxsa.dcl_resource , , +// CHECK: dxsa.instruction "hs_control_point_phase" +// CHECK: dxsa.dcl_input vOutputControlPointID +// CHECK: dxsa.dcl_input vPrim +// CHECK: dxsa.dcl_input v<[16, 0], > +// CHECK: dxsa.dcl_output o<0, > +// CHECK: dxsa.dcl_temps 2 +// CHECK: %[[INDEX_0:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_0:.*]] = dxsa.operand %[[INDEX_0]] {mask = 16 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[OPERAND_1:.*]] = dxsa.operand {num_components = 1 : i32, type = 11 : i32} +// CHECK: dxsa.instruction "mov" %[[OPERAND_0]], %[[OPERAND_1]] +// CHECK: dxsa.ftou r<0, >, v<[r<0, >, 0], > +// CHECK: dxsa.ftoi r<1>, v<[r<0, >, 0], > +// CHECK: %[[INDEX_1:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_2:.*]] = dxsa.operand %[[INDEX_1]] {mask = 224 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_2:.*]] = dxsa.index.imm {imm = 1 : i32} +// CHECK: %[[OPERAND_3:.*]] = dxsa.operand %[[INDEX_2]] {num_components = 4 : i32, swizzle = dense<[0, 1, 2, 3]> : vector<4xi32>, type = 0 : i32} +// CHECK: %[[INDEX_3:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[INDEX_4:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_4:.*]] = dxsa.operand %[[INDEX_4]] {num_components = 4 : i32, one = 1 : i32, type = 0 : i32} +// CHECK: %[[INDEX_5:.*]] = dxsa.index.rel.imm %[[OPERAND_4]] {imm = 20 : i32, op = "add"} +// CHECK: %[[OPERAND_5:.*]] = dxsa.operand %[[INDEX_3]], %[[INDEX_5]] {num_components = 4 : i32, swizzle = dense<[3, 0, 1, 2]> : vector<4xi32>, type = 7 : i32} +// CHECK: dxsa.instruction "ld" %[[OPERAND_2]], %[[OPERAND_3]], %[[OPERAND_5]] +// CHECK: dxsa.add r<0, >, r<0, >, v<[r<0, >, 0], > +// CHECK: dxsa.itof r<0, >, cb<[0, 0, 0], vector, > +// CHECK: dxsa.add r<0, >, r<0, >, r<0, > +// CHECK: %[[INDEX_6:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_6:.*]] = dxsa.operand %[[INDEX_6]] {mask = 128 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[OPERAND_7:.*]] = dxsa.operand {num_components = 1 : i32, type = 22 : i32} +// CHECK: dxsa.instruction "mov" %[[OPERAND_6]], %[[OPERAND_7]] +// CHECK: dxsa.add o<0, >, r<0, >, v<[r<0, >, 0], > +// CHECK: dxsa.instruction "ret" +// CHECK: dxsa.instruction "hs_fork_phase" +// CHECK: dxsa.dcl_input vPrim +// CHECK: dxsa.dcl_input vicp<[16, 0], > +// CHECK: dxsa.dcl_output_siv o<0, >, +// CHECK: dxsa.dcl_temps 1 +// CHECK: %[[INDEX_7:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_8:.*]] = dxsa.operand %[[INDEX_7]] {mask = 16 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[OPERAND_9:.*]] = dxsa.operand {num_components = 1 : i32, type = 11 : i32} +// CHECK: dxsa.instruction "mov" %[[OPERAND_8]], %[[OPERAND_9]] +// CHECK: %[[INDEX_8:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_10:.*]] = dxsa.operand %[[INDEX_8]] {mask = 16 : i32, num_components = 4 : i32, type = 2 : i32} +// CHECK: %[[INDEX_9:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_11:.*]] = dxsa.operand %[[INDEX_9]] {num_components = 4 : i32, one = 0 : i32, type = 0 : i32} +// CHECK: %[[INDEX_10:.*]] = dxsa.index.rel %[[OPERAND_11]] +// CHECK: %[[INDEX_11:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_12:.*]] = dxsa.operand %[[INDEX_10]], %[[INDEX_11]] {num_components = 4 : i32, one = 0 : i32, type = 25 : i32} +// CHECK: dxsa.instruction "mov" %[[OPERAND_10]], %[[OPERAND_12]] +// CHECK: dxsa.instruction "ret" +// CHECK: dxsa.instruction "hs_fork_phase" +// CHECK: dxsa.dcl_input vPrim +// CHECK: dxsa.dcl_input vicp<[16, 0], > +// CHECK: dxsa.dcl_output_siv o<1, >, +// CHECK: dxsa.dcl_temps 1 +// CHECK: %[[INDEX_12:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_13:.*]] = dxsa.operand %[[INDEX_12]] {mask = 16 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[OPERAND_14:.*]] = dxsa.operand {num_components = 1 : i32, type = 11 : i32} +// CHECK: dxsa.instruction "mov" %[[OPERAND_13]], %[[OPERAND_14]] +// CHECK: %[[INDEX_13:.*]] = dxsa.index.imm {imm = 1 : i32} +// CHECK: %[[OPERAND_15:.*]] = dxsa.operand %[[INDEX_13]] {mask = 16 : i32, num_components = 4 : i32, type = 2 : i32} +// CHECK: %[[INDEX_14:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_16:.*]] = dxsa.operand %[[INDEX_14]] {num_components = 4 : i32, one = 0 : i32, type = 0 : i32} +// CHECK: %[[INDEX_15:.*]] = dxsa.index.rel %[[OPERAND_16]] +// CHECK: %[[INDEX_16:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_17:.*]] = dxsa.operand %[[INDEX_15]], %[[INDEX_16]] {num_components = 4 : i32, one = 1 : i32, type = 25 : i32} +// CHECK: dxsa.instruction "mov" %[[OPERAND_15]], %[[OPERAND_17]] +// CHECK: dxsa.instruction "ret" +// CHECK: dxsa.instruction "hs_fork_phase" +// CHECK: dxsa.dcl_input vPrim +// CHECK: dxsa.dcl_input vicp<[16, 0], > +// CHECK: dxsa.dcl_output_siv o<2, >, +// CHECK: dxsa.dcl_temps 1 +// CHECK: %[[INDEX_17:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_18:.*]] = dxsa.operand %[[INDEX_17]] {mask = 16 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[OPERAND_19:.*]] = dxsa.operand {num_components = 1 : i32, type = 11 : i32} +// CHECK: dxsa.instruction "mov" %[[OPERAND_18]], %[[OPERAND_19]] +// CHECK: %[[INDEX_18:.*]] = dxsa.index.imm {imm = 2 : i32} +// CHECK: %[[OPERAND_20:.*]] = dxsa.operand %[[INDEX_18]] {mask = 16 : i32, num_components = 4 : i32, type = 2 : i32} +// CHECK: %[[INDEX_19:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_21:.*]] = dxsa.operand %[[INDEX_19]] {num_components = 4 : i32, one = 0 : i32, type = 0 : i32} +// CHECK: %[[INDEX_20:.*]] = dxsa.index.rel %[[OPERAND_21]] +// CHECK: %[[INDEX_21:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_22:.*]] = dxsa.operand %[[INDEX_20]], %[[INDEX_21]] {num_components = 4 : i32, one = 2 : i32, type = 25 : i32} +// CHECK: dxsa.instruction "mov" %[[OPERAND_20]], %[[OPERAND_22]] +// CHECK: dxsa.instruction "ret" +// CHECK: dxsa.instruction "hs_fork_phase" +// CHECK: dxsa.dcl_output_siv o<3, >, +// CHECK: %[[INDEX_22:.*]] = dxsa.index.imm {imm = 3 : i32} +// CHECK: %[[OPERAND_23:.*]] = dxsa.operand %[[INDEX_22]] {mask = 16 : i32, num_components = 4 : i32, type = 2 : i32} +// CHECK: %[[OPERAND_24:.*]] = dxsa.operand.imm {imm = dense<0> : vector<1xi32>} +// CHECK: dxsa.instruction "mov" %[[OPERAND_23]], %[[OPERAND_24]] +// CHECK: dxsa.instruction "ret" +// CHECK: dxsa.instruction "hs_fork_phase" +// CHECK: dxsa.dcl_input vPrim +// CHECK: dxsa.dcl_input vicp<[16, 0], > +// CHECK: dxsa.dcl_output_siv o<4, >, +// CHECK: dxsa.dcl_temps 1 +// CHECK: %[[INDEX_23:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_25:.*]] = dxsa.operand %[[INDEX_23]] {mask = 16 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[OPERAND_26:.*]] = dxsa.operand {num_components = 1 : i32, type = 11 : i32} +// CHECK: dxsa.instruction "mov" %[[OPERAND_25]], %[[OPERAND_26]] +// CHECK: %[[INDEX_24:.*]] = dxsa.index.imm {imm = 4 : i32} +// CHECK: %[[OPERAND_27:.*]] = dxsa.operand %[[INDEX_24]] {mask = 16 : i32, num_components = 4 : i32, type = 2 : i32} +// CHECK: %[[INDEX_25:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_28:.*]] = dxsa.operand %[[INDEX_25]] {num_components = 4 : i32, one = 0 : i32, type = 0 : i32} +// CHECK: %[[INDEX_26:.*]] = dxsa.index.rel %[[OPERAND_28]] +// CHECK: %[[INDEX_27:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_29:.*]] = dxsa.operand %[[INDEX_26]], %[[INDEX_27]] {num_components = 4 : i32, one = 2 : i32, type = 25 : i32} +// CHECK: dxsa.instruction "mov" %[[OPERAND_27]], %[[OPERAND_29]] +// CHECK: dxsa.instruction "ret" +// CHECK: dxsa.instruction "hs_fork_phase" +// CHECK: dxsa.dcl_input vPrim +// CHECK: dxsa.dcl_input vicp<[16, 0], > +// CHECK: dxsa.dcl_output_siv o<5, >, +// CHECK: dxsa.dcl_temps 1 +// CHECK: %[[INDEX_28:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_30:.*]] = dxsa.operand %[[INDEX_28]] {mask = 16 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[OPERAND_31:.*]] = dxsa.operand {num_components = 1 : i32, type = 11 : i32} +// CHECK: dxsa.instruction "mov" %[[OPERAND_30]], %[[OPERAND_31]] +// CHECK: dxsa.add o<5, >, cb<[1, 2, 14], vector, >, vicp<[r<0, >, 0], > +// CHECK: dxsa.instruction "ret" + diff --git a/mlir/test/Target/DXSA/hlsl/hs2.test b/mlir/test/Target/DXSA/hlsl/hs2.test new file mode 100644 index 000000000000..3b70fbfb26dc --- /dev/null +++ b/mlir/test/Target/DXSA/hlsl/hs2.test @@ -0,0 +1,125 @@ +// RUN: mlir-translate --import-dxsa-bin %S/inputs/hs2.shex | FileCheck %s +// NOTE: Assertions have been autogenerated by utils/generate-test-checks.py + + +// CHECK-LABEL: dxsa.instruction "hs_decls" +// CHECK: dxsa.dcl_input_control_point_count 32 +// CHECK: dxsa.dcl_output_control_point_count 16 +// CHECK: dxsa.dcl_tessellator_domain domain_quad +// CHECK: dxsa.dcl_tessellator_partitioning partitioning_fractional_odd +// CHECK: dxsa.dcl_tessellator_output_primitive output_triangle_cw +// CHECK: dxsa.dcl_hs_max_tessfactor 3.000000e+00 +// CHECK: dxsa.dcl_global_flags +// CHECK: dxsa.instruction "hs_control_point_phase" +// CHECK: dxsa.dcl_input vOutputControlPointID +// CHECK: dxsa.dcl_input vPrim +// CHECK: dxsa.dcl_input v<[32, 0]> +// CHECK: dxsa.dcl_output o<0> +// CHECK: dxsa.dcl_temps 1 +// CHECK: %[[INDEX_0:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_0:.*]] = dxsa.operand %[[INDEX_0]] {mask = 16 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[OPERAND_1:.*]] = dxsa.operand {num_components = 1 : i32, type = 22 : i32} +// CHECK: dxsa.instruction "mov" %[[OPERAND_0]], %[[OPERAND_1]] +// CHECK: %[[INDEX_1:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_2:.*]] = dxsa.operand %[[INDEX_1]] {mask = 32 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[OPERAND_3:.*]] = dxsa.operand {num_components = 1 : i32, type = 11 : i32} +// CHECK: dxsa.instruction "mov" %[[OPERAND_2]], %[[OPERAND_3]] +// CHECK: dxsa.add o<0>, v<[r<0, >, 0]>, v<[r<0, >, 0]> +// CHECK: dxsa.instruction "ret" +// CHECK: dxsa.instruction "hs_fork_phase" +// CHECK: dxsa.dcl_hs_fork_phase_instance_count 4 +// CHECK: dxsa.dcl_input vPrim +// CHECK: dxsa.dcl_input vForkInstanceID +// CHECK: dxsa.dcl_input vicp<[32, 0], > +// CHECK: dxsa.dcl_output_siv o<0, >, +// CHECK: dxsa.dcl_output_siv o<1, >, +// CHECK: dxsa.dcl_output_siv o<2, >, +// CHECK: dxsa.dcl_output_siv o<3, >, +// CHECK: dxsa.dcl_temps 1 +// CHECK: dxsa.dcl_index_range o<0, >, 4 +// CHECK: %[[INDEX_2:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_4:.*]] = dxsa.operand %[[INDEX_2]] {mask = 16 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[OPERAND_5:.*]] = dxsa.operand {num_components = 1 : i32, type = 11 : i32} +// CHECK: dxsa.instruction "mov" %[[OPERAND_4]], %[[OPERAND_5]] +// CHECK: dxsa.min r<0, >, l(0x40400000), vicp<[r<0, >, 0], > +// CHECK: %[[INDEX_3:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_6:.*]] = dxsa.operand %[[INDEX_3]] {mask = 32 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[OPERAND_7:.*]] = dxsa.operand {num_components = 4 : i32, one = 0 : i32, type = 23 : i32} +// CHECK: dxsa.instruction "mov" %[[OPERAND_6]], %[[OPERAND_7]] +// CHECK: %[[INDEX_4:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_8:.*]] = dxsa.operand %[[INDEX_4]] {num_components = 4 : i32, one = 1 : i32, type = 0 : i32} +// CHECK: %[[INDEX_5:.*]] = dxsa.index.rel %[[OPERAND_8]] +// CHECK: %[[OPERAND_9:.*]] = dxsa.operand %[[INDEX_5]] {mask = 16 : i32, num_components = 4 : i32, type = 2 : i32} +// CHECK: %[[INDEX_6:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_10:.*]] = dxsa.operand %[[INDEX_6]] {num_components = 4 : i32, one = 0 : i32, type = 0 : i32} +// CHECK: dxsa.instruction "mov" %[[OPERAND_9]], %[[OPERAND_10]] +// CHECK: dxsa.instruction "ret" +// CHECK: dxsa.instruction "hs_fork_phase" +// CHECK: dxsa.dcl_input vPrim +// CHECK: dxsa.dcl_input vicp<[32, 0], > +// CHECK: dxsa.dcl_input vocp<[16, 0], > +// CHECK: dxsa.dcl_output o<6> +// CHECK: dxsa.dcl_temps 3 +// CHECK: %[[INDEX_7:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_11:.*]] = dxsa.operand %[[INDEX_7]] {mask = 240 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[OPERAND_12:.*]] = dxsa.operand.imm {imm = dense<0> : vector<4xi32>} +// CHECK: dxsa.instruction "mov" %[[OPERAND_11]], %[[OPERAND_12]] +// CHECK: %[[INDEX_8:.*]] = dxsa.index.imm {imm = 1 : i32} +// CHECK: %[[OPERAND_13:.*]] = dxsa.operand %[[INDEX_8]] {mask = 16 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[OPERAND_14:.*]] = dxsa.operand.imm {imm = dense<0> : vector<1xi32>} +// CHECK: dxsa.instruction "mov" %[[OPERAND_13]], %[[OPERAND_14]] +// CHECK: dxsa.instruction "loop" +// CHECK: dxsa.ige r<1, >, r<1, >, l(0x20) +// CHECK: %[[INDEX_9:.*]] = dxsa.index.imm {imm = 1 : i32} +// CHECK: %[[OPERAND_15:.*]] = dxsa.operand %[[INDEX_9]] {num_components = 4 : i32, one = 1 : i32, type = 0 : i32} +// CHECK: dxsa.instruction "breakc" %[[OPERAND_15]] +// CHECK: %[[INDEX_10:.*]] = dxsa.index.imm {imm = 1 : i32} +// CHECK: %[[OPERAND_16:.*]] = dxsa.operand %[[INDEX_10]] {mask = 32 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[OPERAND_17:.*]] = dxsa.operand {num_components = 1 : i32, type = 11 : i32} +// CHECK: dxsa.instruction "mov" %[[OPERAND_16]], %[[OPERAND_17]] +// CHECK: dxsa.mad r<1, >, vicp<[r<1, >, 0], >, vicp<[r<1, >, 0], >, vicp<[r<1, >, 0], > +// CHECK: dxsa.add r<2>, r<1, >, r<0> +// CHECK: dxsa.ushr r<1, >, r<1, >, l(0x1) +// CHECK: dxsa.add r<0>, r<2>, vocp<[r<1, >, 0], > +// CHECK: %[[INDEX_11:.*]] = dxsa.index.imm {imm = 1 : i32} +// CHECK: %[[OPERAND_18:.*]] = dxsa.operand %[[INDEX_11]] {mask = 16 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_12:.*]] = dxsa.index.imm {imm = 1 : i32} +// CHECK: %[[OPERAND_19:.*]] = dxsa.operand %[[INDEX_12]] {num_components = 4 : i32, one = 0 : i32, type = 0 : i32} +// CHECK: %[[OPERAND_20:.*]] = dxsa.operand.imm {imm = dense<1> : vector<1xi32>} +// CHECK: dxsa.instruction "iadd" %[[OPERAND_18]], %[[OPERAND_19]], %[[OPERAND_20]] +// CHECK: dxsa.instruction "endloop" +// CHECK: %[[INDEX_13:.*]] = dxsa.index.imm {imm = 6 : i32} +// CHECK: %[[OPERAND_21:.*]] = dxsa.operand %[[INDEX_13]] {mask = 240 : i32, num_components = 4 : i32, type = 2 : i32} +// CHECK: %[[INDEX_14:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_22:.*]] = dxsa.operand %[[INDEX_14]] {num_components = 4 : i32, swizzle = dense<[0, 1, 2, 3]> : vector<4xi32>, type = 0 : i32} +// CHECK: dxsa.instruction "mov" %[[OPERAND_21]], %[[OPERAND_22]] +// CHECK: dxsa.instruction "ret" +// CHECK: dxsa.instruction "hs_join_phase" +// CHECK: dxsa.dcl_hs_join_phase_instance_count 2 +// CHECK: dxsa.dcl_input vpc<6, > +// CHECK: dxsa.dcl_input vPrim +// CHECK: dxsa.dcl_input vJoinInstanceID +// CHECK: dxsa.dcl_input vicp<[32, 0], > +// CHECK: dxsa.dcl_output_siv o<4, >, +// CHECK: dxsa.dcl_output_siv o<5, >, +// CHECK: dxsa.dcl_temps 1 +// CHECK: dxsa.dcl_index_range o<4, >, 2 +// CHECK: %[[INDEX_15:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_23:.*]] = dxsa.operand %[[INDEX_15]] {mask = 16 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[OPERAND_24:.*]] = dxsa.operand {num_components = 1 : i32, type = 11 : i32} +// CHECK: dxsa.instruction "mov" %[[OPERAND_23]], %[[OPERAND_24]] +// CHECK: dxsa.add r<0, >, vicp<[r<0, >, 0], >, vpc<6, > +// CHECK: dxsa.min r<0, >, r<0, >, l(0x40400000) +// CHECK: %[[INDEX_16:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_25:.*]] = dxsa.operand %[[INDEX_16]] {mask = 32 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[OPERAND_26:.*]] = dxsa.operand {num_components = 4 : i32, one = 0 : i32, type = 24 : i32} +// CHECK: dxsa.instruction "mov" %[[OPERAND_25]], %[[OPERAND_26]] +// CHECK: %[[INDEX_17:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_27:.*]] = dxsa.operand %[[INDEX_17]] {num_components = 4 : i32, one = 1 : i32, type = 0 : i32} +// CHECK: %[[INDEX_18:.*]] = dxsa.index.rel.imm %[[OPERAND_27]] {imm = 4 : i32, op = "add"} +// CHECK: %[[OPERAND_28:.*]] = dxsa.operand %[[INDEX_18]] {mask = 16 : i32, num_components = 4 : i32, type = 2 : i32} +// CHECK: %[[INDEX_19:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_29:.*]] = dxsa.operand %[[INDEX_19]] {num_components = 4 : i32, one = 0 : i32, type = 0 : i32} +// CHECK: dxsa.instruction "mov" %[[OPERAND_28]], %[[OPERAND_29]] +// CHECK: dxsa.instruction "ret" + diff --git a/mlir/test/Target/DXSA/hlsl/icb1.test b/mlir/test/Target/DXSA/hlsl/icb1.test new file mode 100644 index 000000000000..72bd40ba022b --- /dev/null +++ b/mlir/test/Target/DXSA/hlsl/icb1.test @@ -0,0 +1,25 @@ +// RUN: mlir-translate --import-dxsa-bin %S/inputs/icb1.shex | FileCheck %s +// NOTE: Assertions have been autogenerated by utils/generate-test-checks.py + + +// CHECK-LABEL: dxsa.dcl_global_flags +// CHECK: dxsa.unknown +// CHECK: dxsa.dcl_input_ps linear v<0> +// CHECK: dxsa.dcl_input_ps linear v<1> +// CHECK: dxsa.dcl_input_ps linear v<2> +// CHECK: dxsa.dcl_input_ps linear v<3> +// CHECK: dxsa.dcl_input_ps constant v<4, > +// CHECK: dxsa.dcl_output o<0, > +// CHECK: dxsa.dcl_temps 2 +// CHECK: %[[INDEX_0:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_0:.*]] = dxsa.operand %[[INDEX_0]] {mask = 48 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_1:.*]] = dxsa.index.imm {imm = 4 : i32} +// CHECK: %[[OPERAND_1:.*]] = dxsa.operand %[[INDEX_1]] {num_components = 4 : i32, swizzle = dense<[1, 0, 1, 1]> : vector<4xi32>, type = 1 : i32} +// CHECK: dxsa.instruction "mov" %[[OPERAND_0]], %[[OPERAND_1]] +// CHECK: dxsa.dp4 r<1, >, v<0>, icb>, vector> +// CHECK: dxsa.dp4 r<1, >, v<1>, icb>, vector> +// CHECK: dxsa.dp4 r<1, >, v<2>, icb>, vector> +// CHECK: dxsa.dp4 r<1, >, v<3>, icb>, vector> +// CHECK: dxsa.dp4 o<0, >, r<1>, icb>, vector> +// CHECK: dxsa.instruction "ret" + diff --git a/mlir/test/Target/DXSA/hlsl/if1.test b/mlir/test/Target/DXSA/hlsl/if1.test new file mode 100644 index 000000000000..63b28be307c7 --- /dev/null +++ b/mlir/test/Target/DXSA/hlsl/if1.test @@ -0,0 +1,29 @@ +// RUN: mlir-translate --import-dxsa-bin %S/inputs/if1.shex | FileCheck %s +// NOTE: Assertions have been autogenerated by utils/generate-test-checks.py + + +// CHECK-LABEL: dxsa.dcl_global_flags +// CHECK: dxsa.dcl_input_ps linear v<0, > +// CHECK: dxsa.dcl_input_ps constant v<1, > +// CHECK: dxsa.dcl_output o<0, > +// CHECK: dxsa.dcl_temps 1 +// CHECK: dxsa.ieq r<0, >, v<1, >, l(0x1) +// CHECK: %[[INDEX_0:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_0:.*]] = dxsa.operand %[[INDEX_0]] {num_components = 4 : i32, one = 0 : i32, type = 0 : i32} +// CHECK: dxsa.instruction "if" %[[OPERAND_0]] +// CHECK: %[[INDEX_1:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_1:.*]] = dxsa.operand %[[INDEX_1]] {mask = 16 : i32, num_components = 4 : i32, type = 2 : i32} +// CHECK: %[[INDEX_2:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_2:.*]] = dxsa.operand %[[INDEX_2]] {num_components = 4 : i32, one = 0 : i32, type = 1 : i32} +// CHECK: dxsa.instruction "mov" %[[OPERAND_1]], %[[OPERAND_2]] +// CHECK: dxsa.instruction "ret" +// CHECK: dxsa.instruction "else" +// CHECK: %[[INDEX_3:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_3:.*]] = dxsa.operand %[[INDEX_3]] {mask = 16 : i32, num_components = 4 : i32, type = 2 : i32} +// CHECK: %[[INDEX_4:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_4:.*]] = dxsa.operand %[[INDEX_4]] {num_components = 4 : i32, one = 1 : i32, type = 1 : i32} +// CHECK: dxsa.instruction "mov" %[[OPERAND_3]], %[[OPERAND_4]] +// CHECK: dxsa.instruction "ret" +// CHECK: dxsa.instruction "endif" +// CHECK: dxsa.instruction "ret" + diff --git a/mlir/test/Target/DXSA/hlsl/if2.test b/mlir/test/Target/DXSA/hlsl/if2.test new file mode 100644 index 000000000000..435b9fc74987 --- /dev/null +++ b/mlir/test/Target/DXSA/hlsl/if2.test @@ -0,0 +1,27 @@ +// RUN: mlir-translate --import-dxsa-bin %S/inputs/if2.shex | FileCheck %s +// NOTE: Assertions have been autogenerated by utils/generate-test-checks.py + + +// CHECK-LABEL: dxsa.dcl_global_flags +// CHECK: dxsa.dcl_input_ps linear v<0, > +// CHECK: dxsa.dcl_input_ps constant v<1, > +// CHECK: dxsa.dcl_output o<0, > +// CHECK: dxsa.dcl_temps 1 +// CHECK: dxsa.ieq r<0, >, v<1, >, l(0x1) +// CHECK: %[[INDEX_0:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_0:.*]] = dxsa.operand %[[INDEX_0]] {num_components = 4 : i32, one = 0 : i32, type = 0 : i32} +// CHECK: dxsa.instruction "if" %[[OPERAND_0]] +// CHECK: %[[INDEX_1:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_1:.*]] = dxsa.operand %[[INDEX_1]] {mask = 16 : i32, num_components = 4 : i32, type = 2 : i32} +// CHECK: %[[INDEX_2:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_2:.*]] = dxsa.operand %[[INDEX_2]] {num_components = 4 : i32, one = 0 : i32, type = 1 : i32} +// CHECK: dxsa.instruction "mov" %[[OPERAND_1]], %[[OPERAND_2]] +// CHECK: dxsa.instruction "ret" +// CHECK: dxsa.instruction "endif" +// CHECK: %[[INDEX_3:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_3:.*]] = dxsa.operand %[[INDEX_3]] {mask = 16 : i32, num_components = 4 : i32, type = 2 : i32} +// CHECK: %[[INDEX_4:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_4:.*]] = dxsa.operand %[[INDEX_4]] {num_components = 4 : i32, one = 1 : i32, type = 1 : i32} +// CHECK: dxsa.instruction "mov" %[[OPERAND_3]], %[[OPERAND_4]] +// CHECK: dxsa.instruction "ret" + diff --git a/mlir/test/Target/DXSA/hlsl/if3.test b/mlir/test/Target/DXSA/hlsl/if3.test new file mode 100644 index 000000000000..dc6e6f1343e4 --- /dev/null +++ b/mlir/test/Target/DXSA/hlsl/if3.test @@ -0,0 +1,19 @@ +// RUN: mlir-translate --import-dxsa-bin %S/inputs/if3.shex | FileCheck %s +// NOTE: Assertions have been autogenerated by utils/generate-test-checks.py + + +// CHECK-LABEL: dxsa.dcl_global_flags +// CHECK: dxsa.dcl_input_ps linear v<0, > +// CHECK: dxsa.dcl_input_ps constant v<1, > +// CHECK: dxsa.dcl_output o<0, > +// CHECK: dxsa.dcl_temps 1 +// CHECK: dxsa.ieq r<0, >, v<1, >, l(0x1) +// CHECK: %[[INDEX_0:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_0:.*]] = dxsa.operand %[[INDEX_0]] {num_components = 4 : i32, one = 0 : i32, type = 0 : i32} +// CHECK: dxsa.instruction "if" %[[OPERAND_0]] +// CHECK: dxsa.add o<0, >, v<0, >, l(0x40A00000) +// CHECK: dxsa.instruction "else" +// CHECK: dxsa.add o<0, >, v<0, >, l(0xC29A0000) +// CHECK: dxsa.instruction "endif" +// CHECK: dxsa.instruction "ret" + diff --git a/mlir/test/Target/DXSA/hlsl/if4.test b/mlir/test/Target/DXSA/hlsl/if4.test new file mode 100644 index 000000000000..93550ab4435e --- /dev/null +++ b/mlir/test/Target/DXSA/hlsl/if4.test @@ -0,0 +1,25 @@ +// RUN: mlir-translate --import-dxsa-bin %S/inputs/if4.shex | FileCheck %s +// NOTE: Assertions have been autogenerated by utils/generate-test-checks.py + + +// CHECK-LABEL: dxsa.dcl_global_flags +// CHECK: dxsa.dcl_input_ps linear v<0, > +// CHECK: dxsa.dcl_input_ps constant v<1, > +// CHECK: dxsa.dcl_output o<0, > +// CHECK: dxsa.dcl_temps 1 +// CHECK: dxsa.ieq r<0, >, v<1, >, l(0x1) +// CHECK: %[[INDEX_0:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_0:.*]] = dxsa.operand %[[INDEX_0]] {num_components = 4 : i32, one = 0 : i32, type = 0 : i32} +// CHECK: dxsa.instruction "if" %[[OPERAND_0]] +// CHECK: %[[INDEX_1:.*]] = dxsa.index.imm {imm = 1 : i32} +// CHECK: %[[OPERAND_1:.*]] = dxsa.operand %[[INDEX_1]] {num_components = 4 : i32, one = 1 : i32, type = 1 : i32} +// CHECK: dxsa.instruction "if" %[[OPERAND_1]] +// CHECK: dxsa.add o<0, >, v<0, >, l(0x40A00000) +// CHECK: dxsa.instruction "else" +// CHECK: dxsa.add o<0, >, v<0, >, l(0xC0000000) +// CHECK: dxsa.instruction "endif" +// CHECK: dxsa.instruction "else" +// CHECK: dxsa.add o<0, >, v<0, >, l(0xC29A0000) +// CHECK: dxsa.instruction "endif" +// CHECK: dxsa.instruction "ret" + diff --git a/mlir/test/Target/DXSA/hlsl/if5.test b/mlir/test/Target/DXSA/hlsl/if5.test new file mode 100644 index 000000000000..ae114b247d6e --- /dev/null +++ b/mlir/test/Target/DXSA/hlsl/if5.test @@ -0,0 +1,29 @@ +// RUN: mlir-translate --import-dxsa-bin %S/inputs/if5.shex | FileCheck %s +// NOTE: Assertions have been autogenerated by utils/generate-test-checks.py + + +// CHECK-LABEL: dxsa.dcl_global_flags +// CHECK: dxsa.dcl_input_ps linear v<0, > +// CHECK: dxsa.dcl_input_ps constant v<1, > +// CHECK: dxsa.dcl_output o<0, > +// CHECK: dxsa.dcl_temps 1 +// CHECK: dxsa.ieq r<0, >, v<1, >, l(0x1) +// CHECK: %[[INDEX_0:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_0:.*]] = dxsa.operand %[[INDEX_0]] {num_components = 4 : i32, one = 0 : i32, type = 0 : i32} +// CHECK: dxsa.instruction "if" %[[OPERAND_0]] +// CHECK: %[[INDEX_1:.*]] = dxsa.index.imm {imm = 1 : i32} +// CHECK: %[[OPERAND_1:.*]] = dxsa.operand %[[INDEX_1]] {num_components = 4 : i32, one = 1 : i32, type = 1 : i32} +// CHECK: dxsa.instruction "if" %[[OPERAND_1]] +// CHECK: dxsa.add o<0, >, v<0, >, l(0x40A00000) +// CHECK: dxsa.instruction "else" +// CHECK: dxsa.add o<0, >, v<0, >, l(0xC0000000) +// CHECK: dxsa.instruction "endif" +// CHECK: dxsa.instruction "else" +// CHECK: %[[INDEX_2:.*]] = dxsa.index.imm {imm = 1 : i32} +// CHECK: %[[OPERAND_2:.*]] = dxsa.operand %[[INDEX_2]] {num_components = 4 : i32, one = 2 : i32, type = 1 : i32} +// CHECK: dxsa.instruction "if" %[[OPERAND_2]] +// CHECK: dxsa.add o<0, >, v<0, >, l(0xC29A0000) +// CHECK: dxsa.instruction "endif" +// CHECK: dxsa.instruction "endif" +// CHECK: dxsa.instruction "ret" + diff --git a/mlir/test/Target/DXSA/hlsl/indexableinput1.test b/mlir/test/Target/DXSA/hlsl/indexableinput1.test new file mode 100644 index 000000000000..fbbcaeb84c7d --- /dev/null +++ b/mlir/test/Target/DXSA/hlsl/indexableinput1.test @@ -0,0 +1,24 @@ +// RUN: mlir-translate --import-dxsa-bin %S/inputs/indexableinput1.shex | FileCheck %s +// NOTE: Assertions have been autogenerated by utils/generate-test-checks.py + + +// CHECK-LABEL: dxsa.dcl_global_flags +// CHECK: dxsa.dcl_input_ps linear v<0, > +// CHECK: dxsa.dcl_input_ps linear v<2, > +// CHECK: dxsa.dcl_input_ps linear v<4, > +// CHECK: dxsa.dcl_input_ps linear v<5, > +// CHECK: dxsa.dcl_input_ps linear v<6, > +// CHECK: dxsa.dcl_input_ps linear v<7, > +// CHECK: dxsa.dcl_input_ps constant v<8, > +// CHECK: dxsa.dcl_output o<0, > +// CHECK: dxsa.dcl_temps 1 +// CHECK: dxsa.dcl_index_range v<4, >, 4 +// CHECK: %[[INDEX_0:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_0:.*]] = dxsa.operand %[[INDEX_0]] {mask = 16 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_1:.*]] = dxsa.index.imm {imm = 8 : i32} +// CHECK: %[[OPERAND_1:.*]] = dxsa.operand %[[INDEX_1]] {num_components = 4 : i32, one = 0 : i32, type = 1 : i32} +// CHECK: dxsa.instruction "mov" %[[OPERAND_0]], %[[OPERAND_1]] +// CHECK: dxsa.add r<0, >, v<2, >, v<4 + r<0, >, > +// CHECK: dxsa.add o<0, >, r<0, >, v<0, > +// CHECK: dxsa.instruction "ret" + diff --git a/mlir/test/Target/DXSA/hlsl/indexableinput2.test b/mlir/test/Target/DXSA/hlsl/indexableinput2.test new file mode 100644 index 000000000000..f827389ac0ce --- /dev/null +++ b/mlir/test/Target/DXSA/hlsl/indexableinput2.test @@ -0,0 +1,34 @@ +// RUN: mlir-translate --import-dxsa-bin %S/inputs/indexableinput2.shex | FileCheck %s +// NOTE: Assertions have been autogenerated by utils/generate-test-checks.py + + +// CHECK-LABEL: dxsa.dcl_global_flags +// CHECK: dxsa.dcl_input_ps linear v<0, > +// CHECK: dxsa.dcl_input_ps linear v<1, > +// CHECK: dxsa.dcl_input_ps linear v<2, > +// CHECK: dxsa.dcl_input_ps linear v<3, > +// CHECK: dxsa.dcl_input_ps linear v<4, > +// CHECK: dxsa.dcl_input_ps linear v<5, > +// CHECK: dxsa.dcl_input_ps linear v<6, > +// CHECK: dxsa.dcl_input_ps linear v<7, > +// CHECK: dxsa.dcl_input_ps linear v<8, > +// CHECK: dxsa.dcl_input_ps constant v<9, > +// CHECK: dxsa.dcl_input_ps_sgv v<10, >, +// CHECK: dxsa.dcl_output o<0, > +// CHECK: dxsa.dcl_temps 1 +// CHECK: dxsa.dcl_index_range v<0, >, 3 +// CHECK: dxsa.dcl_index_range v<3, >, 6 +// CHECK: %[[INDEX_0:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_0:.*]] = dxsa.operand %[[INDEX_0]] {mask = 16 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_1:.*]] = dxsa.index.imm {imm = 10 : i32} +// CHECK: %[[OPERAND_1:.*]] = dxsa.operand %[[INDEX_1]] {num_components = 4 : i32, one = 0 : i32, type = 1 : i32} +// CHECK: dxsa.instruction "mov" %[[OPERAND_0]], %[[OPERAND_1]] +// CHECK: dxsa.add r<0, >, v>, >, v<2, > +// CHECK: %[[INDEX_2:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_2:.*]] = dxsa.operand %[[INDEX_2]] {mask = 32 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_3:.*]] = dxsa.index.imm {imm = 9 : i32} +// CHECK: %[[OPERAND_3:.*]] = dxsa.operand %[[INDEX_3]] {num_components = 4 : i32, one = 0 : i32, type = 1 : i32} +// CHECK: dxsa.instruction "mov" %[[OPERAND_2]], %[[OPERAND_3]] +// CHECK: dxsa.add o<0, >, r<0, >, v<3 + r<0, >, > +// CHECK: dxsa.instruction "ret" + diff --git a/mlir/test/Target/DXSA/hlsl/indexableoutput1.test b/mlir/test/Target/DXSA/hlsl/indexableoutput1.test new file mode 100644 index 000000000000..bb3e1ebc1f7d --- /dev/null +++ b/mlir/test/Target/DXSA/hlsl/indexableoutput1.test @@ -0,0 +1,20 @@ +// RUN: mlir-translate --import-dxsa-bin %S/inputs/indexableoutput1.shex | FileCheck %s +// NOTE: Assertions have been autogenerated by utils/generate-test-checks.py + + +// CHECK-LABEL: dxsa.dcl_global_flags +// CHECK: dxsa.dcl_input v<0, > +// CHECK: dxsa.dcl_output o<2> +// CHECK: dxsa.dcl_output_siv o<7>, +// CHECK: %[[INDEX_0:.*]] = dxsa.index.imm {imm = 2 : i32} +// CHECK: %[[OPERAND_0:.*]] = dxsa.operand %[[INDEX_0]] {mask = 240 : i32, num_components = 4 : i32, type = 2 : i32} +// CHECK: %[[INDEX_1:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_1:.*]] = dxsa.operand %[[INDEX_1]] {num_components = 4 : i32, swizzle = dense<0> : vector<4xi32>, type = 1 : i32} +// CHECK: dxsa.instruction "mov" %[[OPERAND_0]], %[[OPERAND_1]] +// CHECK: %[[INDEX_2:.*]] = dxsa.index.imm {imm = 7 : i32} +// CHECK: %[[OPERAND_2:.*]] = dxsa.operand %[[INDEX_2]] {mask = 240 : i32, num_components = 4 : i32, type = 2 : i32} +// CHECK: %[[INDEX_3:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_3:.*]] = dxsa.operand %[[INDEX_3]] {num_components = 4 : i32, swizzle = dense<0> : vector<4xi32>, type = 1 : i32} +// CHECK: dxsa.instruction "mov" %[[OPERAND_2]], %[[OPERAND_3]] +// CHECK: dxsa.instruction "ret" + diff --git a/mlir/test/Target/DXSA/hlsl/indexabletemp1.test b/mlir/test/Target/DXSA/hlsl/indexabletemp1.test new file mode 100644 index 000000000000..fad41c18260c --- /dev/null +++ b/mlir/test/Target/DXSA/hlsl/indexabletemp1.test @@ -0,0 +1,93 @@ +// RUN: mlir-translate --import-dxsa-bin %S/inputs/indexabletemp1.shex | FileCheck %s +// NOTE: Assertions have been autogenerated by utils/generate-test-checks.py + + +// CHECK-LABEL: dxsa.dcl_global_flags +// CHECK: dxsa.dcl_constant_buffer , +// CHECK: dxsa.dcl_input_ps constant v<1, > +// CHECK: dxsa.dcl_input_ps constant v<1, > +// CHECK: dxsa.dcl_output o<0, > +// CHECK: dxsa.dcl_temps 1 +// CHECK: dxsa.dcl_indexable_temp x<0>[6] +// CHECK: %[[INDEX_0:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_0:.*]] = dxsa.operand %[[INDEX_0]] {mask = 16 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_1:.*]] = dxsa.index.imm {imm = 1 : i32} +// CHECK: %[[OPERAND_1:.*]] = dxsa.operand %[[INDEX_1]] {num_components = 4 : i32, one = 0 : i32, type = 1 : i32} +// CHECK: dxsa.instruction "mov" %[[OPERAND_0]], %[[OPERAND_1]] +// CHECK: %[[INDEX_2:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[INDEX_3:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_2:.*]] = dxsa.operand %[[INDEX_2]], %[[INDEX_3]] {mask = 16 : i32, num_components = 4 : i32, type = 3 : i32} +// CHECK: %[[INDEX_4:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[INDEX_5:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_3:.*]] = dxsa.operand %[[INDEX_5]] {num_components = 4 : i32, one = 0 : i32, type = 0 : i32} +// CHECK: %[[INDEX_6:.*]] = dxsa.index.rel %[[OPERAND_3]] +// CHECK: %[[OPERAND_4:.*]] = dxsa.operand %[[INDEX_4]], %[[INDEX_6]] {num_components = 4 : i32, one = 0 : i32, type = 8 : i32} +// CHECK: dxsa.instruction "mov" %[[OPERAND_2]], %[[OPERAND_4]] +// CHECK: %[[INDEX_7:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[INDEX_8:.*]] = dxsa.index.imm {imm = 1 : i32} +// CHECK: %[[OPERAND_5:.*]] = dxsa.operand %[[INDEX_7]], %[[INDEX_8]] {mask = 16 : i32, num_components = 4 : i32, type = 3 : i32} +// CHECK: %[[INDEX_9:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[INDEX_10:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_6:.*]] = dxsa.operand %[[INDEX_10]] {num_components = 4 : i32, one = 0 : i32, type = 0 : i32} +// CHECK: %[[INDEX_11:.*]] = dxsa.index.rel.imm %[[OPERAND_6]] {imm = 6 : i32, op = "add"} +// CHECK: %[[OPERAND_7:.*]] = dxsa.operand %[[INDEX_9]], %[[INDEX_11]] {num_components = 4 : i32, one = 0 : i32, type = 8 : i32} +// CHECK: dxsa.instruction "mov" %[[OPERAND_5]], %[[OPERAND_7]] +// CHECK: %[[INDEX_12:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_8:.*]] = dxsa.operand %[[INDEX_12]] {mask = 240 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_13:.*]] = dxsa.index.imm {imm = 1 : i32} +// CHECK: %[[OPERAND_9:.*]] = dxsa.operand %[[INDEX_13]] {num_components = 4 : i32, swizzle = dense<0> : vector<4xi32>, type = 1 : i32} +// CHECK: %[[OPERAND_10:.*]] = dxsa.operand.imm {imm = dense<[2, 3, 4, 5]> : vector<4xi32>} +// CHECK: dxsa.instruction "iadd" %[[OPERAND_8]], %[[OPERAND_9]], %[[OPERAND_10]] +// CHECK: %[[INDEX_14:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[INDEX_15:.*]] = dxsa.index.imm {imm = 2 : i32} +// CHECK: %[[OPERAND_11:.*]] = dxsa.operand %[[INDEX_14]], %[[INDEX_15]] {mask = 16 : i32, num_components = 4 : i32, type = 3 : i32} +// CHECK: %[[INDEX_16:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[INDEX_17:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_12:.*]] = dxsa.operand %[[INDEX_17]] {num_components = 4 : i32, one = 0 : i32, type = 0 : i32} +// CHECK: %[[INDEX_18:.*]] = dxsa.index.rel %[[OPERAND_12]] +// CHECK: %[[OPERAND_13:.*]] = dxsa.operand %[[INDEX_16]], %[[INDEX_18]] {num_components = 4 : i32, one = 0 : i32, type = 8 : i32} +// CHECK: dxsa.instruction "mov" %[[OPERAND_11]], %[[OPERAND_13]] +// CHECK: %[[INDEX_19:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[INDEX_20:.*]] = dxsa.index.imm {imm = 3 : i32} +// CHECK: %[[OPERAND_14:.*]] = dxsa.operand %[[INDEX_19]], %[[INDEX_20]] {mask = 16 : i32, num_components = 4 : i32, type = 3 : i32} +// CHECK: %[[INDEX_21:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[INDEX_22:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_15:.*]] = dxsa.operand %[[INDEX_22]] {num_components = 4 : i32, one = 1 : i32, type = 0 : i32} +// CHECK: %[[INDEX_23:.*]] = dxsa.index.rel %[[OPERAND_15]] +// CHECK: %[[OPERAND_16:.*]] = dxsa.operand %[[INDEX_21]], %[[INDEX_23]] {num_components = 4 : i32, one = 0 : i32, type = 8 : i32} +// CHECK: dxsa.instruction "mov" %[[OPERAND_14]], %[[OPERAND_16]] +// CHECK: %[[INDEX_24:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[INDEX_25:.*]] = dxsa.index.imm {imm = 4 : i32} +// CHECK: %[[OPERAND_17:.*]] = dxsa.operand %[[INDEX_24]], %[[INDEX_25]] {mask = 16 : i32, num_components = 4 : i32, type = 3 : i32} +// CHECK: %[[INDEX_26:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[INDEX_27:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_18:.*]] = dxsa.operand %[[INDEX_27]] {num_components = 4 : i32, one = 2 : i32, type = 0 : i32} +// CHECK: %[[INDEX_28:.*]] = dxsa.index.rel %[[OPERAND_18]] +// CHECK: %[[OPERAND_19:.*]] = dxsa.operand %[[INDEX_26]], %[[INDEX_28]] {num_components = 4 : i32, one = 0 : i32, type = 8 : i32} +// CHECK: dxsa.instruction "mov" %[[OPERAND_17]], %[[OPERAND_19]] +// CHECK: %[[INDEX_29:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[INDEX_30:.*]] = dxsa.index.imm {imm = 5 : i32} +// CHECK: %[[OPERAND_20:.*]] = dxsa.operand %[[INDEX_29]], %[[INDEX_30]] {mask = 16 : i32, num_components = 4 : i32, type = 3 : i32} +// CHECK: %[[INDEX_31:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[INDEX_32:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_21:.*]] = dxsa.operand %[[INDEX_32]] {num_components = 4 : i32, one = 3 : i32, type = 0 : i32} +// CHECK: %[[INDEX_33:.*]] = dxsa.index.rel %[[OPERAND_21]] +// CHECK: %[[OPERAND_22:.*]] = dxsa.operand %[[INDEX_31]], %[[INDEX_33]] {num_components = 4 : i32, one = 0 : i32, type = 8 : i32} +// CHECK: dxsa.instruction "mov" %[[OPERAND_20]], %[[OPERAND_22]] +// CHECK: %[[INDEX_34:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_23:.*]] = dxsa.operand %[[INDEX_34]] {mask = 16 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_35:.*]] = dxsa.index.imm {imm = 1 : i32} +// CHECK: %[[OPERAND_24:.*]] = dxsa.operand %[[INDEX_35]] {num_components = 4 : i32, one = 0 : i32, type = 1 : i32} +// CHECK: %[[INDEX_36:.*]] = dxsa.index.imm {imm = 1 : i32} +// CHECK: %[[OPERAND_25:.*]] = dxsa.operand %[[INDEX_36]] {num_components = 4 : i32, one = 1 : i32, type = 1 : i32} +// CHECK: dxsa.instruction "iadd" %[[OPERAND_23]], %[[OPERAND_24]], %[[OPERAND_25]] +// CHECK: %[[INDEX_37:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_26:.*]] = dxsa.operand %[[INDEX_37]] {mask = 16 : i32, num_components = 4 : i32, type = 2 : i32} +// CHECK: %[[INDEX_38:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[INDEX_39:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_27:.*]] = dxsa.operand %[[INDEX_39]] {num_components = 4 : i32, one = 0 : i32, type = 0 : i32} +// CHECK: %[[INDEX_40:.*]] = dxsa.index.rel %[[OPERAND_27]] +// CHECK: %[[OPERAND_28:.*]] = dxsa.operand %[[INDEX_38]], %[[INDEX_40]] {num_components = 4 : i32, one = 0 : i32, type = 3 : i32} +// CHECK: dxsa.instruction "mov" %[[OPERAND_26]], %[[OPERAND_28]] +// CHECK: dxsa.instruction "ret" + diff --git a/mlir/test/Target/DXSA/hlsl/indexabletemp2.test b/mlir/test/Target/DXSA/hlsl/indexabletemp2.test new file mode 100644 index 000000000000..5a51583aa7b3 --- /dev/null +++ b/mlir/test/Target/DXSA/hlsl/indexabletemp2.test @@ -0,0 +1,116 @@ +// RUN: mlir-translate --import-dxsa-bin %S/inputs/indexabletemp2.shex | FileCheck %s +// NOTE: Assertions have been autogenerated by utils/generate-test-checks.py + + +// CHECK-LABEL: dxsa.dcl_global_flags +// CHECK: dxsa.dcl_constant_buffer , +// CHECK: dxsa.dcl_input_ps constant v<1, > +// CHECK: dxsa.dcl_input_ps constant v<1, > +// CHECK: dxsa.dcl_output o<0, > +// CHECK: dxsa.dcl_temps 1 +// CHECK: dxsa.dcl_indexable_temp x<0>[4] +// CHECK: dxsa.dcl_indexable_temp x<1>[2] +// CHECK: %[[INDEX_0:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_0:.*]] = dxsa.operand %[[INDEX_0]] {mask = 16 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_1:.*]] = dxsa.index.imm {imm = 1 : i32} +// CHECK: %[[OPERAND_1:.*]] = dxsa.operand %[[INDEX_1]] {num_components = 4 : i32, one = 0 : i32, type = 1 : i32} +// CHECK: dxsa.instruction "mov" %[[OPERAND_0]], %[[OPERAND_1]] +// CHECK: %[[INDEX_2:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[INDEX_3:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_2:.*]] = dxsa.operand %[[INDEX_2]], %[[INDEX_3]] {mask = 16 : i32, num_components = 4 : i32, type = 3 : i32} +// CHECK: %[[INDEX_4:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[INDEX_5:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_3:.*]] = dxsa.operand %[[INDEX_5]] {num_components = 4 : i32, one = 0 : i32, type = 0 : i32} +// CHECK: %[[INDEX_6:.*]] = dxsa.index.rel %[[OPERAND_3]] +// CHECK: %[[OPERAND_4:.*]] = dxsa.operand %[[INDEX_4]], %[[INDEX_6]] {num_components = 4 : i32, one = 0 : i32, type = 8 : i32} +// CHECK: dxsa.instruction "mov" %[[OPERAND_2]], %[[OPERAND_4]] +// CHECK: %[[INDEX_7:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[INDEX_8:.*]] = dxsa.index.imm {imm = 1 : i32} +// CHECK: %[[OPERAND_5:.*]] = dxsa.operand %[[INDEX_7]], %[[INDEX_8]] {mask = 16 : i32, num_components = 4 : i32, type = 3 : i32} +// CHECK: %[[INDEX_9:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[INDEX_10:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_6:.*]] = dxsa.operand %[[INDEX_10]] {num_components = 4 : i32, one = 0 : i32, type = 0 : i32} +// CHECK: %[[INDEX_11:.*]] = dxsa.index.rel.imm %[[OPERAND_6]] {imm = 4 : i32, op = "add"} +// CHECK: %[[OPERAND_7:.*]] = dxsa.operand %[[INDEX_9]], %[[INDEX_11]] {num_components = 4 : i32, one = 0 : i32, type = 8 : i32} +// CHECK: dxsa.instruction "mov" %[[OPERAND_5]], %[[OPERAND_7]] +// CHECK: %[[INDEX_12:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_8:.*]] = dxsa.operand %[[INDEX_12]] {mask = 240 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_13:.*]] = dxsa.index.imm {imm = 1 : i32} +// CHECK: %[[OPERAND_9:.*]] = dxsa.operand %[[INDEX_13]] {num_components = 4 : i32, swizzle = dense<[0, 0, 0, 1]> : vector<4xi32>, type = 1 : i32} +// CHECK: %[[OPERAND_10:.*]] = dxsa.operand.imm {imm = dense<[2, 3, 11, 13]> : vector<4xi32>} +// CHECK: dxsa.instruction "iadd" %[[OPERAND_8]], %[[OPERAND_9]], %[[OPERAND_10]] +// CHECK: %[[INDEX_14:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[INDEX_15:.*]] = dxsa.index.imm {imm = 2 : i32} +// CHECK: %[[OPERAND_11:.*]] = dxsa.operand %[[INDEX_14]], %[[INDEX_15]] {mask = 16 : i32, num_components = 4 : i32, type = 3 : i32} +// CHECK: %[[INDEX_16:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[INDEX_17:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_12:.*]] = dxsa.operand %[[INDEX_17]] {num_components = 4 : i32, one = 0 : i32, type = 0 : i32} +// CHECK: %[[INDEX_18:.*]] = dxsa.index.rel %[[OPERAND_12]] +// CHECK: %[[OPERAND_13:.*]] = dxsa.operand %[[INDEX_16]], %[[INDEX_18]] {num_components = 4 : i32, one = 0 : i32, type = 8 : i32} +// CHECK: dxsa.instruction "mov" %[[OPERAND_11]], %[[OPERAND_13]] +// CHECK: %[[INDEX_19:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[INDEX_20:.*]] = dxsa.index.imm {imm = 3 : i32} +// CHECK: %[[OPERAND_14:.*]] = dxsa.operand %[[INDEX_19]], %[[INDEX_20]] {mask = 16 : i32, num_components = 4 : i32, type = 3 : i32} +// CHECK: %[[INDEX_21:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[INDEX_22:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_15:.*]] = dxsa.operand %[[INDEX_22]] {num_components = 4 : i32, one = 1 : i32, type = 0 : i32} +// CHECK: %[[INDEX_23:.*]] = dxsa.index.rel %[[OPERAND_15]] +// CHECK: %[[OPERAND_16:.*]] = dxsa.operand %[[INDEX_21]], %[[INDEX_23]] {num_components = 4 : i32, one = 0 : i32, type = 8 : i32} +// CHECK: dxsa.instruction "mov" %[[OPERAND_14]], %[[OPERAND_16]] +// CHECK: %[[INDEX_24:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_17:.*]] = dxsa.operand %[[INDEX_24]] {mask = 16 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_25:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[INDEX_26:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_18:.*]] = dxsa.operand %[[INDEX_26]] {num_components = 4 : i32, one = 2 : i32, type = 0 : i32} +// CHECK: %[[INDEX_27:.*]] = dxsa.index.rel.imm %[[OPERAND_18]] {imm = 12 : i32, op = "add"} +// CHECK: %[[OPERAND_19:.*]] = dxsa.operand %[[INDEX_25]], %[[INDEX_27]] {num_components = 4 : i32, one = 0 : i32, type = 8 : i32} +// CHECK: %[[INDEX_28:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[INDEX_29:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_20:.*]] = dxsa.operand %[[INDEX_29]] {num_components = 4 : i32, one = 3 : i32, type = 0 : i32} +// CHECK: %[[INDEX_30:.*]] = dxsa.index.rel.imm %[[OPERAND_20]] {imm = 16 : i32, op = "add"} +// CHECK: %[[OPERAND_21:.*]] = dxsa.operand %[[INDEX_28]], %[[INDEX_30]] {num_components = 4 : i32, one = 0 : i32, type = 8 : i32} +// CHECK: dxsa.instruction "iadd" %[[OPERAND_17]], %[[OPERAND_19]], %[[OPERAND_21]] +// CHECK: %[[INDEX_31:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_22:.*]] = dxsa.operand %[[INDEX_31]] {mask = 32 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[OPERAND_23:.*]] = dxsa.operand.imm {imm = dense<-13> : vector<1xi32>} +// CHECK: %[[INDEX_32:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[INDEX_33:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_24:.*]] = dxsa.operand %[[INDEX_33]] {num_components = 4 : i32, one = 3 : i32, type = 0 : i32} +// CHECK: %[[INDEX_34:.*]] = dxsa.index.rel.imm %[[OPERAND_24]] {imm = 16 : i32, op = "add"} +// CHECK: %[[OPERAND_25:.*]] = dxsa.operand %[[INDEX_32]], %[[INDEX_34]] {num_components = 4 : i32, one = 0 : i32, type = 8 : i32} +// CHECK: dxsa.instruction "iadd" %[[OPERAND_22]], %[[OPERAND_23]], %[[OPERAND_25]] +// CHECK: %[[INDEX_35:.*]] = dxsa.index.imm {imm = 1 : i32} +// CHECK: %[[INDEX_36:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_26:.*]] = dxsa.operand %[[INDEX_35]], %[[INDEX_36]] {mask = 16 : i32, num_components = 4 : i32, type = 3 : i32} +// CHECK: %[[INDEX_37:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_27:.*]] = dxsa.operand %[[INDEX_37]] {num_components = 4 : i32, one = 0 : i32, type = 0 : i32} +// CHECK: dxsa.instruction "mov" %[[OPERAND_26]], %[[OPERAND_27]] +// CHECK: %[[INDEX_38:.*]] = dxsa.index.imm {imm = 1 : i32} +// CHECK: %[[INDEX_39:.*]] = dxsa.index.imm {imm = 1 : i32} +// CHECK: %[[OPERAND_28:.*]] = dxsa.operand %[[INDEX_38]], %[[INDEX_39]] {mask = 16 : i32, num_components = 4 : i32, type = 3 : i32} +// CHECK: %[[INDEX_40:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_29:.*]] = dxsa.operand %[[INDEX_40]] {num_components = 4 : i32, one = 1 : i32, type = 0 : i32} +// CHECK: dxsa.instruction "mov" %[[OPERAND_28]], %[[OPERAND_29]] +// CHECK: %[[INDEX_41:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_30:.*]] = dxsa.operand %[[INDEX_41]] {mask = 16 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_42:.*]] = dxsa.index.imm {imm = 1 : i32} +// CHECK: %[[OPERAND_31:.*]] = dxsa.operand %[[INDEX_42]] {num_components = 4 : i32, one = 1 : i32, type = 1 : i32} +// CHECK: dxsa.instruction "mov" %[[OPERAND_30]], %[[OPERAND_31]] +// CHECK: %[[INDEX_43:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_32:.*]] = dxsa.operand %[[INDEX_43]] {mask = 16 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_44:.*]] = dxsa.index.imm {imm = 1 : i32} +// CHECK: %[[INDEX_45:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_33:.*]] = dxsa.operand %[[INDEX_45]] {num_components = 4 : i32, one = 0 : i32, type = 0 : i32} +// CHECK: %[[INDEX_46:.*]] = dxsa.index.rel %[[OPERAND_33]] +// CHECK: %[[OPERAND_34:.*]] = dxsa.operand %[[INDEX_44]], %[[INDEX_46]] {num_components = 4 : i32, one = 0 : i32, type = 3 : i32} +// CHECK: dxsa.instruction "mov" %[[OPERAND_32]], %[[OPERAND_34]] +// CHECK: %[[INDEX_47:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_35:.*]] = dxsa.operand %[[INDEX_47]] {mask = 16 : i32, num_components = 4 : i32, type = 2 : i32} +// CHECK: %[[INDEX_48:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[INDEX_49:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_36:.*]] = dxsa.operand %[[INDEX_49]] {num_components = 4 : i32, one = 0 : i32, type = 0 : i32} +// CHECK: %[[INDEX_50:.*]] = dxsa.index.rel %[[OPERAND_36]] +// CHECK: %[[OPERAND_37:.*]] = dxsa.operand %[[INDEX_48]], %[[INDEX_50]] {num_components = 4 : i32, one = 0 : i32, type = 3 : i32} +// CHECK: dxsa.instruction "mov" %[[OPERAND_35]], %[[OPERAND_37]] +// CHECK: dxsa.instruction "ret" + diff --git a/mlir/test/Target/DXSA/hlsl/indexabletemp3.test b/mlir/test/Target/DXSA/hlsl/indexabletemp3.test new file mode 100644 index 000000000000..c17bec8b6b64 --- /dev/null +++ b/mlir/test/Target/DXSA/hlsl/indexabletemp3.test @@ -0,0 +1,49 @@ +// RUN: mlir-translate --import-dxsa-bin %S/inputs/indexabletemp3.shex | FileCheck %s +// NOTE: Assertions have been autogenerated by utils/generate-test-checks.py + + +// CHECK-LABEL: dxsa.dcl_global_flags +// CHECK: dxsa.dcl_constant_buffer , +// CHECK: dxsa.dcl_input_ps constant v<1, > +// CHECK: dxsa.dcl_input_ps constant v<1, > +// CHECK: dxsa.dcl_output o<0, > +// CHECK: dxsa.dcl_temps 1 +// CHECK: dxsa.dcl_indexable_temp x<0>[4] +// CHECK: %[[INDEX_0:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_0:.*]] = dxsa.operand %[[INDEX_0]] {mask = 16 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_1:.*]] = dxsa.index.imm {imm = 1 : i32} +// CHECK: %[[OPERAND_1:.*]] = dxsa.operand %[[INDEX_1]] {num_components = 4 : i32, one = 0 : i32, type = 1 : i32} +// CHECK: dxsa.instruction "mov" %[[OPERAND_0]], %[[OPERAND_1]] +// CHECK: %[[INDEX_2:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[INDEX_3:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_2:.*]] = dxsa.operand %[[INDEX_2]], %[[INDEX_3]] {mask = 16 : i32, num_components = 4 : i32, type = 3 : i32} +// CHECK: %[[INDEX_4:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[INDEX_5:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_3:.*]] = dxsa.operand %[[INDEX_5]] {num_components = 4 : i32, one = 0 : i32, type = 0 : i32} +// CHECK: %[[INDEX_6:.*]] = dxsa.index.rel %[[OPERAND_3]] +// CHECK: %[[OPERAND_4:.*]] = dxsa.operand %[[INDEX_4]], %[[INDEX_6]] {num_components = 4 : i32, one = 0 : i32, type = 8 : i32} +// CHECK: dxsa.instruction "mov" %[[OPERAND_2]], %[[OPERAND_4]] +// CHECK: %[[INDEX_7:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[INDEX_8:.*]] = dxsa.index.imm {imm = 1 : i32} +// CHECK: %[[OPERAND_5:.*]] = dxsa.operand %[[INDEX_7]], %[[INDEX_8]] {mask = 16 : i32, num_components = 4 : i32, type = 3 : i32} +// CHECK: %[[INDEX_9:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[INDEX_10:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_6:.*]] = dxsa.operand %[[INDEX_10]] {num_components = 4 : i32, one = 0 : i32, type = 0 : i32} +// CHECK: %[[INDEX_11:.*]] = dxsa.index.rel.imm %[[OPERAND_6]] {imm = 4 : i32, op = "add"} +// CHECK: %[[OPERAND_7:.*]] = dxsa.operand %[[INDEX_9]], %[[INDEX_11]] {num_components = 4 : i32, one = 0 : i32, type = 8 : i32} +// CHECK: dxsa.instruction "mov" %[[OPERAND_5]], %[[OPERAND_7]] +// CHECK: %[[INDEX_12:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_8:.*]] = dxsa.operand %[[INDEX_12]] {mask = 16 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_13:.*]] = dxsa.index.imm {imm = 1 : i32} +// CHECK: %[[OPERAND_9:.*]] = dxsa.operand %[[INDEX_13]] {num_components = 4 : i32, one = 1 : i32, type = 1 : i32} +// CHECK: dxsa.instruction "mov" %[[OPERAND_8]], %[[OPERAND_9]] +// CHECK: %[[INDEX_14:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_10:.*]] = dxsa.operand %[[INDEX_14]] {mask = 16 : i32, num_components = 4 : i32, type = 2 : i32} +// CHECK: %[[INDEX_15:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[INDEX_16:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_11:.*]] = dxsa.operand %[[INDEX_16]] {num_components = 4 : i32, one = 0 : i32, type = 0 : i32} +// CHECK: %[[INDEX_17:.*]] = dxsa.index.rel %[[OPERAND_11]] +// CHECK: %[[OPERAND_12:.*]] = dxsa.operand %[[INDEX_15]], %[[INDEX_17]] {num_components = 4 : i32, one = 0 : i32, type = 3 : i32} +// CHECK: dxsa.instruction "mov" %[[OPERAND_10]], %[[OPERAND_12]] +// CHECK: dxsa.instruction "ret" + diff --git a/mlir/test/Target/DXSA/hlsl/indexabletemp5.test b/mlir/test/Target/DXSA/hlsl/indexabletemp5.test new file mode 100644 index 000000000000..43737b806c87 --- /dev/null +++ b/mlir/test/Target/DXSA/hlsl/indexabletemp5.test @@ -0,0 +1,49 @@ +// RUN: mlir-translate --import-dxsa-bin %S/inputs/indexabletemp5.shex | FileCheck %s +// NOTE: Assertions have been autogenerated by utils/generate-test-checks.py + + +// CHECK-LABEL: dxsa.dcl_global_flags +// CHECK: dxsa.dcl_constant_buffer , +// CHECK: dxsa.dcl_input_ps constant v<1, > +// CHECK: dxsa.dcl_input_ps constant v<1, > +// CHECK: dxsa.dcl_output o<0, min16f, > +// CHECK: dxsa.dcl_temps 1 +// CHECK: dxsa.dcl_indexable_temp x<0>[4] +// CHECK: %[[INDEX_0:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_0:.*]] = dxsa.operand %[[INDEX_0]] {mask = 16 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_1:.*]] = dxsa.index.imm {imm = 1 : i32} +// CHECK: %[[OPERAND_1:.*]] = dxsa.operand %[[INDEX_1]] {num_components = 4 : i32, one = 0 : i32, type = 1 : i32} +// CHECK: dxsa.instruction "mov" %[[OPERAND_0]], %[[OPERAND_1]] +// CHECK: %[[INDEX_2:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[INDEX_3:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_2:.*]] = dxsa.operand %[[INDEX_2]], %[[INDEX_3]] {mask = 16 : i32, min_precision = 1 : i32, num_components = 4 : i32, type = 3 : i32} +// CHECK: %[[INDEX_4:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[INDEX_5:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_3:.*]] = dxsa.operand %[[INDEX_5]] {num_components = 4 : i32, one = 0 : i32, type = 0 : i32} +// CHECK: %[[INDEX_6:.*]] = dxsa.index.rel %[[OPERAND_3]] +// CHECK: %[[OPERAND_4:.*]] = dxsa.operand %[[INDEX_4]], %[[INDEX_6]] {min_precision = 1 : i32, num_components = 4 : i32, one = 0 : i32, type = 8 : i32} +// CHECK: dxsa.instruction "mov" %[[OPERAND_2]], %[[OPERAND_4]] +// CHECK: %[[INDEX_7:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[INDEX_8:.*]] = dxsa.index.imm {imm = 1 : i32} +// CHECK: %[[OPERAND_5:.*]] = dxsa.operand %[[INDEX_7]], %[[INDEX_8]] {mask = 16 : i32, min_precision = 1 : i32, num_components = 4 : i32, type = 3 : i32} +// CHECK: %[[INDEX_9:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[INDEX_10:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_6:.*]] = dxsa.operand %[[INDEX_10]] {num_components = 4 : i32, one = 0 : i32, type = 0 : i32} +// CHECK: %[[INDEX_11:.*]] = dxsa.index.rel.imm %[[OPERAND_6]] {imm = 4 : i32, op = "add"} +// CHECK: %[[OPERAND_7:.*]] = dxsa.operand %[[INDEX_9]], %[[INDEX_11]] {min_precision = 1 : i32, num_components = 4 : i32, one = 0 : i32, type = 8 : i32} +// CHECK: dxsa.instruction "mov" %[[OPERAND_5]], %[[OPERAND_7]] +// CHECK: %[[INDEX_12:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_8:.*]] = dxsa.operand %[[INDEX_12]] {mask = 16 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_13:.*]] = dxsa.index.imm {imm = 1 : i32} +// CHECK: %[[OPERAND_9:.*]] = dxsa.operand %[[INDEX_13]] {num_components = 4 : i32, one = 1 : i32, type = 1 : i32} +// CHECK: dxsa.instruction "mov" %[[OPERAND_8]], %[[OPERAND_9]] +// CHECK: %[[INDEX_14:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_10:.*]] = dxsa.operand %[[INDEX_14]] {mask = 16 : i32, min_precision = 1 : i32, num_components = 4 : i32, type = 2 : i32} +// CHECK: %[[INDEX_15:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[INDEX_16:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_11:.*]] = dxsa.operand %[[INDEX_16]] {num_components = 4 : i32, one = 0 : i32, type = 0 : i32} +// CHECK: %[[INDEX_17:.*]] = dxsa.index.rel %[[OPERAND_11]] +// CHECK: %[[OPERAND_12:.*]] = dxsa.operand %[[INDEX_15]], %[[INDEX_17]] {min_precision = 1 : i32, num_components = 4 : i32, one = 0 : i32, type = 3 : i32} +// CHECK: dxsa.instruction "mov" %[[OPERAND_10]], %[[OPERAND_12]] +// CHECK: dxsa.instruction "ret" + diff --git a/mlir/test/Target/DXSA/hlsl/input1.test b/mlir/test/Target/DXSA/hlsl/input1.test new file mode 100644 index 000000000000..f5431776dfc1 --- /dev/null +++ b/mlir/test/Target/DXSA/hlsl/input1.test @@ -0,0 +1,45 @@ +// RUN: mlir-translate --import-dxsa-bin %S/inputs/input1.shex | FileCheck %s +// NOTE: Assertions have been autogenerated by utils/generate-test-checks.py + + +// CHECK-LABEL: dxsa.dcl_global_flags +// CHECK: dxsa.dcl_input_ps linear v<0> +// CHECK: dxsa.dcl_input_ps constant v<1> +// CHECK: dxsa.dcl_input_ps constant v<2> +// CHECK: dxsa.dcl_input_ps linear v<3, min16f> +// CHECK: dxsa.dcl_input_ps_siv linear v<4, >, +// CHECK: dxsa.dcl_input_ps_siv linear v<4, >, +// CHECK: dxsa.dcl_input_ps constant v<5, > +// CHECK: dxsa.dcl_input_ps_sgv v<5, >, +// CHECK: dxsa.dcl_input_ps_siv constant v<5, >, +// CHECK: dxsa.dcl_input_ps_siv constant v<5, >, +// CHECK: dxsa.dcl_input_ps_siv linearNoPerspective v<6>, +// CHECK: dxsa.dcl_input_ps_sgv v<7, >, +// CHECK: dxsa.dcl_input_ps_sgv v<7, >, +// CHECK: dxsa.dcl_input vCoverage +// CHECK: dxsa.dcl_output o<0> +// CHECK: dxsa.dcl_temps 2 +// CHECK: dxsa.itof r<0>, v<1> +// CHECK: dxsa.add r<0>, r<0>, v<0> +// CHECK: dxsa.utof r<1>, v<2> +// CHECK: dxsa.add r<0>, r<0>, r<1> +// CHECK: dxsa.add r<0>, r<0>, v<3, min16f> +// CHECK: dxsa.add r<0>, r<0>, v<4, > +// CHECK: dxsa.add r<0>, r<0>, v<4, > +// CHECK: dxsa.utof r<1, >, vCoverage> +// CHECK: dxsa.add r<0>, r<0>, r<1, > +// CHECK: dxsa.utof r<1, >, v<5, > +// CHECK: dxsa.add r<0>, r<0>, r<1, > +// CHECK: dxsa.utof r<1, >, v<5, > +// CHECK: dxsa.add r<0>, r<0>, r<1, > +// CHECK: dxsa.utof r<1, >, v<5, > +// CHECK: dxsa.add r<0>, r<0>, r<1, > +// CHECK: dxsa.utof r<1, >, v<5, > +// CHECK: dxsa.add r<0>, r<0>, r<1, > +// CHECK: dxsa.add r<0>, r<0>, v<6> +// CHECK: dxsa.utof r<1, >, v<7, > +// CHECK: dxsa.add r<0>, r<0>, r<1, > +// CHECK: dxsa.and r<1, >, v<7, >, l(0x3F800000) +// CHECK: dxsa.add o<0>, r<0>, r<1, > +// CHECK: dxsa.instruction "ret" + diff --git a/mlir/test/Target/DXSA/hlsl/input2.test b/mlir/test/Target/DXSA/hlsl/input2.test new file mode 100644 index 000000000000..53d390f97730 --- /dev/null +++ b/mlir/test/Target/DXSA/hlsl/input2.test @@ -0,0 +1,45 @@ +// RUN: mlir-translate --import-dxsa-bin %S/inputs/input2.shex | FileCheck %s +// NOTE: Assertions have been autogenerated by utils/generate-test-checks.py + + +// CHECK-LABEL: dxsa.dcl_global_flags +// CHECK: dxsa.dcl_input_ps linear v<0> +// CHECK: dxsa.dcl_input_ps constant v<1> +// CHECK: dxsa.dcl_input_ps constant v<2> +// CHECK: dxsa.dcl_input_ps linear v<3, min16f> +// CHECK: dxsa.dcl_input_ps_siv linear v<4, >, +// CHECK: dxsa.dcl_input_ps_siv linear v<4, >, +// CHECK: dxsa.dcl_input_ps constant v<5, > +// CHECK: dxsa.dcl_input_ps_sgv v<5, >, +// CHECK: dxsa.dcl_input_ps_siv constant v<5, >, +// CHECK: dxsa.dcl_input_ps_siv constant v<5, >, +// CHECK: dxsa.dcl_input_ps_siv linearNoPerspective v<6>, +// CHECK: dxsa.dcl_input_ps_sgv v<7, >, +// CHECK: dxsa.dcl_input_ps_sgv v<7, >, +// CHECK: dxsa.dcl_input vInnerCoverage +// CHECK: dxsa.dcl_output o<0> +// CHECK: dxsa.dcl_temps 2 +// CHECK: dxsa.itof r<0>, v<1> +// CHECK: dxsa.add r<0>, r<0>, v<0> +// CHECK: dxsa.utof r<1>, v<2> +// CHECK: dxsa.add r<0>, r<0>, r<1> +// CHECK: dxsa.add r<0>, r<0>, v<3, min16f> +// CHECK: dxsa.add r<0>, r<0>, v<4, > +// CHECK: dxsa.add r<0>, r<0>, v<4, > +// CHECK: dxsa.utof r<1, >, vInnerCoverage> +// CHECK: dxsa.add r<0>, r<0>, r<1, > +// CHECK: dxsa.utof r<1, >, v<5, > +// CHECK: dxsa.add r<0>, r<0>, r<1, > +// CHECK: dxsa.utof r<1, >, v<5, > +// CHECK: dxsa.add r<0>, r<0>, r<1, > +// CHECK: dxsa.utof r<1, >, v<5, > +// CHECK: dxsa.add r<0>, r<0>, r<1, > +// CHECK: dxsa.utof r<1, >, v<5, > +// CHECK: dxsa.add r<0>, r<0>, r<1, > +// CHECK: dxsa.add r<0>, r<0>, v<6> +// CHECK: dxsa.utof r<1, >, v<7, > +// CHECK: dxsa.add r<0>, r<0>, r<1, > +// CHECK: dxsa.and r<1, >, v<7, >, l(0x3F800000) +// CHECK: dxsa.add o<0>, r<0>, r<1, > +// CHECK: dxsa.instruction "ret" + diff --git a/mlir/test/Target/DXSA/hlsl/input3.test b/mlir/test/Target/DXSA/hlsl/input3.test new file mode 100644 index 000000000000..8fd2e117ad57 --- /dev/null +++ b/mlir/test/Target/DXSA/hlsl/input3.test @@ -0,0 +1,16 @@ +// RUN: mlir-translate --import-dxsa-bin %S/inputs/input3.shex | FileCheck %s +// NOTE: Assertions have been autogenerated by utils/generate-test-checks.py + + +// CHECK-LABEL: dxsa.dcl_global_flags +// CHECK: dxsa.dcl_input v<0> +// CHECK: dxsa.dcl_input_sgv v<1, >, +// CHECK: dxsa.dcl_input_sgv v<2, >, +// CHECK: dxsa.dcl_output_siv o<0>, +// CHECK: dxsa.dcl_temps 2 +// CHECK: dxsa.utof r<0, >, v<1, > +// CHECK: dxsa.add r<0>, r<0, >, v<0> +// CHECK: dxsa.utof r<1, >, v<2, > +// CHECK: dxsa.add o<0>, r<0>, r<1, > +// CHECK: dxsa.instruction "ret" + diff --git a/mlir/test/Target/DXSA/hlsl/inputs/abs1.shex b/mlir/test/Target/DXSA/hlsl/inputs/abs1.shex new file mode 100644 index 000000000000..d7fcd98e2a88 Binary files /dev/null and b/mlir/test/Target/DXSA/hlsl/inputs/abs1.shex differ diff --git a/mlir/test/Target/DXSA/hlsl/inputs/abs2.shex b/mlir/test/Target/DXSA/hlsl/inputs/abs2.shex new file mode 100644 index 000000000000..0e9e0f58b3d4 Binary files /dev/null and b/mlir/test/Target/DXSA/hlsl/inputs/abs2.shex differ diff --git a/mlir/test/Target/DXSA/hlsl/inputs/atomics.shex b/mlir/test/Target/DXSA/hlsl/inputs/atomics.shex new file mode 100644 index 000000000000..94dc1be85c37 Binary files /dev/null and b/mlir/test/Target/DXSA/hlsl/inputs/atomics.shex differ diff --git a/mlir/test/Target/DXSA/hlsl/inputs/bad_ftoi.shex b/mlir/test/Target/DXSA/hlsl/inputs/bad_ftoi.shex new file mode 100644 index 000000000000..bf7bbbe648b3 Binary files /dev/null and b/mlir/test/Target/DXSA/hlsl/inputs/bad_ftoi.shex differ diff --git a/mlir/test/Target/DXSA/hlsl/inputs/binary1.shex b/mlir/test/Target/DXSA/hlsl/inputs/binary1.shex new file mode 100644 index 000000000000..f60e8d31b00b Binary files /dev/null and b/mlir/test/Target/DXSA/hlsl/inputs/binary1.shex differ diff --git a/mlir/test/Target/DXSA/hlsl/inputs/bool1.shex b/mlir/test/Target/DXSA/hlsl/inputs/bool1.shex new file mode 100644 index 000000000000..b683a7c5d442 Binary files /dev/null and b/mlir/test/Target/DXSA/hlsl/inputs/bool1.shex differ diff --git a/mlir/test/Target/DXSA/hlsl/inputs/bool2.shex b/mlir/test/Target/DXSA/hlsl/inputs/bool2.shex new file mode 100644 index 000000000000..718789556918 Binary files /dev/null and b/mlir/test/Target/DXSA/hlsl/inputs/bool2.shex differ diff --git a/mlir/test/Target/DXSA/hlsl/inputs/bufinfo.shex b/mlir/test/Target/DXSA/hlsl/inputs/bufinfo.shex new file mode 100644 index 000000000000..2f22dad777f8 Binary files /dev/null and b/mlir/test/Target/DXSA/hlsl/inputs/bufinfo.shex differ diff --git a/mlir/test/Target/DXSA/hlsl/inputs/calc_lod.shex b/mlir/test/Target/DXSA/hlsl/inputs/calc_lod.shex new file mode 100644 index 000000000000..e3cdd36a0ecf Binary files /dev/null and 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a/mlir/test/Target/DXSA/hlsl/inputs/switch2.shex b/mlir/test/Target/DXSA/hlsl/inputs/switch2.shex new file mode 100644 index 000000000000..563dbbc39848 Binary files /dev/null and b/mlir/test/Target/DXSA/hlsl/inputs/switch2.shex differ diff --git a/mlir/test/Target/DXSA/hlsl/inputs/switch3.shex b/mlir/test/Target/DXSA/hlsl/inputs/switch3.shex new file mode 100644 index 000000000000..8db70470559e Binary files /dev/null and b/mlir/test/Target/DXSA/hlsl/inputs/switch3.shex differ diff --git a/mlir/test/Target/DXSA/hlsl/inputs/swizzle1.shex b/mlir/test/Target/DXSA/hlsl/inputs/swizzle1.shex new file mode 100644 index 000000000000..5b022cf6866f Binary files /dev/null and b/mlir/test/Target/DXSA/hlsl/inputs/swizzle1.shex differ diff --git a/mlir/test/Target/DXSA/hlsl/inputs/temp1.shex b/mlir/test/Target/DXSA/hlsl/inputs/temp1.shex new file mode 100644 index 000000000000..87446dfcef51 Binary files /dev/null and b/mlir/test/Target/DXSA/hlsl/inputs/temp1.shex differ diff --git a/mlir/test/Target/DXSA/hlsl/inputs/temp2.shex b/mlir/test/Target/DXSA/hlsl/inputs/temp2.shex new file mode 100644 index 000000000000..043878a3be5a Binary files /dev/null and b/mlir/test/Target/DXSA/hlsl/inputs/temp2.shex differ diff --git a/mlir/test/Target/DXSA/hlsl/inputs/uav_counter_dec.shex b/mlir/test/Target/DXSA/hlsl/inputs/uav_counter_dec.shex new file mode 100644 index 000000000000..e8ce92c606d8 Binary files /dev/null and b/mlir/test/Target/DXSA/hlsl/inputs/uav_counter_dec.shex differ diff --git a/mlir/test/Target/DXSA/hlsl/inputs/uav_counter_inc.shex b/mlir/test/Target/DXSA/hlsl/inputs/uav_counter_inc.shex new file mode 100644 index 000000000000..8baa63b91e9c Binary files /dev/null and b/mlir/test/Target/DXSA/hlsl/inputs/uav_counter_inc.shex differ diff --git a/mlir/test/Target/DXSA/hlsl/inputs/uav_raw1.shex b/mlir/test/Target/DXSA/hlsl/inputs/uav_raw1.shex new file mode 100644 index 000000000000..6255a020fb18 Binary files /dev/null and b/mlir/test/Target/DXSA/hlsl/inputs/uav_raw1.shex differ diff --git a/mlir/test/Target/DXSA/hlsl/inputs/uav_typed_load_store1.shex b/mlir/test/Target/DXSA/hlsl/inputs/uav_typed_load_store1.shex new file mode 100644 index 000000000000..a3068362bf87 Binary files /dev/null and b/mlir/test/Target/DXSA/hlsl/inputs/uav_typed_load_store1.shex differ diff --git a/mlir/test/Target/DXSA/hlsl/inputs/uav_typed_load_store2.shex b/mlir/test/Target/DXSA/hlsl/inputs/uav_typed_load_store2.shex new file mode 100644 index 000000000000..0e1476bbd048 Binary files /dev/null and b/mlir/test/Target/DXSA/hlsl/inputs/uav_typed_load_store2.shex differ diff --git a/mlir/test/Target/DXSA/hlsl/inputs/ubfeu16.shex b/mlir/test/Target/DXSA/hlsl/inputs/ubfeu16.shex new file mode 100644 index 000000000000..e38cb085a325 Binary files /dev/null and b/mlir/test/Target/DXSA/hlsl/inputs/ubfeu16.shex differ diff --git a/mlir/test/Target/DXSA/hlsl/interface1.test b/mlir/test/Target/DXSA/hlsl/interface1.test new file mode 100644 index 000000000000..9b18dc14ddd9 --- /dev/null +++ b/mlir/test/Target/DXSA/hlsl/interface1.test @@ -0,0 +1,81 @@ +// RUN: mlir-translate --import-dxsa-bin %S/inputs/interface1.shex | FileCheck %s +// NOTE: Assertions have been autogenerated by utils/generate-test-checks.py + + +// CHECK-LABEL: dxsa.dcl_global_flags +// CHECK: dxsa.dcl_constant_buffer , +// CHECK: dxsa.unknown +// CHECK: dxsa.unknown +// CHECK: dxsa.unknown +// CHECK: dxsa.unknown +// CHECK: dxsa.unknown +// CHECK: dxsa.dcl_output o<0, > +// CHECK: dxsa.dcl_temps 2 +// CHECK: %[[INDEX_0:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_0:.*]] = dxsa.operand %[[INDEX_0]] {mask = 16 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_1:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[INDEX_2:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_1:.*]] = dxsa.operand %[[INDEX_1]], %[[INDEX_2]] {num_components = 4 : i32, one = 0 : i32, type = 8 : i32} +// CHECK: dxsa.instruction "mov" %[[OPERAND_0]], %[[OPERAND_1]] +// CHECK: dxsa.unknown +// CHECK: %[[INDEX_3:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_2:.*]] = dxsa.operand %[[INDEX_3]] {mask = 16 : i32, num_components = 4 : i32, type = 2 : i32} +// CHECK: %[[INDEX_4:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_3:.*]] = dxsa.operand %[[INDEX_4]] {num_components = 4 : i32, one = 1 : i32, type = 0 : i32} +// CHECK: dxsa.instruction "mov" %[[OPERAND_2]], %[[OPERAND_3]] +// CHECK: dxsa.instruction "ret" +// CHECK: %[[INDEX_5:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_4:.*]] = dxsa.operand %[[INDEX_5]] {num_components = 0 : i32, type = 17 : i32} +// CHECK: dxsa.instruction "label" %[[OPERAND_4]] +// CHECK: %[[INDEX_6:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_5:.*]] = dxsa.operand %[[INDEX_6]] {mask = 192 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_7:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_6:.*]] = dxsa.operand %[[INDEX_7]] {num_components = 4 : i32, one = 0 : i32, type = 0 : i32} +// CHECK: %[[INDEX_8:.*]] = dxsa.index.rel %[[OPERAND_6]] +// CHECK: %[[OPERAND_7:.*]] = dxsa.operand %[[INDEX_8]] {num_components = 4 : i32, swizzle = dense<[2, 2, 2, 3]> : vector<4xi32>, type = 29 : i32} +// CHECK: dxsa.instruction "mov" %[[OPERAND_5]], %[[OPERAND_7]] +// CHECK: dxsa.unknown +// CHECK: %[[INDEX_9:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_8:.*]] = dxsa.operand %[[INDEX_9]] {mask = 128 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_10:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_9:.*]] = dxsa.operand %[[INDEX_10]] {num_components = 4 : i32, one = 0 : i32, type = 0 : i32} +// CHECK: %[[INDEX_11:.*]] = dxsa.index.rel %[[OPERAND_9]] +// CHECK: %[[OPERAND_10:.*]] = dxsa.operand %[[INDEX_11]] {num_components = 4 : i32, one = 1 : i32, type = 29 : i32} +// CHECK: dxsa.instruction "mov" %[[OPERAND_8]], %[[OPERAND_10]] +// CHECK: %[[INDEX_12:.*]] = dxsa.index.imm {imm = 1 : i32} +// CHECK: %[[OPERAND_11:.*]] = dxsa.operand %[[INDEX_12]] {mask = 16 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_13:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_12:.*]] = dxsa.operand %[[INDEX_13]] {num_components = 4 : i32, one = 0 : i32, type = 0 : i32} +// CHECK: %[[INDEX_14:.*]] = dxsa.index.rel %[[OPERAND_12]] +// CHECK: %[[OPERAND_13:.*]] = dxsa.operand %[[INDEX_14]] {num_components = 4 : i32, one = 0 : i32, type = 29 : i32} +// CHECK: dxsa.instruction "mov" %[[OPERAND_11]], %[[OPERAND_13]] +// CHECK: dxsa.add r<0, >, r<0, >, cb<[r<1, >, r<0, >], vector, > +// CHECK: dxsa.instruction "ret" +// CHECK: %[[INDEX_15:.*]] = dxsa.index.imm {imm = 1 : i32} +// CHECK: %[[OPERAND_14:.*]] = dxsa.operand %[[INDEX_15]] {num_components = 0 : i32, type = 17 : i32} +// CHECK: dxsa.instruction "label" %[[OPERAND_14]] +// CHECK: %[[INDEX_16:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_15:.*]] = dxsa.operand %[[INDEX_16]] {mask = 192 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_17:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_16:.*]] = dxsa.operand %[[INDEX_17]] {num_components = 4 : i32, one = 0 : i32, type = 0 : i32} +// CHECK: %[[INDEX_18:.*]] = dxsa.index.rel %[[OPERAND_16]] +// CHECK: %[[OPERAND_17:.*]] = dxsa.operand %[[INDEX_18]] {num_components = 4 : i32, swizzle = dense<[2, 2, 2, 3]> : vector<4xi32>, type = 29 : i32} +// CHECK: dxsa.instruction "mov" %[[OPERAND_15]], %[[OPERAND_17]] +// CHECK: dxsa.unknown +// CHECK: %[[INDEX_19:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_18:.*]] = dxsa.operand %[[INDEX_19]] {mask = 128 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_20:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_19:.*]] = dxsa.operand %[[INDEX_20]] {num_components = 4 : i32, one = 0 : i32, type = 0 : i32} +// CHECK: %[[INDEX_21:.*]] = dxsa.index.rel %[[OPERAND_19]] +// CHECK: %[[OPERAND_20:.*]] = dxsa.operand %[[INDEX_21]] {num_components = 4 : i32, one = 1 : i32, type = 29 : i32} +// CHECK: dxsa.instruction "mov" %[[OPERAND_18]], %[[OPERAND_20]] +// CHECK: %[[INDEX_22:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_21:.*]] = dxsa.operand %[[INDEX_22]] {mask = 16 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_23:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_22:.*]] = dxsa.operand %[[INDEX_23]] {num_components = 4 : i32, one = 0 : i32, type = 0 : i32} +// CHECK: %[[INDEX_24:.*]] = dxsa.index.rel %[[OPERAND_22]] +// CHECK: %[[OPERAND_23:.*]] = dxsa.operand %[[INDEX_24]] {num_components = 4 : i32, one = 0 : i32, type = 29 : i32} +// CHECK: dxsa.instruction "mov" %[[OPERAND_21]], %[[OPERAND_23]] +// CHECK: dxsa.mul r<0, >, r<0, >, cb<[r<0, >, r<0, >], vector, > +// CHECK: dxsa.instruction "ret" + diff --git a/mlir/test/Target/DXSA/hlsl/liveness1.test b/mlir/test/Target/DXSA/hlsl/liveness1.test new file mode 100644 index 000000000000..d4f88953dff8 --- /dev/null +++ b/mlir/test/Target/DXSA/hlsl/liveness1.test @@ -0,0 +1,21 @@ +// RUN: mlir-translate --import-dxsa-bin %S/inputs/liveness1.shex | FileCheck %s +// NOTE: Assertions have been autogenerated by utils/generate-test-checks.py + + +// CHECK-LABEL: dxsa.dcl_global_flags +// CHECK: dxsa.dcl_input_ps linear v<0> +// CHECK: dxsa.dcl_input_ps constant v<1, > +// CHECK: dxsa.dcl_output o<0, > +// CHECK: dxsa.dcl_temps 1 +// CHECK: dxsa.dp2 r<0, >, v<0, >, v<0, > +// CHECK: dxsa.ieq r<0, >, v<1, >, l(0x1) +// CHECK: %[[INDEX_0:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_0:.*]] = dxsa.operand %[[INDEX_0]] {num_components = 4 : i32, one = 1 : i32, type = 0 : i32} +// CHECK: dxsa.instruction "if" %[[OPERAND_0]] +// CHECK: dxsa.add r<0, >, r<0, >, l(0x42300000) +// CHECK: dxsa.instruction "else" +// CHECK: dxsa.add r<0, >, v<0, >, l(0xC29A0000) +// CHECK: dxsa.instruction "endif" +// CHECK: dxsa.mul o<0, >, r<0, >, r<0, > +// CHECK: dxsa.instruction "ret" + diff --git a/mlir/test/Target/DXSA/hlsl/loop1.test b/mlir/test/Target/DXSA/hlsl/loop1.test new file mode 100644 index 000000000000..c6d08fd8dc05 --- /dev/null +++ b/mlir/test/Target/DXSA/hlsl/loop1.test @@ -0,0 +1,33 @@ +// RUN: mlir-translate --import-dxsa-bin %S/inputs/loop1.shex | FileCheck %s +// NOTE: Assertions have been autogenerated by utils/generate-test-checks.py + + +// CHECK-LABEL: dxsa.dcl_global_flags +// CHECK: dxsa.dcl_input_ps linear v<0, > +// CHECK: dxsa.dcl_input_ps constant v<1, > +// CHECK: dxsa.dcl_output o<0, > +// CHECK: dxsa.dcl_temps 1 +// CHECK: %[[INDEX_0:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_0:.*]] = dxsa.operand %[[INDEX_0]] {mask = 48 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[OPERAND_1:.*]] = dxsa.operand.imm {imm = dense<0> : vector<4xi32>} +// CHECK: dxsa.instruction "mov" %[[OPERAND_0]], %[[OPERAND_1]] +// CHECK: dxsa.instruction "loop" +// CHECK: dxsa.ige r<0, >, r<0, >, v<1, > +// CHECK: %[[INDEX_1:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_2:.*]] = dxsa.operand %[[INDEX_1]] {num_components = 4 : i32, one = 2 : i32, type = 0 : i32} +// CHECK: dxsa.instruction "breakc" %[[OPERAND_2]] +// CHECK: dxsa.add r<0, >, r<0, >, v<0, > +// CHECK: %[[INDEX_2:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_3:.*]] = dxsa.operand %[[INDEX_2]] {mask = 32 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_3:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_4:.*]] = dxsa.operand %[[INDEX_3]] {num_components = 4 : i32, one = 1 : i32, type = 0 : i32} +// CHECK: %[[OPERAND_5:.*]] = dxsa.operand.imm {imm = dense<1> : vector<1xi32>} +// CHECK: dxsa.instruction "iadd" %[[OPERAND_3]], %[[OPERAND_4]], %[[OPERAND_5]] +// CHECK: dxsa.instruction "endloop" +// CHECK: %[[INDEX_4:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_6:.*]] = dxsa.operand %[[INDEX_4]] {mask = 16 : i32, num_components = 4 : i32, type = 2 : i32} +// CHECK: %[[INDEX_5:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_7:.*]] = dxsa.operand %[[INDEX_5]] {num_components = 4 : i32, one = 0 : i32, type = 0 : i32} +// CHECK: dxsa.instruction "mov" %[[OPERAND_6]], %[[OPERAND_7]] +// CHECK: dxsa.instruction "ret" + diff --git a/mlir/test/Target/DXSA/hlsl/loop2.test b/mlir/test/Target/DXSA/hlsl/loop2.test new file mode 100644 index 000000000000..efdf3f62d115 --- /dev/null +++ b/mlir/test/Target/DXSA/hlsl/loop2.test @@ -0,0 +1,49 @@ +// RUN: mlir-translate --import-dxsa-bin %S/inputs/loop2.shex | FileCheck %s +// NOTE: Assertions have been autogenerated by utils/generate-test-checks.py + + +// CHECK-LABEL: dxsa.dcl_global_flags +// CHECK: dxsa.dcl_input_ps linear v<0, > +// CHECK: dxsa.dcl_input_ps constant v<1, > +// CHECK: dxsa.dcl_output o<0, > +// CHECK: dxsa.dcl_temps 1 +// CHECK: %[[INDEX_0:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_0:.*]] = dxsa.operand %[[INDEX_0]] {mask = 48 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[OPERAND_1:.*]] = dxsa.operand.imm {imm = dense<0> : vector<4xi32>} +// CHECK: dxsa.instruction "mov" %[[OPERAND_0]], %[[OPERAND_1]] +// CHECK: %[[INDEX_1:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_2:.*]] = dxsa.operand %[[INDEX_1]] {mask = 64 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_2:.*]] = dxsa.index.imm {imm = 1 : i32} +// CHECK: %[[OPERAND_3:.*]] = dxsa.operand %[[INDEX_2]] {num_components = 4 : i32, one = 1 : i32, type = 1 : i32} +// CHECK: dxsa.instruction "mov" %[[OPERAND_2]], %[[OPERAND_3]] +// CHECK: dxsa.instruction "loop" +// CHECK: dxsa.ige r<0, >, r<0, >, v<1, > +// CHECK: %[[INDEX_3:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_4:.*]] = dxsa.operand %[[INDEX_3]] {num_components = 4 : i32, one = 3 : i32, type = 0 : i32} +// CHECK: dxsa.instruction "breakc" %[[OPERAND_4]] +// CHECK: %[[INDEX_4:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_5:.*]] = dxsa.operand %[[INDEX_4]] {num_components = 4 : i32, one = 2 : i32, type = 0 : i32} +// CHECK: dxsa.instruction "if" %[[OPERAND_5]] +// CHECK: dxsa.add r<0, >, r<0, >, l(0x43480000) +// CHECK: %[[INDEX_5:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_6:.*]] = dxsa.operand %[[INDEX_5]] {mask = 16 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_6:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_7:.*]] = dxsa.operand %[[INDEX_6]] {num_components = 4 : i32, one = 3 : i32, type = 0 : i32} +// CHECK: dxsa.instruction "mov" %[[OPERAND_6]], %[[OPERAND_7]] +// CHECK: dxsa.instruction "break" +// CHECK: dxsa.instruction "endif" +// CHECK: dxsa.add r<0, >, r<0, >, v<0, > +// CHECK: %[[INDEX_7:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_8:.*]] = dxsa.operand %[[INDEX_7]] {mask = 32 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_8:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_9:.*]] = dxsa.operand %[[INDEX_8]] {num_components = 4 : i32, one = 1 : i32, type = 0 : i32} +// CHECK: %[[OPERAND_10:.*]] = dxsa.operand.imm {imm = dense<1> : vector<1xi32>} +// CHECK: dxsa.instruction "iadd" %[[OPERAND_8]], %[[OPERAND_9]], %[[OPERAND_10]] +// CHECK: dxsa.instruction "endloop" +// CHECK: %[[INDEX_9:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_11:.*]] = dxsa.operand %[[INDEX_9]] {mask = 16 : i32, num_components = 4 : i32, type = 2 : i32} +// CHECK: %[[INDEX_10:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_12:.*]] = dxsa.operand %[[INDEX_10]] {num_components = 4 : i32, one = 0 : i32, type = 0 : i32} +// CHECK: dxsa.instruction "mov" %[[OPERAND_11]], %[[OPERAND_12]] +// CHECK: dxsa.instruction "ret" + diff --git a/mlir/test/Target/DXSA/hlsl/loop3.test b/mlir/test/Target/DXSA/hlsl/loop3.test new file mode 100644 index 000000000000..72affaf370f5 --- /dev/null +++ b/mlir/test/Target/DXSA/hlsl/loop3.test @@ -0,0 +1,94 @@ +// RUN: mlir-translate --import-dxsa-bin %S/inputs/loop3.shex | FileCheck %s +// NOTE: Assertions have been autogenerated by utils/generate-test-checks.py + + +// CHECK-LABEL: dxsa.dcl_global_flags +// CHECK: dxsa.dcl_input_ps linear v<0, > +// CHECK: dxsa.dcl_input_ps constant v<1, > +// CHECK: dxsa.dcl_output o<0, > +// CHECK: dxsa.dcl_temps 3 +// CHECK: %[[INDEX_0:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_0:.*]] = dxsa.operand %[[INDEX_0]] {mask = 16 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[OPERAND_1:.*]] = dxsa.operand.imm {imm = dense<16> : vector<1xi32>} +// CHECK: dxsa.instruction "mov" %[[OPERAND_0]], %[[OPERAND_1]] +// CHECK: %[[INDEX_1:.*]] = dxsa.index.imm {imm = 1 : i32} +// CHECK: %[[OPERAND_2:.*]] = dxsa.operand %[[INDEX_1]] {mask = 16 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_2:.*]] = dxsa.index.imm {imm = 1 : i32} +// CHECK: %[[OPERAND_3:.*]] = dxsa.operand %[[INDEX_2]] {num_components = 4 : i32, one = 2 : i32, type = 1 : i32} +// CHECK: dxsa.instruction "mov" %[[OPERAND_2]], %[[OPERAND_3]] +// CHECK: %[[INDEX_3:.*]] = dxsa.index.imm {imm = 1 : i32} +// CHECK: %[[OPERAND_4:.*]] = dxsa.operand %[[INDEX_3]] {mask = 32 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[OPERAND_5:.*]] = dxsa.operand.imm {imm = dense<0> : vector<1xi32>} +// CHECK: dxsa.instruction "mov" %[[OPERAND_4]], %[[OPERAND_5]] +// CHECK: %[[INDEX_4:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_6:.*]] = dxsa.operand %[[INDEX_4]] {mask = 64 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[OPERAND_7:.*]] = dxsa.operand.imm {imm = dense<0> : vector<1xi32>} +// CHECK: dxsa.instruction "mov" %[[OPERAND_6]], %[[OPERAND_7]] +// CHECK: dxsa.instruction "loop" +// CHECK: dxsa.ige r<0, >, r<0, >, v<1, > +// CHECK: %[[INDEX_5:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_8:.*]] = dxsa.operand %[[INDEX_5]] {num_components = 4 : i32, one = 3 : i32, type = 0 : i32} +// CHECK: dxsa.instruction "breakc" %[[OPERAND_8]] +// CHECK: dxsa.ieq r<0, >, r<1, >, l(0x9) +// CHECK: %[[INDEX_6:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_9:.*]] = dxsa.operand %[[INDEX_6]] {num_components = 4 : i32, one = 3 : i32, type = 0 : i32} +// CHECK: dxsa.instruction "if" %[[OPERAND_9]] +// CHECK: dxsa.instruction "break" +// CHECK: dxsa.instruction "endif" +// CHECK: %[[INDEX_7:.*]] = dxsa.index.imm {imm = 1 : i32} +// CHECK: %[[OPERAND_10:.*]] = dxsa.operand %[[INDEX_7]] {mask = 192 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_8:.*]] = dxsa.index.imm {imm = 1 : i32} +// CHECK: %[[OPERAND_11:.*]] = dxsa.operand %[[INDEX_8]] {num_components = 4 : i32, swizzle = dense<[0, 0, 0, 1]> : vector<4xi32>, type = 0 : i32} +// CHECK: dxsa.instruction "mov" %[[OPERAND_10]], %[[OPERAND_11]] +// CHECK: %[[INDEX_9:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_12:.*]] = dxsa.operand %[[INDEX_9]] {mask = 128 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[OPERAND_13:.*]] = dxsa.operand.imm {imm = dense<0> : vector<1xi32>} +// CHECK: dxsa.instruction "mov" %[[OPERAND_12]], %[[OPERAND_13]] +// CHECK: dxsa.instruction "loop" +// CHECK: dxsa.ige r<2, >, r<0, >, v<1, > +// CHECK: %[[INDEX_10:.*]] = dxsa.index.imm {imm = 2 : i32} +// CHECK: %[[OPERAND_14:.*]] = dxsa.operand %[[INDEX_10]] {num_components = 4 : i32, one = 0 : i32, type = 0 : i32} +// CHECK: dxsa.instruction "breakc" %[[OPERAND_14]] +// CHECK: dxsa.ieq r<2, >, r<1, >, l(0x10) +// CHECK: %[[INDEX_11:.*]] = dxsa.index.imm {imm = 2 : i32} +// CHECK: %[[OPERAND_15:.*]] = dxsa.operand %[[INDEX_11]] {num_components = 4 : i32, one = 0 : i32, type = 0 : i32} +// CHECK: dxsa.instruction "if" %[[OPERAND_15]] +// CHECK: %[[INDEX_12:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_16:.*]] = dxsa.operand %[[INDEX_12]] {mask = 32 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_13:.*]] = dxsa.index.imm {imm = 1 : i32} +// CHECK: %[[OPERAND_17:.*]] = dxsa.operand %[[INDEX_13]] {num_components = 4 : i32, one = 3 : i32, type = 0 : i32} +// CHECK: dxsa.instruction "mov" %[[OPERAND_16]], %[[OPERAND_17]] +// CHECK: %[[INDEX_14:.*]] = dxsa.index.imm {imm = 1 : i32} +// CHECK: %[[OPERAND_18:.*]] = dxsa.operand %[[INDEX_14]] {mask = 192 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_15:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_19:.*]] = dxsa.operand %[[INDEX_15]] {num_components = 4 : i32, swizzle = dense<[0, 0, 0, 1]> : vector<4xi32>, type = 0 : i32} +// CHECK: dxsa.instruction "mov" %[[OPERAND_18]], %[[OPERAND_19]] +// CHECK: dxsa.instruction "break" +// CHECK: dxsa.instruction "endif" +// CHECK: dxsa.add r<1, >, r<1, >, v<0, > +// CHECK: %[[INDEX_16:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_20:.*]] = dxsa.operand %[[INDEX_16]] {mask = 128 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_17:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_21:.*]] = dxsa.operand %[[INDEX_17]] {num_components = 4 : i32, one = 3 : i32, type = 0 : i32} +// CHECK: %[[OPERAND_22:.*]] = dxsa.operand.imm {imm = dense<1> : vector<1xi32>} +// CHECK: dxsa.instruction "iadd" %[[OPERAND_20]], %[[OPERAND_21]], %[[OPERAND_22]] +// CHECK: dxsa.instruction "endloop" +// CHECK: %[[INDEX_18:.*]] = dxsa.index.imm {imm = 1 : i32} +// CHECK: %[[OPERAND_23:.*]] = dxsa.operand %[[INDEX_18]] {mask = 48 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_19:.*]] = dxsa.index.imm {imm = 1 : i32} +// CHECK: %[[OPERAND_24:.*]] = dxsa.operand %[[INDEX_19]] {num_components = 4 : i32, swizzle = dense<[2, 3, 2, 2]> : vector<4xi32>, type = 0 : i32} +// CHECK: dxsa.instruction "mov" %[[OPERAND_23]], %[[OPERAND_24]] +// CHECK: %[[INDEX_20:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_25:.*]] = dxsa.operand %[[INDEX_20]] {mask = 64 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_21:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_26:.*]] = dxsa.operand %[[INDEX_21]] {num_components = 4 : i32, one = 2 : i32, type = 0 : i32} +// CHECK: %[[OPERAND_27:.*]] = dxsa.operand.imm {imm = dense<1> : vector<1xi32>} +// CHECK: dxsa.instruction "iadd" %[[OPERAND_25]], %[[OPERAND_26]], %[[OPERAND_27]] +// CHECK: dxsa.instruction "endloop" +// CHECK: %[[INDEX_22:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_28:.*]] = dxsa.operand %[[INDEX_22]] {mask = 16 : i32, num_components = 4 : i32, type = 2 : i32} +// CHECK: %[[INDEX_23:.*]] = dxsa.index.imm {imm = 1 : i32} +// CHECK: %[[OPERAND_29:.*]] = dxsa.operand %[[INDEX_23]] {num_components = 4 : i32, one = 1 : i32, type = 0 : i32} +// CHECK: dxsa.instruction "mov" %[[OPERAND_28]], %[[OPERAND_29]] +// CHECK: dxsa.instruction "ret" + diff --git a/mlir/test/Target/DXSA/hlsl/loop4.test b/mlir/test/Target/DXSA/hlsl/loop4.test new file mode 100644 index 000000000000..446502f0a802 --- /dev/null +++ b/mlir/test/Target/DXSA/hlsl/loop4.test @@ -0,0 +1,81 @@ +// RUN: mlir-translate --import-dxsa-bin %S/inputs/loop4.shex | FileCheck %s +// NOTE: Assertions have been autogenerated by utils/generate-test-checks.py + + +// CHECK-LABEL: dxsa.dcl_global_flags +// CHECK: dxsa.dcl_input_ps linear v<0, > +// CHECK: dxsa.dcl_input_ps constant v<1, > +// CHECK: dxsa.dcl_output o<0, > +// CHECK: dxsa.dcl_temps 3 +// CHECK: %[[INDEX_0:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_0:.*]] = dxsa.operand %[[INDEX_0]] {mask = 96 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[OPERAND_1:.*]] = dxsa.operand.imm {imm = dense<[0, 5, 7, 0]> : vector<4xi32>} +// CHECK: dxsa.instruction "mov" %[[OPERAND_0]], %[[OPERAND_1]] +// CHECK: %[[INDEX_1:.*]] = dxsa.index.imm {imm = 1 : i32} +// CHECK: %[[OPERAND_2:.*]] = dxsa.operand %[[INDEX_1]] {mask = 32 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_2:.*]] = dxsa.index.imm {imm = 1 : i32} +// CHECK: %[[OPERAND_3:.*]] = dxsa.operand %[[INDEX_2]] {num_components = 4 : i32, one = 2 : i32, type = 1 : i32} +// CHECK: dxsa.instruction "mov" %[[OPERAND_2]], %[[OPERAND_3]] +// CHECK: %[[INDEX_3:.*]] = dxsa.index.imm {imm = 1 : i32} +// CHECK: %[[OPERAND_4:.*]] = dxsa.operand %[[INDEX_3]] {mask = 16 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[OPERAND_5:.*]] = dxsa.operand.imm {imm = dense<0> : vector<1xi32>} +// CHECK: dxsa.instruction "mov" %[[OPERAND_4]], %[[OPERAND_5]] +// CHECK: %[[INDEX_4:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_6:.*]] = dxsa.operand %[[INDEX_4]] {mask = 128 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[OPERAND_7:.*]] = dxsa.operand.imm {imm = dense<0> : vector<1xi32>} +// CHECK: dxsa.instruction "mov" %[[OPERAND_6]], %[[OPERAND_7]] +// CHECK: dxsa.instruction "loop" +// CHECK: dxsa.ige r<1, >, r<1, >, v<1, > +// CHECK: %[[INDEX_5:.*]] = dxsa.index.imm {imm = 1 : i32} +// CHECK: %[[OPERAND_8:.*]] = dxsa.operand %[[INDEX_5]] {num_components = 4 : i32, one = 2 : i32, type = 0 : i32} +// CHECK: dxsa.instruction "breakc" %[[OPERAND_8]] +// CHECK: dxsa.ieq r<1, >, r<1, >, l(0x5) +// CHECK: %[[INDEX_6:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_9:.*]] = dxsa.operand %[[INDEX_6]] {mask = 16 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_7:.*]] = dxsa.index.imm {imm = 1 : i32} +// CHECK: %[[OPERAND_10:.*]] = dxsa.operand %[[INDEX_7]] {num_components = 4 : i32, one = 0 : i32, type = 0 : i32} +// CHECK: %[[OPERAND_11:.*]] = dxsa.operand.imm {imm = dense<1> : vector<1xi32>} +// CHECK: dxsa.instruction "iadd" %[[OPERAND_9]], %[[OPERAND_10]], %[[OPERAND_11]] +// CHECK: %[[INDEX_8:.*]] = dxsa.index.imm {imm = 2 : i32} +// CHECK: %[[OPERAND_12:.*]] = dxsa.operand %[[INDEX_8]] {mask = 48 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_9:.*]] = dxsa.index.imm {imm = 1 : i32} +// CHECK: %[[OPERAND_13:.*]] = dxsa.operand %[[INDEX_9]] {num_components = 4 : i32, swizzle = dense<2> : vector<4xi32>, type = 0 : i32} +// CHECK: %[[INDEX_10:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_14:.*]] = dxsa.operand %[[INDEX_10]] {num_components = 4 : i32, swizzle = dense<[1, 0, 1, 1]> : vector<4xi32>, type = 0 : i32} +// CHECK: %[[INDEX_11:.*]] = dxsa.index.imm {imm = 1 : i32} +// CHECK: %[[OPERAND_15:.*]] = dxsa.operand %[[INDEX_11]] {num_components = 4 : i32, swizzle = dense<[1, 0, 1, 1]> : vector<4xi32>, type = 0 : i32} +// CHECK: dxsa.instruction "movc" %[[OPERAND_12]], %[[OPERAND_13]], %[[OPERAND_14]], %[[OPERAND_15]] +// CHECK: %[[INDEX_12:.*]] = dxsa.index.imm {imm = 1 : i32} +// CHECK: %[[OPERAND_16:.*]] = dxsa.operand %[[INDEX_12]] {mask = 48 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_13:.*]] = dxsa.index.imm {imm = 2 : i32} +// CHECK: %[[OPERAND_17:.*]] = dxsa.operand %[[INDEX_13]] {num_components = 4 : i32, swizzle = dense<[1, 0, 1, 1]> : vector<4xi32>, type = 0 : i32} +// CHECK: dxsa.instruction "mov" %[[OPERAND_16]], %[[OPERAND_17]] +// CHECK: %[[INDEX_14:.*]] = dxsa.index.imm {imm = 1 : i32} +// CHECK: %[[OPERAND_18:.*]] = dxsa.operand %[[INDEX_14]] {num_components = 4 : i32, one = 2 : i32, type = 0 : i32} +// CHECK: dxsa.instruction "continuec" %[[OPERAND_18]] +// CHECK: dxsa.ieq r<1, >, r<1, >, l(0x7) +// CHECK: %[[INDEX_15:.*]] = dxsa.index.imm {imm = 1 : i32} +// CHECK: %[[OPERAND_19:.*]] = dxsa.operand %[[INDEX_15]] {num_components = 4 : i32, one = 2 : i32, type = 0 : i32} +// CHECK: dxsa.instruction "if" %[[OPERAND_19]] +// CHECK: %[[INDEX_16:.*]] = dxsa.index.imm {imm = 1 : i32} +// CHECK: %[[OPERAND_20:.*]] = dxsa.operand %[[INDEX_16]] {mask = 48 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_17:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_21:.*]] = dxsa.operand %[[INDEX_17]] {num_components = 4 : i32, swizzle = dense<[0, 2, 0, 0]> : vector<4xi32>, type = 0 : i32} +// CHECK: dxsa.instruction "mov" %[[OPERAND_20]], %[[OPERAND_21]] +// CHECK: dxsa.instruction "continue" +// CHECK: dxsa.instruction "endif" +// CHECK: dxsa.add r<0, >, r<0, >, v<0, > +// CHECK: %[[INDEX_18:.*]] = dxsa.index.imm {imm = 1 : i32} +// CHECK: %[[OPERAND_22:.*]] = dxsa.operand %[[INDEX_18]] {mask = 16 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_19:.*]] = dxsa.index.imm {imm = 1 : i32} +// CHECK: %[[OPERAND_23:.*]] = dxsa.operand %[[INDEX_19]] {num_components = 4 : i32, one = 0 : i32, type = 0 : i32} +// CHECK: %[[OPERAND_24:.*]] = dxsa.operand.imm {imm = dense<1> : vector<1xi32>} +// CHECK: dxsa.instruction "iadd" %[[OPERAND_22]], %[[OPERAND_23]], %[[OPERAND_24]] +// CHECK: dxsa.instruction "endloop" +// CHECK: %[[INDEX_20:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_25:.*]] = dxsa.operand %[[INDEX_20]] {mask = 16 : i32, num_components = 4 : i32, type = 2 : i32} +// CHECK: %[[INDEX_21:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_26:.*]] = dxsa.operand %[[INDEX_21]] {num_components = 4 : i32, one = 3 : i32, type = 0 : i32} +// CHECK: dxsa.instruction "mov" %[[OPERAND_25]], %[[OPERAND_26]] +// CHECK: dxsa.instruction "ret" + diff --git a/mlir/test/Target/DXSA/hlsl/loop5.test b/mlir/test/Target/DXSA/hlsl/loop5.test new file mode 100644 index 000000000000..e4bf6bcbe919 --- /dev/null +++ b/mlir/test/Target/DXSA/hlsl/loop5.test @@ -0,0 +1,58 @@ +// RUN: mlir-translate --import-dxsa-bin %S/inputs/loop5.shex | FileCheck %s +// NOTE: Assertions have been autogenerated by utils/generate-test-checks.py + + +// CHECK-LABEL: dxsa.dcl_global_flags +// CHECK: dxsa.dcl_input_ps linear v<0, > +// CHECK: dxsa.dcl_input_ps constant v<1, > +// CHECK: dxsa.dcl_output o<0, > +// CHECK: dxsa.dcl_temps 1 +// CHECK: %[[INDEX_0:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_0:.*]] = dxsa.operand %[[INDEX_0]] {mask = 16 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_1:.*]] = dxsa.index.imm {imm = 1 : i32} +// CHECK: %[[OPERAND_1:.*]] = dxsa.operand %[[INDEX_1]] {num_components = 4 : i32, one = 2 : i32, type = 1 : i32} +// CHECK: dxsa.instruction "mov" %[[OPERAND_0]], %[[OPERAND_1]] +// CHECK: %[[INDEX_2:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_2:.*]] = dxsa.operand %[[INDEX_2]] {mask = 96 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[OPERAND_3:.*]] = dxsa.operand.imm {imm = dense<0> : vector<4xi32>} +// CHECK: dxsa.instruction "mov" %[[OPERAND_2]], %[[OPERAND_3]] +// CHECK: dxsa.instruction "loop" +// CHECK: dxsa.ige r<0, >, r<0, >, v<1, > +// CHECK: %[[INDEX_3:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_4:.*]] = dxsa.operand %[[INDEX_3]] {num_components = 4 : i32, one = 3 : i32, type = 0 : i32} +// CHECK: dxsa.instruction "breakc" %[[OPERAND_4]] +// CHECK: dxsa.ieq r<0, >, r<0, >, l(0x5) +// CHECK: %[[INDEX_4:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_5:.*]] = dxsa.operand %[[INDEX_4]] {mask = 16 : i32, num_components = 4 : i32, type = 2 : i32} +// CHECK: %[[INDEX_5:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_6:.*]] = dxsa.operand %[[INDEX_5]] {num_components = 4 : i32, one = 1 : i32, type = 0 : i32} +// CHECK: dxsa.instruction "mov" %[[OPERAND_5]], %[[OPERAND_6]] +// CHECK: %[[INDEX_6:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_7:.*]] = dxsa.operand %[[INDEX_6]] {num_components = 4 : i32, one = 3 : i32, type = 0 : i32} +// CHECK: dxsa.instruction "retc" %[[OPERAND_7]] +// CHECK: dxsa.ieq r<0, >, r<0, >, l(0x7) +// CHECK: %[[INDEX_7:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_8:.*]] = dxsa.operand %[[INDEX_7]] {num_components = 4 : i32, one = 3 : i32, type = 0 : i32} +// CHECK: dxsa.instruction "if" %[[OPERAND_8]] +// CHECK: %[[INDEX_8:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_9:.*]] = dxsa.operand %[[INDEX_8]] {mask = 16 : i32, num_components = 4 : i32, type = 2 : i32} +// CHECK: %[[INDEX_9:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_10:.*]] = dxsa.operand %[[INDEX_9]] {num_components = 4 : i32, one = 1 : i32, type = 0 : i32} +// CHECK: dxsa.instruction "mov" %[[OPERAND_9]], %[[OPERAND_10]] +// CHECK: dxsa.instruction "ret" +// CHECK: dxsa.instruction "endif" +// CHECK: dxsa.add r<0, >, r<0, >, v<0, > +// CHECK: %[[INDEX_10:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_11:.*]] = dxsa.operand %[[INDEX_10]] {mask = 64 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_11:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_12:.*]] = dxsa.operand %[[INDEX_11]] {num_components = 4 : i32, one = 2 : i32, type = 0 : i32} +// CHECK: %[[OPERAND_13:.*]] = dxsa.operand.imm {imm = dense<1> : vector<1xi32>} +// CHECK: dxsa.instruction "iadd" %[[OPERAND_11]], %[[OPERAND_12]], %[[OPERAND_13]] +// CHECK: dxsa.instruction "endloop" +// CHECK: %[[INDEX_12:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_14:.*]] = dxsa.operand %[[INDEX_12]] {mask = 16 : i32, num_components = 4 : i32, type = 2 : i32} +// CHECK: %[[INDEX_13:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_15:.*]] = dxsa.operand %[[INDEX_13]] {num_components = 4 : i32, one = 1 : i32, type = 0 : i32} +// CHECK: dxsa.instruction "mov" %[[OPERAND_14]], %[[OPERAND_15]] +// CHECK: dxsa.instruction "ret" + diff --git a/mlir/test/Target/DXSA/hlsl/minprec1.test b/mlir/test/Target/DXSA/hlsl/minprec1.test new file mode 100644 index 000000000000..b55edeaec763 --- /dev/null +++ b/mlir/test/Target/DXSA/hlsl/minprec1.test @@ -0,0 +1,16 @@ +// RUN: mlir-translate --import-dxsa-bin %S/inputs/minprec1.shex | FileCheck %s +// NOTE: Assertions have been autogenerated by utils/generate-test-checks.py + + +// CHECK-LABEL: dxsa.dcl_global_flags +// CHECK: dxsa.dcl_input_ps linear v<0, min16f, > +// CHECK: dxsa.dcl_output o<0, > +// CHECK: dxsa.dcl_temps 1 +// CHECK: dxsa.add r<0, min16f, >, v<0, min16f, >, l(0x40000000) +// CHECK: %[[INDEX_0:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_0:.*]] = dxsa.operand %[[INDEX_0]] {mask = 16 : i32, num_components = 4 : i32, type = 2 : i32} +// CHECK: %[[INDEX_1:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_1:.*]] = dxsa.operand %[[INDEX_1]] {min_precision = 1 : i32, num_components = 4 : i32, one = 0 : i32, type = 0 : i32} +// CHECK: dxsa.instruction "mov" %[[OPERAND_0]], %[[OPERAND_1]] +// CHECK: dxsa.instruction "ret" + diff --git a/mlir/test/Target/DXSA/hlsl/minprec2.test b/mlir/test/Target/DXSA/hlsl/minprec2.test new file mode 100644 index 000000000000..6a12031b48b0 --- /dev/null +++ b/mlir/test/Target/DXSA/hlsl/minprec2.test @@ -0,0 +1,14 @@ +// RUN: mlir-translate --import-dxsa-bin %S/inputs/minprec2.shex | FileCheck %s +// NOTE: Assertions have been autogenerated by utils/generate-test-checks.py + + +// CHECK-LABEL: dxsa.dcl_global_flags +// CHECK: dxsa.dcl_input_ps linear v<0, min16f, > +// CHECK: dxsa.dcl_output o<0, > +// CHECK: %[[INDEX_0:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_0:.*]] = dxsa.operand %[[INDEX_0]] {mask = 16 : i32, num_components = 4 : i32, type = 2 : i32} +// CHECK: %[[INDEX_1:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_1:.*]] = dxsa.operand %[[INDEX_1]] {min_precision = 1 : i32, num_components = 4 : i32, one = 0 : i32, type = 1 : i32} +// CHECK: dxsa.instruction "mov" %[[OPERAND_0]], %[[OPERAND_1]] +// CHECK: dxsa.instruction "ret" + diff --git a/mlir/test/Target/DXSA/hlsl/minprec3.test b/mlir/test/Target/DXSA/hlsl/minprec3.test new file mode 100644 index 000000000000..0a30f8b9124f --- /dev/null +++ b/mlir/test/Target/DXSA/hlsl/minprec3.test @@ -0,0 +1,32 @@ +// RUN: mlir-translate --import-dxsa-bin %S/inputs/minprec3.shex | FileCheck %s +// NOTE: Assertions have been autogenerated by utils/generate-test-checks.py + + +// CHECK-LABEL: dxsa.dcl_global_flags +// CHECK: dxsa.dcl_input_ps constant v<0, min16i, > +// CHECK: dxsa.dcl_output o<0, > +// CHECK: dxsa.dcl_temps 2 +// CHECK: %[[INDEX_0:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_0:.*]] = dxsa.operand %[[INDEX_0]] {mask = 16 : i32, min_precision = 4 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_1:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_1:.*]] = dxsa.operand %[[INDEX_1]] {min_precision = 4 : i32, num_components = 4 : i32, one = 0 : i32, type = 1 : i32} +// CHECK: %[[OPERAND_2:.*]] = dxsa.operand.imm {imm = dense<2> : vector<1xi32>} +// CHECK: dxsa.instruction "iadd" %[[OPERAND_0]], %[[OPERAND_1]], %[[OPERAND_2]] +// CHECK: dxsa.ieq r<1, >, r<0, min16i, >, l(0x7) +// CHECK: %[[INDEX_2:.*]] = dxsa.index.imm {imm = 1 : i32} +// CHECK: %[[OPERAND_3:.*]] = dxsa.operand %[[INDEX_2]] {num_components = 4 : i32, one = 0 : i32, type = 0 : i32} +// CHECK: dxsa.instruction "if" %[[OPERAND_3]] +// CHECK: %[[INDEX_3:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_4:.*]] = dxsa.operand %[[INDEX_3]] {mask = 16 : i32, num_components = 4 : i32, type = 2 : i32} +// CHECK: %[[OPERAND_5:.*]] = dxsa.operand.imm {imm = dense<4> : vector<1xi32>} +// CHECK: dxsa.instruction "mov" %[[OPERAND_4]], %[[OPERAND_5]] +// CHECK: dxsa.instruction "ret" +// CHECK: dxsa.instruction "else" +// CHECK: %[[INDEX_4:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_6:.*]] = dxsa.operand %[[INDEX_4]] {mask = 16 : i32, num_components = 4 : i32, type = 2 : i32} +// CHECK: %[[OPERAND_7:.*]] = dxsa.operand.imm {imm = dense<1> : vector<1xi32>} +// CHECK: dxsa.instruction "mov" %[[OPERAND_6]], %[[OPERAND_7]] +// CHECK: dxsa.instruction "ret" +// CHECK: dxsa.instruction "endif" +// CHECK: dxsa.instruction "ret" + diff --git a/mlir/test/Target/DXSA/hlsl/minprec4.test b/mlir/test/Target/DXSA/hlsl/minprec4.test new file mode 100644 index 000000000000..c7b5076995c8 --- /dev/null +++ b/mlir/test/Target/DXSA/hlsl/minprec4.test @@ -0,0 +1,21 @@ +// RUN: mlir-translate --import-dxsa-bin %S/inputs/minprec4.shex | FileCheck %s +// NOTE: Assertions have been autogenerated by utils/generate-test-checks.py + + +// CHECK-LABEL: dxsa.dcl_global_flags +// CHECK: dxsa.dcl_input_ps constant v<0, min16u, > +// CHECK: dxsa.dcl_output o<0, > +// CHECK: dxsa.dcl_temps 1 +// CHECK: %[[INDEX_0:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_0:.*]] = dxsa.operand %[[INDEX_0]] {mask = 16 : i32, min_precision = 5 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_1:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_1:.*]] = dxsa.operand %[[INDEX_1]] {min_precision = 5 : i32, num_components = 4 : i32, one = 0 : i32, type = 1 : i32} +// CHECK: %[[OPERAND_2:.*]] = dxsa.operand.imm {imm = dense<-3> : vector<1xi32>} +// CHECK: dxsa.instruction "iadd" %[[OPERAND_0]], %[[OPERAND_1]], %[[OPERAND_2]] +// CHECK: %[[INDEX_2:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_3:.*]] = dxsa.operand %[[INDEX_2]] {mask = 16 : i32, num_components = 4 : i32, type = 2 : i32} +// CHECK: %[[INDEX_3:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_4:.*]] = dxsa.operand %[[INDEX_3]] {min_precision = 5 : i32, num_components = 4 : i32, one = 0 : i32, type = 0 : i32} +// CHECK: dxsa.instruction "mov" %[[OPERAND_3]], %[[OPERAND_4]] +// CHECK: dxsa.instruction "ret" + diff --git a/mlir/test/Target/DXSA/hlsl/minprec5.test b/mlir/test/Target/DXSA/hlsl/minprec5.test new file mode 100644 index 000000000000..f8ea38ac6eab --- /dev/null +++ b/mlir/test/Target/DXSA/hlsl/minprec5.test @@ -0,0 +1,10 @@ +// RUN: mlir-translate --import-dxsa-bin %S/inputs/minprec5.shex | FileCheck %s +// NOTE: Assertions have been autogenerated by utils/generate-test-checks.py + + +// CHECK-LABEL: dxsa.dcl_global_flags +// CHECK: dxsa.dcl_input_ps linear v<0, > +// CHECK: dxsa.dcl_output o<0, min16f, > +// CHECK: dxsa.add o<0, min16f, >, v<0, >, l(0x40A00000) +// CHECK: dxsa.instruction "ret" + diff --git a/mlir/test/Target/DXSA/hlsl/minprec6.test b/mlir/test/Target/DXSA/hlsl/minprec6.test new file mode 100644 index 000000000000..cdbb154703cc --- /dev/null +++ b/mlir/test/Target/DXSA/hlsl/minprec6.test @@ -0,0 +1,40 @@ +// RUN: mlir-translate --import-dxsa-bin %S/inputs/minprec6.shex | FileCheck %s +// NOTE: Assertions have been autogenerated by utils/generate-test-checks.py + + +// CHECK-LABEL: dxsa.dcl_global_flags +// CHECK: dxsa.dcl_constant_buffer , +// CHECK: dxsa.dcl_input_ps constant v<0, min16i, > +// CHECK: dxsa.dcl_output o<0, > +// CHECK: dxsa.dcl_temps 2 +// CHECK: %[[INDEX_0:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_0:.*]] = dxsa.operand %[[INDEX_0]] {mask = 16 : i32, min_precision = 4 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_1:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_1:.*]] = dxsa.operand %[[INDEX_1]] {min_precision = 4 : i32, num_components = 4 : i32, one = 0 : i32, type = 1 : i32} +// CHECK: %[[OPERAND_2:.*]] = dxsa.operand.imm {imm = dense<2> : vector<1xi32>} +// CHECK: dxsa.instruction "iadd" %[[OPERAND_0]], %[[OPERAND_1]], %[[OPERAND_2]] +// CHECK: dxsa.ieq r<1, >, r<0, min16i, >, cb<[0, 0], vector, min16i, > +// CHECK: %[[INDEX_2:.*]] = dxsa.index.imm {imm = 1 : i32} +// CHECK: %[[OPERAND_3:.*]] = dxsa.operand %[[INDEX_2]] {num_components = 4 : i32, one = 0 : i32, type = 0 : i32} +// CHECK: dxsa.instruction "if" %[[OPERAND_3]] +// CHECK: %[[INDEX_3:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_4:.*]] = dxsa.operand %[[INDEX_3]] {mask = 16 : i32, min_precision = 4 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_4:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_5:.*]] = dxsa.operand %[[INDEX_4]] {min_precision = 4 : i32, num_components = 4 : i32, one = 0 : i32, type = 1 : i32} +// CHECK: %[[OPERAND_6:.*]] = dxsa.operand.imm {imm = dense<-1> : vector<1xi32>} +// CHECK: dxsa.instruction "iadd" %[[OPERAND_4]], %[[OPERAND_5]], %[[OPERAND_6]] +// CHECK: %[[INDEX_5:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_7:.*]] = dxsa.operand %[[INDEX_5]] {mask = 16 : i32, num_components = 4 : i32, type = 2 : i32} +// CHECK: %[[INDEX_6:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_8:.*]] = dxsa.operand %[[INDEX_6]] {min_precision = 4 : i32, num_components = 4 : i32, one = 0 : i32, type = 0 : i32} +// CHECK: dxsa.instruction "mov" %[[OPERAND_7]], %[[OPERAND_8]] +// CHECK: dxsa.instruction "ret" +// CHECK: dxsa.instruction "else" +// CHECK: %[[INDEX_7:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_9:.*]] = dxsa.operand %[[INDEX_7]] {mask = 16 : i32, num_components = 4 : i32, type = 2 : i32} +// CHECK: %[[OPERAND_10:.*]] = dxsa.operand.imm {imm = dense<1> : vector<1xi32>} +// CHECK: dxsa.instruction "mov" %[[OPERAND_9]], %[[OPERAND_10]] +// CHECK: dxsa.instruction "ret" +// CHECK: dxsa.instruction "endif" +// CHECK: dxsa.instruction "ret" + diff --git a/mlir/test/Target/DXSA/hlsl/minprec7.test b/mlir/test/Target/DXSA/hlsl/minprec7.test new file mode 100644 index 000000000000..e8f05fff92c6 --- /dev/null +++ b/mlir/test/Target/DXSA/hlsl/minprec7.test @@ -0,0 +1,16 @@ +// RUN: mlir-translate --import-dxsa-bin %S/inputs/minprec7.shex | FileCheck %s +// NOTE: Assertions have been autogenerated by utils/generate-test-checks.py + + +// CHECK-LABEL: dxsa.dcl_global_flags +// CHECK: dxsa.dcl_input_ps linear v<0, > +// CHECK: dxsa.dcl_output o<0, > +// CHECK: dxsa.dcl_temps 1 +// CHECK: dxsa.add r<0, min16f, >, v<0, >, l(0x40A00000) +// CHECK: %[[INDEX_0:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_0:.*]] = dxsa.operand %[[INDEX_0]] {mask = 16 : i32, num_components = 4 : i32, type = 2 : i32} +// CHECK: %[[INDEX_1:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_1:.*]] = dxsa.operand %[[INDEX_1]] {min_precision = 1 : i32, num_components = 4 : i32, one = 0 : i32, type = 0 : i32} +// CHECK: dxsa.instruction "mov" %[[OPERAND_0]], %[[OPERAND_1]] +// CHECK: dxsa.instruction "ret" + diff --git a/mlir/test/Target/DXSA/hlsl/neg1.test b/mlir/test/Target/DXSA/hlsl/neg1.test new file mode 100644 index 000000000000..e9c28ce57c10 --- /dev/null +++ b/mlir/test/Target/DXSA/hlsl/neg1.test @@ -0,0 +1,14 @@ +// RUN: mlir-translate --import-dxsa-bin %S/inputs/neg1.shex | FileCheck %s +// NOTE: Assertions have been autogenerated by utils/generate-test-checks.py + + +// CHECK-LABEL: dxsa.dcl_global_flags +// CHECK: dxsa.dcl_input_ps linear v<0, > +// CHECK: dxsa.dcl_output o<0> +// CHECK: %[[INDEX_0:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_0:.*]] = dxsa.operand %[[INDEX_0]] {mask = 240 : i32, num_components = 4 : i32, type = 2 : i32} +// CHECK: %[[INDEX_1:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_1:.*]] = dxsa.operand %[[INDEX_1]] {modifier = 1 : i32, num_components = 4 : i32, swizzle = dense<[1, 0, 0, 0]> : vector<4xi32>, type = 1 : i32} +// CHECK: dxsa.instruction "mov" %[[OPERAND_0]], %[[OPERAND_1]] +// CHECK: dxsa.instruction "ret" + diff --git a/mlir/test/Target/DXSA/hlsl/neg2.test b/mlir/test/Target/DXSA/hlsl/neg2.test new file mode 100644 index 000000000000..465b9f79c789 --- /dev/null +++ b/mlir/test/Target/DXSA/hlsl/neg2.test @@ -0,0 +1,14 @@ +// RUN: mlir-translate --import-dxsa-bin %S/inputs/neg2.shex | FileCheck %s +// NOTE: Assertions have been autogenerated by utils/generate-test-checks.py + + +// CHECK-LABEL: dxsa.dcl_global_flags +// CHECK: dxsa.dcl_input_ps constant v<0, > +// CHECK: dxsa.dcl_output o<0> +// CHECK: %[[INDEX_0:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_0:.*]] = dxsa.operand %[[INDEX_0]] {mask = 240 : i32, num_components = 4 : i32, type = 2 : i32} +// CHECK: %[[INDEX_1:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_1:.*]] = dxsa.operand %[[INDEX_1]] {num_components = 4 : i32, swizzle = dense<[1, 0, 0, 0]> : vector<4xi32>, type = 1 : i32} +// CHECK: dxsa.instruction "ineg" %[[OPERAND_0]], %[[OPERAND_1]] +// CHECK: dxsa.instruction "ret" + diff --git a/mlir/test/Target/DXSA/hlsl/negabs1.test b/mlir/test/Target/DXSA/hlsl/negabs1.test new file mode 100644 index 000000000000..ae9d5e8dc355 --- /dev/null +++ b/mlir/test/Target/DXSA/hlsl/negabs1.test @@ -0,0 +1,14 @@ +// RUN: mlir-translate --import-dxsa-bin %S/inputs/negabs1.shex | FileCheck %s +// NOTE: Assertions have been autogenerated by utils/generate-test-checks.py + + +// CHECK-LABEL: dxsa.dcl_global_flags +// CHECK: dxsa.dcl_input_ps linear v<0, > +// CHECK: dxsa.dcl_output o<0> +// CHECK: %[[INDEX_0:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_0:.*]] = dxsa.operand %[[INDEX_0]] {mask = 240 : i32, num_components = 4 : i32, type = 2 : i32} +// CHECK: %[[INDEX_1:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_1:.*]] = dxsa.operand %[[INDEX_1]] {modifier = 3 : i32, num_components = 4 : i32, swizzle = dense<[1, 0, 0, 0]> : vector<4xi32>, type = 1 : i32} +// CHECK: dxsa.instruction "mov" %[[OPERAND_0]], %[[OPERAND_1]] +// CHECK: dxsa.instruction "ret" + diff --git a/mlir/test/Target/DXSA/hlsl/nonuniform1.test b/mlir/test/Target/DXSA/hlsl/nonuniform1.test new file mode 100644 index 000000000000..ba2bdda8c5ba --- /dev/null +++ b/mlir/test/Target/DXSA/hlsl/nonuniform1.test @@ -0,0 +1,52 @@ +// RUN: mlir-translate --import-dxsa-bin %S/inputs/nonuniform1.shex | FileCheck %s +// NOTE: Assertions have been autogenerated by utils/generate-test-checks.py + + +// CHECK-LABEL: dxsa.dcl_global_flags +// CHECK: dxsa.dcl_sampler +// CHECK: dxsa.dcl_resource , , +// CHECK: dxsa.dcl_input_ps constant v<0, > +// CHECK: dxsa.dcl_input_ps linear v<1, > +// CHECK: dxsa.dcl_output o<0> +// CHECK: dxsa.dcl_temps 2 +// CHECK: dxsa.itof r<0, >, v<0, > +// CHECK: %[[INDEX_0:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_0:.*]] = dxsa.operand %[[INDEX_0]] {mask = 32 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_1:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_1:.*]] = dxsa.operand %[[INDEX_1]] {num_components = 4 : i32, one = 0 : i32, type = 1 : i32} +// CHECK: dxsa.instruction "mov" %[[OPERAND_0]], %[[OPERAND_1]] +// CHECK: %[[INDEX_2:.*]] = dxsa.index.imm {imm = 1 : i32} +// CHECK: %[[OPERAND_2:.*]] = dxsa.operand %[[INDEX_2]] {mask = 240 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_3:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_3:.*]] = dxsa.operand %[[INDEX_3]] {num_components = 4 : i32, swizzle = dense<0> : vector<4xi32>, type = 0 : i32} +// CHECK: %[[INDEX_4:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[INDEX_5:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_4:.*]] = dxsa.operand %[[INDEX_5]] {num_components = 4 : i32, one = 1 : i32, type = 0 : i32} +// CHECK: %[[INDEX_6:.*]] = dxsa.index.rel.imm %[[OPERAND_4]] {imm = 3 : i32, op = "add"} +// CHECK: %[[OPERAND_5:.*]] = dxsa.operand %[[INDEX_4]], %[[INDEX_6]] {non_uniform = 1 : i32, num_components = 4 : i32, swizzle = dense<[0, 1, 2, 3]> : vector<4xi32>, type = 7 : i32} +// CHECK: %[[INDEX_7:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[INDEX_8:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_6:.*]] = dxsa.operand %[[INDEX_8]] {num_components = 4 : i32, one = 1 : i32, type = 0 : i32} +// CHECK: %[[INDEX_9:.*]] = dxsa.index.rel.imm %[[OPERAND_6]] {imm = 2 : i32, op = "add"} +// CHECK: %[[OPERAND_7:.*]] = dxsa.operand %[[INDEX_7]], %[[INDEX_9]] {non_uniform = 1 : i32, num_components = 0 : i32, type = 6 : i32} +// CHECK: dxsa.instruction "sample" %[[OPERAND_2]], %[[OPERAND_3]], %[[OPERAND_5]], %[[OPERAND_7]] +// CHECK: dxsa.ftou r<0, >, v<1, > +// CHECK: dxsa.add r<0, >, v<1, >, l(0x40000000) +// CHECK: %[[INDEX_10:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_8:.*]] = dxsa.operand %[[INDEX_10]] {mask = 240 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_11:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_9:.*]] = dxsa.operand %[[INDEX_11]] {num_components = 4 : i32, swizzle = dense<2> : vector<4xi32>, type = 0 : i32} +// CHECK: %[[INDEX_12:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[INDEX_13:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_10:.*]] = dxsa.operand %[[INDEX_13]] {num_components = 4 : i32, one = 0 : i32, type = 0 : i32} +// CHECK: %[[INDEX_14:.*]] = dxsa.index.rel.imm %[[OPERAND_10]] {imm = 3 : i32, op = "add"} +// CHECK: %[[OPERAND_11:.*]] = dxsa.operand %[[INDEX_12]], %[[INDEX_14]] {non_uniform = 1 : i32, num_components = 4 : i32, swizzle = dense<[0, 1, 2, 3]> : vector<4xi32>, type = 7 : i32} +// CHECK: %[[INDEX_15:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[INDEX_16:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_12:.*]] = dxsa.operand %[[INDEX_16]] {num_components = 4 : i32, one = 1 : i32, type = 0 : i32} +// CHECK: %[[INDEX_17:.*]] = dxsa.index.rel.imm %[[OPERAND_12]] {imm = 2 : i32, op = "add"} +// CHECK: %[[OPERAND_13:.*]] = dxsa.operand %[[INDEX_15]], %[[INDEX_17]] {num_components = 0 : i32, type = 6 : i32} +// CHECK: dxsa.instruction "sample" %[[OPERAND_8]], %[[OPERAND_9]], %[[OPERAND_11]], %[[OPERAND_13]] +// CHECK: dxsa.add o<0>, r<0>, r<1> +// CHECK: dxsa.instruction "ret" + diff --git a/mlir/test/Target/DXSA/hlsl/output1.test b/mlir/test/Target/DXSA/hlsl/output1.test new file mode 100644 index 000000000000..dcc754fd2961 --- /dev/null +++ b/mlir/test/Target/DXSA/hlsl/output1.test @@ -0,0 +1,32 @@ +// RUN: mlir-translate --import-dxsa-bin %S/inputs/output1.shex | FileCheck %s +// NOTE: Assertions have been autogenerated by utils/generate-test-checks.py + + +// CHECK-LABEL: dxsa.dcl_global_flags +// CHECK: dxsa.dcl_input_ps linear v<0> +// CHECK: dxsa.dcl_input_ps_sgv v<1, >, +// CHECK: dxsa.dcl_input_ps_sgv v<1, >, +// CHECK: dxsa.dcl_output o<0> +// CHECK: dxsa.dcl_output o<5> +// CHECK: dxsa.dcl_output oDepth +// CHECK: dxsa.dcl_temps 2 +// CHECK: dxsa.utof r<0, >, v<1, > +// CHECK: dxsa.add r<0>, r<0, >, v<0> +// CHECK: dxsa.and r<1, >, v<1, >, l(0x3F800000) +// CHECK: dxsa.add r<0>, r<0>, r<1, > +// CHECK: %[[OPERAND_0:.*]] = dxsa.operand {num_components = 1 : i32, type = 12 : i32} +// CHECK: %[[INDEX_0:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_1:.*]] = dxsa.operand %[[INDEX_0]] {num_components = 4 : i32, one = 0 : i32, type = 0 : i32} +// CHECK: dxsa.instruction "mov" %[[OPERAND_0]], %[[OPERAND_1]] +// CHECK: %[[INDEX_1:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_2:.*]] = dxsa.operand %[[INDEX_1]] {mask = 240 : i32, num_components = 4 : i32, type = 2 : i32} +// CHECK: %[[INDEX_2:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_3:.*]] = dxsa.operand %[[INDEX_2]] {num_components = 4 : i32, swizzle = dense<[0, 1, 2, 3]> : vector<4xi32>, type = 0 : i32} +// CHECK: dxsa.instruction "mov" %[[OPERAND_2]], %[[OPERAND_3]] +// CHECK: %[[INDEX_3:.*]] = dxsa.index.imm {imm = 5 : i32} +// CHECK: %[[OPERAND_4:.*]] = dxsa.operand %[[INDEX_3]] {mask = 240 : i32, num_components = 4 : i32, type = 2 : i32} +// CHECK: %[[INDEX_4:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_5:.*]] = dxsa.operand %[[INDEX_4]] {num_components = 4 : i32, swizzle = dense<[0, 1, 2, 3]> : vector<4xi32>, type = 0 : i32} +// CHECK: dxsa.instruction "mov" %[[OPERAND_4]], %[[OPERAND_5]] +// CHECK: dxsa.instruction "ret" + diff --git a/mlir/test/Target/DXSA/hlsl/output2.test b/mlir/test/Target/DXSA/hlsl/output2.test new file mode 100644 index 000000000000..6c7a856d1f08 --- /dev/null +++ b/mlir/test/Target/DXSA/hlsl/output2.test @@ -0,0 +1,28 @@ +// RUN: mlir-translate --import-dxsa-bin %S/inputs/output2.shex | FileCheck %s +// NOTE: Assertions have been autogenerated by utils/generate-test-checks.py + + +// CHECK-LABEL: dxsa.dcl_global_flags +// CHECK: dxsa.dcl_input_ps linear v<0> +// CHECK: dxsa.dcl_input_ps linear v<1> +// CHECK: dxsa.dcl_output o<0> +// CHECK: dxsa.dcl_output o<5> +// CHECK: dxsa.dcl_output oDepthGE +// CHECK: dxsa.dcl_temps 1 +// CHECK: dxsa.add r<0>, v<0>, v<1> +// CHECK: %[[OPERAND_0:.*]] = dxsa.operand {num_components = 1 : i32, type = 38 : i32} +// CHECK: %[[INDEX_0:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_1:.*]] = dxsa.operand %[[INDEX_0]] {num_components = 4 : i32, one = 0 : i32, type = 0 : i32} +// CHECK: dxsa.instruction "mov" %[[OPERAND_0]], %[[OPERAND_1]] +// CHECK: %[[INDEX_1:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_2:.*]] = dxsa.operand %[[INDEX_1]] {mask = 240 : i32, num_components = 4 : i32, type = 2 : i32} +// CHECK: %[[INDEX_2:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_3:.*]] = dxsa.operand %[[INDEX_2]] {num_components = 4 : i32, swizzle = dense<[0, 1, 2, 3]> : vector<4xi32>, type = 0 : i32} +// CHECK: dxsa.instruction "mov" %[[OPERAND_2]], %[[OPERAND_3]] +// CHECK: %[[INDEX_3:.*]] = dxsa.index.imm {imm = 5 : i32} +// CHECK: %[[OPERAND_4:.*]] = dxsa.operand %[[INDEX_3]] {mask = 240 : i32, num_components = 4 : i32, type = 2 : i32} +// CHECK: %[[INDEX_4:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_5:.*]] = dxsa.operand %[[INDEX_4]] {num_components = 4 : i32, swizzle = dense<[0, 1, 2, 3]> : vector<4xi32>, type = 0 : i32} +// CHECK: dxsa.instruction "mov" %[[OPERAND_4]], %[[OPERAND_5]] +// CHECK: dxsa.instruction "ret" + diff --git a/mlir/test/Target/DXSA/hlsl/output3.test b/mlir/test/Target/DXSA/hlsl/output3.test new file mode 100644 index 000000000000..a71375e9dc27 --- /dev/null +++ b/mlir/test/Target/DXSA/hlsl/output3.test @@ -0,0 +1,27 @@ +// RUN: mlir-translate --import-dxsa-bin %S/inputs/output3.shex | FileCheck %s +// NOTE: Assertions have been autogenerated by utils/generate-test-checks.py + + +// CHECK-LABEL: dxsa.dcl_global_flags +// CHECK: dxsa.dcl_input_ps linear v<0> +// CHECK: dxsa.dcl_output o<0> +// CHECK: dxsa.dcl_output o<5> +// CHECK: dxsa.dcl_output oDepthLE +// CHECK: dxsa.dcl_output oStencilRef +// CHECK: %[[OPERAND_0:.*]] = dxsa.operand {num_components = 1 : i32, type = 39 : i32} +// CHECK: %[[INDEX_0:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_1:.*]] = dxsa.operand %[[INDEX_0]] {num_components = 4 : i32, one = 0 : i32, type = 1 : i32} +// CHECK: dxsa.instruction "mov" %[[OPERAND_0]], %[[OPERAND_1]] +// CHECK: dxsa.ftou oStencilRef, v<0, > +// CHECK: %[[INDEX_1:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_2:.*]] = dxsa.operand %[[INDEX_1]] {mask = 240 : i32, num_components = 4 : i32, type = 2 : i32} +// CHECK: %[[INDEX_2:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_3:.*]] = dxsa.operand %[[INDEX_2]] {num_components = 4 : i32, swizzle = dense<[0, 1, 2, 3]> : vector<4xi32>, type = 1 : i32} +// CHECK: dxsa.instruction "mov" %[[OPERAND_2]], %[[OPERAND_3]] +// CHECK: %[[INDEX_3:.*]] = dxsa.index.imm {imm = 5 : i32} +// CHECK: %[[OPERAND_4:.*]] = dxsa.operand %[[INDEX_3]] {mask = 240 : i32, num_components = 4 : i32, type = 2 : i32} +// CHECK: %[[INDEX_4:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_5:.*]] = dxsa.operand %[[INDEX_4]] {num_components = 4 : i32, swizzle = dense<[0, 1, 2, 3]> : vector<4xi32>, type = 1 : i32} +// CHECK: dxsa.instruction "mov" %[[OPERAND_4]], %[[OPERAND_5]] +// CHECK: dxsa.instruction "ret" + diff --git a/mlir/test/Target/DXSA/hlsl/output4.test b/mlir/test/Target/DXSA/hlsl/output4.test new file mode 100644 index 000000000000..d8cf1d10df69 --- /dev/null +++ b/mlir/test/Target/DXSA/hlsl/output4.test @@ -0,0 +1,32 @@ +// RUN: mlir-translate --import-dxsa-bin %S/inputs/output4.shex | FileCheck %s +// NOTE: Assertions have been autogenerated by utils/generate-test-checks.py + + +// CHECK-LABEL: dxsa.dcl_global_flags +// CHECK: dxsa.dcl_input v<0> +// CHECK: dxsa.dcl_output_siv o<0>, +// CHECK: dxsa.dcl_output_siv o<1, min16f, >, +// CHECK: dxsa.dcl_output_siv o<1, >, +// CHECK: dxsa.dcl_output_siv o<2, min16f, >, +// CHECK: %[[INDEX_0:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_0:.*]] = dxsa.operand %[[INDEX_0]] {mask = 240 : i32, num_components = 4 : i32, type = 2 : i32} +// CHECK: %[[INDEX_1:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_1:.*]] = dxsa.operand %[[INDEX_1]] {num_components = 4 : i32, swizzle = dense<[0, 1, 2, 3]> : vector<4xi32>, type = 1 : i32} +// CHECK: dxsa.instruction "mov" %[[OPERAND_0]], %[[OPERAND_1]] +// CHECK: %[[INDEX_2:.*]] = dxsa.index.imm {imm = 1 : i32} +// CHECK: %[[OPERAND_2:.*]] = dxsa.operand %[[INDEX_2]] {mask = 16 : i32, min_precision = 1 : i32, num_components = 4 : i32, type = 2 : i32} +// CHECK: %[[INDEX_3:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_3:.*]] = dxsa.operand %[[INDEX_3]] {num_components = 4 : i32, one = 0 : i32, type = 1 : i32} +// CHECK: dxsa.instruction "mov" %[[OPERAND_2]], %[[OPERAND_3]] +// CHECK: %[[INDEX_4:.*]] = dxsa.index.imm {imm = 1 : i32} +// CHECK: %[[OPERAND_4:.*]] = dxsa.operand %[[INDEX_4]] {mask = 96 : i32, num_components = 4 : i32, type = 2 : i32} +// CHECK: %[[INDEX_5:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_5:.*]] = dxsa.operand %[[INDEX_5]] {num_components = 4 : i32, swizzle = dense<[0, 0, 3, 0]> : vector<4xi32>, type = 1 : i32} +// CHECK: dxsa.instruction "mov" %[[OPERAND_4]], %[[OPERAND_5]] +// CHECK: %[[INDEX_6:.*]] = dxsa.index.imm {imm = 2 : i32} +// CHECK: %[[OPERAND_6:.*]] = dxsa.operand %[[INDEX_6]] {mask = 48 : i32, min_precision = 1 : i32, num_components = 4 : i32, type = 2 : i32} +// CHECK: %[[INDEX_7:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_7:.*]] = dxsa.operand %[[INDEX_7]] {num_components = 4 : i32, swizzle = dense<[1, 2, 1, 1]> : vector<4xi32>, type = 1 : i32} +// CHECK: dxsa.instruction "mov" %[[OPERAND_6]], %[[OPERAND_7]] +// CHECK: dxsa.instruction "ret" + diff --git a/mlir/test/Target/DXSA/hlsl/passthrough1.test b/mlir/test/Target/DXSA/hlsl/passthrough1.test new file mode 100644 index 000000000000..b388f28d3eef --- /dev/null +++ b/mlir/test/Target/DXSA/hlsl/passthrough1.test @@ -0,0 +1,14 @@ +// RUN: mlir-translate --import-dxsa-bin %S/inputs/passthrough1.shex | FileCheck %s +// NOTE: Assertions have been autogenerated by utils/generate-test-checks.py + + +// CHECK-LABEL: dxsa.dcl_global_flags +// CHECK: dxsa.dcl_input v<0> +// CHECK: dxsa.dcl_output_siv o<0>, +// CHECK: %[[INDEX_0:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_0:.*]] = dxsa.operand %[[INDEX_0]] {mask = 240 : i32, num_components = 4 : i32, type = 2 : i32} +// CHECK: %[[INDEX_1:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_1:.*]] = dxsa.operand %[[INDEX_1]] {num_components = 4 : i32, swizzle = dense<[0, 1, 2, 3]> : vector<4xi32>, type = 1 : i32} +// CHECK: dxsa.instruction "mov" %[[OPERAND_0]], %[[OPERAND_1]] +// CHECK: dxsa.instruction "ret" + diff --git a/mlir/test/Target/DXSA/hlsl/passthrough2.test b/mlir/test/Target/DXSA/hlsl/passthrough2.test new file mode 100644 index 000000000000..7645d86e88a7 --- /dev/null +++ b/mlir/test/Target/DXSA/hlsl/passthrough2.test @@ -0,0 +1,14 @@ +// RUN: mlir-translate --import-dxsa-bin %S/inputs/passthrough2.shex | FileCheck %s +// NOTE: Assertions have been autogenerated by utils/generate-test-checks.py + + +// CHECK-LABEL: dxsa.dcl_global_flags +// CHECK: dxsa.dcl_input_ps linear v<0, > +// CHECK: dxsa.dcl_output o<0> +// CHECK: %[[INDEX_0:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_0:.*]] = dxsa.operand %[[INDEX_0]] {mask = 240 : i32, num_components = 4 : i32, type = 2 : i32} +// CHECK: %[[INDEX_1:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_1:.*]] = dxsa.operand %[[INDEX_1]] {num_components = 4 : i32, swizzle = dense<[0, 0, 0, 1]> : vector<4xi32>, type = 1 : i32} +// CHECK: dxsa.instruction "mov" %[[OPERAND_0]], %[[OPERAND_1]] +// CHECK: dxsa.instruction "ret" + diff --git a/mlir/test/Target/DXSA/hlsl/precise1.test b/mlir/test/Target/DXSA/hlsl/precise1.test new file mode 100644 index 000000000000..97ad1d4cf980 --- /dev/null +++ b/mlir/test/Target/DXSA/hlsl/precise1.test @@ -0,0 +1,21 @@ +// RUN: mlir-translate --import-dxsa-bin %S/inputs/precise1.shex | FileCheck %s +// NOTE: Assertions have been autogenerated by utils/generate-test-checks.py + + +// CHECK-LABEL: dxsa.dcl_global_flags +// CHECK: dxsa.dcl_constant_buffer , +// CHECK: dxsa.dcl_sampler +// CHECK: dxsa.dcl_resource , , +// CHECK: dxsa.dcl_input_ps linear v<0, > +// CHECK: dxsa.dcl_output o<0> +// CHECK: dxsa.dcl_temps 1 +// CHECK: dxsa.unknown +// CHECK: dxsa.mul precise r<0>, r<0>, cb<[0, 0], vector> +// CHECK: dxsa.mad precise r<0>, r<0>, cb<[0, 1], vector>, cb<[0, 2], vector> +// CHECK: %[[INDEX_0:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_0:.*]] = dxsa.operand %[[INDEX_0]] {mask = 240 : i32, num_components = 4 : i32, type = 2 : i32} +// CHECK: %[[INDEX_1:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_1:.*]] = dxsa.operand %[[INDEX_1]] {modifier = 1 : i32, num_components = 4 : i32, swizzle = dense<[0, 1, 2, 3]> : vector<4xi32>, type = 0 : i32} +// CHECK: dxsa.instruction "mov" %[[OPERAND_0]], %[[OPERAND_1]] +// CHECK: dxsa.instruction "ret" + diff --git a/mlir/test/Target/DXSA/hlsl/raw_buf1.test b/mlir/test/Target/DXSA/hlsl/raw_buf1.test new file mode 100644 index 000000000000..7cc2bb1bcf0e --- /dev/null +++ b/mlir/test/Target/DXSA/hlsl/raw_buf1.test @@ -0,0 +1,154 @@ +// RUN: mlir-translate --import-dxsa-bin %S/inputs/raw_buf1.shex | FileCheck %s +// NOTE: Assertions have been autogenerated by utils/generate-test-checks.py + + +// CHECK-LABEL: dxsa.dcl_global_flags +// CHECK: dxsa.dcl_resource_raw +// CHECK: dxsa.dcl_uav_raw +// CHECK: dxsa.dcl_input_ps linear v<0, > +// CHECK: dxsa.dcl_input_ps linear v<0, > +// CHECK: dxsa.dcl_output o<0> +// CHECK: dxsa.dcl_temps 16 +// CHECK: dxsa.ftou r<0, >, v<0, > +// CHECK: dxsa.unknown +// CHECK: dxsa.add r<1, >, v<0, >, l(0x3F800000, 0x40000000, 0x40400000, 0x0) +// CHECK: dxsa.ftou r<1, >, r<1, > +// CHECK: dxsa.unknown +// CHECK: dxsa.unknown +// CHECK: dxsa.utof r<3, >, r<3, > +// CHECK: dxsa.unknown +// CHECK: dxsa.utof r<4>, r<4> +// CHECK: dxsa.unknown +// CHECK: dxsa.unknown +// CHECK: dxsa.unknown +// CHECK: dxsa.unknown +// CHECK: dxsa.unknown +// CHECK: dxsa.utof r<13, min16f, >, r<0, > +// CHECK: dxsa.unknown +// CHECK: dxsa.utof r<2>, r<2> +// CHECK: dxsa.add r<2, >, r<2, >, r<13, min16f, > +// CHECK: dxsa.unknown +// CHECK: dxsa.utof r<5, >, r<5, > +// CHECK: dxsa.add r<14, >, r<2, >, r<5, > +// CHECK: dxsa.add r<14, >, r<5, >, r<13, min16f, > +// CHECK: dxsa.unknown +// CHECK: dxsa.utof r<15>, r<15> +// CHECK: dxsa.add r<14, >, r<14, >, r<15, > +// CHECK: dxsa.add r<14, >, r<13, min16f, >, r<15, > +// CHECK: dxsa.unknown +// CHECK: %[[INDEX_0:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_0:.*]] = dxsa.operand %[[INDEX_0]] {mask = 128 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_1:.*]] = dxsa.index.imm {imm = 15 : i32} +// CHECK: %[[OPERAND_1:.*]] = dxsa.operand %[[INDEX_1]] {num_components = 4 : i32, one = 0 : i32, type = 0 : i32} +// CHECK: dxsa.instruction "check_access_fully_mapped" %[[OPERAND_0]], %[[OPERAND_1]] +// CHECK: dxsa.utof r<0, >, r<0, > +// CHECK: dxsa.add r<13>, r<0, >, r<14> +// CHECK: dxsa.add r<13>, r<0, >, r<13> +// CHECK: dxsa.unknown +// CHECK: %[[INDEX_2:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_2:.*]] = dxsa.operand %[[INDEX_2]] {mask = 128 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_3:.*]] = dxsa.index.imm {imm = 1 : i32} +// CHECK: %[[OPERAND_3:.*]] = dxsa.operand %[[INDEX_3]] {num_components = 4 : i32, one = 0 : i32, type = 0 : i32} +// CHECK: dxsa.instruction "check_access_fully_mapped" %[[OPERAND_2]], %[[OPERAND_3]] +// CHECK: dxsa.utof r<0, >, r<0, > +// CHECK: dxsa.add r<13, >, r<0, >, r<13, > +// CHECK: dxsa.add r<13>, r<0, >, r<13> +// CHECK: dxsa.unknown +// CHECK: dxsa.unknown +// CHECK: %[[INDEX_4:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_4:.*]] = dxsa.operand %[[INDEX_4]] {mask = 128 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_5:.*]] = dxsa.index.imm {imm = 1 : i32} +// CHECK: %[[OPERAND_5:.*]] = dxsa.operand %[[INDEX_5]] {num_components = 4 : i32, one = 0 : i32, type = 0 : i32} +// CHECK: dxsa.instruction "check_access_fully_mapped" %[[OPERAND_4]], %[[OPERAND_5]] +// CHECK: dxsa.utof r<0, >, r<0, > +// CHECK: dxsa.add r<13, >, r<0, >, r<13, > +// CHECK: dxsa.add r<1>, r<0, >, r<13> +// CHECK: dxsa.utof r<0, >, r<14, > +// CHECK: %[[INDEX_6:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_6:.*]] = dxsa.operand %[[INDEX_6]] {mask = 128 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_7:.*]] = dxsa.index.imm {imm = 15 : i32} +// CHECK: %[[OPERAND_7:.*]] = dxsa.operand %[[INDEX_7]] {num_components = 4 : i32, one = 0 : i32, type = 0 : i32} +// CHECK: dxsa.instruction "check_access_fully_mapped" %[[OPERAND_6]], %[[OPERAND_7]] +// CHECK: dxsa.utof r<0, >, r<0, > +// CHECK: dxsa.add r<1>, r<0, >, r<1> +// CHECK: dxsa.add r<1>, r<0, >, r<1> +// CHECK: dxsa.add r<1>, r<0, >, r<1> +// CHECK: dxsa.add r<1, >, r<2, >, r<1, > +// CHECK: dxsa.add r<1, >, r<3, >, r<1, > +// CHECK: dxsa.add r<1>, r<4>, r<1> +// CHECK: dxsa.utof r<0, >, r<5, > +// CHECK: %[[INDEX_8:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_8:.*]] = dxsa.operand %[[INDEX_8]] {mask = 64 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_9:.*]] = dxsa.index.imm {imm = 6 : i32} +// CHECK: %[[OPERAND_9:.*]] = dxsa.operand %[[INDEX_9]] {num_components = 4 : i32, one = 0 : i32, type = 0 : i32} +// CHECK: dxsa.instruction "check_access_fully_mapped" %[[OPERAND_8]], %[[OPERAND_9]] +// CHECK: dxsa.utof r<0, >, r<0, > +// CHECK: dxsa.add r<1>, r<0, >, r<1> +// CHECK: dxsa.add r<1>, r<0, >, r<1> +// CHECK: dxsa.utof r<0, >, r<7, > +// CHECK: %[[INDEX_10:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_10:.*]] = dxsa.operand %[[INDEX_10]] {mask = 64 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_11:.*]] = dxsa.index.imm {imm = 8 : i32} +// CHECK: %[[OPERAND_11:.*]] = dxsa.operand %[[INDEX_11]] {num_components = 4 : i32, one = 0 : i32, type = 0 : i32} +// CHECK: dxsa.instruction "check_access_fully_mapped" %[[OPERAND_10]], %[[OPERAND_11]] +// CHECK: dxsa.utof r<0, >, r<0, > +// CHECK: dxsa.add r<1, >, r<0, >, r<1, > +// CHECK: dxsa.add r<1>, r<0, >, r<1> +// CHECK: dxsa.utof r<0, >, r<9, > +// CHECK: %[[INDEX_12:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_12:.*]] = dxsa.operand %[[INDEX_12]] {mask = 64 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_13:.*]] = dxsa.index.imm {imm = 10 : i32} +// CHECK: %[[OPERAND_13:.*]] = dxsa.operand %[[INDEX_13]] {num_components = 4 : i32, one = 0 : i32, type = 0 : i32} +// CHECK: dxsa.instruction "check_access_fully_mapped" %[[OPERAND_12]], %[[OPERAND_13]] +// CHECK: dxsa.utof r<0, >, r<0, > +// CHECK: dxsa.add r<1, >, r<0, >, r<1, > +// CHECK: dxsa.add r<1>, r<0, >, r<1> +// CHECK: dxsa.utof r<0, >, r<11, > +// CHECK: %[[INDEX_14:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_14:.*]] = dxsa.operand %[[INDEX_14]] {mask = 64 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_15:.*]] = dxsa.index.imm {imm = 12 : i32} +// CHECK: %[[OPERAND_15:.*]] = dxsa.operand %[[INDEX_15]] {num_components = 4 : i32, one = 0 : i32, type = 0 : i32} +// CHECK: dxsa.instruction "check_access_fully_mapped" %[[OPERAND_14]], %[[OPERAND_15]] +// CHECK: dxsa.utof r<0, >, r<0, > +// CHECK: dxsa.add r<1>, r<0, >, r<1> +// CHECK: dxsa.add r<1>, r<0, >, r<1> +// CHECK: dxsa.ftou r<0, >, r<1, > +// CHECK: %[[INDEX_16:.*]] = dxsa.index.imm {imm = 1 : i32} +// CHECK: %[[OPERAND_16:.*]] = dxsa.operand %[[INDEX_16]] {mask = 16 : i32, num_components = 4 : i32, type = 30 : i32} +// CHECK: %[[INDEX_17:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_17:.*]] = dxsa.operand %[[INDEX_17]] {num_components = 4 : i32, one = 1 : i32, type = 0 : i32} +// CHECK: %[[INDEX_18:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_18:.*]] = dxsa.operand %[[INDEX_18]] {num_components = 4 : i32, one = 0 : i32, type = 0 : i32} +// CHECK: dxsa.instruction "store_raw" %[[OPERAND_16]], %[[OPERAND_17]], %[[OPERAND_18]] +// CHECK: dxsa.add r<2, >, v<0, >, l(0x3F800000, 0x40000000, 0x40400000, 0x0) +// CHECK: dxsa.ftou r<2, >, r<2, > +// CHECK: %[[INDEX_19:.*]] = dxsa.index.imm {imm = 1 : i32} +// CHECK: %[[OPERAND_19:.*]] = dxsa.operand %[[INDEX_19]] {mask = 48 : i32, num_components = 4 : i32, type = 30 : i32} +// CHECK: %[[INDEX_20:.*]] = dxsa.index.imm {imm = 2 : i32} +// CHECK: %[[OPERAND_20:.*]] = dxsa.operand %[[INDEX_20]] {num_components = 4 : i32, one = 0 : i32, type = 0 : i32} +// CHECK: %[[INDEX_21:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_21:.*]] = dxsa.operand %[[INDEX_21]] {num_components = 4 : i32, swizzle = dense<[2, 3, 2, 2]> : vector<4xi32>, type = 0 : i32} +// CHECK: dxsa.instruction "store_raw" %[[OPERAND_19]], %[[OPERAND_20]], %[[OPERAND_21]] +// CHECK: dxsa.ftou r<0, >, r<1, > +// CHECK: %[[INDEX_22:.*]] = dxsa.index.imm {imm = 1 : i32} +// CHECK: %[[OPERAND_22:.*]] = dxsa.operand %[[INDEX_22]] {mask = 112 : i32, num_components = 4 : i32, type = 30 : i32} +// CHECK: %[[INDEX_23:.*]] = dxsa.index.imm {imm = 2 : i32} +// CHECK: %[[OPERAND_23:.*]] = dxsa.operand %[[INDEX_23]] {num_components = 4 : i32, one = 1 : i32, type = 0 : i32} +// CHECK: %[[INDEX_24:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_24:.*]] = dxsa.operand %[[INDEX_24]] {num_components = 4 : i32, swizzle = dense<[0, 1, 2, 0]> : vector<4xi32>, type = 0 : i32} +// CHECK: dxsa.instruction "store_raw" %[[OPERAND_22]], %[[OPERAND_23]], %[[OPERAND_24]] +// CHECK: dxsa.ftou r<0>, r<1, > +// CHECK: %[[INDEX_25:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_25:.*]] = dxsa.operand %[[INDEX_25]] {mask = 240 : i32, num_components = 4 : i32, type = 2 : i32} +// CHECK: %[[INDEX_26:.*]] = dxsa.index.imm {imm = 1 : i32} +// CHECK: %[[OPERAND_26:.*]] = dxsa.operand %[[INDEX_26]] {num_components = 4 : i32, swizzle = dense<[0, 1, 2, 3]> : vector<4xi32>, type = 0 : i32} +// CHECK: dxsa.instruction "mov" %[[OPERAND_25]], %[[OPERAND_26]] +// CHECK: %[[INDEX_27:.*]] = dxsa.index.imm {imm = 1 : i32} +// CHECK: %[[OPERAND_27:.*]] = dxsa.operand %[[INDEX_27]] {mask = 240 : i32, num_components = 4 : i32, type = 30 : i32} +// CHECK: %[[INDEX_28:.*]] = dxsa.index.imm {imm = 2 : i32} +// CHECK: %[[OPERAND_28:.*]] = dxsa.operand %[[INDEX_28]] {num_components = 4 : i32, one = 2 : i32, type = 0 : i32} +// CHECK: %[[INDEX_29:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_29:.*]] = dxsa.operand %[[INDEX_29]] {num_components = 4 : i32, swizzle = dense<[0, 1, 2, 3]> : vector<4xi32>, type = 0 : i32} +// CHECK: dxsa.instruction "store_raw" %[[OPERAND_27]], %[[OPERAND_28]], %[[OPERAND_29]] +// CHECK: dxsa.instruction "ret" + diff --git a/mlir/test/Target/DXSA/hlsl/rcp1.test b/mlir/test/Target/DXSA/hlsl/rcp1.test new file mode 100644 index 000000000000..c4e3b8e835c4 --- /dev/null +++ b/mlir/test/Target/DXSA/hlsl/rcp1.test @@ -0,0 +1,10 @@ +// RUN: mlir-translate --import-dxsa-bin %S/inputs/rcp1.shex | FileCheck %s +// NOTE: Assertions have been autogenerated by utils/generate-test-checks.py + + +// CHECK-LABEL: dxsa.dcl_global_flags +// CHECK: dxsa.dcl_input_ps linear v<0, > +// CHECK: dxsa.dcl_output o<0, > +// CHECK: dxsa.rcp o<0, >, v<0, > +// CHECK: dxsa.instruction "ret" + diff --git a/mlir/test/Target/DXSA/hlsl/redundantinput1.test b/mlir/test/Target/DXSA/hlsl/redundantinput1.test new file mode 100644 index 000000000000..1ac5b2116773 --- /dev/null +++ b/mlir/test/Target/DXSA/hlsl/redundantinput1.test @@ -0,0 +1,10 @@ +// RUN: mlir-translate --import-dxsa-bin %S/inputs/redundantinput1.shex | FileCheck %s +// NOTE: Assertions have been autogenerated by utils/generate-test-checks.py + + +// CHECK-LABEL: dxsa.dcl_global_flags +// CHECK: dxsa.dcl_input_ps linear v<0> +// CHECK: dxsa.dcl_output o<0> +// CHECK: dxsa.add o<0>, |v<0>|, v<0> +// CHECK: dxsa.instruction "ret" + diff --git a/mlir/test/Target/DXSA/hlsl/sample1.test b/mlir/test/Target/DXSA/hlsl/sample1.test new file mode 100644 index 000000000000..f07edf4f3f76 --- /dev/null +++ b/mlir/test/Target/DXSA/hlsl/sample1.test @@ -0,0 +1,15 @@ +// RUN: mlir-translate --import-dxsa-bin %S/inputs/sample1.shex | FileCheck %s +// NOTE: Assertions have been autogenerated by utils/generate-test-checks.py + + +// CHECK-LABEL: dxsa.dcl_global_flags +// CHECK: dxsa.dcl_constant_buffer , +// CHECK: dxsa.dcl_sampler +// CHECK: dxsa.dcl_resource , , +// CHECK: dxsa.dcl_input_ps linear v<0, > +// CHECK: dxsa.dcl_output o<0> +// CHECK: dxsa.dcl_temps 1 +// CHECK: dxsa.unknown +// CHECK: dxsa.add o<0>, r<0>, cb<[0, 2], vector> +// CHECK: dxsa.instruction "ret" + diff --git a/mlir/test/Target/DXSA/hlsl/sample2.test b/mlir/test/Target/DXSA/hlsl/sample2.test new file mode 100644 index 000000000000..92171a975b22 --- /dev/null +++ b/mlir/test/Target/DXSA/hlsl/sample2.test @@ -0,0 +1,15 @@ +// RUN: mlir-translate --import-dxsa-bin %S/inputs/sample2.shex | FileCheck %s +// NOTE: Assertions have been autogenerated by utils/generate-test-checks.py + + +// CHECK-LABEL: dxsa.dcl_global_flags +// CHECK: dxsa.dcl_constant_buffer , +// CHECK: dxsa.dcl_sampler +// CHECK: dxsa.dcl_resource , , +// CHECK: dxsa.dcl_input_ps linear v<0, > +// CHECK: dxsa.dcl_output o<0, > +// CHECK: dxsa.dcl_temps 1 +// CHECK: dxsa.unknown +// CHECK: dxsa.add o<0, >, r<0, >, cb<[0, 2], vector, > +// CHECK: dxsa.instruction "ret" + diff --git a/mlir/test/Target/DXSA/hlsl/sample3.test b/mlir/test/Target/DXSA/hlsl/sample3.test new file mode 100644 index 000000000000..82d77bd469ea --- /dev/null +++ b/mlir/test/Target/DXSA/hlsl/sample3.test @@ -0,0 +1,35 @@ +// RUN: mlir-translate --import-dxsa-bin %S/inputs/sample3.shex | FileCheck %s +// NOTE: Assertions have been autogenerated by utils/generate-test-checks.py + + +// CHECK-LABEL: dxsa.dcl_global_flags +// CHECK: dxsa.dcl_sampler +// CHECK: dxsa.dcl_resource , , +// CHECK: dxsa.dcl_input_ps linear v<0, > +// CHECK: dxsa.dcl_output o<0> +// CHECK: dxsa.dcl_temps 3 +// CHECK: dxsa.unknown +// CHECK: dxsa.unknown +// CHECK: dxsa.add r<0>, r<0>, r<1> +// CHECK: dxsa.unknown +// CHECK: dxsa.add r<0>, r<0>, r<1> +// CHECK: dxsa.unknown +// CHECK: dxsa.add r<0>, r<0>, r<1> +// CHECK: %[[INDEX_0:.*]] = dxsa.index.imm {imm = 1 : i32} +// CHECK: %[[OPERAND_0:.*]] = dxsa.operand %[[INDEX_0]] {mask = 16 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_1:.*]] = dxsa.index.imm {imm = 2 : i32} +// CHECK: %[[OPERAND_1:.*]] = dxsa.operand %[[INDEX_1]] {num_components = 4 : i32, one = 0 : i32, type = 0 : i32} +// CHECK: dxsa.instruction "check_access_fully_mapped" %[[OPERAND_0]], %[[OPERAND_1]] +// CHECK: dxsa.utof r<1, >, r<1, > +// CHECK: dxsa.add r<0>, r<0>, r<1, > +// CHECK: dxsa.unknown +// CHECK: dxsa.add r<0>, r<0>, r<1> +// CHECK: %[[INDEX_2:.*]] = dxsa.index.imm {imm = 1 : i32} +// CHECK: %[[OPERAND_2:.*]] = dxsa.operand %[[INDEX_2]] {mask = 16 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_3:.*]] = dxsa.index.imm {imm = 2 : i32} +// CHECK: %[[OPERAND_3:.*]] = dxsa.operand %[[INDEX_3]] {num_components = 4 : i32, one = 0 : i32, type = 0 : i32} +// CHECK: dxsa.instruction "check_access_fully_mapped" %[[OPERAND_2]], %[[OPERAND_3]] +// CHECK: dxsa.utof r<1, >, r<1, > +// CHECK: dxsa.add o<0>, r<0>, r<1, > +// CHECK: dxsa.instruction "ret" + diff --git a/mlir/test/Target/DXSA/hlsl/sample_b1.test b/mlir/test/Target/DXSA/hlsl/sample_b1.test new file mode 100644 index 000000000000..a077add057f4 --- /dev/null +++ b/mlir/test/Target/DXSA/hlsl/sample_b1.test @@ -0,0 +1,35 @@ +// RUN: mlir-translate --import-dxsa-bin %S/inputs/sample_b1.shex | FileCheck %s +// NOTE: Assertions have been autogenerated by utils/generate-test-checks.py + + +// CHECK-LABEL: dxsa.dcl_global_flags +// CHECK: dxsa.dcl_sampler +// CHECK: dxsa.dcl_resource , , +// CHECK: dxsa.dcl_input_ps linear v<0, > +// CHECK: dxsa.dcl_output o<0> +// CHECK: dxsa.dcl_temps 3 +// CHECK: dxsa.unknown +// CHECK: dxsa.unknown +// CHECK: dxsa.add r<0>, r<0>, r<1> +// CHECK: dxsa.unknown +// CHECK: dxsa.add r<0>, r<0>, r<1> +// CHECK: dxsa.unknown +// CHECK: dxsa.add r<0>, r<0>, r<1> +// CHECK: %[[INDEX_0:.*]] = dxsa.index.imm {imm = 1 : i32} +// CHECK: %[[OPERAND_0:.*]] = dxsa.operand %[[INDEX_0]] {mask = 16 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_1:.*]] = dxsa.index.imm {imm = 2 : i32} +// CHECK: %[[OPERAND_1:.*]] = dxsa.operand %[[INDEX_1]] {num_components = 4 : i32, one = 0 : i32, type = 0 : i32} +// CHECK: dxsa.instruction "check_access_fully_mapped" %[[OPERAND_0]], %[[OPERAND_1]] +// CHECK: dxsa.utof r<1, >, r<1, > +// CHECK: dxsa.add r<0>, r<0>, r<1, > +// CHECK: dxsa.unknown +// CHECK: dxsa.add r<0>, r<0>, r<1> +// CHECK: %[[INDEX_2:.*]] = dxsa.index.imm {imm = 1 : i32} +// CHECK: %[[OPERAND_2:.*]] = dxsa.operand %[[INDEX_2]] {mask = 16 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_3:.*]] = dxsa.index.imm {imm = 2 : i32} +// CHECK: %[[OPERAND_3:.*]] = dxsa.operand %[[INDEX_3]] {num_components = 4 : i32, one = 0 : i32, type = 0 : i32} +// CHECK: dxsa.instruction "check_access_fully_mapped" %[[OPERAND_2]], %[[OPERAND_3]] +// CHECK: dxsa.utof r<1, >, r<1, > +// CHECK: dxsa.add o<0>, r<0>, r<1, > +// CHECK: dxsa.instruction "ret" + diff --git a/mlir/test/Target/DXSA/hlsl/sample_cmp1.test b/mlir/test/Target/DXSA/hlsl/sample_cmp1.test new file mode 100644 index 000000000000..88fac5d4d1e1 --- /dev/null +++ b/mlir/test/Target/DXSA/hlsl/sample_cmp1.test @@ -0,0 +1,38 @@ +// RUN: mlir-translate --import-dxsa-bin %S/inputs/sample_cmp1.shex | FileCheck %s +// NOTE: Assertions have been autogenerated by utils/generate-test-checks.py + + +// CHECK-LABEL: dxsa.dcl_global_flags +// CHECK: dxsa.dcl_sampler +// CHECK: dxsa.dcl_resource , , +// CHECK: dxsa.dcl_input_ps linear v<0, > +// CHECK: dxsa.dcl_output o<0> +// CHECK: dxsa.dcl_temps 4 +// CHECK: dxsa.add r<0, >, v<0, >, v<0, > +// CHECK: dxsa.ftou r<0, >, r<0, > +// CHECK: dxsa.utof r<0, >, r<0, > +// CHECK: dxsa.unknown +// CHECK: dxsa.unknown +// CHECK: dxsa.add r<0, >, r<0, >, r<0, > +// CHECK: dxsa.unknown +// CHECK: dxsa.add r<0, >, r<0, >, r<1, > +// CHECK: dxsa.unknown +// CHECK: dxsa.unknown +// CHECK: dxsa.add r<0, >, r<0, >, r<1, > +// CHECK: %[[INDEX_0:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_0:.*]] = dxsa.operand %[[INDEX_0]] {mask = 64 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_1:.*]] = dxsa.index.imm {imm = 2 : i32} +// CHECK: %[[OPERAND_1:.*]] = dxsa.operand %[[INDEX_1]] {num_components = 4 : i32, one = 0 : i32, type = 0 : i32} +// CHECK: dxsa.instruction "check_access_fully_mapped" %[[OPERAND_0]], %[[OPERAND_1]] +// CHECK: dxsa.utof r<0, >, r<0, > +// CHECK: dxsa.add r<0, >, r<0, >, r<0, > +// CHECK: dxsa.add r<0, >, r<0, >, r<0, > +// CHECK: %[[INDEX_2:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_2:.*]] = dxsa.operand %[[INDEX_2]] {mask = 32 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_3:.*]] = dxsa.index.imm {imm = 3 : i32} +// CHECK: %[[OPERAND_3:.*]] = dxsa.operand %[[INDEX_3]] {num_components = 4 : i32, one = 0 : i32, type = 0 : i32} +// CHECK: dxsa.instruction "check_access_fully_mapped" %[[OPERAND_2]], %[[OPERAND_3]] +// CHECK: dxsa.utof r<0, >, r<0, > +// CHECK: dxsa.add o<0>, r<0, >, r<0, > +// CHECK: dxsa.instruction "ret" + diff --git a/mlir/test/Target/DXSA/hlsl/sample_cmp2.test b/mlir/test/Target/DXSA/hlsl/sample_cmp2.test new file mode 100644 index 000000000000..a394d3e6a879 --- /dev/null +++ b/mlir/test/Target/DXSA/hlsl/sample_cmp2.test @@ -0,0 +1,31 @@ +// RUN: mlir-translate --import-dxsa-bin %S/inputs/sample_cmp2.shex | FileCheck %s +// NOTE: Assertions have been autogenerated by utils/generate-test-checks.py + + +// CHECK-LABEL: dxsa.dcl_global_flags +// CHECK: dxsa.dcl_sampler +// CHECK: dxsa.dcl_resource , , +// CHECK: dxsa.dcl_input_ps linear v<0, > +// CHECK: dxsa.dcl_output o<0> +// CHECK: dxsa.dcl_temps 2 +// CHECK: dxsa.add r<0, >, v<0, >, v<0, > +// CHECK: dxsa.ftou r<0, >, r<0, > +// CHECK: dxsa.utof r<0, >, r<0, > +// CHECK: dxsa.unknown +// CHECK: dxsa.unknown +// CHECK: dxsa.add r<0, >, r<0, >, r<0, > +// CHECK: dxsa.unknown +// CHECK: dxsa.unknown +// CHECK: dxsa.add r<0, >, r<0, >, r<0, > +// CHECK: dxsa.add r<0, >, r<0, >, r<0, > +// CHECK: %[[INDEX_0:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_0:.*]] = dxsa.operand %[[INDEX_0]] {mask = 64 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_1:.*]] = dxsa.index.imm {imm = 1 : i32} +// CHECK: %[[OPERAND_1:.*]] = dxsa.operand %[[INDEX_1]] {num_components = 4 : i32, one = 0 : i32, type = 0 : i32} +// CHECK: dxsa.instruction "check_access_fully_mapped" %[[OPERAND_0]], %[[OPERAND_1]] +// CHECK: dxsa.utof r<0, >, r<0, > +// CHECK: dxsa.add r<0, >, r<0, >, r<0, > +// CHECK: dxsa.add r<0, >, r<0, >, r<0, > +// CHECK: dxsa.add o<0>, r<0, >, r<0, > +// CHECK: dxsa.instruction "ret" + diff --git a/mlir/test/Target/DXSA/hlsl/sample_grad1.test b/mlir/test/Target/DXSA/hlsl/sample_grad1.test new file mode 100644 index 000000000000..55bd3cc1e834 --- /dev/null +++ b/mlir/test/Target/DXSA/hlsl/sample_grad1.test @@ -0,0 +1,35 @@ +// RUN: mlir-translate --import-dxsa-bin %S/inputs/sample_grad1.shex | FileCheck %s +// NOTE: Assertions have been autogenerated by utils/generate-test-checks.py + + +// CHECK-LABEL: dxsa.dcl_global_flags +// CHECK: dxsa.dcl_sampler +// CHECK: dxsa.dcl_resource , , +// CHECK: dxsa.dcl_input_ps linear v<0, > +// CHECK: dxsa.dcl_output o<0> +// CHECK: dxsa.dcl_temps 3 +// CHECK: dxsa.unknown +// CHECK: dxsa.unknown +// CHECK: dxsa.add r<0>, r<0>, r<1> +// CHECK: dxsa.unknown +// CHECK: dxsa.add r<0>, r<0>, r<1> +// CHECK: dxsa.unknown +// CHECK: dxsa.add r<0>, r<0>, r<1> +// CHECK: %[[INDEX_0:.*]] = dxsa.index.imm {imm = 1 : i32} +// CHECK: %[[OPERAND_0:.*]] = dxsa.operand %[[INDEX_0]] {mask = 16 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_1:.*]] = dxsa.index.imm {imm = 2 : i32} +// CHECK: %[[OPERAND_1:.*]] = dxsa.operand %[[INDEX_1]] {num_components = 4 : i32, one = 0 : i32, type = 0 : i32} +// CHECK: dxsa.instruction "check_access_fully_mapped" %[[OPERAND_0]], %[[OPERAND_1]] +// CHECK: dxsa.utof r<1, >, r<1, > +// CHECK: dxsa.add r<0>, r<0>, r<1, > +// CHECK: dxsa.unknown +// CHECK: dxsa.add r<0>, r<0>, r<1> +// CHECK: %[[INDEX_2:.*]] = dxsa.index.imm {imm = 1 : i32} +// CHECK: %[[OPERAND_2:.*]] = dxsa.operand %[[INDEX_2]] {mask = 16 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_3:.*]] = dxsa.index.imm {imm = 2 : i32} +// CHECK: %[[OPERAND_3:.*]] = dxsa.operand %[[INDEX_3]] {num_components = 4 : i32, one = 0 : i32, type = 0 : i32} +// CHECK: dxsa.instruction "check_access_fully_mapped" %[[OPERAND_2]], %[[OPERAND_3]] +// CHECK: dxsa.utof r<1, >, r<1, > +// CHECK: dxsa.add o<0>, r<0>, r<1, > +// CHECK: dxsa.instruction "ret" + diff --git a/mlir/test/Target/DXSA/hlsl/sample_l1.test b/mlir/test/Target/DXSA/hlsl/sample_l1.test new file mode 100644 index 000000000000..8b010f19d46a --- /dev/null +++ b/mlir/test/Target/DXSA/hlsl/sample_l1.test @@ -0,0 +1,42 @@ +// RUN: mlir-translate --import-dxsa-bin %S/inputs/sample_l1.shex | FileCheck %s +// NOTE: Assertions have been autogenerated by utils/generate-test-checks.py + + +// CHECK-LABEL: dxsa.dcl_global_flags +// CHECK: dxsa.dcl_sampler +// CHECK: dxsa.dcl_resource , , +// CHECK: dxsa.dcl_resource , , +// CHECK: dxsa.dcl_input_ps linear v<0> +// CHECK: dxsa.dcl_output o<0> +// CHECK: dxsa.dcl_temps 3 +// CHECK: dxsa.unknown +// CHECK: dxsa.unknown +// CHECK: dxsa.add r<0>, r<0>, r<1> +// CHECK: dxsa.unknown +// CHECK: dxsa.add r<0>, r<0>, r<1> +// CHECK: dxsa.unknown +// CHECK: dxsa.add r<0>, r<0>, r<1> +// CHECK: %[[INDEX_0:.*]] = dxsa.index.imm {imm = 2 : i32} +// CHECK: %[[OPERAND_0:.*]] = dxsa.operand %[[INDEX_0]] {mask = 16 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_1:.*]] = dxsa.index.imm {imm = 2 : i32} +// CHECK: %[[OPERAND_1:.*]] = dxsa.operand %[[INDEX_1]] {num_components = 4 : i32, one = 0 : i32, type = 0 : i32} +// CHECK: dxsa.instruction "check_access_fully_mapped" %[[OPERAND_0]], %[[OPERAND_1]] +// CHECK: dxsa.utof r<2, >, r<2, > +// CHECK: dxsa.add r<0>, r<0>, r<2, > +// CHECK: dxsa.add r<0>, r<1>, r<0> +// CHECK: dxsa.add r<0>, r<2, >, r<0> +// CHECK: dxsa.unknown +// CHECK: dxsa.mad r<0>, r<1>, l(0x40400000, 0x40400000, 0x40400000, 0x40400000), r<0> +// CHECK: dxsa.unknown +// CHECK: dxsa.add r<0>, r<0>, r<1> +// CHECK: %[[INDEX_2:.*]] = dxsa.index.imm {imm = 2 : i32} +// CHECK: %[[OPERAND_2:.*]] = dxsa.operand %[[INDEX_2]] {mask = 16 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_3:.*]] = dxsa.index.imm {imm = 2 : i32} +// CHECK: %[[OPERAND_3:.*]] = dxsa.operand %[[INDEX_3]] {num_components = 4 : i32, one = 0 : i32, type = 0 : i32} +// CHECK: dxsa.instruction "check_access_fully_mapped" %[[OPERAND_2]], %[[OPERAND_3]] +// CHECK: dxsa.utof r<2, >, r<2, > +// CHECK: dxsa.add r<0>, r<0>, r<2, > +// CHECK: dxsa.add r<0>, r<1>, r<0> +// CHECK: dxsa.add o<0>, r<2, >, r<0> +// CHECK: dxsa.instruction "ret" + diff --git a/mlir/test/Target/DXSA/hlsl/samplecount.test b/mlir/test/Target/DXSA/hlsl/samplecount.test new file mode 100644 index 000000000000..88818895ffe5 --- /dev/null +++ b/mlir/test/Target/DXSA/hlsl/samplecount.test @@ -0,0 +1,16 @@ +// RUN: mlir-translate --import-dxsa-bin %S/inputs/samplecount.shex | FileCheck %s +// NOTE: Assertions have been autogenerated by utils/generate-test-checks.py + + +// CHECK-LABEL: dxsa.dcl_global_flags +// CHECK: dxsa.dcl_output o<0> +// CHECK: %[[INDEX_0:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_0:.*]] = dxsa.operand %[[INDEX_0]] {mask = 48 : i32, num_components = 4 : i32, type = 2 : i32} +// CHECK: %[[OPERAND_1:.*]] = dxsa.operand {num_components = 4 : i32, one = 0 : i32, type = 14 : i32} +// CHECK: dxsa.instruction "sampleinfo" %[[OPERAND_0]], %[[OPERAND_1]] +// CHECK: %[[INDEX_1:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_2:.*]] = dxsa.operand %[[INDEX_1]] {mask = 192 : i32, num_components = 4 : i32, type = 2 : i32} +// CHECK: %[[OPERAND_3:.*]] = dxsa.operand.imm {imm = dense<0> : vector<4xi32>} +// CHECK: dxsa.instruction "mov" %[[OPERAND_2]], %[[OPERAND_3]] +// CHECK: dxsa.instruction "ret" + diff --git a/mlir/test/Target/DXSA/hlsl/samplepos.test b/mlir/test/Target/DXSA/hlsl/samplepos.test new file mode 100644 index 000000000000..b7f3cab7da87 --- /dev/null +++ b/mlir/test/Target/DXSA/hlsl/samplepos.test @@ -0,0 +1,44 @@ +// RUN: mlir-translate --import-dxsa-bin %S/inputs/samplepos.shex | FileCheck %s +// NOTE: Assertions have been autogenerated by utils/generate-test-checks.py + + +// CHECK-LABEL: dxsa.dcl_global_flags +// CHECK: dxsa.unknown +// CHECK: dxsa.unknown +// CHECK: dxsa.dcl_input_ps linear v<0, > +// CHECK: dxsa.dcl_output o<0> +// CHECK: dxsa.dcl_output o<1> +// CHECK: dxsa.dcl_temps 2 +// CHECK: dxsa.ftoi r<0, >, v<0, > +// CHECK: dxsa.unknown +// CHECK: dxsa.unknown +// CHECK: %[[INDEX_0:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_0:.*]] = dxsa.operand %[[INDEX_0]] {mask = 96 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[OPERAND_1:.*]] = dxsa.operand {num_components = 4 : i32, swizzle = dense<[0, 0, 1, 0]> : vector<4xi32>, type = 14 : i32} +// CHECK: %[[INDEX_1:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_2:.*]] = dxsa.operand %[[INDEX_1]] {num_components = 4 : i32, one = 2 : i32, type = 0 : i32} +// CHECK: dxsa.instruction "samplepos" %[[OPERAND_0]], %[[OPERAND_1]], %[[OPERAND_2]] +// CHECK: dxsa.add r<0, >, r<0, >, r<1, > +// CHECK: %[[INDEX_2:.*]] = dxsa.index.imm {imm = 1 : i32} +// CHECK: %[[OPERAND_3:.*]] = dxsa.operand %[[INDEX_2]] {mask = 48 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[OPERAND_4:.*]] = dxsa.operand {num_components = 4 : i32, swizzle = dense<[0, 1, 0, 0]> : vector<4xi32>, type = 14 : i32} +// CHECK: %[[OPERAND_5:.*]] = dxsa.operand.imm {imm = dense<3> : vector<1xi32>} +// CHECK: dxsa.instruction "samplepos" %[[OPERAND_3]], %[[OPERAND_4]], %[[OPERAND_5]] +// CHECK: dxsa.add r<0, >, r<0, >, r<1, > +// CHECK: dxsa.add r<0, >, r<0, >, r<0, > +// CHECK: %[[INDEX_3:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_6:.*]] = dxsa.operand %[[INDEX_3]] {mask = 48 : i32, num_components = 4 : i32, type = 2 : i32} +// CHECK: %[[INDEX_4:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_7:.*]] = dxsa.operand %[[INDEX_4]] {num_components = 4 : i32, swizzle = dense<[0, 1, 0, 0]> : vector<4xi32>, type = 0 : i32} +// CHECK: dxsa.instruction "mov" %[[OPERAND_6]], %[[OPERAND_7]] +// CHECK: dxsa.add o<1, >, r<0, >, l(0x40A00000, 0x40A00000, 0x0, 0x0) +// CHECK: %[[INDEX_5:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_8:.*]] = dxsa.operand %[[INDEX_5]] {mask = 192 : i32, num_components = 4 : i32, type = 2 : i32} +// CHECK: %[[OPERAND_9:.*]] = dxsa.operand.imm {imm = dense<0> : vector<4xi32>} +// CHECK: dxsa.instruction "mov" %[[OPERAND_8]], %[[OPERAND_9]] +// CHECK: %[[INDEX_6:.*]] = dxsa.index.imm {imm = 1 : i32} +// CHECK: %[[OPERAND_10:.*]] = dxsa.operand %[[INDEX_6]] {mask = 192 : i32, num_components = 4 : i32, type = 2 : i32} +// CHECK: %[[OPERAND_11:.*]] = dxsa.operand.imm {imm = dense<[0, 0, 1084227584, 1084227584]> : vector<4xi32>} +// CHECK: dxsa.instruction "mov" %[[OPERAND_10]], %[[OPERAND_11]] +// CHECK: dxsa.instruction "ret" + diff --git a/mlir/test/Target/DXSA/hlsl/saturate1.test b/mlir/test/Target/DXSA/hlsl/saturate1.test new file mode 100644 index 000000000000..a5ebcce31861 --- /dev/null +++ b/mlir/test/Target/DXSA/hlsl/saturate1.test @@ -0,0 +1,14 @@ +// RUN: mlir-translate --import-dxsa-bin %S/inputs/saturate1.shex | FileCheck %s +// NOTE: Assertions have been autogenerated by utils/generate-test-checks.py + + +// CHECK-LABEL: dxsa.dcl_global_flags +// CHECK: dxsa.dcl_input_ps linear v<0, > +// CHECK: dxsa.dcl_output o<0, > +// CHECK: %[[INDEX_0:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_0:.*]] = dxsa.operand %[[INDEX_0]] {mask = 112 : i32, num_components = 4 : i32, type = 2 : i32} +// CHECK: %[[INDEX_1:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_1:.*]] = dxsa.operand %[[INDEX_1]] {num_components = 4 : i32, swizzle = dense<[0, 2, 0, 0]> : vector<4xi32>, type = 1 : i32} +// CHECK: dxsa.instruction "mov" %[[OPERAND_0]], %[[OPERAND_1]] +// CHECK: dxsa.instruction "ret" + diff --git a/mlir/test/Target/DXSA/hlsl/shift1.test b/mlir/test/Target/DXSA/hlsl/shift1.test new file mode 100644 index 000000000000..a91b55621b9c --- /dev/null +++ b/mlir/test/Target/DXSA/hlsl/shift1.test @@ -0,0 +1,53 @@ +// RUN: mlir-translate --import-dxsa-bin %S/inputs/shift1.shex | FileCheck %s +// NOTE: Assertions have been autogenerated by utils/generate-test-checks.py + + +// CHECK-LABEL: dxsa.dcl_global_flags +// CHECK: dxsa.dcl_input_ps constant v<0, > +// CHECK: dxsa.dcl_input_ps constant v<0, > +// CHECK: dxsa.dcl_input_ps constant v<0, > +// CHECK: dxsa.dcl_output o<0, > +// CHECK: dxsa.dcl_temps 1 +// CHECK: dxsa.ishl r<0, >, v<0, >, l(0x4D) +// CHECK: dxsa.ishr r<0, >, v<0, >, l(0x3) +// CHECK: %[[INDEX_0:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_0:.*]] = dxsa.operand %[[INDEX_0]] {mask = 16 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_1:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_1:.*]] = dxsa.operand %[[INDEX_1]] {num_components = 4 : i32, one = 1 : i32, type = 0 : i32} +// CHECK: %[[INDEX_2:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_2:.*]] = dxsa.operand %[[INDEX_2]] {num_components = 4 : i32, one = 0 : i32, type = 0 : i32} +// CHECK: dxsa.instruction "iadd" %[[OPERAND_0]], %[[OPERAND_1]], %[[OPERAND_2]] +// CHECK: dxsa.ushr r<0, >, v<0, >, l(0x8) +// CHECK: %[[INDEX_3:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_3:.*]] = dxsa.operand %[[INDEX_3]] {mask = 16 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_4:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_4:.*]] = dxsa.operand %[[INDEX_4]] {num_components = 4 : i32, one = 1 : i32, type = 0 : i32} +// CHECK: %[[INDEX_5:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_5:.*]] = dxsa.operand %[[INDEX_5]] {num_components = 4 : i32, one = 0 : i32, type = 0 : i32} +// CHECK: dxsa.instruction "iadd" %[[OPERAND_3]], %[[OPERAND_4]], %[[OPERAND_5]] +// CHECK: dxsa.ishl r<0, >, v<0, >, v<0, > +// CHECK: %[[INDEX_6:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_6:.*]] = dxsa.operand %[[INDEX_6]] {mask = 16 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_7:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_7:.*]] = dxsa.operand %[[INDEX_7]] {num_components = 4 : i32, one = 1 : i32, type = 0 : i32} +// CHECK: %[[INDEX_8:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_8:.*]] = dxsa.operand %[[INDEX_8]] {num_components = 4 : i32, one = 0 : i32, type = 0 : i32} +// CHECK: dxsa.instruction "iadd" %[[OPERAND_6]], %[[OPERAND_7]], %[[OPERAND_8]] +// CHECK: dxsa.ishr r<0, >, v<0, >, v<0, > +// CHECK: %[[INDEX_9:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_9:.*]] = dxsa.operand %[[INDEX_9]] {mask = 16 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_10:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_10:.*]] = dxsa.operand %[[INDEX_10]] {num_components = 4 : i32, one = 1 : i32, type = 0 : i32} +// CHECK: %[[INDEX_11:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_11:.*]] = dxsa.operand %[[INDEX_11]] {num_components = 4 : i32, one = 0 : i32, type = 0 : i32} +// CHECK: dxsa.instruction "iadd" %[[OPERAND_9]], %[[OPERAND_10]], %[[OPERAND_11]] +// CHECK: dxsa.ushr r<0, >, v<0, >, v<0, > +// CHECK: %[[INDEX_12:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_12:.*]] = dxsa.operand %[[INDEX_12]] {mask = 16 : i32, num_components = 4 : i32, type = 2 : i32} +// CHECK: %[[INDEX_13:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_13:.*]] = dxsa.operand %[[INDEX_13]] {num_components = 4 : i32, one = 1 : i32, type = 0 : i32} +// CHECK: %[[INDEX_14:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_14:.*]] = dxsa.operand %[[INDEX_14]] {num_components = 4 : i32, one = 0 : i32, type = 0 : i32} +// CHECK: dxsa.instruction "iadd" %[[OPERAND_12]], %[[OPERAND_13]], %[[OPERAND_14]] +// CHECK: dxsa.instruction "ret" + diff --git a/mlir/test/Target/DXSA/hlsl/sincos.test b/mlir/test/Target/DXSA/hlsl/sincos.test new file mode 100644 index 000000000000..3489db595ad3 --- /dev/null +++ b/mlir/test/Target/DXSA/hlsl/sincos.test @@ -0,0 +1,15 @@ +// RUN: mlir-translate --import-dxsa-bin %S/inputs/sincos.shex | FileCheck %s +// NOTE: Assertions have been autogenerated by utils/generate-test-checks.py + + +// CHECK-LABEL: dxsa.dcl_global_flags +// CHECK: dxsa.dcl_input v<0> +// CHECK: dxsa.dcl_output_siv o<0>, +// CHECK: dxsa.dcl_temps 3 +// CHECK: dxsa.add r<0, >, v<0, >, v<0, > +// CHECK: dxsa.sincos r<0, >, null, r<0, > +// CHECK: dxsa.sincos r<1>, r<2>, v<0> +// CHECK: dxsa.add r<1>, r<1>, r<2> +// CHECK: dxsa.add o<0>, r<0, >, r<1> +// CHECK: dxsa.instruction "ret" + diff --git a/mlir/test/Target/DXSA/hlsl/snorm1.test b/mlir/test/Target/DXSA/hlsl/snorm1.test new file mode 100644 index 000000000000..5c782b910919 --- /dev/null +++ b/mlir/test/Target/DXSA/hlsl/snorm1.test @@ -0,0 +1,16 @@ +// RUN: mlir-translate --import-dxsa-bin %S/inputs/snorm1.shex | FileCheck %s +// NOTE: Assertions have been autogenerated by utils/generate-test-checks.py + + +// CHECK-LABEL: dxsa.dcl_global_flags +// CHECK: dxsa.dcl_sampler +// CHECK: dxsa.dcl_resource , , +// CHECK: dxsa.dcl_resource , , +// CHECK: dxsa.dcl_input_ps linear v<0, > +// CHECK: dxsa.dcl_output o<0> +// CHECK: dxsa.dcl_temps 2 +// CHECK: dxsa.unknown +// CHECK: dxsa.unknown +// CHECK: dxsa.add o<0>, r<0>, r<1, > +// CHECK: dxsa.instruction "ret" + diff --git a/mlir/test/Target/DXSA/hlsl/srv_ms_load1.test b/mlir/test/Target/DXSA/hlsl/srv_ms_load1.test new file mode 100644 index 000000000000..f9444868484e --- /dev/null +++ b/mlir/test/Target/DXSA/hlsl/srv_ms_load1.test @@ -0,0 +1,56 @@ +// RUN: mlir-translate --import-dxsa-bin %S/inputs/srv_ms_load1.shex | FileCheck %s +// NOTE: Assertions have been autogenerated by utils/generate-test-checks.py + + +// CHECK-LABEL: dxsa.dcl_global_flags +// CHECK: dxsa.unknown +// CHECK: dxsa.dcl_input_ps constant v<0, > +// CHECK: dxsa.dcl_input_ps constant v<0, > +// CHECK: dxsa.dcl_input_ps constant v<1, > +// CHECK: dxsa.dcl_output o<0, > +// CHECK: dxsa.dcl_temps 4 +// CHECK: %[[INDEX_0:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_0:.*]] = dxsa.operand %[[INDEX_0]] {mask = 48 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_1:.*]] = dxsa.index.imm {imm = 1 : i32} +// CHECK: %[[OPERAND_1:.*]] = dxsa.operand %[[INDEX_1]] {num_components = 4 : i32, swizzle = dense<[0, 1, 0, 0]> : vector<4xi32>, type = 1 : i32} +// CHECK: dxsa.instruction "mov" %[[OPERAND_0]], %[[OPERAND_1]] +// CHECK: %[[INDEX_2:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_2:.*]] = dxsa.operand %[[INDEX_2]] {mask = 192 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[OPERAND_3:.*]] = dxsa.operand.imm {imm = dense<0> : vector<4xi32>} +// CHECK: dxsa.instruction "mov" %[[OPERAND_2]], %[[OPERAND_3]] +// CHECK: dxsa.unknown +// CHECK: %[[INDEX_3:.*]] = dxsa.index.imm {imm = 1 : i32} +// CHECK: %[[OPERAND_4:.*]] = dxsa.operand %[[INDEX_3]] {mask = 48 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_4:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_5:.*]] = dxsa.operand %[[INDEX_4]] {num_components = 4 : i32, swizzle = dense<[0, 1, 0, 0]> : vector<4xi32>, type = 1 : i32} +// CHECK: dxsa.instruction "mov" %[[OPERAND_4]], %[[OPERAND_5]] +// CHECK: %[[INDEX_5:.*]] = dxsa.index.imm {imm = 1 : i32} +// CHECK: %[[OPERAND_6:.*]] = dxsa.operand %[[INDEX_5]] {mask = 192 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[OPERAND_7:.*]] = dxsa.operand.imm {imm = dense<0> : vector<4xi32>} +// CHECK: dxsa.instruction "mov" %[[OPERAND_6]], %[[OPERAND_7]] +// CHECK: dxsa.unknown +// CHECK: dxsa.add r<0, >, r<0, >, r<2, > +// CHECK: dxsa.unknown +// CHECK: dxsa.add r<0, >, r<0, >, r<2, > +// CHECK: dxsa.unknown +// CHECK: dxsa.add r<0, >, r<0, >, r<2, > +// CHECK: %[[INDEX_6:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_8:.*]] = dxsa.operand %[[INDEX_6]] {mask = 128 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_7:.*]] = dxsa.index.imm {imm = 3 : i32} +// CHECK: %[[OPERAND_9:.*]] = dxsa.operand %[[INDEX_7]] {num_components = 4 : i32, one = 0 : i32, type = 0 : i32} +// CHECK: dxsa.instruction "check_access_fully_mapped" %[[OPERAND_8]], %[[OPERAND_9]] +// CHECK: dxsa.utof r<0, >, r<0, > +// CHECK: dxsa.add r<0, >, r<0, >, r<0, > +// CHECK: dxsa.unknown +// CHECK: dxsa.unknown +// CHECK: dxsa.add r<0, >, r<0, >, r<2, > +// CHECK: %[[INDEX_8:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_10:.*]] = dxsa.operand %[[INDEX_8]] {mask = 128 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_9:.*]] = dxsa.index.imm {imm = 3 : i32} +// CHECK: %[[OPERAND_11:.*]] = dxsa.operand %[[INDEX_9]] {num_components = 4 : i32, one = 0 : i32, type = 0 : i32} +// CHECK: dxsa.instruction "check_access_fully_mapped" %[[OPERAND_10]], %[[OPERAND_11]] +// CHECK: dxsa.utof r<0, >, r<0, > +// CHECK: dxsa.add r<0, >, r<0, >, r<0, > +// CHECK: dxsa.add o<0, >, r<1, >, r<0, > +// CHECK: dxsa.instruction "ret" + diff --git a/mlir/test/Target/DXSA/hlsl/srv_typed_load1.test b/mlir/test/Target/DXSA/hlsl/srv_typed_load1.test new file mode 100644 index 000000000000..5621621dcdbb --- /dev/null +++ b/mlir/test/Target/DXSA/hlsl/srv_typed_load1.test @@ -0,0 +1,41 @@ +// RUN: mlir-translate --import-dxsa-bin %S/inputs/srv_typed_load1.shex | FileCheck %s +// NOTE: Assertions have been autogenerated by utils/generate-test-checks.py + + +// CHECK-LABEL: dxsa.dcl_global_flags +// CHECK: dxsa.dcl_resource , , +// CHECK: dxsa.dcl_input_ps linear v<0, > +// CHECK: dxsa.dcl_input_ps linear v<1, > +// CHECK: dxsa.dcl_output o<0> +// CHECK: dxsa.dcl_temps 5 +// CHECK: dxsa.ftou r<0, >, v<1, > +// CHECK: %[[INDEX_0:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_0:.*]] = dxsa.operand %[[INDEX_0]] {mask = 192 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[OPERAND_1:.*]] = dxsa.operand.imm {imm = dense<0> : vector<4xi32>} +// CHECK: dxsa.instruction "mov" %[[OPERAND_0]], %[[OPERAND_1]] +// CHECK: dxsa.unknown +// CHECK: dxsa.ftoi r<1>, v<0, > +// CHECK: dxsa.unknown +// CHECK: dxsa.add r<0>, r<0>, r<2> +// CHECK: dxsa.unknown +// CHECK: dxsa.add r<0>, r<0>, r<2> +// CHECK: dxsa.unknown +// CHECK: dxsa.unknown +// CHECK: dxsa.add r<0>, r<0>, r<2> +// CHECK: %[[INDEX_1:.*]] = dxsa.index.imm {imm = 2 : i32} +// CHECK: %[[OPERAND_2:.*]] = dxsa.operand %[[INDEX_1]] {mask = 16 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_2:.*]] = dxsa.index.imm {imm = 3 : i32} +// CHECK: %[[OPERAND_3:.*]] = dxsa.operand %[[INDEX_2]] {num_components = 4 : i32, one = 0 : i32, type = 0 : i32} +// CHECK: dxsa.instruction "check_access_fully_mapped" %[[OPERAND_2]], %[[OPERAND_3]] +// CHECK: dxsa.utof r<2, >, r<2, > +// CHECK: dxsa.add r<0>, r<0>, r<2, > +// CHECK: dxsa.add r<0>, r<1>, r<0> +// CHECK: %[[INDEX_3:.*]] = dxsa.index.imm {imm = 1 : i32} +// CHECK: %[[OPERAND_4:.*]] = dxsa.operand %[[INDEX_3]] {mask = 16 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_4:.*]] = dxsa.index.imm {imm = 4 : i32} +// CHECK: %[[OPERAND_5:.*]] = dxsa.operand %[[INDEX_4]] {num_components = 4 : i32, one = 0 : i32, type = 0 : i32} +// CHECK: dxsa.instruction "check_access_fully_mapped" %[[OPERAND_4]], %[[OPERAND_5]] +// CHECK: dxsa.utof r<1, >, r<1, > +// CHECK: dxsa.add o<0>, r<0>, r<1, > +// CHECK: dxsa.instruction "ret" + diff --git a/mlir/test/Target/DXSA/hlsl/srv_typed_load2.test b/mlir/test/Target/DXSA/hlsl/srv_typed_load2.test new file mode 100644 index 000000000000..2c97440b7978 --- /dev/null +++ b/mlir/test/Target/DXSA/hlsl/srv_typed_load2.test @@ -0,0 +1,21 @@ +// RUN: mlir-translate --import-dxsa-bin %S/inputs/srv_typed_load2.shex | FileCheck %s +// NOTE: Assertions have been autogenerated by utils/generate-test-checks.py + + +// CHECK-LABEL: dxsa.dcl_global_flags +// CHECK: dxsa.dcl_resource , , +// CHECK: dxsa.dcl_input_ps constant v<0, > +// CHECK: dxsa.dcl_output o<0> +// CHECK: dxsa.dcl_temps 3 +// CHECK: dxsa.unknown +// CHECK: dxsa.unknown +// CHECK: dxsa.mad r<0>, r<0>, l(0x40000000, 0x40000000, 0x40000000, 0x40000000), r<1> +// CHECK: %[[INDEX_0:.*]] = dxsa.index.imm {imm = 1 : i32} +// CHECK: %[[OPERAND_0:.*]] = dxsa.operand %[[INDEX_0]] {mask = 16 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_1:.*]] = dxsa.index.imm {imm = 2 : i32} +// CHECK: %[[OPERAND_1:.*]] = dxsa.operand %[[INDEX_1]] {num_components = 4 : i32, one = 0 : i32, type = 0 : i32} +// CHECK: dxsa.instruction "check_access_fully_mapped" %[[OPERAND_0]], %[[OPERAND_1]] +// CHECK: dxsa.utof r<1, >, r<1, > +// CHECK: dxsa.add o<0>, r<0>, r<1, > +// CHECK: dxsa.instruction "ret" + diff --git a/mlir/test/Target/DXSA/hlsl/struct_buf1.test b/mlir/test/Target/DXSA/hlsl/struct_buf1.test new file mode 100644 index 000000000000..e7fe0ccafcd6 --- /dev/null +++ b/mlir/test/Target/DXSA/hlsl/struct_buf1.test @@ -0,0 +1,340 @@ +// RUN: mlir-translate --import-dxsa-bin %S/inputs/struct_buf1.shex | FileCheck %s +// NOTE: Assertions have been autogenerated by utils/generate-test-checks.py + + +// CHECK-LABEL: dxsa.dcl_global_flags +// CHECK: dxsa.dcl_resource_structured +// CHECK: dxsa.dcl_uav_structured +// CHECK: dxsa.dcl_input_ps linear v<0, > +// CHECK: dxsa.dcl_input_ps linear v<0, > +// CHECK: dxsa.dcl_output o<0> +// CHECK: dxsa.dcl_temps 22 +// CHECK: dxsa.add r<0, >, v<0, >, l(0x43480000, 0x43480000, 0x0, 0x0) +// CHECK: dxsa.ftoi r<0, >, r<0, > +// CHECK: dxsa.unknown +// CHECK: dxsa.unknown +// CHECK: dxsa.unknown +// CHECK: dxsa.unknown +// CHECK: dxsa.unknown +// CHECK: dxsa.unknown +// CHECK: dxsa.unknown +// CHECK: dxsa.unknown +// CHECK: dxsa.unknown +// CHECK: dxsa.unknown +// CHECK: dxsa.unknown +// CHECK: dxsa.unknown +// CHECK: %[[INDEX_0:.*]] = dxsa.index.imm {imm = 14 : i32} +// CHECK: %[[OPERAND_0:.*]] = dxsa.operand %[[INDEX_0]] {mask = 64 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[OPERAND_1:.*]] = dxsa.operand.imm {imm = dense<0> : vector<1xi32>} +// CHECK: dxsa.instruction "mov" %[[OPERAND_0]], %[[OPERAND_1]] +// CHECK: dxsa.ftou r<1, >, v<0, > +// CHECK: %[[INDEX_1:.*]] = dxsa.index.imm {imm = 5 : i32} +// CHECK: %[[OPERAND_2:.*]] = dxsa.operand %[[INDEX_1]] {mask = 64 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_2:.*]] = dxsa.index.imm {imm = 1 : i32} +// CHECK: %[[OPERAND_3:.*]] = dxsa.operand %[[INDEX_2]] {num_components = 4 : i32, one = 3 : i32, type = 0 : i32} +// CHECK: dxsa.instruction "ineg" %[[OPERAND_2]], %[[OPERAND_3]] +// CHECK: dxsa.ult r<7, >, r<1, >, l(0x0, 0x1, 0x2, 0x3) +// CHECK: dxsa.and r<5, >, r<5, >, r<7, > +// CHECK: dxsa.ftoi r<8, >, v<0, > +// CHECK: dxsa.unknown +// CHECK: %[[INDEX_3:.*]] = dxsa.index.imm {imm = 16 : i32} +// CHECK: %[[OPERAND_4:.*]] = dxsa.operand %[[INDEX_3]] {mask = 128 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_4:.*]] = dxsa.index.imm {imm = 15 : i32} +// CHECK: %[[OPERAND_5:.*]] = dxsa.operand %[[INDEX_4]] {num_components = 4 : i32, one = 1 : i32, type = 0 : i32} +// CHECK: dxsa.instruction "mov" %[[OPERAND_4]], %[[OPERAND_5]] +// CHECK: dxsa.unknown +// CHECK: dxsa.and r<9, >, r<5, >, r<16, > +// CHECK: dxsa.and r<11, >, r<7, >, r<16, > +// CHECK: dxsa.or r<9, >, r<9, >, r<11, > +// CHECK: %[[INDEX_5:.*]] = dxsa.index.imm {imm = 5 : i32} +// CHECK: %[[OPERAND_6:.*]] = dxsa.operand %[[INDEX_5]] {mask = 128 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_6:.*]] = dxsa.index.imm {imm = 1 : i32} +// CHECK: %[[OPERAND_7:.*]] = dxsa.operand %[[INDEX_6]] {num_components = 4 : i32, one = 3 : i32, type = 0 : i32} +// CHECK: %[[OPERAND_8:.*]] = dxsa.operand.imm {imm = dense<-3> : vector<1xi32>} +// CHECK: dxsa.instruction "iadd" %[[OPERAND_6]], %[[OPERAND_7]], %[[OPERAND_8]] +// CHECK: dxsa.ishl r<1, >, r<1, >, l(0x3) +// CHECK: %[[INDEX_7:.*]] = dxsa.index.imm {imm = 1 : i32} +// CHECK: %[[OPERAND_9:.*]] = dxsa.operand %[[INDEX_7]] {mask = 128 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_8:.*]] = dxsa.index.imm {imm = 1 : i32} +// CHECK: %[[OPERAND_10:.*]] = dxsa.operand %[[INDEX_8]] {num_components = 4 : i32, one = 3 : i32, type = 0 : i32} +// CHECK: %[[OPERAND_11:.*]] = dxsa.operand.imm {imm = dense<20> : vector<1xi32>} +// CHECK: dxsa.instruction "iadd" %[[OPERAND_9]], %[[OPERAND_10]], %[[OPERAND_11]] +// CHECK: %[[INDEX_9:.*]] = dxsa.index.imm {imm = 5 : i32} +// CHECK: %[[OPERAND_12:.*]] = dxsa.operand %[[INDEX_9]] {mask = 128 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_10:.*]] = dxsa.index.imm {imm = 7 : i32} +// CHECK: %[[OPERAND_13:.*]] = dxsa.operand %[[INDEX_10]] {num_components = 4 : i32, one = 2 : i32, type = 0 : i32} +// CHECK: %[[OPERAND_14:.*]] = dxsa.operand.imm {imm = dense<0> : vector<1xi32>} +// CHECK: %[[INDEX_11:.*]] = dxsa.index.imm {imm = 5 : i32} +// CHECK: %[[OPERAND_15:.*]] = dxsa.operand %[[INDEX_11]] {num_components = 4 : i32, one = 3 : i32, type = 0 : i32} +// CHECK: dxsa.instruction "movc" %[[OPERAND_12]], %[[OPERAND_13]], %[[OPERAND_14]], %[[OPERAND_15]] +// CHECK: dxsa.and r<11, >, r<15, >, r<5, > +// CHECK: dxsa.or r<9, >, r<9, >, r<11, > +// CHECK: dxsa.ieq r<7, >, r<7, >, l(0x0) +// CHECK: dxsa.unknown +// CHECK: dxsa.and r<11, >, r<7, >, r<15, > +// CHECK: dxsa.or r<9, >, r<9, >, r<11, > +// CHECK: dxsa.itof r<9, >, r<9, > +// CHECK: %[[INDEX_12:.*]] = dxsa.index.imm {imm = 15 : i32} +// CHECK: %[[OPERAND_16:.*]] = dxsa.operand %[[INDEX_12]] {mask = 64 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[OPERAND_17:.*]] = dxsa.operand.imm {imm = dense<0> : vector<1xi32>} +// CHECK: dxsa.instruction "mov" %[[OPERAND_16]], %[[OPERAND_17]] +// CHECK: dxsa.unknown +// CHECK: dxsa.unknown +// CHECK: dxsa.add r<14, >, r<11, >, r<15, > +// CHECK: dxsa.add r<15, >, r<9, >, r<14, > +// CHECK: %[[INDEX_13:.*]] = dxsa.index.imm {imm = 15 : i32} +// CHECK: %[[OPERAND_18:.*]] = dxsa.operand %[[INDEX_13]] {mask = 32 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_14:.*]] = dxsa.index.imm {imm = 14 : i32} +// CHECK: %[[OPERAND_19:.*]] = dxsa.operand %[[INDEX_14]] {num_components = 4 : i32, one = 0 : i32, type = 0 : i32} +// CHECK: dxsa.instruction "mov" %[[OPERAND_18]], %[[OPERAND_19]] +// CHECK: dxsa.unknown +// CHECK: dxsa.add r<14, >, r<15, >, r<16, > +// CHECK: %[[INDEX_15:.*]] = dxsa.index.imm {imm = 7 : i32} +// CHECK: %[[OPERAND_20:.*]] = dxsa.operand %[[INDEX_15]] {mask = 128 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_16:.*]] = dxsa.index.imm {imm = 17 : i32} +// CHECK: %[[OPERAND_21:.*]] = dxsa.operand %[[INDEX_16]] {num_components = 4 : i32, one = 0 : i32, type = 0 : i32} +// CHECK: dxsa.instruction "check_access_fully_mapped" %[[OPERAND_20]], %[[OPERAND_21]] +// CHECK: %[[INDEX_17:.*]] = dxsa.index.imm {imm = 16 : i32} +// CHECK: %[[OPERAND_22:.*]] = dxsa.operand %[[INDEX_17]] {mask = 48 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_18:.*]] = dxsa.index.imm {imm = 16 : i32} +// CHECK: %[[OPERAND_23:.*]] = dxsa.operand %[[INDEX_18]] {num_components = 4 : i32, swizzle = dense<[2, 3, 2, 2]> : vector<4xi32>, type = 0 : i32} +// CHECK: dxsa.instruction "mov" %[[OPERAND_22]], %[[OPERAND_23]] +// CHECK: dxsa.unknown +// CHECK: %[[INDEX_19:.*]] = dxsa.index.imm {imm = 8 : i32} +// CHECK: %[[OPERAND_24:.*]] = dxsa.operand %[[INDEX_19]] {mask = 32 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_20:.*]] = dxsa.index.imm {imm = 18 : i32} +// CHECK: %[[OPERAND_25:.*]] = dxsa.operand %[[INDEX_20]] {num_components = 4 : i32, one = 0 : i32, type = 0 : i32} +// CHECK: dxsa.instruction "check_access_fully_mapped" %[[OPERAND_24]], %[[OPERAND_25]] +// CHECK: dxsa.and r<7, >, r<7, >, r<8, > +// CHECK: dxsa.unknown +// CHECK: dxsa.unknown +// CHECK: %[[INDEX_21:.*]] = dxsa.index.imm {imm = 8 : i32} +// CHECK: %[[OPERAND_26:.*]] = dxsa.operand %[[INDEX_21]] {mask = 32 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_22:.*]] = dxsa.index.imm {imm = 19 : i32} +// CHECK: %[[OPERAND_27:.*]] = dxsa.operand %[[INDEX_22]] {num_components = 4 : i32, one = 0 : i32, type = 0 : i32} +// CHECK: dxsa.instruction "check_access_fully_mapped" %[[OPERAND_26]], %[[OPERAND_27]] +// CHECK: dxsa.and r<7, >, r<7, >, r<8, > +// CHECK: %[[INDEX_23:.*]] = dxsa.index.imm {imm = 8 : i32} +// CHECK: %[[OPERAND_28:.*]] = dxsa.operand %[[INDEX_23]] {mask = 32 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_24:.*]] = dxsa.index.imm {imm = 21 : i32} +// CHECK: %[[OPERAND_29:.*]] = dxsa.operand %[[INDEX_24]] {num_components = 4 : i32, one = 0 : i32, type = 0 : i32} +// CHECK: dxsa.instruction "check_access_fully_mapped" %[[OPERAND_28]], %[[OPERAND_29]] +// CHECK: dxsa.and r<7, >, r<7, >, r<8, > +// CHECK: dxsa.utof r<7, >, r<7, > +// CHECK: dxsa.add r<8, >, r<7, >, r<14, > +// CHECK: dxsa.mul r<15, >, r<7, >, l(0x3F800000, 0x0, 0x40000000, 0x0) +// CHECK: %[[INDEX_25:.*]] = dxsa.index.imm {imm = 16 : i32} +// CHECK: %[[OPERAND_30:.*]] = dxsa.operand %[[INDEX_25]] {mask = 64 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_26:.*]] = dxsa.index.imm {imm = 17 : i32} +// CHECK: %[[OPERAND_31:.*]] = dxsa.operand %[[INDEX_26]] {num_components = 4 : i32, one = 0 : i32, type = 0 : i32} +// CHECK: dxsa.instruction "mov" %[[OPERAND_30]], %[[OPERAND_31]] +// CHECK: dxsa.add r<14, >, r<8, >, r<16, > +// CHECK: %[[INDEX_27:.*]] = dxsa.index.imm {imm = 15 : i32} +// CHECK: %[[OPERAND_32:.*]] = dxsa.operand %[[INDEX_27]] {mask = 32 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_28:.*]] = dxsa.index.imm {imm = 14 : i32} +// CHECK: %[[OPERAND_33:.*]] = dxsa.operand %[[INDEX_28]] {num_components = 4 : i32, one = 1 : i32, type = 0 : i32} +// CHECK: dxsa.instruction "mov" %[[OPERAND_32]], %[[OPERAND_33]] +// CHECK: dxsa.add r<8, >, r<15, >, r<15, > +// CHECK: %[[INDEX_29:.*]] = dxsa.index.imm {imm = 14 : i32} +// CHECK: %[[OPERAND_34:.*]] = dxsa.operand %[[INDEX_29]] {mask = 128 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_30:.*]] = dxsa.index.imm {imm = 15 : i32} +// CHECK: %[[OPERAND_35:.*]] = dxsa.operand %[[INDEX_30]] {num_components = 4 : i32, one = 0 : i32, type = 0 : i32} +// CHECK: dxsa.instruction "mov" %[[OPERAND_34]], %[[OPERAND_35]] +// CHECK: dxsa.and r<9, >, r<7, >, r<17, > +// CHECK: %[[INDEX_31:.*]] = dxsa.index.imm {imm = 17 : i32} +// CHECK: %[[OPERAND_36:.*]] = dxsa.operand %[[INDEX_31]] {mask = 32 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_32:.*]] = dxsa.index.imm {imm = 18 : i32} +// CHECK: %[[OPERAND_37:.*]] = dxsa.operand %[[INDEX_32]] {num_components = 4 : i32, one = 0 : i32, type = 0 : i32} +// CHECK: dxsa.instruction "mov" %[[OPERAND_36]], %[[OPERAND_37]] +// CHECK: dxsa.and r<11, >, r<5, >, r<17, > +// CHECK: dxsa.or r<9, >, r<9, >, r<11, > +// CHECK: dxsa.and r<11, >, r<5, >, r<18, > +// CHECK: %[[INDEX_33:.*]] = dxsa.index.imm {imm = 20 : i32} +// CHECK: %[[OPERAND_38:.*]] = dxsa.operand %[[INDEX_33]] {mask = 32 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_34:.*]] = dxsa.index.imm {imm = 18 : i32} +// CHECK: %[[OPERAND_39:.*]] = dxsa.operand %[[INDEX_34]] {num_components = 4 : i32, one = 3 : i32, type = 0 : i32} +// CHECK: dxsa.instruction "mov" %[[OPERAND_38]], %[[OPERAND_39]] +// CHECK: dxsa.and r<12, >, r<7, >, r<20, > +// CHECK: dxsa.or r<9, >, r<9, >, r<11, > +// CHECK: dxsa.or r<9, >, r<9, >, r<12, > +// CHECK: dxsa.itof r<9, >, r<9, > +// CHECK: dxsa.add r<15, >, r<8, >, r<9, > +// CHECK: %[[INDEX_35:.*]] = dxsa.index.imm {imm = 15 : i32} +// CHECK: %[[OPERAND_40:.*]] = dxsa.operand %[[INDEX_35]] {mask = 80 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_36:.*]] = dxsa.index.imm {imm = 8 : i32} +// CHECK: %[[OPERAND_41:.*]] = dxsa.operand %[[INDEX_36]] {num_components = 4 : i32, swizzle = dense<1> : vector<4xi32>, type = 0 : i32} +// CHECK: dxsa.instruction "mov" %[[OPERAND_40]], %[[OPERAND_41]] +// CHECK: dxsa.add r<14>, r<14, >, r<15> +// CHECK: dxsa.add r<14, >, r<0, >, r<14, > +// CHECK: dxsa.add r<14, >, r<1, >, r<14, > +// CHECK: dxsa.and r<0, >, r<2, >, r<7, > +// CHECK: dxsa.and r<1, >, r<6, >, r<7, > +// CHECK: %[[INDEX_37:.*]] = dxsa.index.imm {imm = 2 : i32} +// CHECK: %[[OPERAND_42:.*]] = dxsa.operand %[[INDEX_37]] {mask = 128 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_38:.*]] = dxsa.index.imm {imm = 3 : i32} +// CHECK: %[[OPERAND_43:.*]] = dxsa.operand %[[INDEX_38]] {num_components = 4 : i32, one = 0 : i32, type = 0 : i32} +// CHECK: dxsa.instruction "mov" %[[OPERAND_42]], %[[OPERAND_43]] +// CHECK: dxsa.and r<2, >, r<2, >, r<5, > +// CHECK: dxsa.or r<0, >, r<0, >, r<2, > +// CHECK: dxsa.and r<2, >, r<3, >, r<5, > +// CHECK: dxsa.and r<2, >, r<10, >, r<5, > +// CHECK: %[[INDEX_39:.*]] = dxsa.index.imm {imm = 4 : i32} +// CHECK: %[[OPERAND_44:.*]] = dxsa.operand %[[INDEX_39]] {mask = 16 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_40:.*]] = dxsa.index.imm {imm = 3 : i32} +// CHECK: %[[OPERAND_45:.*]] = dxsa.operand %[[INDEX_40]] {num_components = 4 : i32, one = 3 : i32, type = 0 : i32} +// CHECK: dxsa.instruction "mov" %[[OPERAND_44]], %[[OPERAND_45]] +// CHECK: dxsa.and r<3, >, r<4, >, r<7, > +// CHECK: dxsa.or r<0, >, r<0, >, r<2, > +// CHECK: dxsa.or r<0, >, r<0, >, r<3, > +// CHECK: dxsa.itof r<0, >, r<0, > +// CHECK: dxsa.add r<3, >, r<0, >, r<14, > +// CHECK: %[[INDEX_41:.*]] = dxsa.index.imm {imm = 3 : i32} +// CHECK: %[[OPERAND_46:.*]] = dxsa.operand %[[INDEX_41]] {mask = 96 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_42:.*]] = dxsa.index.imm {imm = 14 : i32} +// CHECK: %[[OPERAND_47:.*]] = dxsa.operand %[[INDEX_42]] {num_components = 4 : i32, swizzle = dense<[0, 0, 2, 0]> : vector<4xi32>, type = 0 : i32} +// CHECK: dxsa.instruction "mov" %[[OPERAND_46]], %[[OPERAND_47]] +// CHECK: dxsa.add r<3, >, r<5, >, r<3, > +// CHECK: %[[INDEX_43:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_48:.*]] = dxsa.operand %[[INDEX_43]] {mask = 16 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_44:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_49:.*]] = dxsa.operand %[[INDEX_44]] {num_components = 4 : i32, one = 0 : i32, type = 0 : i32} +// CHECK: dxsa.instruction "check_access_fully_mapped" %[[OPERAND_48]], %[[OPERAND_49]] +// CHECK: dxsa.unknown +// CHECK: %[[INDEX_45:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_50:.*]] = dxsa.operand %[[INDEX_45]] {mask = 64 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_46:.*]] = dxsa.index.imm {imm = 2 : i32} +// CHECK: %[[OPERAND_51:.*]] = dxsa.operand %[[INDEX_46]] {num_components = 4 : i32, one = 0 : i32, type = 0 : i32} +// CHECK: dxsa.instruction "check_access_fully_mapped" %[[OPERAND_50]], %[[OPERAND_51]] +// CHECK: dxsa.and r<0, >, r<0, >, r<0, > +// CHECK: dxsa.unknown +// CHECK: dxsa.unknown +// CHECK: %[[INDEX_47:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_52:.*]] = dxsa.operand %[[INDEX_47]] {mask = 64 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_48:.*]] = dxsa.index.imm {imm = 4 : i32} +// CHECK: %[[OPERAND_53:.*]] = dxsa.operand %[[INDEX_48]] {num_components = 4 : i32, one = 0 : i32, type = 0 : i32} +// CHECK: dxsa.instruction "check_access_fully_mapped" %[[OPERAND_52]], %[[OPERAND_53]] +// CHECK: %[[INDEX_49:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_54:.*]] = dxsa.operand %[[INDEX_49]] {mask = 128 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_50:.*]] = dxsa.index.imm {imm = 2 : i32} +// CHECK: %[[OPERAND_55:.*]] = dxsa.operand %[[INDEX_50]] {num_components = 4 : i32, one = 0 : i32, type = 0 : i32} +// CHECK: dxsa.instruction "check_access_fully_mapped" %[[OPERAND_54]], %[[OPERAND_55]] +// CHECK: dxsa.and r<0, >, r<0, >, r<0, > +// CHECK: dxsa.and r<0, >, r<0, >, r<0, > +// CHECK: dxsa.utof r<0, >, r<0, > +// CHECK: dxsa.add r<3>, r<0, >, r<3> +// CHECK: %[[INDEX_51:.*]] = dxsa.index.imm {imm = 4 : i32} +// CHECK: %[[OPERAND_56:.*]] = dxsa.operand %[[INDEX_51]] {mask = 48 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_52:.*]] = dxsa.index.imm {imm = 4 : i32} +// CHECK: %[[OPERAND_57:.*]] = dxsa.operand %[[INDEX_52]] {num_components = 4 : i32, swizzle = dense<[2, 3, 2, 2]> : vector<4xi32>, type = 0 : i32} +// CHECK: dxsa.instruction "mov" %[[OPERAND_56]], %[[OPERAND_57]] +// CHECK: %[[INDEX_53:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_58:.*]] = dxsa.operand %[[INDEX_53]] {mask = 16 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_54:.*]] = dxsa.index.imm {imm = 6 : i32} +// CHECK: %[[OPERAND_59:.*]] = dxsa.operand %[[INDEX_54]] {num_components = 4 : i32, one = 0 : i32, type = 0 : i32} +// CHECK: dxsa.instruction "check_access_fully_mapped" %[[OPERAND_58]], %[[OPERAND_59]] +// CHECK: %[[INDEX_55:.*]] = dxsa.index.imm {imm = 4 : i32} +// CHECK: %[[OPERAND_60:.*]] = dxsa.operand %[[INDEX_55]] {mask = 64 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_56:.*]] = dxsa.index.imm {imm = 7 : i32} +// CHECK: %[[OPERAND_61:.*]] = dxsa.operand %[[INDEX_56]] {num_components = 4 : i32, one = 0 : i32, type = 0 : i32} +// CHECK: dxsa.instruction "mov" %[[OPERAND_60]], %[[OPERAND_61]] +// CHECK: %[[INDEX_57:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_62:.*]] = dxsa.operand %[[INDEX_57]] {mask = 64 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_58:.*]] = dxsa.index.imm {imm = 8 : i32} +// CHECK: %[[OPERAND_63:.*]] = dxsa.operand %[[INDEX_58]] {num_components = 4 : i32, one = 0 : i32, type = 0 : i32} +// CHECK: dxsa.instruction "check_access_fully_mapped" %[[OPERAND_62]], %[[OPERAND_63]] +// CHECK: dxsa.and r<0, >, r<0, >, r<0, > +// CHECK: dxsa.add r<3, >, r<3, >, r<4, > +// CHECK: dxsa.unknown +// CHECK: %[[INDEX_59:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_64:.*]] = dxsa.operand %[[INDEX_59]] {mask = 64 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_60:.*]] = dxsa.index.imm {imm = 2 : i32} +// CHECK: %[[OPERAND_65:.*]] = dxsa.operand %[[INDEX_60]] {num_components = 4 : i32, one = 0 : i32, type = 0 : i32} +// CHECK: dxsa.instruction "check_access_fully_mapped" %[[OPERAND_64]], %[[OPERAND_65]] +// CHECK: dxsa.and r<0, >, r<0, >, r<0, > +// CHECK: dxsa.unknown +// CHECK: dxsa.unknown +// CHECK: %[[INDEX_61:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_66:.*]] = dxsa.operand %[[INDEX_61]] {mask = 32 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_62:.*]] = dxsa.index.imm {imm = 4 : i32} +// CHECK: %[[OPERAND_67:.*]] = dxsa.operand %[[INDEX_62]] {num_components = 4 : i32, one = 0 : i32, type = 0 : i32} +// CHECK: dxsa.instruction "check_access_fully_mapped" %[[OPERAND_66]], %[[OPERAND_67]] +// CHECK: %[[INDEX_63:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_68:.*]] = dxsa.operand %[[INDEX_63]] {mask = 64 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_64:.*]] = dxsa.index.imm {imm = 2 : i32} +// CHECK: %[[OPERAND_69:.*]] = dxsa.operand %[[INDEX_64]] {num_components = 4 : i32, one = 0 : i32, type = 0 : i32} +// CHECK: dxsa.instruction "check_access_fully_mapped" %[[OPERAND_68]], %[[OPERAND_69]] +// CHECK: dxsa.and r<0, >, r<0, >, r<0, > +// CHECK: dxsa.utof r<0, >, r<0, > +// CHECK: dxsa.add r<3>, r<0, >, r<3> +// CHECK: %[[INDEX_65:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_70:.*]] = dxsa.operand %[[INDEX_65]] {mask = 16 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_66:.*]] = dxsa.index.imm {imm = 9 : i32} +// CHECK: %[[OPERAND_71:.*]] = dxsa.operand %[[INDEX_66]] {num_components = 4 : i32, one = 0 : i32, type = 0 : i32} +// CHECK: dxsa.instruction "check_access_fully_mapped" %[[OPERAND_70]], %[[OPERAND_71]] +// CHECK: dxsa.and r<0, >, r<0, >, r<0, > +// CHECK: %[[INDEX_67:.*]] = dxsa.index.imm {imm = 6 : i32} +// CHECK: %[[OPERAND_72:.*]] = dxsa.operand %[[INDEX_67]] {mask = 32 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_68:.*]] = dxsa.index.imm {imm = 10 : i32} +// CHECK: %[[OPERAND_73:.*]] = dxsa.operand %[[INDEX_68]] {num_components = 4 : i32, one = 0 : i32, type = 0 : i32} +// CHECK: dxsa.instruction "mov" %[[OPERAND_72]], %[[OPERAND_73]] +// CHECK: dxsa.and r<0, >, r<5, >, r<6, > +// CHECK: dxsa.or r<0, >, r<1, >, r<0, > +// CHECK: dxsa.or r<0, >, r<0, >, r<2, > +// CHECK: %[[INDEX_69:.*]] = dxsa.index.imm {imm = 12 : i32} +// CHECK: %[[OPERAND_74:.*]] = dxsa.operand %[[INDEX_69]] {mask = 32 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_70:.*]] = dxsa.index.imm {imm = 10 : i32} +// CHECK: %[[OPERAND_75:.*]] = dxsa.operand %[[INDEX_70]] {num_components = 4 : i32, one = 3 : i32, type = 0 : i32} +// CHECK: dxsa.instruction "mov" %[[OPERAND_74]], %[[OPERAND_75]] +// CHECK: %[[INDEX_71:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_76:.*]] = dxsa.operand %[[INDEX_71]] {mask = 128 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_72:.*]] = dxsa.index.imm {imm = 11 : i32} +// CHECK: %[[OPERAND_77:.*]] = dxsa.operand %[[INDEX_72]] {num_components = 4 : i32, one = 0 : i32, type = 0 : i32} +// CHECK: dxsa.instruction "check_access_fully_mapped" %[[OPERAND_76]], %[[OPERAND_77]] +// CHECK: dxsa.and r<0, >, r<0, >, r<0, > +// CHECK: dxsa.and r<1, >, r<7, >, r<12, > +// CHECK: %[[INDEX_73:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_78:.*]] = dxsa.operand %[[INDEX_73]] {mask = 128 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_74:.*]] = dxsa.index.imm {imm = 13 : i32} +// CHECK: %[[OPERAND_79:.*]] = dxsa.operand %[[INDEX_74]] {num_components = 4 : i32, one = 0 : i32, type = 0 : i32} +// CHECK: dxsa.instruction "check_access_fully_mapped" %[[OPERAND_78]], %[[OPERAND_79]] +// CHECK: dxsa.and r<0, >, r<0, >, r<0, > +// CHECK: dxsa.utof r<0, >, r<0, > +// CHECK: dxsa.or r<0, >, r<0, >, r<1, > +// CHECK: dxsa.itof r<0, >, r<0, > +// CHECK: dxsa.add r<3, >, r<0, >, r<3, > +// CHECK: dxsa.add r<0>, r<0, >, r<3> +// CHECK: dxsa.mul r<1, >, v<0, >, l(0x40400000) +// CHECK: dxsa.ftou r<1, >, r<1, > +// CHECK: %[[INDEX_75:.*]] = dxsa.index.imm {imm = 1 : i32} +// CHECK: %[[OPERAND_80:.*]] = dxsa.operand %[[INDEX_75]] {mask = 48 : i32, num_components = 4 : i32, type = 30 : i32} +// CHECK: %[[INDEX_76:.*]] = dxsa.index.imm {imm = 1 : i32} +// CHECK: %[[OPERAND_81:.*]] = dxsa.operand %[[INDEX_76]] {num_components = 4 : i32, one = 0 : i32, type = 0 : i32} +// CHECK: %[[OPERAND_82:.*]] = dxsa.operand.imm {imm = dense<0> : vector<1xi32>} +// CHECK: %[[INDEX_77:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_83:.*]] = dxsa.operand %[[INDEX_77]] {num_components = 4 : i32, swizzle = dense<[0, 1, 0, 0]> : vector<4xi32>, type = 0 : i32} +// CHECK: dxsa.instruction "store_structured" %[[OPERAND_80]], %[[OPERAND_81]], %[[OPERAND_82]], %[[OPERAND_83]] +// CHECK: %[[INDEX_78:.*]] = dxsa.index.imm {imm = 1 : i32} +// CHECK: %[[OPERAND_84:.*]] = dxsa.operand %[[INDEX_78]] {mask = 112 : i32, num_components = 4 : i32, type = 30 : i32} +// CHECK: %[[INDEX_79:.*]] = dxsa.index.imm {imm = 1 : i32} +// CHECK: %[[OPERAND_85:.*]] = dxsa.operand %[[INDEX_79]] {num_components = 4 : i32, one = 0 : i32, type = 0 : i32} +// CHECK: %[[OPERAND_86:.*]] = dxsa.operand.imm {imm = dense<8> : vector<1xi32>} +// CHECK: %[[INDEX_80:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_87:.*]] = dxsa.operand %[[INDEX_80]] {num_components = 4 : i32, swizzle = dense<[0, 1, 2, 0]> : vector<4xi32>, type = 0 : i32} +// CHECK: dxsa.instruction "store_structured" %[[OPERAND_84]], %[[OPERAND_85]], %[[OPERAND_86]], %[[OPERAND_87]] +// CHECK: dxsa.ftoi r<1, >, r<0, > +// CHECK: %[[INDEX_81:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_88:.*]] = dxsa.operand %[[INDEX_81]] {mask = 240 : i32, num_components = 4 : i32, type = 2 : i32} +// CHECK: %[[INDEX_82:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_89:.*]] = dxsa.operand %[[INDEX_82]] {num_components = 4 : i32, swizzle = dense<[0, 1, 2, 3]> : vector<4xi32>, type = 0 : i32} +// CHECK: dxsa.instruction "mov" %[[OPERAND_88]], %[[OPERAND_89]] +// CHECK: %[[INDEX_83:.*]] = dxsa.index.imm {imm = 1 : i32} +// CHECK: %[[OPERAND_90:.*]] = dxsa.operand %[[INDEX_83]] {mask = 48 : i32, num_components = 4 : i32, type = 30 : i32} +// CHECK: %[[INDEX_84:.*]] = dxsa.index.imm {imm = 1 : i32} +// CHECK: %[[OPERAND_91:.*]] = dxsa.operand %[[INDEX_84]] {num_components = 4 : i32, one = 0 : i32, type = 0 : i32} +// CHECK: %[[INDEX_85:.*]] = dxsa.index.imm {imm = 1 : i32} +// CHECK: %[[OPERAND_92:.*]] = dxsa.operand %[[INDEX_85]] {num_components = 4 : i32, one = 3 : i32, type = 0 : i32} +// CHECK: %[[INDEX_86:.*]] = dxsa.index.imm {imm = 1 : i32} +// CHECK: %[[OPERAND_93:.*]] = dxsa.operand %[[INDEX_86]] {num_components = 4 : i32, swizzle = dense<[1, 2, 1, 1]> : vector<4xi32>, type = 0 : i32} +// CHECK: dxsa.instruction "store_structured" %[[OPERAND_90]], %[[OPERAND_91]], %[[OPERAND_92]], %[[OPERAND_93]] +// CHECK: dxsa.instruction "ret" + diff --git a/mlir/test/Target/DXSA/hlsl/sub1.test b/mlir/test/Target/DXSA/hlsl/sub1.test new file mode 100644 index 000000000000..e96a3b87b931 --- /dev/null +++ b/mlir/test/Target/DXSA/hlsl/sub1.test @@ -0,0 +1,84 @@ +// RUN: mlir-translate --import-dxsa-bin %S/inputs/sub1.shex | FileCheck %s +// NOTE: Assertions have been autogenerated by utils/generate-test-checks.py + + +// CHECK-LABEL: dxsa.dcl_global_flags +// CHECK: dxsa.dcl_constant_buffer , +// CHECK: dxsa.dcl_input_ps linear v<0, > +// CHECK: dxsa.dcl_output o<0> +// CHECK: dxsa.dcl_temps 1 +// CHECK: dxsa.dcl_indexable_temp x<0>[8] +// CHECK: %[[INDEX_0:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[INDEX_1:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_0:.*]] = dxsa.operand %[[INDEX_0]], %[[INDEX_1]] {num_components = 4 : i32, one = 0 : i32, type = 8 : i32} +// CHECK: dxsa.instruction "switch" %[[OPERAND_0]] +// CHECK: %[[OPERAND_1:.*]] = dxsa.operand.imm {imm = dense<0> : vector<1xi32>} +// CHECK: dxsa.instruction "case" %[[OPERAND_1]] +// CHECK: %[[INDEX_2:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_2:.*]] = dxsa.operand %[[INDEX_2]] {num_components = 0 : i32, type = 10 : i32} +// CHECK: dxsa.instruction "call" %[[OPERAND_2]] +// CHECK: dxsa.instruction "break" +// CHECK: %[[OPERAND_3:.*]] = dxsa.operand.imm {imm = dense<1> : vector<1xi32>} +// CHECK: dxsa.instruction "case" %[[OPERAND_3]] +// CHECK: %[[INDEX_3:.*]] = dxsa.index.imm {imm = 1 : i32} +// CHECK: %[[OPERAND_4:.*]] = dxsa.operand %[[INDEX_3]] {num_components = 0 : i32, type = 10 : i32} +// CHECK: dxsa.instruction "call" %[[OPERAND_4]] +// CHECK: dxsa.instruction "break" +// CHECK: dxsa.instruction "default" +// CHECK: %[[INDEX_4:.*]] = dxsa.index.imm {imm = 2 : i32} +// CHECK: %[[OPERAND_5:.*]] = dxsa.operand %[[INDEX_4]] {num_components = 0 : i32, type = 10 : i32} +// CHECK: dxsa.instruction "call" %[[OPERAND_5]] +// CHECK: dxsa.instruction "break" +// CHECK: dxsa.instruction "endswitch" +// CHECK: %[[INDEX_5:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_6:.*]] = dxsa.operand %[[INDEX_5]] {mask = 16 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_6:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[INDEX_7:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_7:.*]] = dxsa.operand %[[INDEX_6]], %[[INDEX_7]] {num_components = 4 : i32, one = 1 : i32, type = 8 : i32} +// CHECK: dxsa.instruction "mov" %[[OPERAND_6]], %[[OPERAND_7]] +// CHECK: %[[INDEX_8:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_8:.*]] = dxsa.operand %[[INDEX_8]] {mask = 240 : i32, num_components = 4 : i32, type = 2 : i32} +// CHECK: %[[INDEX_9:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[INDEX_10:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_9:.*]] = dxsa.operand %[[INDEX_10]] {num_components = 4 : i32, one = 0 : i32, type = 0 : i32} +// CHECK: %[[INDEX_11:.*]] = dxsa.index.rel %[[OPERAND_9]] +// CHECK: %[[OPERAND_10:.*]] = dxsa.operand %[[INDEX_9]], %[[INDEX_11]] {num_components = 4 : i32, swizzle = dense<[0, 1, 2, 3]> : vector<4xi32>, type = 3 : i32} +// CHECK: dxsa.instruction "mov" %[[OPERAND_8]], %[[OPERAND_10]] +// CHECK: dxsa.instruction "ret" +// CHECK: %[[INDEX_12:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_11:.*]] = dxsa.operand %[[INDEX_12]] {num_components = 0 : i32, type = 10 : i32} +// CHECK: dxsa.instruction "label" %[[OPERAND_11]] +// CHECK: %[[INDEX_13:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[INDEX_14:.*]] = dxsa.index.imm {imm = 2 : i32} +// CHECK: %[[OPERAND_12:.*]] = dxsa.operand %[[INDEX_13]], %[[INDEX_14]] {mask = 240 : i32, num_components = 4 : i32, type = 3 : i32} +// CHECK: %[[OPERAND_13:.*]] = dxsa.operand.imm {imm = dense<1082130432> : vector<4xi32>} +// CHECK: dxsa.instruction "mov" %[[OPERAND_12]], %[[OPERAND_13]] +// CHECK: dxsa.instruction "ret" +// CHECK: %[[INDEX_15:.*]] = dxsa.index.imm {imm = 1 : i32} +// CHECK: %[[OPERAND_14:.*]] = dxsa.operand %[[INDEX_15]] {num_components = 0 : i32, type = 10 : i32} +// CHECK: dxsa.instruction "label" %[[OPERAND_14]] +// CHECK: %[[INDEX_16:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[INDEX_17:.*]] = dxsa.index.imm {imm = 2 : i32} +// CHECK: %[[OPERAND_15:.*]] = dxsa.operand %[[INDEX_16]], %[[INDEX_17]] {mask = 240 : i32, num_components = 4 : i32, type = 3 : i32} +// CHECK: %[[INDEX_18:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_16:.*]] = dxsa.operand %[[INDEX_18]] {num_components = 4 : i32, swizzle = dense<0> : vector<4xi32>, type = 1 : i32} +// CHECK: dxsa.instruction "mov" %[[OPERAND_15]], %[[OPERAND_16]] +// CHECK: dxsa.instruction "ret" +// CHECK: %[[INDEX_19:.*]] = dxsa.index.imm {imm = 2 : i32} +// CHECK: %[[OPERAND_17:.*]] = dxsa.operand %[[INDEX_19]] {num_components = 0 : i32, type = 10 : i32} +// CHECK: dxsa.instruction "label" %[[OPERAND_17]] +// CHECK: %[[INDEX_20:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_18:.*]] = dxsa.operand %[[INDEX_20]] {mask = 16 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_21:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[INDEX_22:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_19:.*]] = dxsa.operand %[[INDEX_21]], %[[INDEX_22]] {num_components = 4 : i32, one = 0 : i32, type = 8 : i32} +// CHECK: dxsa.instruction "mov" %[[OPERAND_18]], %[[OPERAND_19]] +// CHECK: %[[INDEX_23:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[INDEX_24:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_20:.*]] = dxsa.operand %[[INDEX_24]] {num_components = 4 : i32, one = 0 : i32, type = 0 : i32} +// CHECK: %[[INDEX_25:.*]] = dxsa.index.rel %[[OPERAND_20]] +// CHECK: %[[OPERAND_21:.*]] = dxsa.operand %[[INDEX_23]], %[[INDEX_25]] {mask = 240 : i32, num_components = 4 : i32, type = 3 : i32} +// CHECK: %[[OPERAND_22:.*]] = dxsa.operand.imm {imm = dense<0> : vector<4xi32>} +// CHECK: dxsa.instruction "mov" %[[OPERAND_21]], %[[OPERAND_22]] +// CHECK: dxsa.instruction "ret" + diff --git a/mlir/test/Target/DXSA/hlsl/switch1.test b/mlir/test/Target/DXSA/hlsl/switch1.test new file mode 100644 index 000000000000..e77032402536 --- /dev/null +++ b/mlir/test/Target/DXSA/hlsl/switch1.test @@ -0,0 +1,41 @@ +// RUN: mlir-translate --import-dxsa-bin %S/inputs/switch1.shex | FileCheck %s +// NOTE: Assertions have been autogenerated by utils/generate-test-checks.py + + +// CHECK-LABEL: dxsa.dcl_global_flags +// CHECK: dxsa.dcl_input_ps linear v<0, > +// CHECK: dxsa.dcl_input_ps constant v<1, > +// CHECK: dxsa.dcl_output o<0, > +// CHECK: dxsa.dcl_temps 1 +// CHECK: %[[INDEX_0:.*]] = dxsa.index.imm {imm = 1 : i32} +// CHECK: %[[OPERAND_0:.*]] = dxsa.operand %[[INDEX_0]] {num_components = 4 : i32, one = 0 : i32, type = 1 : i32} +// CHECK: dxsa.instruction "switch" %[[OPERAND_0]] +// CHECK: %[[OPERAND_1:.*]] = dxsa.operand.imm {imm = dense<1> : vector<1xi32>} +// CHECK: dxsa.instruction "case" %[[OPERAND_1]] +// CHECK: %[[INDEX_1:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_2:.*]] = dxsa.operand %[[INDEX_1]] {mask = 16 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[OPERAND_3:.*]] = dxsa.operand.imm {imm = dense<1084227584> : vector<1xi32>} +// CHECK: dxsa.instruction "mov" %[[OPERAND_2]], %[[OPERAND_3]] +// CHECK: dxsa.instruction "break" +// CHECK: %[[OPERAND_4:.*]] = dxsa.operand.imm {imm = dense<2> : vector<1xi32>} +// CHECK: dxsa.instruction "case" %[[OPERAND_4]] +// CHECK: %[[INDEX_2:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_5:.*]] = dxsa.operand %[[INDEX_2]] {mask = 16 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_3:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_6:.*]] = dxsa.operand %[[INDEX_3]] {num_components = 4 : i32, one = 0 : i32, type = 1 : i32} +// CHECK: dxsa.instruction "mov" %[[OPERAND_5]], %[[OPERAND_6]] +// CHECK: dxsa.instruction "break" +// CHECK: dxsa.instruction "default" +// CHECK: %[[INDEX_4:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_7:.*]] = dxsa.operand %[[INDEX_4]] {mask = 16 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[OPERAND_8:.*]] = dxsa.operand.imm {imm = dense<1077936128> : vector<1xi32>} +// CHECK: dxsa.instruction "mov" %[[OPERAND_7]], %[[OPERAND_8]] +// CHECK: dxsa.instruction "break" +// CHECK: dxsa.instruction "endswitch" +// CHECK: %[[INDEX_5:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_9:.*]] = dxsa.operand %[[INDEX_5]] {mask = 16 : i32, num_components = 4 : i32, type = 2 : i32} +// CHECK: %[[INDEX_6:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_10:.*]] = dxsa.operand %[[INDEX_6]] {num_components = 4 : i32, one = 0 : i32, type = 0 : i32} +// CHECK: dxsa.instruction "mov" %[[OPERAND_9]], %[[OPERAND_10]] +// CHECK: dxsa.instruction "ret" + diff --git a/mlir/test/Target/DXSA/hlsl/switch2.test b/mlir/test/Target/DXSA/hlsl/switch2.test new file mode 100644 index 000000000000..440ec3da9df4 --- /dev/null +++ b/mlir/test/Target/DXSA/hlsl/switch2.test @@ -0,0 +1,55 @@ +// RUN: mlir-translate --import-dxsa-bin %S/inputs/switch2.shex | FileCheck %s +// NOTE: Assertions have been autogenerated by utils/generate-test-checks.py + + +// CHECK-LABEL: dxsa.dcl_global_flags +// CHECK: dxsa.dcl_input_ps linear v<0, > +// CHECK: dxsa.dcl_input_ps constant v<1, > +// CHECK: dxsa.dcl_output o<0, > +// CHECK: dxsa.dcl_temps 1 +// CHECK: %[[INDEX_0:.*]] = dxsa.index.imm {imm = 1 : i32} +// CHECK: %[[OPERAND_0:.*]] = dxsa.operand %[[INDEX_0]] {num_components = 4 : i32, one = 0 : i32, type = 1 : i32} +// CHECK: dxsa.instruction "switch" %[[OPERAND_0]] +// CHECK: %[[OPERAND_1:.*]] = dxsa.operand.imm {imm = dense<1> : vector<1xi32>} +// CHECK: dxsa.instruction "case" %[[OPERAND_1]] +// CHECK: dxsa.ieq r<0, >, v<1, >, l(0xB) +// CHECK: %[[INDEX_1:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_2:.*]] = dxsa.operand %[[INDEX_1]] {num_components = 4 : i32, one = 1 : i32, type = 0 : i32} +// CHECK: dxsa.instruction "if" %[[OPERAND_2]] +// CHECK: %[[INDEX_2:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_3:.*]] = dxsa.operand %[[INDEX_2]] {mask = 16 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[OPERAND_4:.*]] = dxsa.operand.imm {imm = dense<1084227584> : vector<1xi32>} +// CHECK: dxsa.instruction "mov" %[[OPERAND_3]], %[[OPERAND_4]] +// CHECK: dxsa.instruction "break" +// CHECK: dxsa.instruction "endif" +// CHECK: %[[INDEX_3:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_5:.*]] = dxsa.operand %[[INDEX_3]] {mask = 16 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[OPERAND_6:.*]] = dxsa.operand.imm {imm = dense<1085276160> : vector<1xi32>} +// CHECK: dxsa.instruction "mov" %[[OPERAND_5]], %[[OPERAND_6]] +// CHECK: dxsa.instruction "break" +// CHECK: %[[OPERAND_7:.*]] = dxsa.operand.imm {imm = dense<2> : vector<1xi32>} +// CHECK: dxsa.instruction "case" %[[OPERAND_7]] +// CHECK: dxsa.ieq r<0, >, v<1, >, l(0xC) +// CHECK: %[[INDEX_4:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_8:.*]] = dxsa.operand %[[INDEX_4]] {num_components = 4 : i32, one = 1 : i32, type = 0 : i32} +// CHECK: dxsa.instruction "breakc" %[[OPERAND_8]] +// CHECK: %[[INDEX_5:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_9:.*]] = dxsa.operand %[[INDEX_5]] {mask = 16 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_6:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_10:.*]] = dxsa.operand %[[INDEX_6]] {num_components = 4 : i32, one = 0 : i32, type = 1 : i32} +// CHECK: dxsa.instruction "mov" %[[OPERAND_9]], %[[OPERAND_10]] +// CHECK: dxsa.instruction "break" +// CHECK: dxsa.instruction "default" +// CHECK: %[[INDEX_7:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_11:.*]] = dxsa.operand %[[INDEX_7]] {mask = 16 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[OPERAND_12:.*]] = dxsa.operand.imm {imm = dense<1077936128> : vector<1xi32>} +// CHECK: dxsa.instruction "mov" %[[OPERAND_11]], %[[OPERAND_12]] +// CHECK: dxsa.instruction "break" +// CHECK: dxsa.instruction "endswitch" +// CHECK: %[[INDEX_8:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_13:.*]] = dxsa.operand %[[INDEX_8]] {mask = 16 : i32, num_components = 4 : i32, type = 2 : i32} +// CHECK: %[[INDEX_9:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_14:.*]] = dxsa.operand %[[INDEX_9]] {num_components = 4 : i32, one = 0 : i32, type = 0 : i32} +// CHECK: dxsa.instruction "mov" %[[OPERAND_13]], %[[OPERAND_14]] +// CHECK: dxsa.instruction "ret" + diff --git a/mlir/test/Target/DXSA/hlsl/switch3.test b/mlir/test/Target/DXSA/hlsl/switch3.test new file mode 100644 index 000000000000..9215a3517b7b --- /dev/null +++ b/mlir/test/Target/DXSA/hlsl/switch3.test @@ -0,0 +1,73 @@ +// RUN: mlir-translate --import-dxsa-bin %S/inputs/switch3.shex | FileCheck %s +// NOTE: Assertions have been autogenerated by utils/generate-test-checks.py + + +// CHECK-LABEL: dxsa.dcl_global_flags +// CHECK: dxsa.dcl_input_ps linear v<0, > +// CHECK: dxsa.dcl_input_ps constant v<1, > +// CHECK: dxsa.dcl_output o<0, > +// CHECK: dxsa.dcl_temps 1 +// CHECK: %[[INDEX_0:.*]] = dxsa.index.imm {imm = 1 : i32} +// CHECK: %[[OPERAND_0:.*]] = dxsa.operand %[[INDEX_0]] {num_components = 4 : i32, one = 0 : i32, type = 1 : i32} +// CHECK: dxsa.instruction "switch" %[[OPERAND_0]] +// CHECK: %[[OPERAND_1:.*]] = dxsa.operand.imm {imm = dense<1> : vector<1xi32>} +// CHECK: dxsa.instruction "case" %[[OPERAND_1]] +// CHECK: %[[INDEX_1:.*]] = dxsa.index.imm {imm = 1 : i32} +// CHECK: %[[OPERAND_2:.*]] = dxsa.operand %[[INDEX_1]] {num_components = 4 : i32, one = 1 : i32, type = 1 : i32} +// CHECK: dxsa.instruction "switch" %[[OPERAND_2]] +// CHECK: %[[OPERAND_3:.*]] = dxsa.operand.imm {imm = dense<20> : vector<1xi32>} +// CHECK: dxsa.instruction "case" %[[OPERAND_3]] +// CHECK: dxsa.ieq r<0, >, v<1, >, l(0x1E) +// CHECK: %[[INDEX_2:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_4:.*]] = dxsa.operand %[[INDEX_2]] {num_components = 4 : i32, one = 1 : i32, type = 0 : i32} +// CHECK: dxsa.instruction "if" %[[OPERAND_4]] +// CHECK: %[[INDEX_3:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_5:.*]] = dxsa.operand %[[INDEX_3]] {mask = 16 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[OPERAND_6:.*]] = dxsa.operand.imm {imm = dense<1085276160> : vector<1xi32>} +// CHECK: dxsa.instruction "mov" %[[OPERAND_5]], %[[OPERAND_6]] +// CHECK: dxsa.instruction "break" +// CHECK: dxsa.instruction "endif" +// CHECK: dxsa.ieq r<0, >, v<1, >, l(0x1F) +// CHECK: %[[INDEX_4:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_7:.*]] = dxsa.operand %[[INDEX_4]] {mask = 16 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[OPERAND_8:.*]] = dxsa.operand.imm {imm = dense<1085695590> : vector<1xi32>} +// CHECK: dxsa.instruction "mov" %[[OPERAND_7]], %[[OPERAND_8]] +// CHECK: %[[INDEX_5:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_9:.*]] = dxsa.operand %[[INDEX_5]] {num_components = 4 : i32, one = 1 : i32, type = 0 : i32} +// CHECK: dxsa.instruction "breakc" %[[OPERAND_9]] +// CHECK: %[[INDEX_6:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_10:.*]] = dxsa.operand %[[INDEX_6]] {mask = 16 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[OPERAND_11:.*]] = dxsa.operand.imm {imm = dense<1085905306> : vector<1xi32>} +// CHECK: dxsa.instruction "mov" %[[OPERAND_10]], %[[OPERAND_11]] +// CHECK: dxsa.instruction "break" +// CHECK: dxsa.instruction "default" +// CHECK: %[[INDEX_7:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_12:.*]] = dxsa.operand %[[INDEX_7]] {mask = 16 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_8:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_13:.*]] = dxsa.operand %[[INDEX_8]] {num_components = 4 : i32, one = 1 : i32, type = 1 : i32} +// CHECK: dxsa.instruction "mov" %[[OPERAND_12]], %[[OPERAND_13]] +// CHECK: dxsa.instruction "break" +// CHECK: dxsa.instruction "endswitch" +// CHECK: dxsa.instruction "break" +// CHECK: %[[OPERAND_14:.*]] = dxsa.operand.imm {imm = dense<2> : vector<1xi32>} +// CHECK: dxsa.instruction "case" %[[OPERAND_14]] +// CHECK: %[[INDEX_9:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_15:.*]] = dxsa.operand %[[INDEX_9]] {mask = 16 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_10:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_16:.*]] = dxsa.operand %[[INDEX_10]] {num_components = 4 : i32, one = 0 : i32, type = 1 : i32} +// CHECK: dxsa.instruction "mov" %[[OPERAND_15]], %[[OPERAND_16]] +// CHECK: dxsa.instruction "break" +// CHECK: dxsa.instruction "default" +// CHECK: %[[INDEX_11:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_17:.*]] = dxsa.operand %[[INDEX_11]] {mask = 16 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[OPERAND_18:.*]] = dxsa.operand.imm {imm = dense<1077936128> : vector<1xi32>} +// CHECK: dxsa.instruction "mov" %[[OPERAND_17]], %[[OPERAND_18]] +// CHECK: dxsa.instruction "break" +// CHECK: dxsa.instruction "endswitch" +// CHECK: %[[INDEX_12:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_19:.*]] = dxsa.operand %[[INDEX_12]] {mask = 16 : i32, num_components = 4 : i32, type = 2 : i32} +// CHECK: %[[INDEX_13:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_20:.*]] = dxsa.operand %[[INDEX_13]] {num_components = 4 : i32, one = 0 : i32, type = 0 : i32} +// CHECK: dxsa.instruction "mov" %[[OPERAND_19]], %[[OPERAND_20]] +// CHECK: dxsa.instruction "ret" + diff --git a/mlir/test/Target/DXSA/hlsl/swizzle1.test b/mlir/test/Target/DXSA/hlsl/swizzle1.test new file mode 100644 index 000000000000..04b4be354f42 --- /dev/null +++ b/mlir/test/Target/DXSA/hlsl/swizzle1.test @@ -0,0 +1,15 @@ +// RUN: mlir-translate --import-dxsa-bin %S/inputs/swizzle1.shex | FileCheck %s +// NOTE: Assertions have been autogenerated by utils/generate-test-checks.py + + +// CHECK-LABEL: dxsa.dcl_global_flags +// CHECK: dxsa.dcl_input_ps linear v<0, > +// CHECK: dxsa.dcl_input_ps linear v<1, > +// CHECK: dxsa.dcl_input_ps linear v<2, > +// CHECK: dxsa.dcl_output o<0> +// CHECK: dxsa.dcl_temps 1 +// CHECK: dxsa.add r<0>, v<0, >, v<1, > +// CHECK: dxsa.add r<0>, r<0>, v<2, > +// CHECK: dxsa.add o<0>, r<0>, l(0x0, 0x3F800000, 0x40000000, 0x40400000) +// CHECK: dxsa.instruction "ret" + diff --git a/mlir/test/Target/DXSA/hlsl/temp1.test b/mlir/test/Target/DXSA/hlsl/temp1.test new file mode 100644 index 000000000000..03c3d8ddd830 --- /dev/null +++ b/mlir/test/Target/DXSA/hlsl/temp1.test @@ -0,0 +1,13 @@ +// RUN: mlir-translate --import-dxsa-bin %S/inputs/temp1.shex | FileCheck %s +// NOTE: Assertions have been autogenerated by utils/generate-test-checks.py + + +// CHECK-LABEL: dxsa.dcl_global_flags +// CHECK: dxsa.dcl_input_ps linear v<0> +// CHECK: dxsa.dcl_input_ps linear v<1> +// CHECK: dxsa.dcl_output o<0> +// CHECK: dxsa.dcl_temps 1 +// CHECK: dxsa.add r<0>, v<0>, v<1> +// CHECK: dxsa.add o<0>, r<0>, l(0x0, 0x3F800000, 0x40000000, 0x40400000) +// CHECK: dxsa.instruction "ret" + diff --git a/mlir/test/Target/DXSA/hlsl/temp2.test b/mlir/test/Target/DXSA/hlsl/temp2.test new file mode 100644 index 000000000000..fbe2fd8c935d --- /dev/null +++ b/mlir/test/Target/DXSA/hlsl/temp2.test @@ -0,0 +1,24 @@ +// RUN: mlir-translate --import-dxsa-bin %S/inputs/temp2.shex | FileCheck %s +// NOTE: Assertions have been autogenerated by utils/generate-test-checks.py + + +// CHECK-LABEL: dxsa.dcl_global_flags +// CHECK: dxsa.dcl_input_ps constant v<0> +// CHECK: dxsa.dcl_input_ps constant v<1> +// CHECK: dxsa.dcl_output o<0> +// CHECK: dxsa.dcl_temps 1 +// CHECK: %[[INDEX_0:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_0:.*]] = dxsa.operand %[[INDEX_0]] {mask = 240 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_1:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_1:.*]] = dxsa.operand %[[INDEX_1]] {num_components = 4 : i32, swizzle = dense<[0, 1, 2, 3]> : vector<4xi32>, type = 1 : i32} +// CHECK: %[[INDEX_2:.*]] = dxsa.index.imm {imm = 1 : i32} +// CHECK: %[[OPERAND_2:.*]] = dxsa.operand %[[INDEX_2]] {num_components = 4 : i32, swizzle = dense<[0, 1, 2, 3]> : vector<4xi32>, type = 1 : i32} +// CHECK: dxsa.instruction "iadd" %[[OPERAND_0]], %[[OPERAND_1]], %[[OPERAND_2]] +// CHECK: %[[INDEX_3:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_3:.*]] = dxsa.operand %[[INDEX_3]] {mask = 240 : i32, num_components = 4 : i32, type = 2 : i32} +// CHECK: %[[INDEX_4:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_4:.*]] = dxsa.operand %[[INDEX_4]] {num_components = 4 : i32, swizzle = dense<[0, 1, 2, 3]> : vector<4xi32>, type = 0 : i32} +// CHECK: %[[OPERAND_5:.*]] = dxsa.operand.imm {imm = dense<[0, 1, 2, 3]> : vector<4xi32>} +// CHECK: dxsa.instruction "iadd" %[[OPERAND_3]], %[[OPERAND_4]], %[[OPERAND_5]] +// CHECK: dxsa.instruction "ret" + diff --git a/mlir/test/Target/DXSA/hlsl/uav_counter_dec.test b/mlir/test/Target/DXSA/hlsl/uav_counter_dec.test new file mode 100644 index 000000000000..139bab0a43da --- /dev/null +++ b/mlir/test/Target/DXSA/hlsl/uav_counter_dec.test @@ -0,0 +1,14 @@ +// RUN: mlir-translate --import-dxsa-bin %S/inputs/uav_counter_dec.shex | FileCheck %s +// NOTE: Assertions have been autogenerated by utils/generate-test-checks.py + + +// CHECK-LABEL: dxsa.dcl_global_flags +// CHECK: dxsa.dcl_uav_structured , +// CHECK: dxsa.dcl_temps 1 +// CHECK: %[[INDEX_0:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_0:.*]] = dxsa.operand %[[INDEX_0]] {mask = 16 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_1:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_1:.*]] = dxsa.operand %[[INDEX_1]] {num_components = 0 : i32, type = 30 : i32} +// CHECK: dxsa.instruction "imm_atomic_consume" %[[OPERAND_0]], %[[OPERAND_1]] +// CHECK: dxsa.instruction "ret" + diff --git a/mlir/test/Target/DXSA/hlsl/uav_counter_inc.test b/mlir/test/Target/DXSA/hlsl/uav_counter_inc.test new file mode 100644 index 000000000000..7b70fbe19e03 --- /dev/null +++ b/mlir/test/Target/DXSA/hlsl/uav_counter_inc.test @@ -0,0 +1,14 @@ +// RUN: mlir-translate --import-dxsa-bin %S/inputs/uav_counter_inc.shex | FileCheck %s +// NOTE: Assertions have been autogenerated by utils/generate-test-checks.py + + +// CHECK-LABEL: dxsa.dcl_global_flags +// CHECK: dxsa.dcl_uav_structured , +// CHECK: dxsa.dcl_temps 1 +// CHECK: %[[INDEX_0:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_0:.*]] = dxsa.operand %[[INDEX_0]] {mask = 16 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_1:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_1:.*]] = dxsa.operand %[[INDEX_1]] {num_components = 0 : i32, type = 30 : i32} +// CHECK: dxsa.instruction "imm_atomic_alloc" %[[OPERAND_0]], %[[OPERAND_1]] +// CHECK: dxsa.instruction "ret" + diff --git a/mlir/test/Target/DXSA/hlsl/uav_raw1.test b/mlir/test/Target/DXSA/hlsl/uav_raw1.test new file mode 100644 index 000000000000..90256701cd89 --- /dev/null +++ b/mlir/test/Target/DXSA/hlsl/uav_raw1.test @@ -0,0 +1,35 @@ +// RUN: mlir-translate --import-dxsa-bin %S/inputs/uav_raw1.shex | FileCheck %s +// NOTE: Assertions have been autogenerated by utils/generate-test-checks.py + + +// CHECK-LABEL: dxsa.dcl_global_flags +// CHECK: dxsa.dcl_uav_raw +// CHECK: dxsa.dcl_input_ps constant v<0, > +// CHECK: dxsa.dcl_input_ps constant v<0, > +// CHECK: dxsa.dcl_output o<0> +// CHECK: dxsa.dcl_temps 2 +// CHECK: dxsa.unknown +// CHECK: dxsa.utof r<0, >, r<0, > +// CHECK: dxsa.unknown +// CHECK: %[[INDEX_0:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_0:.*]] = dxsa.operand %[[INDEX_0]] {mask = 32 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_1:.*]] = dxsa.index.imm {imm = 1 : i32} +// CHECK: %[[OPERAND_1:.*]] = dxsa.operand %[[INDEX_1]] {num_components = 4 : i32, one = 0 : i32, type = 0 : i32} +// CHECK: dxsa.instruction "check_access_fully_mapped" %[[OPERAND_0]], %[[OPERAND_1]] +// CHECK: dxsa.utof r<0, >, r<0, > +// CHECK: dxsa.mad r<0>, r<0, >, l(0x40000000, 0x40000000, 0x40000000, 0x40000000), r<0, > +// CHECK: dxsa.ftou r<1, >, r<0, > +// CHECK: %[[INDEX_2:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_2:.*]] = dxsa.operand %[[INDEX_2]] {mask = 240 : i32, num_components = 4 : i32, type = 2 : i32} +// CHECK: %[[INDEX_3:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_3:.*]] = dxsa.operand %[[INDEX_3]] {num_components = 4 : i32, swizzle = dense<[0, 1, 2, 3]> : vector<4xi32>, type = 0 : i32} +// CHECK: dxsa.instruction "mov" %[[OPERAND_2]], %[[OPERAND_3]] +// CHECK: %[[INDEX_4:.*]] = dxsa.index.imm {imm = 3 : i32} +// CHECK: %[[OPERAND_4:.*]] = dxsa.operand %[[INDEX_4]] {mask = 240 : i32, num_components = 4 : i32, type = 30 : i32} +// CHECK: %[[INDEX_5:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_5:.*]] = dxsa.operand %[[INDEX_5]] {num_components = 4 : i32, one = 1 : i32, type = 1 : i32} +// CHECK: %[[INDEX_6:.*]] = dxsa.index.imm {imm = 1 : i32} +// CHECK: %[[OPERAND_6:.*]] = dxsa.operand %[[INDEX_6]] {num_components = 4 : i32, swizzle = dense<0> : vector<4xi32>, type = 0 : i32} +// CHECK: dxsa.instruction "store_raw" %[[OPERAND_4]], %[[OPERAND_5]], %[[OPERAND_6]] +// CHECK: dxsa.instruction "ret" + diff --git a/mlir/test/Target/DXSA/hlsl/uav_typed_load_store1.test b/mlir/test/Target/DXSA/hlsl/uav_typed_load_store1.test new file mode 100644 index 000000000000..b66349001864 --- /dev/null +++ b/mlir/test/Target/DXSA/hlsl/uav_typed_load_store1.test @@ -0,0 +1,35 @@ +// RUN: mlir-translate --import-dxsa-bin %S/inputs/uav_typed_load_store1.shex | FileCheck %s +// NOTE: Assertions have been autogenerated by utils/generate-test-checks.py + + +// CHECK-LABEL: dxsa.dcl_global_flags +// CHECK: dxsa.dcl_uav_typed , +// CHECK: dxsa.dcl_input_ps constant v<0, > +// CHECK: dxsa.dcl_input_ps constant v<0, > +// CHECK: dxsa.dcl_output o<0> +// CHECK: dxsa.dcl_temps 2 +// CHECK: dxsa.unknown +// CHECK: dxsa.unknown +// CHECK: dxsa.add r<0>, r<0>, r<1> +// CHECK: dxsa.unknown +// CHECK: %[[INDEX_0:.*]] = dxsa.index.imm {imm = 1 : i32} +// CHECK: %[[OPERAND_0:.*]] = dxsa.operand %[[INDEX_0]] {mask = 16 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_1:.*]] = dxsa.index.imm {imm = 1 : i32} +// CHECK: %[[OPERAND_1:.*]] = dxsa.operand %[[INDEX_1]] {num_components = 4 : i32, one = 0 : i32, type = 0 : i32} +// CHECK: dxsa.instruction "check_access_fully_mapped" %[[OPERAND_0]], %[[OPERAND_1]] +// CHECK: dxsa.utof r<1, >, r<1, > +// CHECK: dxsa.mad r<0>, r<1, >, l(0x40000000, 0x40000000, 0x40000000, 0x40000000), r<0> +// CHECK: %[[INDEX_2:.*]] = dxsa.index.imm {imm = 3 : i32} +// CHECK: %[[OPERAND_2:.*]] = dxsa.operand %[[INDEX_2]] {mask = 240 : i32, num_components = 4 : i32, type = 30 : i32} +// CHECK: %[[INDEX_3:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_3:.*]] = dxsa.operand %[[INDEX_3]] {num_components = 4 : i32, swizzle = dense<[2, 3, 3, 3]> : vector<4xi32>, type = 1 : i32} +// CHECK: %[[INDEX_4:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_4:.*]] = dxsa.operand %[[INDEX_4]] {num_components = 4 : i32, swizzle = dense<[0, 1, 2, 3]> : vector<4xi32>, type = 0 : i32} +// CHECK: dxsa.instruction "store_uav_typed" %[[OPERAND_2]], %[[OPERAND_3]], %[[OPERAND_4]] +// CHECK: %[[INDEX_5:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_5:.*]] = dxsa.operand %[[INDEX_5]] {mask = 240 : i32, num_components = 4 : i32, type = 2 : i32} +// CHECK: %[[INDEX_6:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_6:.*]] = dxsa.operand %[[INDEX_6]] {num_components = 4 : i32, swizzle = dense<[0, 1, 2, 3]> : vector<4xi32>, type = 0 : i32} +// CHECK: dxsa.instruction "mov" %[[OPERAND_5]], %[[OPERAND_6]] +// CHECK: dxsa.instruction "ret" + diff --git a/mlir/test/Target/DXSA/hlsl/uav_typed_load_store2.test b/mlir/test/Target/DXSA/hlsl/uav_typed_load_store2.test new file mode 100644 index 000000000000..3a68ac55c9cc --- /dev/null +++ b/mlir/test/Target/DXSA/hlsl/uav_typed_load_store2.test @@ -0,0 +1,66 @@ +// RUN: mlir-translate --import-dxsa-bin %S/inputs/uav_typed_load_store2.shex | FileCheck %s +// NOTE: Assertions have been autogenerated by utils/generate-test-checks.py + + +// CHECK-LABEL: dxsa.dcl_global_flags +// CHECK: dxsa.dcl_uav_typed , +// CHECK: dxsa.dcl_input_ps constant v<0, > +// CHECK: dxsa.dcl_input_ps constant v<0, > +// CHECK: dxsa.dcl_output o<0, > +// CHECK: dxsa.dcl_temps 5 +// CHECK: dxsa.unknown +// CHECK: dxsa.unknown +// CHECK: %[[INDEX_0:.*]] = dxsa.index.imm {imm = 2 : i32} +// CHECK: %[[OPERAND_0:.*]] = dxsa.operand %[[INDEX_0]] {mask = 112 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_1:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_1:.*]] = dxsa.operand %[[INDEX_1]] {min_precision = 4 : i32, num_components = 4 : i32, swizzle = dense<[0, 1, 2, 0]> : vector<4xi32>, type = 0 : i32} +// CHECK: %[[INDEX_2:.*]] = dxsa.index.imm {imm = 1 : i32} +// CHECK: %[[OPERAND_2:.*]] = dxsa.operand %[[INDEX_2]] {min_precision = 4 : i32, num_components = 4 : i32, swizzle = dense<[0, 1, 2, 0]> : vector<4xi32>, type = 0 : i32} +// CHECK: dxsa.instruction "iadd" %[[OPERAND_0]], %[[OPERAND_1]], %[[OPERAND_2]] +// CHECK: dxsa.unknown +// CHECK: dxsa.unknown +// CHECK: %[[INDEX_3:.*]] = dxsa.index.imm {imm = 2 : i32} +// CHECK: %[[OPERAND_3:.*]] = dxsa.operand %[[INDEX_3]] {mask = 128 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_4:.*]] = dxsa.index.imm {imm = 3 : i32} +// CHECK: %[[OPERAND_4:.*]] = dxsa.operand %[[INDEX_4]] {num_components = 4 : i32, one = 0 : i32, type = 0 : i32} +// CHECK: dxsa.instruction "check_access_fully_mapped" %[[OPERAND_3]], %[[OPERAND_4]] +// CHECK: %[[INDEX_5:.*]] = dxsa.index.imm {imm = 2 : i32} +// CHECK: %[[OPERAND_5:.*]] = dxsa.operand %[[INDEX_5]] {mask = 112 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_6:.*]] = dxsa.index.imm {imm = 2 : i32} +// CHECK: %[[OPERAND_6:.*]] = dxsa.operand %[[INDEX_6]] {num_components = 4 : i32, swizzle = dense<3> : vector<4xi32>, type = 0 : i32} +// CHECK: %[[INDEX_7:.*]] = dxsa.index.imm {imm = 2 : i32} +// CHECK: %[[OPERAND_7:.*]] = dxsa.operand %[[INDEX_7]] {num_components = 4 : i32, swizzle = dense<[0, 1, 2, 0]> : vector<4xi32>, type = 0 : i32} +// CHECK: dxsa.instruction "iadd" %[[OPERAND_5]], %[[OPERAND_6]], %[[OPERAND_7]] +// CHECK: %[[INDEX_8:.*]] = dxsa.index.imm {imm = 2 : i32} +// CHECK: %[[OPERAND_8:.*]] = dxsa.operand %[[INDEX_8]] {mask = 128 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_9:.*]] = dxsa.index.imm {imm = 4 : i32} +// CHECK: %[[OPERAND_9:.*]] = dxsa.operand %[[INDEX_9]] {num_components = 4 : i32, one = 0 : i32, type = 0 : i32} +// CHECK: dxsa.instruction "check_access_fully_mapped" %[[OPERAND_8]], %[[OPERAND_9]] +// CHECK: %[[INDEX_10:.*]] = dxsa.index.imm {imm = 2 : i32} +// CHECK: %[[OPERAND_10:.*]] = dxsa.operand %[[INDEX_10]] {mask = 112 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_11:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_11:.*]] = dxsa.operand %[[INDEX_11]] {min_precision = 4 : i32, num_components = 4 : i32, swizzle = dense<[0, 1, 2, 0]> : vector<4xi32>, type = 0 : i32} +// CHECK: %[[INDEX_12:.*]] = dxsa.index.imm {imm = 2 : i32} +// CHECK: %[[OPERAND_12:.*]] = dxsa.operand %[[INDEX_12]] {num_components = 4 : i32, swizzle = dense<[0, 1, 2, 0]> : vector<4xi32>, type = 0 : i32} +// CHECK: dxsa.instruction "iadd" %[[OPERAND_10]], %[[OPERAND_11]], %[[OPERAND_12]] +// CHECK: %[[INDEX_13:.*]] = dxsa.index.imm {imm = 2 : i32} +// CHECK: %[[OPERAND_13:.*]] = dxsa.operand %[[INDEX_13]] {mask = 112 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_14:.*]] = dxsa.index.imm {imm = 2 : i32} +// CHECK: %[[OPERAND_14:.*]] = dxsa.operand %[[INDEX_14]] {num_components = 4 : i32, swizzle = dense<3> : vector<4xi32>, type = 0 : i32} +// CHECK: %[[INDEX_15:.*]] = dxsa.index.imm {imm = 2 : i32} +// CHECK: %[[OPERAND_15:.*]] = dxsa.operand %[[INDEX_15]] {num_components = 4 : i32, swizzle = dense<[0, 1, 2, 0]> : vector<4xi32>, type = 0 : i32} +// CHECK: dxsa.instruction "iadd" %[[OPERAND_13]], %[[OPERAND_14]], %[[OPERAND_15]] +// CHECK: %[[INDEX_16:.*]] = dxsa.index.imm {imm = 3 : i32} +// CHECK: %[[OPERAND_16:.*]] = dxsa.operand %[[INDEX_16]] {mask = 240 : i32, num_components = 4 : i32, type = 30 : i32} +// CHECK: %[[INDEX_17:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_17:.*]] = dxsa.operand %[[INDEX_17]] {num_components = 4 : i32, swizzle = dense<1> : vector<4xi32>, type = 1 : i32} +// CHECK: %[[INDEX_18:.*]] = dxsa.index.imm {imm = 2 : i32} +// CHECK: %[[OPERAND_18:.*]] = dxsa.operand %[[INDEX_18]] {num_components = 4 : i32, swizzle = dense<[0, 1, 2, 0]> : vector<4xi32>, type = 0 : i32} +// CHECK: dxsa.instruction "store_uav_typed" %[[OPERAND_16]], %[[OPERAND_17]], %[[OPERAND_18]] +// CHECK: %[[INDEX_19:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_19:.*]] = dxsa.operand %[[INDEX_19]] {mask = 112 : i32, num_components = 4 : i32, type = 2 : i32} +// CHECK: %[[INDEX_20:.*]] = dxsa.index.imm {imm = 2 : i32} +// CHECK: %[[OPERAND_20:.*]] = dxsa.operand %[[INDEX_20]] {num_components = 4 : i32, swizzle = dense<[0, 1, 2, 0]> : vector<4xi32>, type = 0 : i32} +// CHECK: dxsa.instruction "mov" %[[OPERAND_19]], %[[OPERAND_20]] +// CHECK: dxsa.instruction "ret" + diff --git a/mlir/test/Target/DXSA/hlsl/ubfeu16.test b/mlir/test/Target/DXSA/hlsl/ubfeu16.test new file mode 100644 index 000000000000..0edd46526d0a --- /dev/null +++ b/mlir/test/Target/DXSA/hlsl/ubfeu16.test @@ -0,0 +1,27 @@ +// RUN: mlir-translate --import-dxsa-bin %S/inputs/ubfeu16.shex | FileCheck %s +// NOTE: Assertions have been autogenerated by utils/generate-test-checks.py + + +// CHECK-LABEL: dxsa.dcl_global_flags +// CHECK: dxsa.dcl_constant_buffer , +// CHECK: dxsa.dcl_output o<0, min16u, > +// CHECK: dxsa.dcl_temps 1 +// CHECK: %[[INDEX_0:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_0:.*]] = dxsa.operand %[[INDEX_0]] {mask = 16 : i32, min_precision = 5 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[OPERAND_1:.*]] = dxsa.operand.imm {imm = dense<27> : vector<1xi32>} +// CHECK: %[[OPERAND_2:.*]] = dxsa.operand.imm {imm = dense<5> : vector<1xi32>} +// CHECK: %[[INDEX_1:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[INDEX_2:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_3:.*]] = dxsa.operand %[[INDEX_1]], %[[INDEX_2]] {min_precision = 5 : i32, num_components = 4 : i32, one = 0 : i32, type = 8 : i32} +// CHECK: dxsa.instruction "ubfe" %[[OPERAND_0]], %[[OPERAND_1]], %[[OPERAND_2]], %[[OPERAND_3]] +// CHECK: dxsa.and r<0, min16u, >, cb<[0, 0], vector, min16u, >, l(0xFFFFFFFC) +// CHECK: dxsa.xor r<0, min16u, >, r<0, min16u, >, r<0, min16u, > +// CHECK: %[[INDEX_3:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_4:.*]] = dxsa.operand %[[INDEX_3]] {mask = 16 : i32, min_precision = 5 : i32, num_components = 4 : i32, type = 2 : i32} +// CHECK: %[[INDEX_4:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_5:.*]] = dxsa.operand %[[INDEX_4]] {min_precision = 5 : i32, num_components = 4 : i32, one = 0 : i32, type = 0 : i32} +// CHECK: %[[INDEX_5:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_6:.*]] = dxsa.operand %[[INDEX_5]] {min_precision = 5 : i32, num_components = 4 : i32, one = 1 : i32, type = 0 : i32} +// CHECK: dxsa.instruction "iadd" %[[OPERAND_4]], %[[OPERAND_5]], %[[OPERAND_6]] +// CHECK: dxsa.instruction "ret" +