From f46e042558ff4fa7a475128444b518e53f0af984 Mon Sep 17 00:00:00 2001 From: Andrew Savonichev Date: Fri, 5 Jun 2026 23:57:27 +0900 Subject: [PATCH 1/2] [dxsa][mlir] Port LIT tests from dxilconv dxilconv tool has a LIT test suite that covers most instructions. These original tests are DXBC container binaries, but the current mlir-translate tool cannot translate from them directly - it needs only the content of SHEX section. The tests are generated by extracting shader binaries from DXBC containers. LIT checks are auto-generated by MLIR utils/generate-test-checks.py script. The checks reflect the current state of the compiler, and it is expected they will change once we enable more instructions. Tests in hlsl directory are from: https://github.com/microsoft/DirectXShaderCompiler/tree/main/projects/dxilconv/test/dxbc2dxil Tests in asm directory are from: https://github.com/microsoft/DirectXShaderCompiler/tree/main/projects/dxilconv/test/dxbc2dxil-asm --- mlir/test/Target/DXSA/asm/call2.test | 82 +++++ mlir/test/Target/DXSA/asm/cs3.test | 75 ++++ mlir/test/Target/DXSA/asm/cyclecounter.test | 28 ++ mlir/test/Target/DXSA/asm/hs3.test | 194 ++++++++++ mlir/test/Target/DXSA/asm/indexabletemp4.test | 63 ++++ mlir/test/Target/DXSA/asm/indexabletemp6.test | 72 ++++ mlir/test/Target/DXSA/asm/inputs/call2.bin | Bin 0 -> 356 bytes mlir/test/Target/DXSA/asm/inputs/cs3.bin | Bin 0 -> 324 bytes .../Target/DXSA/asm/inputs/cyclecounter.bin | Bin 0 -> 92 bytes mlir/test/Target/DXSA/asm/inputs/hs3.bin | Bin 0 -> 1300 bytes .../Target/DXSA/asm/inputs/indexabletemp4.bin | Bin 0 -> 260 bytes .../Target/DXSA/asm/inputs/indexabletemp6.bin | Bin 0 -> 372 bytes mlir/test/Target/DXSA/hlsl/abs1.test | 21 ++ mlir/test/Target/DXSA/hlsl/abs2.test | 23 ++ mlir/test/Target/DXSA/hlsl/atomics.test | 258 +++++++++++++ mlir/test/Target/DXSA/hlsl/bad_ftoi.test | 18 + mlir/test/Target/DXSA/hlsl/binary1.test | 24 ++ mlir/test/Target/DXSA/hlsl/bool1.test | 36 ++ mlir/test/Target/DXSA/hlsl/bool2.test | 26 ++ mlir/test/Target/DXSA/hlsl/bufinfo.test | 75 ++++ mlir/test/Target/DXSA/hlsl/calc_lod.test | 50 +++ mlir/test/Target/DXSA/hlsl/call1.test | 69 ++++ mlir/test/Target/DXSA/hlsl/call3.test | 105 ++++++ mlir/test/Target/DXSA/hlsl/cast1.test | 17 + mlir/test/Target/DXSA/hlsl/cast2.test | 17 + mlir/test/Target/DXSA/hlsl/cast3.test | 17 + mlir/test/Target/DXSA/hlsl/cast4.test | 17 + mlir/test/Target/DXSA/hlsl/cast5.test | 21 ++ mlir/test/Target/DXSA/hlsl/cast6.test | 21 ++ mlir/test/Target/DXSA/hlsl/cbuffer1.50.test | 22 ++ mlir/test/Target/DXSA/hlsl/cbuffer1.51.test | 23 ++ mlir/test/Target/DXSA/hlsl/cbuffer2.50.test | 22 ++ mlir/test/Target/DXSA/hlsl/cbuffer2.51.test | 23 ++ mlir/test/Target/DXSA/hlsl/cbuffer3.50.test | 40 ++ mlir/test/Target/DXSA/hlsl/cbuffer3.51.test | 52 +++ mlir/test/Target/DXSA/hlsl/cmp1.test | 18 + mlir/test/Target/DXSA/hlsl/constoperand1.test | 19 + mlir/test/Target/DXSA/hlsl/cs1.test | 53 +++ mlir/test/Target/DXSA/hlsl/cs2.test | 113 ++++++ mlir/test/Target/DXSA/hlsl/cs4.test | 120 ++++++ mlir/test/Target/DXSA/hlsl/cs5.test | 113 ++++++ mlir/test/Target/DXSA/hlsl/derivatives.test | 53 +++ mlir/test/Target/DXSA/hlsl/discard.test | 29 ++ mlir/test/Target/DXSA/hlsl/dot1.test | 23 ++ mlir/test/Target/DXSA/hlsl/double1.test | 59 +++ mlir/test/Target/DXSA/hlsl/double2.test | 65 ++++ mlir/test/Target/DXSA/hlsl/double3.test | 74 ++++ mlir/test/Target/DXSA/hlsl/double4.test | 55 +++ mlir/test/Target/DXSA/hlsl/double5.test | 104 ++++++ mlir/test/Target/DXSA/hlsl/double6.test | 175 +++++++++ mlir/test/Target/DXSA/hlsl/ds1.test | 68 ++++ mlir/test/Target/DXSA/hlsl/empty.test | 14 + mlir/test/Target/DXSA/hlsl/eval.test | 89 +++++ mlir/test/Target/DXSA/hlsl/f32f16.test | 22 ++ mlir/test/Target/DXSA/hlsl/gather.test | 51 +++ mlir/test/Target/DXSA/hlsl/gather_cmp.test | 51 +++ mlir/test/Target/DXSA/hlsl/gather_po.test | 87 +++++ mlir/test/Target/DXSA/hlsl/gather_po_cmp.test | 87 +++++ mlir/test/Target/DXSA/hlsl/getdim.test | 212 +++++++++++ mlir/test/Target/DXSA/hlsl/gs1.test | 63 ++++ mlir/test/Target/DXSA/hlsl/gs2.test | 152 ++++++++ mlir/test/Target/DXSA/hlsl/half_rcp.test | 26 ++ mlir/test/Target/DXSA/hlsl/hs1.test | 143 ++++++++ mlir/test/Target/DXSA/hlsl/hs2.test | 132 +++++++ mlir/test/Target/DXSA/hlsl/icb1.test | 32 ++ mlir/test/Target/DXSA/hlsl/if1.test | 36 ++ mlir/test/Target/DXSA/hlsl/if2.test | 34 ++ mlir/test/Target/DXSA/hlsl/if3.test | 26 ++ mlir/test/Target/DXSA/hlsl/if4.test | 32 ++ mlir/test/Target/DXSA/hlsl/if5.test | 36 ++ .../Target/DXSA/hlsl/indexableinput1.test | 31 ++ .../Target/DXSA/hlsl/indexableinput2.test | 41 +++ .../Target/DXSA/hlsl/indexableoutput1.test | 27 ++ .../test/Target/DXSA/hlsl/indexabletemp1.test | 100 +++++ .../test/Target/DXSA/hlsl/indexabletemp2.test | 123 +++++++ .../test/Target/DXSA/hlsl/indexabletemp3.test | 56 +++ .../test/Target/DXSA/hlsl/indexabletemp5.test | 56 +++ mlir/test/Target/DXSA/hlsl/input1.test | 52 +++ mlir/test/Target/DXSA/hlsl/input2.test | 52 +++ mlir/test/Target/DXSA/hlsl/input3.test | 23 ++ mlir/test/Target/DXSA/hlsl/inputs/abs1.bin | Bin 0 -> 64 bytes mlir/test/Target/DXSA/hlsl/inputs/abs2.bin | Bin 0 -> 72 bytes mlir/test/Target/DXSA/hlsl/inputs/atomics.bin | Bin 0 -> 1204 bytes .../test/Target/DXSA/hlsl/inputs/bad_ftoi.bin | Bin 0 -> 100 bytes mlir/test/Target/DXSA/hlsl/inputs/binary1.bin | Bin 0 -> 212 bytes mlir/test/Target/DXSA/hlsl/inputs/bool1.bin | Bin 0 -> 136 bytes mlir/test/Target/DXSA/hlsl/inputs/bool2.bin | Bin 0 -> 124 bytes mlir/test/Target/DXSA/hlsl/inputs/bufinfo.bin | Bin 0 -> 488 bytes .../test/Target/DXSA/hlsl/inputs/calc_lod.bin | Bin 0 -> 272 bytes mlir/test/Target/DXSA/hlsl/inputs/call1.bin | Bin 0 -> 280 bytes mlir/test/Target/DXSA/hlsl/inputs/call3.bin | Bin 0 -> 456 bytes mlir/test/Target/DXSA/hlsl/inputs/cast1.bin | Bin 0 -> 60 bytes mlir/test/Target/DXSA/hlsl/inputs/cast2.bin | Bin 0 -> 60 bytes mlir/test/Target/DXSA/hlsl/inputs/cast3.bin | Bin 0 -> 60 bytes mlir/test/Target/DXSA/hlsl/inputs/cast4.bin | Bin 0 -> 60 bytes mlir/test/Target/DXSA/hlsl/inputs/cast5.bin | Bin 0 -> 68 bytes mlir/test/Target/DXSA/hlsl/inputs/cast6.bin | Bin 0 -> 68 bytes .../Target/DXSA/hlsl/inputs/cbuffer1.50.bin | Bin 0 -> 68 bytes .../Target/DXSA/hlsl/inputs/cbuffer1.51.bin | Bin 0 -> 84 bytes .../Target/DXSA/hlsl/inputs/cbuffer2.50.bin | Bin 0 -> 68 bytes .../Target/DXSA/hlsl/inputs/cbuffer2.51.bin | Bin 0 -> 84 bytes .../Target/DXSA/hlsl/inputs/cbuffer3.50.bin | Bin 0 -> 156 bytes .../Target/DXSA/hlsl/inputs/cbuffer3.51.bin | Bin 0 -> 232 bytes mlir/test/Target/DXSA/hlsl/inputs/cmp1.bin | Bin 0 -> 80 bytes .../Target/DXSA/hlsl/inputs/constoperand1.bin | Bin 0 -> 64 bytes mlir/test/Target/DXSA/hlsl/inputs/cs1.bin | Bin 0 -> 308 bytes mlir/test/Target/DXSA/hlsl/inputs/cs2.bin | Bin 0 -> 736 bytes mlir/test/Target/DXSA/hlsl/inputs/cs4.bin | Bin 0 -> 728 bytes mlir/test/Target/DXSA/hlsl/inputs/cs5.bin | Bin 0 -> 736 bytes .../Target/DXSA/hlsl/inputs/derivatives.bin | Bin 0 -> 320 bytes mlir/test/Target/DXSA/hlsl/inputs/discard.bin | Bin 0 -> 160 bytes mlir/test/Target/DXSA/hlsl/inputs/dot1.bin | Bin 0 -> 200 bytes mlir/test/Target/DXSA/hlsl/inputs/double1.bin | Bin 0 -> 260 bytes mlir/test/Target/DXSA/hlsl/inputs/double2.bin | Bin 0 -> 296 bytes mlir/test/Target/DXSA/hlsl/inputs/double3.bin | Bin 0 -> 364 bytes mlir/test/Target/DXSA/hlsl/inputs/double4.bin | Bin 0 -> 216 bytes mlir/test/Target/DXSA/hlsl/inputs/double5.bin | Bin 0 -> 412 bytes mlir/test/Target/DXSA/hlsl/inputs/double6.bin | Bin 0 -> 876 bytes mlir/test/Target/DXSA/hlsl/inputs/ds1.bin | Bin 0 -> 752 bytes mlir/test/Target/DXSA/hlsl/inputs/empty.bin | Bin 0 -> 16 bytes mlir/test/Target/DXSA/hlsl/inputs/eval.bin | Bin 0 -> 584 bytes mlir/test/Target/DXSA/hlsl/inputs/f32f16.bin | Bin 0 -> 148 bytes mlir/test/Target/DXSA/hlsl/inputs/gather.bin | Bin 0 -> 680 bytes .../Target/DXSA/hlsl/inputs/gather_cmp.bin | Bin 0 -> 720 bytes .../Target/DXSA/hlsl/inputs/gather_po.bin | Bin 0 -> 1312 bytes .../Target/DXSA/hlsl/inputs/gather_po_cmp.bin | Bin 0 -> 1408 bytes mlir/test/Target/DXSA/hlsl/inputs/getdim.bin | Bin 0 -> 1296 bytes mlir/test/Target/DXSA/hlsl/inputs/gs1.bin | Bin 0 -> 524 bytes mlir/test/Target/DXSA/hlsl/inputs/gs2.bin | Bin 0 -> 848 bytes .../test/Target/DXSA/hlsl/inputs/half_rcp.bin | Bin 0 -> 112 bytes mlir/test/Target/DXSA/hlsl/inputs/hs1.bin | Bin 0 -> 996 bytes mlir/test/Target/DXSA/hlsl/inputs/hs2.bin | Bin 0 -> 1032 bytes mlir/test/Target/DXSA/hlsl/inputs/icb1.bin | Bin 0 -> 348 bytes mlir/test/Target/DXSA/hlsl/inputs/if1.bin | Bin 0 -> 156 bytes mlir/test/Target/DXSA/hlsl/inputs/if2.bin | Bin 0 -> 148 bytes mlir/test/Target/DXSA/hlsl/inputs/if3.bin | Bin 0 -> 164 bytes mlir/test/Target/DXSA/hlsl/inputs/if4.bin | Bin 0 -> 212 bytes mlir/test/Target/DXSA/hlsl/inputs/if5.bin | Bin 0 -> 228 bytes .../DXSA/hlsl/inputs/indexableinput1.bin | Bin 0 -> 220 bytes .../DXSA/hlsl/inputs/indexableinput2.bin | Bin 0 -> 312 bytes .../DXSA/hlsl/inputs/indexableoutput1.bin | Bin 0 -> 96 bytes .../DXSA/hlsl/inputs/indexabletemp1.bin | Bin 0 -> 404 bytes .../DXSA/hlsl/inputs/indexabletemp2.bin | Bin 0 -> 516 bytes .../DXSA/hlsl/inputs/indexabletemp3.bin | Bin 0 -> 228 bytes .../DXSA/hlsl/inputs/indexabletemp5.bin | Bin 0 -> 256 bytes mlir/test/Target/DXSA/hlsl/inputs/input1.bin | Bin 0 -> 788 bytes mlir/test/Target/DXSA/hlsl/inputs/input2.bin | Bin 0 -> 788 bytes mlir/test/Target/DXSA/hlsl/inputs/input3.bin | Bin 0 -> 180 bytes .../Target/DXSA/hlsl/inputs/interface1.bin | Bin 0 -> 576 bytes .../Target/DXSA/hlsl/inputs/liveness1.bin | Bin 0 -> 220 bytes mlir/test/Target/DXSA/hlsl/inputs/loop1.bin | Bin 0 -> 216 bytes mlir/test/Target/DXSA/hlsl/inputs/loop2.bin | Bin 0 -> 304 bytes mlir/test/Target/DXSA/hlsl/inputs/loop3.bin | Bin 0 -> 536 bytes mlir/test/Target/DXSA/hlsl/inputs/loop4.bin | Bin 0 -> 468 bytes mlir/test/Target/DXSA/hlsl/inputs/loop5.bin | Bin 0 -> 364 bytes .../test/Target/DXSA/hlsl/inputs/minprec1.bin | Bin 0 -> 112 bytes .../test/Target/DXSA/hlsl/inputs/minprec2.bin | Bin 0 -> 68 bytes .../test/Target/DXSA/hlsl/inputs/minprec3.bin | Bin 0 -> 188 bytes .../test/Target/DXSA/hlsl/inputs/minprec4.bin | Bin 0 -> 112 bytes .../test/Target/DXSA/hlsl/inputs/minprec5.bin | Bin 0 -> 76 bytes .../test/Target/DXSA/hlsl/inputs/minprec6.bin | Bin 0 -> 252 bytes .../test/Target/DXSA/hlsl/inputs/minprec7.bin | Bin 0 -> 104 bytes mlir/test/Target/DXSA/hlsl/inputs/neg1.bin | Bin 0 -> 64 bytes mlir/test/Target/DXSA/hlsl/inputs/neg2.bin | Bin 0 -> 60 bytes mlir/test/Target/DXSA/hlsl/inputs/negabs1.bin | Bin 0 -> 64 bytes .../Target/DXSA/hlsl/inputs/nonuniform1.bin | Bin 0 -> 360 bytes mlir/test/Target/DXSA/hlsl/inputs/output1.bin | Bin 0 -> 260 bytes mlir/test/Target/DXSA/hlsl/inputs/output2.bin | Bin 0 -> 164 bytes mlir/test/Target/DXSA/hlsl/inputs/output3.bin | Bin 0 -> 148 bytes mlir/test/Target/DXSA/hlsl/inputs/output4.bin | Bin 0 -> 188 bytes .../Target/DXSA/hlsl/inputs/passthrough1.bin | Bin 0 -> 64 bytes .../Target/DXSA/hlsl/inputs/passthrough2.bin | Bin 0 -> 60 bytes .../test/Target/DXSA/hlsl/inputs/precise1.bin | Bin 0 -> 236 bytes .../test/Target/DXSA/hlsl/inputs/raw_buf1.bin | Bin 0 -> 2312 bytes mlir/test/Target/DXSA/hlsl/inputs/rcp1.bin | Bin 0 -> 60 bytes .../DXSA/hlsl/inputs/redundantinput1.bin | Bin 0 -> 72 bytes mlir/test/Target/DXSA/hlsl/inputs/sample1.bin | Bin 0 -> 168 bytes mlir/test/Target/DXSA/hlsl/inputs/sample2.bin | Bin 0 -> 168 bytes mlir/test/Target/DXSA/hlsl/inputs/sample3.bin | Bin 0 -> 604 bytes .../Target/DXSA/hlsl/inputs/sample_b1.bin | Bin 0 -> 644 bytes .../Target/DXSA/hlsl/inputs/sample_cmp1.bin | Bin 0 -> 712 bytes .../Target/DXSA/hlsl/inputs/sample_cmp2.bin | Bin 0 -> 580 bytes .../Target/DXSA/hlsl/inputs/sample_grad1.bin | Bin 0 -> 684 bytes .../Target/DXSA/hlsl/inputs/sample_l1.bin | Bin 0 -> 840 bytes .../Target/DXSA/hlsl/inputs/samplecount.bin | Bin 0 -> 76 bytes .../Target/DXSA/hlsl/inputs/samplepos.bin | Bin 0 -> 432 bytes .../Target/DXSA/hlsl/inputs/saturate1.bin | Bin 0 -> 60 bytes mlir/test/Target/DXSA/hlsl/inputs/shift1.bin | Bin 0 -> 380 bytes mlir/test/Target/DXSA/hlsl/inputs/sincos.bin | Bin 0 -> 188 bytes mlir/test/Target/DXSA/hlsl/inputs/snorm1.bin | Bin 0 -> 208 bytes .../Target/DXSA/hlsl/inputs/srv_ms_load1.bin | Bin 0 -> 756 bytes .../DXSA/hlsl/inputs/srv_typed_load1.bin | Bin 0 -> 600 bytes .../DXSA/hlsl/inputs/srv_typed_load2.bin | Bin 0 -> 260 bytes .../Target/DXSA/hlsl/inputs/struct_buf1.bin | Bin 0 -> 4392 bytes mlir/test/Target/DXSA/hlsl/inputs/sub1.bin | Bin 0 -> 400 bytes mlir/test/Target/DXSA/hlsl/inputs/switch1.bin | Bin 0 -> 196 bytes mlir/test/Target/DXSA/hlsl/inputs/switch2.bin | Bin 0 -> 304 bytes mlir/test/Target/DXSA/hlsl/inputs/switch3.bin | Bin 0 -> 384 bytes .../test/Target/DXSA/hlsl/inputs/swizzle1.bin | Bin 0 -> 168 bytes mlir/test/Target/DXSA/hlsl/inputs/temp1.bin | Bin 0 -> 128 bytes mlir/test/Target/DXSA/hlsl/inputs/temp2.bin | Bin 0 -> 128 bytes .../DXSA/hlsl/inputs/uav_counter_dec.bin | Bin 0 -> 60 bytes .../DXSA/hlsl/inputs/uav_counter_inc.bin | Bin 0 -> 60 bytes .../test/Target/DXSA/hlsl/inputs/uav_raw1.bin | Bin 0 -> 324 bytes .../hlsl/inputs/uav_typed_load_store1.bin | Bin 0 -> 352 bytes .../hlsl/inputs/uav_typed_load_store2.bin | Bin 0 -> 456 bytes mlir/test/Target/DXSA/hlsl/inputs/ubfeu16.bin | Bin 0 -> 224 bytes mlir/test/Target/DXSA/hlsl/interface1.test | 88 +++++ mlir/test/Target/DXSA/hlsl/liveness1.test | 28 ++ mlir/test/Target/DXSA/hlsl/loop1.test | 40 ++ mlir/test/Target/DXSA/hlsl/loop2.test | 56 +++ mlir/test/Target/DXSA/hlsl/loop3.test | 101 +++++ mlir/test/Target/DXSA/hlsl/loop4.test | 88 +++++ mlir/test/Target/DXSA/hlsl/loop5.test | 65 ++++ mlir/test/Target/DXSA/hlsl/minprec1.test | 23 ++ mlir/test/Target/DXSA/hlsl/minprec2.test | 21 ++ mlir/test/Target/DXSA/hlsl/minprec3.test | 39 ++ mlir/test/Target/DXSA/hlsl/minprec4.test | 28 ++ mlir/test/Target/DXSA/hlsl/minprec5.test | 17 + mlir/test/Target/DXSA/hlsl/minprec6.test | 47 +++ mlir/test/Target/DXSA/hlsl/minprec7.test | 23 ++ mlir/test/Target/DXSA/hlsl/neg1.test | 21 ++ mlir/test/Target/DXSA/hlsl/neg2.test | 21 ++ mlir/test/Target/DXSA/hlsl/negabs1.test | 21 ++ mlir/test/Target/DXSA/hlsl/nonuniform1.test | 59 +++ mlir/test/Target/DXSA/hlsl/output1.test | 39 ++ mlir/test/Target/DXSA/hlsl/output2.test | 35 ++ mlir/test/Target/DXSA/hlsl/output3.test | 34 ++ mlir/test/Target/DXSA/hlsl/output4.test | 39 ++ mlir/test/Target/DXSA/hlsl/passthrough1.test | 21 ++ mlir/test/Target/DXSA/hlsl/passthrough2.test | 21 ++ mlir/test/Target/DXSA/hlsl/precise1.test | 28 ++ mlir/test/Target/DXSA/hlsl/raw_buf1.test | 161 ++++++++ mlir/test/Target/DXSA/hlsl/rcp1.test | 17 + .../Target/DXSA/hlsl/redundantinput1.test | 17 + mlir/test/Target/DXSA/hlsl/sample1.test | 22 ++ mlir/test/Target/DXSA/hlsl/sample2.test | 22 ++ mlir/test/Target/DXSA/hlsl/sample3.test | 42 +++ mlir/test/Target/DXSA/hlsl/sample_b1.test | 42 +++ mlir/test/Target/DXSA/hlsl/sample_cmp1.test | 45 +++ mlir/test/Target/DXSA/hlsl/sample_cmp2.test | 38 ++ mlir/test/Target/DXSA/hlsl/sample_grad1.test | 42 +++ mlir/test/Target/DXSA/hlsl/sample_l1.test | 49 +++ mlir/test/Target/DXSA/hlsl/samplecount.test | 23 ++ mlir/test/Target/DXSA/hlsl/samplepos.test | 51 +++ mlir/test/Target/DXSA/hlsl/saturate1.test | 21 ++ mlir/test/Target/DXSA/hlsl/shift1.test | 60 +++ mlir/test/Target/DXSA/hlsl/sincos.test | 22 ++ mlir/test/Target/DXSA/hlsl/snorm1.test | 23 ++ mlir/test/Target/DXSA/hlsl/srv_ms_load1.test | 63 ++++ .../Target/DXSA/hlsl/srv_typed_load1.test | 48 +++ .../Target/DXSA/hlsl/srv_typed_load2.test | 28 ++ mlir/test/Target/DXSA/hlsl/struct_buf1.test | 347 ++++++++++++++++++ mlir/test/Target/DXSA/hlsl/sub1.test | 91 +++++ mlir/test/Target/DXSA/hlsl/switch1.test | 48 +++ mlir/test/Target/DXSA/hlsl/switch2.test | 62 ++++ mlir/test/Target/DXSA/hlsl/switch3.test | 80 ++++ mlir/test/Target/DXSA/hlsl/swizzle1.test | 22 ++ mlir/test/Target/DXSA/hlsl/temp1.test | 20 + mlir/test/Target/DXSA/hlsl/temp2.test | 31 ++ .../Target/DXSA/hlsl/uav_counter_dec.test | 21 ++ .../Target/DXSA/hlsl/uav_counter_inc.test | 21 ++ mlir/test/Target/DXSA/hlsl/uav_raw1.test | 42 +++ .../DXSA/hlsl/uav_typed_load_store1.test | 42 +++ .../DXSA/hlsl/uav_typed_load_store2.test | 73 ++++ mlir/test/Target/DXSA/hlsl/ubfeu16.test | 34 ++ 266 files changed, 7311 insertions(+) create mode 100644 mlir/test/Target/DXSA/asm/call2.test create mode 100644 mlir/test/Target/DXSA/asm/cs3.test create mode 100644 mlir/test/Target/DXSA/asm/cyclecounter.test create mode 100644 mlir/test/Target/DXSA/asm/hs3.test create mode 100644 mlir/test/Target/DXSA/asm/indexabletemp4.test create mode 100644 mlir/test/Target/DXSA/asm/indexabletemp6.test create mode 100644 mlir/test/Target/DXSA/asm/inputs/call2.bin create mode 100644 mlir/test/Target/DXSA/asm/inputs/cs3.bin create mode 100644 mlir/test/Target/DXSA/asm/inputs/cyclecounter.bin create mode 100644 mlir/test/Target/DXSA/asm/inputs/hs3.bin create mode 100644 mlir/test/Target/DXSA/asm/inputs/indexabletemp4.bin create mode 100644 mlir/test/Target/DXSA/asm/inputs/indexabletemp6.bin create mode 100644 mlir/test/Target/DXSA/hlsl/abs1.test create mode 100644 mlir/test/Target/DXSA/hlsl/abs2.test create mode 100644 mlir/test/Target/DXSA/hlsl/atomics.test create mode 100644 mlir/test/Target/DXSA/hlsl/bad_ftoi.test create mode 100644 mlir/test/Target/DXSA/hlsl/binary1.test create mode 100644 mlir/test/Target/DXSA/hlsl/bool1.test create mode 100644 mlir/test/Target/DXSA/hlsl/bool2.test create mode 100644 mlir/test/Target/DXSA/hlsl/bufinfo.test create mode 100644 mlir/test/Target/DXSA/hlsl/calc_lod.test create mode 100644 mlir/test/Target/DXSA/hlsl/call1.test create mode 100644 mlir/test/Target/DXSA/hlsl/call3.test create mode 100644 mlir/test/Target/DXSA/hlsl/cast1.test create mode 100644 mlir/test/Target/DXSA/hlsl/cast2.test create mode 100644 mlir/test/Target/DXSA/hlsl/cast3.test create mode 100644 mlir/test/Target/DXSA/hlsl/cast4.test create mode 100644 mlir/test/Target/DXSA/hlsl/cast5.test create mode 100644 mlir/test/Target/DXSA/hlsl/cast6.test create mode 100644 mlir/test/Target/DXSA/hlsl/cbuffer1.50.test create mode 100644 mlir/test/Target/DXSA/hlsl/cbuffer1.51.test create mode 100644 mlir/test/Target/DXSA/hlsl/cbuffer2.50.test create mode 100644 mlir/test/Target/DXSA/hlsl/cbuffer2.51.test create mode 100644 mlir/test/Target/DXSA/hlsl/cbuffer3.50.test create mode 100644 mlir/test/Target/DXSA/hlsl/cbuffer3.51.test create mode 100644 mlir/test/Target/DXSA/hlsl/cmp1.test create mode 100644 mlir/test/Target/DXSA/hlsl/constoperand1.test create mode 100644 mlir/test/Target/DXSA/hlsl/cs1.test create mode 100644 mlir/test/Target/DXSA/hlsl/cs2.test create mode 100644 mlir/test/Target/DXSA/hlsl/cs4.test create mode 100644 mlir/test/Target/DXSA/hlsl/cs5.test create mode 100644 mlir/test/Target/DXSA/hlsl/derivatives.test create mode 100644 mlir/test/Target/DXSA/hlsl/discard.test create mode 100644 mlir/test/Target/DXSA/hlsl/dot1.test create mode 100644 mlir/test/Target/DXSA/hlsl/double1.test create mode 100644 mlir/test/Target/DXSA/hlsl/double2.test create mode 100644 mlir/test/Target/DXSA/hlsl/double3.test create mode 100644 mlir/test/Target/DXSA/hlsl/double4.test create mode 100644 mlir/test/Target/DXSA/hlsl/double5.test create mode 100644 mlir/test/Target/DXSA/hlsl/double6.test create mode 100644 mlir/test/Target/DXSA/hlsl/ds1.test create mode 100644 mlir/test/Target/DXSA/hlsl/empty.test create mode 100644 mlir/test/Target/DXSA/hlsl/eval.test create mode 100644 mlir/test/Target/DXSA/hlsl/f32f16.test create mode 100644 mlir/test/Target/DXSA/hlsl/gather.test create mode 100644 mlir/test/Target/DXSA/hlsl/gather_cmp.test create mode 100644 mlir/test/Target/DXSA/hlsl/gather_po.test create mode 100644 mlir/test/Target/DXSA/hlsl/gather_po_cmp.test create mode 100644 mlir/test/Target/DXSA/hlsl/getdim.test create mode 100644 mlir/test/Target/DXSA/hlsl/gs1.test create mode 100644 mlir/test/Target/DXSA/hlsl/gs2.test create mode 100644 mlir/test/Target/DXSA/hlsl/half_rcp.test create mode 100644 mlir/test/Target/DXSA/hlsl/hs1.test create mode 100644 mlir/test/Target/DXSA/hlsl/hs2.test create mode 100644 mlir/test/Target/DXSA/hlsl/icb1.test create mode 100644 mlir/test/Target/DXSA/hlsl/if1.test create mode 100644 mlir/test/Target/DXSA/hlsl/if2.test create mode 100644 mlir/test/Target/DXSA/hlsl/if3.test create mode 100644 mlir/test/Target/DXSA/hlsl/if4.test create mode 100644 mlir/test/Target/DXSA/hlsl/if5.test create mode 100644 mlir/test/Target/DXSA/hlsl/indexableinput1.test create mode 100644 mlir/test/Target/DXSA/hlsl/indexableinput2.test create mode 100644 mlir/test/Target/DXSA/hlsl/indexableoutput1.test create mode 100644 mlir/test/Target/DXSA/hlsl/indexabletemp1.test create mode 100644 mlir/test/Target/DXSA/hlsl/indexabletemp2.test create mode 100644 mlir/test/Target/DXSA/hlsl/indexabletemp3.test create mode 100644 mlir/test/Target/DXSA/hlsl/indexabletemp5.test create mode 100644 mlir/test/Target/DXSA/hlsl/input1.test create mode 100644 mlir/test/Target/DXSA/hlsl/input2.test create mode 100644 mlir/test/Target/DXSA/hlsl/input3.test create mode 100644 mlir/test/Target/DXSA/hlsl/inputs/abs1.bin create mode 100644 mlir/test/Target/DXSA/hlsl/inputs/abs2.bin create mode 100644 mlir/test/Target/DXSA/hlsl/inputs/atomics.bin create mode 100644 mlir/test/Target/DXSA/hlsl/inputs/bad_ftoi.bin create mode 100644 mlir/test/Target/DXSA/hlsl/inputs/binary1.bin create mode 100644 mlir/test/Target/DXSA/hlsl/inputs/bool1.bin create mode 100644 mlir/test/Target/DXSA/hlsl/inputs/bool2.bin create mode 100644 mlir/test/Target/DXSA/hlsl/inputs/bufinfo.bin create mode 100644 mlir/test/Target/DXSA/hlsl/inputs/calc_lod.bin create mode 100644 mlir/test/Target/DXSA/hlsl/inputs/call1.bin create mode 100644 mlir/test/Target/DXSA/hlsl/inputs/call3.bin create mode 100644 mlir/test/Target/DXSA/hlsl/inputs/cast1.bin create mode 100644 mlir/test/Target/DXSA/hlsl/inputs/cast2.bin create mode 100644 mlir/test/Target/DXSA/hlsl/inputs/cast3.bin create mode 100644 mlir/test/Target/DXSA/hlsl/inputs/cast4.bin create mode 100644 mlir/test/Target/DXSA/hlsl/inputs/cast5.bin create mode 100644 mlir/test/Target/DXSA/hlsl/inputs/cast6.bin create mode 100644 mlir/test/Target/DXSA/hlsl/inputs/cbuffer1.50.bin create mode 100644 mlir/test/Target/DXSA/hlsl/inputs/cbuffer1.51.bin create mode 100644 mlir/test/Target/DXSA/hlsl/inputs/cbuffer2.50.bin create mode 100644 mlir/test/Target/DXSA/hlsl/inputs/cbuffer2.51.bin create mode 100644 mlir/test/Target/DXSA/hlsl/inputs/cbuffer3.50.bin create mode 100644 mlir/test/Target/DXSA/hlsl/inputs/cbuffer3.51.bin create mode 100644 mlir/test/Target/DXSA/hlsl/inputs/cmp1.bin create mode 100644 mlir/test/Target/DXSA/hlsl/inputs/constoperand1.bin create mode 100644 mlir/test/Target/DXSA/hlsl/inputs/cs1.bin create mode 100644 mlir/test/Target/DXSA/hlsl/inputs/cs2.bin create mode 100644 mlir/test/Target/DXSA/hlsl/inputs/cs4.bin create mode 100644 mlir/test/Target/DXSA/hlsl/inputs/cs5.bin create mode 100644 mlir/test/Target/DXSA/hlsl/inputs/derivatives.bin create mode 100644 mlir/test/Target/DXSA/hlsl/inputs/discard.bin create mode 100644 mlir/test/Target/DXSA/hlsl/inputs/dot1.bin create mode 100644 mlir/test/Target/DXSA/hlsl/inputs/double1.bin create mode 100644 mlir/test/Target/DXSA/hlsl/inputs/double2.bin create mode 100644 mlir/test/Target/DXSA/hlsl/inputs/double3.bin create mode 100644 mlir/test/Target/DXSA/hlsl/inputs/double4.bin create mode 100644 mlir/test/Target/DXSA/hlsl/inputs/double5.bin create mode 100644 mlir/test/Target/DXSA/hlsl/inputs/double6.bin create mode 100644 mlir/test/Target/DXSA/hlsl/inputs/ds1.bin create mode 100644 mlir/test/Target/DXSA/hlsl/inputs/empty.bin create mode 100644 mlir/test/Target/DXSA/hlsl/inputs/eval.bin create mode 100644 mlir/test/Target/DXSA/hlsl/inputs/f32f16.bin create mode 100644 mlir/test/Target/DXSA/hlsl/inputs/gather.bin create mode 100644 mlir/test/Target/DXSA/hlsl/inputs/gather_cmp.bin create mode 100644 mlir/test/Target/DXSA/hlsl/inputs/gather_po.bin create mode 100644 mlir/test/Target/DXSA/hlsl/inputs/gather_po_cmp.bin create mode 100644 mlir/test/Target/DXSA/hlsl/inputs/getdim.bin create mode 100644 mlir/test/Target/DXSA/hlsl/inputs/gs1.bin create mode 100644 mlir/test/Target/DXSA/hlsl/inputs/gs2.bin create mode 100644 mlir/test/Target/DXSA/hlsl/inputs/half_rcp.bin create mode 100644 mlir/test/Target/DXSA/hlsl/inputs/hs1.bin create mode 100644 mlir/test/Target/DXSA/hlsl/inputs/hs2.bin create mode 100644 mlir/test/Target/DXSA/hlsl/inputs/icb1.bin create mode 100644 mlir/test/Target/DXSA/hlsl/inputs/if1.bin create mode 100644 mlir/test/Target/DXSA/hlsl/inputs/if2.bin create mode 100644 mlir/test/Target/DXSA/hlsl/inputs/if3.bin create mode 100644 mlir/test/Target/DXSA/hlsl/inputs/if4.bin create mode 100644 mlir/test/Target/DXSA/hlsl/inputs/if5.bin create mode 100644 mlir/test/Target/DXSA/hlsl/inputs/indexableinput1.bin create mode 100644 mlir/test/Target/DXSA/hlsl/inputs/indexableinput2.bin create mode 100644 mlir/test/Target/DXSA/hlsl/inputs/indexableoutput1.bin create mode 100644 mlir/test/Target/DXSA/hlsl/inputs/indexabletemp1.bin create mode 100644 mlir/test/Target/DXSA/hlsl/inputs/indexabletemp2.bin create mode 100644 mlir/test/Target/DXSA/hlsl/inputs/indexabletemp3.bin create mode 100644 mlir/test/Target/DXSA/hlsl/inputs/indexabletemp5.bin create mode 100644 mlir/test/Target/DXSA/hlsl/inputs/input1.bin create mode 100644 mlir/test/Target/DXSA/hlsl/inputs/input2.bin create mode 100644 mlir/test/Target/DXSA/hlsl/inputs/input3.bin create mode 100644 mlir/test/Target/DXSA/hlsl/inputs/interface1.bin create mode 100644 mlir/test/Target/DXSA/hlsl/inputs/liveness1.bin create mode 100644 mlir/test/Target/DXSA/hlsl/inputs/loop1.bin create mode 100644 mlir/test/Target/DXSA/hlsl/inputs/loop2.bin create mode 100644 mlir/test/Target/DXSA/hlsl/inputs/loop3.bin create mode 100644 mlir/test/Target/DXSA/hlsl/inputs/loop4.bin create mode 100644 mlir/test/Target/DXSA/hlsl/inputs/loop5.bin create mode 100644 mlir/test/Target/DXSA/hlsl/inputs/minprec1.bin create mode 100644 mlir/test/Target/DXSA/hlsl/inputs/minprec2.bin create mode 100644 mlir/test/Target/DXSA/hlsl/inputs/minprec3.bin create mode 100644 mlir/test/Target/DXSA/hlsl/inputs/minprec4.bin create mode 100644 mlir/test/Target/DXSA/hlsl/inputs/minprec5.bin create mode 100644 mlir/test/Target/DXSA/hlsl/inputs/minprec6.bin create mode 100644 mlir/test/Target/DXSA/hlsl/inputs/minprec7.bin create mode 100644 mlir/test/Target/DXSA/hlsl/inputs/neg1.bin create mode 100644 mlir/test/Target/DXSA/hlsl/inputs/neg2.bin create mode 100644 mlir/test/Target/DXSA/hlsl/inputs/negabs1.bin create mode 100644 mlir/test/Target/DXSA/hlsl/inputs/nonuniform1.bin create mode 100644 mlir/test/Target/DXSA/hlsl/inputs/output1.bin create mode 100644 mlir/test/Target/DXSA/hlsl/inputs/output2.bin create mode 100644 mlir/test/Target/DXSA/hlsl/inputs/output3.bin create mode 100644 mlir/test/Target/DXSA/hlsl/inputs/output4.bin create mode 100644 mlir/test/Target/DXSA/hlsl/inputs/passthrough1.bin create mode 100644 mlir/test/Target/DXSA/hlsl/inputs/passthrough2.bin create mode 100644 mlir/test/Target/DXSA/hlsl/inputs/precise1.bin create mode 100644 mlir/test/Target/DXSA/hlsl/inputs/raw_buf1.bin create mode 100644 mlir/test/Target/DXSA/hlsl/inputs/rcp1.bin create mode 100644 mlir/test/Target/DXSA/hlsl/inputs/redundantinput1.bin create mode 100644 mlir/test/Target/DXSA/hlsl/inputs/sample1.bin create mode 100644 mlir/test/Target/DXSA/hlsl/inputs/sample2.bin create mode 100644 mlir/test/Target/DXSA/hlsl/inputs/sample3.bin create mode 100644 mlir/test/Target/DXSA/hlsl/inputs/sample_b1.bin create mode 100644 mlir/test/Target/DXSA/hlsl/inputs/sample_cmp1.bin create mode 100644 mlir/test/Target/DXSA/hlsl/inputs/sample_cmp2.bin create mode 100644 mlir/test/Target/DXSA/hlsl/inputs/sample_grad1.bin create mode 100644 mlir/test/Target/DXSA/hlsl/inputs/sample_l1.bin create mode 100644 mlir/test/Target/DXSA/hlsl/inputs/samplecount.bin create mode 100644 mlir/test/Target/DXSA/hlsl/inputs/samplepos.bin create mode 100644 mlir/test/Target/DXSA/hlsl/inputs/saturate1.bin create mode 100644 mlir/test/Target/DXSA/hlsl/inputs/shift1.bin create mode 100644 mlir/test/Target/DXSA/hlsl/inputs/sincos.bin create mode 100644 mlir/test/Target/DXSA/hlsl/inputs/snorm1.bin create mode 100644 mlir/test/Target/DXSA/hlsl/inputs/srv_ms_load1.bin create mode 100644 mlir/test/Target/DXSA/hlsl/inputs/srv_typed_load1.bin create mode 100644 mlir/test/Target/DXSA/hlsl/inputs/srv_typed_load2.bin create mode 100644 mlir/test/Target/DXSA/hlsl/inputs/struct_buf1.bin create mode 100644 mlir/test/Target/DXSA/hlsl/inputs/sub1.bin create mode 100644 mlir/test/Target/DXSA/hlsl/inputs/switch1.bin create mode 100644 mlir/test/Target/DXSA/hlsl/inputs/switch2.bin create mode 100644 mlir/test/Target/DXSA/hlsl/inputs/switch3.bin create mode 100644 mlir/test/Target/DXSA/hlsl/inputs/swizzle1.bin create mode 100644 mlir/test/Target/DXSA/hlsl/inputs/temp1.bin create mode 100644 mlir/test/Target/DXSA/hlsl/inputs/temp2.bin create mode 100644 mlir/test/Target/DXSA/hlsl/inputs/uav_counter_dec.bin create mode 100644 mlir/test/Target/DXSA/hlsl/inputs/uav_counter_inc.bin create mode 100644 mlir/test/Target/DXSA/hlsl/inputs/uav_raw1.bin create mode 100644 mlir/test/Target/DXSA/hlsl/inputs/uav_typed_load_store1.bin create mode 100644 mlir/test/Target/DXSA/hlsl/inputs/uav_typed_load_store2.bin create mode 100644 mlir/test/Target/DXSA/hlsl/inputs/ubfeu16.bin create mode 100644 mlir/test/Target/DXSA/hlsl/interface1.test create mode 100644 mlir/test/Target/DXSA/hlsl/liveness1.test create mode 100644 mlir/test/Target/DXSA/hlsl/loop1.test create mode 100644 mlir/test/Target/DXSA/hlsl/loop2.test create mode 100644 mlir/test/Target/DXSA/hlsl/loop3.test create mode 100644 mlir/test/Target/DXSA/hlsl/loop4.test create mode 100644 mlir/test/Target/DXSA/hlsl/loop5.test create mode 100644 mlir/test/Target/DXSA/hlsl/minprec1.test create mode 100644 mlir/test/Target/DXSA/hlsl/minprec2.test create mode 100644 mlir/test/Target/DXSA/hlsl/minprec3.test create mode 100644 mlir/test/Target/DXSA/hlsl/minprec4.test create mode 100644 mlir/test/Target/DXSA/hlsl/minprec5.test create mode 100644 mlir/test/Target/DXSA/hlsl/minprec6.test create mode 100644 mlir/test/Target/DXSA/hlsl/minprec7.test create mode 100644 mlir/test/Target/DXSA/hlsl/neg1.test create mode 100644 mlir/test/Target/DXSA/hlsl/neg2.test create mode 100644 mlir/test/Target/DXSA/hlsl/negabs1.test create mode 100644 mlir/test/Target/DXSA/hlsl/nonuniform1.test create mode 100644 mlir/test/Target/DXSA/hlsl/output1.test create mode 100644 mlir/test/Target/DXSA/hlsl/output2.test create mode 100644 mlir/test/Target/DXSA/hlsl/output3.test create mode 100644 mlir/test/Target/DXSA/hlsl/output4.test create mode 100644 mlir/test/Target/DXSA/hlsl/passthrough1.test create mode 100644 mlir/test/Target/DXSA/hlsl/passthrough2.test create mode 100644 mlir/test/Target/DXSA/hlsl/precise1.test create mode 100644 mlir/test/Target/DXSA/hlsl/raw_buf1.test create mode 100644 mlir/test/Target/DXSA/hlsl/rcp1.test create mode 100644 mlir/test/Target/DXSA/hlsl/redundantinput1.test create mode 100644 mlir/test/Target/DXSA/hlsl/sample1.test create mode 100644 mlir/test/Target/DXSA/hlsl/sample2.test create mode 100644 mlir/test/Target/DXSA/hlsl/sample3.test create mode 100644 mlir/test/Target/DXSA/hlsl/sample_b1.test create mode 100644 mlir/test/Target/DXSA/hlsl/sample_cmp1.test create mode 100644 mlir/test/Target/DXSA/hlsl/sample_cmp2.test create mode 100644 mlir/test/Target/DXSA/hlsl/sample_grad1.test create mode 100644 mlir/test/Target/DXSA/hlsl/sample_l1.test create mode 100644 mlir/test/Target/DXSA/hlsl/samplecount.test create mode 100644 mlir/test/Target/DXSA/hlsl/samplepos.test create mode 100644 mlir/test/Target/DXSA/hlsl/saturate1.test create mode 100644 mlir/test/Target/DXSA/hlsl/shift1.test create mode 100644 mlir/test/Target/DXSA/hlsl/sincos.test create mode 100644 mlir/test/Target/DXSA/hlsl/snorm1.test create mode 100644 mlir/test/Target/DXSA/hlsl/srv_ms_load1.test create mode 100644 mlir/test/Target/DXSA/hlsl/srv_typed_load1.test create mode 100644 mlir/test/Target/DXSA/hlsl/srv_typed_load2.test create mode 100644 mlir/test/Target/DXSA/hlsl/struct_buf1.test create mode 100644 mlir/test/Target/DXSA/hlsl/sub1.test create mode 100644 mlir/test/Target/DXSA/hlsl/switch1.test create mode 100644 mlir/test/Target/DXSA/hlsl/switch2.test create mode 100644 mlir/test/Target/DXSA/hlsl/switch3.test create mode 100644 mlir/test/Target/DXSA/hlsl/swizzle1.test create mode 100644 mlir/test/Target/DXSA/hlsl/temp1.test create mode 100644 mlir/test/Target/DXSA/hlsl/temp2.test create mode 100644 mlir/test/Target/DXSA/hlsl/uav_counter_dec.test create mode 100644 mlir/test/Target/DXSA/hlsl/uav_counter_inc.test create mode 100644 mlir/test/Target/DXSA/hlsl/uav_raw1.test create mode 100644 mlir/test/Target/DXSA/hlsl/uav_typed_load_store1.test create mode 100644 mlir/test/Target/DXSA/hlsl/uav_typed_load_store2.test create mode 100644 mlir/test/Target/DXSA/hlsl/ubfeu16.test diff --git a/mlir/test/Target/DXSA/asm/call2.test b/mlir/test/Target/DXSA/asm/call2.test new file mode 100644 index 000000000000..6204c7f4d601 --- /dev/null +++ b/mlir/test/Target/DXSA/asm/call2.test @@ -0,0 +1,82 @@ +// RUN: mlir-translate --import-dxsa-bin %S/inputs/call2.bin | FileCheck %s +// NOTE: Assertions have been autogenerated by utils/generate-test-checks.py + +// This script is intended to make adding checks to a test case quick and easy. +// It is *not* authoritative about what constitutes a good test. After using the +// script, be sure to review and refine the generated checks. For example, +// CHECK lines should be minimized and named to reflect the test’s intent. +// For comprehensive guidelines, see: +// * https://mlir.llvm.org/getting_started/TestingGuide/ + + +// CHECK-LABEL: dxsa.dcl_global_flags +// CHECK: dxsa.dcl_input_ps linear v<0, > +// CHECK: dxsa.dcl_input_ps constant v<1, > +// CHECK: dxsa.dcl_output o<0, > +// CHECK: dxsa.dcl_temps 1 +// CHECK: %[[INDEX_0:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_0:.*]] = dxsa.operand %[[INDEX_0]] {mask = 112 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_1:.*]] = dxsa.index.imm {imm = 1 : i32} +// CHECK: %[[OPERAND_1:.*]] = dxsa.operand %[[INDEX_1]] {num_components = 4 : i32, swizzle = dense<[0, 1, 2, 2]> : vector<4xi32>, type = 1 : i32} +// CHECK: dxsa.instruction "mov" %[[OPERAND_0]], %[[OPERAND_1]] +// CHECK: %[[INDEX_2:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_2:.*]] = dxsa.operand %[[INDEX_2]] {num_components = 0 : i32, type = 10 : i32} +// CHECK: dxsa.instruction "call" %[[OPERAND_2]] +// CHECK: %[[INDEX_3:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_3:.*]] = dxsa.operand %[[INDEX_3]] {num_components = 4 : i32, one = 0 : i32, type = 0 : i32} +// CHECK: %[[INDEX_4:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_4:.*]] = dxsa.operand %[[INDEX_4]] {num_components = 0 : i32, type = 10 : i32} +// CHECK: dxsa.instruction "callc" %[[OPERAND_3]], %[[OPERAND_4]] +// CHECK: %[[INDEX_5:.*]] = dxsa.index.imm {imm = 1 : i32} +// CHECK: %[[OPERAND_5:.*]] = dxsa.operand %[[INDEX_5]] {num_components = 4 : i32, one = 0 : i32, type = 1 : i32} +// CHECK: dxsa.instruction "switch" %[[OPERAND_5]] +// CHECK: %[[OPERAND_6:.*]] = dxsa.operand.imm {imm = dense<1> : vector<1xi32>} +// CHECK: dxsa.instruction "case" %[[OPERAND_6]] +// CHECK: %[[INDEX_6:.*]] = dxsa.index.imm {imm = 2 : i32} +// CHECK: %[[OPERAND_7:.*]] = dxsa.operand %[[INDEX_6]] {num_components = 0 : i32, type = 10 : i32} +// CHECK: dxsa.instruction "call" %[[OPERAND_7]] +// CHECK: %[[INDEX_7:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_8:.*]] = dxsa.operand %[[INDEX_7]] {num_components = 4 : i32, one = 1 : i32, type = 0 : i32} +// CHECK: %[[INDEX_8:.*]] = dxsa.index.imm {imm = 1 : i32} +// CHECK: %[[OPERAND_9:.*]] = dxsa.operand %[[INDEX_8]] {num_components = 0 : i32, type = 10 : i32} +// CHECK: dxsa.instruction "callc" %[[OPERAND_8]], %[[OPERAND_9]] +// CHECK: dxsa.instruction "break" +// CHECK: dxsa.instruction "default" +// CHECK: %[[INDEX_9:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_10:.*]] = dxsa.operand %[[INDEX_9]] {num_components = 4 : i32, one = 2 : i32, type = 0 : i32} +// CHECK: %[[INDEX_10:.*]] = dxsa.index.imm {imm = 2 : i32} +// CHECK: %[[OPERAND_11:.*]] = dxsa.operand %[[INDEX_10]] {num_components = 0 : i32, type = 10 : i32} +// CHECK: dxsa.instruction "callc" %[[OPERAND_10]], %[[OPERAND_11]] +// CHECK: dxsa.instruction "break" +// CHECK: %[[OPERAND_12:.*]] = dxsa.operand.imm {imm = dense<2> : vector<1xi32>} +// CHECK: dxsa.instruction "case" %[[OPERAND_12]] +// CHECK: dxsa.instruction "break" +// CHECK: dxsa.instruction "endswitch" +// CHECK: dxsa.add o<0, >, r<0, >, l(0x3F800000) +// CHECK: dxsa.instruction "ret" +// CHECK: %[[INDEX_11:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_13:.*]] = dxsa.operand %[[INDEX_11]] {num_components = 0 : i32, type = 10 : i32} +// CHECK: dxsa.instruction "label" %[[OPERAND_13]] +// CHECK: %[[INDEX_12:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_14:.*]] = dxsa.operand %[[INDEX_12]] {mask = 16 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[OPERAND_15:.*]] = dxsa.operand.imm {imm = dense<1084227584> : vector<1xi32>} +// CHECK: dxsa.instruction "mov" %[[OPERAND_14]], %[[OPERAND_15]] +// CHECK: dxsa.instruction "ret" +// CHECK: %[[INDEX_13:.*]] = dxsa.index.imm {imm = 1 : i32} +// CHECK: %[[OPERAND_16:.*]] = dxsa.operand %[[INDEX_13]] {num_components = 0 : i32, type = 10 : i32} +// CHECK: dxsa.instruction "label" %[[OPERAND_16]] +// CHECK: %[[INDEX_14:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_17:.*]] = dxsa.operand %[[INDEX_14]] {mask = 16 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_15:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_18:.*]] = dxsa.operand %[[INDEX_15]] {num_components = 4 : i32, one = 0 : i32, type = 1 : i32} +// CHECK: dxsa.instruction "mov" %[[OPERAND_17]], %[[OPERAND_18]] +// CHECK: dxsa.instruction "ret" +// CHECK: %[[INDEX_16:.*]] = dxsa.index.imm {imm = 2 : i32} +// CHECK: %[[OPERAND_19:.*]] = dxsa.operand %[[INDEX_16]] {num_components = 0 : i32, type = 10 : i32} +// CHECK: dxsa.instruction "label" %[[OPERAND_19]] +// CHECK: %[[INDEX_17:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_20:.*]] = dxsa.operand %[[INDEX_17]] {mask = 16 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[OPERAND_21:.*]] = dxsa.operand.imm {imm = dense<1077936128> : vector<1xi32>} +// CHECK: dxsa.instruction "mov" %[[OPERAND_20]], %[[OPERAND_21]] +// CHECK: dxsa.instruction "ret" + diff --git a/mlir/test/Target/DXSA/asm/cs3.test b/mlir/test/Target/DXSA/asm/cs3.test new file mode 100644 index 000000000000..1942c5044224 --- /dev/null +++ b/mlir/test/Target/DXSA/asm/cs3.test @@ -0,0 +1,75 @@ +// RUN: mlir-translate --import-dxsa-bin %S/inputs/cs3.bin | FileCheck %s +// NOTE: Assertions have been autogenerated by utils/generate-test-checks.py + +// This script is intended to make adding checks to a test case quick and easy. +// It is *not* authoritative about what constitutes a good test. After using the +// script, be sure to review and refine the generated checks. For example, +// CHECK lines should be minimized and named to reflect the test’s intent. +// For comprehensive guidelines, see: +// * https://mlir.llvm.org/getting_started/TestingGuide/ + + +// CHECK-LABEL: dxsa.dcl_global_flags +// CHECK: dxsa.dcl_constant_buffer , +// CHECK: dxsa.dcl_input vThreadIDInGroup<> +// CHECK: dxsa.dcl_temps 3 +// CHECK: dxsa.dcl_tgsm_raw g<0>, 1024 +// CHECK: dxsa.dcl_thread_group +// CHECK: dxsa.ishl r<0, >, vThreadIDInGroup<>, l(0x2) +// CHECK: %[[INDEX_0:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_0:.*]] = dxsa.operand %[[INDEX_0]] {mask = 48 : i32, num_components = 4 : i32, type = 31 : i32} +// CHECK: %[[INDEX_1:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_1:.*]] = dxsa.operand %[[INDEX_1]] {num_components = 4 : i32, one = 0 : i32, type = 0 : i32} +// CHECK: %[[INDEX_2:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[INDEX_3:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_2:.*]] = dxsa.operand %[[INDEX_2]], %[[INDEX_3]] {num_components = 4 : i32, swizzle = dense<[3, 2, 1, 0]> : vector<4xi32>, type = 8 : i32} +// CHECK: dxsa.instruction "store_raw" %[[OPERAND_0]], %[[OPERAND_1]], %[[OPERAND_2]] +// CHECK: dxsa.instruction "sync" +// CHECK: dxsa.instruction "sync" +// CHECK: dxsa.instruction "sync" +// CHECK: dxsa.instruction "sync" +// CHECK: dxsa.instruction "sync" +// CHECK: dxsa.instruction "sync" +// CHECK: dxsa.instruction "sync" +// CHECK: dxsa.instruction "sync" +// CHECK: dxsa.instruction "sync" +// CHECK: dxsa.instruction "sync" +// CHECK: %[[INDEX_4:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_3:.*]] = dxsa.operand %[[INDEX_4]] {mask = 80 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_5:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_4:.*]] = dxsa.operand %[[INDEX_5]] {num_components = 4 : i32, one = 0 : i32, type = 0 : i32} +// CHECK: %[[INDEX_6:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_5:.*]] = dxsa.operand %[[INDEX_6]] {num_components = 4 : i32, swizzle = dense<[2, 0, 3, 1]> : vector<4xi32>, type = 31 : i32} +// CHECK: dxsa.instruction "ld_raw" %[[OPERAND_3]], %[[OPERAND_4]], %[[OPERAND_5]] +// CHECK: %[[INDEX_7:.*]] = dxsa.index.imm {imm = 2 : i32} +// CHECK: %[[OPERAND_6:.*]] = dxsa.operand %[[INDEX_7]] {mask = 16 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_8:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_7:.*]] = dxsa.operand %[[INDEX_8]] {num_components = 0 : i32, type = 31 : i32} +// CHECK: %[[INDEX_9:.*]] = dxsa.index.imm {imm = 1 : i32} +// CHECK: %[[OPERAND_8:.*]] = dxsa.operand %[[INDEX_9]] {num_components = 4 : i32, swizzle = dense<[0, 1, 0, 0]> : vector<4xi32>, type = 0 : i32} +// CHECK: %[[OPERAND_9:.*]] = dxsa.operand {num_components = 4 : i32, one = 0 : i32, type = 34 : i32} +// CHECK: dxsa.instruction "imm_atomic_iadd" %[[OPERAND_6]], %[[OPERAND_7]], %[[OPERAND_8]], %[[OPERAND_9]] +// CHECK: %[[INDEX_10:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_10:.*]] = dxsa.operand %[[INDEX_10]] {num_components = 0 : i32, type = 31 : i32} +// CHECK: %[[INDEX_11:.*]] = dxsa.index.imm {imm = 1 : i32} +// CHECK: %[[OPERAND_11:.*]] = dxsa.operand %[[INDEX_11]] {num_components = 4 : i32, swizzle = dense<[0, 1, 0, 0]> : vector<4xi32>, type = 0 : i32} +// CHECK: %[[OPERAND_12:.*]] = dxsa.operand {num_components = 4 : i32, one = 0 : i32, type = 34 : i32} +// CHECK: dxsa.instruction "atomic_or" %[[OPERAND_10]], %[[OPERAND_11]], %[[OPERAND_12]] +// CHECK: %[[INDEX_12:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_13:.*]] = dxsa.operand %[[INDEX_12]] {num_components = 0 : i32, type = 31 : i32} +// CHECK: %[[INDEX_13:.*]] = dxsa.index.imm {imm = 1 : i32} +// CHECK: %[[OPERAND_14:.*]] = dxsa.operand %[[INDEX_13]] {num_components = 4 : i32, swizzle = dense<[0, 1, 0, 0]> : vector<4xi32>, type = 0 : i32} +// CHECK: %[[OPERAND_15:.*]] = dxsa.operand {num_components = 4 : i32, one = 1 : i32, type = 34 : i32} +// CHECK: %[[OPERAND_16:.*]] = dxsa.operand {num_components = 4 : i32, one = 0 : i32, type = 34 : i32} +// CHECK: dxsa.instruction "atomic_cmp_store" %[[OPERAND_13]], %[[OPERAND_14]], %[[OPERAND_15]], %[[OPERAND_16]] +// CHECK: %[[INDEX_14:.*]] = dxsa.index.imm {imm = 1 : i32} +// CHECK: %[[OPERAND_17:.*]] = dxsa.operand %[[INDEX_14]] {mask = 16 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_15:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_18:.*]] = dxsa.operand %[[INDEX_15]] {num_components = 0 : i32, type = 31 : i32} +// CHECK: %[[INDEX_16:.*]] = dxsa.index.imm {imm = 1 : i32} +// CHECK: %[[OPERAND_19:.*]] = dxsa.operand %[[INDEX_16]] {num_components = 4 : i32, swizzle = dense<[0, 1, 0, 0]> : vector<4xi32>, type = 0 : i32} +// CHECK: %[[OPERAND_20:.*]] = dxsa.operand {num_components = 4 : i32, one = 1 : i32, type = 34 : i32} +// CHECK: %[[OPERAND_21:.*]] = dxsa.operand {num_components = 4 : i32, one = 0 : i32, type = 34 : i32} +// CHECK: dxsa.instruction "imm_atomic_cmp_exch" %[[OPERAND_17]], %[[OPERAND_18]], %[[OPERAND_19]], %[[OPERAND_20]], %[[OPERAND_21]] +// CHECK: dxsa.instruction "ret" + diff --git a/mlir/test/Target/DXSA/asm/cyclecounter.test b/mlir/test/Target/DXSA/asm/cyclecounter.test new file mode 100644 index 000000000000..308e5a316157 --- /dev/null +++ b/mlir/test/Target/DXSA/asm/cyclecounter.test @@ -0,0 +1,28 @@ +// RUN: mlir-translate --import-dxsa-bin %S/inputs/cyclecounter.bin | FileCheck %s +// NOTE: Assertions have been autogenerated by utils/generate-test-checks.py + +// This script is intended to make adding checks to a test case quick and easy. +// It is *not* authoritative about what constitutes a good test. After using the +// script, be sure to review and refine the generated checks. For example, +// CHECK lines should be minimized and named to reflect the test’s intent. +// For comprehensive guidelines, see: +// * https://mlir.llvm.org/getting_started/TestingGuide/ + + +// CHECK-LABEL: dxsa.dcl_temps 1 +// CHECK: dxsa.dcl_output o<0> +// CHECK: dxsa.dcl_input cycleCounter<> +// CHECK: %[[INDEX_0:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_0:.*]] = dxsa.operand %[[INDEX_0]] {mask = 240 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[OPERAND_1:.*]] = dxsa.operand.imm {imm = dense<0> : vector<1xi32>} +// CHECK: dxsa.instruction "mov" %[[OPERAND_0]], %[[OPERAND_1]] +// CHECK: %[[INDEX_1:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_2:.*]] = dxsa.operand %[[INDEX_1]] {mask = 64 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[OPERAND_3:.*]] = dxsa.operand {num_components = 4 : i32, one = 0 : i32, type = 40 : i32} +// CHECK: dxsa.instruction "mov" %[[OPERAND_2]], %[[OPERAND_3]] +// CHECK: %[[INDEX_2:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_4:.*]] = dxsa.operand %[[INDEX_2]] {mask = 240 : i32, num_components = 4 : i32, type = 2 : i32} +// CHECK: %[[INDEX_3:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_5:.*]] = dxsa.operand %[[INDEX_3]] {num_components = 4 : i32, swizzle = dense<[0, 1, 2, 3]> : vector<4xi32>, type = 0 : i32} +// CHECK: dxsa.instruction "mov" %[[OPERAND_4]], %[[OPERAND_5]] + diff --git a/mlir/test/Target/DXSA/asm/hs3.test b/mlir/test/Target/DXSA/asm/hs3.test new file mode 100644 index 000000000000..38bf63bc5154 --- /dev/null +++ b/mlir/test/Target/DXSA/asm/hs3.test @@ -0,0 +1,194 @@ +// RUN: mlir-translate --import-dxsa-bin %S/inputs/hs3.bin | FileCheck %s +// NOTE: Assertions have been autogenerated by utils/generate-test-checks.py + +// This script is intended to make adding checks to a test case quick and easy. +// It is *not* authoritative about what constitutes a good test. After using the +// script, be sure to review and refine the generated checks. For example, +// CHECK lines should be minimized and named to reflect the test’s intent. +// For comprehensive guidelines, see: +// * https://mlir.llvm.org/getting_started/TestingGuide/ + + +// CHECK-LABEL: dxsa.instruction "hs_decls" +// CHECK: dxsa.dcl_input_control_point_count 4 +// CHECK: dxsa.dcl_output_control_point_count 32 +// CHECK: dxsa.dcl_tessellator_domain domain_quad +// CHECK: dxsa.dcl_tessellator_partitioning partitioning_fractional_odd +// CHECK: dxsa.dcl_tessellator_output_primitive output_triangle_cw +// CHECK: dxsa.dcl_hs_max_tessfactor 6.400000e+01 +// CHECK: dxsa.instruction "hs_control_point_phase" +// CHECK: dxsa.dcl_input v<[4, 0]> +// CHECK: dxsa.dcl_input v<[4, 1], > +// CHECK: dxsa.dcl_input v<[4, 2], > +// CHECK: dxsa.dcl_input vOutputControlPointID +// CHECK: dxsa.dcl_input vPrim +// CHECK: dxsa.dcl_output o<0> +// CHECK: dxsa.dcl_output o<1, > +// CHECK: dxsa.dcl_output o<2, > +// CHECK: dxsa.dcl_temps 1 +// CHECK: %[[OPERAND_0:.*]] = dxsa.operand {num_components = 0 : i32, type = 13 : i32} +// CHECK: %[[INDEX_0:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_1:.*]] = dxsa.operand %[[INDEX_0]] {mask = 16 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[OPERAND_2:.*]] = dxsa.operand {num_components = 1 : i32, type = 22 : i32} +// CHECK: %[[OPERAND_3:.*]] = dxsa.operand.imm {imm = dense<4> : vector<1xi32>} +// CHECK: dxsa.instruction "udiv" %[[OPERAND_0]], %[[OPERAND_1]], %[[OPERAND_2]], %[[OPERAND_3]] +// CHECK: %[[INDEX_1:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_4:.*]] = dxsa.operand %[[INDEX_1]] {mask = 240 : i32, num_components = 4 : i32, type = 2 : i32} +// CHECK: %[[INDEX_2:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_5:.*]] = dxsa.operand %[[INDEX_2]] {num_components = 4 : i32, one = 0 : i32, type = 0 : i32} +// CHECK: %[[INDEX_3:.*]] = dxsa.index.rel %[[OPERAND_5]] +// CHECK: %[[INDEX_4:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_6:.*]] = dxsa.operand %[[INDEX_3]], %[[INDEX_4]] {num_components = 4 : i32, swizzle = dense<[0, 1, 2, 3]> : vector<4xi32>, type = 1 : i32} +// CHECK: dxsa.instruction "mov" %[[OPERAND_4]], %[[OPERAND_6]] +// CHECK: %[[INDEX_5:.*]] = dxsa.index.imm {imm = 1 : i32} +// CHECK: %[[OPERAND_7:.*]] = dxsa.operand %[[INDEX_5]] {mask = 48 : i32, num_components = 4 : i32, type = 2 : i32} +// CHECK: %[[INDEX_6:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_8:.*]] = dxsa.operand %[[INDEX_6]] {num_components = 4 : i32, one = 0 : i32, type = 0 : i32} +// CHECK: %[[INDEX_7:.*]] = dxsa.index.rel %[[OPERAND_8]] +// CHECK: %[[INDEX_8:.*]] = dxsa.index.imm {imm = 1 : i32} +// CHECK: %[[OPERAND_9:.*]] = dxsa.operand %[[INDEX_7]], %[[INDEX_8]] {num_components = 4 : i32, swizzle = dense<[0, 1, 0, 0]> : vector<4xi32>, type = 1 : i32} +// CHECK: dxsa.instruction "mov" %[[OPERAND_7]], %[[OPERAND_9]] +// CHECK: %[[INDEX_9:.*]] = dxsa.index.imm {imm = 2 : i32} +// CHECK: %[[OPERAND_10:.*]] = dxsa.operand %[[INDEX_9]] {mask = 112 : i32, num_components = 4 : i32, type = 2 : i32} +// CHECK: %[[INDEX_10:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_11:.*]] = dxsa.operand %[[INDEX_10]] {num_components = 4 : i32, one = 0 : i32, type = 0 : i32} +// CHECK: %[[INDEX_11:.*]] = dxsa.index.rel %[[OPERAND_11]] +// CHECK: %[[INDEX_12:.*]] = dxsa.index.imm {imm = 2 : i32} +// CHECK: %[[OPERAND_12:.*]] = dxsa.operand %[[INDEX_11]], %[[INDEX_12]] {num_components = 4 : i32, swizzle = dense<[0, 1, 2, 0]> : vector<4xi32>, type = 1 : i32} +// CHECK: dxsa.instruction "mov" %[[OPERAND_10]], %[[OPERAND_12]] +// CHECK: dxsa.instruction "hs_fork_phase" +// CHECK: dxsa.dcl_input vicp<[4, 0]> +// CHECK: dxsa.dcl_input vicp<[4, 1], > +// CHECK: dxsa.dcl_input vicp<[4, 2], > +// CHECK: dxsa.dcl_input vocp<[32, 0]> +// CHECK: dxsa.dcl_input vocp<[32, 1], > +// CHECK: dxsa.dcl_input vocp<[32, 2], > +// CHECK: dxsa.dcl_hs_fork_phase_instance_count 4 +// CHECK: dxsa.dcl_input vForkInstanceID +// CHECK: dxsa.dcl_input vPrim +// CHECK: dxsa.dcl_index_range o<0>, 4 +// CHECK: dxsa.dcl_temps 1 +// CHECK: dxsa.dcl_indexable_temp x<0>[4], 1 +// CHECK: dxsa.dcl_output_siv o<0, >, +// CHECK: dxsa.dcl_output_siv o<1, >, +// CHECK: dxsa.dcl_output_siv o<2, >, +// CHECK: dxsa.dcl_output_siv o<3, >, +// CHECK: %[[INDEX_13:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[INDEX_14:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_13:.*]] = dxsa.operand %[[INDEX_13]], %[[INDEX_14]] {mask = 16 : i32, num_components = 4 : i32, type = 3 : i32} +// CHECK: %[[OPERAND_14:.*]] = dxsa.operand.imm {imm = dense<1073741824> : vector<1xi32>} +// CHECK: dxsa.instruction "mov" %[[OPERAND_13]], %[[OPERAND_14]] +// CHECK: %[[INDEX_15:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[INDEX_16:.*]] = dxsa.index.imm {imm = 1 : i32} +// CHECK: %[[OPERAND_15:.*]] = dxsa.operand %[[INDEX_15]], %[[INDEX_16]] {mask = 16 : i32, num_components = 4 : i32, type = 3 : i32} +// CHECK: %[[OPERAND_16:.*]] = dxsa.operand.imm {imm = dense<1082130432> : vector<1xi32>} +// CHECK: dxsa.instruction "mov" %[[OPERAND_15]], %[[OPERAND_16]] +// CHECK: %[[INDEX_17:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[INDEX_18:.*]] = dxsa.index.imm {imm = 2 : i32} +// CHECK: %[[OPERAND_17:.*]] = dxsa.operand %[[INDEX_17]], %[[INDEX_18]] {mask = 16 : i32, num_components = 4 : i32, type = 3 : i32} +// CHECK: %[[OPERAND_18:.*]] = dxsa.operand.imm {imm = dense<1097859072> : vector<1xi32>} +// CHECK: dxsa.instruction "mov" %[[OPERAND_17]], %[[OPERAND_18]] +// CHECK: %[[INDEX_19:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[INDEX_20:.*]] = dxsa.index.imm {imm = 3 : i32} +// CHECK: %[[OPERAND_19:.*]] = dxsa.operand %[[INDEX_19]], %[[INDEX_20]] {mask = 16 : i32, num_components = 4 : i32, type = 3 : i32} +// CHECK: %[[OPERAND_20:.*]] = dxsa.operand.imm {imm = dense<1086324736> : vector<1xi32>} +// CHECK: dxsa.instruction "mov" %[[OPERAND_19]], %[[OPERAND_20]] +// CHECK: %[[INDEX_21:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_21:.*]] = dxsa.operand %[[INDEX_21]] {mask = 16 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[OPERAND_22:.*]] = dxsa.operand {num_components = 0 : i32, type = 23 : i32} +// CHECK: dxsa.instruction "mov" %[[OPERAND_21]], %[[OPERAND_22]] +// CHECK: %[[INDEX_22:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_23:.*]] = dxsa.operand %[[INDEX_22]] {num_components = 4 : i32, one = 0 : i32, type = 0 : i32} +// CHECK: %[[INDEX_23:.*]] = dxsa.index.rel %[[OPERAND_23]] +// CHECK: %[[OPERAND_24:.*]] = dxsa.operand %[[INDEX_23]] {mask = 16 : i32, num_components = 4 : i32, type = 2 : i32} +// CHECK: %[[INDEX_24:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[INDEX_25:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_25:.*]] = dxsa.operand %[[INDEX_25]] {num_components = 4 : i32, one = 0 : i32, type = 0 : i32} +// CHECK: %[[INDEX_26:.*]] = dxsa.index.rel %[[OPERAND_25]] +// CHECK: %[[OPERAND_26:.*]] = dxsa.operand %[[INDEX_24]], %[[INDEX_26]] {num_components = 4 : i32, one = 0 : i32, type = 3 : i32} +// CHECK: dxsa.instruction "mov" %[[OPERAND_24]], %[[OPERAND_26]] +// CHECK: dxsa.instruction "hs_fork_phase" +// CHECK: dxsa.dcl_input vicp<[4, 0]> +// CHECK: dxsa.dcl_input vicp<[4, 1], > +// CHECK: dxsa.dcl_input vicp<[4, 2], > +// CHECK: dxsa.dcl_input vocp<[32, 0]> +// CHECK: dxsa.dcl_input vocp<[32, 1], > +// CHECK: dxsa.dcl_input vocp<[32, 2], > +// CHECK: dxsa.dcl_hs_fork_phase_instance_count 4 +// CHECK: dxsa.dcl_input vForkInstanceID +// CHECK: dxsa.dcl_input vPrim +// CHECK: dxsa.dcl_index_range o<0>, 4 +// CHECK: dxsa.dcl_temps 1 +// CHECK: dxsa.dcl_indexable_temp x<0>[4], 1 +// CHECK: dxsa.dcl_output o<0, > +// CHECK: dxsa.dcl_output o<1, > +// CHECK: dxsa.dcl_output o<2, > +// CHECK: dxsa.dcl_output o<3, > +// CHECK: %[[INDEX_27:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[INDEX_28:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_27:.*]] = dxsa.operand %[[INDEX_27]], %[[INDEX_28]] {mask = 16 : i32, num_components = 4 : i32, type = 3 : i32} +// CHECK: %[[OPERAND_28:.*]] = dxsa.operand.imm {imm = dense<1094713344> : vector<1xi32>} +// CHECK: dxsa.instruction "mov" %[[OPERAND_27]], %[[OPERAND_28]] +// CHECK: %[[INDEX_29:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[INDEX_30:.*]] = dxsa.index.imm {imm = 1 : i32} +// CHECK: %[[OPERAND_29:.*]] = dxsa.operand %[[INDEX_29]], %[[INDEX_30]] {mask = 16 : i32, num_components = 4 : i32, type = 3 : i32} +// CHECK: %[[OPERAND_30:.*]] = dxsa.operand.imm {imm = dense<1107296256> : vector<1xi32>} +// CHECK: dxsa.instruction "mov" %[[OPERAND_29]], %[[OPERAND_30]] +// CHECK: %[[INDEX_31:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[INDEX_32:.*]] = dxsa.index.imm {imm = 2 : i32} +// CHECK: %[[OPERAND_31:.*]] = dxsa.operand %[[INDEX_31]], %[[INDEX_32]] {mask = 16 : i32, num_components = 4 : i32, type = 3 : i32} +// CHECK: %[[OPERAND_32:.*]] = dxsa.operand.imm {imm = dense<1097859072> : vector<1xi32>} +// CHECK: dxsa.instruction "mov" %[[OPERAND_31]], %[[OPERAND_32]] +// CHECK: %[[INDEX_33:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[INDEX_34:.*]] = dxsa.index.imm {imm = 3 : i32} +// CHECK: %[[OPERAND_33:.*]] = dxsa.operand %[[INDEX_33]], %[[INDEX_34]] {mask = 16 : i32, num_components = 4 : i32, type = 3 : i32} +// CHECK: %[[OPERAND_34:.*]] = dxsa.operand.imm {imm = dense<1084227584> : vector<1xi32>} +// CHECK: dxsa.instruction "mov" %[[OPERAND_33]], %[[OPERAND_34]] +// CHECK: %[[INDEX_35:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_35:.*]] = dxsa.operand %[[INDEX_35]] {mask = 16 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[OPERAND_36:.*]] = dxsa.operand {num_components = 0 : i32, type = 23 : i32} +// CHECK: dxsa.instruction "mov" %[[OPERAND_35]], %[[OPERAND_36]] +// CHECK: %[[INDEX_36:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_37:.*]] = dxsa.operand %[[INDEX_36]] {num_components = 4 : i32, one = 0 : i32, type = 0 : i32} +// CHECK: %[[INDEX_37:.*]] = dxsa.index.rel %[[OPERAND_37]] +// CHECK: %[[OPERAND_38:.*]] = dxsa.operand %[[INDEX_37]] {mask = 32 : i32, num_components = 4 : i32, type = 2 : i32} +// CHECK: %[[INDEX_38:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[INDEX_39:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_39:.*]] = dxsa.operand %[[INDEX_39]] {num_components = 4 : i32, one = 0 : i32, type = 0 : i32} +// CHECK: %[[INDEX_40:.*]] = dxsa.index.rel %[[OPERAND_39]] +// CHECK: %[[OPERAND_40:.*]] = dxsa.operand %[[INDEX_38]], %[[INDEX_40]] {num_components = 4 : i32, one = 0 : i32, type = 3 : i32} +// CHECK: dxsa.instruction "mov" %[[OPERAND_38]], %[[OPERAND_40]] +// CHECK: dxsa.instruction "hs_join_phase" +// CHECK: dxsa.dcl_input vicp<[4, 0]> +// CHECK: dxsa.dcl_input vicp<[4, 1], > +// CHECK: dxsa.dcl_input vicp<[4, 2], > +// CHECK: dxsa.dcl_input vocp<[32, 0]> +// CHECK: dxsa.dcl_input vocp<[32, 1], > +// CHECK: dxsa.dcl_input vocp<[32, 2], > +// CHECK: dxsa.dcl_input vpc<0, > +// CHECK: dxsa.dcl_input vpc<1, > +// CHECK: dxsa.dcl_input vpc<2, > +// CHECK: dxsa.dcl_input vpc<3, > +// CHECK: dxsa.dcl_index_range vpc<0>, 4 +// CHECK: dxsa.dcl_output_siv o<4, >, +// CHECK: dxsa.dcl_output_siv o<5, >, +// CHECK: dxsa.dcl_output o<4, > +// CHECK: dxsa.dcl_output o<5, > +// CHECK: dxsa.dcl_input vPrim +// CHECK: %[[INDEX_41:.*]] = dxsa.index.imm {imm = 4 : i32} +// CHECK: %[[OPERAND_41:.*]] = dxsa.operand %[[INDEX_41]] {mask = 16 : i32, num_components = 4 : i32, type = 2 : i32} +// CHECK: %[[OPERAND_42:.*]] = dxsa.operand.imm {imm = dense<1094713344> : vector<1xi32>} +// CHECK: dxsa.instruction "mov" %[[OPERAND_41]], %[[OPERAND_42]] +// CHECK: %[[INDEX_42:.*]] = dxsa.index.imm {imm = 5 : i32} +// CHECK: %[[OPERAND_43:.*]] = dxsa.operand %[[INDEX_42]] {mask = 16 : i32, num_components = 4 : i32, type = 2 : i32} +// CHECK: %[[OPERAND_44:.*]] = dxsa.operand.imm {imm = dense<1086324736> : vector<1xi32>} +// CHECK: dxsa.instruction "mov" %[[OPERAND_43]], %[[OPERAND_44]] +// CHECK: %[[INDEX_43:.*]] = dxsa.index.imm {imm = 4 : i32} +// CHECK: %[[OPERAND_45:.*]] = dxsa.operand %[[INDEX_43]] {mask = 32 : i32, num_components = 4 : i32, type = 2 : i32} +// CHECK: %[[OPERAND_46:.*]] = dxsa.operand.imm {imm = dense<0> : vector<1xi32>} +// CHECK: dxsa.instruction "mov" %[[OPERAND_45]], %[[OPERAND_46]] +// CHECK: %[[INDEX_44:.*]] = dxsa.index.imm {imm = 5 : i32} +// CHECK: %[[OPERAND_47:.*]] = dxsa.operand %[[INDEX_44]] {mask = 32 : i32, num_components = 4 : i32, type = 2 : i32} +// CHECK: %[[OPERAND_48:.*]] = dxsa.operand.imm {imm = dense<0> : vector<1xi32>} +// CHECK: dxsa.instruction "mov" %[[OPERAND_47]], %[[OPERAND_48]] + diff --git a/mlir/test/Target/DXSA/asm/indexabletemp4.test b/mlir/test/Target/DXSA/asm/indexabletemp4.test new file mode 100644 index 000000000000..7646e2d3bf02 --- /dev/null +++ b/mlir/test/Target/DXSA/asm/indexabletemp4.test @@ -0,0 +1,63 @@ +// RUN: mlir-translate --import-dxsa-bin %S/inputs/indexabletemp4.bin | FileCheck %s +// NOTE: Assertions have been autogenerated by utils/generate-test-checks.py + +// This script is intended to make adding checks to a test case quick and easy. +// It is *not* authoritative about what constitutes a good test. After using the +// script, be sure to review and refine the generated checks. For example, +// CHECK lines should be minimized and named to reflect the test’s intent. +// For comprehensive guidelines, see: +// * https://mlir.llvm.org/getting_started/TestingGuide/ + + +// CHECK-LABEL: dxsa.dcl_global_flags +// CHECK: dxsa.dcl_constant_buffer , +// CHECK: dxsa.dcl_input_ps constant v<1, > +// CHECK: dxsa.dcl_input_ps constant v<1, > +// CHECK: dxsa.dcl_output o<0, > +// CHECK: dxsa.dcl_temps 1 +// CHECK: dxsa.dcl_indexable_temp x<0>[4], 2 +// CHECK: %[[INDEX_0:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_0:.*]] = dxsa.operand %[[INDEX_0]] {mask = 16 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_1:.*]] = dxsa.index.imm {imm = 1 : i32} +// CHECK: %[[OPERAND_1:.*]] = dxsa.operand %[[INDEX_1]] {num_components = 4 : i32, one = 0 : i32, type = 1 : i32} +// CHECK: dxsa.instruction "mov" %[[OPERAND_0]], %[[OPERAND_1]] +// CHECK: %[[INDEX_2:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[INDEX_3:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_2:.*]] = dxsa.operand %[[INDEX_2]], %[[INDEX_3]] {mask = 16 : i32, num_components = 4 : i32, type = 3 : i32} +// CHECK: %[[INDEX_4:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[INDEX_5:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_3:.*]] = dxsa.operand %[[INDEX_5]] {num_components = 4 : i32, one = 0 : i32, type = 0 : i32} +// CHECK: %[[INDEX_6:.*]] = dxsa.index.rel %[[OPERAND_3]] +// CHECK: %[[OPERAND_4:.*]] = dxsa.operand %[[INDEX_4]], %[[INDEX_6]] {num_components = 4 : i32, one = 0 : i32, type = 8 : i32} +// CHECK: dxsa.instruction "mov" %[[OPERAND_2]], %[[OPERAND_4]] +// CHECK: %[[INDEX_7:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[INDEX_8:.*]] = dxsa.index.imm {imm = 1 : i32} +// CHECK: %[[OPERAND_5:.*]] = dxsa.operand %[[INDEX_7]], %[[INDEX_8]] {mask = 16 : i32, num_components = 4 : i32, type = 3 : i32} +// CHECK: %[[INDEX_9:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[INDEX_10:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_6:.*]] = dxsa.operand %[[INDEX_10]] {num_components = 4 : i32, one = 0 : i32, type = 0 : i32} +// CHECK: %[[INDEX_11:.*]] = dxsa.index.rel.imm %[[OPERAND_6]] {imm = 4 : i32, op = "add"} +// CHECK: %[[OPERAND_7:.*]] = dxsa.operand %[[INDEX_9]], %[[INDEX_11]] {num_components = 4 : i32, one = 0 : i32, type = 8 : i32} +// CHECK: dxsa.instruction "mov" %[[OPERAND_5]], %[[OPERAND_7]] +// CHECK: %[[INDEX_12:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_8:.*]] = dxsa.operand %[[INDEX_12]] {mask = 16 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_13:.*]] = dxsa.index.imm {imm = 1 : i32} +// CHECK: %[[OPERAND_9:.*]] = dxsa.operand %[[INDEX_13]] {num_components = 4 : i32, one = 1 : i32, type = 1 : i32} +// CHECK: dxsa.instruction "mov" %[[OPERAND_8]], %[[OPERAND_9]] +// CHECK: %[[INDEX_14:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[INDEX_15:.*]] = dxsa.index.imm {imm = 1 : i32} +// CHECK: %[[OPERAND_10:.*]] = dxsa.operand %[[INDEX_14]], %[[INDEX_15]] {mask = 32 : i32, num_components = 4 : i32, type = 3 : i32} +// CHECK: %[[INDEX_16:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_11:.*]] = dxsa.operand %[[INDEX_16]] {num_components = 4 : i32, one = 0 : i32, type = 0 : i32} +// CHECK: dxsa.instruction "mov" %[[OPERAND_10]], %[[OPERAND_11]] +// CHECK: %[[INDEX_17:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_12:.*]] = dxsa.operand %[[INDEX_17]] {mask = 16 : i32, num_components = 4 : i32, type = 2 : i32} +// CHECK: %[[INDEX_18:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[INDEX_19:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[INDEX_20:.*]] = dxsa.index.imm {imm = 1 : i32} +// CHECK: %[[OPERAND_13:.*]] = dxsa.operand %[[INDEX_19]], %[[INDEX_20]] {num_components = 4 : i32, one = 1 : i32, type = 3 : i32} +// CHECK: %[[INDEX_21:.*]] = dxsa.index.rel.imm %[[OPERAND_13]] {imm = 77 : i32, op = "add"} +// CHECK: %[[OPERAND_14:.*]] = dxsa.operand %[[INDEX_18]], %[[INDEX_21]] {num_components = 4 : i32, one = 0 : i32, type = 3 : i32} +// CHECK: dxsa.instruction "mov" %[[OPERAND_12]], %[[OPERAND_14]] +// CHECK: dxsa.instruction "ret" + diff --git a/mlir/test/Target/DXSA/asm/indexabletemp6.test b/mlir/test/Target/DXSA/asm/indexabletemp6.test new file mode 100644 index 000000000000..8785ecc63bf5 --- /dev/null +++ b/mlir/test/Target/DXSA/asm/indexabletemp6.test @@ -0,0 +1,72 @@ +// RUN: mlir-translate --import-dxsa-bin %S/inputs/indexabletemp6.bin | FileCheck %s +// NOTE: Assertions have been autogenerated by utils/generate-test-checks.py + +// This script is intended to make adding checks to a test case quick and easy. +// It is *not* authoritative about what constitutes a good test. After using the +// script, be sure to review and refine the generated checks. For example, +// CHECK lines should be minimized and named to reflect the test’s intent. +// For comprehensive guidelines, see: +// * https://mlir.llvm.org/getting_started/TestingGuide/ + + +// CHECK-LABEL: dxsa.dcl_global_flags +// CHECK: dxsa.dcl_constant_buffer , +// CHECK: dxsa.dcl_input_ps constant v<1, > +// CHECK: dxsa.dcl_input_ps constant v<1, > +// CHECK: dxsa.dcl_output o<0, min16f, > +// CHECK: dxsa.dcl_temps 1 +// CHECK: dxsa.dcl_indexable_temp x<0>[4] +// CHECK: %[[INDEX_0:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_0:.*]] = dxsa.operand %[[INDEX_0]] {mask = 16 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_1:.*]] = dxsa.index.imm {imm = 1 : i32} +// CHECK: %[[OPERAND_1:.*]] = dxsa.operand %[[INDEX_1]] {num_components = 4 : i32, one = 0 : i32, type = 1 : i32} +// CHECK: dxsa.instruction "mov" %[[OPERAND_0]], %[[OPERAND_1]] +// CHECK: %[[INDEX_2:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[INDEX_3:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_2:.*]] = dxsa.operand %[[INDEX_2]], %[[INDEX_3]] {mask = 16 : i32, num_components = 4 : i32, type = 3 : i32} +// CHECK: %[[INDEX_4:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[INDEX_5:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_3:.*]] = dxsa.operand %[[INDEX_5]] {num_components = 4 : i32, one = 0 : i32, type = 0 : i32} +// CHECK: %[[INDEX_6:.*]] = dxsa.index.rel.imm %[[OPERAND_3]] {imm = 4 : i32, op = "add"} +// CHECK: %[[OPERAND_4:.*]] = dxsa.operand %[[INDEX_4]], %[[INDEX_6]] {num_components = 4 : i32, one = 0 : i32, type = 8 : i32} +// CHECK: dxsa.instruction "mov" %[[OPERAND_2]], %[[OPERAND_4]] +// CHECK: %[[INDEX_7:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_5:.*]] = dxsa.operand %[[INDEX_7]] {mask = 32 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_8:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[INDEX_9:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_6:.*]] = dxsa.operand %[[INDEX_8]], %[[INDEX_9]] {num_components = 4 : i32, one = 0 : i32, type = 3 : i32} +// CHECK: dxsa.instruction "mov" %[[OPERAND_5]], %[[OPERAND_6]] +// CHECK: %[[INDEX_10:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[INDEX_11:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_7:.*]] = dxsa.operand %[[INDEX_10]], %[[INDEX_11]] {mask = 16 : i32, min_precision = 1 : i32, num_components = 4 : i32, type = 3 : i32} +// CHECK: %[[INDEX_12:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[INDEX_13:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_8:.*]] = dxsa.operand %[[INDEX_13]] {num_components = 4 : i32, one = 0 : i32, type = 0 : i32} +// CHECK: %[[INDEX_14:.*]] = dxsa.index.rel %[[OPERAND_8]] +// CHECK: %[[OPERAND_9:.*]] = dxsa.operand %[[INDEX_12]], %[[INDEX_14]] {min_precision = 1 : i32, num_components = 4 : i32, one = 0 : i32, type = 8 : i32} +// CHECK: dxsa.instruction "mov" %[[OPERAND_7]], %[[OPERAND_9]] +// CHECK: %[[INDEX_15:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[INDEX_16:.*]] = dxsa.index.imm {imm = 1 : i32} +// CHECK: %[[OPERAND_10:.*]] = dxsa.operand %[[INDEX_15]], %[[INDEX_16]] {mask = 16 : i32, min_precision = 1 : i32, num_components = 4 : i32, type = 3 : i32} +// CHECK: %[[INDEX_17:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[INDEX_18:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_11:.*]] = dxsa.operand %[[INDEX_18]] {num_components = 4 : i32, one = 0 : i32, type = 0 : i32} +// CHECK: %[[INDEX_19:.*]] = dxsa.index.rel.imm %[[OPERAND_11]] {imm = 4 : i32, op = "add"} +// CHECK: %[[OPERAND_12:.*]] = dxsa.operand %[[INDEX_17]], %[[INDEX_19]] {min_precision = 1 : i32, num_components = 4 : i32, one = 0 : i32, type = 8 : i32} +// CHECK: dxsa.instruction "mov" %[[OPERAND_10]], %[[OPERAND_12]] +// CHECK: %[[INDEX_20:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_13:.*]] = dxsa.operand %[[INDEX_20]] {mask = 16 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_21:.*]] = dxsa.index.imm {imm = 1 : i32} +// CHECK: %[[OPERAND_14:.*]] = dxsa.operand %[[INDEX_21]] {num_components = 4 : i32, one = 1 : i32, type = 1 : i32} +// CHECK: dxsa.instruction "mov" %[[OPERAND_13]], %[[OPERAND_14]] +// CHECK: dxsa.add x<[0, r<0, >], min16f, >, x<[0, r<0, >], min16f, >, r<0, min16f, > +// CHECK: %[[INDEX_22:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_15:.*]] = dxsa.operand %[[INDEX_22]] {mask = 16 : i32, min_precision = 1 : i32, num_components = 4 : i32, type = 2 : i32} +// CHECK: %[[INDEX_23:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[INDEX_24:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_16:.*]] = dxsa.operand %[[INDEX_24]] {num_components = 4 : i32, one = 0 : i32, type = 0 : i32} +// CHECK: %[[INDEX_25:.*]] = dxsa.index.rel %[[OPERAND_16]] +// CHECK: %[[OPERAND_17:.*]] = dxsa.operand %[[INDEX_23]], %[[INDEX_25]] {min_precision = 1 : i32, num_components = 4 : i32, one = 0 : i32, type = 3 : i32} +// CHECK: dxsa.instruction "mov" %[[OPERAND_15]], %[[OPERAND_17]] +// CHECK: dxsa.instruction "ret" + diff --git a/mlir/test/Target/DXSA/asm/inputs/call2.bin b/mlir/test/Target/DXSA/asm/inputs/call2.bin new file mode 100644 index 0000000000000000000000000000000000000000..e0fe124cfbac3496004e6f986cad99c129b6be98 GIT binary patch literal 356 zcmZWku?oUK41L%3wA^%b5jr`Gv!mYRU?7mZ_wtfF0lb*s z9%0I8hn(2~Q;&9L9az6X{HXW`Xau_eafV{|QFR@4SQLxsVye7h5Avyc?pTL{&EMu4 z`pVqs=42P~keI@q94C6=%**N?zuT4k+1)C?4AoaPOYs`}*EI5jgxARK If1k4XtTcBLkpKVy literal 0 HcmV?d00001 diff --git a/mlir/test/Target/DXSA/asm/inputs/cs3.bin b/mlir/test/Target/DXSA/asm/inputs/cs3.bin new file mode 100644 index 0000000000000000000000000000000000000000..979c550dcb062987cd513ea67ed67d2d81bb4c3c GIT binary patch literal 324 zcmZ{gEe^s!5QV=jf2FFR2&#$zil9)WszDYMC@ev811`V?5GW7?Nk}j~6AsIpv^4}a z`F3~q&CI^tlp1qj>*H2XO%9PFaAFPKF7nuDttdW8=hZUVb{sWp!4swrpx!3b4u-08 zajsp!9~X5&p+EMKvhtCIxGWN}=!m|UiIGUfL@aS25yW6~!9uvj( ejzC_n^7iZerk>yDUFBQN6Pni3di=|o>Z?BU1t1du literal 0 HcmV?d00001 diff --git a/mlir/test/Target/DXSA/asm/inputs/cyclecounter.bin b/mlir/test/Target/DXSA/asm/inputs/cyclecounter.bin new file mode 100644 index 0000000000000000000000000000000000000000..3f883fb28ba45fe3776aba9a973d0286c9e43102 GIT binary patch literal 92 zcmWGwU|Q@)H$I430Cx5VsQ>@~ literal 0 HcmV?d00001 diff --git a/mlir/test/Target/DXSA/asm/inputs/hs3.bin b/mlir/test/Target/DXSA/asm/inputs/hs3.bin new file mode 100644 index 0000000000000000000000000000000000000000..f817cea934d42183b1444d12a2c6652ee656c946 GIT binary patch literal 1300 zcmdT@OHKko6s%?jHTc6>xiSMMAS_%Xi7bhG7rHU(4$%W}1QP!{j=&K-f@hf%Sk>K+ zX%eF=7j`nC>iv4E=5dA$rw+IS++zv%1m~U);a>Q>@_7Rqz-%~W{sPFWc8MI}i1#Ds z2#8N3XOnmXmoEG+fh!=Z%C>J7?h~s|cuK6E8}=wR1~%~t6bSW>bKHOzFn7$H%^4jn z(26xo`JBxiwd9-|IhkuHEcL&kf5X!}7(jyhyzv zjou8_JgYs%Fs=XH@2ui`3KO zE}ri6&N9Iub@j9lUg5qN7H# +// CHECK: dxsa.dcl_input_ps linear v<0, > +// CHECK: dxsa.dcl_output o<0> +// CHECK: %[[INDEX_0:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_0:.*]] = dxsa.operand %[[INDEX_0]] {mask = 240 : i32, num_components = 4 : i32, type = 2 : i32} +// CHECK: %[[INDEX_1:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_1:.*]] = dxsa.operand %[[INDEX_1]] {modifier = 2 : i32, num_components = 4 : i32, swizzle = dense<[1, 0, 0, 0]> : vector<4xi32>, type = 1 : i32} +// CHECK: dxsa.instruction "mov" %[[OPERAND_0]], %[[OPERAND_1]] +// CHECK: dxsa.instruction "ret" + diff --git a/mlir/test/Target/DXSA/hlsl/abs2.test b/mlir/test/Target/DXSA/hlsl/abs2.test new file mode 100644 index 000000000000..66b66e14fb49 --- /dev/null +++ b/mlir/test/Target/DXSA/hlsl/abs2.test @@ -0,0 +1,23 @@ +// RUN: mlir-translate --import-dxsa-bin %S/inputs/abs2.bin | FileCheck %s +// NOTE: Assertions have been autogenerated by utils/generate-test-checks.py + +// This script is intended to make adding checks to a test case quick and easy. +// It is *not* authoritative about what constitutes a good test. After using the +// script, be sure to review and refine the generated checks. For example, +// CHECK lines should be minimized and named to reflect the test’s intent. +// For comprehensive guidelines, see: +// * https://mlir.llvm.org/getting_started/TestingGuide/ + + +// CHECK-LABEL: dxsa.dcl_global_flags +// CHECK: dxsa.dcl_input_ps constant v<0, > +// CHECK: dxsa.dcl_output o<0> +// CHECK: %[[INDEX_0:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_0:.*]] = dxsa.operand %[[INDEX_0]] {mask = 240 : i32, num_components = 4 : i32, type = 2 : i32} +// CHECK: %[[INDEX_1:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_1:.*]] = dxsa.operand %[[INDEX_1]] {modifier = 1 : i32, num_components = 4 : i32, swizzle = dense<[1, 0, 0, 0]> : vector<4xi32>, type = 1 : i32} +// CHECK: %[[INDEX_2:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_2:.*]] = dxsa.operand %[[INDEX_2]] {num_components = 4 : i32, swizzle = dense<[1, 0, 0, 0]> : vector<4xi32>, type = 1 : i32} +// CHECK: dxsa.instruction "imax" %[[OPERAND_0]], %[[OPERAND_1]], %[[OPERAND_2]] +// CHECK: dxsa.instruction "ret" + diff --git a/mlir/test/Target/DXSA/hlsl/atomics.test b/mlir/test/Target/DXSA/hlsl/atomics.test new file mode 100644 index 000000000000..0a700e93f5ec --- /dev/null +++ b/mlir/test/Target/DXSA/hlsl/atomics.test @@ -0,0 +1,258 @@ +// RUN: mlir-translate --import-dxsa-bin %S/inputs/atomics.bin | FileCheck %s +// NOTE: Assertions have been autogenerated by utils/generate-test-checks.py + +// This script is intended to make adding checks to a test case quick and easy. +// It is *not* authoritative about what constitutes a good test. After using the +// script, be sure to review and refine the generated checks. For example, +// CHECK lines should be minimized and named to reflect the test’s intent. +// For comprehensive guidelines, see: +// * https://mlir.llvm.org/getting_started/TestingGuide/ + + +// CHECK-LABEL: dxsa.dcl_global_flags +// CHECK: dxsa.dcl_uav_typed , +// CHECK: dxsa.dcl_uav_raw +// CHECK: dxsa.dcl_uav_raw +// CHECK: dxsa.dcl_uav_typed , +// CHECK: dxsa.dcl_uav_typed , +// CHECK: dxsa.dcl_uav_typed , +// CHECK: dxsa.dcl_uav_typed , +// CHECK: dxsa.dcl_input_ps constant v<0> +// CHECK: dxsa.dcl_output o<0> +// CHECK: dxsa.dcl_temps 2 +// CHECK: %[[INDEX_0:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[INDEX_1:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_0:.*]] = dxsa.operand %[[INDEX_0]], %[[INDEX_1]] {num_components = 0 : i32, type = 30 : i32} +// CHECK: %[[INDEX_2:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_1:.*]] = dxsa.operand %[[INDEX_2]] {num_components = 4 : i32, one = 2 : i32, type = 1 : i32} +// CHECK: %[[INDEX_3:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_2:.*]] = dxsa.operand %[[INDEX_3]] {num_components = 4 : i32, one = 2 : i32, type = 1 : i32} +// CHECK: dxsa.instruction "atomic_iadd" %[[OPERAND_0]], %[[OPERAND_1]], %[[OPERAND_2]] +// CHECK: %[[INDEX_4:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[INDEX_5:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_3:.*]] = dxsa.operand %[[INDEX_4]], %[[INDEX_5]] {num_components = 0 : i32, type = 30 : i32} +// CHECK: %[[INDEX_6:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_4:.*]] = dxsa.operand %[[INDEX_6]] {num_components = 4 : i32, one = 2 : i32, type = 1 : i32} +// CHECK: %[[INDEX_7:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_5:.*]] = dxsa.operand %[[INDEX_7]] {num_components = 4 : i32, one = 2 : i32, type = 1 : i32} +// CHECK: dxsa.instruction "atomic_umin" %[[OPERAND_3]], %[[OPERAND_4]], %[[OPERAND_5]] +// CHECK: %[[INDEX_8:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[INDEX_9:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_6:.*]] = dxsa.operand %[[INDEX_8]], %[[INDEX_9]] {num_components = 0 : i32, type = 30 : i32} +// CHECK: %[[INDEX_10:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_7:.*]] = dxsa.operand %[[INDEX_10]] {num_components = 4 : i32, one = 2 : i32, type = 1 : i32} +// CHECK: %[[INDEX_11:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_8:.*]] = dxsa.operand %[[INDEX_11]] {num_components = 4 : i32, one = 2 : i32, type = 1 : i32} +// CHECK: dxsa.instruction "atomic_umax" %[[OPERAND_6]], %[[OPERAND_7]], %[[OPERAND_8]] +// CHECK: %[[INDEX_12:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[INDEX_13:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_9:.*]] = dxsa.operand %[[INDEX_12]], %[[INDEX_13]] {num_components = 0 : i32, type = 30 : i32} +// CHECK: %[[INDEX_14:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_10:.*]] = dxsa.operand %[[INDEX_14]] {num_components = 4 : i32, one = 2 : i32, type = 1 : i32} +// CHECK: %[[INDEX_15:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_11:.*]] = dxsa.operand %[[INDEX_15]] {num_components = 4 : i32, one = 2 : i32, type = 1 : i32} +// CHECK: dxsa.instruction "atomic_and" %[[OPERAND_9]], %[[OPERAND_10]], %[[OPERAND_11]] +// CHECK: %[[INDEX_16:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[INDEX_17:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_12:.*]] = dxsa.operand %[[INDEX_16]], %[[INDEX_17]] {num_components = 0 : i32, type = 30 : i32} +// CHECK: %[[INDEX_18:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_13:.*]] = dxsa.operand %[[INDEX_18]] {num_components = 4 : i32, one = 2 : i32, type = 1 : i32} +// CHECK: %[[INDEX_19:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_14:.*]] = dxsa.operand %[[INDEX_19]] {num_components = 4 : i32, one = 2 : i32, type = 1 : i32} +// CHECK: dxsa.instruction "atomic_or" %[[OPERAND_12]], %[[OPERAND_13]], %[[OPERAND_14]] +// CHECK: %[[INDEX_20:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[INDEX_21:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_15:.*]] = dxsa.operand %[[INDEX_20]], %[[INDEX_21]] {num_components = 0 : i32, type = 30 : i32} +// CHECK: %[[INDEX_22:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_16:.*]] = dxsa.operand %[[INDEX_22]] {num_components = 4 : i32, one = 2 : i32, type = 1 : i32} +// CHECK: %[[INDEX_23:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_17:.*]] = dxsa.operand %[[INDEX_23]] {num_components = 4 : i32, one = 2 : i32, type = 1 : i32} +// CHECK: dxsa.instruction "atomic_xor" %[[OPERAND_15]], %[[OPERAND_16]], %[[OPERAND_17]] +// CHECK: %[[INDEX_24:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_18:.*]] = dxsa.operand %[[INDEX_24]] {mask = 16 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_25:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[INDEX_26:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_19:.*]] = dxsa.operand %[[INDEX_25]], %[[INDEX_26]] {num_components = 0 : i32, type = 30 : i32} +// CHECK: %[[INDEX_27:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_20:.*]] = dxsa.operand %[[INDEX_27]] {num_components = 4 : i32, one = 2 : i32, type = 1 : i32} +// CHECK: %[[INDEX_28:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_21:.*]] = dxsa.operand %[[INDEX_28]] {num_components = 4 : i32, one = 2 : i32, type = 1 : i32} +// CHECK: dxsa.instruction "imm_atomic_iadd" %[[OPERAND_18]], %[[OPERAND_19]], %[[OPERAND_20]], %[[OPERAND_21]] +// CHECK: %[[INDEX_29:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_22:.*]] = dxsa.operand %[[INDEX_29]] {mask = 16 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_30:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_23:.*]] = dxsa.operand %[[INDEX_30]] {num_components = 4 : i32, one = 0 : i32, type = 0 : i32} +// CHECK: %[[INDEX_31:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_24:.*]] = dxsa.operand %[[INDEX_31]] {num_components = 4 : i32, one = 2 : i32, type = 1 : i32} +// CHECK: dxsa.instruction "iadd" %[[OPERAND_22]], %[[OPERAND_23]], %[[OPERAND_24]] +// CHECK: %[[INDEX_32:.*]] = dxsa.index.imm {imm = 3 : i32} +// CHECK: %[[INDEX_33:.*]] = dxsa.index.imm {imm = 30 : i32} +// CHECK: %[[OPERAND_25:.*]] = dxsa.operand %[[INDEX_32]], %[[INDEX_33]] {num_components = 0 : i32, type = 30 : i32} +// CHECK: %[[INDEX_34:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_26:.*]] = dxsa.operand %[[INDEX_34]] {num_components = 4 : i32, swizzle = dense<[0, 1, 0, 0]> : vector<4xi32>, type = 1 : i32} +// CHECK: %[[INDEX_35:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_27:.*]] = dxsa.operand %[[INDEX_35]] {num_components = 4 : i32, one = 0 : i32, type = 0 : i32} +// CHECK: dxsa.instruction "atomic_iadd" %[[OPERAND_25]], %[[OPERAND_26]], %[[OPERAND_27]] +// CHECK: %[[INDEX_36:.*]] = dxsa.index.imm {imm = 4 : i32} +// CHECK: %[[INDEX_37:.*]] = dxsa.index.imm {imm = 31 : i32} +// CHECK: %[[OPERAND_28:.*]] = dxsa.operand %[[INDEX_36]], %[[INDEX_37]] {num_components = 0 : i32, type = 30 : i32} +// CHECK: %[[INDEX_38:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_29:.*]] = dxsa.operand %[[INDEX_38]] {num_components = 4 : i32, swizzle = dense<[1, 3, 2, 1]> : vector<4xi32>, type = 1 : i32} +// CHECK: %[[INDEX_39:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_30:.*]] = dxsa.operand %[[INDEX_39]] {num_components = 4 : i32, one = 0 : i32, type = 0 : i32} +// CHECK: dxsa.instruction "atomic_iadd" %[[OPERAND_28]], %[[OPERAND_29]], %[[OPERAND_30]] +// CHECK: %[[INDEX_40:.*]] = dxsa.index.imm {imm = 5 : i32} +// CHECK: %[[INDEX_41:.*]] = dxsa.index.imm {imm = 32 : i32} +// CHECK: %[[OPERAND_31:.*]] = dxsa.operand %[[INDEX_40]], %[[INDEX_41]] {num_components = 0 : i32, type = 30 : i32} +// CHECK: %[[INDEX_42:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_32:.*]] = dxsa.operand %[[INDEX_42]] {num_components = 4 : i32, swizzle = dense<[0, 1, 2, 0]> : vector<4xi32>, type = 1 : i32} +// CHECK: %[[INDEX_43:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_33:.*]] = dxsa.operand %[[INDEX_43]] {num_components = 4 : i32, one = 0 : i32, type = 0 : i32} +// CHECK: dxsa.instruction "atomic_iadd" %[[OPERAND_31]], %[[OPERAND_32]], %[[OPERAND_33]] +// CHECK: %[[INDEX_44:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_34:.*]] = dxsa.operand %[[INDEX_44]] {mask = 32 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[OPERAND_35:.*]] = dxsa.operand.imm {imm = dense<30> : vector<1xi32>} +// CHECK: %[[OPERAND_36:.*]] = dxsa.operand.imm {imm = dense<2> : vector<1xi32>} +// CHECK: %[[INDEX_45:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_37:.*]] = dxsa.operand %[[INDEX_45]] {num_components = 4 : i32, one = 0 : i32, type = 1 : i32} +// CHECK: %[[OPERAND_38:.*]] = dxsa.operand.imm {imm = dense<1> : vector<1xi32>} +// CHECK: dxsa.instruction "bfi" %[[OPERAND_34]], %[[OPERAND_35]], %[[OPERAND_36]], %[[OPERAND_37]], %[[OPERAND_38]] +// CHECK: %[[INDEX_46:.*]] = dxsa.index.imm {imm = 6 : i32} +// CHECK: %[[INDEX_47:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_39:.*]] = dxsa.operand %[[INDEX_47]] {num_components = 4 : i32, one = 1 : i32, type = 0 : i32} +// CHECK: %[[INDEX_48:.*]] = dxsa.index.rel.imm %[[OPERAND_39]] {imm = 33 : i32, op = "add"} +// CHECK: %[[OPERAND_40:.*]] = dxsa.operand %[[INDEX_46]], %[[INDEX_48]] {num_components = 0 : i32, type = 30 : i32} +// CHECK: %[[INDEX_49:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_41:.*]] = dxsa.operand %[[INDEX_49]] {num_components = 4 : i32, swizzle = dense<[0, 1, 2, 0]> : vector<4xi32>, type = 1 : i32} +// CHECK: %[[INDEX_50:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_42:.*]] = dxsa.operand %[[INDEX_50]] {num_components = 4 : i32, one = 0 : i32, type = 0 : i32} +// CHECK: dxsa.instruction "atomic_iadd" %[[OPERAND_40]], %[[OPERAND_41]], %[[OPERAND_42]] +// CHECK: %[[INDEX_51:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_43:.*]] = dxsa.operand %[[INDEX_51]] {mask = 16 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_52:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[INDEX_53:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_44:.*]] = dxsa.operand %[[INDEX_52]], %[[INDEX_53]] {num_components = 0 : i32, type = 30 : i32} +// CHECK: %[[INDEX_54:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_45:.*]] = dxsa.operand %[[INDEX_54]] {num_components = 4 : i32, one = 2 : i32, type = 1 : i32} +// CHECK: %[[INDEX_55:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_46:.*]] = dxsa.operand %[[INDEX_55]] {num_components = 4 : i32, one = 3 : i32, type = 1 : i32} +// CHECK: %[[INDEX_56:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_47:.*]] = dxsa.operand %[[INDEX_56]] {num_components = 4 : i32, one = 0 : i32, type = 0 : i32} +// CHECK: dxsa.instruction "imm_atomic_cmp_exch" %[[OPERAND_43]], %[[OPERAND_44]], %[[OPERAND_45]], %[[OPERAND_46]], %[[OPERAND_47]] +// CHECK: %[[INDEX_57:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_48:.*]] = dxsa.operand %[[INDEX_57]] {mask = 16 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_58:.*]] = dxsa.index.imm {imm = 1 : i32} +// CHECK: %[[INDEX_59:.*]] = dxsa.index.imm {imm = 1 : i32} +// CHECK: %[[OPERAND_49:.*]] = dxsa.operand %[[INDEX_58]], %[[INDEX_59]] {num_components = 0 : i32, type = 30 : i32} +// CHECK: %[[INDEX_60:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_50:.*]] = dxsa.operand %[[INDEX_60]] {num_components = 4 : i32, one = 0 : i32, type = 1 : i32} +// CHECK: %[[INDEX_61:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_51:.*]] = dxsa.operand %[[INDEX_61]] {num_components = 4 : i32, one = 2 : i32, type = 1 : i32} +// CHECK: dxsa.instruction "imm_atomic_iadd" %[[OPERAND_48]], %[[OPERAND_49]], %[[OPERAND_50]], %[[OPERAND_51]] +// CHECK: %[[INDEX_62:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_52:.*]] = dxsa.operand %[[INDEX_62]] {mask = 16 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_63:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_53:.*]] = dxsa.operand %[[INDEX_63]] {num_components = 4 : i32, one = 1 : i32, type = 1 : i32} +// CHECK: %[[OPERAND_54:.*]] = dxsa.operand.imm {imm = dense<14> : vector<1xi32>} +// CHECK: dxsa.instruction "iadd" %[[OPERAND_52]], %[[OPERAND_53]], %[[OPERAND_54]] +// CHECK: %[[INDEX_64:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_55:.*]] = dxsa.operand %[[INDEX_64]] {mask = 16 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_65:.*]] = dxsa.index.imm {imm = 2 : i32} +// CHECK: %[[INDEX_66:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_56:.*]] = dxsa.operand %[[INDEX_66]] {num_components = 4 : i32, one = 0 : i32, type = 0 : i32} +// CHECK: %[[INDEX_67:.*]] = dxsa.index.rel.imm %[[OPERAND_56]] {imm = 2 : i32, op = "add"} +// CHECK: %[[OPERAND_57:.*]] = dxsa.operand %[[INDEX_65]], %[[INDEX_67]] {num_components = 0 : i32, type = 30 : i32} +// CHECK: %[[INDEX_68:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_58:.*]] = dxsa.operand %[[INDEX_68]] {num_components = 4 : i32, one = 0 : i32, type = 1 : i32} +// CHECK: %[[INDEX_69:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_59:.*]] = dxsa.operand %[[INDEX_69]] {num_components = 4 : i32, one = 2 : i32, type = 1 : i32} +// CHECK: dxsa.instruction "imm_atomic_iadd" %[[OPERAND_55]], %[[OPERAND_57]], %[[OPERAND_58]], %[[OPERAND_59]] +// CHECK: %[[INDEX_70:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_60:.*]] = dxsa.operand %[[INDEX_70]] {mask = 16 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_71:.*]] = dxsa.index.imm {imm = 1 : i32} +// CHECK: %[[INDEX_72:.*]] = dxsa.index.imm {imm = 1 : i32} +// CHECK: %[[OPERAND_61:.*]] = dxsa.operand %[[INDEX_71]], %[[INDEX_72]] {num_components = 0 : i32, type = 30 : i32} +// CHECK: %[[INDEX_73:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_62:.*]] = dxsa.operand %[[INDEX_73]] {num_components = 4 : i32, one = 0 : i32, type = 1 : i32} +// CHECK: %[[INDEX_74:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_63:.*]] = dxsa.operand %[[INDEX_74]] {num_components = 4 : i32, one = 2 : i32, type = 1 : i32} +// CHECK: dxsa.instruction "imm_atomic_umin" %[[OPERAND_60]], %[[OPERAND_61]], %[[OPERAND_62]], %[[OPERAND_63]] +// CHECK: %[[INDEX_75:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_64:.*]] = dxsa.operand %[[INDEX_75]] {mask = 16 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_76:.*]] = dxsa.index.imm {imm = 1 : i32} +// CHECK: %[[INDEX_77:.*]] = dxsa.index.imm {imm = 1 : i32} +// CHECK: %[[OPERAND_65:.*]] = dxsa.operand %[[INDEX_76]], %[[INDEX_77]] {num_components = 0 : i32, type = 30 : i32} +// CHECK: %[[INDEX_78:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_66:.*]] = dxsa.operand %[[INDEX_78]] {num_components = 4 : i32, one = 0 : i32, type = 1 : i32} +// CHECK: %[[INDEX_79:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_67:.*]] = dxsa.operand %[[INDEX_79]] {num_components = 4 : i32, one = 2 : i32, type = 1 : i32} +// CHECK: dxsa.instruction "imm_atomic_umax" %[[OPERAND_64]], %[[OPERAND_65]], %[[OPERAND_66]], %[[OPERAND_67]] +// CHECK: %[[INDEX_80:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_68:.*]] = dxsa.operand %[[INDEX_80]] {mask = 16 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_81:.*]] = dxsa.index.imm {imm = 1 : i32} +// CHECK: %[[INDEX_82:.*]] = dxsa.index.imm {imm = 1 : i32} +// CHECK: %[[OPERAND_69:.*]] = dxsa.operand %[[INDEX_81]], %[[INDEX_82]] {num_components = 0 : i32, type = 30 : i32} +// CHECK: %[[INDEX_83:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_70:.*]] = dxsa.operand %[[INDEX_83]] {num_components = 4 : i32, one = 0 : i32, type = 1 : i32} +// CHECK: %[[INDEX_84:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_71:.*]] = dxsa.operand %[[INDEX_84]] {num_components = 4 : i32, one = 2 : i32, type = 1 : i32} +// CHECK: dxsa.instruction "imm_atomic_and" %[[OPERAND_68]], %[[OPERAND_69]], %[[OPERAND_70]], %[[OPERAND_71]] +// CHECK: %[[INDEX_85:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_72:.*]] = dxsa.operand %[[INDEX_85]] {mask = 16 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_86:.*]] = dxsa.index.imm {imm = 1 : i32} +// CHECK: %[[INDEX_87:.*]] = dxsa.index.imm {imm = 1 : i32} +// CHECK: %[[OPERAND_73:.*]] = dxsa.operand %[[INDEX_86]], %[[INDEX_87]] {num_components = 0 : i32, type = 30 : i32} +// CHECK: %[[INDEX_88:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_74:.*]] = dxsa.operand %[[INDEX_88]] {num_components = 4 : i32, one = 0 : i32, type = 1 : i32} +// CHECK: %[[INDEX_89:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_75:.*]] = dxsa.operand %[[INDEX_89]] {num_components = 4 : i32, one = 2 : i32, type = 1 : i32} +// CHECK: dxsa.instruction "imm_atomic_or" %[[OPERAND_72]], %[[OPERAND_73]], %[[OPERAND_74]], %[[OPERAND_75]] +// CHECK: %[[INDEX_90:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_76:.*]] = dxsa.operand %[[INDEX_90]] {mask = 16 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_91:.*]] = dxsa.index.imm {imm = 1 : i32} +// CHECK: %[[INDEX_92:.*]] = dxsa.index.imm {imm = 1 : i32} +// CHECK: %[[OPERAND_77:.*]] = dxsa.operand %[[INDEX_91]], %[[INDEX_92]] {num_components = 0 : i32, type = 30 : i32} +// CHECK: %[[INDEX_93:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_78:.*]] = dxsa.operand %[[INDEX_93]] {num_components = 4 : i32, one = 0 : i32, type = 1 : i32} +// CHECK: %[[INDEX_94:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_79:.*]] = dxsa.operand %[[INDEX_94]] {num_components = 4 : i32, one = 2 : i32, type = 1 : i32} +// CHECK: dxsa.instruction "imm_atomic_xor" %[[OPERAND_76]], %[[OPERAND_77]], %[[OPERAND_78]], %[[OPERAND_79]] +// CHECK: %[[INDEX_95:.*]] = dxsa.index.imm {imm = 1 : i32} +// CHECK: %[[OPERAND_80:.*]] = dxsa.operand %[[INDEX_95]] {mask = 16 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_96:.*]] = dxsa.index.imm {imm = 1 : i32} +// CHECK: %[[INDEX_97:.*]] = dxsa.index.imm {imm = 1 : i32} +// CHECK: %[[OPERAND_81:.*]] = dxsa.operand %[[INDEX_96]], %[[INDEX_97]] {num_components = 0 : i32, type = 30 : i32} +// CHECK: %[[INDEX_98:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_82:.*]] = dxsa.operand %[[INDEX_98]] {num_components = 4 : i32, one = 2 : i32, type = 1 : i32} +// CHECK: %[[INDEX_99:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_83:.*]] = dxsa.operand %[[INDEX_99]] {num_components = 4 : i32, one = 0 : i32, type = 0 : i32} +// CHECK: dxsa.instruction "imm_atomic_exch" %[[OPERAND_80]], %[[OPERAND_81]], %[[OPERAND_82]], %[[OPERAND_83]] +// CHECK: %[[INDEX_100:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_84:.*]] = dxsa.operand %[[INDEX_100]] {mask = 16 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_101:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_85:.*]] = dxsa.operand %[[INDEX_101]] {num_components = 4 : i32, one = 0 : i32, type = 0 : i32} +// CHECK: %[[INDEX_102:.*]] = dxsa.index.imm {imm = 1 : i32} +// CHECK: %[[OPERAND_86:.*]] = dxsa.operand %[[INDEX_102]] {num_components = 4 : i32, one = 0 : i32, type = 0 : i32} +// CHECK: dxsa.instruction "iadd" %[[OPERAND_84]], %[[OPERAND_85]], %[[OPERAND_86]] +// CHECK: %[[INDEX_103:.*]] = dxsa.index.imm {imm = 1 : i32} +// CHECK: %[[OPERAND_87:.*]] = dxsa.operand %[[INDEX_103]] {mask = 16 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_104:.*]] = dxsa.index.imm {imm = 1 : i32} +// CHECK: %[[INDEX_105:.*]] = dxsa.index.imm {imm = 1 : i32} +// CHECK: %[[OPERAND_88:.*]] = dxsa.operand %[[INDEX_104]], %[[INDEX_105]] {num_components = 0 : i32, type = 30 : i32} +// CHECK: %[[INDEX_106:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_89:.*]] = dxsa.operand %[[INDEX_106]] {num_components = 4 : i32, one = 2 : i32, type = 1 : i32} +// CHECK: %[[INDEX_107:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_90:.*]] = dxsa.operand %[[INDEX_107]] {num_components = 4 : i32, one = 3 : i32, type = 1 : i32} +// CHECK: %[[INDEX_108:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_91:.*]] = dxsa.operand %[[INDEX_108]] {num_components = 4 : i32, one = 0 : i32, type = 0 : i32} +// CHECK: dxsa.instruction "imm_atomic_cmp_exch" %[[OPERAND_87]], %[[OPERAND_88]], %[[OPERAND_89]], %[[OPERAND_90]], %[[OPERAND_91]] +// CHECK: %[[INDEX_109:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_92:.*]] = dxsa.operand %[[INDEX_109]] {mask = 16 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_110:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_93:.*]] = dxsa.operand %[[INDEX_110]] {num_components = 4 : i32, one = 0 : i32, type = 0 : i32} +// CHECK: %[[INDEX_111:.*]] = dxsa.index.imm {imm = 1 : i32} +// CHECK: %[[OPERAND_94:.*]] = dxsa.operand %[[INDEX_111]] {num_components = 4 : i32, one = 0 : i32, type = 0 : i32} +// CHECK: dxsa.instruction "iadd" %[[OPERAND_92]], %[[OPERAND_93]], %[[OPERAND_94]] +// CHECK: dxsa.utof o<0>, r<0, > +// CHECK: dxsa.instruction "ret" + diff --git a/mlir/test/Target/DXSA/hlsl/bad_ftoi.test b/mlir/test/Target/DXSA/hlsl/bad_ftoi.test new file mode 100644 index 000000000000..194ad7f38fbe --- /dev/null +++ b/mlir/test/Target/DXSA/hlsl/bad_ftoi.test @@ -0,0 +1,18 @@ +// RUN: mlir-translate --import-dxsa-bin %S/inputs/bad_ftoi.bin | FileCheck %s +// NOTE: Assertions have been autogenerated by utils/generate-test-checks.py + +// This script is intended to make adding checks to a test case quick and easy. +// It is *not* authoritative about what constitutes a good test. After using the +// script, be sure to review and refine the generated checks. For example, +// CHECK lines should be minimized and named to reflect the test’s intent. +// For comprehensive guidelines, see: +// * https://mlir.llvm.org/getting_started/TestingGuide/ + + +// CHECK-LABEL: dxsa.dcl_global_flags +// CHECK: dxsa.dcl_output o<0> +// CHECK: dxsa.ftou o<0, >, l(0x7F7FFFFF) +// CHECK: dxsa.ftou o<0, >, l(0xFF7FFFFF) +// CHECK: dxsa.ftoi o<0, >, l(0x7F7FFFFF, 0xFF7FFFFF, 0x0, 0x0) +// CHECK: dxsa.instruction "ret" + diff --git a/mlir/test/Target/DXSA/hlsl/binary1.test b/mlir/test/Target/DXSA/hlsl/binary1.test new file mode 100644 index 000000000000..4a4b09be54b6 --- /dev/null +++ b/mlir/test/Target/DXSA/hlsl/binary1.test @@ -0,0 +1,24 @@ +// RUN: mlir-translate --import-dxsa-bin %S/inputs/binary1.bin | FileCheck %s +// NOTE: Assertions have been autogenerated by utils/generate-test-checks.py + +// This script is intended to make adding checks to a test case quick and easy. +// It is *not* authoritative about what constitutes a good test. After using the +// script, be sure to review and refine the generated checks. For example, +// CHECK lines should be minimized and named to reflect the test’s intent. +// For comprehensive guidelines, see: +// * https://mlir.llvm.org/getting_started/TestingGuide/ + + +// CHECK-LABEL: dxsa.dcl_global_flags +// CHECK: dxsa.dcl_input_ps linear v<0, > +// CHECK: dxsa.dcl_input_ps linear v<0, > +// CHECK: dxsa.dcl_input_ps linear v<0, > +// CHECK: dxsa.dcl_output o<0, > +// CHECK: dxsa.dcl_temps 1 +// CHECK: dxsa.add r<0, >, v<0, >, v<0, > +// CHECK: dxsa.div r<0, >, r<0, >, v<0, > +// CHECK: dxsa.mul r<0, >, r<0, >, v<0, > +// CHECK: dxsa.max r<0, >, r<0, >, v<0, > +// CHECK: dxsa.min o<0, >, r<0, >, v<0, > +// CHECK: dxsa.instruction "ret" + diff --git a/mlir/test/Target/DXSA/hlsl/bool1.test b/mlir/test/Target/DXSA/hlsl/bool1.test new file mode 100644 index 000000000000..b5e35f27036e --- /dev/null +++ b/mlir/test/Target/DXSA/hlsl/bool1.test @@ -0,0 +1,36 @@ +// RUN: mlir-translate --import-dxsa-bin %S/inputs/bool1.bin | FileCheck %s +// NOTE: Assertions have been autogenerated by utils/generate-test-checks.py + +// This script is intended to make adding checks to a test case quick and easy. +// It is *not* authoritative about what constitutes a good test. After using the +// script, be sure to review and refine the generated checks. For example, +// CHECK lines should be minimized and named to reflect the test’s intent. +// For comprehensive guidelines, see: +// * https://mlir.llvm.org/getting_started/TestingGuide/ + + +// CHECK-LABEL: dxsa.dcl_global_flags +// CHECK: dxsa.dcl_input_ps constant v<0, > +// CHECK: dxsa.dcl_output o<0, > +// CHECK: dxsa.dcl_temps 1 +// CHECK: %[[INDEX_0:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_0:.*]] = dxsa.operand %[[INDEX_0]] {mask = 16 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_1:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_1:.*]] = dxsa.operand %[[INDEX_1]] {num_components = 4 : i32, one = 0 : i32, type = 1 : i32} +// CHECK: dxsa.instruction "firstbit_hi" %[[OPERAND_0]], %[[OPERAND_1]] +// CHECK: %[[INDEX_2:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_2:.*]] = dxsa.operand %[[INDEX_2]] {mask = 16 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_3:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_3:.*]] = dxsa.operand %[[INDEX_3]] {modifier = 1 : i32, num_components = 4 : i32, one = 0 : i32, type = 0 : i32} +// CHECK: %[[OPERAND_4:.*]] = dxsa.operand.imm {imm = dense<31> : vector<1xi32>} +// CHECK: dxsa.instruction "iadd" %[[OPERAND_2]], %[[OPERAND_3]], %[[OPERAND_4]] +// CHECK: %[[INDEX_4:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_5:.*]] = dxsa.operand %[[INDEX_4]] {mask = 16 : i32, num_components = 4 : i32, type = 2 : i32} +// CHECK: %[[INDEX_5:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_6:.*]] = dxsa.operand %[[INDEX_5]] {num_components = 4 : i32, one = 0 : i32, type = 1 : i32} +// CHECK: %[[INDEX_6:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_7:.*]] = dxsa.operand %[[INDEX_6]] {num_components = 4 : i32, one = 0 : i32, type = 0 : i32} +// CHECK: %[[OPERAND_8:.*]] = dxsa.operand.imm {imm = dense<-1> : vector<1xi32>} +// CHECK: dxsa.instruction "movc" %[[OPERAND_5]], %[[OPERAND_6]], %[[OPERAND_7]], %[[OPERAND_8]] +// CHECK: dxsa.instruction "ret" + diff --git a/mlir/test/Target/DXSA/hlsl/bool2.test b/mlir/test/Target/DXSA/hlsl/bool2.test new file mode 100644 index 000000000000..8208dd27b201 --- /dev/null +++ b/mlir/test/Target/DXSA/hlsl/bool2.test @@ -0,0 +1,26 @@ +// RUN: mlir-translate --import-dxsa-bin %S/inputs/bool2.bin | FileCheck %s +// NOTE: Assertions have been autogenerated by utils/generate-test-checks.py + +// This script is intended to make adding checks to a test case quick and easy. +// It is *not* authoritative about what constitutes a good test. After using the +// script, be sure to review and refine the generated checks. For example, +// CHECK lines should be minimized and named to reflect the test’s intent. +// For comprehensive guidelines, see: +// * https://mlir.llvm.org/getting_started/TestingGuide/ + + +// CHECK-LABEL: dxsa.dcl_global_flags +// CHECK: dxsa.dcl_input_ps linear v<0, > +// CHECK: dxsa.dcl_input_ps linear v<0, > +// CHECK: dxsa.dcl_output o<0, > +// CHECK: dxsa.dcl_temps 1 +// CHECK: dxsa.lt r<0, >, v<0, >, v<0, > +// CHECK: %[[INDEX_0:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_0:.*]] = dxsa.operand %[[INDEX_0]] {mask = 16 : i32, num_components = 4 : i32, type = 2 : i32} +// CHECK: %[[INDEX_1:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_1:.*]] = dxsa.operand %[[INDEX_1]] {num_components = 4 : i32, one = 0 : i32, type = 0 : i32} +// CHECK: %[[OPERAND_2:.*]] = dxsa.operand.imm {imm = dense<0> : vector<1xi32>} +// CHECK: %[[OPERAND_3:.*]] = dxsa.operand.imm {imm = dense<1065353216> : vector<1xi32>} +// CHECK: dxsa.instruction "movc" %[[OPERAND_0]], %[[OPERAND_1]], %[[OPERAND_2]], %[[OPERAND_3]] +// CHECK: dxsa.instruction "ret" + diff --git a/mlir/test/Target/DXSA/hlsl/bufinfo.test b/mlir/test/Target/DXSA/hlsl/bufinfo.test new file mode 100644 index 000000000000..2ef0154b7deb --- /dev/null +++ b/mlir/test/Target/DXSA/hlsl/bufinfo.test @@ -0,0 +1,75 @@ +// RUN: mlir-translate --import-dxsa-bin %S/inputs/bufinfo.bin | FileCheck %s +// NOTE: Assertions have been autogenerated by utils/generate-test-checks.py + +// This script is intended to make adding checks to a test case quick and easy. +// It is *not* authoritative about what constitutes a good test. After using the +// script, be sure to review and refine the generated checks. For example, +// CHECK lines should be minimized and named to reflect the test’s intent. +// For comprehensive guidelines, see: +// * https://mlir.llvm.org/getting_started/TestingGuide/ + + +// CHECK-LABEL: dxsa.dcl_global_flags +// CHECK: dxsa.dcl_resource_structured +// CHECK: dxsa.dcl_resource_raw +// CHECK: dxsa.dcl_resource , , +// CHECK: dxsa.dcl_uav_structured +// CHECK: dxsa.dcl_uav_raw +// CHECK: dxsa.dcl_uav_typed , +// CHECK: dxsa.dcl_output o<0, > +// CHECK: dxsa.dcl_temps 1 +// CHECK: dxsa.unknown +// CHECK: %[[INDEX_0:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_0:.*]] = dxsa.operand %[[INDEX_0]] {mask = 16 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_1:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_1:.*]] = dxsa.operand %[[INDEX_1]] {num_components = 4 : i32, one = 0 : i32, type = 0 : i32} +// CHECK: %[[OPERAND_2:.*]] = dxsa.operand.imm {imm = dense<52> : vector<1xi32>} +// CHECK: dxsa.instruction "iadd" %[[OPERAND_0]], %[[OPERAND_1]], %[[OPERAND_2]] +// CHECK: dxsa.unknown +// CHECK: %[[INDEX_2:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_3:.*]] = dxsa.operand %[[INDEX_2]] {mask = 16 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_3:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_4:.*]] = dxsa.operand %[[INDEX_3]] {num_components = 4 : i32, one = 0 : i32, type = 0 : i32} +// CHECK: %[[INDEX_4:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_5:.*]] = dxsa.operand %[[INDEX_4]] {num_components = 4 : i32, one = 1 : i32, type = 0 : i32} +// CHECK: dxsa.instruction "iadd" %[[OPERAND_3]], %[[OPERAND_4]], %[[OPERAND_5]] +// CHECK: %[[INDEX_5:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_6:.*]] = dxsa.operand %[[INDEX_5]] {mask = 16 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_6:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_7:.*]] = dxsa.operand %[[INDEX_6]] {num_components = 4 : i32, one = 0 : i32, type = 0 : i32} +// CHECK: %[[OPERAND_8:.*]] = dxsa.operand.imm {imm = dense<52> : vector<1xi32>} +// CHECK: dxsa.instruction "iadd" %[[OPERAND_6]], %[[OPERAND_7]], %[[OPERAND_8]] +// CHECK: dxsa.unknown +// CHECK: %[[INDEX_7:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_9:.*]] = dxsa.operand %[[INDEX_7]] {mask = 16 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_8:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_10:.*]] = dxsa.operand %[[INDEX_8]] {num_components = 4 : i32, one = 1 : i32, type = 0 : i32} +// CHECK: %[[INDEX_9:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_11:.*]] = dxsa.operand %[[INDEX_9]] {num_components = 4 : i32, one = 0 : i32, type = 0 : i32} +// CHECK: dxsa.instruction "iadd" %[[OPERAND_9]], %[[OPERAND_10]], %[[OPERAND_11]] +// CHECK: dxsa.unknown +// CHECK: %[[INDEX_10:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_12:.*]] = dxsa.operand %[[INDEX_10]] {mask = 16 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_11:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_13:.*]] = dxsa.operand %[[INDEX_11]] {num_components = 4 : i32, one = 1 : i32, type = 0 : i32} +// CHECK: %[[INDEX_12:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_14:.*]] = dxsa.operand %[[INDEX_12]] {num_components = 4 : i32, one = 0 : i32, type = 0 : i32} +// CHECK: dxsa.instruction "iadd" %[[OPERAND_12]], %[[OPERAND_13]], %[[OPERAND_14]] +// CHECK: dxsa.unknown +// CHECK: %[[INDEX_13:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_15:.*]] = dxsa.operand %[[INDEX_13]] {mask = 16 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_14:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_16:.*]] = dxsa.operand %[[INDEX_14]] {num_components = 4 : i32, one = 1 : i32, type = 0 : i32} +// CHECK: %[[INDEX_15:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_17:.*]] = dxsa.operand %[[INDEX_15]] {num_components = 4 : i32, one = 0 : i32, type = 0 : i32} +// CHECK: dxsa.instruction "iadd" %[[OPERAND_15]], %[[OPERAND_16]], %[[OPERAND_17]] +// CHECK: dxsa.unknown +// CHECK: %[[INDEX_16:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_18:.*]] = dxsa.operand %[[INDEX_16]] {mask = 16 : i32, num_components = 4 : i32, type = 2 : i32} +// CHECK: %[[INDEX_17:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_19:.*]] = dxsa.operand %[[INDEX_17]] {num_components = 4 : i32, one = 1 : i32, type = 0 : i32} +// CHECK: %[[INDEX_18:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_20:.*]] = dxsa.operand %[[INDEX_18]] {num_components = 4 : i32, one = 0 : i32, type = 0 : i32} +// CHECK: dxsa.instruction "iadd" %[[OPERAND_18]], %[[OPERAND_19]], %[[OPERAND_20]] +// CHECK: dxsa.instruction "ret" + diff --git a/mlir/test/Target/DXSA/hlsl/calc_lod.test b/mlir/test/Target/DXSA/hlsl/calc_lod.test new file mode 100644 index 000000000000..e83a32678605 --- /dev/null +++ b/mlir/test/Target/DXSA/hlsl/calc_lod.test @@ -0,0 +1,50 @@ +// RUN: mlir-translate --import-dxsa-bin %S/inputs/calc_lod.bin | FileCheck %s +// NOTE: Assertions have been autogenerated by utils/generate-test-checks.py + +// This script is intended to make adding checks to a test case quick and easy. +// It is *not* authoritative about what constitutes a good test. After using the +// script, be sure to review and refine the generated checks. For example, +// CHECK lines should be minimized and named to reflect the test’s intent. +// For comprehensive guidelines, see: +// * https://mlir.llvm.org/getting_started/TestingGuide/ + + +// CHECK-LABEL: dxsa.dcl_global_flags +// CHECK: dxsa.dcl_sampler +// CHECK: dxsa.dcl_resource , , +// CHECK: dxsa.dcl_resource , , +// CHECK: dxsa.dcl_resource , , +// CHECK: dxsa.dcl_input_ps linear v<0, > +// CHECK: dxsa.dcl_output o<0> +// CHECK: dxsa.dcl_temps 1 +// CHECK: %[[INDEX_0:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_0:.*]] = dxsa.operand %[[INDEX_0]] {mask = 16 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_1:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_1:.*]] = dxsa.operand %[[INDEX_1]] {num_components = 4 : i32, swizzle = dense<[0, 1, 0, 0]> : vector<4xi32>, type = 1 : i32} +// CHECK: %[[INDEX_2:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_2:.*]] = dxsa.operand %[[INDEX_2]] {num_components = 4 : i32, one = 0 : i32, type = 7 : i32} +// CHECK: %[[INDEX_3:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_3:.*]] = dxsa.operand %[[INDEX_3]] {num_components = 0 : i32, type = 6 : i32} +// CHECK: dxsa.instruction "lod" %[[OPERAND_0]], %[[OPERAND_1]], %[[OPERAND_2]], %[[OPERAND_3]] +// CHECK: %[[INDEX_4:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_4:.*]] = dxsa.operand %[[INDEX_4]] {mask = 32 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_5:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_5:.*]] = dxsa.operand %[[INDEX_5]] {num_components = 4 : i32, swizzle = dense<[0, 1, 0, 0]> : vector<4xi32>, type = 1 : i32} +// CHECK: %[[INDEX_6:.*]] = dxsa.index.imm {imm = 1 : i32} +// CHECK: %[[OPERAND_6:.*]] = dxsa.operand %[[INDEX_6]] {num_components = 4 : i32, one = 0 : i32, type = 7 : i32} +// CHECK: %[[INDEX_7:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_7:.*]] = dxsa.operand %[[INDEX_7]] {num_components = 0 : i32, type = 6 : i32} +// CHECK: dxsa.instruction "lod" %[[OPERAND_4]], %[[OPERAND_5]], %[[OPERAND_6]], %[[OPERAND_7]] +// CHECK: dxsa.add r<0, >, r<0, >, r<0, > +// CHECK: %[[INDEX_8:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_8:.*]] = dxsa.operand %[[INDEX_8]] {mask = 32 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_9:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_9:.*]] = dxsa.operand %[[INDEX_9]] {num_components = 4 : i32, swizzle = dense<[0, 1, 2, 0]> : vector<4xi32>, type = 1 : i32} +// CHECK: %[[INDEX_10:.*]] = dxsa.index.imm {imm = 2 : i32} +// CHECK: %[[OPERAND_10:.*]] = dxsa.operand %[[INDEX_10]] {num_components = 4 : i32, one = 0 : i32, type = 7 : i32} +// CHECK: %[[INDEX_11:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_11:.*]] = dxsa.operand %[[INDEX_11]] {num_components = 0 : i32, type = 6 : i32} +// CHECK: dxsa.instruction "lod" %[[OPERAND_8]], %[[OPERAND_9]], %[[OPERAND_10]], %[[OPERAND_11]] +// CHECK: dxsa.add o<0>, r<0, >, r<0, > +// CHECK: dxsa.instruction "ret" + diff --git a/mlir/test/Target/DXSA/hlsl/call1.test b/mlir/test/Target/DXSA/hlsl/call1.test new file mode 100644 index 000000000000..66973a03503a --- /dev/null +++ b/mlir/test/Target/DXSA/hlsl/call1.test @@ -0,0 +1,69 @@ +// RUN: mlir-translate --import-dxsa-bin %S/inputs/call1.bin | FileCheck %s +// NOTE: Assertions have been autogenerated by utils/generate-test-checks.py + +// This script is intended to make adding checks to a test case quick and easy. +// It is *not* authoritative about what constitutes a good test. After using the +// script, be sure to review and refine the generated checks. For example, +// CHECK lines should be minimized and named to reflect the test’s intent. +// For comprehensive guidelines, see: +// * https://mlir.llvm.org/getting_started/TestingGuide/ + + +// CHECK-LABEL: dxsa.dcl_global_flags +// CHECK: dxsa.dcl_input_ps linear v<0, > +// CHECK: dxsa.dcl_input_ps constant v<1, > +// CHECK: dxsa.dcl_output o<0, > +// CHECK: dxsa.dcl_temps 1 +// CHECK: %[[INDEX_0:.*]] = dxsa.index.imm {imm = 1 : i32} +// CHECK: %[[OPERAND_0:.*]] = dxsa.operand %[[INDEX_0]] {num_components = 4 : i32, one = 0 : i32, type = 1 : i32} +// CHECK: dxsa.instruction "switch" %[[OPERAND_0]] +// CHECK: %[[OPERAND_1:.*]] = dxsa.operand.imm {imm = dense<1> : vector<1xi32>} +// CHECK: dxsa.instruction "case" %[[OPERAND_1]] +// CHECK: %[[INDEX_1:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_2:.*]] = dxsa.operand %[[INDEX_1]] {num_components = 0 : i32, type = 10 : i32} +// CHECK: dxsa.instruction "call" %[[OPERAND_2]] +// CHECK: dxsa.instruction "break" +// CHECK: %[[OPERAND_3:.*]] = dxsa.operand.imm {imm = dense<2> : vector<1xi32>} +// CHECK: dxsa.instruction "case" %[[OPERAND_3]] +// CHECK: %[[INDEX_2:.*]] = dxsa.index.imm {imm = 1 : i32} +// CHECK: %[[OPERAND_4:.*]] = dxsa.operand %[[INDEX_2]] {num_components = 0 : i32, type = 10 : i32} +// CHECK: dxsa.instruction "call" %[[OPERAND_4]] +// CHECK: dxsa.instruction "break" +// CHECK: dxsa.instruction "default" +// CHECK: %[[INDEX_3:.*]] = dxsa.index.imm {imm = 2 : i32} +// CHECK: %[[OPERAND_5:.*]] = dxsa.operand %[[INDEX_3]] {num_components = 0 : i32, type = 10 : i32} +// CHECK: dxsa.instruction "call" %[[OPERAND_5]] +// CHECK: dxsa.instruction "break" +// CHECK: dxsa.instruction "endswitch" +// CHECK: %[[INDEX_4:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_6:.*]] = dxsa.operand %[[INDEX_4]] {mask = 16 : i32, num_components = 4 : i32, type = 2 : i32} +// CHECK: %[[INDEX_5:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_7:.*]] = dxsa.operand %[[INDEX_5]] {num_components = 4 : i32, one = 0 : i32, type = 0 : i32} +// CHECK: dxsa.instruction "mov" %[[OPERAND_6]], %[[OPERAND_7]] +// CHECK: dxsa.instruction "ret" +// CHECK: %[[INDEX_6:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_8:.*]] = dxsa.operand %[[INDEX_6]] {num_components = 0 : i32, type = 10 : i32} +// CHECK: dxsa.instruction "label" %[[OPERAND_8]] +// CHECK: %[[INDEX_7:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_9:.*]] = dxsa.operand %[[INDEX_7]] {mask = 16 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[OPERAND_10:.*]] = dxsa.operand.imm {imm = dense<1084227584> : vector<1xi32>} +// CHECK: dxsa.instruction "mov" %[[OPERAND_9]], %[[OPERAND_10]] +// CHECK: dxsa.instruction "ret" +// CHECK: %[[INDEX_8:.*]] = dxsa.index.imm {imm = 1 : i32} +// CHECK: %[[OPERAND_11:.*]] = dxsa.operand %[[INDEX_8]] {num_components = 0 : i32, type = 10 : i32} +// CHECK: dxsa.instruction "label" %[[OPERAND_11]] +// CHECK: %[[INDEX_9:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_12:.*]] = dxsa.operand %[[INDEX_9]] {mask = 16 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_10:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_13:.*]] = dxsa.operand %[[INDEX_10]] {num_components = 4 : i32, one = 0 : i32, type = 1 : i32} +// CHECK: dxsa.instruction "mov" %[[OPERAND_12]], %[[OPERAND_13]] +// CHECK: dxsa.instruction "ret" +// CHECK: %[[INDEX_11:.*]] = dxsa.index.imm {imm = 2 : i32} +// CHECK: %[[OPERAND_14:.*]] = dxsa.operand %[[INDEX_11]] {num_components = 0 : i32, type = 10 : i32} +// CHECK: dxsa.instruction "label" %[[OPERAND_14]] +// CHECK: %[[INDEX_12:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_15:.*]] = dxsa.operand %[[INDEX_12]] {mask = 16 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[OPERAND_16:.*]] = dxsa.operand.imm {imm = dense<1077936128> : vector<1xi32>} +// CHECK: dxsa.instruction "mov" %[[OPERAND_15]], %[[OPERAND_16]] +// CHECK: dxsa.instruction "ret" + diff --git a/mlir/test/Target/DXSA/hlsl/call3.test b/mlir/test/Target/DXSA/hlsl/call3.test new file mode 100644 index 000000000000..ff6d0fdca9bb --- /dev/null +++ b/mlir/test/Target/DXSA/hlsl/call3.test @@ -0,0 +1,105 @@ +// RUN: mlir-translate --import-dxsa-bin %S/inputs/call3.bin | FileCheck %s +// NOTE: Assertions have been autogenerated by utils/generate-test-checks.py + +// This script is intended to make adding checks to a test case quick and easy. +// It is *not* authoritative about what constitutes a good test. After using the +// script, be sure to review and refine the generated checks. For example, +// CHECK lines should be minimized and named to reflect the test’s intent. +// For comprehensive guidelines, see: +// * https://mlir.llvm.org/getting_started/TestingGuide/ + + +// CHECK-LABEL: dxsa.dcl_global_flags +// CHECK: dxsa.dcl_input_ps linear v<0, > +// CHECK: dxsa.dcl_input_ps constant v<1, > +// CHECK: dxsa.dcl_output o<0, > +// CHECK: dxsa.dcl_temps 1 +// CHECK: %[[INDEX_0:.*]] = dxsa.index.imm {imm = 1 : i32} +// CHECK: %[[OPERAND_0:.*]] = dxsa.operand %[[INDEX_0]] {num_components = 4 : i32, one = 1 : i32, type = 1 : i32} +// CHECK: dxsa.instruction "if" %[[OPERAND_0]] +// CHECK: %[[INDEX_1:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_1:.*]] = dxsa.operand %[[INDEX_1]] {mask = 16 : i32, num_components = 4 : i32, type = 2 : i32} +// CHECK: %[[INDEX_2:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_2:.*]] = dxsa.operand %[[INDEX_2]] {num_components = 4 : i32, one = 1 : i32, type = 1 : i32} +// CHECK: dxsa.instruction "mov" %[[OPERAND_1]], %[[OPERAND_2]] +// CHECK: dxsa.instruction "ret" +// CHECK: dxsa.instruction "endif" +// CHECK: %[[INDEX_3:.*]] = dxsa.index.imm {imm = 1 : i32} +// CHECK: %[[OPERAND_3:.*]] = dxsa.operand %[[INDEX_3]] {num_components = 4 : i32, one = 0 : i32, type = 1 : i32} +// CHECK: dxsa.instruction "switch" %[[OPERAND_3]] +// CHECK: %[[OPERAND_4:.*]] = dxsa.operand.imm {imm = dense<1> : vector<1xi32>} +// CHECK: dxsa.instruction "case" %[[OPERAND_4]] +// CHECK: %[[INDEX_4:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_5:.*]] = dxsa.operand %[[INDEX_4]] {num_components = 0 : i32, type = 10 : i32} +// CHECK: dxsa.instruction "call" %[[OPERAND_5]] +// CHECK: dxsa.instruction "break" +// CHECK: %[[OPERAND_6:.*]] = dxsa.operand.imm {imm = dense<2> : vector<1xi32>} +// CHECK: dxsa.instruction "case" %[[OPERAND_6]] +// CHECK: %[[INDEX_5:.*]] = dxsa.index.imm {imm = 1 : i32} +// CHECK: %[[OPERAND_7:.*]] = dxsa.operand %[[INDEX_5]] {num_components = 0 : i32, type = 10 : i32} +// CHECK: dxsa.instruction "call" %[[OPERAND_7]] +// CHECK: dxsa.instruction "break" +// CHECK: dxsa.instruction "default" +// CHECK: %[[INDEX_6:.*]] = dxsa.index.imm {imm = 2 : i32} +// CHECK: %[[OPERAND_8:.*]] = dxsa.operand %[[INDEX_6]] {num_components = 0 : i32, type = 10 : i32} +// CHECK: dxsa.instruction "call" %[[OPERAND_8]] +// CHECK: dxsa.instruction "break" +// CHECK: dxsa.instruction "endswitch" +// CHECK: %[[INDEX_7:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_9:.*]] = dxsa.operand %[[INDEX_7]] {mask = 16 : i32, num_components = 4 : i32, type = 2 : i32} +// CHECK: %[[INDEX_8:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_10:.*]] = dxsa.operand %[[INDEX_8]] {num_components = 4 : i32, one = 0 : i32, type = 0 : i32} +// CHECK: dxsa.instruction "mov" %[[OPERAND_9]], %[[OPERAND_10]] +// CHECK: %[[INDEX_9:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_11:.*]] = dxsa.operand %[[INDEX_9]] {num_components = 4 : i32, one = 2 : i32, type = 0 : i32} +// CHECK: dxsa.instruction "retc" %[[OPERAND_11]] +// CHECK: %[[INDEX_10:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_12:.*]] = dxsa.operand %[[INDEX_10]] {mask = 16 : i32, num_components = 4 : i32, type = 2 : i32} +// CHECK: %[[INDEX_11:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_13:.*]] = dxsa.operand %[[INDEX_11]] {num_components = 4 : i32, one = 1 : i32, type = 0 : i32} +// CHECK: dxsa.instruction "mov" %[[OPERAND_12]], %[[OPERAND_13]] +// CHECK: dxsa.instruction "ret" +// CHECK: %[[INDEX_12:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_14:.*]] = dxsa.operand %[[INDEX_12]] {num_components = 0 : i32, type = 10 : i32} +// CHECK: dxsa.instruction "label" %[[OPERAND_14]] +// CHECK: %[[INDEX_13:.*]] = dxsa.index.imm {imm = 1 : i32} +// CHECK: %[[OPERAND_15:.*]] = dxsa.operand %[[INDEX_13]] {num_components = 4 : i32, one = 1 : i32, type = 1 : i32} +// CHECK: dxsa.instruction "if" %[[OPERAND_15]] +// CHECK: %[[INDEX_14:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_16:.*]] = dxsa.operand %[[INDEX_14]] {mask = 16 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_15:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_17:.*]] = dxsa.operand %[[INDEX_15]] {num_components = 4 : i32, one = 1 : i32, type = 1 : i32} +// CHECK: dxsa.instruction "mov" %[[OPERAND_16]], %[[OPERAND_17]] +// CHECK: %[[INDEX_16:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_18:.*]] = dxsa.operand %[[INDEX_16]] {mask = 64 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[OPERAND_19:.*]] = dxsa.operand.imm {imm = dense<-1> : vector<1xi32>} +// CHECK: dxsa.instruction "mov" %[[OPERAND_18]], %[[OPERAND_19]] +// CHECK: dxsa.instruction "ret" +// CHECK: dxsa.instruction "endif" +// CHECK: %[[INDEX_17:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_20:.*]] = dxsa.operand %[[INDEX_17]] {mask = 96 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[OPERAND_21:.*]] = dxsa.operand.imm {imm = dense<[0, 1084227584, 0, 0]> : vector<4xi32>} +// CHECK: dxsa.instruction "mov" %[[OPERAND_20]], %[[OPERAND_21]] +// CHECK: dxsa.instruction "ret" +// CHECK: %[[INDEX_18:.*]] = dxsa.index.imm {imm = 1 : i32} +// CHECK: %[[OPERAND_22:.*]] = dxsa.operand %[[INDEX_18]] {num_components = 0 : i32, type = 10 : i32} +// CHECK: dxsa.instruction "label" %[[OPERAND_22]] +// CHECK: %[[INDEX_19:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_23:.*]] = dxsa.operand %[[INDEX_19]] {mask = 32 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_20:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_24:.*]] = dxsa.operand %[[INDEX_20]] {num_components = 4 : i32, one = 0 : i32, type = 1 : i32} +// CHECK: dxsa.instruction "mov" %[[OPERAND_23]], %[[OPERAND_24]] +// CHECK: %[[INDEX_21:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_25:.*]] = dxsa.operand %[[INDEX_21]] {mask = 64 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[OPERAND_26:.*]] = dxsa.operand.imm {imm = dense<0> : vector<1xi32>} +// CHECK: dxsa.instruction "mov" %[[OPERAND_25]], %[[OPERAND_26]] +// CHECK: dxsa.instruction "ret" +// CHECK: %[[INDEX_22:.*]] = dxsa.index.imm {imm = 2 : i32} +// CHECK: %[[OPERAND_27:.*]] = dxsa.operand %[[INDEX_22]] {num_components = 0 : i32, type = 10 : i32} +// CHECK: dxsa.instruction "label" %[[OPERAND_27]] +// CHECK: %[[INDEX_23:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_28:.*]] = dxsa.operand %[[INDEX_23]] {mask = 96 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[OPERAND_29:.*]] = dxsa.operand.imm {imm = dense<[0, 1077936128, 0, 0]> : vector<4xi32>} +// CHECK: dxsa.instruction "mov" %[[OPERAND_28]], %[[OPERAND_29]] +// CHECK: dxsa.instruction "ret" + diff --git a/mlir/test/Target/DXSA/hlsl/cast1.test b/mlir/test/Target/DXSA/hlsl/cast1.test new file mode 100644 index 000000000000..6c10516efbe9 --- /dev/null +++ b/mlir/test/Target/DXSA/hlsl/cast1.test @@ -0,0 +1,17 @@ +// RUN: mlir-translate --import-dxsa-bin %S/inputs/cast1.bin | FileCheck %s +// NOTE: Assertions have been autogenerated by utils/generate-test-checks.py + +// This script is intended to make adding checks to a test case quick and easy. +// It is *not* authoritative about what constitutes a good test. After using the +// script, be sure to review and refine the generated checks. For example, +// CHECK lines should be minimized and named to reflect the test’s intent. +// For comprehensive guidelines, see: +// * https://mlir.llvm.org/getting_started/TestingGuide/ + + +// CHECK-LABEL: dxsa.dcl_global_flags +// CHECK: dxsa.dcl_input_ps constant v<0, > +// CHECK: dxsa.dcl_output o<0, > +// CHECK: dxsa.itof o<0, >, v<0, > +// CHECK: dxsa.instruction "ret" + diff --git a/mlir/test/Target/DXSA/hlsl/cast2.test b/mlir/test/Target/DXSA/hlsl/cast2.test new file mode 100644 index 000000000000..2c73e3397dff --- /dev/null +++ b/mlir/test/Target/DXSA/hlsl/cast2.test @@ -0,0 +1,17 @@ +// RUN: mlir-translate --import-dxsa-bin %S/inputs/cast2.bin | FileCheck %s +// NOTE: Assertions have been autogenerated by utils/generate-test-checks.py + +// This script is intended to make adding checks to a test case quick and easy. +// It is *not* authoritative about what constitutes a good test. After using the +// script, be sure to review and refine the generated checks. For example, +// CHECK lines should be minimized and named to reflect the test’s intent. +// For comprehensive guidelines, see: +// * https://mlir.llvm.org/getting_started/TestingGuide/ + + +// CHECK-LABEL: dxsa.dcl_global_flags +// CHECK: dxsa.dcl_input_ps constant v<0, > +// CHECK: dxsa.dcl_output o<0, > +// CHECK: dxsa.utof o<0, >, v<0, > +// CHECK: dxsa.instruction "ret" + diff --git a/mlir/test/Target/DXSA/hlsl/cast3.test b/mlir/test/Target/DXSA/hlsl/cast3.test new file mode 100644 index 000000000000..0e25e0ed0162 --- /dev/null +++ b/mlir/test/Target/DXSA/hlsl/cast3.test @@ -0,0 +1,17 @@ +// RUN: mlir-translate --import-dxsa-bin %S/inputs/cast3.bin | FileCheck %s +// NOTE: Assertions have been autogenerated by utils/generate-test-checks.py + +// This script is intended to make adding checks to a test case quick and easy. +// It is *not* authoritative about what constitutes a good test. After using the +// script, be sure to review and refine the generated checks. For example, +// CHECK lines should be minimized and named to reflect the test’s intent. +// For comprehensive guidelines, see: +// * https://mlir.llvm.org/getting_started/TestingGuide/ + + +// CHECK-LABEL: dxsa.dcl_global_flags +// CHECK: dxsa.dcl_input_ps linear v<0, > +// CHECK: dxsa.dcl_output o<0, > +// CHECK: dxsa.ftoi o<0, >, v<0, > +// CHECK: dxsa.instruction "ret" + diff --git a/mlir/test/Target/DXSA/hlsl/cast4.test b/mlir/test/Target/DXSA/hlsl/cast4.test new file mode 100644 index 000000000000..df9f4359fc9f --- /dev/null +++ b/mlir/test/Target/DXSA/hlsl/cast4.test @@ -0,0 +1,17 @@ +// RUN: mlir-translate --import-dxsa-bin %S/inputs/cast4.bin | FileCheck %s +// NOTE: Assertions have been autogenerated by utils/generate-test-checks.py + +// This script is intended to make adding checks to a test case quick and easy. +// It is *not* authoritative about what constitutes a good test. After using the +// script, be sure to review and refine the generated checks. For example, +// CHECK lines should be minimized and named to reflect the test’s intent. +// For comprehensive guidelines, see: +// * https://mlir.llvm.org/getting_started/TestingGuide/ + + +// CHECK-LABEL: dxsa.dcl_global_flags +// CHECK: dxsa.dcl_input_ps linear v<0, > +// CHECK: dxsa.dcl_output o<0, > +// CHECK: dxsa.ftou o<0, >, v<0, > +// CHECK: dxsa.instruction "ret" + diff --git a/mlir/test/Target/DXSA/hlsl/cast5.test b/mlir/test/Target/DXSA/hlsl/cast5.test new file mode 100644 index 000000000000..a7061094e09d --- /dev/null +++ b/mlir/test/Target/DXSA/hlsl/cast5.test @@ -0,0 +1,21 @@ +// RUN: mlir-translate --import-dxsa-bin %S/inputs/cast5.bin | FileCheck %s +// NOTE: Assertions have been autogenerated by utils/generate-test-checks.py + +// This script is intended to make adding checks to a test case quick and easy. +// It is *not* authoritative about what constitutes a good test. After using the +// script, be sure to review and refine the generated checks. For example, +// CHECK lines should be minimized and named to reflect the test’s intent. +// For comprehensive guidelines, see: +// * https://mlir.llvm.org/getting_started/TestingGuide/ + + +// CHECK-LABEL: dxsa.dcl_global_flags +// CHECK: dxsa.dcl_input_ps linear v<0, min16f, > +// CHECK: dxsa.dcl_output o<0, > +// CHECK: %[[INDEX_0:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_0:.*]] = dxsa.operand %[[INDEX_0]] {mask = 16 : i32, num_components = 4 : i32, type = 2 : i32} +// CHECK: %[[INDEX_1:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_1:.*]] = dxsa.operand %[[INDEX_1]] {min_precision = 1 : i32, num_components = 4 : i32, one = 0 : i32, type = 1 : i32} +// CHECK: dxsa.instruction "mov" %[[OPERAND_0]], %[[OPERAND_1]] +// CHECK: dxsa.instruction "ret" + diff --git a/mlir/test/Target/DXSA/hlsl/cast6.test b/mlir/test/Target/DXSA/hlsl/cast6.test new file mode 100644 index 000000000000..a9d5687069c9 --- /dev/null +++ b/mlir/test/Target/DXSA/hlsl/cast6.test @@ -0,0 +1,21 @@ +// RUN: mlir-translate --import-dxsa-bin %S/inputs/cast6.bin | FileCheck %s +// NOTE: Assertions have been autogenerated by utils/generate-test-checks.py + +// This script is intended to make adding checks to a test case quick and easy. +// It is *not* authoritative about what constitutes a good test. After using the +// script, be sure to review and refine the generated checks. For example, +// CHECK lines should be minimized and named to reflect the test’s intent. +// For comprehensive guidelines, see: +// * https://mlir.llvm.org/getting_started/TestingGuide/ + + +// CHECK-LABEL: dxsa.dcl_global_flags +// CHECK: dxsa.dcl_input_ps linear v<0, > +// CHECK: dxsa.dcl_output o<0, min16f, > +// CHECK: %[[INDEX_0:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_0:.*]] = dxsa.operand %[[INDEX_0]] {mask = 16 : i32, min_precision = 1 : i32, num_components = 4 : i32, type = 2 : i32} +// CHECK: %[[INDEX_1:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_1:.*]] = dxsa.operand %[[INDEX_1]] {num_components = 4 : i32, one = 0 : i32, type = 1 : i32} +// CHECK: dxsa.instruction "mov" %[[OPERAND_0]], %[[OPERAND_1]] +// CHECK: dxsa.instruction "ret" + diff --git a/mlir/test/Target/DXSA/hlsl/cbuffer1.50.test b/mlir/test/Target/DXSA/hlsl/cbuffer1.50.test new file mode 100644 index 000000000000..118713206653 --- /dev/null +++ b/mlir/test/Target/DXSA/hlsl/cbuffer1.50.test @@ -0,0 +1,22 @@ +// RUN: mlir-translate --import-dxsa-bin %S/inputs/cbuffer1.50.bin | FileCheck %s +// NOTE: Assertions have been autogenerated by utils/generate-test-checks.py + +// This script is intended to make adding checks to a test case quick and easy. +// It is *not* authoritative about what constitutes a good test. After using the +// script, be sure to review and refine the generated checks. For example, +// CHECK lines should be minimized and named to reflect the test’s intent. +// For comprehensive guidelines, see: +// * https://mlir.llvm.org/getting_started/TestingGuide/ + + +// CHECK-LABEL: dxsa.dcl_global_flags +// CHECK: dxsa.dcl_constant_buffer , +// CHECK: dxsa.dcl_output o<0> +// CHECK: %[[INDEX_0:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_0:.*]] = dxsa.operand %[[INDEX_0]] {mask = 240 : i32, num_components = 4 : i32, type = 2 : i32} +// CHECK: %[[INDEX_1:.*]] = dxsa.index.imm {imm = 5 : i32} +// CHECK: %[[INDEX_2:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_1:.*]] = dxsa.operand %[[INDEX_1]], %[[INDEX_2]] {num_components = 4 : i32, swizzle = dense<[0, 1, 2, 3]> : vector<4xi32>, type = 8 : i32} +// CHECK: dxsa.instruction "mov" %[[OPERAND_0]], %[[OPERAND_1]] +// CHECK: dxsa.instruction "ret" + diff --git a/mlir/test/Target/DXSA/hlsl/cbuffer1.51.test b/mlir/test/Target/DXSA/hlsl/cbuffer1.51.test new file mode 100644 index 000000000000..edc689932965 --- /dev/null +++ b/mlir/test/Target/DXSA/hlsl/cbuffer1.51.test @@ -0,0 +1,23 @@ +// RUN: mlir-translate --import-dxsa-bin %S/inputs/cbuffer1.51.bin | FileCheck %s +// NOTE: Assertions have been autogenerated by utils/generate-test-checks.py + +// This script is intended to make adding checks to a test case quick and easy. +// It is *not* authoritative about what constitutes a good test. After using the +// script, be sure to review and refine the generated checks. For example, +// CHECK lines should be minimized and named to reflect the test’s intent. +// For comprehensive guidelines, see: +// * https://mlir.llvm.org/getting_started/TestingGuide/ + + +// CHECK-LABEL: dxsa.dcl_global_flags +// CHECK: dxsa.dcl_constant_buffer , +// CHECK: dxsa.dcl_output o<0> +// CHECK: %[[INDEX_0:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_0:.*]] = dxsa.operand %[[INDEX_0]] {mask = 240 : i32, num_components = 4 : i32, type = 2 : i32} +// CHECK: %[[INDEX_1:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[INDEX_2:.*]] = dxsa.index.imm {imm = 5 : i32} +// CHECK: %[[INDEX_3:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_1:.*]] = dxsa.operand %[[INDEX_1]], %[[INDEX_2]], %[[INDEX_3]] {num_components = 4 : i32, swizzle = dense<[0, 1, 2, 3]> : vector<4xi32>, type = 8 : i32} +// CHECK: dxsa.instruction "mov" %[[OPERAND_0]], %[[OPERAND_1]] +// CHECK: dxsa.instruction "ret" + diff --git a/mlir/test/Target/DXSA/hlsl/cbuffer2.50.test b/mlir/test/Target/DXSA/hlsl/cbuffer2.50.test new file mode 100644 index 000000000000..af3489a1fdb3 --- /dev/null +++ b/mlir/test/Target/DXSA/hlsl/cbuffer2.50.test @@ -0,0 +1,22 @@ +// RUN: mlir-translate --import-dxsa-bin %S/inputs/cbuffer2.50.bin | FileCheck %s +// NOTE: Assertions have been autogenerated by utils/generate-test-checks.py + +// This script is intended to make adding checks to a test case quick and easy. +// It is *not* authoritative about what constitutes a good test. After using the +// script, be sure to review and refine the generated checks. For example, +// CHECK lines should be minimized and named to reflect the test’s intent. +// For comprehensive guidelines, see: +// * https://mlir.llvm.org/getting_started/TestingGuide/ + + +// CHECK-LABEL: dxsa.dcl_global_flags +// CHECK: dxsa.dcl_constant_buffer , +// CHECK: dxsa.dcl_output o<0> +// CHECK: %[[INDEX_0:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_0:.*]] = dxsa.operand %[[INDEX_0]] {mask = 240 : i32, num_components = 4 : i32, type = 2 : i32} +// CHECK: %[[INDEX_1:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[INDEX_2:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_1:.*]] = dxsa.operand %[[INDEX_1]], %[[INDEX_2]] {num_components = 4 : i32, swizzle = dense<[3, 1, 1, 1]> : vector<4xi32>, type = 8 : i32} +// CHECK: dxsa.instruction "mov" %[[OPERAND_0]], %[[OPERAND_1]] +// CHECK: dxsa.instruction "ret" + diff --git a/mlir/test/Target/DXSA/hlsl/cbuffer2.51.test b/mlir/test/Target/DXSA/hlsl/cbuffer2.51.test new file mode 100644 index 000000000000..aa029652dca5 --- /dev/null +++ b/mlir/test/Target/DXSA/hlsl/cbuffer2.51.test @@ -0,0 +1,23 @@ +// RUN: mlir-translate --import-dxsa-bin %S/inputs/cbuffer2.51.bin | FileCheck %s +// NOTE: Assertions have been autogenerated by utils/generate-test-checks.py + +// This script is intended to make adding checks to a test case quick and easy. +// It is *not* authoritative about what constitutes a good test. After using the +// script, be sure to review and refine the generated checks. For example, +// CHECK lines should be minimized and named to reflect the test’s intent. +// For comprehensive guidelines, see: +// * https://mlir.llvm.org/getting_started/TestingGuide/ + + +// CHECK-LABEL: dxsa.dcl_global_flags +// CHECK: dxsa.dcl_constant_buffer , +// CHECK: dxsa.dcl_output o<0> +// CHECK: %[[INDEX_0:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_0:.*]] = dxsa.operand %[[INDEX_0]] {mask = 240 : i32, num_components = 4 : i32, type = 2 : i32} +// CHECK: %[[INDEX_1:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[INDEX_2:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[INDEX_3:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_1:.*]] = dxsa.operand %[[INDEX_1]], %[[INDEX_2]], %[[INDEX_3]] {num_components = 4 : i32, swizzle = dense<[3, 1, 1, 1]> : vector<4xi32>, type = 8 : i32} +// CHECK: dxsa.instruction "mov" %[[OPERAND_0]], %[[OPERAND_1]] +// CHECK: dxsa.instruction "ret" + diff --git a/mlir/test/Target/DXSA/hlsl/cbuffer3.50.test b/mlir/test/Target/DXSA/hlsl/cbuffer3.50.test new file mode 100644 index 000000000000..4677489c6818 --- /dev/null +++ b/mlir/test/Target/DXSA/hlsl/cbuffer3.50.test @@ -0,0 +1,40 @@ +// RUN: mlir-translate --import-dxsa-bin %S/inputs/cbuffer3.50.bin | FileCheck %s +// NOTE: Assertions have been autogenerated by utils/generate-test-checks.py + +// This script is intended to make adding checks to a test case quick and easy. +// It is *not* authoritative about what constitutes a good test. After using the +// script, be sure to review and refine the generated checks. For example, +// CHECK lines should be minimized and named to reflect the test’s intent. +// For comprehensive guidelines, see: +// * https://mlir.llvm.org/getting_started/TestingGuide/ + + +// CHECK-LABEL: dxsa.dcl_global_flags +// CHECK: dxsa.dcl_constant_buffer , +// CHECK: dxsa.dcl_constant_buffer , +// CHECK: dxsa.dcl_input_ps constant v<0, > +// CHECK: dxsa.dcl_output o<0> +// CHECK: dxsa.dcl_temps 1 +// CHECK: %[[INDEX_0:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_0:.*]] = dxsa.operand %[[INDEX_0]] {mask = 16 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_1:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_1:.*]] = dxsa.operand %[[INDEX_1]] {num_components = 4 : i32, one = 0 : i32, type = 1 : i32} +// CHECK: dxsa.instruction "mov" %[[OPERAND_0]], %[[OPERAND_1]] +// CHECK: %[[INDEX_2:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_2:.*]] = dxsa.operand %[[INDEX_2]] {mask = 16 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_3:.*]] = dxsa.index.imm {imm = 1 : i32} +// CHECK: %[[INDEX_4:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_3:.*]] = dxsa.operand %[[INDEX_4]] {num_components = 4 : i32, one = 0 : i32, type = 0 : i32} +// CHECK: %[[INDEX_5:.*]] = dxsa.index.rel %[[OPERAND_3]] +// CHECK: %[[OPERAND_4:.*]] = dxsa.operand %[[INDEX_3]], %[[INDEX_5]] {num_components = 4 : i32, one = 2 : i32, type = 8 : i32} +// CHECK: dxsa.instruction "mov" %[[OPERAND_2]], %[[OPERAND_4]] +// CHECK: %[[INDEX_6:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_5:.*]] = dxsa.operand %[[INDEX_6]] {mask = 240 : i32, num_components = 4 : i32, type = 2 : i32} +// CHECK: %[[INDEX_7:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[INDEX_8:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_6:.*]] = dxsa.operand %[[INDEX_8]] {num_components = 4 : i32, one = 0 : i32, type = 0 : i32} +// CHECK: %[[INDEX_9:.*]] = dxsa.index.rel %[[OPERAND_6]] +// CHECK: %[[OPERAND_7:.*]] = dxsa.operand %[[INDEX_7]], %[[INDEX_9]] {num_components = 4 : i32, swizzle = dense<[3, 1, 1, 1]> : vector<4xi32>, type = 8 : i32} +// CHECK: dxsa.instruction "mov" %[[OPERAND_5]], %[[OPERAND_7]] +// CHECK: dxsa.instruction "ret" + diff --git a/mlir/test/Target/DXSA/hlsl/cbuffer3.51.test b/mlir/test/Target/DXSA/hlsl/cbuffer3.51.test new file mode 100644 index 000000000000..3d370b0d61ea --- /dev/null +++ b/mlir/test/Target/DXSA/hlsl/cbuffer3.51.test @@ -0,0 +1,52 @@ +// RUN: mlir-translate --import-dxsa-bin %S/inputs/cbuffer3.51.bin | FileCheck %s +// NOTE: Assertions have been autogenerated by utils/generate-test-checks.py + +// This script is intended to make adding checks to a test case quick and easy. +// It is *not* authoritative about what constitutes a good test. After using the +// script, be sure to review and refine the generated checks. For example, +// CHECK lines should be minimized and named to reflect the test’s intent. +// For comprehensive guidelines, see: +// * https://mlir.llvm.org/getting_started/TestingGuide/ + + +// CHECK-LABEL: dxsa.dcl_global_flags +// CHECK: dxsa.dcl_constant_buffer , +// CHECK: dxsa.dcl_constant_buffer , +// CHECK: dxsa.dcl_input_ps constant v<0, > +// CHECK: dxsa.dcl_output o<0> +// CHECK: dxsa.dcl_temps 1 +// CHECK: %[[INDEX_0:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_0:.*]] = dxsa.operand %[[INDEX_0]] {mask = 16 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_1:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_1:.*]] = dxsa.operand %[[INDEX_1]] {num_components = 4 : i32, one = 2 : i32, type = 1 : i32} +// CHECK: %[[OPERAND_2:.*]] = dxsa.operand.imm {imm = dense<12> : vector<1xi32>} +// CHECK: dxsa.instruction "iadd" %[[OPERAND_0]], %[[OPERAND_1]], %[[OPERAND_2]] +// CHECK: %[[INDEX_2:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_3:.*]] = dxsa.operand %[[INDEX_2]] {mask = 96 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_3:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_4:.*]] = dxsa.operand %[[INDEX_3]] {num_components = 4 : i32, swizzle = dense<[1, 1, 0, 1]> : vector<4xi32>, type = 1 : i32} +// CHECK: dxsa.instruction "mov" %[[OPERAND_3]], %[[OPERAND_4]] +// CHECK: %[[INDEX_4:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_5:.*]] = dxsa.operand %[[INDEX_4]] {mask = 32 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_5:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[INDEX_6:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_6:.*]] = dxsa.operand %[[INDEX_6]] {num_components = 4 : i32, one = 2 : i32, type = 0 : i32} +// CHECK: %[[INDEX_7:.*]] = dxsa.index.rel.imm %[[OPERAND_6]] {imm = 17 : i32, op = "add"} +// CHECK: %[[INDEX_8:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_7:.*]] = dxsa.operand %[[INDEX_8]] {num_components = 4 : i32, one = 1 : i32, type = 0 : i32} +// CHECK: %[[INDEX_9:.*]] = dxsa.index.rel %[[OPERAND_7]] +// CHECK: %[[OPERAND_8:.*]] = dxsa.operand %[[INDEX_5]], %[[INDEX_7]], %[[INDEX_9]] {num_components = 4 : i32, one = 2 : i32, type = 8 : i32} +// CHECK: dxsa.instruction "mov" %[[OPERAND_5]], %[[OPERAND_8]] +// CHECK: %[[INDEX_10:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_9:.*]] = dxsa.operand %[[INDEX_10]] {mask = 240 : i32, num_components = 4 : i32, type = 2 : i32} +// CHECK: %[[INDEX_11:.*]] = dxsa.index.imm {imm = 1 : i32} +// CHECK: %[[INDEX_12:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_10:.*]] = dxsa.operand %[[INDEX_12]] {num_components = 4 : i32, one = 1 : i32, type = 0 : i32} +// CHECK: %[[INDEX_13:.*]] = dxsa.index.rel.imm %[[OPERAND_10]] {imm = 77 : i32, op = "add"} +// CHECK: %[[INDEX_14:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_11:.*]] = dxsa.operand %[[INDEX_14]] {num_components = 4 : i32, one = 0 : i32, type = 0 : i32} +// CHECK: %[[INDEX_15:.*]] = dxsa.index.rel %[[OPERAND_11]] +// CHECK: %[[OPERAND_12:.*]] = dxsa.operand %[[INDEX_11]], %[[INDEX_13]], %[[INDEX_15]] {num_components = 4 : i32, swizzle = dense<[3, 1, 1, 1]> : vector<4xi32>, type = 8 : i32} +// CHECK: dxsa.instruction "mov" %[[OPERAND_9]], %[[OPERAND_12]] +// CHECK: dxsa.instruction "ret" + diff --git a/mlir/test/Target/DXSA/hlsl/cmp1.test b/mlir/test/Target/DXSA/hlsl/cmp1.test new file mode 100644 index 000000000000..1152b8ae17cd --- /dev/null +++ b/mlir/test/Target/DXSA/hlsl/cmp1.test @@ -0,0 +1,18 @@ +// RUN: mlir-translate --import-dxsa-bin %S/inputs/cmp1.bin | FileCheck %s +// NOTE: Assertions have been autogenerated by utils/generate-test-checks.py + +// This script is intended to make adding checks to a test case quick and easy. +// It is *not* authoritative about what constitutes a good test. After using the +// script, be sure to review and refine the generated checks. For example, +// CHECK lines should be minimized and named to reflect the test’s intent. +// For comprehensive guidelines, see: +// * https://mlir.llvm.org/getting_started/TestingGuide/ + + +// CHECK-LABEL: dxsa.dcl_global_flags +// CHECK: dxsa.dcl_input_ps linear v<0, > +// CHECK: dxsa.dcl_input_ps linear v<0, > +// CHECK: dxsa.dcl_output o<0, > +// CHECK: dxsa.eq o<0, >, v<0, >, v<0, > +// CHECK: dxsa.instruction "ret" + diff --git a/mlir/test/Target/DXSA/hlsl/constoperand1.test b/mlir/test/Target/DXSA/hlsl/constoperand1.test new file mode 100644 index 000000000000..1bfbc4393dd9 --- /dev/null +++ b/mlir/test/Target/DXSA/hlsl/constoperand1.test @@ -0,0 +1,19 @@ +// RUN: mlir-translate --import-dxsa-bin %S/inputs/constoperand1.bin | FileCheck %s +// NOTE: Assertions have been autogenerated by utils/generate-test-checks.py + +// This script is intended to make adding checks to a test case quick and easy. +// It is *not* authoritative about what constitutes a good test. After using the +// script, be sure to review and refine the generated checks. For example, +// CHECK lines should be minimized and named to reflect the test’s intent. +// For comprehensive guidelines, see: +// * https://mlir.llvm.org/getting_started/TestingGuide/ + + +// CHECK-LABEL: dxsa.dcl_global_flags +// CHECK: dxsa.dcl_output_siv o<0>, +// CHECK: %[[INDEX_0:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_0:.*]] = dxsa.operand %[[INDEX_0]] {mask = 240 : i32, num_components = 4 : i32, type = 2 : i32} +// CHECK: %[[OPERAND_1:.*]] = dxsa.operand.imm {imm = dense<[1077936128, 0, 1056964608, 1039979355]> : vector<4xi32>} +// CHECK: dxsa.instruction "mov" %[[OPERAND_0]], %[[OPERAND_1]] +// CHECK: dxsa.instruction "ret" + diff --git a/mlir/test/Target/DXSA/hlsl/cs1.test b/mlir/test/Target/DXSA/hlsl/cs1.test new file mode 100644 index 000000000000..3a9013e420f8 --- /dev/null +++ b/mlir/test/Target/DXSA/hlsl/cs1.test @@ -0,0 +1,53 @@ +// RUN: mlir-translate --import-dxsa-bin %S/inputs/cs1.bin | FileCheck %s +// NOTE: Assertions have been autogenerated by utils/generate-test-checks.py + +// This script is intended to make adding checks to a test case quick and easy. +// It is *not* authoritative about what constitutes a good test. After using the +// script, be sure to review and refine the generated checks. For example, +// CHECK lines should be minimized and named to reflect the test’s intent. +// For comprehensive guidelines, see: +// * https://mlir.llvm.org/getting_started/TestingGuide/ + + +// CHECK-LABEL: dxsa.dcl_global_flags +// CHECK: dxsa.dcl_uav_raw +// CHECK: dxsa.dcl_input vThreadIDInGroupFlattened +// CHECK: dxsa.dcl_input vThreadGroupID<> +// CHECK: dxsa.dcl_input vThreadIDInGroup<> +// CHECK: dxsa.dcl_input vThreadID<> +// CHECK: dxsa.dcl_temps 1 +// CHECK: dxsa.dcl_thread_group +// CHECK: dxsa.ishl r<0, >, vThreadID<>, l(0x7) +// CHECK: dxsa.ishl r<0, >, vThreadGroupID<>, l(0xA) +// CHECK: %[[INDEX_0:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_0:.*]] = dxsa.operand %[[INDEX_0]] {mask = 16 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_1:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_1:.*]] = dxsa.operand %[[INDEX_1]] {num_components = 4 : i32, one = 1 : i32, type = 0 : i32} +// CHECK: %[[INDEX_2:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_2:.*]] = dxsa.operand %[[INDEX_2]] {num_components = 4 : i32, one = 0 : i32, type = 0 : i32} +// CHECK: dxsa.instruction "iadd" %[[OPERAND_0]], %[[OPERAND_1]], %[[OPERAND_2]] +// CHECK: %[[INDEX_3:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_3:.*]] = dxsa.operand %[[INDEX_3]] {mask = 16 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_4:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_4:.*]] = dxsa.operand %[[INDEX_4]] {num_components = 4 : i32, one = 0 : i32, type = 0 : i32} +// CHECK: %[[OPERAND_5:.*]] = dxsa.operand {num_components = 4 : i32, one = 2 : i32, type = 34 : i32} +// CHECK: dxsa.instruction "iadd" %[[OPERAND_3]], %[[OPERAND_4]], %[[OPERAND_5]] +// CHECK: %[[INDEX_5:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_6:.*]] = dxsa.operand %[[INDEX_5]] {mask = 16 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_6:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_7:.*]] = dxsa.operand %[[INDEX_6]] {num_components = 4 : i32, one = 0 : i32, type = 0 : i32} +// CHECK: %[[OPERAND_8:.*]] = dxsa.operand {num_components = 4 : i32, one = 0 : i32, type = 36 : i32} +// CHECK: dxsa.instruction "iadd" %[[OPERAND_6]], %[[OPERAND_7]], %[[OPERAND_8]] +// CHECK: dxsa.unknown +// CHECK: dxsa.add r<0, >, r<0, >, l(0x40400000) +// CHECK: dxsa.instruction "sync" +// CHECK: %[[INDEX_7:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_9:.*]] = dxsa.operand %[[INDEX_7]] {mask = 16 : i32, num_components = 4 : i32, type = 30 : i32} +// CHECK: %[[INDEX_8:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_10:.*]] = dxsa.operand %[[INDEX_8]] {num_components = 4 : i32, one = 0 : i32, type = 0 : i32} +// CHECK: %[[INDEX_9:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_11:.*]] = dxsa.operand %[[INDEX_9]] {num_components = 4 : i32, one = 1 : i32, type = 0 : i32} +// CHECK: dxsa.instruction "store_raw" %[[OPERAND_9]], %[[OPERAND_10]], %[[OPERAND_11]] +// CHECK: dxsa.instruction "sync" +// CHECK: dxsa.instruction "ret" + diff --git a/mlir/test/Target/DXSA/hlsl/cs2.test b/mlir/test/Target/DXSA/hlsl/cs2.test new file mode 100644 index 000000000000..a5dc33a053a2 --- /dev/null +++ b/mlir/test/Target/DXSA/hlsl/cs2.test @@ -0,0 +1,113 @@ +// RUN: mlir-translate --import-dxsa-bin %S/inputs/cs2.bin | FileCheck %s +// NOTE: Assertions have been autogenerated by utils/generate-test-checks.py + +// This script is intended to make adding checks to a test case quick and easy. +// It is *not* authoritative about what constitutes a good test. After using the +// script, be sure to review and refine the generated checks. For example, +// CHECK lines should be minimized and named to reflect the test’s intent. +// For comprehensive guidelines, see: +// * https://mlir.llvm.org/getting_started/TestingGuide/ + + +// CHECK-LABEL: dxsa.dcl_global_flags +// CHECK: dxsa.dcl_constant_buffer , +// CHECK: dxsa.dcl_uav_raw +// CHECK: dxsa.dcl_input vThreadIDInGroupFlattened +// CHECK: dxsa.dcl_input vThreadGroupID<> +// CHECK: dxsa.dcl_input vThreadIDInGroup<> +// CHECK: dxsa.dcl_input vThreadID<> +// CHECK: dxsa.dcl_temps 3 +// CHECK: dxsa.dcl_tgsm_structured g<0>, 16, 384 +// CHECK: dxsa.dcl_thread_group +// CHECK: dxsa.ishl r<0, >, vThreadID<>, l(0x7) +// CHECK: dxsa.ishl r<0, >, vThreadGroupID<>, l(0xA) +// CHECK: %[[INDEX_0:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_0:.*]] = dxsa.operand %[[INDEX_0]] {mask = 16 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_1:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_1:.*]] = dxsa.operand %[[INDEX_1]] {num_components = 4 : i32, one = 1 : i32, type = 0 : i32} +// CHECK: %[[INDEX_2:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_2:.*]] = dxsa.operand %[[INDEX_2]] {num_components = 4 : i32, one = 0 : i32, type = 0 : i32} +// CHECK: dxsa.instruction "iadd" %[[OPERAND_0]], %[[OPERAND_1]], %[[OPERAND_2]] +// CHECK: %[[INDEX_3:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_3:.*]] = dxsa.operand %[[INDEX_3]] {mask = 16 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_4:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_4:.*]] = dxsa.operand %[[INDEX_4]] {num_components = 4 : i32, one = 0 : i32, type = 0 : i32} +// CHECK: %[[OPERAND_5:.*]] = dxsa.operand {num_components = 4 : i32, one = 2 : i32, type = 34 : i32} +// CHECK: dxsa.instruction "iadd" %[[OPERAND_3]], %[[OPERAND_4]], %[[OPERAND_5]] +// CHECK: %[[INDEX_5:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_6:.*]] = dxsa.operand %[[INDEX_5]] {mask = 16 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_6:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_7:.*]] = dxsa.operand %[[INDEX_6]] {num_components = 4 : i32, one = 0 : i32, type = 0 : i32} +// CHECK: %[[OPERAND_8:.*]] = dxsa.operand {num_components = 4 : i32, one = 0 : i32, type = 36 : i32} +// CHECK: dxsa.instruction "iadd" %[[OPERAND_6]], %[[OPERAND_7]], %[[OPERAND_8]] +// CHECK: dxsa.unknown +// CHECK: dxsa.add r<1, min16f, >, r<0, >, l(0x40000000) +// CHECK: %[[INDEX_7:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_9:.*]] = dxsa.operand %[[INDEX_7]] {mask = 16 : i32, num_components = 4 : i32, type = 31 : i32} +// CHECK: %[[OPERAND_10:.*]] = dxsa.operand {num_components = 4 : i32, one = 0 : i32, type = 36 : i32} +// CHECK: %[[OPERAND_11:.*]] = dxsa.operand.imm {imm = dense<4> : vector<1xi32>} +// CHECK: %[[INDEX_8:.*]] = dxsa.index.imm {imm = 1 : i32} +// CHECK: %[[OPERAND_12:.*]] = dxsa.operand %[[INDEX_8]] {min_precision = 1 : i32, num_components = 4 : i32, one = 0 : i32, type = 0 : i32} +// CHECK: dxsa.instruction "store_structured" %[[OPERAND_9]], %[[OPERAND_10]], %[[OPERAND_11]], %[[OPERAND_12]] +// CHECK: %[[INDEX_9:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_13:.*]] = dxsa.operand %[[INDEX_9]] {mask = 16 : i32, num_components = 4 : i32, type = 31 : i32} +// CHECK: %[[OPERAND_14:.*]] = dxsa.operand {num_components = 4 : i32, one = 0 : i32, type = 36 : i32} +// CHECK: %[[OPERAND_15:.*]] = dxsa.operand.imm {imm = dense<8> : vector<1xi32>} +// CHECK: %[[INDEX_10:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_16:.*]] = dxsa.operand %[[INDEX_10]] {num_components = 4 : i32, one = 1 : i32, type = 0 : i32} +// CHECK: dxsa.instruction "store_structured" %[[OPERAND_13]], %[[OPERAND_14]], %[[OPERAND_15]], %[[OPERAND_16]] +// CHECK: dxsa.ftoi r<2, min16i, >, r<0, > +// CHECK: %[[INDEX_11:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_17:.*]] = dxsa.operand %[[INDEX_11]] {mask = 16 : i32, num_components = 4 : i32, type = 31 : i32} +// CHECK: %[[OPERAND_18:.*]] = dxsa.operand {num_components = 4 : i32, one = 0 : i32, type = 36 : i32} +// CHECK: %[[OPERAND_19:.*]] = dxsa.operand.imm {imm = dense<12> : vector<1xi32>} +// CHECK: %[[INDEX_12:.*]] = dxsa.index.imm {imm = 2 : i32} +// CHECK: %[[OPERAND_20:.*]] = dxsa.operand %[[INDEX_12]] {min_precision = 4 : i32, num_components = 4 : i32, one = 0 : i32, type = 0 : i32} +// CHECK: dxsa.instruction "store_structured" %[[OPERAND_17]], %[[OPERAND_18]], %[[OPERAND_19]], %[[OPERAND_20]] +// CHECK: dxsa.instruction "sync" +// CHECK: %[[INDEX_13:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_21:.*]] = dxsa.operand %[[INDEX_13]] {mask = 64 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[OPERAND_22:.*]] = dxsa.operand {num_components = 4 : i32, one = 0 : i32, type = 36 : i32} +// CHECK: %[[INDEX_14:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[INDEX_15:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_23:.*]] = dxsa.operand %[[INDEX_14]], %[[INDEX_15]] {num_components = 4 : i32, one = 0 : i32, type = 8 : i32} +// CHECK: dxsa.instruction "iadd" %[[OPERAND_21]], %[[OPERAND_22]], %[[OPERAND_23]] +// CHECK: %[[INDEX_16:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_24:.*]] = dxsa.operand %[[INDEX_16]] {mask = 128 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_17:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_25:.*]] = dxsa.operand %[[INDEX_17]] {num_components = 4 : i32, one = 2 : i32, type = 0 : i32} +// CHECK: %[[OPERAND_26:.*]] = dxsa.operand.imm {imm = dense<8> : vector<1xi32>} +// CHECK: %[[INDEX_18:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_27:.*]] = dxsa.operand %[[INDEX_18]] {num_components = 4 : i32, swizzle = dense<0> : vector<4xi32>, type = 31 : i32} +// CHECK: dxsa.instruction "ld_structured" %[[OPERAND_24]], %[[OPERAND_25]], %[[OPERAND_26]], %[[OPERAND_27]] +// CHECK: dxsa.add r<0, >, r<0, >, r<0, > +// CHECK: %[[INDEX_19:.*]] = dxsa.index.imm {imm = 2 : i32} +// CHECK: %[[OPERAND_28:.*]] = dxsa.operand %[[INDEX_19]] {mask = 16 : i32, min_precision = 4 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_20:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_29:.*]] = dxsa.operand %[[INDEX_20]] {num_components = 4 : i32, one = 2 : i32, type = 0 : i32} +// CHECK: %[[OPERAND_30:.*]] = dxsa.operand.imm {imm = dense<12> : vector<1xi32>} +// CHECK: %[[INDEX_21:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_31:.*]] = dxsa.operand %[[INDEX_21]] {num_components = 4 : i32, swizzle = dense<0> : vector<4xi32>, type = 31 : i32} +// CHECK: dxsa.instruction "ld_structured" %[[OPERAND_28]], %[[OPERAND_29]], %[[OPERAND_30]], %[[OPERAND_31]] +// CHECK: dxsa.itof r<0, >, r<2, min16i, > +// CHECK: dxsa.add r<0, >, r<0, >, r<0, > +// CHECK: dxsa.instruction "sync" +// CHECK: dxsa.instruction "sync" +// CHECK: %[[INDEX_22:.*]] = dxsa.index.imm {imm = 1 : i32} +// CHECK: %[[OPERAND_32:.*]] = dxsa.operand %[[INDEX_22]] {mask = 16 : i32, min_precision = 1 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_23:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_33:.*]] = dxsa.operand %[[INDEX_23]] {num_components = 4 : i32, one = 2 : i32, type = 0 : i32} +// CHECK: %[[OPERAND_34:.*]] = dxsa.operand.imm {imm = dense<4> : vector<1xi32>} +// CHECK: %[[INDEX_24:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_35:.*]] = dxsa.operand %[[INDEX_24]] {num_components = 4 : i32, swizzle = dense<0> : vector<4xi32>, type = 31 : i32} +// CHECK: dxsa.instruction "ld_structured" %[[OPERAND_32]], %[[OPERAND_33]], %[[OPERAND_34]], %[[OPERAND_35]] +// CHECK: dxsa.add r<0, >, r<0, >, r<1, min16f, > +// CHECK: %[[INDEX_25:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_36:.*]] = dxsa.operand %[[INDEX_25]] {mask = 16 : i32, num_components = 4 : i32, type = 30 : i32} +// CHECK: %[[INDEX_26:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_37:.*]] = dxsa.operand %[[INDEX_26]] {num_components = 4 : i32, one = 0 : i32, type = 0 : i32} +// CHECK: %[[INDEX_27:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_38:.*]] = dxsa.operand %[[INDEX_27]] {num_components = 4 : i32, one = 1 : i32, type = 0 : i32} +// CHECK: dxsa.instruction "store_raw" %[[OPERAND_36]], %[[OPERAND_37]], %[[OPERAND_38]] +// CHECK: dxsa.instruction "ret" + diff --git a/mlir/test/Target/DXSA/hlsl/cs4.test b/mlir/test/Target/DXSA/hlsl/cs4.test new file mode 100644 index 000000000000..7ad619584340 --- /dev/null +++ b/mlir/test/Target/DXSA/hlsl/cs4.test @@ -0,0 +1,120 @@ +// RUN: mlir-translate --import-dxsa-bin %S/inputs/cs4.bin | FileCheck %s +// NOTE: Assertions have been autogenerated by utils/generate-test-checks.py + +// This script is intended to make adding checks to a test case quick and easy. +// It is *not* authoritative about what constitutes a good test. After using the +// script, be sure to review and refine the generated checks. For example, +// CHECK lines should be minimized and named to reflect the test’s intent. +// For comprehensive guidelines, see: +// * https://mlir.llvm.org/getting_started/TestingGuide/ + + +// CHECK-LABEL: dxsa.dcl_global_flags +// CHECK: dxsa.dcl_constant_buffer , +// CHECK: dxsa.dcl_uav_raw +// CHECK: dxsa.dcl_input vThreadIDInGroupFlattened +// CHECK: dxsa.dcl_input vThreadGroupID<> +// CHECK: dxsa.dcl_input vThreadIDInGroup<> +// CHECK: dxsa.dcl_input vThreadID<> +// CHECK: dxsa.dcl_temps 3 +// CHECK: dxsa.dcl_tgsm_structured g<0>, 20, 384 +// CHECK: dxsa.dcl_thread_group +// CHECK: dxsa.ishl r<0, >, vThreadID<>, l(0x7) +// CHECK: dxsa.ishl r<0, >, vThreadGroupID<>, l(0xA) +// CHECK: %[[INDEX_0:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_0:.*]] = dxsa.operand %[[INDEX_0]] {mask = 16 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_1:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_1:.*]] = dxsa.operand %[[INDEX_1]] {num_components = 4 : i32, one = 1 : i32, type = 0 : i32} +// CHECK: %[[INDEX_2:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_2:.*]] = dxsa.operand %[[INDEX_2]] {num_components = 4 : i32, one = 0 : i32, type = 0 : i32} +// CHECK: dxsa.instruction "iadd" %[[OPERAND_0]], %[[OPERAND_1]], %[[OPERAND_2]] +// CHECK: %[[INDEX_3:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_3:.*]] = dxsa.operand %[[INDEX_3]] {mask = 16 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_4:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_4:.*]] = dxsa.operand %[[INDEX_4]] {num_components = 4 : i32, one = 0 : i32, type = 0 : i32} +// CHECK: %[[OPERAND_5:.*]] = dxsa.operand {num_components = 4 : i32, one = 2 : i32, type = 34 : i32} +// CHECK: dxsa.instruction "iadd" %[[OPERAND_3]], %[[OPERAND_4]], %[[OPERAND_5]] +// CHECK: %[[INDEX_5:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_6:.*]] = dxsa.operand %[[INDEX_5]] {mask = 16 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_6:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_7:.*]] = dxsa.operand %[[INDEX_6]] {num_components = 4 : i32, one = 0 : i32, type = 0 : i32} +// CHECK: %[[OPERAND_8:.*]] = dxsa.operand {num_components = 4 : i32, one = 0 : i32, type = 36 : i32} +// CHECK: dxsa.instruction "iadd" %[[OPERAND_6]], %[[OPERAND_7]], %[[OPERAND_8]] +// CHECK: dxsa.unknown +// CHECK: dxsa.ftou r<0, >, r<0, > +// CHECK: %[[INDEX_7:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_9:.*]] = dxsa.operand %[[INDEX_7]] {mask = 16 : i32, num_components = 4 : i32, type = 31 : i32} +// CHECK: %[[OPERAND_10:.*]] = dxsa.operand {num_components = 4 : i32, one = 0 : i32, type = 36 : i32} +// CHECK: %[[OPERAND_11:.*]] = dxsa.operand.imm {imm = dense<16> : vector<1xi32>} +// CHECK: %[[INDEX_8:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_12:.*]] = dxsa.operand %[[INDEX_8]] {num_components = 4 : i32, one = 2 : i32, type = 0 : i32} +// CHECK: dxsa.instruction "store_structured" %[[OPERAND_9]], %[[OPERAND_10]], %[[OPERAND_11]], %[[OPERAND_12]] +// CHECK: %[[INDEX_9:.*]] = dxsa.index.imm {imm = 1 : i32} +// CHECK: %[[OPERAND_13:.*]] = dxsa.operand %[[INDEX_9]] {mask = 16 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[OPERAND_14:.*]] = dxsa.operand {num_components = 4 : i32, one = 0 : i32, type = 36 : i32} +// CHECK: dxsa.instruction "mov" %[[OPERAND_13]], %[[OPERAND_14]] +// CHECK: %[[INDEX_10:.*]] = dxsa.index.imm {imm = 1 : i32} +// CHECK: %[[OPERAND_15:.*]] = dxsa.operand %[[INDEX_10]] {mask = 32 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[OPERAND_16:.*]] = dxsa.operand.imm {imm = dense<16> : vector<1xi32>} +// CHECK: dxsa.instruction "mov" %[[OPERAND_15]], %[[OPERAND_16]] +// CHECK: %[[INDEX_11:.*]] = dxsa.index.imm {imm = 2 : i32} +// CHECK: %[[OPERAND_17:.*]] = dxsa.operand %[[INDEX_11]] {mask = 16 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_12:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_18:.*]] = dxsa.operand %[[INDEX_12]] {num_components = 0 : i32, type = 31 : i32} +// CHECK: %[[INDEX_13:.*]] = dxsa.index.imm {imm = 1 : i32} +// CHECK: %[[OPERAND_19:.*]] = dxsa.operand %[[INDEX_13]] {num_components = 4 : i32, swizzle = dense<[0, 1, 0, 0]> : vector<4xi32>, type = 0 : i32} +// CHECK: %[[OPERAND_20:.*]] = dxsa.operand {num_components = 4 : i32, one = 0 : i32, type = 32 : i32} +// CHECK: dxsa.instruction "imm_atomic_iadd" %[[OPERAND_17]], %[[OPERAND_18]], %[[OPERAND_19]], %[[OPERAND_20]] +// CHECK: %[[INDEX_14:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_21:.*]] = dxsa.operand %[[INDEX_14]] {num_components = 0 : i32, type = 31 : i32} +// CHECK: %[[INDEX_15:.*]] = dxsa.index.imm {imm = 1 : i32} +// CHECK: %[[OPERAND_22:.*]] = dxsa.operand %[[INDEX_15]] {num_components = 4 : i32, swizzle = dense<[0, 1, 0, 0]> : vector<4xi32>, type = 0 : i32} +// CHECK: %[[OPERAND_23:.*]] = dxsa.operand {num_components = 4 : i32, one = 0 : i32, type = 32 : i32} +// CHECK: dxsa.instruction "atomic_or" %[[OPERAND_21]], %[[OPERAND_22]], %[[OPERAND_23]] +// CHECK: dxsa.utof r<0, >, r<2, > +// CHECK: dxsa.add r<0, >, r<0, >, r<0, > +// CHECK: %[[INDEX_16:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_24:.*]] = dxsa.operand %[[INDEX_16]] {num_components = 0 : i32, type = 31 : i32} +// CHECK: %[[INDEX_17:.*]] = dxsa.index.imm {imm = 1 : i32} +// CHECK: %[[OPERAND_25:.*]] = dxsa.operand %[[INDEX_17]] {num_components = 4 : i32, swizzle = dense<[0, 1, 0, 0]> : vector<4xi32>, type = 0 : i32} +// CHECK: %[[OPERAND_26:.*]] = dxsa.operand {num_components = 4 : i32, one = 1 : i32, type = 33 : i32} +// CHECK: %[[OPERAND_27:.*]] = dxsa.operand {num_components = 4 : i32, one = 0 : i32, type = 32 : i32} +// CHECK: dxsa.instruction "atomic_cmp_store" %[[OPERAND_24]], %[[OPERAND_25]], %[[OPERAND_26]], %[[OPERAND_27]] +// CHECK: %[[INDEX_18:.*]] = dxsa.index.imm {imm = 1 : i32} +// CHECK: %[[OPERAND_28:.*]] = dxsa.operand %[[INDEX_18]] {mask = 16 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_19:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_29:.*]] = dxsa.operand %[[INDEX_19]] {num_components = 0 : i32, type = 31 : i32} +// CHECK: %[[INDEX_20:.*]] = dxsa.index.imm {imm = 1 : i32} +// CHECK: %[[OPERAND_30:.*]] = dxsa.operand %[[INDEX_20]] {num_components = 4 : i32, swizzle = dense<[0, 1, 0, 0]> : vector<4xi32>, type = 0 : i32} +// CHECK: %[[OPERAND_31:.*]] = dxsa.operand {num_components = 4 : i32, one = 1 : i32, type = 33 : i32} +// CHECK: %[[OPERAND_32:.*]] = dxsa.operand {num_components = 4 : i32, one = 0 : i32, type = 32 : i32} +// CHECK: dxsa.instruction "imm_atomic_cmp_exch" %[[OPERAND_28]], %[[OPERAND_29]], %[[OPERAND_30]], %[[OPERAND_31]], %[[OPERAND_32]] +// CHECK: dxsa.instruction "sync" +// CHECK: dxsa.utof r<0, >, r<1, > +// CHECK: dxsa.add r<0, >, r<0, >, r<0, > +// CHECK: %[[INDEX_21:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_33:.*]] = dxsa.operand %[[INDEX_21]] {mask = 64 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[OPERAND_34:.*]] = dxsa.operand {num_components = 4 : i32, one = 0 : i32, type = 36 : i32} +// CHECK: %[[INDEX_22:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[INDEX_23:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_35:.*]] = dxsa.operand %[[INDEX_22]], %[[INDEX_23]] {num_components = 4 : i32, one = 0 : i32, type = 8 : i32} +// CHECK: dxsa.instruction "iadd" %[[OPERAND_33]], %[[OPERAND_34]], %[[OPERAND_35]] +// CHECK: %[[INDEX_24:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_36:.*]] = dxsa.operand %[[INDEX_24]] {mask = 64 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_25:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_37:.*]] = dxsa.operand %[[INDEX_25]] {num_components = 4 : i32, one = 2 : i32, type = 0 : i32} +// CHECK: %[[OPERAND_38:.*]] = dxsa.operand.imm {imm = dense<16> : vector<1xi32>} +// CHECK: %[[INDEX_26:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_39:.*]] = dxsa.operand %[[INDEX_26]] {num_components = 4 : i32, swizzle = dense<0> : vector<4xi32>, type = 31 : i32} +// CHECK: dxsa.instruction "ld_structured" %[[OPERAND_36]], %[[OPERAND_37]], %[[OPERAND_38]], %[[OPERAND_39]] +// CHECK: dxsa.utof r<0, >, r<0, > +// CHECK: dxsa.add r<0, >, r<0, >, r<0, > +// CHECK: %[[INDEX_27:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_40:.*]] = dxsa.operand %[[INDEX_27]] {mask = 16 : i32, num_components = 4 : i32, type = 30 : i32} +// CHECK: %[[INDEX_28:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_41:.*]] = dxsa.operand %[[INDEX_28]] {num_components = 4 : i32, one = 0 : i32, type = 0 : i32} +// CHECK: %[[INDEX_29:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_42:.*]] = dxsa.operand %[[INDEX_29]] {num_components = 4 : i32, one = 1 : i32, type = 0 : i32} +// CHECK: dxsa.instruction "store_raw" %[[OPERAND_40]], %[[OPERAND_41]], %[[OPERAND_42]] +// CHECK: dxsa.instruction "ret" + diff --git a/mlir/test/Target/DXSA/hlsl/cs5.test b/mlir/test/Target/DXSA/hlsl/cs5.test new file mode 100644 index 000000000000..efb1b13e6935 --- /dev/null +++ b/mlir/test/Target/DXSA/hlsl/cs5.test @@ -0,0 +1,113 @@ +// RUN: mlir-translate --import-dxsa-bin %S/inputs/cs5.bin | FileCheck %s +// NOTE: Assertions have been autogenerated by utils/generate-test-checks.py + +// This script is intended to make adding checks to a test case quick and easy. +// It is *not* authoritative about what constitutes a good test. After using the +// script, be sure to review and refine the generated checks. For example, +// CHECK lines should be minimized and named to reflect the test’s intent. +// For comprehensive guidelines, see: +// * https://mlir.llvm.org/getting_started/TestingGuide/ + + +// CHECK-LABEL: dxsa.dcl_global_flags +// CHECK: dxsa.dcl_constant_buffer , +// CHECK: dxsa.dcl_uav_raw +// CHECK: dxsa.dcl_input vThreadIDInGroupFlattened +// CHECK: dxsa.dcl_input vThreadGroupID<> +// CHECK: dxsa.dcl_input vThreadIDInGroup<> +// CHECK: dxsa.dcl_input vThreadID<> +// CHECK: dxsa.dcl_temps 3 +// CHECK: dxsa.dcl_tgsm_structured g<0>, 16, 384 +// CHECK: dxsa.dcl_thread_group +// CHECK: dxsa.ishl r<0, >, vThreadID<>, l(0x7) +// CHECK: dxsa.ishl r<0, >, vThreadGroupID<>, l(0xA) +// CHECK: %[[INDEX_0:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_0:.*]] = dxsa.operand %[[INDEX_0]] {mask = 16 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_1:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_1:.*]] = dxsa.operand %[[INDEX_1]] {num_components = 4 : i32, one = 1 : i32, type = 0 : i32} +// CHECK: %[[INDEX_2:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_2:.*]] = dxsa.operand %[[INDEX_2]] {num_components = 4 : i32, one = 0 : i32, type = 0 : i32} +// CHECK: dxsa.instruction "iadd" %[[OPERAND_0]], %[[OPERAND_1]], %[[OPERAND_2]] +// CHECK: %[[INDEX_3:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_3:.*]] = dxsa.operand %[[INDEX_3]] {mask = 16 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_4:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_4:.*]] = dxsa.operand %[[INDEX_4]] {num_components = 4 : i32, one = 0 : i32, type = 0 : i32} +// CHECK: %[[OPERAND_5:.*]] = dxsa.operand {num_components = 4 : i32, one = 2 : i32, type = 34 : i32} +// CHECK: dxsa.instruction "iadd" %[[OPERAND_3]], %[[OPERAND_4]], %[[OPERAND_5]] +// CHECK: %[[INDEX_5:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_6:.*]] = dxsa.operand %[[INDEX_5]] {mask = 16 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_6:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_7:.*]] = dxsa.operand %[[INDEX_6]] {num_components = 4 : i32, one = 0 : i32, type = 0 : i32} +// CHECK: %[[OPERAND_8:.*]] = dxsa.operand {num_components = 4 : i32, one = 0 : i32, type = 36 : i32} +// CHECK: dxsa.instruction "iadd" %[[OPERAND_6]], %[[OPERAND_7]], %[[OPERAND_8]] +// CHECK: dxsa.unknown +// CHECK: dxsa.add r<1, min16f, >, r<0, >, l(0x40000000) +// CHECK: %[[INDEX_7:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_9:.*]] = dxsa.operand %[[INDEX_7]] {mask = 16 : i32, num_components = 4 : i32, type = 31 : i32} +// CHECK: %[[OPERAND_10:.*]] = dxsa.operand {num_components = 4 : i32, one = 0 : i32, type = 36 : i32} +// CHECK: %[[OPERAND_11:.*]] = dxsa.operand.imm {imm = dense<4> : vector<1xi32>} +// CHECK: %[[INDEX_8:.*]] = dxsa.index.imm {imm = 1 : i32} +// CHECK: %[[OPERAND_12:.*]] = dxsa.operand %[[INDEX_8]] {min_precision = 1 : i32, num_components = 4 : i32, one = 0 : i32, type = 0 : i32} +// CHECK: dxsa.instruction "store_structured" %[[OPERAND_9]], %[[OPERAND_10]], %[[OPERAND_11]], %[[OPERAND_12]] +// CHECK: %[[INDEX_9:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_13:.*]] = dxsa.operand %[[INDEX_9]] {mask = 16 : i32, num_components = 4 : i32, type = 31 : i32} +// CHECK: %[[OPERAND_14:.*]] = dxsa.operand {num_components = 4 : i32, one = 0 : i32, type = 36 : i32} +// CHECK: %[[OPERAND_15:.*]] = dxsa.operand.imm {imm = dense<8> : vector<1xi32>} +// CHECK: %[[INDEX_10:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_16:.*]] = dxsa.operand %[[INDEX_10]] {num_components = 4 : i32, one = 1 : i32, type = 0 : i32} +// CHECK: dxsa.instruction "store_structured" %[[OPERAND_13]], %[[OPERAND_14]], %[[OPERAND_15]], %[[OPERAND_16]] +// CHECK: dxsa.ftoi r<2, min16i, >, r<0, > +// CHECK: %[[INDEX_11:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_17:.*]] = dxsa.operand %[[INDEX_11]] {mask = 16 : i32, num_components = 4 : i32, type = 31 : i32} +// CHECK: %[[OPERAND_18:.*]] = dxsa.operand {num_components = 4 : i32, one = 0 : i32, type = 36 : i32} +// CHECK: %[[OPERAND_19:.*]] = dxsa.operand.imm {imm = dense<12> : vector<1xi32>} +// CHECK: %[[INDEX_12:.*]] = dxsa.index.imm {imm = 2 : i32} +// CHECK: %[[OPERAND_20:.*]] = dxsa.operand %[[INDEX_12]] {min_precision = 4 : i32, num_components = 4 : i32, one = 0 : i32, type = 0 : i32} +// CHECK: dxsa.instruction "store_structured" %[[OPERAND_17]], %[[OPERAND_18]], %[[OPERAND_19]], %[[OPERAND_20]] +// CHECK: dxsa.instruction "sync" +// CHECK: %[[INDEX_13:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_21:.*]] = dxsa.operand %[[INDEX_13]] {mask = 64 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[OPERAND_22:.*]] = dxsa.operand {num_components = 4 : i32, one = 0 : i32, type = 36 : i32} +// CHECK: %[[INDEX_14:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[INDEX_15:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_23:.*]] = dxsa.operand %[[INDEX_14]], %[[INDEX_15]] {num_components = 4 : i32, one = 0 : i32, type = 8 : i32} +// CHECK: dxsa.instruction "iadd" %[[OPERAND_21]], %[[OPERAND_22]], %[[OPERAND_23]] +// CHECK: %[[INDEX_16:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_24:.*]] = dxsa.operand %[[INDEX_16]] {mask = 128 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_17:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_25:.*]] = dxsa.operand %[[INDEX_17]] {num_components = 4 : i32, one = 2 : i32, type = 0 : i32} +// CHECK: %[[OPERAND_26:.*]] = dxsa.operand.imm {imm = dense<8> : vector<1xi32>} +// CHECK: %[[INDEX_18:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_27:.*]] = dxsa.operand %[[INDEX_18]] {num_components = 4 : i32, swizzle = dense<0> : vector<4xi32>, type = 31 : i32} +// CHECK: dxsa.instruction "ld_structured" %[[OPERAND_24]], %[[OPERAND_25]], %[[OPERAND_26]], %[[OPERAND_27]] +// CHECK: dxsa.add r<0, >, r<0, >, r<0, > +// CHECK: %[[INDEX_19:.*]] = dxsa.index.imm {imm = 2 : i32} +// CHECK: %[[OPERAND_28:.*]] = dxsa.operand %[[INDEX_19]] {mask = 16 : i32, min_precision = 4 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_20:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_29:.*]] = dxsa.operand %[[INDEX_20]] {num_components = 4 : i32, one = 2 : i32, type = 0 : i32} +// CHECK: %[[OPERAND_30:.*]] = dxsa.operand.imm {imm = dense<12> : vector<1xi32>} +// CHECK: %[[INDEX_21:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_31:.*]] = dxsa.operand %[[INDEX_21]] {num_components = 4 : i32, swizzle = dense<0> : vector<4xi32>, type = 31 : i32} +// CHECK: dxsa.instruction "ld_structured" %[[OPERAND_28]], %[[OPERAND_29]], %[[OPERAND_30]], %[[OPERAND_31]] +// CHECK: dxsa.itof r<0, >, r<2, min16i, > +// CHECK: dxsa.add r<0, >, r<0, >, r<0, > +// CHECK: dxsa.instruction "sync" +// CHECK: dxsa.instruction "sync" +// CHECK: %[[INDEX_22:.*]] = dxsa.index.imm {imm = 1 : i32} +// CHECK: %[[OPERAND_32:.*]] = dxsa.operand %[[INDEX_22]] {mask = 16 : i32, min_precision = 1 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_23:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_33:.*]] = dxsa.operand %[[INDEX_23]] {num_components = 4 : i32, one = 2 : i32, type = 0 : i32} +// CHECK: %[[OPERAND_34:.*]] = dxsa.operand.imm {imm = dense<4> : vector<1xi32>} +// CHECK: %[[INDEX_24:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_35:.*]] = dxsa.operand %[[INDEX_24]] {num_components = 4 : i32, swizzle = dense<0> : vector<4xi32>, type = 31 : i32} +// CHECK: dxsa.instruction "ld_structured" %[[OPERAND_32]], %[[OPERAND_33]], %[[OPERAND_34]], %[[OPERAND_35]] +// CHECK: dxsa.add r<0, >, r<0, >, r<1, min16f, > +// CHECK: %[[INDEX_25:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_36:.*]] = dxsa.operand %[[INDEX_25]] {mask = 16 : i32, num_components = 4 : i32, type = 30 : i32} +// CHECK: %[[INDEX_26:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_37:.*]] = dxsa.operand %[[INDEX_26]] {num_components = 4 : i32, one = 0 : i32, type = 0 : i32} +// CHECK: %[[INDEX_27:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_38:.*]] = dxsa.operand %[[INDEX_27]] {num_components = 4 : i32, one = 1 : i32, type = 0 : i32} +// CHECK: dxsa.instruction "store_raw" %[[OPERAND_36]], %[[OPERAND_37]], %[[OPERAND_38]] +// CHECK: dxsa.instruction "ret" + diff --git a/mlir/test/Target/DXSA/hlsl/derivatives.test b/mlir/test/Target/DXSA/hlsl/derivatives.test new file mode 100644 index 000000000000..ebfd5c4d464e --- /dev/null +++ b/mlir/test/Target/DXSA/hlsl/derivatives.test @@ -0,0 +1,53 @@ +// RUN: mlir-translate --import-dxsa-bin %S/inputs/derivatives.bin | FileCheck %s +// NOTE: Assertions have been autogenerated by utils/generate-test-checks.py + +// This script is intended to make adding checks to a test case quick and easy. +// It is *not* authoritative about what constitutes a good test. After using the +// script, be sure to review and refine the generated checks. For example, +// CHECK lines should be minimized and named to reflect the test’s intent. +// For comprehensive guidelines, see: +// * https://mlir.llvm.org/getting_started/TestingGuide/ + + +// CHECK-LABEL: dxsa.dcl_global_flags +// CHECK: dxsa.dcl_input_ps linear v<0> +// CHECK: dxsa.dcl_input_ps linear v<1> +// CHECK: dxsa.dcl_output o<0> +// CHECK: dxsa.dcl_temps 2 +// CHECK: %[[INDEX_0:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_0:.*]] = dxsa.operand %[[INDEX_0]] {mask = 240 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_1:.*]] = dxsa.index.imm {imm = 1 : i32} +// CHECK: %[[OPERAND_1:.*]] = dxsa.operand %[[INDEX_1]] {num_components = 4 : i32, swizzle = dense<[0, 1, 2, 3]> : vector<4xi32>, type = 1 : i32} +// CHECK: dxsa.instruction "deriv_rtx_coarse" %[[OPERAND_0]], %[[OPERAND_1]] +// CHECK: %[[INDEX_2:.*]] = dxsa.index.imm {imm = 1 : i32} +// CHECK: %[[OPERAND_2:.*]] = dxsa.operand %[[INDEX_2]] {mask = 240 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_3:.*]] = dxsa.index.imm {imm = 1 : i32} +// CHECK: %[[OPERAND_3:.*]] = dxsa.operand %[[INDEX_3]] {num_components = 4 : i32, swizzle = dense<[0, 1, 2, 3]> : vector<4xi32>, type = 1 : i32} +// CHECK: dxsa.instruction "deriv_rty_coarse" %[[OPERAND_2]], %[[OPERAND_3]] +// CHECK: dxsa.add r<0>, r<0>, r<1> +// CHECK: %[[INDEX_4:.*]] = dxsa.index.imm {imm = 1 : i32} +// CHECK: %[[OPERAND_4:.*]] = dxsa.operand %[[INDEX_4]] {mask = 240 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_5:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_5:.*]] = dxsa.operand %[[INDEX_5]] {num_components = 4 : i32, swizzle = dense<[0, 1, 2, 3]> : vector<4xi32>, type = 1 : i32} +// CHECK: dxsa.instruction "deriv_rtx_coarse" %[[OPERAND_4]], %[[OPERAND_5]] +// CHECK: dxsa.add r<0>, r<0>, r<1> +// CHECK: %[[INDEX_6:.*]] = dxsa.index.imm {imm = 1 : i32} +// CHECK: %[[OPERAND_6:.*]] = dxsa.operand %[[INDEX_6]] {mask = 240 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_7:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_7:.*]] = dxsa.operand %[[INDEX_7]] {num_components = 4 : i32, swizzle = dense<[0, 1, 2, 3]> : vector<4xi32>, type = 1 : i32} +// CHECK: dxsa.instruction "deriv_rty_coarse" %[[OPERAND_6]], %[[OPERAND_7]] +// CHECK: dxsa.add r<0>, r<0>, r<1> +// CHECK: %[[INDEX_8:.*]] = dxsa.index.imm {imm = 1 : i32} +// CHECK: %[[OPERAND_8:.*]] = dxsa.operand %[[INDEX_8]] {mask = 240 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_9:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_9:.*]] = dxsa.operand %[[INDEX_9]] {num_components = 4 : i32, swizzle = dense<[0, 1, 2, 3]> : vector<4xi32>, type = 1 : i32} +// CHECK: dxsa.instruction "deriv_rtx_fine" %[[OPERAND_8]], %[[OPERAND_9]] +// CHECK: dxsa.add r<0>, r<0>, r<1> +// CHECK: %[[INDEX_10:.*]] = dxsa.index.imm {imm = 1 : i32} +// CHECK: %[[OPERAND_10:.*]] = dxsa.operand %[[INDEX_10]] {mask = 240 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_11:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_11:.*]] = dxsa.operand %[[INDEX_11]] {num_components = 4 : i32, swizzle = dense<[0, 1, 2, 3]> : vector<4xi32>, type = 1 : i32} +// CHECK: dxsa.instruction "deriv_rty_fine" %[[OPERAND_10]], %[[OPERAND_11]] +// CHECK: dxsa.add o<0>, r<0>, r<1> +// CHECK: dxsa.instruction "ret" + diff --git a/mlir/test/Target/DXSA/hlsl/discard.test b/mlir/test/Target/DXSA/hlsl/discard.test new file mode 100644 index 000000000000..bcd54ecfcd3e --- /dev/null +++ b/mlir/test/Target/DXSA/hlsl/discard.test @@ -0,0 +1,29 @@ +// RUN: mlir-translate --import-dxsa-bin %S/inputs/discard.bin | FileCheck %s +// NOTE: Assertions have been autogenerated by utils/generate-test-checks.py + +// This script is intended to make adding checks to a test case quick and easy. +// It is *not* authoritative about what constitutes a good test. After using the +// script, be sure to review and refine the generated checks. For example, +// CHECK lines should be minimized and named to reflect the test’s intent. +// For comprehensive guidelines, see: +// * https://mlir.llvm.org/getting_started/TestingGuide/ + + +// CHECK-LABEL: dxsa.dcl_global_flags +// CHECK: dxsa.dcl_input_ps linear v<0, > +// CHECK: dxsa.dcl_output o<0> +// CHECK: dxsa.dcl_temps 1 +// CHECK: dxsa.lt r<0, >, l(0x3E99999A), v<0, > +// CHECK: %[[INDEX_0:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_0:.*]] = dxsa.operand %[[INDEX_0]] {num_components = 4 : i32, one = 0 : i32, type = 0 : i32} +// CHECK: dxsa.instruction "discard" %[[OPERAND_0]] +// CHECK: dxsa.ne r<0, >, v<0, >, l(0x0) +// CHECK: %[[INDEX_1:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_1:.*]] = dxsa.operand %[[INDEX_1]] {num_components = 4 : i32, one = 0 : i32, type = 0 : i32} +// CHECK: dxsa.instruction "discard" %[[OPERAND_1]] +// CHECK: %[[INDEX_2:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_2:.*]] = dxsa.operand %[[INDEX_2]] {mask = 240 : i32, num_components = 4 : i32, type = 2 : i32} +// CHECK: %[[OPERAND_3:.*]] = dxsa.operand.imm {imm = dense<0> : vector<4xi32>} +// CHECK: dxsa.instruction "mov" %[[OPERAND_2]], %[[OPERAND_3]] +// CHECK: dxsa.instruction "ret" + diff --git a/mlir/test/Target/DXSA/hlsl/dot1.test b/mlir/test/Target/DXSA/hlsl/dot1.test new file mode 100644 index 000000000000..8af54616e298 --- /dev/null +++ b/mlir/test/Target/DXSA/hlsl/dot1.test @@ -0,0 +1,23 @@ +// RUN: mlir-translate --import-dxsa-bin %S/inputs/dot1.bin | FileCheck %s +// NOTE: Assertions have been autogenerated by utils/generate-test-checks.py + +// This script is intended to make adding checks to a test case quick and easy. +// It is *not* authoritative about what constitutes a good test. After using the +// script, be sure to review and refine the generated checks. For example, +// CHECK lines should be minimized and named to reflect the test’s intent. +// For comprehensive guidelines, see: +// * https://mlir.llvm.org/getting_started/TestingGuide/ + + +// CHECK-LABEL: dxsa.dcl_global_flags +// CHECK: dxsa.dcl_input_ps linear v<0> +// CHECK: dxsa.dcl_input_ps linear v<1> +// CHECK: dxsa.dcl_output o<0, > +// CHECK: dxsa.dcl_temps 1 +// CHECK: dxsa.dp4 r<0, >, v<0>, v<1> +// CHECK: dxsa.dp3 r<0, >, v<0, >, v<1, > +// CHECK: dxsa.add r<0, >, r<0, >, r<0, > +// CHECK: dxsa.dp2 r<0, >, v<0, >, v<1, > +// CHECK: dxsa.add o<0, >, r<0, >, r<0, > +// CHECK: dxsa.instruction "ret" + diff --git a/mlir/test/Target/DXSA/hlsl/double1.test b/mlir/test/Target/DXSA/hlsl/double1.test new file mode 100644 index 000000000000..52d7cfe722cf --- /dev/null +++ b/mlir/test/Target/DXSA/hlsl/double1.test @@ -0,0 +1,59 @@ +// RUN: mlir-translate --import-dxsa-bin %S/inputs/double1.bin | FileCheck %s +// NOTE: Assertions have been autogenerated by utils/generate-test-checks.py + +// This script is intended to make adding checks to a test case quick and easy. +// It is *not* authoritative about what constitutes a good test. After using the +// script, be sure to review and refine the generated checks. For example, +// CHECK lines should be minimized and named to reflect the test’s intent. +// For comprehensive guidelines, see: +// * https://mlir.llvm.org/getting_started/TestingGuide/ + + +// CHECK-LABEL: dxsa.dcl_global_flags +// CHECK: dxsa.dcl_input_ps constant v<0, > +// CHECK: dxsa.dcl_input_ps constant v<0, > +// CHECK: dxsa.dcl_output o<0, > +// CHECK: dxsa.dcl_temps 1 +// CHECK: %[[INDEX_0:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_0:.*]] = dxsa.operand %[[INDEX_0]] {mask = 240 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_1:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_1:.*]] = dxsa.operand %[[INDEX_1]] {num_components = 4 : i32, swizzle = dense<[0, 1, 2, 3]> : vector<4xi32>, type = 1 : i32} +// CHECK: dxsa.instruction "mov" %[[OPERAND_0]], %[[OPERAND_1]] +// CHECK: %[[INDEX_2:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_2:.*]] = dxsa.operand %[[INDEX_2]] {mask = 48 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_3:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_3:.*]] = dxsa.operand %[[INDEX_3]] {num_components = 4 : i32, swizzle = dense<[2, 3, 2, 3]> : vector<4xi32>, type = 0 : i32} +// CHECK: %[[INDEX_4:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_4:.*]] = dxsa.operand %[[INDEX_4]] {num_components = 4 : i32, swizzle = dense<[0, 1, 0, 1]> : vector<4xi32>, type = 0 : i32} +// CHECK: dxsa.instruction "ddiv" %[[OPERAND_2]], %[[OPERAND_3]], %[[OPERAND_4]] +// CHECK: %[[INDEX_5:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_5:.*]] = dxsa.operand %[[INDEX_5]] {mask = 192 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_6:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_6:.*]] = dxsa.operand %[[INDEX_6]] {num_components = 4 : i32, swizzle = dense<[2, 3, 2, 3]> : vector<4xi32>, type = 0 : i32} +// CHECK: %[[OPERAND_7:.*]] = dxsa.operand.imm {imm = dense<[0, 6917529030863447654]> : vector<2xi64>} +// CHECK: dxsa.instruction "dadd" %[[OPERAND_5]], %[[OPERAND_6]], %[[OPERAND_7]] +// CHECK: %[[INDEX_7:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_8:.*]] = dxsa.operand %[[INDEX_7]] {mask = 48 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_8:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_9:.*]] = dxsa.operand %[[INDEX_8]] {num_components = 4 : i32, swizzle = dense<[0, 1, 0, 1]> : vector<4xi32>, type = 0 : i32} +// CHECK: %[[OPERAND_10:.*]] = dxsa.operand.imm {imm = dense<[-9223372035781275157, 0]> : vector<2xi64>} +// CHECK: dxsa.instruction "dmin" %[[OPERAND_8]], %[[OPERAND_9]], %[[OPERAND_10]] +// CHECK: %[[INDEX_9:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_11:.*]] = dxsa.operand %[[INDEX_9]] {mask = 48 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_10:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_12:.*]] = dxsa.operand %[[INDEX_10]] {num_components = 4 : i32, swizzle = dense<[2, 3, 2, 3]> : vector<4xi32>, type = 0 : i32} +// CHECK: %[[INDEX_11:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_13:.*]] = dxsa.operand %[[INDEX_11]] {num_components = 4 : i32, swizzle = dense<[0, 1, 0, 1]> : vector<4xi32>, type = 0 : i32} +// CHECK: dxsa.instruction "dmax" %[[OPERAND_11]], %[[OPERAND_12]], %[[OPERAND_13]] +// CHECK: %[[INDEX_12:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_14:.*]] = dxsa.operand %[[INDEX_12]] {mask = 48 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_13:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_15:.*]] = dxsa.operand %[[INDEX_13]] {modifier = 2 : i32, num_components = 4 : i32, swizzle = dense<[0, 1, 0, 1]> : vector<4xi32>, type = 0 : i32} +// CHECK: dxsa.instruction "dmov" %[[OPERAND_14]], %[[OPERAND_15]] +// CHECK: %[[INDEX_14:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_16:.*]] = dxsa.operand %[[INDEX_14]] {mask = 48 : i32, num_components = 4 : i32, type = 2 : i32} +// CHECK: %[[INDEX_15:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_17:.*]] = dxsa.operand %[[INDEX_15]] {num_components = 4 : i32, swizzle = dense<[0, 1, 0, 0]> : vector<4xi32>, type = 0 : i32} +// CHECK: dxsa.instruction "mov" %[[OPERAND_16]], %[[OPERAND_17]] +// CHECK: dxsa.instruction "ret" + diff --git a/mlir/test/Target/DXSA/hlsl/double2.test b/mlir/test/Target/DXSA/hlsl/double2.test new file mode 100644 index 000000000000..dbcbfd8ecab1 --- /dev/null +++ b/mlir/test/Target/DXSA/hlsl/double2.test @@ -0,0 +1,65 @@ +// RUN: mlir-translate --import-dxsa-bin %S/inputs/double2.bin | FileCheck %s +// NOTE: Assertions have been autogenerated by utils/generate-test-checks.py + +// This script is intended to make adding checks to a test case quick and easy. +// It is *not* authoritative about what constitutes a good test. After using the +// script, be sure to review and refine the generated checks. For example, +// CHECK lines should be minimized and named to reflect the test’s intent. +// For comprehensive guidelines, see: +// * https://mlir.llvm.org/getting_started/TestingGuide/ + + +// CHECK-LABEL: dxsa.dcl_global_flags +// CHECK: dxsa.dcl_constant_buffer , +// CHECK: dxsa.dcl_input_ps constant v<0, > +// CHECK: dxsa.dcl_input_ps constant v<0, > +// CHECK: dxsa.dcl_output o<0, > +// CHECK: dxsa.dcl_temps 1 +// CHECK: %[[INDEX_0:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_0:.*]] = dxsa.operand %[[INDEX_0]] {mask = 240 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_1:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_1:.*]] = dxsa.operand %[[INDEX_1]] {num_components = 4 : i32, swizzle = dense<[0, 1, 2, 3]> : vector<4xi32>, type = 1 : i32} +// CHECK: dxsa.instruction "mov" %[[OPERAND_0]], %[[OPERAND_1]] +// CHECK: %[[INDEX_2:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_2:.*]] = dxsa.operand %[[INDEX_2]] {mask = 48 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_3:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_3:.*]] = dxsa.operand %[[INDEX_3]] {num_components = 4 : i32, swizzle = dense<[2, 3, 2, 3]> : vector<4xi32>, type = 0 : i32} +// CHECK: %[[INDEX_4:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_4:.*]] = dxsa.operand %[[INDEX_4]] {num_components = 4 : i32, swizzle = dense<[0, 1, 0, 1]> : vector<4xi32>, type = 0 : i32} +// CHECK: dxsa.instruction "ddiv" %[[OPERAND_2]], %[[OPERAND_3]], %[[OPERAND_4]] +// CHECK: %[[INDEX_5:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_5:.*]] = dxsa.operand %[[INDEX_5]] {mask = 192 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_6:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_6:.*]] = dxsa.operand %[[INDEX_6]] {num_components = 4 : i32, swizzle = dense<[2, 3, 2, 3]> : vector<4xi32>, type = 0 : i32} +// CHECK: %[[OPERAND_7:.*]] = dxsa.operand.imm {imm = dense<[0, 6917529030863447654]> : vector<2xi64>} +// CHECK: dxsa.instruction "dadd" %[[OPERAND_5]], %[[OPERAND_6]], %[[OPERAND_7]] +// CHECK: %[[INDEX_7:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_8:.*]] = dxsa.operand %[[INDEX_7]] {mask = 48 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_8:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_9:.*]] = dxsa.operand %[[INDEX_8]] {num_components = 4 : i32, swizzle = dense<[0, 1, 0, 1]> : vector<4xi32>, type = 0 : i32} +// CHECK: %[[OPERAND_10:.*]] = dxsa.operand.imm {imm = dense<[-9223372035781275157, 0]> : vector<2xi64>} +// CHECK: dxsa.instruction "dmin" %[[OPERAND_8]], %[[OPERAND_9]], %[[OPERAND_10]] +// CHECK: %[[INDEX_9:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_11:.*]] = dxsa.operand %[[INDEX_9]] {mask = 48 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_10:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_12:.*]] = dxsa.operand %[[INDEX_10]] {num_components = 4 : i32, swizzle = dense<[2, 3, 2, 3]> : vector<4xi32>, type = 0 : i32} +// CHECK: %[[INDEX_11:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_13:.*]] = dxsa.operand %[[INDEX_11]] {num_components = 4 : i32, swizzle = dense<[0, 1, 0, 1]> : vector<4xi32>, type = 0 : i32} +// CHECK: dxsa.instruction "dmax" %[[OPERAND_11]], %[[OPERAND_12]], %[[OPERAND_13]] +// CHECK: %[[INDEX_12:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_14:.*]] = dxsa.operand %[[INDEX_12]] {mask = 48 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_13:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[INDEX_14:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_15:.*]] = dxsa.operand %[[INDEX_13]], %[[INDEX_14]] {num_components = 4 : i32, swizzle = dense<0> : vector<4xi32>, type = 8 : i32} +// CHECK: %[[INDEX_15:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_16:.*]] = dxsa.operand %[[INDEX_15]] {modifier = 2 : i32, num_components = 4 : i32, swizzle = dense<[0, 1, 0, 1]> : vector<4xi32>, type = 0 : i32} +// CHECK: %[[INDEX_16:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_17:.*]] = dxsa.operand %[[INDEX_16]] {num_components = 4 : i32, swizzle = dense<[0, 1, 0, 1]> : vector<4xi32>, type = 0 : i32} +// CHECK: dxsa.instruction "dmovc" %[[OPERAND_14]], %[[OPERAND_15]], %[[OPERAND_16]], %[[OPERAND_17]] +// CHECK: %[[INDEX_17:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_18:.*]] = dxsa.operand %[[INDEX_17]] {mask = 48 : i32, num_components = 4 : i32, type = 2 : i32} +// CHECK: %[[INDEX_18:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_19:.*]] = dxsa.operand %[[INDEX_18]] {num_components = 4 : i32, swizzle = dense<[0, 1, 0, 0]> : vector<4xi32>, type = 0 : i32} +// CHECK: dxsa.instruction "mov" %[[OPERAND_18]], %[[OPERAND_19]] +// CHECK: dxsa.instruction "ret" + diff --git a/mlir/test/Target/DXSA/hlsl/double3.test b/mlir/test/Target/DXSA/hlsl/double3.test new file mode 100644 index 000000000000..98339a36cfa6 --- /dev/null +++ b/mlir/test/Target/DXSA/hlsl/double3.test @@ -0,0 +1,74 @@ +// RUN: mlir-translate --import-dxsa-bin %S/inputs/double3.bin | FileCheck %s +// NOTE: Assertions have been autogenerated by utils/generate-test-checks.py + +// This script is intended to make adding checks to a test case quick and easy. +// It is *not* authoritative about what constitutes a good test. After using the +// script, be sure to review and refine the generated checks. For example, +// CHECK lines should be minimized and named to reflect the test’s intent. +// For comprehensive guidelines, see: +// * https://mlir.llvm.org/getting_started/TestingGuide/ + + +// CHECK-LABEL: dxsa.dcl_global_flags +// CHECK: dxsa.dcl_input_ps constant v<0, > +// CHECK: dxsa.dcl_input_ps constant v<0, > +// CHECK: dxsa.dcl_input_ps constant v<1, > +// CHECK: dxsa.dcl_output o<0, > +// CHECK: dxsa.dcl_temps 2 +// CHECK: %[[INDEX_0:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_0:.*]] = dxsa.operand %[[INDEX_0]] {mask = 240 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_1:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_1:.*]] = dxsa.operand %[[INDEX_1]] {num_components = 4 : i32, swizzle = dense<[0, 1, 2, 3]> : vector<4xi32>, type = 1 : i32} +// CHECK: dxsa.instruction "mov" %[[OPERAND_0]], %[[OPERAND_1]] +// CHECK: %[[INDEX_2:.*]] = dxsa.index.imm {imm = 1 : i32} +// CHECK: %[[OPERAND_2:.*]] = dxsa.operand %[[INDEX_2]] {mask = 16 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_3:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_3:.*]] = dxsa.operand %[[INDEX_3]] {num_components = 4 : i32, swizzle = dense<[2, 3, 2, 3]> : vector<4xi32>, type = 0 : i32} +// CHECK: %[[INDEX_4:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_4:.*]] = dxsa.operand %[[INDEX_4]] {num_components = 4 : i32, swizzle = dense<[0, 1, 0, 1]> : vector<4xi32>, type = 0 : i32} +// CHECK: dxsa.instruction "deq" %[[OPERAND_2]], %[[OPERAND_3]], %[[OPERAND_4]] +// CHECK: %[[INDEX_5:.*]] = dxsa.index.imm {imm = 1 : i32} +// CHECK: %[[OPERAND_5:.*]] = dxsa.operand %[[INDEX_5]] {mask = 192 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_6:.*]] = dxsa.index.imm {imm = 1 : i32} +// CHECK: %[[OPERAND_6:.*]] = dxsa.operand %[[INDEX_6]] {num_components = 4 : i32, swizzle = dense<[0, 0, 0, 1]> : vector<4xi32>, type = 1 : i32} +// CHECK: dxsa.instruction "mov" %[[OPERAND_5]], %[[OPERAND_6]] +// CHECK: %[[INDEX_7:.*]] = dxsa.index.imm {imm = 1 : i32} +// CHECK: %[[OPERAND_7:.*]] = dxsa.operand %[[INDEX_7]] {mask = 32 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_8:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_8:.*]] = dxsa.operand %[[INDEX_8]] {num_components = 4 : i32, swizzle = dense<[0, 1, 0, 1]> : vector<4xi32>, type = 0 : i32} +// CHECK: %[[INDEX_9:.*]] = dxsa.index.imm {imm = 1 : i32} +// CHECK: %[[OPERAND_9:.*]] = dxsa.operand %[[INDEX_9]] {num_components = 4 : i32, swizzle = dense<[2, 3, 2, 3]> : vector<4xi32>, type = 0 : i32} +// CHECK: dxsa.instruction "dne" %[[OPERAND_7]], %[[OPERAND_8]], %[[OPERAND_9]] +// CHECK: dxsa.and r<1, >, r<1, >, r<1, > +// CHECK: %[[INDEX_10:.*]] = dxsa.index.imm {imm = 1 : i32} +// CHECK: %[[OPERAND_10:.*]] = dxsa.operand %[[INDEX_10]] {mask = 32 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_11:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_11:.*]] = dxsa.operand %[[INDEX_11]] {num_components = 4 : i32, swizzle = dense<[2, 3, 2, 3]> : vector<4xi32>, type = 0 : i32} +// CHECK: %[[INDEX_12:.*]] = dxsa.index.imm {imm = 1 : i32} +// CHECK: %[[OPERAND_12:.*]] = dxsa.operand %[[INDEX_12]] {num_components = 4 : i32, swizzle = dense<[2, 3, 2, 3]> : vector<4xi32>, type = 0 : i32} +// CHECK: dxsa.instruction "dlt" %[[OPERAND_10]], %[[OPERAND_11]], %[[OPERAND_12]] +// CHECK: %[[INDEX_13:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_13:.*]] = dxsa.operand %[[INDEX_13]] {mask = 192 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_14:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_14:.*]] = dxsa.operand %[[INDEX_14]] {num_components = 4 : i32, swizzle = dense<[2, 3, 2, 3]> : vector<4xi32>, type = 0 : i32} +// CHECK: %[[INDEX_15:.*]] = dxsa.index.imm {imm = 1 : i32} +// CHECK: %[[OPERAND_15:.*]] = dxsa.operand %[[INDEX_15]] {num_components = 4 : i32, swizzle = dense<[2, 3, 2, 3]> : vector<4xi32>, type = 0 : i32} +// CHECK: dxsa.instruction "dmul" %[[OPERAND_13]], %[[OPERAND_14]], %[[OPERAND_15]] +// CHECK: %[[INDEX_16:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_16:.*]] = dxsa.operand %[[INDEX_16]] {mask = 192 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_17:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_17:.*]] = dxsa.operand %[[INDEX_17]] {num_components = 4 : i32, swizzle = dense<[2, 3, 2, 3]> : vector<4xi32>, type = 0 : i32} +// CHECK: %[[INDEX_18:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_18:.*]] = dxsa.operand %[[INDEX_18]] {num_components = 4 : i32, swizzle = dense<[0, 1, 0, 1]> : vector<4xi32>, type = 0 : i32} +// CHECK: dxsa.instruction "dadd" %[[OPERAND_16]], %[[OPERAND_17]], %[[OPERAND_18]] +// CHECK: %[[INDEX_19:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_19:.*]] = dxsa.operand %[[INDEX_19]] {mask = 16 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_20:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_20:.*]] = dxsa.operand %[[INDEX_20]] {num_components = 4 : i32, swizzle = dense<[0, 1, 0, 1]> : vector<4xi32>, type = 0 : i32} +// CHECK: %[[INDEX_21:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_21:.*]] = dxsa.operand %[[INDEX_21]] {num_components = 4 : i32, swizzle = dense<[2, 3, 2, 3]> : vector<4xi32>, type = 0 : i32} +// CHECK: dxsa.instruction "dlt" %[[OPERAND_19]], %[[OPERAND_20]], %[[OPERAND_21]] +// CHECK: dxsa.and r<0, >, r<1, >, r<1, > +// CHECK: dxsa.and o<0, >, r<0, >, r<0, > +// CHECK: dxsa.instruction "ret" + diff --git a/mlir/test/Target/DXSA/hlsl/double4.test b/mlir/test/Target/DXSA/hlsl/double4.test new file mode 100644 index 000000000000..08bfd41d4293 --- /dev/null +++ b/mlir/test/Target/DXSA/hlsl/double4.test @@ -0,0 +1,55 @@ +// RUN: mlir-translate --import-dxsa-bin %S/inputs/double4.bin | FileCheck %s +// NOTE: Assertions have been autogenerated by utils/generate-test-checks.py + +// This script is intended to make adding checks to a test case quick and easy. +// It is *not* authoritative about what constitutes a good test. After using the +// script, be sure to review and refine the generated checks. For example, +// CHECK lines should be minimized and named to reflect the test’s intent. +// For comprehensive guidelines, see: +// * https://mlir.llvm.org/getting_started/TestingGuide/ + + +// CHECK-LABEL: dxsa.dcl_global_flags +// CHECK: dxsa.dcl_input_ps constant v<0> +// CHECK: dxsa.dcl_input_ps constant v<1> +// CHECK: dxsa.dcl_input_ps constant v<2> +// CHECK: dxsa.dcl_output o<0> +// CHECK: dxsa.dcl_temps 3 +// CHECK: %[[INDEX_0:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_0:.*]] = dxsa.operand %[[INDEX_0]] {mask = 240 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_1:.*]] = dxsa.index.imm {imm = 1 : i32} +// CHECK: %[[OPERAND_1:.*]] = dxsa.operand %[[INDEX_1]] {num_components = 4 : i32, swizzle = dense<[0, 1, 2, 3]> : vector<4xi32>, type = 1 : i32} +// CHECK: dxsa.instruction "mov" %[[OPERAND_0]], %[[OPERAND_1]] +// CHECK: %[[INDEX_2:.*]] = dxsa.index.imm {imm = 1 : i32} +// CHECK: %[[OPERAND_2:.*]] = dxsa.operand %[[INDEX_2]] {mask = 240 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_3:.*]] = dxsa.index.imm {imm = 2 : i32} +// CHECK: %[[OPERAND_3:.*]] = dxsa.operand %[[INDEX_3]] {num_components = 4 : i32, swizzle = dense<[0, 1, 2, 3]> : vector<4xi32>, type = 1 : i32} +// CHECK: dxsa.instruction "mov" %[[OPERAND_2]], %[[OPERAND_3]] +// CHECK: %[[INDEX_4:.*]] = dxsa.index.imm {imm = 2 : i32} +// CHECK: %[[OPERAND_4:.*]] = dxsa.operand %[[INDEX_4]] {mask = 240 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_5:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_5:.*]] = dxsa.operand %[[INDEX_5]] {num_components = 4 : i32, swizzle = dense<[0, 1, 2, 3]> : vector<4xi32>, type = 1 : i32} +// CHECK: dxsa.instruction "mov" %[[OPERAND_4]], %[[OPERAND_5]] +// CHECK: %[[INDEX_6:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_6:.*]] = dxsa.operand %[[INDEX_6]] {mask = 240 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_7:.*]] = dxsa.index.imm {imm = 2 : i32} +// CHECK: %[[OPERAND_7:.*]] = dxsa.operand %[[INDEX_7]] {num_components = 4 : i32, swizzle = dense<[0, 1, 2, 3]> : vector<4xi32>, type = 0 : i32} +// CHECK: %[[INDEX_8:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_8:.*]] = dxsa.operand %[[INDEX_8]] {num_components = 4 : i32, swizzle = dense<[0, 1, 2, 3]> : vector<4xi32>, type = 0 : i32} +// CHECK: %[[INDEX_9:.*]] = dxsa.index.imm {imm = 1 : i32} +// CHECK: %[[OPERAND_9:.*]] = dxsa.operand %[[INDEX_9]] {num_components = 4 : i32, swizzle = dense<[0, 1, 2, 3]> : vector<4xi32>, type = 0 : i32} +// CHECK: dxsa.instruction "dfma" %[[OPERAND_6]], %[[OPERAND_7]], %[[OPERAND_8]], %[[OPERAND_9]] +// CHECK: %[[INDEX_10:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_10:.*]] = dxsa.operand %[[INDEX_10]] {mask = 240 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_11:.*]] = dxsa.index.imm {imm = 2 : i32} +// CHECK: %[[OPERAND_11:.*]] = dxsa.operand %[[INDEX_11]] {num_components = 4 : i32, swizzle = dense<[0, 1, 2, 3]> : vector<4xi32>, type = 0 : i32} +// CHECK: %[[INDEX_12:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_12:.*]] = dxsa.operand %[[INDEX_12]] {num_components = 4 : i32, swizzle = dense<[0, 1, 2, 3]> : vector<4xi32>, type = 0 : i32} +// CHECK: dxsa.instruction "dadd" %[[OPERAND_10]], %[[OPERAND_11]], %[[OPERAND_12]] +// CHECK: %[[INDEX_13:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_13:.*]] = dxsa.operand %[[INDEX_13]] {mask = 240 : i32, num_components = 4 : i32, type = 2 : i32} +// CHECK: %[[INDEX_14:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_14:.*]] = dxsa.operand %[[INDEX_14]] {num_components = 4 : i32, swizzle = dense<[0, 3, 0, 3]> : vector<4xi32>, type = 0 : i32} +// CHECK: dxsa.instruction "mov" %[[OPERAND_13]], %[[OPERAND_14]] +// CHECK: dxsa.instruction "ret" + diff --git a/mlir/test/Target/DXSA/hlsl/double5.test b/mlir/test/Target/DXSA/hlsl/double5.test new file mode 100644 index 000000000000..c719f0fb3f81 --- /dev/null +++ b/mlir/test/Target/DXSA/hlsl/double5.test @@ -0,0 +1,104 @@ +// RUN: mlir-translate --import-dxsa-bin %S/inputs/double5.bin | FileCheck %s +// NOTE: Assertions have been autogenerated by utils/generate-test-checks.py + +// This script is intended to make adding checks to a test case quick and easy. +// It is *not* authoritative about what constitutes a good test. After using the +// script, be sure to review and refine the generated checks. For example, +// CHECK lines should be minimized and named to reflect the test’s intent. +// For comprehensive guidelines, see: +// * https://mlir.llvm.org/getting_started/TestingGuide/ + + +// CHECK-LABEL: dxsa.dcl_global_flags +// CHECK: dxsa.dcl_input_ps constant v<0, > +// CHECK: dxsa.dcl_input_ps constant v<1, > +// CHECK: dxsa.dcl_input_ps constant v<2, > +// CHECK: dxsa.dcl_output o<0> +// CHECK: dxsa.dcl_temps 2 +// CHECK: %[[INDEX_0:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_0:.*]] = dxsa.operand %[[INDEX_0]] {mask = 48 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_1:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_1:.*]] = dxsa.operand %[[INDEX_1]] {num_components = 4 : i32, swizzle = dense<[0, 1, 0, 0]> : vector<4xi32>, type = 1 : i32} +// CHECK: dxsa.instruction "mov" %[[OPERAND_0]], %[[OPERAND_1]] +// CHECK: %[[INDEX_2:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_2:.*]] = dxsa.operand %[[INDEX_2]] {mask = 16 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_3:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_3:.*]] = dxsa.operand %[[INDEX_3]] {num_components = 4 : i32, swizzle = dense<[0, 1, 0, 1]> : vector<4xi32>, type = 0 : i32} +// CHECK: dxsa.instruction "dtof" %[[OPERAND_2]], %[[OPERAND_3]] +// CHECK: %[[INDEX_4:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_4:.*]] = dxsa.operand %[[INDEX_4]] {mask = 48 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_5:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_5:.*]] = dxsa.operand %[[INDEX_5]] {num_components = 4 : i32, one = 0 : i32, type = 0 : i32} +// CHECK: dxsa.instruction "ftod" %[[OPERAND_4]], %[[OPERAND_5]] +// CHECK: %[[INDEX_6:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_6:.*]] = dxsa.operand %[[INDEX_6]] {mask = 192 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_7:.*]] = dxsa.index.imm {imm = 1 : i32} +// CHECK: %[[OPERAND_7:.*]] = dxsa.operand %[[INDEX_7]] {num_components = 4 : i32, swizzle = dense<[0, 0, 0, 1]> : vector<4xi32>, type = 1 : i32} +// CHECK: dxsa.instruction "mov" %[[OPERAND_6]], %[[OPERAND_7]] +// CHECK: %[[INDEX_8:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_8:.*]] = dxsa.operand %[[INDEX_8]] {mask = 64 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_9:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_9:.*]] = dxsa.operand %[[INDEX_9]] {num_components = 4 : i32, swizzle = dense<[2, 3, 2, 3]> : vector<4xi32>, type = 0 : i32} +// CHECK: dxsa.instruction "dtoi" %[[OPERAND_8]], %[[OPERAND_9]] +// CHECK: %[[INDEX_10:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_10:.*]] = dxsa.operand %[[INDEX_10]] {mask = 192 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_11:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_11:.*]] = dxsa.operand %[[INDEX_11]] {num_components = 4 : i32, one = 2 : i32, type = 0 : i32} +// CHECK: dxsa.instruction "itod" %[[OPERAND_10]], %[[OPERAND_11]] +// CHECK: %[[INDEX_12:.*]] = dxsa.index.imm {imm = 1 : i32} +// CHECK: %[[OPERAND_12:.*]] = dxsa.operand %[[INDEX_12]] {mask = 48 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_13:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_13:.*]] = dxsa.operand %[[INDEX_13]] {num_components = 4 : i32, swizzle = dense<[2, 3, 2, 3]> : vector<4xi32>, type = 0 : i32} +// CHECK: %[[INDEX_14:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_14:.*]] = dxsa.operand %[[INDEX_14]] {num_components = 4 : i32, swizzle = dense<[0, 1, 0, 1]> : vector<4xi32>, type = 0 : i32} +// CHECK: dxsa.instruction "dadd" %[[OPERAND_12]], %[[OPERAND_13]], %[[OPERAND_14]] +// CHECK: %[[INDEX_15:.*]] = dxsa.index.imm {imm = 1 : i32} +// CHECK: %[[OPERAND_15:.*]] = dxsa.operand %[[INDEX_15]] {mask = 48 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_16:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_16:.*]] = dxsa.operand %[[INDEX_16]] {num_components = 4 : i32, swizzle = dense<[2, 3, 2, 3]> : vector<4xi32>, type = 0 : i32} +// CHECK: %[[INDEX_17:.*]] = dxsa.index.imm {imm = 1 : i32} +// CHECK: %[[OPERAND_17:.*]] = dxsa.operand %[[INDEX_17]] {num_components = 4 : i32, swizzle = dense<[0, 1, 0, 1]> : vector<4xi32>, type = 0 : i32} +// CHECK: dxsa.instruction "dadd" %[[OPERAND_15]], %[[OPERAND_16]], %[[OPERAND_17]] +// CHECK: %[[INDEX_18:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_18:.*]] = dxsa.operand %[[INDEX_18]] {mask = 48 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_19:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_19:.*]] = dxsa.operand %[[INDEX_19]] {num_components = 4 : i32, swizzle = dense<[0, 1, 0, 1]> : vector<4xi32>, type = 0 : i32} +// CHECK: %[[INDEX_20:.*]] = dxsa.index.imm {imm = 1 : i32} +// CHECK: %[[OPERAND_20:.*]] = dxsa.operand %[[INDEX_20]] {num_components = 4 : i32, swizzle = dense<[0, 1, 0, 1]> : vector<4xi32>, type = 0 : i32} +// CHECK: dxsa.instruction "dadd" %[[OPERAND_18]], %[[OPERAND_19]], %[[OPERAND_20]] +// CHECK: %[[INDEX_21:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_21:.*]] = dxsa.operand %[[INDEX_21]] {mask = 48 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_22:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_22:.*]] = dxsa.operand %[[INDEX_22]] {num_components = 4 : i32, swizzle = dense<[2, 3, 2, 3]> : vector<4xi32>, type = 0 : i32} +// CHECK: %[[INDEX_23:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_23:.*]] = dxsa.operand %[[INDEX_23]] {num_components = 4 : i32, swizzle = dense<[0, 1, 0, 1]> : vector<4xi32>, type = 0 : i32} +// CHECK: dxsa.instruction "dadd" %[[OPERAND_21]], %[[OPERAND_22]], %[[OPERAND_23]] +// CHECK: %[[INDEX_24:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_24:.*]] = dxsa.operand %[[INDEX_24]] {mask = 192 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_25:.*]] = dxsa.index.imm {imm = 2 : i32} +// CHECK: %[[OPERAND_25:.*]] = dxsa.operand %[[INDEX_25]] {num_components = 4 : i32, swizzle = dense<[0, 0, 0, 1]> : vector<4xi32>, type = 1 : i32} +// CHECK: dxsa.instruction "mov" %[[OPERAND_24]], %[[OPERAND_25]] +// CHECK: %[[INDEX_26:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_26:.*]] = dxsa.operand %[[INDEX_26]] {mask = 64 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_27:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_27:.*]] = dxsa.operand %[[INDEX_27]] {num_components = 4 : i32, swizzle = dense<[2, 3, 2, 3]> : vector<4xi32>, type = 0 : i32} +// CHECK: dxsa.instruction "dtou" %[[OPERAND_26]], %[[OPERAND_27]] +// CHECK: %[[INDEX_28:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_28:.*]] = dxsa.operand %[[INDEX_28]] {mask = 192 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_29:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_29:.*]] = dxsa.operand %[[INDEX_29]] {num_components = 4 : i32, one = 2 : i32, type = 0 : i32} +// CHECK: dxsa.instruction "utod" %[[OPERAND_28]], %[[OPERAND_29]] +// CHECK: %[[INDEX_30:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_30:.*]] = dxsa.operand %[[INDEX_30]] {mask = 48 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_31:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_31:.*]] = dxsa.operand %[[INDEX_31]] {num_components = 4 : i32, swizzle = dense<[2, 3, 2, 3]> : vector<4xi32>, type = 0 : i32} +// CHECK: %[[INDEX_32:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_32:.*]] = dxsa.operand %[[INDEX_32]] {num_components = 4 : i32, swizzle = dense<[0, 1, 0, 1]> : vector<4xi32>, type = 0 : i32} +// CHECK: dxsa.instruction "dadd" %[[OPERAND_30]], %[[OPERAND_31]], %[[OPERAND_32]] +// CHECK: %[[INDEX_33:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_33:.*]] = dxsa.operand %[[INDEX_33]] {mask = 240 : i32, num_components = 4 : i32, type = 2 : i32} +// CHECK: %[[INDEX_34:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_34:.*]] = dxsa.operand %[[INDEX_34]] {num_components = 4 : i32, swizzle = dense<[0, 1, 0, 1]> : vector<4xi32>, type = 0 : i32} +// CHECK: dxsa.instruction "mov" %[[OPERAND_33]], %[[OPERAND_34]] +// CHECK: dxsa.instruction "ret" + diff --git a/mlir/test/Target/DXSA/hlsl/double6.test b/mlir/test/Target/DXSA/hlsl/double6.test new file mode 100644 index 000000000000..d082fc9ed7fc --- /dev/null +++ b/mlir/test/Target/DXSA/hlsl/double6.test @@ -0,0 +1,175 @@ +// RUN: mlir-translate --import-dxsa-bin %S/inputs/double6.bin | FileCheck %s +// NOTE: Assertions have been autogenerated by utils/generate-test-checks.py + +// This script is intended to make adding checks to a test case quick and easy. +// It is *not* authoritative about what constitutes a good test. After using the +// script, be sure to review and refine the generated checks. For example, +// CHECK lines should be minimized and named to reflect the test’s intent. +// For comprehensive guidelines, see: +// * https://mlir.llvm.org/getting_started/TestingGuide/ + + +// CHECK-LABEL: dxsa.dcl_global_flags +// CHECK: dxsa.dcl_constant_buffer , +// CHECK: dxsa.dcl_input_ps constant v<0, > +// CHECK: dxsa.dcl_input_ps constant v<1, > +// CHECK: dxsa.dcl_input_ps constant v<2, > +// CHECK: dxsa.dcl_output o<0> +// CHECK: dxsa.dcl_temps 2 +// CHECK: dxsa.dcl_indexable_temp x<0>[6] +// CHECK: dxsa.dcl_indexable_temp x<1>[4] +// CHECK: %[[INDEX_0:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[INDEX_1:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_0:.*]] = dxsa.operand %[[INDEX_0]], %[[INDEX_1]] {mask = 48 : i32, num_components = 4 : i32, type = 3 : i32} +// CHECK: %[[OPERAND_1:.*]] = dxsa.operand.imm {imm = dense<[1075838976, 0]> : vector<2xi64>} +// CHECK: dxsa.instruction "dmov" %[[OPERAND_0]], %[[OPERAND_1]] +// CHECK: %[[INDEX_2:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[INDEX_3:.*]] = dxsa.index.imm {imm = 1 : i32} +// CHECK: %[[OPERAND_2:.*]] = dxsa.operand %[[INDEX_2]], %[[INDEX_3]] {mask = 48 : i32, num_components = 4 : i32, type = 3 : i32} +// CHECK: %[[OPERAND_3:.*]] = dxsa.operand.imm {imm = dense<[1072693248, 0]> : vector<2xi64>} +// CHECK: dxsa.instruction "dmov" %[[OPERAND_2]], %[[OPERAND_3]] +// CHECK: %[[INDEX_4:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[INDEX_5:.*]] = dxsa.index.imm {imm = 2 : i32} +// CHECK: %[[OPERAND_4:.*]] = dxsa.operand %[[INDEX_4]], %[[INDEX_5]] {mask = 48 : i32, num_components = 4 : i32, type = 3 : i32} +// CHECK: %[[OPERAND_5:.*]] = dxsa.operand.imm {imm = dense<[1073741824, 0]> : vector<2xi64>} +// CHECK: dxsa.instruction "dmov" %[[OPERAND_4]], %[[OPERAND_5]] +// CHECK: %[[INDEX_6:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[INDEX_7:.*]] = dxsa.index.imm {imm = 3 : i32} +// CHECK: %[[OPERAND_6:.*]] = dxsa.operand %[[INDEX_6]], %[[INDEX_7]] {mask = 48 : i32, num_components = 4 : i32, type = 3 : i32} +// CHECK: %[[OPERAND_7:.*]] = dxsa.operand.imm {imm = dense<[4611686019501947617, 0]> : vector<2xi64>} +// CHECK: dxsa.instruction "dmov" %[[OPERAND_6]], %[[OPERAND_7]] +// CHECK: %[[INDEX_8:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[INDEX_9:.*]] = dxsa.index.imm {imm = 4 : i32} +// CHECK: %[[OPERAND_8:.*]] = dxsa.operand %[[INDEX_8]], %[[INDEX_9]] {mask = 48 : i32, num_components = 4 : i32, type = 3 : i32} +// CHECK: %[[OPERAND_9:.*]] = dxsa.operand.imm {imm = dense<[1075576832, 0]> : vector<2xi64>} +// CHECK: dxsa.instruction "dmov" %[[OPERAND_8]], %[[OPERAND_9]] +// CHECK: %[[INDEX_10:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[INDEX_11:.*]] = dxsa.index.imm {imm = 5 : i32} +// CHECK: %[[OPERAND_10:.*]] = dxsa.operand %[[INDEX_10]], %[[INDEX_11]] {mask = 48 : i32, num_components = 4 : i32, type = 3 : i32} +// CHECK: %[[OPERAND_11:.*]] = dxsa.operand.imm {imm = dense<[1077968896, 0]> : vector<2xi64>} +// CHECK: dxsa.instruction "dmov" %[[OPERAND_10]], %[[OPERAND_11]] +// CHECK: %[[INDEX_12:.*]] = dxsa.index.imm {imm = 1 : i32} +// CHECK: %[[INDEX_13:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_12:.*]] = dxsa.operand %[[INDEX_12]], %[[INDEX_13]] {mask = 48 : i32, num_components = 4 : i32, type = 3 : i32} +// CHECK: %[[OPERAND_13:.*]] = dxsa.operand.imm {imm = dense<[1072693248, 0]> : vector<2xi64>} +// CHECK: dxsa.instruction "dmov" %[[OPERAND_12]], %[[OPERAND_13]] +// CHECK: %[[INDEX_14:.*]] = dxsa.index.imm {imm = 1 : i32} +// CHECK: %[[INDEX_15:.*]] = dxsa.index.imm {imm = 1 : i32} +// CHECK: %[[OPERAND_14:.*]] = dxsa.operand %[[INDEX_14]], %[[INDEX_15]] {mask = 48 : i32, num_components = 4 : i32, type = 3 : i32} +// CHECK: %[[OPERAND_15:.*]] = dxsa.operand.imm {imm = dense<[1073741824, 0]> : vector<2xi64>} +// CHECK: dxsa.instruction "dmov" %[[OPERAND_14]], %[[OPERAND_15]] +// CHECK: %[[INDEX_16:.*]] = dxsa.index.imm {imm = 1 : i32} +// CHECK: %[[INDEX_17:.*]] = dxsa.index.imm {imm = 2 : i32} +// CHECK: %[[OPERAND_16:.*]] = dxsa.operand %[[INDEX_16]], %[[INDEX_17]] {mask = 48 : i32, num_components = 4 : i32, type = 3 : i32} +// CHECK: %[[OPERAND_17:.*]] = dxsa.operand.imm {imm = dense<[4611686019501947617, 0]> : vector<2xi64>} +// CHECK: dxsa.instruction "dmov" %[[OPERAND_16]], %[[OPERAND_17]] +// CHECK: %[[INDEX_18:.*]] = dxsa.index.imm {imm = 1 : i32} +// CHECK: %[[INDEX_19:.*]] = dxsa.index.imm {imm = 3 : i32} +// CHECK: %[[OPERAND_18:.*]] = dxsa.operand %[[INDEX_18]], %[[INDEX_19]] {mask = 48 : i32, num_components = 4 : i32, type = 3 : i32} +// CHECK: %[[OPERAND_19:.*]] = dxsa.operand.imm {imm = dense<[1075576832, 0]> : vector<2xi64>} +// CHECK: dxsa.instruction "dmov" %[[OPERAND_18]], %[[OPERAND_19]] +// CHECK: %[[INDEX_20:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_20:.*]] = dxsa.operand %[[INDEX_20]] {mask = 48 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_21:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[INDEX_22:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_21:.*]] = dxsa.operand %[[INDEX_21]], %[[INDEX_22]] {num_components = 4 : i32, swizzle = dense<[0, 1, 0, 0]> : vector<4xi32>, type = 8 : i32} +// CHECK: dxsa.instruction "mov" %[[OPERAND_20]], %[[OPERAND_21]] +// CHECK: %[[INDEX_23:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_22:.*]] = dxsa.operand %[[INDEX_23]] {mask = 192 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_24:.*]] = dxsa.index.imm {imm = 1 : i32} +// CHECK: %[[INDEX_25:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_23:.*]] = dxsa.operand %[[INDEX_25]] {num_components = 4 : i32, one = 0 : i32, type = 0 : i32} +// CHECK: %[[INDEX_26:.*]] = dxsa.index.rel %[[OPERAND_23]] +// CHECK: %[[OPERAND_24:.*]] = dxsa.operand %[[INDEX_24]], %[[INDEX_26]] {num_components = 4 : i32, swizzle = dense<[0, 1, 0, 1]> : vector<4xi32>, type = 3 : i32} +// CHECK: dxsa.instruction "dmov" %[[OPERAND_22]], %[[OPERAND_24]] +// CHECK: %[[INDEX_27:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_25:.*]] = dxsa.operand %[[INDEX_27]] {mask = 192 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_28:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_26:.*]] = dxsa.operand %[[INDEX_28]] {num_components = 4 : i32, swizzle = dense<[2, 3, 2, 3]> : vector<4xi32>, type = 0 : i32} +// CHECK: %[[INDEX_29:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[INDEX_30:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_27:.*]] = dxsa.operand %[[INDEX_30]] {num_components = 4 : i32, one = 0 : i32, type = 0 : i32} +// CHECK: %[[INDEX_31:.*]] = dxsa.index.rel.imm %[[OPERAND_27]] {imm = 1 : i32, op = "add"} +// CHECK: %[[OPERAND_28:.*]] = dxsa.operand %[[INDEX_29]], %[[INDEX_31]] {num_components = 4 : i32, swizzle = dense<[0, 1, 0, 1]> : vector<4xi32>, type = 8 : i32} +// CHECK: dxsa.instruction "dadd" %[[OPERAND_25]], %[[OPERAND_26]], %[[OPERAND_28]] +// CHECK: %[[INDEX_32:.*]] = dxsa.index.imm {imm = 1 : i32} +// CHECK: %[[OPERAND_29:.*]] = dxsa.operand %[[INDEX_32]] {mask = 48 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_33:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[INDEX_34:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_30:.*]] = dxsa.operand %[[INDEX_34]] {num_components = 4 : i32, one = 1 : i32, type = 0 : i32} +// CHECK: %[[INDEX_35:.*]] = dxsa.index.rel %[[OPERAND_30]] +// CHECK: %[[OPERAND_31:.*]] = dxsa.operand %[[INDEX_33]], %[[INDEX_35]] {num_components = 4 : i32, swizzle = dense<[0, 1, 0, 1]> : vector<4xi32>, type = 3 : i32} +// CHECK: dxsa.instruction "dmov" %[[OPERAND_29]], %[[OPERAND_31]] +// CHECK: %[[INDEX_36:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_32:.*]] = dxsa.operand %[[INDEX_36]] {mask = 192 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_37:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_33:.*]] = dxsa.operand %[[INDEX_37]] {num_components = 4 : i32, swizzle = dense<[2, 3, 2, 3]> : vector<4xi32>, type = 0 : i32} +// CHECK: %[[INDEX_38:.*]] = dxsa.index.imm {imm = 1 : i32} +// CHECK: %[[OPERAND_34:.*]] = dxsa.operand %[[INDEX_38]] {num_components = 4 : i32, swizzle = dense<[0, 1, 0, 1]> : vector<4xi32>, type = 0 : i32} +// CHECK: dxsa.instruction "dadd" %[[OPERAND_32]], %[[OPERAND_33]], %[[OPERAND_34]] +// CHECK: %[[INDEX_39:.*]] = dxsa.index.imm {imm = 1 : i32} +// CHECK: %[[OPERAND_35:.*]] = dxsa.operand %[[INDEX_39]] {mask = 48 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_40:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_36:.*]] = dxsa.operand %[[INDEX_40]] {num_components = 4 : i32, swizzle = dense<[0, 1, 0, 0]> : vector<4xi32>, type = 1 : i32} +// CHECK: dxsa.instruction "mov" %[[OPERAND_35]], %[[OPERAND_36]] +// CHECK: %[[INDEX_41:.*]] = dxsa.index.imm {imm = 1 : i32} +// CHECK: %[[OPERAND_37:.*]] = dxsa.operand %[[INDEX_41]] {mask = 192 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_42:.*]] = dxsa.index.imm {imm = 1 : i32} +// CHECK: %[[OPERAND_38:.*]] = dxsa.operand %[[INDEX_42]] {num_components = 4 : i32, swizzle = dense<[0, 0, 0, 1]> : vector<4xi32>, type = 1 : i32} +// CHECK: dxsa.instruction "mov" %[[OPERAND_37]], %[[OPERAND_38]] +// CHECK: %[[INDEX_43:.*]] = dxsa.index.imm {imm = 1 : i32} +// CHECK: %[[OPERAND_39:.*]] = dxsa.operand %[[INDEX_43]] {mask = 48 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_44:.*]] = dxsa.index.imm {imm = 1 : i32} +// CHECK: %[[OPERAND_40:.*]] = dxsa.operand %[[INDEX_44]] {num_components = 4 : i32, swizzle = dense<[2, 3, 2, 3]> : vector<4xi32>, type = 0 : i32} +// CHECK: %[[INDEX_45:.*]] = dxsa.index.imm {imm = 1 : i32} +// CHECK: %[[OPERAND_41:.*]] = dxsa.operand %[[INDEX_45]] {num_components = 4 : i32, swizzle = dense<[0, 1, 0, 1]> : vector<4xi32>, type = 0 : i32} +// CHECK: dxsa.instruction "dadd" %[[OPERAND_39]], %[[OPERAND_40]], %[[OPERAND_41]] +// CHECK: %[[INDEX_46:.*]] = dxsa.index.imm {imm = 1 : i32} +// CHECK: %[[OPERAND_42:.*]] = dxsa.operand %[[INDEX_46]] {mask = 192 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_47:.*]] = dxsa.index.imm {imm = 2 : i32} +// CHECK: %[[OPERAND_43:.*]] = dxsa.operand %[[INDEX_47]] {num_components = 4 : i32, swizzle = dense<[0, 0, 0, 1]> : vector<4xi32>, type = 1 : i32} +// CHECK: dxsa.instruction "mov" %[[OPERAND_42]], %[[OPERAND_43]] +// CHECK: %[[INDEX_48:.*]] = dxsa.index.imm {imm = 1 : i32} +// CHECK: %[[OPERAND_44:.*]] = dxsa.operand %[[INDEX_48]] {mask = 48 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_49:.*]] = dxsa.index.imm {imm = 1 : i32} +// CHECK: %[[OPERAND_45:.*]] = dxsa.operand %[[INDEX_49]] {num_components = 4 : i32, swizzle = dense<[2, 3, 2, 3]> : vector<4xi32>, type = 0 : i32} +// CHECK: %[[INDEX_50:.*]] = dxsa.index.imm {imm = 1 : i32} +// CHECK: %[[OPERAND_46:.*]] = dxsa.operand %[[INDEX_50]] {num_components = 4 : i32, swizzle = dense<[0, 1, 0, 1]> : vector<4xi32>, type = 0 : i32} +// CHECK: dxsa.instruction "dadd" %[[OPERAND_44]], %[[OPERAND_45]], %[[OPERAND_46]] +// CHECK: %[[INDEX_51:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_47:.*]] = dxsa.operand %[[INDEX_51]] {mask = 192 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_52:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_48:.*]] = dxsa.operand %[[INDEX_52]] {num_components = 4 : i32, swizzle = dense<[2, 3, 2, 3]> : vector<4xi32>, type = 0 : i32} +// CHECK: %[[INDEX_53:.*]] = dxsa.index.imm {imm = 1 : i32} +// CHECK: %[[OPERAND_49:.*]] = dxsa.operand %[[INDEX_53]] {num_components = 4 : i32, swizzle = dense<[0, 1, 0, 1]> : vector<4xi32>, type = 0 : i32} +// CHECK: dxsa.instruction "dadd" %[[OPERAND_47]], %[[OPERAND_48]], %[[OPERAND_49]] +// CHECK: %[[INDEX_54:.*]] = dxsa.index.imm {imm = 1 : i32} +// CHECK: %[[INDEX_55:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_50:.*]] = dxsa.operand %[[INDEX_55]] {num_components = 4 : i32, one = 1 : i32, type = 0 : i32} +// CHECK: %[[INDEX_56:.*]] = dxsa.index.rel %[[OPERAND_50]] +// CHECK: %[[OPERAND_51:.*]] = dxsa.operand %[[INDEX_54]], %[[INDEX_56]] {mask = 48 : i32, num_components = 4 : i32, type = 3 : i32} +// CHECK: %[[INDEX_57:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_52:.*]] = dxsa.operand %[[INDEX_57]] {num_components = 4 : i32, swizzle = dense<[2, 3, 2, 3]> : vector<4xi32>, type = 0 : i32} +// CHECK: dxsa.instruction "dmov" %[[OPERAND_51]], %[[OPERAND_52]] +// CHECK: %[[INDEX_58:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_53:.*]] = dxsa.operand %[[INDEX_58]] {mask = 48 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_59:.*]] = dxsa.index.imm {imm = 1 : i32} +// CHECK: %[[INDEX_60:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_54:.*]] = dxsa.operand %[[INDEX_60]] {num_components = 4 : i32, one = 0 : i32, type = 0 : i32} +// CHECK: %[[INDEX_61:.*]] = dxsa.index.rel %[[OPERAND_54]] +// CHECK: %[[OPERAND_55:.*]] = dxsa.operand %[[INDEX_59]], %[[INDEX_61]] {num_components = 4 : i32, swizzle = dense<[0, 1, 0, 1]> : vector<4xi32>, type = 3 : i32} +// CHECK: dxsa.instruction "dmov" %[[OPERAND_53]], %[[OPERAND_55]] +// CHECK: %[[INDEX_62:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_56:.*]] = dxsa.operand %[[INDEX_62]] {mask = 48 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_63:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_57:.*]] = dxsa.operand %[[INDEX_63]] {num_components = 4 : i32, swizzle = dense<[0, 1, 0, 1]> : vector<4xi32>, type = 0 : i32} +// CHECK: %[[INDEX_64:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_58:.*]] = dxsa.operand %[[INDEX_64]] {num_components = 4 : i32, swizzle = dense<[2, 3, 2, 3]> : vector<4xi32>, type = 0 : i32} +// CHECK: dxsa.instruction "dadd" %[[OPERAND_56]], %[[OPERAND_57]], %[[OPERAND_58]] +// CHECK: %[[INDEX_65:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_59:.*]] = dxsa.operand %[[INDEX_65]] {mask = 240 : i32, num_components = 4 : i32, type = 2 : i32} +// CHECK: %[[INDEX_66:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_60:.*]] = dxsa.operand %[[INDEX_66]] {num_components = 4 : i32, swizzle = dense<[0, 1, 0, 1]> : vector<4xi32>, type = 0 : i32} +// CHECK: dxsa.instruction "mov" %[[OPERAND_59]], %[[OPERAND_60]] +// CHECK: dxsa.instruction "ret" + diff --git a/mlir/test/Target/DXSA/hlsl/ds1.test b/mlir/test/Target/DXSA/hlsl/ds1.test new file mode 100644 index 000000000000..ddca404c8ef7 --- /dev/null +++ b/mlir/test/Target/DXSA/hlsl/ds1.test @@ -0,0 +1,68 @@ +// RUN: mlir-translate --import-dxsa-bin %S/inputs/ds1.bin | FileCheck %s +// NOTE: Assertions have been autogenerated by utils/generate-test-checks.py + +// This script is intended to make adding checks to a test case quick and easy. +// It is *not* authoritative about what constitutes a good test. After using the +// script, be sure to review and refine the generated checks. For example, +// CHECK lines should be minimized and named to reflect the test’s intent. +// For comprehensive guidelines, see: +// * https://mlir.llvm.org/getting_started/TestingGuide/ + + +// CHECK-LABEL: dxsa.dcl_input_control_point_count 16 +// CHECK: dxsa.dcl_tessellator_domain domain_quad +// CHECK: dxsa.dcl_global_flags +// CHECK: dxsa.dcl_constant_buffer , +// CHECK: dxsa.dcl_input_siv vpc<0, >, +// CHECK: dxsa.dcl_input_siv vpc<1, >, +// CHECK: dxsa.dcl_input_siv vpc<2, >, +// CHECK: dxsa.dcl_input_siv vpc<3, >, +// CHECK: dxsa.dcl_input_siv vpc<4, >, +// CHECK: dxsa.dcl_input_siv vpc<5, >, +// CHECK: dxsa.dcl_input vpc<6> +// CHECK: dxsa.dcl_input vpc<7, > +// CHECK: dxsa.dcl_input vpc<8, > +// CHECK: dxsa.dcl_input vpc<9, > +// CHECK: dxsa.dcl_input vDomain<> +// CHECK: dxsa.dcl_input vicp<[16, 0], > +// CHECK: dxsa.dcl_output_siv o<0>, +// CHECK: dxsa.dcl_temps 2 +// CHECK: dxsa.dcl_index_range vpc<7, >, 3 +// CHECK: %[[INDEX_0:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_0:.*]] = dxsa.operand %[[INDEX_0]] {mask = 240 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[OPERAND_1:.*]] = dxsa.operand.imm {imm = dense<0> : vector<4xi32>} +// CHECK: dxsa.instruction "mov" %[[OPERAND_0]], %[[OPERAND_1]] +// CHECK: %[[INDEX_1:.*]] = dxsa.index.imm {imm = 1 : i32} +// CHECK: %[[OPERAND_2:.*]] = dxsa.operand %[[INDEX_1]] {mask = 16 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[OPERAND_3:.*]] = dxsa.operand.imm {imm = dense<0> : vector<1xi32>} +// CHECK: dxsa.instruction "mov" %[[OPERAND_2]], %[[OPERAND_3]] +// CHECK: dxsa.instruction "loop" +// CHECK: dxsa.ige r<1, >, r<1, >, l(0x10) +// CHECK: %[[INDEX_2:.*]] = dxsa.index.imm {imm = 1 : i32} +// CHECK: %[[OPERAND_4:.*]] = dxsa.operand %[[INDEX_2]] {num_components = 4 : i32, one = 1 : i32, type = 0 : i32} +// CHECK: dxsa.instruction "breakc" %[[OPERAND_4]] +// CHECK: dxsa.add r<0>, r<0>, vicp<[r<1, >, 0], > +// CHECK: %[[INDEX_3:.*]] = dxsa.index.imm {imm = 1 : i32} +// CHECK: %[[OPERAND_5:.*]] = dxsa.operand %[[INDEX_3]] {mask = 16 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_4:.*]] = dxsa.index.imm {imm = 1 : i32} +// CHECK: %[[OPERAND_6:.*]] = dxsa.operand %[[INDEX_4]] {num_components = 4 : i32, one = 0 : i32, type = 0 : i32} +// CHECK: %[[OPERAND_7:.*]] = dxsa.operand.imm {imm = dense<1> : vector<1xi32>} +// CHECK: dxsa.instruction "iadd" %[[OPERAND_5]], %[[OPERAND_6]], %[[OPERAND_7]] +// CHECK: dxsa.instruction "endloop" +// CHECK: dxsa.add r<0>, r<0>, vpc<0, > +// CHECK: dxsa.mad r<0>, vpc<1, >, l(0x40000000, 0x40000000, 0x40000000, 0x40000000), r<0> +// CHECK: dxsa.mad r<0>, vpc<2, >, l(0x40400000, 0x40400000, 0x40400000, 0x40400000), r<0> +// CHECK: dxsa.mad r<0>, vpc<3, >, l(0x40800000, 0x40800000, 0x40800000, 0x40800000), r<0> +// CHECK: dxsa.add r<1, >, vpc<4, >, vpc<5, > +// CHECK: dxsa.add r<0>, r<0>, r<1, > +// CHECK: %[[INDEX_5:.*]] = dxsa.index.imm {imm = 1 : i32} +// CHECK: %[[OPERAND_8:.*]] = dxsa.operand %[[INDEX_5]] {mask = 16 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_6:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[INDEX_7:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_9:.*]] = dxsa.operand %[[INDEX_6]], %[[INDEX_7]] {num_components = 4 : i32, one = 0 : i32, type = 8 : i32} +// CHECK: dxsa.instruction "mov" %[[OPERAND_8]], %[[OPERAND_9]] +// CHECK: dxsa.add r<1>, vpc<6, >, vpc<7 + r<1, >, > +// CHECK: dxsa.add r<0>, r<0>, r<1> +// CHECK: dxsa.mul o<0>, r<0>, vDomain<> +// CHECK: dxsa.instruction "ret" + diff --git a/mlir/test/Target/DXSA/hlsl/empty.test b/mlir/test/Target/DXSA/hlsl/empty.test new file mode 100644 index 000000000000..a1e6d3887751 --- /dev/null +++ b/mlir/test/Target/DXSA/hlsl/empty.test @@ -0,0 +1,14 @@ +// RUN: mlir-translate --import-dxsa-bin %S/inputs/empty.bin | FileCheck %s +// NOTE: Assertions have been autogenerated by utils/generate-test-checks.py + +// This script is intended to make adding checks to a test case quick and easy. +// It is *not* authoritative about what constitutes a good test. After using the +// script, be sure to review and refine the generated checks. For example, +// CHECK lines should be minimized and named to reflect the test’s intent. +// For comprehensive guidelines, see: +// * https://mlir.llvm.org/getting_started/TestingGuide/ + + +// CHECK-LABEL: dxsa.dcl_global_flags +// CHECK: dxsa.instruction "ret" + diff --git a/mlir/test/Target/DXSA/hlsl/eval.test b/mlir/test/Target/DXSA/hlsl/eval.test new file mode 100644 index 000000000000..1f738fd78a6e --- /dev/null +++ b/mlir/test/Target/DXSA/hlsl/eval.test @@ -0,0 +1,89 @@ +// RUN: mlir-translate --import-dxsa-bin %S/inputs/eval.bin | FileCheck %s +// NOTE: Assertions have been autogenerated by utils/generate-test-checks.py + +// This script is intended to make adding checks to a test case quick and easy. +// It is *not* authoritative about what constitutes a good test. After using the +// script, be sure to review and refine the generated checks. For example, +// CHECK lines should be minimized and named to reflect the test’s intent. +// For comprehensive guidelines, see: +// * https://mlir.llvm.org/getting_started/TestingGuide/ + + +// CHECK-LABEL: dxsa.dcl_global_flags +// CHECK: dxsa.dcl_input_ps linear v<0> +// CHECK: dxsa.dcl_input_ps constant v<1, > +// CHECK: dxsa.dcl_input_ps linear v<2> +// CHECK: dxsa.dcl_input_ps linear v<3> +// CHECK: dxsa.dcl_input_ps linear v<4> +// CHECK: dxsa.dcl_input_ps linear v<5> +// CHECK: dxsa.dcl_input_ps linear v<6> +// CHECK: dxsa.dcl_input_ps linear v<7> +// CHECK: dxsa.dcl_output o<0> +// CHECK: dxsa.dcl_temps 3 +// CHECK: dxsa.dcl_index_range v<2>, 6 +// CHECK: %[[INDEX_0:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_0:.*]] = dxsa.operand %[[INDEX_0]] {mask = 240 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_1:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_1:.*]] = dxsa.operand %[[INDEX_1]] {num_components = 4 : i32, swizzle = dense<[0, 1, 2, 3]> : vector<4xi32>, type = 1 : i32} +// CHECK: %[[INDEX_2:.*]] = dxsa.index.imm {imm = 1 : i32} +// CHECK: %[[OPERAND_2:.*]] = dxsa.operand %[[INDEX_2]] {num_components = 4 : i32, one = 0 : i32, type = 1 : i32} +// CHECK: dxsa.instruction "eval_sample_index" %[[OPERAND_0]], %[[OPERAND_1]], %[[OPERAND_2]] +// CHECK: %[[INDEX_3:.*]] = dxsa.index.imm {imm = 1 : i32} +// CHECK: %[[OPERAND_3:.*]] = dxsa.operand %[[INDEX_3]] {mask = 240 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_4:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_4:.*]] = dxsa.operand %[[INDEX_4]] {num_components = 4 : i32, swizzle = dense<[0, 1, 2, 3]> : vector<4xi32>, type = 1 : i32} +// CHECK: %[[OPERAND_5:.*]] = dxsa.operand.imm {imm = dense<3> : vector<1xi32>} +// CHECK: dxsa.instruction "eval_sample_index" %[[OPERAND_3]], %[[OPERAND_4]], %[[OPERAND_5]] +// CHECK: dxsa.add r<0>, r<0>, r<1> +// CHECK: %[[INDEX_5:.*]] = dxsa.index.imm {imm = 1 : i32} +// CHECK: %[[OPERAND_6:.*]] = dxsa.operand %[[INDEX_5]] {mask = 240 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_6:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_7:.*]] = dxsa.operand %[[INDEX_6]] {num_components = 4 : i32, swizzle = dense<[0, 1, 2, 3]> : vector<4xi32>, type = 1 : i32} +// CHECK: dxsa.instruction "eval_centroid" %[[OPERAND_6]], %[[OPERAND_7]] +// CHECK: dxsa.add r<0>, r<0>, r<1> +// CHECK: %[[INDEX_7:.*]] = dxsa.index.imm {imm = 1 : i32} +// CHECK: %[[OPERAND_8:.*]] = dxsa.operand %[[INDEX_7]] {mask = 240 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_8:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_9:.*]] = dxsa.operand %[[INDEX_8]] {num_components = 4 : i32, swizzle = dense<[0, 1, 2, 3]> : vector<4xi32>, type = 1 : i32} +// CHECK: %[[OPERAND_10:.*]] = dxsa.operand.imm {imm = dense<[-2, 5, 0, 0]> : vector<4xi32>} +// CHECK: dxsa.instruction "eval_snapped" %[[OPERAND_8]], %[[OPERAND_9]], %[[OPERAND_10]] +// CHECK: dxsa.add r<0>, r<0>, r<1> +// CHECK: %[[INDEX_9:.*]] = dxsa.index.imm {imm = 1 : i32} +// CHECK: %[[OPERAND_11:.*]] = dxsa.operand %[[INDEX_9]] {mask = 16 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_10:.*]] = dxsa.index.imm {imm = 1 : i32} +// CHECK: %[[OPERAND_12:.*]] = dxsa.operand %[[INDEX_10]] {num_components = 4 : i32, one = 1 : i32, type = 1 : i32} +// CHECK: dxsa.instruction "mov" %[[OPERAND_11]], %[[OPERAND_12]] +// CHECK: %[[INDEX_11:.*]] = dxsa.index.imm {imm = 1 : i32} +// CHECK: %[[OPERAND_13:.*]] = dxsa.operand %[[INDEX_11]] {mask = 240 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_12:.*]] = dxsa.index.imm {imm = 1 : i32} +// CHECK: %[[OPERAND_14:.*]] = dxsa.operand %[[INDEX_12]] {num_components = 4 : i32, one = 0 : i32, type = 0 : i32} +// CHECK: %[[INDEX_13:.*]] = dxsa.index.rel.imm %[[OPERAND_14]] {imm = 2 : i32, op = "add"} +// CHECK: %[[OPERAND_15:.*]] = dxsa.operand %[[INDEX_13]] {num_components = 4 : i32, swizzle = dense<[2, 2, 0, 1]> : vector<4xi32>, type = 1 : i32} +// CHECK: %[[INDEX_14:.*]] = dxsa.index.imm {imm = 1 : i32} +// CHECK: %[[OPERAND_16:.*]] = dxsa.operand %[[INDEX_14]] {num_components = 4 : i32, one = 0 : i32, type = 1 : i32} +// CHECK: dxsa.instruction "eval_sample_index" %[[OPERAND_13]], %[[OPERAND_15]], %[[OPERAND_16]] +// CHECK: dxsa.add r<0>, r<0>, r<1> +// CHECK: %[[INDEX_15:.*]] = dxsa.index.imm {imm = 1 : i32} +// CHECK: %[[OPERAND_17:.*]] = dxsa.operand %[[INDEX_15]] {mask = 16 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_16:.*]] = dxsa.index.imm {imm = 1 : i32} +// CHECK: %[[OPERAND_18:.*]] = dxsa.operand %[[INDEX_16]] {num_components = 4 : i32, one = 2 : i32, type = 1 : i32} +// CHECK: dxsa.instruction "mov" %[[OPERAND_17]], %[[OPERAND_18]] +// CHECK: %[[INDEX_17:.*]] = dxsa.index.imm {imm = 2 : i32} +// CHECK: %[[OPERAND_19:.*]] = dxsa.operand %[[INDEX_17]] {mask = 240 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_18:.*]] = dxsa.index.imm {imm = 1 : i32} +// CHECK: %[[OPERAND_20:.*]] = dxsa.operand %[[INDEX_18]] {num_components = 4 : i32, one = 0 : i32, type = 0 : i32} +// CHECK: %[[INDEX_19:.*]] = dxsa.index.rel.imm %[[OPERAND_20]] {imm = 2 : i32, op = "add"} +// CHECK: %[[OPERAND_21:.*]] = dxsa.operand %[[INDEX_19]] {num_components = 4 : i32, swizzle = dense<[0, 1, 2, 3]> : vector<4xi32>, type = 1 : i32} +// CHECK: dxsa.instruction "eval_centroid" %[[OPERAND_19]], %[[OPERAND_21]] +// CHECK: %[[INDEX_20:.*]] = dxsa.index.imm {imm = 1 : i32} +// CHECK: %[[OPERAND_22:.*]] = dxsa.operand %[[INDEX_20]] {mask = 240 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_21:.*]] = dxsa.index.imm {imm = 1 : i32} +// CHECK: %[[OPERAND_23:.*]] = dxsa.operand %[[INDEX_21]] {num_components = 4 : i32, one = 0 : i32, type = 0 : i32} +// CHECK: %[[INDEX_22:.*]] = dxsa.index.rel.imm %[[OPERAND_23]] {imm = 2 : i32, op = "add"} +// CHECK: %[[OPERAND_24:.*]] = dxsa.operand %[[INDEX_22]] {num_components = 4 : i32, swizzle = dense<[0, 1, 2, 3]> : vector<4xi32>, type = 1 : i32} +// CHECK: %[[OPERAND_25:.*]] = dxsa.operand.imm {imm = dense<[-2, 5, 0, 0]> : vector<4xi32>} +// CHECK: dxsa.instruction "eval_snapped" %[[OPERAND_22]], %[[OPERAND_24]], %[[OPERAND_25]] +// CHECK: dxsa.add r<0>, r<0>, r<2> +// CHECK: dxsa.add o<0>, r<1>, r<0> +// CHECK: dxsa.instruction "ret" + diff --git a/mlir/test/Target/DXSA/hlsl/f32f16.test b/mlir/test/Target/DXSA/hlsl/f32f16.test new file mode 100644 index 000000000000..3b191bca454b --- /dev/null +++ b/mlir/test/Target/DXSA/hlsl/f32f16.test @@ -0,0 +1,22 @@ +// RUN: mlir-translate --import-dxsa-bin %S/inputs/f32f16.bin | FileCheck %s +// NOTE: Assertions have been autogenerated by utils/generate-test-checks.py + +// This script is intended to make adding checks to a test case quick and easy. +// It is *not* authoritative about what constitutes a good test. After using the +// script, be sure to review and refine the generated checks. For example, +// CHECK lines should be minimized and named to reflect the test’s intent. +// For comprehensive guidelines, see: +// * https://mlir.llvm.org/getting_started/TestingGuide/ + + +// CHECK-LABEL: dxsa.dcl_global_flags +// CHECK: dxsa.dcl_input_ps linear v<0, > +// CHECK: dxsa.dcl_input_ps constant v<1, > +// CHECK: dxsa.dcl_output o<0> +// CHECK: dxsa.dcl_temps 2 +// CHECK: dxsa.f32tof16 r<0>, v<0, > +// CHECK: dxsa.utof r<0>, r<0> +// CHECK: dxsa.f16tof32 r<1>, v<1, > +// CHECK: dxsa.add o<0>, r<0>, r<1> +// CHECK: dxsa.instruction "ret" + diff --git a/mlir/test/Target/DXSA/hlsl/gather.test b/mlir/test/Target/DXSA/hlsl/gather.test new file mode 100644 index 000000000000..afe46ee6ec7f --- /dev/null +++ b/mlir/test/Target/DXSA/hlsl/gather.test @@ -0,0 +1,51 @@ +// RUN: mlir-translate --import-dxsa-bin %S/inputs/gather.bin | FileCheck %s +// NOTE: Assertions have been autogenerated by utils/generate-test-checks.py + +// This script is intended to make adding checks to a test case quick and easy. +// It is *not* authoritative about what constitutes a good test. After using the +// script, be sure to review and refine the generated checks. For example, +// CHECK lines should be minimized and named to reflect the test’s intent. +// For comprehensive guidelines, see: +// * https://mlir.llvm.org/getting_started/TestingGuide/ + + +// CHECK-LABEL: dxsa.dcl_global_flags +// CHECK: dxsa.dcl_sampler +// CHECK: dxsa.dcl_resource , , +// CHECK: dxsa.dcl_resource , , +// CHECK: dxsa.dcl_resource , , +// CHECK: dxsa.dcl_input_ps linear v<0> +// CHECK: dxsa.dcl_output o<0> +// CHECK: dxsa.dcl_temps 3 +// CHECK: dxsa.unknown +// CHECK: dxsa.unknown +// CHECK: dxsa.add r<0>, r<0>, r<1> +// CHECK: dxsa.unknown +// CHECK: dxsa.add r<0>, r<0>, r<1> +// CHECK: %[[INDEX_0:.*]] = dxsa.index.imm {imm = 1 : i32} +// CHECK: %[[OPERAND_0:.*]] = dxsa.operand %[[INDEX_0]] {mask = 16 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_1:.*]] = dxsa.index.imm {imm = 2 : i32} +// CHECK: %[[OPERAND_1:.*]] = dxsa.operand %[[INDEX_1]] {num_components = 4 : i32, one = 0 : i32, type = 0 : i32} +// CHECK: dxsa.instruction "check_access_fully_mapped" %[[OPERAND_0]], %[[OPERAND_1]] +// CHECK: dxsa.utof r<1, >, r<1, > +// CHECK: dxsa.add r<0>, r<0>, r<1, > +// CHECK: dxsa.unknown +// CHECK: dxsa.add r<0>, r<0>, r<1> +// CHECK: %[[INDEX_2:.*]] = dxsa.index.imm {imm = 1 : i32} +// CHECK: %[[OPERAND_2:.*]] = dxsa.operand %[[INDEX_2]] {mask = 16 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_3:.*]] = dxsa.index.imm {imm = 2 : i32} +// CHECK: %[[OPERAND_3:.*]] = dxsa.operand %[[INDEX_3]] {num_components = 4 : i32, one = 0 : i32, type = 0 : i32} +// CHECK: dxsa.instruction "check_access_fully_mapped" %[[OPERAND_2]], %[[OPERAND_3]] +// CHECK: dxsa.utof r<1, >, r<1, > +// CHECK: dxsa.add r<0>, r<0>, r<1, > +// CHECK: dxsa.unknown +// CHECK: dxsa.add r<0>, r<0>, r<1> +// CHECK: %[[INDEX_4:.*]] = dxsa.index.imm {imm = 1 : i32} +// CHECK: %[[OPERAND_4:.*]] = dxsa.operand %[[INDEX_4]] {mask = 16 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_5:.*]] = dxsa.index.imm {imm = 2 : i32} +// CHECK: %[[OPERAND_5:.*]] = dxsa.operand %[[INDEX_5]] {num_components = 4 : i32, one = 0 : i32, type = 0 : i32} +// CHECK: dxsa.instruction "check_access_fully_mapped" %[[OPERAND_4]], %[[OPERAND_5]] +// CHECK: dxsa.utof r<1, >, r<1, > +// CHECK: dxsa.add o<0>, r<0>, r<1, > +// CHECK: dxsa.instruction "ret" + diff --git a/mlir/test/Target/DXSA/hlsl/gather_cmp.test b/mlir/test/Target/DXSA/hlsl/gather_cmp.test new file mode 100644 index 000000000000..ead4e4302d29 --- /dev/null +++ b/mlir/test/Target/DXSA/hlsl/gather_cmp.test @@ -0,0 +1,51 @@ +// RUN: mlir-translate --import-dxsa-bin %S/inputs/gather_cmp.bin | FileCheck %s +// NOTE: Assertions have been autogenerated by utils/generate-test-checks.py + +// This script is intended to make adding checks to a test case quick and easy. +// It is *not* authoritative about what constitutes a good test. After using the +// script, be sure to review and refine the generated checks. For example, +// CHECK lines should be minimized and named to reflect the test’s intent. +// For comprehensive guidelines, see: +// * https://mlir.llvm.org/getting_started/TestingGuide/ + + +// CHECK-LABEL: dxsa.dcl_global_flags +// CHECK: dxsa.dcl_sampler +// CHECK: dxsa.dcl_resource , , +// CHECK: dxsa.dcl_resource , , +// CHECK: dxsa.dcl_resource , , +// CHECK: dxsa.dcl_input_ps linear v<0> +// CHECK: dxsa.dcl_output o<0> +// CHECK: dxsa.dcl_temps 3 +// CHECK: dxsa.unknown +// CHECK: dxsa.unknown +// CHECK: dxsa.add r<0>, r<0>, r<1> +// CHECK: dxsa.unknown +// CHECK: dxsa.add r<0>, r<0>, r<1> +// CHECK: %[[INDEX_0:.*]] = dxsa.index.imm {imm = 1 : i32} +// CHECK: %[[OPERAND_0:.*]] = dxsa.operand %[[INDEX_0]] {mask = 16 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_1:.*]] = dxsa.index.imm {imm = 2 : i32} +// CHECK: %[[OPERAND_1:.*]] = dxsa.operand %[[INDEX_1]] {num_components = 4 : i32, one = 0 : i32, type = 0 : i32} +// CHECK: dxsa.instruction "check_access_fully_mapped" %[[OPERAND_0]], %[[OPERAND_1]] +// CHECK: dxsa.utof r<1, >, r<1, > +// CHECK: dxsa.add r<0>, r<0>, r<1, > +// CHECK: dxsa.unknown +// CHECK: dxsa.add r<0>, r<0>, r<1> +// CHECK: %[[INDEX_2:.*]] = dxsa.index.imm {imm = 1 : i32} +// CHECK: %[[OPERAND_2:.*]] = dxsa.operand %[[INDEX_2]] {mask = 16 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_3:.*]] = dxsa.index.imm {imm = 2 : i32} +// CHECK: %[[OPERAND_3:.*]] = dxsa.operand %[[INDEX_3]] {num_components = 4 : i32, one = 0 : i32, type = 0 : i32} +// CHECK: dxsa.instruction "check_access_fully_mapped" %[[OPERAND_2]], %[[OPERAND_3]] +// CHECK: dxsa.utof r<1, >, r<1, > +// CHECK: dxsa.add r<0>, r<0>, r<1, > +// CHECK: dxsa.unknown +// CHECK: dxsa.add r<0>, r<0>, r<1> +// CHECK: %[[INDEX_4:.*]] = dxsa.index.imm {imm = 1 : i32} +// CHECK: %[[OPERAND_4:.*]] = dxsa.operand %[[INDEX_4]] {mask = 16 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_5:.*]] = dxsa.index.imm {imm = 2 : i32} +// CHECK: %[[OPERAND_5:.*]] = dxsa.operand %[[INDEX_5]] {num_components = 4 : i32, one = 0 : i32, type = 0 : i32} +// CHECK: dxsa.instruction "check_access_fully_mapped" %[[OPERAND_4]], %[[OPERAND_5]] +// CHECK: dxsa.utof r<1, >, r<1, > +// CHECK: dxsa.add o<0>, r<0>, r<1, > +// CHECK: dxsa.instruction "ret" + diff --git a/mlir/test/Target/DXSA/hlsl/gather_po.test b/mlir/test/Target/DXSA/hlsl/gather_po.test new file mode 100644 index 000000000000..a8efd9b6296e --- /dev/null +++ b/mlir/test/Target/DXSA/hlsl/gather_po.test @@ -0,0 +1,87 @@ +// RUN: mlir-translate --import-dxsa-bin %S/inputs/gather_po.bin | FileCheck %s +// NOTE: Assertions have been autogenerated by utils/generate-test-checks.py + +// This script is intended to make adding checks to a test case quick and easy. +// It is *not* authoritative about what constitutes a good test. After using the +// script, be sure to review and refine the generated checks. For example, +// CHECK lines should be minimized and named to reflect the test’s intent. +// For comprehensive guidelines, see: +// * https://mlir.llvm.org/getting_started/TestingGuide/ + + +// CHECK-LABEL: dxsa.dcl_global_flags +// CHECK: dxsa.dcl_sampler +// CHECK: dxsa.dcl_resource , , +// CHECK: dxsa.dcl_resource , , +// CHECK: dxsa.dcl_input_ps linear v<0> +// CHECK: dxsa.dcl_input_ps linear v<1> +// CHECK: dxsa.dcl_output o<0> +// CHECK: dxsa.dcl_temps 6 +// CHECK: dxsa.ftoi r<0>, v<1> +// CHECK: dxsa.unknown +// CHECK: dxsa.unknown +// CHECK: dxsa.ftoi r<2>, v<0> +// CHECK: dxsa.unknown +// CHECK: dxsa.unknown +// CHECK: dxsa.unknown +// CHECK: %[[INDEX_0:.*]] = dxsa.index.imm {imm = 4 : i32} +// CHECK: %[[OPERAND_0:.*]] = dxsa.operand %[[INDEX_0]] {mask = 16 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_1:.*]] = dxsa.index.imm {imm = 4 : i32} +// CHECK: %[[OPERAND_1:.*]] = dxsa.operand %[[INDEX_1]] {num_components = 4 : i32, one = 0 : i32, type = 0 : i32} +// CHECK: dxsa.instruction "check_access_fully_mapped" %[[OPERAND_0]], %[[OPERAND_1]] +// CHECK: dxsa.unknown +// CHECK: %[[INDEX_2:.*]] = dxsa.index.imm {imm = 4 : i32} +// CHECK: %[[OPERAND_2:.*]] = dxsa.operand %[[INDEX_2]] {mask = 32 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_3:.*]] = dxsa.index.imm {imm = 5 : i32} +// CHECK: %[[OPERAND_3:.*]] = dxsa.operand %[[INDEX_3]] {num_components = 4 : i32, one = 0 : i32, type = 0 : i32} +// CHECK: dxsa.instruction "check_access_fully_mapped" %[[OPERAND_2]], %[[OPERAND_3]] +// CHECK: dxsa.and r<4, >, r<4, >, r<4, > +// CHECK: dxsa.unknown +// CHECK: %[[INDEX_4:.*]] = dxsa.index.imm {imm = 4 : i32} +// CHECK: %[[OPERAND_4:.*]] = dxsa.operand %[[INDEX_4]] {mask = 32 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_5:.*]] = dxsa.index.imm {imm = 5 : i32} +// CHECK: %[[OPERAND_5:.*]] = dxsa.operand %[[INDEX_5]] {num_components = 4 : i32, one = 0 : i32, type = 0 : i32} +// CHECK: dxsa.instruction "check_access_fully_mapped" %[[OPERAND_4]], %[[OPERAND_5]] +// CHECK: dxsa.and r<4, >, r<4, >, r<4, > +// CHECK: dxsa.unknown +// CHECK: %[[INDEX_6:.*]] = dxsa.index.imm {imm = 4 : i32} +// CHECK: %[[OPERAND_6:.*]] = dxsa.operand %[[INDEX_6]] {mask = 32 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_7:.*]] = dxsa.index.imm {imm = 5 : i32} +// CHECK: %[[OPERAND_7:.*]] = dxsa.operand %[[INDEX_7]] {num_components = 4 : i32, one = 0 : i32, type = 0 : i32} +// CHECK: dxsa.instruction "check_access_fully_mapped" %[[OPERAND_6]], %[[OPERAND_7]] +// CHECK: dxsa.and r<4, >, r<4, >, r<4, > +// CHECK: dxsa.utof r<4, >, r<4, > +// CHECK: dxsa.add r<1>, r<1>, r<3> +// CHECK: dxsa.add r<1>, r<4, >, r<1> +// CHECK: dxsa.unknown +// CHECK: dxsa.unknown +// CHECK: %[[INDEX_8:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_8:.*]] = dxsa.operand %[[INDEX_8]] {mask = 16 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_9:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_9:.*]] = dxsa.operand %[[INDEX_9]] {num_components = 4 : i32, one = 0 : i32, type = 0 : i32} +// CHECK: dxsa.instruction "check_access_fully_mapped" %[[OPERAND_8]], %[[OPERAND_9]] +// CHECK: %[[INDEX_10:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_10:.*]] = dxsa.operand %[[INDEX_10]] {mask = 32 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_11:.*]] = dxsa.index.imm {imm = 4 : i32} +// CHECK: %[[OPERAND_11:.*]] = dxsa.operand %[[INDEX_11]] {num_components = 4 : i32, one = 0 : i32, type = 0 : i32} +// CHECK: dxsa.instruction "check_access_fully_mapped" %[[OPERAND_10]], %[[OPERAND_11]] +// CHECK: dxsa.and r<0, >, r<0, >, r<0, > +// CHECK: dxsa.unknown +// CHECK: dxsa.unknown +// CHECK: %[[INDEX_12:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_12:.*]] = dxsa.operand %[[INDEX_12]] {mask = 32 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_13:.*]] = dxsa.index.imm {imm = 2 : i32} +// CHECK: %[[OPERAND_13:.*]] = dxsa.operand %[[INDEX_13]] {num_components = 4 : i32, one = 0 : i32, type = 0 : i32} +// CHECK: dxsa.instruction "check_access_fully_mapped" %[[OPERAND_12]], %[[OPERAND_13]] +// CHECK: dxsa.and r<0, >, r<0, >, r<0, > +// CHECK: %[[INDEX_14:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_14:.*]] = dxsa.operand %[[INDEX_14]] {mask = 32 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_15:.*]] = dxsa.index.imm {imm = 4 : i32} +// CHECK: %[[OPERAND_15:.*]] = dxsa.operand %[[INDEX_15]] {num_components = 4 : i32, one = 0 : i32, type = 0 : i32} +// CHECK: dxsa.instruction "check_access_fully_mapped" %[[OPERAND_14]], %[[OPERAND_15]] +// CHECK: dxsa.and r<0, >, r<0, >, r<0, > +// CHECK: dxsa.utof r<0, >, r<0, > +// CHECK: dxsa.add r<1>, r<1>, r<3> +// CHECK: dxsa.add o<0>, r<0, >, r<1> +// CHECK: dxsa.instruction "ret" + diff --git a/mlir/test/Target/DXSA/hlsl/gather_po_cmp.test b/mlir/test/Target/DXSA/hlsl/gather_po_cmp.test new file mode 100644 index 000000000000..cf8f8ebaba4c --- /dev/null +++ b/mlir/test/Target/DXSA/hlsl/gather_po_cmp.test @@ -0,0 +1,87 @@ +// RUN: mlir-translate --import-dxsa-bin %S/inputs/gather_po_cmp.bin | FileCheck %s +// NOTE: Assertions have been autogenerated by utils/generate-test-checks.py + +// This script is intended to make adding checks to a test case quick and easy. +// It is *not* authoritative about what constitutes a good test. After using the +// script, be sure to review and refine the generated checks. For example, +// CHECK lines should be minimized and named to reflect the test’s intent. +// For comprehensive guidelines, see: +// * https://mlir.llvm.org/getting_started/TestingGuide/ + + +// CHECK-LABEL: dxsa.dcl_global_flags +// CHECK: dxsa.dcl_sampler +// CHECK: dxsa.dcl_resource , , +// CHECK: dxsa.dcl_resource , , +// CHECK: dxsa.dcl_input_ps linear v<0> +// CHECK: dxsa.dcl_input_ps linear v<1> +// CHECK: dxsa.dcl_output o<0> +// CHECK: dxsa.dcl_temps 6 +// CHECK: dxsa.ftoi r<0>, v<1> +// CHECK: dxsa.unknown +// CHECK: dxsa.unknown +// CHECK: dxsa.ftoi r<2>, v<0> +// CHECK: dxsa.unknown +// CHECK: dxsa.unknown +// CHECK: dxsa.unknown +// CHECK: %[[INDEX_0:.*]] = dxsa.index.imm {imm = 4 : i32} +// CHECK: %[[OPERAND_0:.*]] = dxsa.operand %[[INDEX_0]] {mask = 16 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_1:.*]] = dxsa.index.imm {imm = 4 : i32} +// CHECK: %[[OPERAND_1:.*]] = dxsa.operand %[[INDEX_1]] {num_components = 4 : i32, one = 0 : i32, type = 0 : i32} +// CHECK: dxsa.instruction "check_access_fully_mapped" %[[OPERAND_0]], %[[OPERAND_1]] +// CHECK: dxsa.unknown +// CHECK: %[[INDEX_2:.*]] = dxsa.index.imm {imm = 4 : i32} +// CHECK: %[[OPERAND_2:.*]] = dxsa.operand %[[INDEX_2]] {mask = 32 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_3:.*]] = dxsa.index.imm {imm = 5 : i32} +// CHECK: %[[OPERAND_3:.*]] = dxsa.operand %[[INDEX_3]] {num_components = 4 : i32, one = 0 : i32, type = 0 : i32} +// CHECK: dxsa.instruction "check_access_fully_mapped" %[[OPERAND_2]], %[[OPERAND_3]] +// CHECK: dxsa.and r<4, >, r<4, >, r<4, > +// CHECK: dxsa.unknown +// CHECK: %[[INDEX_4:.*]] = dxsa.index.imm {imm = 4 : i32} +// CHECK: %[[OPERAND_4:.*]] = dxsa.operand %[[INDEX_4]] {mask = 32 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_5:.*]] = dxsa.index.imm {imm = 5 : i32} +// CHECK: %[[OPERAND_5:.*]] = dxsa.operand %[[INDEX_5]] {num_components = 4 : i32, one = 0 : i32, type = 0 : i32} +// CHECK: dxsa.instruction "check_access_fully_mapped" %[[OPERAND_4]], %[[OPERAND_5]] +// CHECK: dxsa.and r<4, >, r<4, >, r<4, > +// CHECK: dxsa.unknown +// CHECK: %[[INDEX_6:.*]] = dxsa.index.imm {imm = 4 : i32} +// CHECK: %[[OPERAND_6:.*]] = dxsa.operand %[[INDEX_6]] {mask = 32 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_7:.*]] = dxsa.index.imm {imm = 5 : i32} +// CHECK: %[[OPERAND_7:.*]] = dxsa.operand %[[INDEX_7]] {num_components = 4 : i32, one = 0 : i32, type = 0 : i32} +// CHECK: dxsa.instruction "check_access_fully_mapped" %[[OPERAND_6]], %[[OPERAND_7]] +// CHECK: dxsa.and r<4, >, r<4, >, r<4, > +// CHECK: dxsa.utof r<4, >, r<4, > +// CHECK: dxsa.add r<1>, r<1>, r<3> +// CHECK: dxsa.add r<1>, r<4, >, r<1> +// CHECK: dxsa.unknown +// CHECK: dxsa.unknown +// CHECK: %[[INDEX_8:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_8:.*]] = dxsa.operand %[[INDEX_8]] {mask = 16 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_9:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_9:.*]] = dxsa.operand %[[INDEX_9]] {num_components = 4 : i32, one = 0 : i32, type = 0 : i32} +// CHECK: dxsa.instruction "check_access_fully_mapped" %[[OPERAND_8]], %[[OPERAND_9]] +// CHECK: %[[INDEX_10:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_10:.*]] = dxsa.operand %[[INDEX_10]] {mask = 32 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_11:.*]] = dxsa.index.imm {imm = 4 : i32} +// CHECK: %[[OPERAND_11:.*]] = dxsa.operand %[[INDEX_11]] {num_components = 4 : i32, one = 0 : i32, type = 0 : i32} +// CHECK: dxsa.instruction "check_access_fully_mapped" %[[OPERAND_10]], %[[OPERAND_11]] +// CHECK: dxsa.and r<0, >, r<0, >, r<0, > +// CHECK: dxsa.unknown +// CHECK: dxsa.unknown +// CHECK: %[[INDEX_12:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_12:.*]] = dxsa.operand %[[INDEX_12]] {mask = 32 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_13:.*]] = dxsa.index.imm {imm = 2 : i32} +// CHECK: %[[OPERAND_13:.*]] = dxsa.operand %[[INDEX_13]] {num_components = 4 : i32, one = 0 : i32, type = 0 : i32} +// CHECK: dxsa.instruction "check_access_fully_mapped" %[[OPERAND_12]], %[[OPERAND_13]] +// CHECK: dxsa.and r<0, >, r<0, >, r<0, > +// CHECK: %[[INDEX_14:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_14:.*]] = dxsa.operand %[[INDEX_14]] {mask = 32 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_15:.*]] = dxsa.index.imm {imm = 4 : i32} +// CHECK: %[[OPERAND_15:.*]] = dxsa.operand %[[INDEX_15]] {num_components = 4 : i32, one = 0 : i32, type = 0 : i32} +// CHECK: dxsa.instruction "check_access_fully_mapped" %[[OPERAND_14]], %[[OPERAND_15]] +// CHECK: dxsa.and r<0, >, r<0, >, r<0, > +// CHECK: dxsa.utof r<0, >, r<0, > +// CHECK: dxsa.add r<1>, r<1>, r<3> +// CHECK: dxsa.add o<0>, r<0, >, r<1> +// CHECK: dxsa.instruction "ret" + diff --git a/mlir/test/Target/DXSA/hlsl/getdim.test b/mlir/test/Target/DXSA/hlsl/getdim.test new file mode 100644 index 000000000000..94eb6adff1b3 --- /dev/null +++ b/mlir/test/Target/DXSA/hlsl/getdim.test @@ -0,0 +1,212 @@ +// RUN: mlir-translate --import-dxsa-bin %S/inputs/getdim.bin | FileCheck %s +// NOTE: Assertions have been autogenerated by utils/generate-test-checks.py + +// This script is intended to make adding checks to a test case quick and easy. +// It is *not* authoritative about what constitutes a good test. After using the +// script, be sure to review and refine the generated checks. For example, +// CHECK lines should be minimized and named to reflect the test’s intent. +// For comprehensive guidelines, see: +// * https://mlir.llvm.org/getting_started/TestingGuide/ + + +// CHECK-LABEL: dxsa.dcl_global_flags +// CHECK: dxsa.dcl_resource , , +// CHECK: dxsa.dcl_resource , , +// CHECK: dxsa.dcl_resource , , +// CHECK: dxsa.unknown +// CHECK: dxsa.dcl_uav_typed , +// CHECK: dxsa.dcl_input_ps linear v<0, > +// CHECK: dxsa.dcl_output o<0> +// CHECK: dxsa.dcl_temps 2 +// CHECK: dxsa.ftou r<0, >, v<0, > +// CHECK: dxsa.unknown +// CHECK: %[[INDEX_0:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_0:.*]] = dxsa.operand %[[INDEX_0]] {mask = 32 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_1:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_1:.*]] = dxsa.operand %[[INDEX_1]] {num_components = 4 : i32, one = 1 : i32, type = 0 : i32} +// CHECK: %[[INDEX_2:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_2:.*]] = dxsa.operand %[[INDEX_2]] {num_components = 4 : i32, one = 0 : i32, type = 0 : i32} +// CHECK: dxsa.instruction "iadd" %[[OPERAND_0]], %[[OPERAND_1]], %[[OPERAND_2]] +// CHECK: %[[INDEX_3:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_3:.*]] = dxsa.operand %[[INDEX_3]] {mask = 32 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_4:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_4:.*]] = dxsa.operand %[[INDEX_4]] {num_components = 4 : i32, one = 2 : i32, type = 0 : i32} +// CHECK: %[[INDEX_5:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_5:.*]] = dxsa.operand %[[INDEX_5]] {num_components = 4 : i32, one = 1 : i32, type = 0 : i32} +// CHECK: dxsa.instruction "iadd" %[[OPERAND_3]], %[[OPERAND_4]], %[[OPERAND_5]] +// CHECK: %[[INDEX_6:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_6:.*]] = dxsa.operand %[[INDEX_6]] {mask = 32 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_7:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_7:.*]] = dxsa.operand %[[INDEX_7]] {num_components = 4 : i32, one = 3 : i32, type = 0 : i32} +// CHECK: %[[INDEX_8:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_8:.*]] = dxsa.operand %[[INDEX_8]] {num_components = 4 : i32, one = 1 : i32, type = 0 : i32} +// CHECK: dxsa.instruction "iadd" %[[OPERAND_6]], %[[OPERAND_7]], %[[OPERAND_8]] +// CHECK: dxsa.unknown +// CHECK: %[[INDEX_9:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_9:.*]] = dxsa.operand %[[INDEX_9]] {mask = 64 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_10:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_10:.*]] = dxsa.operand %[[INDEX_10]] {num_components = 4 : i32, one = 0 : i32, type = 0 : i32} +// CHECK: %[[INDEX_11:.*]] = dxsa.index.imm {imm = 1 : i32} +// CHECK: %[[OPERAND_11:.*]] = dxsa.operand %[[INDEX_11]] {num_components = 4 : i32, one = 0 : i32, type = 0 : i32} +// CHECK: dxsa.instruction "iadd" %[[OPERAND_9]], %[[OPERAND_10]], %[[OPERAND_11]] +// CHECK: %[[INDEX_12:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_12:.*]] = dxsa.operand %[[INDEX_12]] {mask = 64 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_13:.*]] = dxsa.index.imm {imm = 1 : i32} +// CHECK: %[[OPERAND_13:.*]] = dxsa.operand %[[INDEX_13]] {num_components = 4 : i32, one = 1 : i32, type = 0 : i32} +// CHECK: %[[INDEX_14:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_14:.*]] = dxsa.operand %[[INDEX_14]] {num_components = 4 : i32, one = 2 : i32, type = 0 : i32} +// CHECK: dxsa.instruction "iadd" %[[OPERAND_12]], %[[OPERAND_13]], %[[OPERAND_14]] +// CHECK: %[[INDEX_15:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_15:.*]] = dxsa.operand %[[INDEX_15]] {mask = 64 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_16:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_16:.*]] = dxsa.operand %[[INDEX_16]] {num_components = 4 : i32, one = 3 : i32, type = 0 : i32} +// CHECK: %[[INDEX_17:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_17:.*]] = dxsa.operand %[[INDEX_17]] {num_components = 4 : i32, one = 2 : i32, type = 0 : i32} +// CHECK: dxsa.instruction "iadd" %[[OPERAND_15]], %[[OPERAND_16]], %[[OPERAND_17]] +// CHECK: dxsa.utof r<0, >, r<0, > +// CHECK: dxsa.add r<0, >, r<0, >, r<0, > +// CHECK: dxsa.unknown +// CHECK: %[[INDEX_18:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_18:.*]] = dxsa.operand %[[INDEX_18]] {mask = 64 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_19:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_19:.*]] = dxsa.operand %[[INDEX_19]] {num_components = 4 : i32, one = 0 : i32, type = 0 : i32} +// CHECK: %[[INDEX_20:.*]] = dxsa.index.imm {imm = 1 : i32} +// CHECK: %[[OPERAND_20:.*]] = dxsa.operand %[[INDEX_20]] {num_components = 4 : i32, one = 0 : i32, type = 0 : i32} +// CHECK: dxsa.instruction "iadd" %[[OPERAND_18]], %[[OPERAND_19]], %[[OPERAND_20]] +// CHECK: %[[INDEX_21:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_21:.*]] = dxsa.operand %[[INDEX_21]] {mask = 64 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_22:.*]] = dxsa.index.imm {imm = 1 : i32} +// CHECK: %[[OPERAND_22:.*]] = dxsa.operand %[[INDEX_22]] {num_components = 4 : i32, one = 1 : i32, type = 0 : i32} +// CHECK: %[[INDEX_23:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_23:.*]] = dxsa.operand %[[INDEX_23]] {num_components = 4 : i32, one = 2 : i32, type = 0 : i32} +// CHECK: dxsa.instruction "iadd" %[[OPERAND_21]], %[[OPERAND_22]], %[[OPERAND_23]] +// CHECK: %[[INDEX_24:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_24:.*]] = dxsa.operand %[[INDEX_24]] {mask = 64 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_25:.*]] = dxsa.index.imm {imm = 1 : i32} +// CHECK: %[[OPERAND_25:.*]] = dxsa.operand %[[INDEX_25]] {num_components = 4 : i32, one = 2 : i32, type = 0 : i32} +// CHECK: %[[INDEX_26:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_26:.*]] = dxsa.operand %[[INDEX_26]] {num_components = 4 : i32, one = 2 : i32, type = 0 : i32} +// CHECK: dxsa.instruction "iadd" %[[OPERAND_24]], %[[OPERAND_25]], %[[OPERAND_26]] +// CHECK: %[[INDEX_27:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_27:.*]] = dxsa.operand %[[INDEX_27]] {mask = 64 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_28:.*]] = dxsa.index.imm {imm = 1 : i32} +// CHECK: %[[OPERAND_28:.*]] = dxsa.operand %[[INDEX_28]] {num_components = 4 : i32, one = 3 : i32, type = 0 : i32} +// CHECK: %[[INDEX_29:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_29:.*]] = dxsa.operand %[[INDEX_29]] {num_components = 4 : i32, one = 2 : i32, type = 0 : i32} +// CHECK: dxsa.instruction "iadd" %[[OPERAND_27]], %[[OPERAND_28]], %[[OPERAND_29]] +// CHECK: dxsa.utof r<0, >, r<0, > +// CHECK: dxsa.add r<0, >, r<0, >, r<0, > +// CHECK: dxsa.unknown +// CHECK: %[[INDEX_30:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_30:.*]] = dxsa.operand %[[INDEX_30]] {mask = 64 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_31:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_31:.*]] = dxsa.operand %[[INDEX_31]] {num_components = 4 : i32, one = 0 : i32, type = 0 : i32} +// CHECK: %[[INDEX_32:.*]] = dxsa.index.imm {imm = 1 : i32} +// CHECK: %[[OPERAND_32:.*]] = dxsa.operand %[[INDEX_32]] {num_components = 4 : i32, one = 0 : i32, type = 0 : i32} +// CHECK: dxsa.instruction "iadd" %[[OPERAND_30]], %[[OPERAND_31]], %[[OPERAND_32]] +// CHECK: %[[INDEX_33:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_33:.*]] = dxsa.operand %[[INDEX_33]] {mask = 64 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_34:.*]] = dxsa.index.imm {imm = 1 : i32} +// CHECK: %[[OPERAND_34:.*]] = dxsa.operand %[[INDEX_34]] {num_components = 4 : i32, one = 1 : i32, type = 0 : i32} +// CHECK: %[[INDEX_35:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_35:.*]] = dxsa.operand %[[INDEX_35]] {num_components = 4 : i32, one = 2 : i32, type = 0 : i32} +// CHECK: dxsa.instruction "iadd" %[[OPERAND_33]], %[[OPERAND_34]], %[[OPERAND_35]] +// CHECK: %[[INDEX_36:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_36:.*]] = dxsa.operand %[[INDEX_36]] {mask = 64 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_37:.*]] = dxsa.index.imm {imm = 1 : i32} +// CHECK: %[[OPERAND_37:.*]] = dxsa.operand %[[INDEX_37]] {num_components = 4 : i32, one = 2 : i32, type = 0 : i32} +// CHECK: %[[INDEX_38:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_38:.*]] = dxsa.operand %[[INDEX_38]] {num_components = 4 : i32, one = 2 : i32, type = 0 : i32} +// CHECK: dxsa.instruction "iadd" %[[OPERAND_36]], %[[OPERAND_37]], %[[OPERAND_38]] +// CHECK: %[[INDEX_39:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_39:.*]] = dxsa.operand %[[INDEX_39]] {mask = 64 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_40:.*]] = dxsa.index.imm {imm = 1 : i32} +// CHECK: %[[OPERAND_40:.*]] = dxsa.operand %[[INDEX_40]] {num_components = 4 : i32, one = 3 : i32, type = 0 : i32} +// CHECK: %[[INDEX_41:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_41:.*]] = dxsa.operand %[[INDEX_41]] {num_components = 4 : i32, one = 2 : i32, type = 0 : i32} +// CHECK: dxsa.instruction "iadd" %[[OPERAND_39]], %[[OPERAND_40]], %[[OPERAND_41]] +// CHECK: dxsa.utof r<0, >, r<0, > +// CHECK: dxsa.add r<0, >, r<0, >, r<0, > +// CHECK: dxsa.unknown +// CHECK: %[[INDEX_42:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_42:.*]] = dxsa.operand %[[INDEX_42]] {mask = 64 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_43:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_43:.*]] = dxsa.operand %[[INDEX_43]] {num_components = 4 : i32, one = 0 : i32, type = 0 : i32} +// CHECK: %[[INDEX_44:.*]] = dxsa.index.imm {imm = 1 : i32} +// CHECK: %[[OPERAND_44:.*]] = dxsa.operand %[[INDEX_44]] {num_components = 4 : i32, one = 0 : i32, type = 0 : i32} +// CHECK: dxsa.instruction "iadd" %[[OPERAND_42]], %[[OPERAND_43]], %[[OPERAND_44]] +// CHECK: %[[INDEX_45:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_45:.*]] = dxsa.operand %[[INDEX_45]] {mask = 64 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_46:.*]] = dxsa.index.imm {imm = 1 : i32} +// CHECK: %[[OPERAND_46:.*]] = dxsa.operand %[[INDEX_46]] {num_components = 4 : i32, one = 1 : i32, type = 0 : i32} +// CHECK: %[[INDEX_47:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_47:.*]] = dxsa.operand %[[INDEX_47]] {num_components = 4 : i32, one = 2 : i32, type = 0 : i32} +// CHECK: dxsa.instruction "iadd" %[[OPERAND_45]], %[[OPERAND_46]], %[[OPERAND_47]] +// CHECK: %[[INDEX_48:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_48:.*]] = dxsa.operand %[[INDEX_48]] {mask = 64 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_49:.*]] = dxsa.index.imm {imm = 1 : i32} +// CHECK: %[[OPERAND_49:.*]] = dxsa.operand %[[INDEX_49]] {num_components = 4 : i32, one = 2 : i32, type = 0 : i32} +// CHECK: %[[INDEX_50:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_50:.*]] = dxsa.operand %[[INDEX_50]] {num_components = 4 : i32, one = 2 : i32, type = 0 : i32} +// CHECK: dxsa.instruction "iadd" %[[OPERAND_48]], %[[OPERAND_49]], %[[OPERAND_50]] +// CHECK: %[[INDEX_51:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_51:.*]] = dxsa.operand %[[INDEX_51]] {mask = 64 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_52:.*]] = dxsa.index.imm {imm = 1 : i32} +// CHECK: %[[OPERAND_52:.*]] = dxsa.operand %[[INDEX_52]] {num_components = 4 : i32, one = 3 : i32, type = 0 : i32} +// CHECK: %[[INDEX_53:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_53:.*]] = dxsa.operand %[[INDEX_53]] {num_components = 4 : i32, one = 2 : i32, type = 0 : i32} +// CHECK: dxsa.instruction "iadd" %[[OPERAND_51]], %[[OPERAND_52]], %[[OPERAND_53]] +// CHECK: %[[INDEX_54:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_54:.*]] = dxsa.operand %[[INDEX_54]] {mask = 128 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_55:.*]] = dxsa.index.imm {imm = 3 : i32} +// CHECK: %[[OPERAND_55:.*]] = dxsa.operand %[[INDEX_55]] {num_components = 4 : i32, one = 0 : i32, type = 7 : i32} +// CHECK: dxsa.instruction "sampleinfo" %[[OPERAND_54]], %[[OPERAND_55]] +// CHECK: %[[INDEX_56:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_56:.*]] = dxsa.operand %[[INDEX_56]] {mask = 64 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_57:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_57:.*]] = dxsa.operand %[[INDEX_57]] {num_components = 4 : i32, one = 3 : i32, type = 0 : i32} +// CHECK: %[[INDEX_58:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_58:.*]] = dxsa.operand %[[INDEX_58]] {num_components = 4 : i32, one = 2 : i32, type = 0 : i32} +// CHECK: dxsa.instruction "iadd" %[[OPERAND_56]], %[[OPERAND_57]], %[[OPERAND_58]] +// CHECK: dxsa.utof r<0, >, r<0, > +// CHECK: dxsa.add r<0, >, r<0, >, r<0, > +// CHECK: dxsa.unknown +// CHECK: %[[INDEX_59:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_59:.*]] = dxsa.operand %[[INDEX_59]] {mask = 16 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_60:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_60:.*]] = dxsa.operand %[[INDEX_60]] {num_components = 4 : i32, one = 0 : i32, type = 0 : i32} +// CHECK: %[[INDEX_61:.*]] = dxsa.index.imm {imm = 1 : i32} +// CHECK: %[[OPERAND_61:.*]] = dxsa.operand %[[INDEX_61]] {num_components = 4 : i32, one = 0 : i32, type = 0 : i32} +// CHECK: dxsa.instruction "iadd" %[[OPERAND_59]], %[[OPERAND_60]], %[[OPERAND_61]] +// CHECK: %[[INDEX_62:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_62:.*]] = dxsa.operand %[[INDEX_62]] {mask = 16 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_63:.*]] = dxsa.index.imm {imm = 1 : i32} +// CHECK: %[[OPERAND_63:.*]] = dxsa.operand %[[INDEX_63]] {num_components = 4 : i32, one = 1 : i32, type = 0 : i32} +// CHECK: %[[INDEX_64:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_64:.*]] = dxsa.operand %[[INDEX_64]] {num_components = 4 : i32, one = 0 : i32, type = 0 : i32} +// CHECK: dxsa.instruction "iadd" %[[OPERAND_62]], %[[OPERAND_63]], %[[OPERAND_64]] +// CHECK: %[[INDEX_65:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_65:.*]] = dxsa.operand %[[INDEX_65]] {mask = 16 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_66:.*]] = dxsa.index.imm {imm = 1 : i32} +// CHECK: %[[OPERAND_66:.*]] = dxsa.operand %[[INDEX_66]] {num_components = 4 : i32, one = 2 : i32, type = 0 : i32} +// CHECK: %[[INDEX_67:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_67:.*]] = dxsa.operand %[[INDEX_67]] {num_components = 4 : i32, one = 0 : i32, type = 0 : i32} +// CHECK: dxsa.instruction "iadd" %[[OPERAND_65]], %[[OPERAND_66]], %[[OPERAND_67]] +// CHECK: %[[INDEX_68:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_68:.*]] = dxsa.operand %[[INDEX_68]] {mask = 16 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_69:.*]] = dxsa.index.imm {imm = 1 : i32} +// CHECK: %[[OPERAND_69:.*]] = dxsa.operand %[[INDEX_69]] {num_components = 4 : i32, one = 3 : i32, type = 0 : i32} +// CHECK: %[[INDEX_70:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_70:.*]] = dxsa.operand %[[INDEX_70]] {num_components = 4 : i32, one = 0 : i32, type = 0 : i32} +// CHECK: dxsa.instruction "iadd" %[[OPERAND_68]], %[[OPERAND_69]], %[[OPERAND_70]] +// CHECK: %[[INDEX_71:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_71:.*]] = dxsa.operand %[[INDEX_71]] {mask = 16 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_72:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_72:.*]] = dxsa.operand %[[INDEX_72]] {num_components = 4 : i32, one = 3 : i32, type = 0 : i32} +// CHECK: %[[INDEX_73:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_73:.*]] = dxsa.operand %[[INDEX_73]] {num_components = 4 : i32, one = 0 : i32, type = 0 : i32} +// CHECK: dxsa.instruction "iadd" %[[OPERAND_71]], %[[OPERAND_72]], %[[OPERAND_73]] +// CHECK: dxsa.utof r<0, >, r<0, > +// CHECK: dxsa.add o<0>, r<0, >, r<0, > +// CHECK: dxsa.instruction "ret" + diff --git a/mlir/test/Target/DXSA/hlsl/gs1.test b/mlir/test/Target/DXSA/hlsl/gs1.test new file mode 100644 index 000000000000..df216b81912d --- /dev/null +++ b/mlir/test/Target/DXSA/hlsl/gs1.test @@ -0,0 +1,63 @@ +// RUN: mlir-translate --import-dxsa-bin %S/inputs/gs1.bin | FileCheck %s +// NOTE: Assertions have been autogenerated by utils/generate-test-checks.py + +// This script is intended to make adding checks to a test case quick and easy. +// It is *not* authoritative about what constitutes a good test. After using the +// script, be sure to review and refine the generated checks. For example, +// CHECK lines should be minimized and named to reflect the test’s intent. +// For comprehensive guidelines, see: +// * https://mlir.llvm.org/getting_started/TestingGuide/ + + +// CHECK-LABEL: dxsa.dcl_global_flags +// CHECK: dxsa.dcl_input v<[6, 0]> +// CHECK: dxsa.dcl_input v<[6, 1], > +// CHECK: dxsa.dcl_input v<[6, 2], > +// CHECK: dxsa.dcl_input v<[6, 3], > +// CHECK: dxsa.dcl_input v<[6, 4], > +// CHECK: dxsa.dcl_input_siv v<[6, 5]>, +// CHECK: dxsa.dcl_temps 1 +// CHECK: dxsa.dcl_index_range v<[6, 2], >, 3 +// CHECK: dxsa.dcl_input_primitive triangle_adj +// CHECK: dxsa.dcl_stream 0 +// CHECK: dxsa.dcl_output_topology trianglestrip +// CHECK: dxsa.dcl_output_siv o<0>, +// CHECK: dxsa.dcl_output o<1, > +// CHECK: dxsa.dcl_output_siv o<2, >, +// CHECK: dxsa.dcl_max_output_vertex_count 18 +// CHECK: dxsa.add r<0, >, v<[1, 0], >, v<[2, 1], > +// CHECK: dxsa.add r<0, >, r<0, >, v<[3, 5], > +// CHECK: dxsa.ftou r<0, >, r<0, > +// CHECK: dxsa.add r<0, >, r<0, >, v<[r<0, >, 2 + r<0, >], > +// CHECK: dxsa.ftou r<0, >, r<0, > +// CHECK: %[[INDEX_0:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_0:.*]] = dxsa.operand %[[INDEX_0]] {mask = 240 : i32, num_components = 4 : i32, type = 2 : i32} +// CHECK: %[[INDEX_1:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_1:.*]] = dxsa.operand %[[INDEX_1]] {num_components = 4 : i32, one = 0 : i32, type = 0 : i32} +// CHECK: %[[INDEX_2:.*]] = dxsa.index.rel %[[OPERAND_1]] +// CHECK: %[[INDEX_3:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_2:.*]] = dxsa.operand %[[INDEX_2]], %[[INDEX_3]] {num_components = 4 : i32, swizzle = dense<[0, 1, 2, 3]> : vector<4xi32>, type = 1 : i32} +// CHECK: dxsa.instruction "mov" %[[OPERAND_0]], %[[OPERAND_2]] +// CHECK: %[[INDEX_4:.*]] = dxsa.index.imm {imm = 1 : i32} +// CHECK: %[[OPERAND_3:.*]] = dxsa.operand %[[INDEX_4]] {mask = 48 : i32, num_components = 4 : i32, type = 2 : i32} +// CHECK: %[[INDEX_5:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_4:.*]] = dxsa.operand %[[INDEX_5]] {num_components = 4 : i32, one = 1 : i32, type = 0 : i32} +// CHECK: %[[INDEX_6:.*]] = dxsa.index.rel %[[OPERAND_4]] +// CHECK: %[[INDEX_7:.*]] = dxsa.index.imm {imm = 1 : i32} +// CHECK: %[[OPERAND_5:.*]] = dxsa.operand %[[INDEX_6]], %[[INDEX_7]] {num_components = 4 : i32, swizzle = dense<[0, 1, 0, 0]> : vector<4xi32>, type = 1 : i32} +// CHECK: dxsa.instruction "mov" %[[OPERAND_3]], %[[OPERAND_5]] +// CHECK: dxsa.add r<0, >, l(0x40400000), v<[r<0, >, 0], > +// CHECK: dxsa.ftou r<0, >, r<0, > +// CHECK: %[[INDEX_8:.*]] = dxsa.index.imm {imm = 2 : i32} +// CHECK: %[[OPERAND_6:.*]] = dxsa.operand %[[INDEX_8]] {mask = 16 : i32, num_components = 4 : i32, type = 2 : i32} +// CHECK: %[[INDEX_9:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_7:.*]] = dxsa.operand %[[INDEX_9]] {num_components = 4 : i32, one = 0 : i32, type = 0 : i32} +// CHECK: dxsa.instruction "mov" %[[OPERAND_6]], %[[OPERAND_7]] +// CHECK: %[[INDEX_10:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_8:.*]] = dxsa.operand %[[INDEX_10]] {num_components = 0 : i32, type = 16 : i32} +// CHECK: dxsa.instruction "emit_stream" %[[OPERAND_8]] +// CHECK: %[[INDEX_11:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_9:.*]] = dxsa.operand %[[INDEX_11]] {num_components = 0 : i32, type = 16 : i32} +// CHECK: dxsa.instruction "cut_stream" %[[OPERAND_9]] +// CHECK: dxsa.instruction "ret" + diff --git a/mlir/test/Target/DXSA/hlsl/gs2.test b/mlir/test/Target/DXSA/hlsl/gs2.test new file mode 100644 index 000000000000..61778bd3fe1b --- /dev/null +++ b/mlir/test/Target/DXSA/hlsl/gs2.test @@ -0,0 +1,152 @@ +// RUN: mlir-translate --import-dxsa-bin %S/inputs/gs2.bin | FileCheck %s +// NOTE: Assertions have been autogenerated by utils/generate-test-checks.py + +// This script is intended to make adding checks to a test case quick and easy. +// It is *not* authoritative about what constitutes a good test. After using the +// script, be sure to review and refine the generated checks. For example, +// CHECK lines should be minimized and named to reflect the test’s intent. +// For comprehensive guidelines, see: +// * https://mlir.llvm.org/getting_started/TestingGuide/ + + +// CHECK-LABEL: dxsa.dcl_global_flags +// CHECK: dxsa.dcl_constant_buffer , +// CHECK: dxsa.dcl_input v<[1, 0]> +// CHECK: dxsa.dcl_temps 2 +// CHECK: dxsa.dcl_input_primitive point +// CHECK: dxsa.dcl_stream 0 +// CHECK: dxsa.dcl_output_topology pointlist +// CHECK: dxsa.dcl_output_siv o<0>, +// CHECK: dxsa.dcl_output o<1, > +// CHECK: dxsa.dcl_stream 1 +// CHECK: dxsa.dcl_output_topology pointlist +// CHECK: dxsa.dcl_output o<0, > +// CHECK: dxsa.dcl_output o<1> +// CHECK: dxsa.dcl_output o<2> +// CHECK: dxsa.dcl_output o<3> +// CHECK: dxsa.dcl_output o<4, > +// CHECK: dxsa.dcl_stream 2 +// CHECK: dxsa.dcl_output_topology pointlist +// CHECK: dxsa.dcl_output_siv o<0>, +// CHECK: dxsa.dcl_output o<1, > +// CHECK: dxsa.dcl_max_output_vertex_count 12 +// CHECK: dxsa.ftou r<0, >, v<[0, 0], > +// CHECK: dxsa.mul r<1>, l(0x42300000, 0x42300000, 0x42300000, 0x42300000), v<[0, 0]> +// CHECK: %[[INDEX_0:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[INDEX_1:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_0:.*]] = dxsa.operand %[[INDEX_0]], %[[INDEX_1]] {num_components = 4 : i32, one = 0 : i32, type = 8 : i32} +// CHECK: dxsa.instruction "if" %[[OPERAND_0]] +// CHECK: %[[INDEX_2:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_1:.*]] = dxsa.operand %[[INDEX_2]] {mask = 240 : i32, num_components = 4 : i32, type = 2 : i32} +// CHECK: %[[INDEX_3:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[INDEX_4:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_2:.*]] = dxsa.operand %[[INDEX_3]], %[[INDEX_4]] {num_components = 4 : i32, swizzle = dense<[0, 1, 2, 3]> : vector<4xi32>, type = 1 : i32} +// CHECK: dxsa.instruction "mov" %[[OPERAND_1]], %[[OPERAND_2]] +// CHECK: %[[INDEX_5:.*]] = dxsa.index.imm {imm = 1 : i32} +// CHECK: %[[OPERAND_3:.*]] = dxsa.operand %[[INDEX_5]] {mask = 48 : i32, num_components = 4 : i32, type = 2 : i32} +// CHECK: %[[INDEX_6:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[INDEX_7:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_4:.*]] = dxsa.operand %[[INDEX_6]], %[[INDEX_7]] {num_components = 4 : i32, swizzle = dense<[0, 1, 0, 0]> : vector<4xi32>, type = 1 : i32} +// CHECK: dxsa.instruction "mov" %[[OPERAND_3]], %[[OPERAND_4]] +// CHECK: %[[INDEX_8:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_5:.*]] = dxsa.operand %[[INDEX_8]] {num_components = 0 : i32, type = 16 : i32} +// CHECK: dxsa.instruction "emit_stream" %[[OPERAND_5]] +// CHECK: %[[INDEX_9:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_6:.*]] = dxsa.operand %[[INDEX_9]] {num_components = 0 : i32, type = 16 : i32} +// CHECK: dxsa.instruction "cut_stream" %[[OPERAND_6]] +// CHECK: %[[INDEX_10:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_7:.*]] = dxsa.operand %[[INDEX_10]] {mask = 128 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_11:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_8:.*]] = dxsa.operand %[[INDEX_11]] {num_components = 4 : i32, one = 0 : i32, type = 0 : i32} +// CHECK: dxsa.instruction "mov" %[[OPERAND_7]], %[[OPERAND_8]] +// CHECK: dxsa.instruction "else" +// CHECK: dxsa.ftou r<0, >, v<[0, 0], > +// CHECK: %[[INDEX_12:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_9:.*]] = dxsa.operand %[[INDEX_12]] {mask = 16 : i32, num_components = 4 : i32, type = 2 : i32} +// CHECK: %[[INDEX_13:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_10:.*]] = dxsa.operand %[[INDEX_13]] {num_components = 4 : i32, one = 3 : i32, type = 0 : i32} +// CHECK: dxsa.instruction "mov" %[[OPERAND_9]], %[[OPERAND_10]] +// CHECK: %[[INDEX_14:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_11:.*]] = dxsa.operand %[[INDEX_14]] {mask = 96 : i32, num_components = 4 : i32, type = 2 : i32} +// CHECK: %[[INDEX_15:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_12:.*]] = dxsa.operand %[[INDEX_15]] {num_components = 4 : i32, swizzle = dense<[1, 1, 2, 1]> : vector<4xi32>, type = 0 : i32} +// CHECK: dxsa.instruction "mov" %[[OPERAND_11]], %[[OPERAND_12]] +// CHECK: %[[INDEX_16:.*]] = dxsa.index.imm {imm = 1 : i32} +// CHECK: %[[OPERAND_13:.*]] = dxsa.operand %[[INDEX_16]] {mask = 240 : i32, num_components = 4 : i32, type = 2 : i32} +// CHECK: %[[OPERAND_14:.*]] = dxsa.operand.imm {imm = dense<0> : vector<4xi32>} +// CHECK: dxsa.instruction "mov" %[[OPERAND_13]], %[[OPERAND_14]] +// CHECK: %[[INDEX_17:.*]] = dxsa.index.imm {imm = 2 : i32} +// CHECK: %[[OPERAND_15:.*]] = dxsa.operand %[[INDEX_17]] {mask = 240 : i32, num_components = 4 : i32, type = 2 : i32} +// CHECK: %[[OPERAND_16:.*]] = dxsa.operand.imm {imm = dense<0> : vector<4xi32>} +// CHECK: dxsa.instruction "mov" %[[OPERAND_15]], %[[OPERAND_16]] +// CHECK: %[[INDEX_18:.*]] = dxsa.index.imm {imm = 3 : i32} +// CHECK: %[[OPERAND_17:.*]] = dxsa.operand %[[INDEX_18]] {mask = 240 : i32, num_components = 4 : i32, type = 2 : i32} +// CHECK: %[[INDEX_19:.*]] = dxsa.index.imm {imm = 1 : i32} +// CHECK: %[[OPERAND_18:.*]] = dxsa.operand %[[INDEX_19]] {num_components = 4 : i32, swizzle = dense<[0, 1, 2, 3]> : vector<4xi32>, type = 0 : i32} +// CHECK: dxsa.instruction "mov" %[[OPERAND_17]], %[[OPERAND_18]] +// CHECK: %[[INDEX_20:.*]] = dxsa.index.imm {imm = 4 : i32} +// CHECK: %[[OPERAND_19:.*]] = dxsa.operand %[[INDEX_20]] {mask = 112 : i32, num_components = 4 : i32, type = 2 : i32} +// CHECK: %[[INDEX_21:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_20:.*]] = dxsa.operand %[[INDEX_21]] {num_components = 4 : i32, swizzle = dense<[0, 1, 2, 0]> : vector<4xi32>, type = 0 : i32} +// CHECK: dxsa.instruction "mov" %[[OPERAND_19]], %[[OPERAND_20]] +// CHECK: %[[INDEX_22:.*]] = dxsa.index.imm {imm = 1 : i32} +// CHECK: %[[OPERAND_21:.*]] = dxsa.operand %[[INDEX_22]] {num_components = 0 : i32, type = 16 : i32} +// CHECK: dxsa.instruction "emit_stream" %[[OPERAND_21]] +// CHECK: %[[INDEX_23:.*]] = dxsa.index.imm {imm = 1 : i32} +// CHECK: %[[OPERAND_22:.*]] = dxsa.operand %[[INDEX_23]] {num_components = 0 : i32, type = 16 : i32} +// CHECK: dxsa.instruction "cut_stream" %[[OPERAND_22]] +// CHECK: dxsa.instruction "endif" +// CHECK: %[[INDEX_24:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_23:.*]] = dxsa.operand %[[INDEX_24]] {mask = 16 : i32, num_components = 4 : i32, type = 2 : i32} +// CHECK: %[[INDEX_25:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_24:.*]] = dxsa.operand %[[INDEX_25]] {num_components = 4 : i32, one = 3 : i32, type = 0 : i32} +// CHECK: dxsa.instruction "mov" %[[OPERAND_23]], %[[OPERAND_24]] +// CHECK: %[[INDEX_26:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_25:.*]] = dxsa.operand %[[INDEX_26]] {mask = 96 : i32, num_components = 4 : i32, type = 2 : i32} +// CHECK: %[[INDEX_27:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_26:.*]] = dxsa.operand %[[INDEX_27]] {num_components = 4 : i32, swizzle = dense<[1, 1, 2, 1]> : vector<4xi32>, type = 0 : i32} +// CHECK: dxsa.instruction "mov" %[[OPERAND_25]], %[[OPERAND_26]] +// CHECK: %[[INDEX_28:.*]] = dxsa.index.imm {imm = 1 : i32} +// CHECK: %[[OPERAND_27:.*]] = dxsa.operand %[[INDEX_28]] {mask = 240 : i32, num_components = 4 : i32, type = 2 : i32} +// CHECK: %[[OPERAND_28:.*]] = dxsa.operand.imm {imm = dense<0> : vector<4xi32>} +// CHECK: dxsa.instruction "mov" %[[OPERAND_27]], %[[OPERAND_28]] +// CHECK: %[[INDEX_29:.*]] = dxsa.index.imm {imm = 2 : i32} +// CHECK: %[[OPERAND_29:.*]] = dxsa.operand %[[INDEX_29]] {mask = 240 : i32, num_components = 4 : i32, type = 2 : i32} +// CHECK: %[[OPERAND_30:.*]] = dxsa.operand.imm {imm = dense<0> : vector<4xi32>} +// CHECK: dxsa.instruction "mov" %[[OPERAND_29]], %[[OPERAND_30]] +// CHECK: %[[INDEX_30:.*]] = dxsa.index.imm {imm = 3 : i32} +// CHECK: %[[OPERAND_31:.*]] = dxsa.operand %[[INDEX_30]] {mask = 240 : i32, num_components = 4 : i32, type = 2 : i32} +// CHECK: %[[INDEX_31:.*]] = dxsa.index.imm {imm = 1 : i32} +// CHECK: %[[OPERAND_32:.*]] = dxsa.operand %[[INDEX_31]] {num_components = 4 : i32, swizzle = dense<[0, 1, 2, 3]> : vector<4xi32>, type = 0 : i32} +// CHECK: dxsa.instruction "mov" %[[OPERAND_31]], %[[OPERAND_32]] +// CHECK: %[[INDEX_32:.*]] = dxsa.index.imm {imm = 4 : i32} +// CHECK: %[[OPERAND_33:.*]] = dxsa.operand %[[INDEX_32]] {mask = 112 : i32, num_components = 4 : i32, type = 2 : i32} +// CHECK: %[[INDEX_33:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_34:.*]] = dxsa.operand %[[INDEX_33]] {num_components = 4 : i32, swizzle = dense<[0, 1, 2, 0]> : vector<4xi32>, type = 0 : i32} +// CHECK: dxsa.instruction "mov" %[[OPERAND_33]], %[[OPERAND_34]] +// CHECK: %[[INDEX_34:.*]] = dxsa.index.imm {imm = 1 : i32} +// CHECK: %[[OPERAND_35:.*]] = dxsa.operand %[[INDEX_34]] {num_components = 0 : i32, type = 16 : i32} +// CHECK: dxsa.instruction "emit_stream" %[[OPERAND_35]] +// CHECK: %[[INDEX_35:.*]] = dxsa.index.imm {imm = 1 : i32} +// CHECK: %[[OPERAND_36:.*]] = dxsa.operand %[[INDEX_35]] {num_components = 0 : i32, type = 16 : i32} +// CHECK: dxsa.instruction "cut_stream" %[[OPERAND_36]] +// CHECK: %[[INDEX_36:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_37:.*]] = dxsa.operand %[[INDEX_36]] {mask = 240 : i32, num_components = 4 : i32, type = 2 : i32} +// CHECK: %[[INDEX_37:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[INDEX_38:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_38:.*]] = dxsa.operand %[[INDEX_37]], %[[INDEX_38]] {num_components = 4 : i32, swizzle = dense<[0, 1, 2, 3]> : vector<4xi32>, type = 1 : i32} +// CHECK: dxsa.instruction "mov" %[[OPERAND_37]], %[[OPERAND_38]] +// CHECK: %[[INDEX_39:.*]] = dxsa.index.imm {imm = 1 : i32} +// CHECK: %[[OPERAND_39:.*]] = dxsa.operand %[[INDEX_39]] {mask = 48 : i32, num_components = 4 : i32, type = 2 : i32} +// CHECK: %[[INDEX_40:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[INDEX_41:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_40:.*]] = dxsa.operand %[[INDEX_40]], %[[INDEX_41]] {num_components = 4 : i32, swizzle = dense<[0, 1, 0, 0]> : vector<4xi32>, type = 1 : i32} +// CHECK: dxsa.instruction "mov" %[[OPERAND_39]], %[[OPERAND_40]] +// CHECK: %[[INDEX_42:.*]] = dxsa.index.imm {imm = 2 : i32} +// CHECK: %[[OPERAND_41:.*]] = dxsa.operand %[[INDEX_42]] {num_components = 0 : i32, type = 16 : i32} +// CHECK: dxsa.instruction "emit_stream" %[[OPERAND_41]] +// CHECK: %[[INDEX_43:.*]] = dxsa.index.imm {imm = 2 : i32} +// CHECK: %[[OPERAND_42:.*]] = dxsa.operand %[[INDEX_43]] {num_components = 0 : i32, type = 16 : i32} +// CHECK: dxsa.instruction "cut_stream" %[[OPERAND_42]] +// CHECK: dxsa.instruction "ret" + diff --git a/mlir/test/Target/DXSA/hlsl/half_rcp.test b/mlir/test/Target/DXSA/hlsl/half_rcp.test new file mode 100644 index 000000000000..2fa1e2e8acc5 --- /dev/null +++ b/mlir/test/Target/DXSA/hlsl/half_rcp.test @@ -0,0 +1,26 @@ +// RUN: mlir-translate --import-dxsa-bin %S/inputs/half_rcp.bin | FileCheck %s +// NOTE: Assertions have been autogenerated by utils/generate-test-checks.py + +// This script is intended to make adding checks to a test case quick and easy. +// It is *not* authoritative about what constitutes a good test. After using the +// script, be sure to review and refine the generated checks. For example, +// CHECK lines should be minimized and named to reflect the test’s intent. +// For comprehensive guidelines, see: +// * https://mlir.llvm.org/getting_started/TestingGuide/ + + +// CHECK-LABEL: dxsa.dcl_global_flags +// CHECK: dxsa.dcl_output o<0, > +// CHECK: dxsa.dcl_temps 1 +// CHECK: %[[INDEX_0:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_0:.*]] = dxsa.operand %[[INDEX_0]] {mask = 16 : i32, min_precision = 1 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[OPERAND_1:.*]] = dxsa.operand.imm {imm = dense<1056964608> : vector<1xi32>} +// CHECK: dxsa.instruction "mov" %[[OPERAND_0]], %[[OPERAND_1]] +// CHECK: dxsa.rcp r<0, min16f, >, r<0, min16f, > +// CHECK: %[[INDEX_1:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_2:.*]] = dxsa.operand %[[INDEX_1]] {mask = 16 : i32, num_components = 4 : i32, type = 2 : i32} +// CHECK: %[[INDEX_2:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_3:.*]] = dxsa.operand %[[INDEX_2]] {min_precision = 1 : i32, num_components = 4 : i32, one = 0 : i32, type = 0 : i32} +// CHECK: dxsa.instruction "mov" %[[OPERAND_2]], %[[OPERAND_3]] +// CHECK: dxsa.instruction "ret" + diff --git a/mlir/test/Target/DXSA/hlsl/hs1.test b/mlir/test/Target/DXSA/hlsl/hs1.test new file mode 100644 index 000000000000..16f9ce4146cf --- /dev/null +++ b/mlir/test/Target/DXSA/hlsl/hs1.test @@ -0,0 +1,143 @@ +// RUN: mlir-translate --import-dxsa-bin %S/inputs/hs1.bin | FileCheck %s +// NOTE: Assertions have been autogenerated by utils/generate-test-checks.py + +// This script is intended to make adding checks to a test case quick and easy. +// It is *not* authoritative about what constitutes a good test. After using the +// script, be sure to review and refine the generated checks. For example, +// CHECK lines should be minimized and named to reflect the test’s intent. +// For comprehensive guidelines, see: +// * https://mlir.llvm.org/getting_started/TestingGuide/ + + +// CHECK-LABEL: dxsa.instruction "hs_decls" +// CHECK: dxsa.dcl_input_control_point_count 16 +// CHECK: dxsa.dcl_output_control_point_count 16 +// CHECK: dxsa.dcl_tessellator_domain domain_quad +// CHECK: dxsa.dcl_tessellator_partitioning partitioning_fractional_odd +// CHECK: dxsa.dcl_tessellator_output_primitive output_triangle_cw +// CHECK: dxsa.dcl_global_flags +// CHECK: dxsa.dcl_constant_buffer , +// CHECK: dxsa.dcl_constant_buffer , +// CHECK: dxsa.dcl_resource , , +// CHECK: dxsa.instruction "hs_control_point_phase" +// CHECK: dxsa.dcl_input vOutputControlPointID +// CHECK: dxsa.dcl_input vPrim +// CHECK: dxsa.dcl_input v<[16, 0], > +// CHECK: dxsa.dcl_output o<0, > +// CHECK: dxsa.dcl_temps 2 +// CHECK: %[[INDEX_0:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_0:.*]] = dxsa.operand %[[INDEX_0]] {mask = 16 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[OPERAND_1:.*]] = dxsa.operand {num_components = 1 : i32, type = 11 : i32} +// CHECK: dxsa.instruction "mov" %[[OPERAND_0]], %[[OPERAND_1]] +// CHECK: dxsa.ftou r<0, >, v<[r<0, >, 0], > +// CHECK: dxsa.ftoi r<1>, v<[r<0, >, 0], > +// CHECK: %[[INDEX_1:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_2:.*]] = dxsa.operand %[[INDEX_1]] {mask = 224 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_2:.*]] = dxsa.index.imm {imm = 1 : i32} +// CHECK: %[[OPERAND_3:.*]] = dxsa.operand %[[INDEX_2]] {num_components = 4 : i32, swizzle = dense<[0, 1, 2, 3]> : vector<4xi32>, type = 0 : i32} +// CHECK: %[[INDEX_3:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[INDEX_4:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_4:.*]] = dxsa.operand %[[INDEX_4]] {num_components = 4 : i32, one = 1 : i32, type = 0 : i32} +// CHECK: %[[INDEX_5:.*]] = dxsa.index.rel.imm %[[OPERAND_4]] {imm = 20 : i32, op = "add"} +// CHECK: %[[OPERAND_5:.*]] = dxsa.operand %[[INDEX_3]], %[[INDEX_5]] {num_components = 4 : i32, swizzle = dense<[3, 0, 1, 2]> : vector<4xi32>, type = 7 : i32} +// CHECK: dxsa.instruction "ld" %[[OPERAND_2]], %[[OPERAND_3]], %[[OPERAND_5]] +// CHECK: dxsa.add r<0, >, r<0, >, v<[r<0, >, 0], > +// CHECK: dxsa.itof r<0, >, cb<[0, 0, 0], vector, > +// CHECK: dxsa.add r<0, >, r<0, >, r<0, > +// CHECK: %[[INDEX_6:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_6:.*]] = dxsa.operand %[[INDEX_6]] {mask = 128 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[OPERAND_7:.*]] = dxsa.operand {num_components = 1 : i32, type = 22 : i32} +// CHECK: dxsa.instruction "mov" %[[OPERAND_6]], %[[OPERAND_7]] +// CHECK: dxsa.add o<0, >, r<0, >, v<[r<0, >, 0], > +// CHECK: dxsa.instruction "ret" +// CHECK: dxsa.instruction "hs_fork_phase" +// CHECK: dxsa.dcl_input vPrim +// CHECK: dxsa.dcl_input vicp<[16, 0], > +// CHECK: dxsa.dcl_output_siv o<0, >, +// CHECK: dxsa.dcl_temps 1 +// CHECK: %[[INDEX_7:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_8:.*]] = dxsa.operand %[[INDEX_7]] {mask = 16 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[OPERAND_9:.*]] = dxsa.operand {num_components = 1 : i32, type = 11 : i32} +// CHECK: dxsa.instruction "mov" %[[OPERAND_8]], %[[OPERAND_9]] +// CHECK: %[[INDEX_8:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_10:.*]] = dxsa.operand %[[INDEX_8]] {mask = 16 : i32, num_components = 4 : i32, type = 2 : i32} +// CHECK: %[[INDEX_9:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_11:.*]] = dxsa.operand %[[INDEX_9]] {num_components = 4 : i32, one = 0 : i32, type = 0 : i32} +// CHECK: %[[INDEX_10:.*]] = dxsa.index.rel %[[OPERAND_11]] +// CHECK: %[[INDEX_11:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_12:.*]] = dxsa.operand %[[INDEX_10]], %[[INDEX_11]] {num_components = 4 : i32, one = 0 : i32, type = 25 : i32} +// CHECK: dxsa.instruction "mov" %[[OPERAND_10]], %[[OPERAND_12]] +// CHECK: dxsa.instruction "ret" +// CHECK: dxsa.instruction "hs_fork_phase" +// CHECK: dxsa.dcl_input vPrim +// CHECK: dxsa.dcl_input vicp<[16, 0], > +// CHECK: dxsa.dcl_output_siv o<1, >, +// CHECK: dxsa.dcl_temps 1 +// CHECK: %[[INDEX_12:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_13:.*]] = dxsa.operand %[[INDEX_12]] {mask = 16 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[OPERAND_14:.*]] = dxsa.operand {num_components = 1 : i32, type = 11 : i32} +// CHECK: dxsa.instruction "mov" %[[OPERAND_13]], %[[OPERAND_14]] +// CHECK: %[[INDEX_13:.*]] = dxsa.index.imm {imm = 1 : i32} +// CHECK: %[[OPERAND_15:.*]] = dxsa.operand %[[INDEX_13]] {mask = 16 : i32, num_components = 4 : i32, type = 2 : i32} +// CHECK: %[[INDEX_14:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_16:.*]] = dxsa.operand %[[INDEX_14]] {num_components = 4 : i32, one = 0 : i32, type = 0 : i32} +// CHECK: %[[INDEX_15:.*]] = dxsa.index.rel %[[OPERAND_16]] +// CHECK: %[[INDEX_16:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_17:.*]] = dxsa.operand %[[INDEX_15]], %[[INDEX_16]] {num_components = 4 : i32, one = 1 : i32, type = 25 : i32} +// CHECK: dxsa.instruction "mov" %[[OPERAND_15]], %[[OPERAND_17]] +// CHECK: dxsa.instruction "ret" +// CHECK: dxsa.instruction "hs_fork_phase" +// CHECK: dxsa.dcl_input vPrim +// CHECK: dxsa.dcl_input vicp<[16, 0], > +// CHECK: dxsa.dcl_output_siv o<2, >, +// CHECK: dxsa.dcl_temps 1 +// CHECK: %[[INDEX_17:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_18:.*]] = dxsa.operand %[[INDEX_17]] {mask = 16 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[OPERAND_19:.*]] = dxsa.operand {num_components = 1 : i32, type = 11 : i32} +// CHECK: dxsa.instruction "mov" %[[OPERAND_18]], %[[OPERAND_19]] +// CHECK: %[[INDEX_18:.*]] = dxsa.index.imm {imm = 2 : i32} +// CHECK: %[[OPERAND_20:.*]] = dxsa.operand %[[INDEX_18]] {mask = 16 : i32, num_components = 4 : i32, type = 2 : i32} +// CHECK: %[[INDEX_19:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_21:.*]] = dxsa.operand %[[INDEX_19]] {num_components = 4 : i32, one = 0 : i32, type = 0 : i32} +// CHECK: %[[INDEX_20:.*]] = dxsa.index.rel %[[OPERAND_21]] +// CHECK: %[[INDEX_21:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_22:.*]] = dxsa.operand %[[INDEX_20]], %[[INDEX_21]] {num_components = 4 : i32, one = 2 : i32, type = 25 : i32} +// CHECK: dxsa.instruction "mov" %[[OPERAND_20]], %[[OPERAND_22]] +// CHECK: dxsa.instruction "ret" +// CHECK: dxsa.instruction "hs_fork_phase" +// CHECK: dxsa.dcl_output_siv o<3, >, +// CHECK: %[[INDEX_22:.*]] = dxsa.index.imm {imm = 3 : i32} +// CHECK: %[[OPERAND_23:.*]] = dxsa.operand %[[INDEX_22]] {mask = 16 : i32, num_components = 4 : i32, type = 2 : i32} +// CHECK: %[[OPERAND_24:.*]] = dxsa.operand.imm {imm = dense<0> : vector<1xi32>} +// CHECK: dxsa.instruction "mov" %[[OPERAND_23]], %[[OPERAND_24]] +// CHECK: dxsa.instruction "ret" +// CHECK: dxsa.instruction "hs_fork_phase" +// CHECK: dxsa.dcl_input vPrim +// CHECK: dxsa.dcl_input vicp<[16, 0], > +// CHECK: dxsa.dcl_output_siv o<4, >, +// CHECK: dxsa.dcl_temps 1 +// CHECK: %[[INDEX_23:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_25:.*]] = dxsa.operand %[[INDEX_23]] {mask = 16 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[OPERAND_26:.*]] = dxsa.operand {num_components = 1 : i32, type = 11 : i32} +// CHECK: dxsa.instruction "mov" %[[OPERAND_25]], %[[OPERAND_26]] +// CHECK: %[[INDEX_24:.*]] = dxsa.index.imm {imm = 4 : i32} +// CHECK: %[[OPERAND_27:.*]] = dxsa.operand %[[INDEX_24]] {mask = 16 : i32, num_components = 4 : i32, type = 2 : i32} +// CHECK: %[[INDEX_25:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_28:.*]] = dxsa.operand %[[INDEX_25]] {num_components = 4 : i32, one = 0 : i32, type = 0 : i32} +// CHECK: %[[INDEX_26:.*]] = dxsa.index.rel %[[OPERAND_28]] +// CHECK: %[[INDEX_27:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_29:.*]] = dxsa.operand %[[INDEX_26]], %[[INDEX_27]] {num_components = 4 : i32, one = 2 : i32, type = 25 : i32} +// CHECK: dxsa.instruction "mov" %[[OPERAND_27]], %[[OPERAND_29]] +// CHECK: dxsa.instruction "ret" +// CHECK: dxsa.instruction "hs_fork_phase" +// CHECK: dxsa.dcl_input vPrim +// CHECK: dxsa.dcl_input vicp<[16, 0], > +// CHECK: dxsa.dcl_output_siv o<5, >, +// CHECK: dxsa.dcl_temps 1 +// CHECK: %[[INDEX_28:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_30:.*]] = dxsa.operand %[[INDEX_28]] {mask = 16 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[OPERAND_31:.*]] = dxsa.operand {num_components = 1 : i32, type = 11 : i32} +// CHECK: dxsa.instruction "mov" %[[OPERAND_30]], %[[OPERAND_31]] +// CHECK: dxsa.add o<5, >, cb<[1, 2, 14], vector, >, vicp<[r<0, >, 0], > +// CHECK: dxsa.instruction "ret" + diff --git a/mlir/test/Target/DXSA/hlsl/hs2.test b/mlir/test/Target/DXSA/hlsl/hs2.test new file mode 100644 index 000000000000..212606437424 --- /dev/null +++ b/mlir/test/Target/DXSA/hlsl/hs2.test @@ -0,0 +1,132 @@ +// RUN: mlir-translate --import-dxsa-bin %S/inputs/hs2.bin | FileCheck %s +// NOTE: Assertions have been autogenerated by utils/generate-test-checks.py + +// This script is intended to make adding checks to a test case quick and easy. +// It is *not* authoritative about what constitutes a good test. After using the +// script, be sure to review and refine the generated checks. For example, +// CHECK lines should be minimized and named to reflect the test’s intent. +// For comprehensive guidelines, see: +// * https://mlir.llvm.org/getting_started/TestingGuide/ + + +// CHECK-LABEL: dxsa.instruction "hs_decls" +// CHECK: dxsa.dcl_input_control_point_count 32 +// CHECK: dxsa.dcl_output_control_point_count 16 +// CHECK: dxsa.dcl_tessellator_domain domain_quad +// CHECK: dxsa.dcl_tessellator_partitioning partitioning_fractional_odd +// CHECK: dxsa.dcl_tessellator_output_primitive output_triangle_cw +// CHECK: dxsa.dcl_hs_max_tessfactor 3.000000e+00 +// CHECK: dxsa.dcl_global_flags +// CHECK: dxsa.instruction "hs_control_point_phase" +// CHECK: dxsa.dcl_input vOutputControlPointID +// CHECK: dxsa.dcl_input vPrim +// CHECK: dxsa.dcl_input v<[32, 0]> +// CHECK: dxsa.dcl_output o<0> +// CHECK: dxsa.dcl_temps 1 +// CHECK: %[[INDEX_0:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_0:.*]] = dxsa.operand %[[INDEX_0]] {mask = 16 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[OPERAND_1:.*]] = dxsa.operand {num_components = 1 : i32, type = 22 : i32} +// CHECK: dxsa.instruction "mov" %[[OPERAND_0]], %[[OPERAND_1]] +// CHECK: %[[INDEX_1:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_2:.*]] = dxsa.operand %[[INDEX_1]] {mask = 32 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[OPERAND_3:.*]] = dxsa.operand {num_components = 1 : i32, type = 11 : i32} +// CHECK: dxsa.instruction "mov" %[[OPERAND_2]], %[[OPERAND_3]] +// CHECK: dxsa.add o<0>, v<[r<0, >, 0]>, v<[r<0, >, 0]> +// CHECK: dxsa.instruction "ret" +// CHECK: dxsa.instruction "hs_fork_phase" +// CHECK: dxsa.dcl_hs_fork_phase_instance_count 4 +// CHECK: dxsa.dcl_input vPrim +// CHECK: dxsa.dcl_input vForkInstanceID +// CHECK: dxsa.dcl_input vicp<[32, 0], > +// CHECK: dxsa.dcl_output_siv o<0, >, +// CHECK: dxsa.dcl_output_siv o<1, >, +// CHECK: dxsa.dcl_output_siv o<2, >, +// CHECK: dxsa.dcl_output_siv o<3, >, +// CHECK: dxsa.dcl_temps 1 +// CHECK: dxsa.dcl_index_range o<0, >, 4 +// CHECK: %[[INDEX_2:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_4:.*]] = dxsa.operand %[[INDEX_2]] {mask = 16 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[OPERAND_5:.*]] = dxsa.operand {num_components = 1 : i32, type = 11 : i32} +// CHECK: dxsa.instruction "mov" %[[OPERAND_4]], %[[OPERAND_5]] +// CHECK: dxsa.min r<0, >, l(0x40400000), vicp<[r<0, >, 0], > +// CHECK: %[[INDEX_3:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_6:.*]] = dxsa.operand %[[INDEX_3]] {mask = 32 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[OPERAND_7:.*]] = dxsa.operand {num_components = 4 : i32, one = 0 : i32, type = 23 : i32} +// CHECK: dxsa.instruction "mov" %[[OPERAND_6]], %[[OPERAND_7]] +// CHECK: %[[INDEX_4:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_8:.*]] = dxsa.operand %[[INDEX_4]] {num_components = 4 : i32, one = 1 : i32, type = 0 : i32} +// CHECK: %[[INDEX_5:.*]] = dxsa.index.rel %[[OPERAND_8]] +// CHECK: %[[OPERAND_9:.*]] = dxsa.operand %[[INDEX_5]] {mask = 16 : i32, num_components = 4 : i32, type = 2 : i32} +// CHECK: %[[INDEX_6:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_10:.*]] = dxsa.operand %[[INDEX_6]] {num_components = 4 : i32, one = 0 : i32, type = 0 : i32} +// CHECK: dxsa.instruction "mov" %[[OPERAND_9]], %[[OPERAND_10]] +// CHECK: dxsa.instruction "ret" +// CHECK: dxsa.instruction "hs_fork_phase" +// CHECK: dxsa.dcl_input vPrim +// CHECK: dxsa.dcl_input vicp<[32, 0], > +// CHECK: dxsa.dcl_input vocp<[16, 0], > +// CHECK: dxsa.dcl_output o<6> +// CHECK: dxsa.dcl_temps 3 +// CHECK: %[[INDEX_7:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_11:.*]] = dxsa.operand %[[INDEX_7]] {mask = 240 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[OPERAND_12:.*]] = dxsa.operand.imm {imm = dense<0> : vector<4xi32>} +// CHECK: dxsa.instruction "mov" %[[OPERAND_11]], %[[OPERAND_12]] +// CHECK: %[[INDEX_8:.*]] = dxsa.index.imm {imm = 1 : i32} +// CHECK: %[[OPERAND_13:.*]] = dxsa.operand %[[INDEX_8]] {mask = 16 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[OPERAND_14:.*]] = dxsa.operand.imm {imm = dense<0> : vector<1xi32>} +// CHECK: dxsa.instruction "mov" %[[OPERAND_13]], %[[OPERAND_14]] +// CHECK: dxsa.instruction "loop" +// CHECK: dxsa.ige r<1, >, r<1, >, l(0x20) +// CHECK: %[[INDEX_9:.*]] = dxsa.index.imm {imm = 1 : i32} +// CHECK: %[[OPERAND_15:.*]] = dxsa.operand %[[INDEX_9]] {num_components = 4 : i32, one = 1 : i32, type = 0 : i32} +// CHECK: dxsa.instruction "breakc" %[[OPERAND_15]] +// CHECK: %[[INDEX_10:.*]] = dxsa.index.imm {imm = 1 : i32} +// CHECK: %[[OPERAND_16:.*]] = dxsa.operand %[[INDEX_10]] {mask = 32 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[OPERAND_17:.*]] = dxsa.operand {num_components = 1 : i32, type = 11 : i32} +// CHECK: dxsa.instruction "mov" %[[OPERAND_16]], %[[OPERAND_17]] +// CHECK: dxsa.mad r<1, >, vicp<[r<1, >, 0], >, vicp<[r<1, >, 0], >, vicp<[r<1, >, 0], > +// CHECK: dxsa.add r<2>, r<1, >, r<0> +// CHECK: dxsa.ushr r<1, >, r<1, >, l(0x1) +// CHECK: dxsa.add r<0>, r<2>, vocp<[r<1, >, 0], > +// CHECK: %[[INDEX_11:.*]] = dxsa.index.imm {imm = 1 : i32} +// CHECK: %[[OPERAND_18:.*]] = dxsa.operand %[[INDEX_11]] {mask = 16 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_12:.*]] = dxsa.index.imm {imm = 1 : i32} +// CHECK: %[[OPERAND_19:.*]] = dxsa.operand %[[INDEX_12]] {num_components = 4 : i32, one = 0 : i32, type = 0 : i32} +// CHECK: %[[OPERAND_20:.*]] = dxsa.operand.imm {imm = dense<1> : vector<1xi32>} +// CHECK: dxsa.instruction "iadd" %[[OPERAND_18]], %[[OPERAND_19]], %[[OPERAND_20]] +// CHECK: dxsa.instruction "endloop" +// CHECK: %[[INDEX_13:.*]] = dxsa.index.imm {imm = 6 : i32} +// CHECK: %[[OPERAND_21:.*]] = dxsa.operand %[[INDEX_13]] {mask = 240 : i32, num_components = 4 : i32, type = 2 : i32} +// CHECK: %[[INDEX_14:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_22:.*]] = dxsa.operand %[[INDEX_14]] {num_components = 4 : i32, swizzle = dense<[0, 1, 2, 3]> : vector<4xi32>, type = 0 : i32} +// CHECK: dxsa.instruction "mov" %[[OPERAND_21]], %[[OPERAND_22]] +// CHECK: dxsa.instruction "ret" +// CHECK: dxsa.instruction "hs_join_phase" +// CHECK: dxsa.dcl_hs_join_phase_instance_count 2 +// CHECK: dxsa.dcl_input vpc<6, > +// CHECK: dxsa.dcl_input vPrim +// CHECK: dxsa.dcl_input vJoinInstanceID +// CHECK: dxsa.dcl_input vicp<[32, 0], > +// CHECK: dxsa.dcl_output_siv o<4, >, +// CHECK: dxsa.dcl_output_siv o<5, >, +// CHECK: dxsa.dcl_temps 1 +// CHECK: dxsa.dcl_index_range o<4, >, 2 +// CHECK: %[[INDEX_15:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_23:.*]] = dxsa.operand %[[INDEX_15]] {mask = 16 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[OPERAND_24:.*]] = dxsa.operand {num_components = 1 : i32, type = 11 : i32} +// CHECK: dxsa.instruction "mov" %[[OPERAND_23]], %[[OPERAND_24]] +// CHECK: dxsa.add r<0, >, vicp<[r<0, >, 0], >, vpc<6, > +// CHECK: dxsa.min r<0, >, r<0, >, l(0x40400000) +// CHECK: %[[INDEX_16:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_25:.*]] = dxsa.operand %[[INDEX_16]] {mask = 32 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[OPERAND_26:.*]] = dxsa.operand {num_components = 4 : i32, one = 0 : i32, type = 24 : i32} +// CHECK: dxsa.instruction "mov" %[[OPERAND_25]], %[[OPERAND_26]] +// CHECK: %[[INDEX_17:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_27:.*]] = dxsa.operand %[[INDEX_17]] {num_components = 4 : i32, one = 1 : i32, type = 0 : i32} +// CHECK: %[[INDEX_18:.*]] = dxsa.index.rel.imm %[[OPERAND_27]] {imm = 4 : i32, op = "add"} +// CHECK: %[[OPERAND_28:.*]] = dxsa.operand %[[INDEX_18]] {mask = 16 : i32, num_components = 4 : i32, type = 2 : i32} +// CHECK: %[[INDEX_19:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_29:.*]] = dxsa.operand %[[INDEX_19]] {num_components = 4 : i32, one = 0 : i32, type = 0 : i32} +// CHECK: dxsa.instruction "mov" %[[OPERAND_28]], %[[OPERAND_29]] +// CHECK: dxsa.instruction "ret" + diff --git a/mlir/test/Target/DXSA/hlsl/icb1.test b/mlir/test/Target/DXSA/hlsl/icb1.test new file mode 100644 index 000000000000..151b2500c7f0 --- /dev/null +++ b/mlir/test/Target/DXSA/hlsl/icb1.test @@ -0,0 +1,32 @@ +// RUN: mlir-translate --import-dxsa-bin %S/inputs/icb1.bin | FileCheck %s +// NOTE: Assertions have been autogenerated by utils/generate-test-checks.py + +// This script is intended to make adding checks to a test case quick and easy. +// It is *not* authoritative about what constitutes a good test. After using the +// script, be sure to review and refine the generated checks. For example, +// CHECK lines should be minimized and named to reflect the test’s intent. +// For comprehensive guidelines, see: +// * https://mlir.llvm.org/getting_started/TestingGuide/ + + +// CHECK-LABEL: dxsa.dcl_global_flags +// CHECK: dxsa.unknown +// CHECK: dxsa.dcl_input_ps linear v<0> +// CHECK: dxsa.dcl_input_ps linear v<1> +// CHECK: dxsa.dcl_input_ps linear v<2> +// CHECK: dxsa.dcl_input_ps linear v<3> +// CHECK: dxsa.dcl_input_ps constant v<4, > +// CHECK: dxsa.dcl_output o<0, > +// CHECK: dxsa.dcl_temps 2 +// CHECK: %[[INDEX_0:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_0:.*]] = dxsa.operand %[[INDEX_0]] {mask = 48 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_1:.*]] = dxsa.index.imm {imm = 4 : i32} +// CHECK: %[[OPERAND_1:.*]] = dxsa.operand %[[INDEX_1]] {num_components = 4 : i32, swizzle = dense<[1, 0, 1, 1]> : vector<4xi32>, type = 1 : i32} +// CHECK: dxsa.instruction "mov" %[[OPERAND_0]], %[[OPERAND_1]] +// CHECK: dxsa.dp4 r<1, >, v<0>, icb>, vector> +// CHECK: dxsa.dp4 r<1, >, v<1>, icb>, vector> +// CHECK: dxsa.dp4 r<1, >, v<2>, icb>, vector> +// CHECK: dxsa.dp4 r<1, >, v<3>, icb>, vector> +// CHECK: dxsa.dp4 o<0, >, r<1>, icb>, vector> +// CHECK: dxsa.instruction "ret" + diff --git a/mlir/test/Target/DXSA/hlsl/if1.test b/mlir/test/Target/DXSA/hlsl/if1.test new file mode 100644 index 000000000000..c77a4d27551f --- /dev/null +++ b/mlir/test/Target/DXSA/hlsl/if1.test @@ -0,0 +1,36 @@ +// RUN: mlir-translate --import-dxsa-bin %S/inputs/if1.bin | FileCheck %s +// NOTE: Assertions have been autogenerated by utils/generate-test-checks.py + +// This script is intended to make adding checks to a test case quick and easy. +// It is *not* authoritative about what constitutes a good test. After using the +// script, be sure to review and refine the generated checks. For example, +// CHECK lines should be minimized and named to reflect the test’s intent. +// For comprehensive guidelines, see: +// * https://mlir.llvm.org/getting_started/TestingGuide/ + + +// CHECK-LABEL: dxsa.dcl_global_flags +// CHECK: dxsa.dcl_input_ps linear v<0, > +// CHECK: dxsa.dcl_input_ps constant v<1, > +// CHECK: dxsa.dcl_output o<0, > +// CHECK: dxsa.dcl_temps 1 +// CHECK: dxsa.ieq r<0, >, v<1, >, l(0x1) +// CHECK: %[[INDEX_0:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_0:.*]] = dxsa.operand %[[INDEX_0]] {num_components = 4 : i32, one = 0 : i32, type = 0 : i32} +// CHECK: dxsa.instruction "if" %[[OPERAND_0]] +// CHECK: %[[INDEX_1:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_1:.*]] = dxsa.operand %[[INDEX_1]] {mask = 16 : i32, num_components = 4 : i32, type = 2 : i32} +// CHECK: %[[INDEX_2:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_2:.*]] = dxsa.operand %[[INDEX_2]] {num_components = 4 : i32, one = 0 : i32, type = 1 : i32} +// CHECK: dxsa.instruction "mov" %[[OPERAND_1]], %[[OPERAND_2]] +// CHECK: dxsa.instruction "ret" +// CHECK: dxsa.instruction "else" +// CHECK: %[[INDEX_3:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_3:.*]] = dxsa.operand %[[INDEX_3]] {mask = 16 : i32, num_components = 4 : i32, type = 2 : i32} +// CHECK: %[[INDEX_4:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_4:.*]] = dxsa.operand %[[INDEX_4]] {num_components = 4 : i32, one = 1 : i32, type = 1 : i32} +// CHECK: dxsa.instruction "mov" %[[OPERAND_3]], %[[OPERAND_4]] +// CHECK: dxsa.instruction "ret" +// CHECK: dxsa.instruction "endif" +// CHECK: dxsa.instruction "ret" + diff --git a/mlir/test/Target/DXSA/hlsl/if2.test b/mlir/test/Target/DXSA/hlsl/if2.test new file mode 100644 index 000000000000..f95c7240db04 --- /dev/null +++ b/mlir/test/Target/DXSA/hlsl/if2.test @@ -0,0 +1,34 @@ +// RUN: mlir-translate --import-dxsa-bin %S/inputs/if2.bin | FileCheck %s +// NOTE: Assertions have been autogenerated by utils/generate-test-checks.py + +// This script is intended to make adding checks to a test case quick and easy. +// It is *not* authoritative about what constitutes a good test. After using the +// script, be sure to review and refine the generated checks. For example, +// CHECK lines should be minimized and named to reflect the test’s intent. +// For comprehensive guidelines, see: +// * https://mlir.llvm.org/getting_started/TestingGuide/ + + +// CHECK-LABEL: dxsa.dcl_global_flags +// CHECK: dxsa.dcl_input_ps linear v<0, > +// CHECK: dxsa.dcl_input_ps constant v<1, > +// CHECK: dxsa.dcl_output o<0, > +// CHECK: dxsa.dcl_temps 1 +// CHECK: dxsa.ieq r<0, >, v<1, >, l(0x1) +// CHECK: %[[INDEX_0:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_0:.*]] = dxsa.operand %[[INDEX_0]] {num_components = 4 : i32, one = 0 : i32, type = 0 : i32} +// CHECK: dxsa.instruction "if" %[[OPERAND_0]] +// CHECK: %[[INDEX_1:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_1:.*]] = dxsa.operand %[[INDEX_1]] {mask = 16 : i32, num_components = 4 : i32, type = 2 : i32} +// CHECK: %[[INDEX_2:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_2:.*]] = dxsa.operand %[[INDEX_2]] {num_components = 4 : i32, one = 0 : i32, type = 1 : i32} +// CHECK: dxsa.instruction "mov" %[[OPERAND_1]], %[[OPERAND_2]] +// CHECK: dxsa.instruction "ret" +// CHECK: dxsa.instruction "endif" +// CHECK: %[[INDEX_3:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_3:.*]] = dxsa.operand %[[INDEX_3]] {mask = 16 : i32, num_components = 4 : i32, type = 2 : i32} +// CHECK: %[[INDEX_4:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_4:.*]] = dxsa.operand %[[INDEX_4]] {num_components = 4 : i32, one = 1 : i32, type = 1 : i32} +// CHECK: dxsa.instruction "mov" %[[OPERAND_3]], %[[OPERAND_4]] +// CHECK: dxsa.instruction "ret" + diff --git a/mlir/test/Target/DXSA/hlsl/if3.test b/mlir/test/Target/DXSA/hlsl/if3.test new file mode 100644 index 000000000000..79ffd4407de9 --- /dev/null +++ b/mlir/test/Target/DXSA/hlsl/if3.test @@ -0,0 +1,26 @@ +// RUN: mlir-translate --import-dxsa-bin %S/inputs/if3.bin | FileCheck %s +// NOTE: Assertions have been autogenerated by utils/generate-test-checks.py + +// This script is intended to make adding checks to a test case quick and easy. +// It is *not* authoritative about what constitutes a good test. After using the +// script, be sure to review and refine the generated checks. For example, +// CHECK lines should be minimized and named to reflect the test’s intent. +// For comprehensive guidelines, see: +// * https://mlir.llvm.org/getting_started/TestingGuide/ + + +// CHECK-LABEL: dxsa.dcl_global_flags +// CHECK: dxsa.dcl_input_ps linear v<0, > +// CHECK: dxsa.dcl_input_ps constant v<1, > +// CHECK: dxsa.dcl_output o<0, > +// CHECK: dxsa.dcl_temps 1 +// CHECK: dxsa.ieq r<0, >, v<1, >, l(0x1) +// CHECK: %[[INDEX_0:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_0:.*]] = dxsa.operand %[[INDEX_0]] {num_components = 4 : i32, one = 0 : i32, type = 0 : i32} +// CHECK: dxsa.instruction "if" %[[OPERAND_0]] +// CHECK: dxsa.add o<0, >, v<0, >, l(0x40A00000) +// CHECK: dxsa.instruction "else" +// CHECK: dxsa.add o<0, >, v<0, >, l(0xC29A0000) +// CHECK: dxsa.instruction "endif" +// CHECK: dxsa.instruction "ret" + diff --git a/mlir/test/Target/DXSA/hlsl/if4.test b/mlir/test/Target/DXSA/hlsl/if4.test new file mode 100644 index 000000000000..1d7c76c27b57 --- /dev/null +++ b/mlir/test/Target/DXSA/hlsl/if4.test @@ -0,0 +1,32 @@ +// RUN: mlir-translate --import-dxsa-bin %S/inputs/if4.bin | FileCheck %s +// NOTE: Assertions have been autogenerated by utils/generate-test-checks.py + +// This script is intended to make adding checks to a test case quick and easy. +// It is *not* authoritative about what constitutes a good test. After using the +// script, be sure to review and refine the generated checks. For example, +// CHECK lines should be minimized and named to reflect the test’s intent. +// For comprehensive guidelines, see: +// * https://mlir.llvm.org/getting_started/TestingGuide/ + + +// CHECK-LABEL: dxsa.dcl_global_flags +// CHECK: dxsa.dcl_input_ps linear v<0, > +// CHECK: dxsa.dcl_input_ps constant v<1, > +// CHECK: dxsa.dcl_output o<0, > +// CHECK: dxsa.dcl_temps 1 +// CHECK: dxsa.ieq r<0, >, v<1, >, l(0x1) +// CHECK: %[[INDEX_0:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_0:.*]] = dxsa.operand %[[INDEX_0]] {num_components = 4 : i32, one = 0 : i32, type = 0 : i32} +// CHECK: dxsa.instruction "if" %[[OPERAND_0]] +// CHECK: %[[INDEX_1:.*]] = dxsa.index.imm {imm = 1 : i32} +// CHECK: %[[OPERAND_1:.*]] = dxsa.operand %[[INDEX_1]] {num_components = 4 : i32, one = 1 : i32, type = 1 : i32} +// CHECK: dxsa.instruction "if" %[[OPERAND_1]] +// CHECK: dxsa.add o<0, >, v<0, >, l(0x40A00000) +// CHECK: dxsa.instruction "else" +// CHECK: dxsa.add o<0, >, v<0, >, l(0xC0000000) +// CHECK: dxsa.instruction "endif" +// CHECK: dxsa.instruction "else" +// CHECK: dxsa.add o<0, >, v<0, >, l(0xC29A0000) +// CHECK: dxsa.instruction "endif" +// CHECK: dxsa.instruction "ret" + diff --git a/mlir/test/Target/DXSA/hlsl/if5.test b/mlir/test/Target/DXSA/hlsl/if5.test new file mode 100644 index 000000000000..c033e9faee14 --- /dev/null +++ b/mlir/test/Target/DXSA/hlsl/if5.test @@ -0,0 +1,36 @@ +// RUN: mlir-translate --import-dxsa-bin %S/inputs/if5.bin | FileCheck %s +// NOTE: Assertions have been autogenerated by utils/generate-test-checks.py + +// This script is intended to make adding checks to a test case quick and easy. +// It is *not* authoritative about what constitutes a good test. After using the +// script, be sure to review and refine the generated checks. For example, +// CHECK lines should be minimized and named to reflect the test’s intent. +// For comprehensive guidelines, see: +// * https://mlir.llvm.org/getting_started/TestingGuide/ + + +// CHECK-LABEL: dxsa.dcl_global_flags +// CHECK: dxsa.dcl_input_ps linear v<0, > +// CHECK: dxsa.dcl_input_ps constant v<1, > +// CHECK: dxsa.dcl_output o<0, > +// CHECK: dxsa.dcl_temps 1 +// CHECK: dxsa.ieq r<0, >, v<1, >, l(0x1) +// CHECK: %[[INDEX_0:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_0:.*]] = dxsa.operand %[[INDEX_0]] {num_components = 4 : i32, one = 0 : i32, type = 0 : i32} +// CHECK: dxsa.instruction "if" %[[OPERAND_0]] +// CHECK: %[[INDEX_1:.*]] = dxsa.index.imm {imm = 1 : i32} +// CHECK: %[[OPERAND_1:.*]] = dxsa.operand %[[INDEX_1]] {num_components = 4 : i32, one = 1 : i32, type = 1 : i32} +// CHECK: dxsa.instruction "if" %[[OPERAND_1]] +// CHECK: dxsa.add o<0, >, v<0, >, l(0x40A00000) +// CHECK: dxsa.instruction "else" +// CHECK: dxsa.add o<0, >, v<0, >, l(0xC0000000) +// CHECK: dxsa.instruction "endif" +// CHECK: dxsa.instruction "else" +// CHECK: %[[INDEX_2:.*]] = dxsa.index.imm {imm = 1 : i32} +// CHECK: %[[OPERAND_2:.*]] = dxsa.operand %[[INDEX_2]] {num_components = 4 : i32, one = 2 : i32, type = 1 : i32} +// CHECK: dxsa.instruction "if" %[[OPERAND_2]] +// CHECK: dxsa.add o<0, >, v<0, >, l(0xC29A0000) +// CHECK: dxsa.instruction "endif" +// CHECK: dxsa.instruction "endif" +// CHECK: dxsa.instruction "ret" + diff --git a/mlir/test/Target/DXSA/hlsl/indexableinput1.test b/mlir/test/Target/DXSA/hlsl/indexableinput1.test new file mode 100644 index 000000000000..91e226c53fc8 --- /dev/null +++ b/mlir/test/Target/DXSA/hlsl/indexableinput1.test @@ -0,0 +1,31 @@ +// RUN: mlir-translate --import-dxsa-bin %S/inputs/indexableinput1.bin | FileCheck %s +// NOTE: Assertions have been autogenerated by utils/generate-test-checks.py + +// This script is intended to make adding checks to a test case quick and easy. +// It is *not* authoritative about what constitutes a good test. After using the +// script, be sure to review and refine the generated checks. For example, +// CHECK lines should be minimized and named to reflect the test’s intent. +// For comprehensive guidelines, see: +// * https://mlir.llvm.org/getting_started/TestingGuide/ + + +// CHECK-LABEL: dxsa.dcl_global_flags +// CHECK: dxsa.dcl_input_ps linear v<0, > +// CHECK: dxsa.dcl_input_ps linear v<2, > +// CHECK: dxsa.dcl_input_ps linear v<4, > +// CHECK: dxsa.dcl_input_ps linear v<5, > +// CHECK: dxsa.dcl_input_ps linear v<6, > +// CHECK: dxsa.dcl_input_ps linear v<7, > +// CHECK: dxsa.dcl_input_ps constant v<8, > +// CHECK: dxsa.dcl_output o<0, > +// CHECK: dxsa.dcl_temps 1 +// CHECK: dxsa.dcl_index_range v<4, >, 4 +// CHECK: %[[INDEX_0:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_0:.*]] = dxsa.operand %[[INDEX_0]] {mask = 16 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_1:.*]] = dxsa.index.imm {imm = 8 : i32} +// CHECK: %[[OPERAND_1:.*]] = dxsa.operand %[[INDEX_1]] {num_components = 4 : i32, one = 0 : i32, type = 1 : i32} +// CHECK: dxsa.instruction "mov" %[[OPERAND_0]], %[[OPERAND_1]] +// CHECK: dxsa.add r<0, >, v<2, >, v<4 + r<0, >, > +// CHECK: dxsa.add o<0, >, r<0, >, v<0, > +// CHECK: dxsa.instruction "ret" + diff --git a/mlir/test/Target/DXSA/hlsl/indexableinput2.test b/mlir/test/Target/DXSA/hlsl/indexableinput2.test new file mode 100644 index 000000000000..f8bf3ab71e25 --- /dev/null +++ b/mlir/test/Target/DXSA/hlsl/indexableinput2.test @@ -0,0 +1,41 @@ +// RUN: mlir-translate --import-dxsa-bin %S/inputs/indexableinput2.bin | FileCheck %s +// NOTE: Assertions have been autogenerated by utils/generate-test-checks.py + +// This script is intended to make adding checks to a test case quick and easy. +// It is *not* authoritative about what constitutes a good test. After using the +// script, be sure to review and refine the generated checks. For example, +// CHECK lines should be minimized and named to reflect the test’s intent. +// For comprehensive guidelines, see: +// * https://mlir.llvm.org/getting_started/TestingGuide/ + + +// CHECK-LABEL: dxsa.dcl_global_flags +// CHECK: dxsa.dcl_input_ps linear v<0, > +// CHECK: dxsa.dcl_input_ps linear v<1, > +// CHECK: dxsa.dcl_input_ps linear v<2, > +// CHECK: dxsa.dcl_input_ps linear v<3, > +// CHECK: dxsa.dcl_input_ps linear v<4, > +// CHECK: dxsa.dcl_input_ps linear v<5, > +// CHECK: dxsa.dcl_input_ps linear v<6, > +// CHECK: dxsa.dcl_input_ps linear v<7, > +// CHECK: dxsa.dcl_input_ps linear v<8, > +// CHECK: dxsa.dcl_input_ps constant v<9, > +// CHECK: dxsa.dcl_input_ps_sgv v<10, >, +// CHECK: dxsa.dcl_output o<0, > +// CHECK: dxsa.dcl_temps 1 +// CHECK: dxsa.dcl_index_range v<0, >, 3 +// CHECK: dxsa.dcl_index_range v<3, >, 6 +// CHECK: %[[INDEX_0:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_0:.*]] = dxsa.operand %[[INDEX_0]] {mask = 16 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_1:.*]] = dxsa.index.imm {imm = 10 : i32} +// CHECK: %[[OPERAND_1:.*]] = dxsa.operand %[[INDEX_1]] {num_components = 4 : i32, one = 0 : i32, type = 1 : i32} +// CHECK: dxsa.instruction "mov" %[[OPERAND_0]], %[[OPERAND_1]] +// CHECK: dxsa.add r<0, >, v>, >, v<2, > +// CHECK: %[[INDEX_2:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_2:.*]] = dxsa.operand %[[INDEX_2]] {mask = 32 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_3:.*]] = dxsa.index.imm {imm = 9 : i32} +// CHECK: %[[OPERAND_3:.*]] = dxsa.operand %[[INDEX_3]] {num_components = 4 : i32, one = 0 : i32, type = 1 : i32} +// CHECK: dxsa.instruction "mov" %[[OPERAND_2]], %[[OPERAND_3]] +// CHECK: dxsa.add o<0, >, r<0, >, v<3 + r<0, >, > +// CHECK: dxsa.instruction "ret" + diff --git a/mlir/test/Target/DXSA/hlsl/indexableoutput1.test b/mlir/test/Target/DXSA/hlsl/indexableoutput1.test new file mode 100644 index 000000000000..6964e9de76fe --- /dev/null +++ b/mlir/test/Target/DXSA/hlsl/indexableoutput1.test @@ -0,0 +1,27 @@ +// RUN: mlir-translate --import-dxsa-bin %S/inputs/indexableoutput1.bin | FileCheck %s +// NOTE: Assertions have been autogenerated by utils/generate-test-checks.py + +// This script is intended to make adding checks to a test case quick and easy. +// It is *not* authoritative about what constitutes a good test. After using the +// script, be sure to review and refine the generated checks. For example, +// CHECK lines should be minimized and named to reflect the test’s intent. +// For comprehensive guidelines, see: +// * https://mlir.llvm.org/getting_started/TestingGuide/ + + +// CHECK-LABEL: dxsa.dcl_global_flags +// CHECK: dxsa.dcl_input v<0, > +// CHECK: dxsa.dcl_output o<2> +// CHECK: dxsa.dcl_output_siv o<7>, +// CHECK: %[[INDEX_0:.*]] = dxsa.index.imm {imm = 2 : i32} +// CHECK: %[[OPERAND_0:.*]] = dxsa.operand %[[INDEX_0]] {mask = 240 : i32, num_components = 4 : i32, type = 2 : i32} +// CHECK: %[[INDEX_1:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_1:.*]] = dxsa.operand %[[INDEX_1]] {num_components = 4 : i32, swizzle = dense<0> : vector<4xi32>, type = 1 : i32} +// CHECK: dxsa.instruction "mov" %[[OPERAND_0]], %[[OPERAND_1]] +// CHECK: %[[INDEX_2:.*]] = dxsa.index.imm {imm = 7 : i32} +// CHECK: %[[OPERAND_2:.*]] = dxsa.operand %[[INDEX_2]] {mask = 240 : i32, num_components = 4 : i32, type = 2 : i32} +// CHECK: %[[INDEX_3:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_3:.*]] = dxsa.operand %[[INDEX_3]] {num_components = 4 : i32, swizzle = dense<0> : vector<4xi32>, type = 1 : i32} +// CHECK: dxsa.instruction "mov" %[[OPERAND_2]], %[[OPERAND_3]] +// CHECK: dxsa.instruction "ret" + diff --git a/mlir/test/Target/DXSA/hlsl/indexabletemp1.test b/mlir/test/Target/DXSA/hlsl/indexabletemp1.test new file mode 100644 index 000000000000..e8144df2bd43 --- /dev/null +++ b/mlir/test/Target/DXSA/hlsl/indexabletemp1.test @@ -0,0 +1,100 @@ +// RUN: mlir-translate --import-dxsa-bin %S/inputs/indexabletemp1.bin | FileCheck %s +// NOTE: Assertions have been autogenerated by utils/generate-test-checks.py + +// This script is intended to make adding checks to a test case quick and easy. +// It is *not* authoritative about what constitutes a good test. After using the +// script, be sure to review and refine the generated checks. For example, +// CHECK lines should be minimized and named to reflect the test’s intent. +// For comprehensive guidelines, see: +// * https://mlir.llvm.org/getting_started/TestingGuide/ + + +// CHECK-LABEL: dxsa.dcl_global_flags +// CHECK: dxsa.dcl_constant_buffer , +// CHECK: dxsa.dcl_input_ps constant v<1, > +// CHECK: dxsa.dcl_input_ps constant v<1, > +// CHECK: dxsa.dcl_output o<0, > +// CHECK: dxsa.dcl_temps 1 +// CHECK: dxsa.dcl_indexable_temp x<0>[6] +// CHECK: %[[INDEX_0:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_0:.*]] = dxsa.operand %[[INDEX_0]] {mask = 16 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_1:.*]] = dxsa.index.imm {imm = 1 : i32} +// CHECK: %[[OPERAND_1:.*]] = dxsa.operand %[[INDEX_1]] {num_components = 4 : i32, one = 0 : i32, type = 1 : i32} +// CHECK: dxsa.instruction "mov" %[[OPERAND_0]], %[[OPERAND_1]] +// CHECK: %[[INDEX_2:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[INDEX_3:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_2:.*]] = dxsa.operand %[[INDEX_2]], %[[INDEX_3]] {mask = 16 : i32, num_components = 4 : i32, type = 3 : i32} +// CHECK: %[[INDEX_4:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[INDEX_5:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_3:.*]] = dxsa.operand %[[INDEX_5]] {num_components = 4 : i32, one = 0 : i32, type = 0 : i32} +// CHECK: %[[INDEX_6:.*]] = dxsa.index.rel %[[OPERAND_3]] +// CHECK: %[[OPERAND_4:.*]] = dxsa.operand %[[INDEX_4]], %[[INDEX_6]] {num_components = 4 : i32, one = 0 : i32, type = 8 : i32} +// CHECK: dxsa.instruction "mov" %[[OPERAND_2]], %[[OPERAND_4]] +// CHECK: %[[INDEX_7:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[INDEX_8:.*]] = dxsa.index.imm {imm = 1 : i32} +// CHECK: %[[OPERAND_5:.*]] = dxsa.operand %[[INDEX_7]], %[[INDEX_8]] {mask = 16 : i32, num_components = 4 : i32, type = 3 : i32} +// CHECK: %[[INDEX_9:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[INDEX_10:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_6:.*]] = dxsa.operand %[[INDEX_10]] {num_components = 4 : i32, one = 0 : i32, type = 0 : i32} +// CHECK: %[[INDEX_11:.*]] = dxsa.index.rel.imm %[[OPERAND_6]] {imm = 6 : i32, op = "add"} +// CHECK: %[[OPERAND_7:.*]] = dxsa.operand %[[INDEX_9]], %[[INDEX_11]] {num_components = 4 : i32, one = 0 : i32, type = 8 : i32} +// CHECK: dxsa.instruction "mov" %[[OPERAND_5]], %[[OPERAND_7]] +// CHECK: %[[INDEX_12:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_8:.*]] = dxsa.operand %[[INDEX_12]] {mask = 240 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_13:.*]] = dxsa.index.imm {imm = 1 : i32} +// CHECK: %[[OPERAND_9:.*]] = dxsa.operand %[[INDEX_13]] {num_components = 4 : i32, swizzle = dense<0> : vector<4xi32>, type = 1 : i32} +// CHECK: %[[OPERAND_10:.*]] = dxsa.operand.imm {imm = dense<[2, 3, 4, 5]> : vector<4xi32>} +// CHECK: dxsa.instruction "iadd" %[[OPERAND_8]], %[[OPERAND_9]], %[[OPERAND_10]] +// CHECK: %[[INDEX_14:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[INDEX_15:.*]] = dxsa.index.imm {imm = 2 : i32} +// CHECK: %[[OPERAND_11:.*]] = dxsa.operand %[[INDEX_14]], %[[INDEX_15]] {mask = 16 : i32, num_components = 4 : i32, type = 3 : i32} +// CHECK: %[[INDEX_16:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[INDEX_17:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_12:.*]] = dxsa.operand %[[INDEX_17]] {num_components = 4 : i32, one = 0 : i32, type = 0 : i32} +// CHECK: %[[INDEX_18:.*]] = dxsa.index.rel %[[OPERAND_12]] +// CHECK: %[[OPERAND_13:.*]] = dxsa.operand %[[INDEX_16]], %[[INDEX_18]] {num_components = 4 : i32, one = 0 : i32, type = 8 : i32} +// CHECK: dxsa.instruction "mov" %[[OPERAND_11]], %[[OPERAND_13]] +// CHECK: %[[INDEX_19:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[INDEX_20:.*]] = dxsa.index.imm {imm = 3 : i32} +// CHECK: %[[OPERAND_14:.*]] = dxsa.operand %[[INDEX_19]], %[[INDEX_20]] {mask = 16 : i32, num_components = 4 : i32, type = 3 : i32} +// CHECK: %[[INDEX_21:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[INDEX_22:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_15:.*]] = dxsa.operand %[[INDEX_22]] {num_components = 4 : i32, one = 1 : i32, type = 0 : i32} +// CHECK: %[[INDEX_23:.*]] = dxsa.index.rel %[[OPERAND_15]] +// CHECK: %[[OPERAND_16:.*]] = dxsa.operand %[[INDEX_21]], %[[INDEX_23]] {num_components = 4 : i32, one = 0 : i32, type = 8 : i32} +// CHECK: dxsa.instruction "mov" %[[OPERAND_14]], %[[OPERAND_16]] +// CHECK: %[[INDEX_24:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[INDEX_25:.*]] = dxsa.index.imm {imm = 4 : i32} +// CHECK: %[[OPERAND_17:.*]] = dxsa.operand %[[INDEX_24]], %[[INDEX_25]] {mask = 16 : i32, num_components = 4 : i32, type = 3 : i32} +// CHECK: %[[INDEX_26:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[INDEX_27:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_18:.*]] = dxsa.operand %[[INDEX_27]] {num_components = 4 : i32, one = 2 : i32, type = 0 : i32} +// CHECK: %[[INDEX_28:.*]] = dxsa.index.rel %[[OPERAND_18]] +// CHECK: %[[OPERAND_19:.*]] = dxsa.operand %[[INDEX_26]], %[[INDEX_28]] {num_components = 4 : i32, one = 0 : i32, type = 8 : i32} +// CHECK: dxsa.instruction "mov" %[[OPERAND_17]], %[[OPERAND_19]] +// CHECK: %[[INDEX_29:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[INDEX_30:.*]] = dxsa.index.imm {imm = 5 : i32} +// CHECK: %[[OPERAND_20:.*]] = dxsa.operand %[[INDEX_29]], %[[INDEX_30]] {mask = 16 : i32, num_components = 4 : i32, type = 3 : i32} +// CHECK: %[[INDEX_31:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[INDEX_32:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_21:.*]] = dxsa.operand %[[INDEX_32]] {num_components = 4 : i32, one = 3 : i32, type = 0 : i32} +// CHECK: %[[INDEX_33:.*]] = dxsa.index.rel %[[OPERAND_21]] +// CHECK: %[[OPERAND_22:.*]] = dxsa.operand %[[INDEX_31]], %[[INDEX_33]] {num_components = 4 : i32, one = 0 : i32, type = 8 : i32} +// CHECK: dxsa.instruction "mov" %[[OPERAND_20]], %[[OPERAND_22]] +// CHECK: %[[INDEX_34:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_23:.*]] = dxsa.operand %[[INDEX_34]] {mask = 16 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_35:.*]] = dxsa.index.imm {imm = 1 : i32} +// CHECK: %[[OPERAND_24:.*]] = dxsa.operand %[[INDEX_35]] {num_components = 4 : i32, one = 0 : i32, type = 1 : i32} +// CHECK: %[[INDEX_36:.*]] = dxsa.index.imm {imm = 1 : i32} +// CHECK: %[[OPERAND_25:.*]] = dxsa.operand %[[INDEX_36]] {num_components = 4 : i32, one = 1 : i32, type = 1 : i32} +// CHECK: dxsa.instruction "iadd" %[[OPERAND_23]], %[[OPERAND_24]], %[[OPERAND_25]] +// CHECK: %[[INDEX_37:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_26:.*]] = dxsa.operand %[[INDEX_37]] {mask = 16 : i32, num_components = 4 : i32, type = 2 : i32} +// CHECK: %[[INDEX_38:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[INDEX_39:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_27:.*]] = dxsa.operand %[[INDEX_39]] {num_components = 4 : i32, one = 0 : i32, type = 0 : i32} +// CHECK: %[[INDEX_40:.*]] = dxsa.index.rel %[[OPERAND_27]] +// CHECK: %[[OPERAND_28:.*]] = dxsa.operand %[[INDEX_38]], %[[INDEX_40]] {num_components = 4 : i32, one = 0 : i32, type = 3 : i32} +// CHECK: dxsa.instruction "mov" %[[OPERAND_26]], %[[OPERAND_28]] +// CHECK: dxsa.instruction "ret" + diff --git a/mlir/test/Target/DXSA/hlsl/indexabletemp2.test b/mlir/test/Target/DXSA/hlsl/indexabletemp2.test new file mode 100644 index 000000000000..4f30151ffe3e --- /dev/null +++ b/mlir/test/Target/DXSA/hlsl/indexabletemp2.test @@ -0,0 +1,123 @@ +// RUN: mlir-translate --import-dxsa-bin %S/inputs/indexabletemp2.bin | FileCheck %s +// NOTE: Assertions have been autogenerated by utils/generate-test-checks.py + +// This script is intended to make adding checks to a test case quick and easy. +// It is *not* authoritative about what constitutes a good test. After using the +// script, be sure to review and refine the generated checks. For example, +// CHECK lines should be minimized and named to reflect the test’s intent. +// For comprehensive guidelines, see: +// * https://mlir.llvm.org/getting_started/TestingGuide/ + + +// CHECK-LABEL: dxsa.dcl_global_flags +// CHECK: dxsa.dcl_constant_buffer , +// CHECK: dxsa.dcl_input_ps constant v<1, > +// CHECK: dxsa.dcl_input_ps constant v<1, > +// CHECK: dxsa.dcl_output o<0, > +// CHECK: dxsa.dcl_temps 1 +// CHECK: dxsa.dcl_indexable_temp x<0>[4] +// CHECK: dxsa.dcl_indexable_temp x<1>[2] +// CHECK: %[[INDEX_0:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_0:.*]] = dxsa.operand %[[INDEX_0]] {mask = 16 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_1:.*]] = dxsa.index.imm {imm = 1 : i32} +// CHECK: %[[OPERAND_1:.*]] = dxsa.operand %[[INDEX_1]] {num_components = 4 : i32, one = 0 : i32, type = 1 : i32} +// CHECK: dxsa.instruction "mov" %[[OPERAND_0]], %[[OPERAND_1]] +// CHECK: %[[INDEX_2:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[INDEX_3:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_2:.*]] = dxsa.operand %[[INDEX_2]], %[[INDEX_3]] {mask = 16 : i32, num_components = 4 : i32, type = 3 : i32} +// CHECK: %[[INDEX_4:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[INDEX_5:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_3:.*]] = dxsa.operand %[[INDEX_5]] {num_components = 4 : i32, one = 0 : i32, type = 0 : i32} +// CHECK: %[[INDEX_6:.*]] = dxsa.index.rel %[[OPERAND_3]] +// CHECK: %[[OPERAND_4:.*]] = dxsa.operand %[[INDEX_4]], %[[INDEX_6]] {num_components = 4 : i32, one = 0 : i32, type = 8 : i32} +// CHECK: dxsa.instruction "mov" %[[OPERAND_2]], %[[OPERAND_4]] +// CHECK: %[[INDEX_7:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[INDEX_8:.*]] = dxsa.index.imm {imm = 1 : i32} +// CHECK: %[[OPERAND_5:.*]] = dxsa.operand %[[INDEX_7]], %[[INDEX_8]] {mask = 16 : i32, num_components = 4 : i32, type = 3 : i32} +// CHECK: %[[INDEX_9:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[INDEX_10:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_6:.*]] = dxsa.operand %[[INDEX_10]] {num_components = 4 : i32, one = 0 : i32, type = 0 : i32} +// CHECK: %[[INDEX_11:.*]] = dxsa.index.rel.imm %[[OPERAND_6]] {imm = 4 : i32, op = "add"} +// CHECK: %[[OPERAND_7:.*]] = dxsa.operand %[[INDEX_9]], %[[INDEX_11]] {num_components = 4 : i32, one = 0 : i32, type = 8 : i32} +// CHECK: dxsa.instruction "mov" %[[OPERAND_5]], %[[OPERAND_7]] +// CHECK: %[[INDEX_12:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_8:.*]] = dxsa.operand %[[INDEX_12]] {mask = 240 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_13:.*]] = dxsa.index.imm {imm = 1 : i32} +// CHECK: %[[OPERAND_9:.*]] = dxsa.operand %[[INDEX_13]] {num_components = 4 : i32, swizzle = dense<[0, 0, 0, 1]> : vector<4xi32>, type = 1 : i32} +// CHECK: %[[OPERAND_10:.*]] = dxsa.operand.imm {imm = dense<[2, 3, 11, 13]> : vector<4xi32>} +// CHECK: dxsa.instruction "iadd" %[[OPERAND_8]], %[[OPERAND_9]], %[[OPERAND_10]] +// CHECK: %[[INDEX_14:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[INDEX_15:.*]] = dxsa.index.imm {imm = 2 : i32} +// CHECK: %[[OPERAND_11:.*]] = dxsa.operand %[[INDEX_14]], %[[INDEX_15]] {mask = 16 : i32, num_components = 4 : i32, type = 3 : i32} +// CHECK: %[[INDEX_16:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[INDEX_17:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_12:.*]] = dxsa.operand %[[INDEX_17]] {num_components = 4 : i32, one = 0 : i32, type = 0 : i32} +// CHECK: %[[INDEX_18:.*]] = dxsa.index.rel %[[OPERAND_12]] +// CHECK: %[[OPERAND_13:.*]] = dxsa.operand %[[INDEX_16]], %[[INDEX_18]] {num_components = 4 : i32, one = 0 : i32, type = 8 : i32} +// CHECK: dxsa.instruction "mov" %[[OPERAND_11]], %[[OPERAND_13]] +// CHECK: %[[INDEX_19:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[INDEX_20:.*]] = dxsa.index.imm {imm = 3 : i32} +// CHECK: %[[OPERAND_14:.*]] = dxsa.operand %[[INDEX_19]], %[[INDEX_20]] {mask = 16 : i32, num_components = 4 : i32, type = 3 : i32} +// CHECK: %[[INDEX_21:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[INDEX_22:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_15:.*]] = dxsa.operand %[[INDEX_22]] {num_components = 4 : i32, one = 1 : i32, type = 0 : i32} +// CHECK: %[[INDEX_23:.*]] = dxsa.index.rel %[[OPERAND_15]] +// CHECK: %[[OPERAND_16:.*]] = dxsa.operand %[[INDEX_21]], %[[INDEX_23]] {num_components = 4 : i32, one = 0 : i32, type = 8 : i32} +// CHECK: dxsa.instruction "mov" %[[OPERAND_14]], %[[OPERAND_16]] +// CHECK: %[[INDEX_24:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_17:.*]] = dxsa.operand %[[INDEX_24]] {mask = 16 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_25:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[INDEX_26:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_18:.*]] = dxsa.operand %[[INDEX_26]] {num_components = 4 : i32, one = 2 : i32, type = 0 : i32} +// CHECK: %[[INDEX_27:.*]] = dxsa.index.rel.imm %[[OPERAND_18]] {imm = 12 : i32, op = "add"} +// CHECK: %[[OPERAND_19:.*]] = dxsa.operand %[[INDEX_25]], %[[INDEX_27]] {num_components = 4 : i32, one = 0 : i32, type = 8 : i32} +// CHECK: %[[INDEX_28:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[INDEX_29:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_20:.*]] = dxsa.operand %[[INDEX_29]] {num_components = 4 : i32, one = 3 : i32, type = 0 : i32} +// CHECK: %[[INDEX_30:.*]] = dxsa.index.rel.imm %[[OPERAND_20]] {imm = 16 : i32, op = "add"} +// CHECK: %[[OPERAND_21:.*]] = dxsa.operand %[[INDEX_28]], %[[INDEX_30]] {num_components = 4 : i32, one = 0 : i32, type = 8 : i32} +// CHECK: dxsa.instruction "iadd" %[[OPERAND_17]], %[[OPERAND_19]], %[[OPERAND_21]] +// CHECK: %[[INDEX_31:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_22:.*]] = dxsa.operand %[[INDEX_31]] {mask = 32 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[OPERAND_23:.*]] = dxsa.operand.imm {imm = dense<-13> : vector<1xi32>} +// CHECK: %[[INDEX_32:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[INDEX_33:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_24:.*]] = dxsa.operand %[[INDEX_33]] {num_components = 4 : i32, one = 3 : i32, type = 0 : i32} +// CHECK: %[[INDEX_34:.*]] = dxsa.index.rel.imm %[[OPERAND_24]] {imm = 16 : i32, op = "add"} +// CHECK: %[[OPERAND_25:.*]] = dxsa.operand %[[INDEX_32]], %[[INDEX_34]] {num_components = 4 : i32, one = 0 : i32, type = 8 : i32} +// CHECK: dxsa.instruction "iadd" %[[OPERAND_22]], %[[OPERAND_23]], %[[OPERAND_25]] +// CHECK: %[[INDEX_35:.*]] = dxsa.index.imm {imm = 1 : i32} +// CHECK: %[[INDEX_36:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_26:.*]] = dxsa.operand %[[INDEX_35]], %[[INDEX_36]] {mask = 16 : i32, num_components = 4 : i32, type = 3 : i32} +// CHECK: %[[INDEX_37:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_27:.*]] = dxsa.operand %[[INDEX_37]] {num_components = 4 : i32, one = 0 : i32, type = 0 : i32} +// CHECK: dxsa.instruction "mov" %[[OPERAND_26]], %[[OPERAND_27]] +// CHECK: %[[INDEX_38:.*]] = dxsa.index.imm {imm = 1 : i32} +// CHECK: %[[INDEX_39:.*]] = dxsa.index.imm {imm = 1 : i32} +// CHECK: %[[OPERAND_28:.*]] = dxsa.operand %[[INDEX_38]], %[[INDEX_39]] {mask = 16 : i32, num_components = 4 : i32, type = 3 : i32} +// CHECK: %[[INDEX_40:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_29:.*]] = dxsa.operand %[[INDEX_40]] {num_components = 4 : i32, one = 1 : i32, type = 0 : i32} +// CHECK: dxsa.instruction "mov" %[[OPERAND_28]], %[[OPERAND_29]] +// CHECK: %[[INDEX_41:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_30:.*]] = dxsa.operand %[[INDEX_41]] {mask = 16 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_42:.*]] = dxsa.index.imm {imm = 1 : i32} +// CHECK: %[[OPERAND_31:.*]] = dxsa.operand %[[INDEX_42]] {num_components = 4 : i32, one = 1 : i32, type = 1 : i32} +// CHECK: dxsa.instruction "mov" %[[OPERAND_30]], %[[OPERAND_31]] +// CHECK: %[[INDEX_43:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_32:.*]] = dxsa.operand %[[INDEX_43]] {mask = 16 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_44:.*]] = dxsa.index.imm {imm = 1 : i32} +// CHECK: %[[INDEX_45:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_33:.*]] = dxsa.operand %[[INDEX_45]] {num_components = 4 : i32, one = 0 : i32, type = 0 : i32} +// CHECK: %[[INDEX_46:.*]] = dxsa.index.rel %[[OPERAND_33]] +// CHECK: %[[OPERAND_34:.*]] = dxsa.operand %[[INDEX_44]], %[[INDEX_46]] {num_components = 4 : i32, one = 0 : i32, type = 3 : i32} +// CHECK: dxsa.instruction "mov" %[[OPERAND_32]], %[[OPERAND_34]] +// CHECK: %[[INDEX_47:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_35:.*]] = dxsa.operand %[[INDEX_47]] {mask = 16 : i32, num_components = 4 : i32, type = 2 : i32} +// CHECK: %[[INDEX_48:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[INDEX_49:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_36:.*]] = dxsa.operand %[[INDEX_49]] {num_components = 4 : i32, one = 0 : i32, type = 0 : i32} +// CHECK: %[[INDEX_50:.*]] = dxsa.index.rel %[[OPERAND_36]] +// CHECK: %[[OPERAND_37:.*]] = dxsa.operand %[[INDEX_48]], %[[INDEX_50]] {num_components = 4 : i32, one = 0 : i32, type = 3 : i32} +// CHECK: dxsa.instruction "mov" %[[OPERAND_35]], %[[OPERAND_37]] +// CHECK: dxsa.instruction "ret" + diff --git a/mlir/test/Target/DXSA/hlsl/indexabletemp3.test b/mlir/test/Target/DXSA/hlsl/indexabletemp3.test new file mode 100644 index 000000000000..75e350240aaf --- /dev/null +++ b/mlir/test/Target/DXSA/hlsl/indexabletemp3.test @@ -0,0 +1,56 @@ +// RUN: mlir-translate --import-dxsa-bin %S/inputs/indexabletemp3.bin | FileCheck %s +// NOTE: Assertions have been autogenerated by utils/generate-test-checks.py + +// This script is intended to make adding checks to a test case quick and easy. +// It is *not* authoritative about what constitutes a good test. After using the +// script, be sure to review and refine the generated checks. For example, +// CHECK lines should be minimized and named to reflect the test’s intent. +// For comprehensive guidelines, see: +// * https://mlir.llvm.org/getting_started/TestingGuide/ + + +// CHECK-LABEL: dxsa.dcl_global_flags +// CHECK: dxsa.dcl_constant_buffer , +// CHECK: dxsa.dcl_input_ps constant v<1, > +// CHECK: dxsa.dcl_input_ps constant v<1, > +// CHECK: dxsa.dcl_output o<0, > +// CHECK: dxsa.dcl_temps 1 +// CHECK: dxsa.dcl_indexable_temp x<0>[4] +// CHECK: %[[INDEX_0:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_0:.*]] = dxsa.operand %[[INDEX_0]] {mask = 16 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_1:.*]] = dxsa.index.imm {imm = 1 : i32} +// CHECK: %[[OPERAND_1:.*]] = dxsa.operand %[[INDEX_1]] {num_components = 4 : i32, one = 0 : i32, type = 1 : i32} +// CHECK: dxsa.instruction "mov" %[[OPERAND_0]], %[[OPERAND_1]] +// CHECK: %[[INDEX_2:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[INDEX_3:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_2:.*]] = dxsa.operand %[[INDEX_2]], %[[INDEX_3]] {mask = 16 : i32, num_components = 4 : i32, type = 3 : i32} +// CHECK: %[[INDEX_4:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[INDEX_5:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_3:.*]] = dxsa.operand %[[INDEX_5]] {num_components = 4 : i32, one = 0 : i32, type = 0 : i32} +// CHECK: %[[INDEX_6:.*]] = dxsa.index.rel %[[OPERAND_3]] +// CHECK: %[[OPERAND_4:.*]] = dxsa.operand %[[INDEX_4]], %[[INDEX_6]] {num_components = 4 : i32, one = 0 : i32, type = 8 : i32} +// CHECK: dxsa.instruction "mov" %[[OPERAND_2]], %[[OPERAND_4]] +// CHECK: %[[INDEX_7:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[INDEX_8:.*]] = dxsa.index.imm {imm = 1 : i32} +// CHECK: %[[OPERAND_5:.*]] = dxsa.operand %[[INDEX_7]], %[[INDEX_8]] {mask = 16 : i32, num_components = 4 : i32, type = 3 : i32} +// CHECK: %[[INDEX_9:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[INDEX_10:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_6:.*]] = dxsa.operand %[[INDEX_10]] {num_components = 4 : i32, one = 0 : i32, type = 0 : i32} +// CHECK: %[[INDEX_11:.*]] = dxsa.index.rel.imm %[[OPERAND_6]] {imm = 4 : i32, op = "add"} +// CHECK: %[[OPERAND_7:.*]] = dxsa.operand %[[INDEX_9]], %[[INDEX_11]] {num_components = 4 : i32, one = 0 : i32, type = 8 : i32} +// CHECK: dxsa.instruction "mov" %[[OPERAND_5]], %[[OPERAND_7]] +// CHECK: %[[INDEX_12:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_8:.*]] = dxsa.operand %[[INDEX_12]] {mask = 16 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_13:.*]] = dxsa.index.imm {imm = 1 : i32} +// CHECK: %[[OPERAND_9:.*]] = dxsa.operand %[[INDEX_13]] {num_components = 4 : i32, one = 1 : i32, type = 1 : i32} +// CHECK: dxsa.instruction "mov" %[[OPERAND_8]], %[[OPERAND_9]] +// CHECK: %[[INDEX_14:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_10:.*]] = dxsa.operand %[[INDEX_14]] {mask = 16 : i32, num_components = 4 : i32, type = 2 : i32} +// CHECK: %[[INDEX_15:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[INDEX_16:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_11:.*]] = dxsa.operand %[[INDEX_16]] {num_components = 4 : i32, one = 0 : i32, type = 0 : i32} +// CHECK: %[[INDEX_17:.*]] = dxsa.index.rel %[[OPERAND_11]] +// CHECK: %[[OPERAND_12:.*]] = dxsa.operand %[[INDEX_15]], %[[INDEX_17]] {num_components = 4 : i32, one = 0 : i32, type = 3 : i32} +// CHECK: dxsa.instruction "mov" %[[OPERAND_10]], %[[OPERAND_12]] +// CHECK: dxsa.instruction "ret" + diff --git a/mlir/test/Target/DXSA/hlsl/indexabletemp5.test b/mlir/test/Target/DXSA/hlsl/indexabletemp5.test new file mode 100644 index 000000000000..fd9bed1d8b5e --- /dev/null +++ b/mlir/test/Target/DXSA/hlsl/indexabletemp5.test @@ -0,0 +1,56 @@ +// RUN: mlir-translate --import-dxsa-bin %S/inputs/indexabletemp5.bin | FileCheck %s +// NOTE: Assertions have been autogenerated by utils/generate-test-checks.py + +// This script is intended to make adding checks to a test case quick and easy. +// It is *not* authoritative about what constitutes a good test. After using the +// script, be sure to review and refine the generated checks. For example, +// CHECK lines should be minimized and named to reflect the test’s intent. +// For comprehensive guidelines, see: +// * https://mlir.llvm.org/getting_started/TestingGuide/ + + +// CHECK-LABEL: dxsa.dcl_global_flags +// CHECK: dxsa.dcl_constant_buffer , +// CHECK: dxsa.dcl_input_ps constant v<1, > +// CHECK: dxsa.dcl_input_ps constant v<1, > +// CHECK: dxsa.dcl_output o<0, min16f, > +// CHECK: dxsa.dcl_temps 1 +// CHECK: dxsa.dcl_indexable_temp x<0>[4] +// CHECK: %[[INDEX_0:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_0:.*]] = dxsa.operand %[[INDEX_0]] {mask = 16 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_1:.*]] = dxsa.index.imm {imm = 1 : i32} +// CHECK: %[[OPERAND_1:.*]] = dxsa.operand %[[INDEX_1]] {num_components = 4 : i32, one = 0 : i32, type = 1 : i32} +// CHECK: dxsa.instruction "mov" %[[OPERAND_0]], %[[OPERAND_1]] +// CHECK: %[[INDEX_2:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[INDEX_3:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_2:.*]] = dxsa.operand %[[INDEX_2]], %[[INDEX_3]] {mask = 16 : i32, min_precision = 1 : i32, num_components = 4 : i32, type = 3 : i32} +// CHECK: %[[INDEX_4:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[INDEX_5:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_3:.*]] = dxsa.operand %[[INDEX_5]] {num_components = 4 : i32, one = 0 : i32, type = 0 : i32} +// CHECK: %[[INDEX_6:.*]] = dxsa.index.rel %[[OPERAND_3]] +// CHECK: %[[OPERAND_4:.*]] = dxsa.operand %[[INDEX_4]], %[[INDEX_6]] {min_precision = 1 : i32, num_components = 4 : i32, one = 0 : i32, type = 8 : i32} +// CHECK: dxsa.instruction "mov" %[[OPERAND_2]], %[[OPERAND_4]] +// CHECK: %[[INDEX_7:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[INDEX_8:.*]] = dxsa.index.imm {imm = 1 : i32} +// CHECK: %[[OPERAND_5:.*]] = dxsa.operand %[[INDEX_7]], %[[INDEX_8]] {mask = 16 : i32, min_precision = 1 : i32, num_components = 4 : i32, type = 3 : i32} +// CHECK: %[[INDEX_9:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[INDEX_10:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_6:.*]] = dxsa.operand %[[INDEX_10]] {num_components = 4 : i32, one = 0 : i32, type = 0 : i32} +// CHECK: %[[INDEX_11:.*]] = dxsa.index.rel.imm %[[OPERAND_6]] {imm = 4 : i32, op = "add"} +// CHECK: %[[OPERAND_7:.*]] = dxsa.operand %[[INDEX_9]], %[[INDEX_11]] {min_precision = 1 : i32, num_components = 4 : i32, one = 0 : i32, type = 8 : i32} +// CHECK: dxsa.instruction "mov" %[[OPERAND_5]], %[[OPERAND_7]] +// CHECK: %[[INDEX_12:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_8:.*]] = dxsa.operand %[[INDEX_12]] {mask = 16 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_13:.*]] = dxsa.index.imm {imm = 1 : i32} +// CHECK: %[[OPERAND_9:.*]] = dxsa.operand %[[INDEX_13]] {num_components = 4 : i32, one = 1 : i32, type = 1 : i32} +// CHECK: dxsa.instruction "mov" %[[OPERAND_8]], %[[OPERAND_9]] +// CHECK: %[[INDEX_14:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_10:.*]] = dxsa.operand %[[INDEX_14]] {mask = 16 : i32, min_precision = 1 : i32, num_components = 4 : i32, type = 2 : i32} +// CHECK: %[[INDEX_15:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[INDEX_16:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_11:.*]] = dxsa.operand %[[INDEX_16]] {num_components = 4 : i32, one = 0 : i32, type = 0 : i32} +// CHECK: %[[INDEX_17:.*]] = dxsa.index.rel %[[OPERAND_11]] +// CHECK: %[[OPERAND_12:.*]] = dxsa.operand %[[INDEX_15]], %[[INDEX_17]] {min_precision = 1 : i32, num_components = 4 : i32, one = 0 : i32, type = 3 : i32} +// CHECK: dxsa.instruction "mov" %[[OPERAND_10]], %[[OPERAND_12]] +// CHECK: dxsa.instruction "ret" + diff --git a/mlir/test/Target/DXSA/hlsl/input1.test b/mlir/test/Target/DXSA/hlsl/input1.test new file mode 100644 index 000000000000..5b4504c9d254 --- /dev/null +++ b/mlir/test/Target/DXSA/hlsl/input1.test @@ -0,0 +1,52 @@ +// RUN: mlir-translate --import-dxsa-bin %S/inputs/input1.bin | FileCheck %s +// NOTE: Assertions have been autogenerated by utils/generate-test-checks.py + +// This script is intended to make adding checks to a test case quick and easy. +// It is *not* authoritative about what constitutes a good test. After using the +// script, be sure to review and refine the generated checks. For example, +// CHECK lines should be minimized and named to reflect the test’s intent. +// For comprehensive guidelines, see: +// * https://mlir.llvm.org/getting_started/TestingGuide/ + + +// CHECK-LABEL: dxsa.dcl_global_flags +// CHECK: dxsa.dcl_input_ps linear v<0> +// CHECK: dxsa.dcl_input_ps constant v<1> +// CHECK: dxsa.dcl_input_ps constant v<2> +// CHECK: dxsa.dcl_input_ps linear v<3, min16f> +// CHECK: dxsa.dcl_input_ps_siv linear v<4, >, +// CHECK: dxsa.dcl_input_ps_siv linear v<4, >, +// CHECK: dxsa.dcl_input_ps constant v<5, > +// CHECK: dxsa.dcl_input_ps_sgv v<5, >, +// CHECK: dxsa.dcl_input_ps_siv constant v<5, >, +// CHECK: dxsa.dcl_input_ps_siv constant v<5, >, +// CHECK: dxsa.dcl_input_ps_siv linearNoPerspective v<6>, +// CHECK: dxsa.dcl_input_ps_sgv v<7, >, +// CHECK: dxsa.dcl_input_ps_sgv v<7, >, +// CHECK: dxsa.dcl_input vCoverage +// CHECK: dxsa.dcl_output o<0> +// CHECK: dxsa.dcl_temps 2 +// CHECK: dxsa.itof r<0>, v<1> +// CHECK: dxsa.add r<0>, r<0>, v<0> +// CHECK: dxsa.utof r<1>, v<2> +// CHECK: dxsa.add r<0>, r<0>, r<1> +// CHECK: dxsa.add r<0>, r<0>, v<3, min16f> +// CHECK: dxsa.add r<0>, r<0>, v<4, > +// CHECK: dxsa.add r<0>, r<0>, v<4, > +// CHECK: dxsa.utof r<1, >, vCoverage> +// CHECK: dxsa.add r<0>, r<0>, r<1, > +// CHECK: dxsa.utof r<1, >, v<5, > +// CHECK: dxsa.add r<0>, r<0>, r<1, > +// CHECK: dxsa.utof r<1, >, v<5, > +// CHECK: dxsa.add r<0>, r<0>, r<1, > +// CHECK: dxsa.utof r<1, >, v<5, > +// CHECK: dxsa.add r<0>, r<0>, r<1, > +// CHECK: dxsa.utof r<1, >, v<5, > +// CHECK: dxsa.add r<0>, r<0>, r<1, > +// CHECK: dxsa.add r<0>, r<0>, v<6> +// CHECK: dxsa.utof r<1, >, v<7, > +// CHECK: dxsa.add r<0>, r<0>, r<1, > +// CHECK: dxsa.and r<1, >, v<7, >, l(0x3F800000) +// CHECK: dxsa.add o<0>, r<0>, r<1, > +// CHECK: dxsa.instruction "ret" + diff --git a/mlir/test/Target/DXSA/hlsl/input2.test b/mlir/test/Target/DXSA/hlsl/input2.test new file mode 100644 index 000000000000..e1eb1de138d1 --- /dev/null +++ b/mlir/test/Target/DXSA/hlsl/input2.test @@ -0,0 +1,52 @@ +// RUN: mlir-translate --import-dxsa-bin %S/inputs/input2.bin | FileCheck %s +// NOTE: Assertions have been autogenerated by utils/generate-test-checks.py + +// This script is intended to make adding checks to a test case quick and easy. +// It is *not* authoritative about what constitutes a good test. After using the +// script, be sure to review and refine the generated checks. For example, +// CHECK lines should be minimized and named to reflect the test’s intent. +// For comprehensive guidelines, see: +// * https://mlir.llvm.org/getting_started/TestingGuide/ + + +// CHECK-LABEL: dxsa.dcl_global_flags +// CHECK: dxsa.dcl_input_ps linear v<0> +// CHECK: dxsa.dcl_input_ps constant v<1> +// CHECK: dxsa.dcl_input_ps constant v<2> +// CHECK: dxsa.dcl_input_ps linear v<3, min16f> +// CHECK: dxsa.dcl_input_ps_siv linear v<4, >, +// CHECK: dxsa.dcl_input_ps_siv linear v<4, >, +// CHECK: dxsa.dcl_input_ps constant v<5, > +// CHECK: dxsa.dcl_input_ps_sgv v<5, >, +// CHECK: dxsa.dcl_input_ps_siv constant v<5, >, +// CHECK: dxsa.dcl_input_ps_siv constant v<5, >, +// CHECK: dxsa.dcl_input_ps_siv linearNoPerspective v<6>, +// CHECK: dxsa.dcl_input_ps_sgv v<7, >, +// CHECK: dxsa.dcl_input_ps_sgv v<7, >, +// CHECK: dxsa.dcl_input vInnerCoverage +// CHECK: dxsa.dcl_output o<0> +// CHECK: dxsa.dcl_temps 2 +// CHECK: dxsa.itof r<0>, v<1> +// CHECK: dxsa.add r<0>, r<0>, v<0> +// CHECK: dxsa.utof r<1>, v<2> +// CHECK: dxsa.add r<0>, r<0>, r<1> +// CHECK: dxsa.add r<0>, r<0>, v<3, min16f> +// CHECK: dxsa.add r<0>, r<0>, v<4, > +// CHECK: dxsa.add r<0>, r<0>, v<4, > +// CHECK: dxsa.utof r<1, >, vInnerCoverage> +// CHECK: dxsa.add r<0>, r<0>, r<1, > +// CHECK: dxsa.utof r<1, >, v<5, > +// CHECK: dxsa.add r<0>, r<0>, r<1, > +// CHECK: dxsa.utof r<1, >, v<5, > +// CHECK: dxsa.add r<0>, r<0>, r<1, > +// CHECK: dxsa.utof r<1, >, v<5, > +// CHECK: dxsa.add r<0>, r<0>, r<1, > +// CHECK: dxsa.utof r<1, >, v<5, > +// CHECK: dxsa.add r<0>, r<0>, r<1, > +// CHECK: dxsa.add r<0>, r<0>, v<6> +// CHECK: dxsa.utof r<1, >, v<7, > +// CHECK: dxsa.add r<0>, r<0>, r<1, > +// CHECK: dxsa.and r<1, >, v<7, >, l(0x3F800000) +// CHECK: dxsa.add o<0>, r<0>, r<1, > +// CHECK: dxsa.instruction "ret" + diff --git a/mlir/test/Target/DXSA/hlsl/input3.test b/mlir/test/Target/DXSA/hlsl/input3.test new file mode 100644 index 000000000000..ec87ea7e7d4b --- /dev/null +++ b/mlir/test/Target/DXSA/hlsl/input3.test @@ -0,0 +1,23 @@ +// RUN: mlir-translate --import-dxsa-bin %S/inputs/input3.bin | FileCheck %s +// NOTE: Assertions have been autogenerated by utils/generate-test-checks.py + +// This script is intended to make adding checks to a test case quick and easy. +// It is *not* authoritative about what constitutes a good test. After using the +// script, be sure to review and refine the generated checks. For example, +// CHECK lines should be minimized and named to reflect the test’s intent. +// For comprehensive guidelines, see: +// * https://mlir.llvm.org/getting_started/TestingGuide/ + + +// CHECK-LABEL: dxsa.dcl_global_flags +// CHECK: dxsa.dcl_input v<0> +// CHECK: dxsa.dcl_input_sgv v<1, >, +// CHECK: dxsa.dcl_input_sgv v<2, >, +// CHECK: dxsa.dcl_output_siv o<0>, +// CHECK: dxsa.dcl_temps 2 +// CHECK: dxsa.utof r<0, >, v<1, > +// CHECK: dxsa.add r<0>, r<0, >, v<0> +// CHECK: dxsa.utof r<1, >, v<2, > +// CHECK: dxsa.add o<0>, r<0>, r<1, > +// CHECK: dxsa.instruction "ret" + diff --git a/mlir/test/Target/DXSA/hlsl/inputs/abs1.bin b/mlir/test/Target/DXSA/hlsl/inputs/abs1.bin new file mode 100644 index 0000000000000000000000000000000000000000..d7fcd98e2a887b7fe905e0e0d9a7670c215bed43 GIT binary patch literal 64 zcmWGwU| literal 0 HcmV?d00001 diff --git a/mlir/test/Target/DXSA/hlsl/inputs/atomics.bin b/mlir/test/Target/DXSA/hlsl/inputs/atomics.bin new file mode 100644 index 0000000000000000000000000000000000000000..94dc1be85c3783f6ddcfc97fd0a11b457826821f GIT binary patch literal 1204 zcma)5OG*Pl5Pf4zXBb6777_w#bR~idw^_(6!tCAT00BWfi$@p_pdu*v1-*uAPmqNt zuqs_|oHQmq4MkV#y{^xz$r*s-1h`C*lqovJ>_j4eXFT@)HQ*EzYGsNrz9zofjt1qF zeV?l({;nBwm4_Z%m-wDph22Ljpq*f+#IPP*_@4}q#z$WMUZ|+erL#UJ1Qe%B; zQP*iu>upQ8lA~VJY5(&Xtj93dXRw=PH9s2io*VLB8uDHn^4^T6{j1iTgPQR>sB6cV Z-pc2`mgNZdwJO&HX!C#UO#4$==PxvNPyYY_ literal 0 HcmV?d00001 diff --git a/mlir/test/Target/DXSA/hlsl/inputs/bad_ftoi.bin b/mlir/test/Target/DXSA/hlsl/inputs/bad_ftoi.bin new file mode 100644 index 0000000000000000000000000000000000000000..bf7bbbe648b33357dd21d401c835a2d5ee4ce7f6 GIT binary patch literal 100 zcmWGwU}TVFU|`7VU|>vTU|{~FAOPesFvu`4usT86j1CM8|Nqz5gT$Ip#r{h(FmM<_ T#h9S#fNK8(jQ|5X1_nj|D>@R! literal 0 HcmV?d00001 diff --git a/mlir/test/Target/DXSA/hlsl/inputs/binary1.bin b/mlir/test/Target/DXSA/hlsl/inputs/binary1.bin new file mode 100644 index 0000000000000000000000000000000000000000..f60e8d31b00b85576128fc1251736e4e1dc22f2d GIT binary patch literal 212 zcmWGwU|=u>;w%mZ#v}m-W+4FqAdi6o#8yILAA+(|8GvdOAZjug7?>Ersu|dY7$9O? pP<1exj{!*zO^pQ>IVq@q6D)FCP&s3e9Mlb5P&2Kda&`<1i~vVZ2w(sJ literal 0 HcmV?d00001 diff --git a/mlir/test/Target/DXSA/hlsl/inputs/bool1.bin b/mlir/test/Target/DXSA/hlsl/inputs/bool1.bin new file mode 100644 index 0000000000000000000000000000000000000000..b683a7c5d4422f0761a444d3acf5be6aab325bab GIT binary patch literal 136 zcmX|(!3lsc6hmJXq4rcdfQn0a6WzcW1VNm_n`3LVtsg!l;Ux>u>ko@rEoJat4mPB_ nsCOugvJ0v}%v|Ccuz!X>=dTTBf>wHfI`8C;OB*k9>qg-Z3=9f4 literal 0 HcmV?d00001 diff --git a/mlir/test/Target/DXSA/hlsl/inputs/bool2.bin b/mlir/test/Target/DXSA/hlsl/inputs/bool2.bin new file mode 100644 index 0000000000000000000000000000000000000000..718789556918e80a7e616843ec93f9a813688eb4 GIT binary patch literal 124 zcmWGwU|^63;w%mZ#v}m-W+4FqAdi6o#8!f`QyGBb3J~!O1_mZZpu8ai1G^9dM2rin dP6|q!Gca(%)N?`AFgk!tWnh5N4fb|GCIFs01~32s literal 0 HcmV?d00001 diff --git a/mlir/test/Target/DXSA/hlsl/inputs/bufinfo.bin b/mlir/test/Target/DXSA/hlsl/inputs/bufinfo.bin new file mode 100644 index 0000000000000000000000000000000000000000..2f22dad777f83272bfb678083763c810b735a267 GIT binary patch literal 488 zcmWGwU|^^M;w%mZ#zhPaEDQw#Kpq2w2@o%2U|glAq9xJ84L_eAoD627}}W@Gd48Olw=TMfXKPk zL1;M!26mVj7gUbX0pccPeM(R{v3C%6VACfBRfA0q*~~*s3}Cmw%>=pyV;?oK-f21WqPuqn#` literal 0 HcmV?d00001 diff --git a/mlir/test/Target/DXSA/hlsl/inputs/calc_lod.bin b/mlir/test/Target/DXSA/hlsl/inputs/calc_lod.bin new file mode 100644 index 0000000000000000000000000000000000000000..e3cdd36a0ecfba4329931942e69bdcdc6aab2ad4 GIT binary patch literal 272 zcmWGwU|?_o;w%mZ#wZ2`W`+a-Adi6|LV|&Xp#Z`T4F&QYAbduk9GD*f;WI(`NdgSa zMFJ4@sX%i+DL~j63=B*lJvj^voI(r`F*m3>E~xo1J3(rcu&4p)hp7Rw*kR^KLDh0W eX%ziJ5W7HjfZT|zALh0&R)`ulsD3*J21Wpag%WN6 literal 0 HcmV?d00001 diff --git a/mlir/test/Target/DXSA/hlsl/inputs/call1.bin b/mlir/test/Target/DXSA/hlsl/inputs/call1.bin new file mode 100644 index 0000000000000000000000000000000000000000..932345d6a768cc984f1917c6fa849c9cad9a5701 GIT binary patch literal 280 zcmYk0F$w}P6hvQkRhCr2#?}K^TS_XcEj+`5Af9TE>P)_Y1U|gXO#b8rJT>2iv=!!a zDZ0V71Sjzu@ip`hOx9LuSy}T*oGOhEV)n>RlDa3RdwydtYr1CN+C_7RWADqvu7~v7 cu)Agcp1WbMW5yk0#((u0GwvKSv8T2@KdXHXApigX literal 0 HcmV?d00001 diff --git a/mlir/test/Target/DXSA/hlsl/inputs/call3.bin b/mlir/test/Target/DXSA/hlsl/inputs/call3.bin new file mode 100644 index 0000000000000000000000000000000000000000..99bca98dfed8d7b5b8bcc8a4a44d7974aedca614 GIT binary patch literal 456 zcmZuty9xp^5S%2Zgj9zh!ZnJeSXo%=VQt|z90+3R7u}!g4A~q(U09gR%)W91@M1nA z+|VK%+LkY1h#5QLI}jF|%s&7xZjB~%^a>w=S<%HQPJml7udGexn-ja9B=v?EWA=Jd zMI)Xx`J^Rg@k#AFRrfBz5nO*y}SzfKR>Y;z5oCK literal 0 HcmV?d00001 diff --git a/mlir/test/Target/DXSA/hlsl/inputs/cast1.bin b/mlir/test/Target/DXSA/hlsl/inputs/cast1.bin new file mode 100644 index 0000000000000000000000000000000000000000..d7352707cf90055005370ee26808af831c61e79d GIT binary patch literal 60 vcmWGwU|`?};w%mZ#v~2~W+4FqAdi6|l>x|BfUvb07+7I!E~va60|O%fZ4CnV literal 0 HcmV?d00001 diff --git a/mlir/test/Target/DXSA/hlsl/inputs/cast2.bin b/mlir/test/Target/DXSA/hlsl/inputs/cast2.bin new file mode 100644 index 0000000000000000000000000000000000000000..efd5aed0104fa3b954d8d532231fecaa3e87d706 GIT binary patch literal 60 vcmWGwU|`?};w%mZ#v~2~W+4FqAdi6|l>x|BfUv_D7+7I!E~va60|O%faTNn1 literal 0 HcmV?d00001 diff --git a/mlir/test/Target/DXSA/hlsl/inputs/cast3.bin b/mlir/test/Target/DXSA/hlsl/inputs/cast3.bin new file mode 100644 index 0000000000000000000000000000000000000000..a7cf21329e81b6d5d344122fd8c2125dca5fc3a4 GIT binary patch literal 60 vcmWGwU|`?};w%mZ#v}m-W+4FqAdi6|l>x|BfUu<*7+7I!E~va60|O%fZ3P1F literal 0 HcmV?d00001 diff --git a/mlir/test/Target/DXSA/hlsl/inputs/cast4.bin b/mlir/test/Target/DXSA/hlsl/inputs/cast4.bin new file mode 100644 index 0000000000000000000000000000000000000000..fcc0436fe3c4fd79da88921a572e65e41cd447bb GIT binary patch literal 60 vcmWGwU|`?};w%mZ#v}m-W+4FqAdi6|l>x|BfUsp47+7I!E~va60|O%fZ5;ye literal 0 HcmV?d00001 diff --git a/mlir/test/Target/DXSA/hlsl/inputs/cast5.bin b/mlir/test/Target/DXSA/hlsl/inputs/cast5.bin new file mode 100644 index 0000000000000000000000000000000000000000..dcff4610f92f69792590cf7de6c214898cb60163 GIT binary patch literal 68 zcmWGwU|)O;w%mZ#z+nZ7PmeHAdi7T0El6HMj)F5h?6)Nn1uvDG7Jo<3=GVl6d>#j z1_maO8Z!n4Rw1xX1_myuI-nRkOiZgmfd!}pwK4;2s?v;feEBuj)8$)2x^iRR2`!O0|O6G&WwS9H3=#gCIZn16ys8Ysc$e) i11bZ%M++(@1*JjiV0M+Y8mPhC29xK4s<@VW literal 0 HcmV?d00001 diff --git a/mlir/test/Target/DXSA/hlsl/inputs/cmp1.bin b/mlir/test/Target/DXSA/hlsl/inputs/cmp1.bin new file mode 100644 index 0000000000000000000000000000000000000000..39dfeeb2cf6afe4c317c7b3c8e0238a97cf5a25e GIT binary patch literal 80 zcmWGwU|vVU|{*A0OBzKMHv{(7#KKUd?p8=0D}XV1TyTSFaNQ%11bXm D%ZUeS literal 0 HcmV?d00001 diff --git a/mlir/test/Target/DXSA/hlsl/inputs/cs1.bin b/mlir/test/Target/DXSA/hlsl/inputs/cs1.bin new file mode 100644 index 0000000000000000000000000000000000000000..99614a7e9c3d6f1b2309a6c74c729281e4fead3e GIT binary patch literal 308 zcmZvXy$!-J7(|~PNFrAu9TW(qgCUSbk3>mFifR Nvbi?rdXHIxc>{7^6ZHT9 literal 0 HcmV?d00001 diff --git a/mlir/test/Target/DXSA/hlsl/inputs/cs2.bin b/mlir/test/Target/DXSA/hlsl/inputs/cs2.bin new file mode 100644 index 0000000000000000000000000000000000000000..635f3508f304304f862ee4b20eb0cc93c0ec2060 GIT binary patch literal 736 zcmaJ(0+kECgiqiT znDy-%3q@G6Zf|yWW_Rr?9N+`MCOCHu3@>*TZ-C?b1Pt(X+}>{hkK`feVw}%amCur? zTjB#UpFzRzTr=jqrqCmGB@TRra|#qC1OXyzT>?go1z#vWrH9~=_?&6uPrJHY&sCp9F{txXbL`Lf;wFdIpHry z<~OZb?wjjz@I8E=_K|5Tw^_r^^_jPztFxJj%@yOG*Vm9o5S)84m-wo9*ce2Pbmj+G%8??qm6*ylj zCpdF&R}RS?+`Ze`-PzfB7wF?1z-owW0qo6hOGZG(_YUac`=E)hfq*JN=VX-5S((m) zsU`6qEAK(VpVV{6xF*q-yd(Y(`Ksm=$O{MoB73t681P^C#PBg^2#>^1nD+YdUtj8H zuEmwGDRu3_V-@fK+&+2-Ry5Asc0J|}GuL6~Gvybymw2R2)25a`<iqIkUVi}luCuG=^9tGj xnc9O-=S(0+kECgiqiT znDy-%3q@G6Zf|yWW_Rr?9N+`MCOCHu3@>*TZ-C?b1Pt(X+}>{hkK`feVw}%amCur? zTjB#UpFzRzTr=jqrqCmGB@TRra|#qC1OXyzT>?go1z#vWrH9~=_?&6uPrJHY&sCp9F{txXbL`Lf;wFdIpHry z<~OZb?wjjz@I8E=_K|5Tw^_r^^_jPztFxJj%@yOG*Vm9TsqoEP13FKy&Kir^hv14Fh1ORxw7$pDz literal 0 HcmV?d00001 diff --git a/mlir/test/Target/DXSA/hlsl/inputs/double2.bin b/mlir/test/Target/DXSA/hlsl/inputs/double2.bin new file mode 100644 index 0000000000000000000000000000000000000000..4cc5866657553d036128e6c0b8a7d24f2b18386d GIT binary patch literal 296 zcmWGwU|{e9;w%X!#z+PR7PmeHAdi885r~sG7?_O&1i*X{`w*0!$^aBsfQV->Fff7C znlUi2eqw-#xyeE3OAHL`Mo_V5d{8+S2)&O98&<;Dj1QFmL_=MAW$953^%A= wsJe#Nfq(2_iVxti>jVP>H_QyS1_hWF2B3KjjZhxUY>+=-eshDm&kh(I0P)Qlh5!Hn literal 0 HcmV?d00001 diff --git a/mlir/test/Target/DXSA/hlsl/inputs/double3.bin b/mlir/test/Target/DXSA/hlsl/inputs/double3.bin new file mode 100644 index 0000000000000000000000000000000000000000..b17f439a704ee100a2b2068c71c8748dbafd03eb GIT binary patch literal 364 zcmZusy9&ZU5S%1Ff`x=&Ar=zy2^N-?sqO6qLHtSKf_{o0;1@XK?n($Q9J@D<+qolv z6VGjp>|CPQRTXc5<}{dvXT&c+Q8%W!0(nks4@}=MtlL`efq6|#p4Za3iFN6dbF-Cc zp47LFb*__7exBc38`mtnKL)0(hCyEExwz>Z4|*i5KiG;w%X!#v~2~W+MRsAdi6o#%4rfGXdGD3=GVl6d-Cc7#Ns9VrC2stVRqF zF*m6GlRz;cm>3I0?i7+bE~p$x?;$9gO+1ejSTjZ{l$)$WCnL!on2h9yR0y;%0ldG<#O&bX*;S*9_L7iVhqTwT`XsA)XAUn3# zc63%Ot=RR>&dz#|Er5&IevQG~1XcTOBm#zF?-P{ua%p4r2g!XQ{thUAjKh2Y1@AtA zibW$aI*eIIpLPbO^~Q+jPO(+bH0q@o)<(?zHHTr}h(VLXlo8WhzvfvC^+le?EQW6r zFkREbP%lrwps$&jzjO69+kE87Y9=O`OQNXxSyoWP?WXOF9KhTcFqc4DKbG_YhH^uD{=V1QTam5Uc4S-P zoybmzr;(i!&mwz7yi2(Tl9v3L$1CDI!bOC~4%_9oQC+%vT67$A>Y_2TQI!#N< LjP;MfIrsVpqL@B| literal 0 HcmV?d00001 diff --git a/mlir/test/Target/DXSA/hlsl/inputs/empty.bin b/mlir/test/Target/DXSA/hlsl/inputs/empty.bin new file mode 100644 index 0000000000000000000000000000000000000000..d8fa56aba81ca074f82d7b9a27273dd482484c46 GIT binary patch literal 16 VcmWGwU|?VY;w%mZMmq)uMgR%M0S5p8 literal 0 HcmV?d00001 diff --git a/mlir/test/Target/DXSA/hlsl/inputs/eval.bin b/mlir/test/Target/DXSA/hlsl/inputs/eval.bin new file mode 100644 index 0000000000000000000000000000000000000000..edd64dc2e243b1233e6c95ea2106b05c791411ae GIT binary patch literal 584 zcma)3F$%&!5S+UtCI*opRu;k92Utp~)b@4(K`ecWkMJ`p_?A4tIGgN|GoWPQ*tzWN z?9OEm;L3AOV5$s3on^cMRf6C`Yy|6f>*2t|p@$<6PdpqGA3^5y*=;N3Kh`19iD%q?dw zbmpqxf9iB^%UA0;RgUvW?NOQ=)ugwUFYj08-bMuBZTa5Q3+Kkx!yHej(vcwKB EALMj7IRF3v literal 0 HcmV?d00001 diff --git a/mlir/test/Target/DXSA/hlsl/inputs/f32f16.bin b/mlir/test/Target/DXSA/hlsl/inputs/f32f16.bin new file mode 100644 index 0000000000000000000000000000000000000000..f1db409d4daf455e77dcc61b88c72c1066a02ec5 GIT binary patch literal 148 zcmWGwU|>)M;w%mZ#v}m-=1l?uKpq1_5(fiw5s=LYWT!GPFn>~jh-WY`Ffjqeniv>Z qKQTbW*kmDe7?PM9A4IGfDh4tq4Qd{c$qq9QrVd1d)YvgFFaiJ+Gz{hd literal 0 HcmV?d00001 diff --git a/mlir/test/Target/DXSA/hlsl/inputs/gather.bin b/mlir/test/Target/DXSA/hlsl/inputs/gather.bin new file mode 100644 index 0000000000000000000000000000000000000000..378bff662fba014d149334c792e719043fa43fb7 GIT binary patch literal 680 zcmWGwU|?7U#915+j8O~>%nS(vKpq1_gaiW%Lji;x8Vck)K=_P6IWRu}!e@f=lLQ!; zKM6q8rvlCSqyS-OFfcGN1J&d*FmxYcU}$g-6=nFu0FiTps&}h{@VTIN1J(90eq(4r zRu8flUA+`kJy41rZYCepY#F5h6d+QQHD5Ukt1hio9rfglQU82SkYA_|M4$%+^)f*?kIfr`2KPyUCgf#H6ET|3iU z(X1DUlgxBaS5?0*0bERghb>HQfD&D89^iTxQ#_`3+nRlvYzqbL+ZttGr+O}eK*L literal 0 HcmV?d00001 diff --git a/mlir/test/Target/DXSA/hlsl/inputs/gather_po_cmp.bin b/mlir/test/Target/DXSA/hlsl/inputs/gather_po_cmp.bin new file mode 100644 index 0000000000000000000000000000000000000000..fdb8a860baa99f61f848bc5aca540145c9d650df GIT binary patch literal 1408 zcmb_byGjH>5Ukt17aPcOAjk=F82SkYA_^OutccMd2x8u*flfF z^$oL==p?h#(^cJ5)q4ZLO@QYmCihF!aIHjuyCY2T62ALh&X?gVso?pcMLo3PUcY(w z2#Ie({0XS$5<3QF1467jX~DcL@ct>=b$^JJ+%eWgzD{#r1Ez6dU&nikJx#FRO{_D5 z)m|#rlU}&CrkAUPkG=TZ5k8B3OR(&vg#7|OtOm98LM^7Uk7;r4_OsZKdwV%ZCMi4~6)T5E0Ym}6^F!(7c&%m1uN?Q=C#5B^&7Hlw#Ze=$gXKf?#R zo&DImdDN_nIn=DGcK?9(Pf)jtb1WEtmiZ(9ncMf@a#*kZ3`Gv>b&f-4h;`^S7h~k( z(z#Oq8KeJPns58C{`>hiZ_)oD*N5e>ex`3Jaio1Sx72r<&swE?_20f-zRUh^f>!jO JOZ~r)QoqZWYv%v} literal 0 HcmV?d00001 diff --git a/mlir/test/Target/DXSA/hlsl/inputs/getdim.bin b/mlir/test/Target/DXSA/hlsl/inputs/getdim.bin new file mode 100644 index 0000000000000000000000000000000000000000..d2cc9b1690ff34552e4ab9188aec9e0915b11b47 GIT binary patch literal 1296 zcmd5+u}T9$5Pg^Pl91{Q2qGe4VPR<*P(l>3Omj!-fFL%Cy&~874}ML)B=`Xq`2zPj z^K@C`fsMGu?ajW~nfK;qZVKQ$18(}rX4}}nT^UY*ssd(Xvjc4Q)a;JzOS5ygUwD7H z3Hi@U*Db%?hxTjbfPv&jY5M$IJ?Y!r!RYTLFfxQve?7wQ5xQ2VLRopL} ziNDrx+eguO{Rd%=Qx5BT@3-Ggv-xdC-fZrvc_ zyv@uv^WN<2z9Pa2z%GOP0^(~~BPHvI8)IjDG>!&58gNYh1`=fG1o4-?~}7DMxMOE&C_vTX?0TO(i&%XO`z2t z+I7ZovHF|4&0={n^!(2IbY(itURo~yQ2PXo{ad=n9))RXgL?j5UD@NodbVp`d2Xd{ c+k%?Vulu~l*Euus|Kn@>;C~N6{=#qh10SRwr~m)} literal 0 HcmV?d00001 diff --git a/mlir/test/Target/DXSA/hlsl/inputs/gs2.bin b/mlir/test/Target/DXSA/hlsl/inputs/gs2.bin new file mode 100644 index 0000000000000000000000000000000000000000..dcc457c55537271231fab861209b39c2ec504de1 GIT binary patch literal 848 zcmdT>!D>P=5S$lZMYI(Az?;;3LV1TG9*Xpkb58}qRw#(#@j*R{A7Fp3U*Z=y^OB{Z zmqKq{NU}Sb?9OhU;qV1u*F&)Y%5d_GfP!nq_&oHjFKi1q$McokPoM+b3dWN0MqEE^ zW4>zGf`nxbnr-U6Z)-_0HbNR}I5ir1ixwvs~i*R`-p1ugMz&-3C!xs63HqQ($l= zuG((S4fjv^3U^*$YZH`Z|KL*uJTRxU%5t9Ynz(WX&d%&3o7X<`$-g=#ZT)ms9KSRh zKFjimU!}UU#25CSu$OMsM64%$-@TcVc-p<@=;qvhm~!g9<{xfi9$^hJ{X=lEj`gKF a`_z~G5ql8-KWL@SKmDaptOA>0|Ps< RI2V!{upX#6$l`WD?EvXk2lD^` literal 0 HcmV?d00001 diff --git a/mlir/test/Target/DXSA/hlsl/inputs/hs1.bin b/mlir/test/Target/DXSA/hlsl/inputs/hs1.bin new file mode 100644 index 0000000000000000000000000000000000000000..5578ecf0ecb815da34b274dfa25892cbe2f6ebcd GIT binary patch literal 996 zcma)4Jxc>Y5Ph2u&s;P)f<=f5XUd3>DusoJ#q|~et+Wxv&a<+S;17_18e9Db`Azu= z7J{Acxw|Hj4Q60&Z*Jbqn|Zg#DB=si4Pc%IFwgXtCd`QbO21x(IR&EZu}jp{jC=Jt zA4mLNrz<{bvhLp2Z7|-Z_xnK1GbiK>DB#@S=Nv<4DNj-)%*!r-VxHRQir50b^@wRW zgkjAVXKTASPTtttR|A{OeK6K6S!+JG$1x@jo7F6)cbBe+SF^UJeJZ(oA4Rrz)|l_L zOP&XZi3eS^n6=2)f7V@n!JgX1*BR*lN}o?))MyrB7=6 zSJ_aysq3vsjq9O}Ea1cz{~B{+@(9Qx<$OK=F+S-{~nDH2nobN8}# yS8NXXpoMl0%~K*)_xnFxgpg^ut(?CN34FXZ|J3zzIk-CZW-^$gU;5;b-45&%VtC^IX6}Uk z07r!T0#`Dc4J$l1s-5}T9mbn2Tw8%nlGqOHnCBgC<8Tq=QQb98IjZWAl*dYa8DzQ)ry2HcWyz)6~?^I@fmX37asFxv|}W(dZRnzQuxV#40Nk^C2#q(Oo!06JU#*qVO0;#Yd-&E$M@{) zA3SBQmT^?P-q+`gLQktT;Ctg4@{xa!e5HeCPuf{c>Hp0ALoJn)ddKN+3=B*lwPp+qtVRqFF)>kyIza{o4k4fz$Xqu$h@9KJ2@FzD sbs%{qBzdqpG@59$t}`CL%@?HCvs0VWw4r~m)} literal 0 HcmV?d00001 diff --git a/mlir/test/Target/DXSA/hlsl/inputs/if1.bin b/mlir/test/Target/DXSA/hlsl/inputs/if1.bin new file mode 100644 index 0000000000000000000000000000000000000000..bded3406a46275d4049504cbe97dbbfb4ef4d909 GIT binary patch literal 156 zcmWGwU|>)O;w%mZ#v}m-W+MRsAdi6|iGzVz2*_pxvQrs=Yz2sT1_J{VNKAo&fnA6J uBE|(($LPQSRxi)M!psGgGh<+2h3N&U0|7grG9e&FmXkt~69vkF)Bpfo(*~gc literal 0 HcmV?d00001 diff --git a/mlir/test/Target/DXSA/hlsl/inputs/if2.bin b/mlir/test/Target/DXSA/hlsl/inputs/if2.bin new file mode 100644 index 0000000000000000000000000000000000000000..9974320bf2c876dff45e6e3e48f9dd55da76b299 GIT binary patch literal 148 zcmWGwU|>)M;w%mZ#v}m-W+MRsAdi6|iGzVz2*_pxvQrs=Yz2sT1_J{VNKAo&fnA6J pBE|(($LPQSRxi)M!psGgGh<+2h3N&U0|7grGEpE#mXkt~0{|%j22B6} literal 0 HcmV?d00001 diff --git a/mlir/test/Target/DXSA/hlsl/inputs/if3.bin b/mlir/test/Target/DXSA/hlsl/inputs/if3.bin new file mode 100644 index 0000000000000000000000000000000000000000..d5a6bfc6057a8c9acbc548eb6a7747e7821b3592 GIT binary patch literal 164 zcmWGwU|`S$;w%mZ#v}m-W+MRsAdi6|iGzVz2*_pxvQrs=Yz2sT1_J{VNKAo&fnA6J zBE|(($LPQSRxi)M!psGg11e>Q=>@3+0gyTdh6N5n5an=rDHQoxheUz$c0ddOsecH2 literal 0 HcmV?d00001 diff --git a/mlir/test/Target/DXSA/hlsl/inputs/if4.bin b/mlir/test/Target/DXSA/hlsl/inputs/if4.bin new file mode 100644 index 0000000000000000000000000000000000000000..fc9bef5b71e77752c4fb49fb7a550dec66141b90 GIT binary patch literal 212 zcmWGwU|=u>;w%mZ#v}m-W+MRsAdi6|i37rB1hP{Z7?_0=AmSMe3``&~1qKFoAqI#T z7f=sKjL`vzfwVjW3o{o~4#bv%$^)g?VdjAJfB;Aj1H%FbA&6ES@(c$=f%52TK<0t~ N#Ee;oKx*uO7ywkQ3Z(!5 literal 0 HcmV?d00001 diff --git a/mlir/test/Target/DXSA/hlsl/inputs/if5.bin b/mlir/test/Target/DXSA/hlsl/inputs/if5.bin new file mode 100644 index 0000000000000000000000000000000000000000..6269bec1d997e3fb8ca858b429810565e1d9a8e5 GIT binary patch literal 228 zcmWGwU|_HW;w%mZ#v}m-W+MRsAdi6|iGzW;2*_pxvQrrtn1vJ|;u#DKOdv4@1_pK^ z28b9JR2`!O16aL00}C@3R1UY+d9tMU54nh#EIOG`)hyvw7YCz^` VVKEP62M9pSn{^1J9)#_H7yv9p3vd7c literal 0 HcmV?d00001 diff --git a/mlir/test/Target/DXSA/hlsl/inputs/indexableinput1.bin b/mlir/test/Target/DXSA/hlsl/inputs/indexableinput1.bin new file mode 100644 index 0000000000000000000000000000000000000000..0c93b6b5bf6d6046894dca2471f6117c3b548205 GIT binary patch literal 220 zcmYk0I|{=v5Cup6DyoD_SH@)y5O*$eg7oPE2IJHENPZhjpasF`G5gpLu;?8g_lwl; z81)0=SzIL^#7)6%!Ck?Z#*vu8w%CfUo>-cGtxqv`t9DI%jfs+(t0-_d;z`w4@&?5 literal 0 HcmV?d00001 diff --git a/mlir/test/Target/DXSA/hlsl/inputs/indexableoutput1.bin b/mlir/test/Target/DXSA/hlsl/inputs/indexableoutput1.bin new file mode 100644 index 0000000000000000000000000000000000000000..4a61ef0eec9cb0e124e3bea4880710f6d42e7920 GIT binary patch literal 96 zcmWGwU}TVBU|`7NU|@`AU|<#!5CHNR7*c`kPYMDIOh9%z0|N_)%?@NU0yWTTvR(yV|zE=Ka8jxyb`mE& z0C>=D1(IWd-u~$s0W;dEKvtC{67y^G&tTq{qTvFh!mmJ2u|6`z%BL2ufqsRy##tZc zifZM_XrH_LZx3fY;=_Qe7x7$7kpgEy_htNi+GLgYdr`v3SN7NIpwk8VCRY literal 0 HcmV?d00001 diff --git a/mlir/test/Target/DXSA/hlsl/inputs/indexabletemp3.bin b/mlir/test/Target/DXSA/hlsl/inputs/indexabletemp3.bin new file mode 100644 index 0000000000000000000000000000000000000000..e893855267b65ddf0ba508b2cfeb9c6b965e0a02 GIT binary patch literal 228 zcmWGwU|_HW;w%mZ#z+nZ7PmeHAdi882Z)n67?_0w1Q-~hY$Yf=l>sQOAOKRvkio#f z1d`8WU|<39K?De!F)*+SF+kLCLG=N}ID`xofU*$4)t~^@!v$3bl;?!WgUkfVvw>8C Y6d|dBn=6GdmmTIFE(26E?HCvs0e`9rY5)KL literal 0 HcmV?d00001 diff --git a/mlir/test/Target/DXSA/hlsl/inputs/indexabletemp5.bin b/mlir/test/Target/DXSA/hlsl/inputs/indexabletemp5.bin new file mode 100644 index 0000000000000000000000000000000000000000..4b2fd600f96fb942be9500ffeeabe3124830ce32 GIT binary patch literal 256 zcmWGwU|?_n;w%nE#z+nZ7PmeHAdi882Z)n67?_0w1Q-~hY$Yf=m4SgpNI{^1(E%s{ z1Q`qrOdvIxKyeTsM1Zgv0|ToNg8)c~feWe^D8?mZpa9nkmTORGftkexRS#6hjjRr2 gK39W68%!O@d?dASd!!Kda3Z^r%K+03I|c?u0A!R8zyJUM literal 0 HcmV?d00001 diff --git a/mlir/test/Target/DXSA/hlsl/inputs/input1.bin b/mlir/test/Target/DXSA/hlsl/inputs/input1.bin new file mode 100644 index 0000000000000000000000000000000000000000..c2c7b0d13f682c5f487695ecde844487b835690d GIT binary patch literal 788 zcmb7CI|{-;6r43Ni59X5HWnh5+E`ntSXf)x3VuL5g?KkFloL3UeTiaH=t9DqH}k%` zI{;69x6HYtN0fU{1RS$qyAQi1+aspt?$$s=d?xNQCZ;W3cw$(*@`!KKK4pQEok~l* zF;4Nq55v-&$3-n9wAF{=l}oW*!>T3R;dfvQZr;L$t>xn|$CWj|eWm3tG@JB#v%r1DUs}G8t=)UM!zE=e Dx2-bf literal 0 HcmV?d00001 diff --git a/mlir/test/Target/DXSA/hlsl/inputs/input2.bin b/mlir/test/Target/DXSA/hlsl/inputs/input2.bin new file mode 100644 index 0000000000000000000000000000000000000000..8ca576aca6548987d57fa43c5d0328fac3480500 GIT binary patch literal 788 zcmb7CI|{-;6r43Ni59X5HWnh5dIJj;3u`M|!4HV12%f~tc%huY8TTcMNudh~Z{E!N z?rs4*_+2yS4jxhAJrQuog6%%+mTZrhn%u2`i1QzXIgMYnkkD2iidQbhb`7hRaEITXEx3CNXSP<1!yFg-)YlAX7YM%1$iMQ@ zomRfyo1-5))2puZ%E43DGfo{~UuoUKWl7_Xiy zt?ltw{qRry^iTc#2Ypko+P&`odp6xUPkpDh3+^i|ccIy&*P8|MC4Xu8J~npmzpI*Eg$h+p702!i3m79p$K7#%fxOQA4R~Q^Aa=;i4+M)teSKBE(wr7>M_}_cu6Ln&z$*00 z4(x1nXY}7wD071p-fz-VDl@NV&z2)T)66Gba`x0t>Z@j%V%pI=<<|MHc`xKY?D7j@ literal 0 HcmV?d00001 diff --git a/mlir/test/Target/DXSA/hlsl/inputs/loop3.bin b/mlir/test/Target/DXSA/hlsl/inputs/loop3.bin new file mode 100644 index 0000000000000000000000000000000000000000..ab3a7ff8983c45d1418b9927b2e05b0cf9428ec7 GIT binary patch literal 536 zcmZ8eF$%&!5S-+q##AAoMGB3Usl>v&w^5V7oxA#zNb-n7ED%nB1vN7yCN z3fnQg0cLN*dwVOZ6HtVsVO_$jh#P%A&YBBe_4^ucT137u@8!PSgXW?Z-mgtO zsGoB3;5>PC588-4IM3%NJk%3!>_<8G%5d0$c*}U7cofg+O!hAXD;Jjid4K-w zB)I^1az6rGU&2>q$tR!>@K@H3^$p}rODOnhss8R-_r_C@=#Bi4!~^3UdH-U#GG{= zwK}CyHfdCgNgMvSTi;+c(v5xImWLWQk5Q)S{f{ZD{ezTW_y6XvIV<1vU()P}{0k`% B5#ay; literal 0 HcmV?d00001 diff --git a/mlir/test/Target/DXSA/hlsl/inputs/loop5.bin b/mlir/test/Target/DXSA/hlsl/inputs/loop5.bin new file mode 100644 index 0000000000000000000000000000000000000000..a6d087f6e17ad5d82a4afade47f77b9c213bfa6e GIT binary patch literal 364 zcma)0y9xp^5S(0;gsZ}V78aVbyvoYLLJz+{Z0!Pq_!)k=lgk_&qF`Xz&Fnn(0^r7a zdYBYon-KT|l83!=Hk|Ju9t-{es*LS{d4qy=;t}&nSk;sC@pgb|0rwhp>b3M1GkXvg zC%jsi=^0ATAv>1rm3F5;w2s=%g!j$o$Qu_dQr%YGV@AF+zcqJf?K<^*TNW+Ze)+xu DpWY5l literal 0 HcmV?d00001 diff --git a/mlir/test/Target/DXSA/hlsl/inputs/minprec1.bin b/mlir/test/Target/DXSA/hlsl/inputs/minprec1.bin new file mode 100644 index 0000000000000000000000000000000000000000..1ef9e51833ef2220d7f589410825ba066571a226 GIT binary patch literal 112 zcmWGwU|^5|;w%nE#v}m-79jzF21W;<01%`yFfa=#2!Poc3=B++U={O7{>|DdYW4bWyTr@Q&KN|G}|lvB2JH`n<~{7tAeFMNjPyx}~EFJM`DGXKh1 HuXsHGy9@}u literal 0 HcmV?d00001 diff --git a/mlir/test/Target/DXSA/hlsl/inputs/minprec4.bin b/mlir/test/Target/DXSA/hlsl/inputs/minprec4.bin new file mode 100644 index 0000000000000000000000000000000000000000..0b807b7e6d7d2b3aa0359cc760741c76a3566ddd GIT binary patch literal 112 zcmWGwU|^5|;w%nE#v~2~79jzF21W-)pa=s)Dgy(vkb(f1ox#As1QL~FVBi#DK&atD bQqSnX!0`9~|NmwT3~VrcTu5r|7#J7TE~q+)`~n9%1_nj| D(dz|( literal 0 HcmV?d00001 diff --git a/mlir/test/Target/DXSA/hlsl/inputs/minprec6.bin b/mlir/test/Target/DXSA/hlsl/inputs/minprec6.bin new file mode 100644 index 0000000000000000000000000000000000000000..ab971d956e9b18e5f4e548a859274b50f969343a GIT binary patch literal 252 zcmaivK?=e!6hz-|qqJFtfLqNex@=v!cI&oK5Kqw)cx9ags@e6!@bj6+Fu4Ph^yD{2>r>~Bsvjl!ht1Dj@}IJIlJfonVb>86 literal 0 HcmV?d00001 diff --git a/mlir/test/Target/DXSA/hlsl/inputs/minprec7.bin b/mlir/test/Target/DXSA/hlsl/inputs/minprec7.bin new file mode 100644 index 0000000000000000000000000000000000000000..2c872521fce27a019feb32849500a07bc9a3566c GIT binary patch literal 104 zcmWGwU|^5};w%nE#v}m-W+4FqAdi6|l>x|BfUq+d7?>Erq6{2D3<3>|4iF9(R4s(R Tz`=}xfeogI3rU?F0|O%fRAB~b literal 0 HcmV?d00001 diff --git a/mlir/test/Target/DXSA/hlsl/inputs/neg1.bin b/mlir/test/Target/DXSA/hlsl/inputs/neg1.bin new file mode 100644 index 0000000000000000000000000000000000000000..8dec73dcd9f4a87feb5b0127e269de6b78b441a5 GIT binary patch literal 64 zcmWGwU|UU7Q@H2xfOEh?5iw;@~HA^i%x6eu4KTDJ=;+UfxM^ zPkRIKV7&_{_S}7roPY&u>36{0Lc2cjj7+ndCLFc}veH^Vv^MM&rw+)5D)1NMB<}#M zN(5%&n-keSVOL-?kV#G+&s<-9mH#RRlW!x(bK>F{`7Uuu7MH%vT*6c>7&V<%oU(o< Z^weo4XD;{VK8||)U$>6$*~M|D<`0-I6$JnQ literal 0 HcmV?d00001 diff --git a/mlir/test/Target/DXSA/hlsl/inputs/output1.bin b/mlir/test/Target/DXSA/hlsl/inputs/output1.bin new file mode 100644 index 0000000000000000000000000000000000000000..8b904ef399f3f7d4cfa3d2360b24404f119092ef GIT binary patch literal 260 zcmX|*I}QRd3X9D*3SK=pfchzlms(B1wctMQf8>EryW$#zq&z>#)own7{yxx49 lyKz691$<7r{(aNB`qppm0XmzT{XcPP`!%;^wr9(Z5Pk(r5}*J8 literal 0 HcmV?d00001 diff --git a/mlir/test/Target/DXSA/hlsl/inputs/output2.bin b/mlir/test/Target/DXSA/hlsl/inputs/output2.bin new file mode 100644 index 0000000000000000000000000000000000000000..900c2c261ab034123955a37b191dd85c5a1ff2c1 GIT binary patch literal 164 zcmWGwU|`S$;w%mZ#v}m-=1&3wKpq1FjLisSr!oM=6(Hg;HY-G&i7|nRA%lT|38W4P r*gr8q)VawaXpo#40|N_4Ef-WC$Y+I_>Ba|93ljsG4HL6tU|<9QR$>mh literal 0 HcmV?d00001 diff --git a/mlir/test/Target/DXSA/hlsl/inputs/output3.bin b/mlir/test/Target/DXSA/hlsl/inputs/output3.bin new file mode 100644 index 0000000000000000000000000000000000000000..89c44a7ece25b537d34f11766dbc863ebf87c5bc GIT binary patch literal 148 zcmWGwU|>)M;w%nE#v}m-=1&3wKpq1_Dg%(MfXZfth%+%3FoES6ConZIIxsSrF)*-z j#JHe(Wf&M(VRA4rpc+<~d2VtLb75j2b75k33=E6_pji%n literal 0 HcmV?d00001 diff --git a/mlir/test/Target/DXSA/hlsl/inputs/output4.bin b/mlir/test/Target/DXSA/hlsl/inputs/output4.bin new file mode 100644 index 0000000000000000000000000000000000000000..97548c16810d5370e8e765c8c966dd85e7c76856 GIT binary patch literal 188 zcmWGwU}Vr|U|`7NU}TJEU|{|vAOPesFr+guuzXU0uo)qIRv`s}21W-4pbnrysG208 z8W5ie!e=#tssZsqYRniISYhV4$wABmim@S^#Rat!q!wl#n=nExvYFFFA>wvGX8-`? C&JK$J literal 0 HcmV?d00001 diff --git a/mlir/test/Target/DXSA/hlsl/inputs/passthrough1.bin b/mlir/test/Target/DXSA/hlsl/inputs/passthrough1.bin new file mode 100644 index 0000000000000000000000000000000000000000..604c3c190a49d9aadb79832f24d3ee4feee4e227 GIT binary patch literal 64 zcmWGwU}O+rU|`7NU|@`AU|{|v0OBz)q%$zEd{Th08G(E=1_o9b-%So8ZpXmD2msT@ B1?K<& literal 0 HcmV?d00001 diff --git a/mlir/test/Target/DXSA/hlsl/inputs/passthrough2.bin b/mlir/test/Target/DXSA/hlsl/inputs/passthrough2.bin new file mode 100644 index 0000000000000000000000000000000000000000..24f313fef19aa131b33730a4b20fe73093b473cc GIT binary patch literal 60 xcmWGwU|`?};w%mZ#v}m-W+MRsAdi6|m4SizlLCZo#=yV|W3!1s#OxRt7y+V*1nK|) literal 0 HcmV?d00001 diff --git a/mlir/test/Target/DXSA/hlsl/inputs/precise1.bin b/mlir/test/Target/DXSA/hlsl/inputs/precise1.bin new file mode 100644 index 0000000000000000000000000000000000000000..9386b54e9057df9be041ab61335636a65e78cb82 GIT binary patch literal 236 zcmWGwU|_HY;w%mZ#z+PR7PmeHAdi888Hl4mRDuAQA0ffO!cYKVhlVmRBndDu8wo)8 zsX%p~6d>#j1_mZZpbl4tita-U3=Phqq70uHAaZU{^=@?#KFn+jh6)b28a}96s5?NG l8!=RHeKkZs0L!3J}S8=pXfBgg3%M5QWD!{=xY(mMB0J5oJmj6ck{&a82b0Kte)Pkwrs;tWY633M2{&3j7Fp zfILE;0J%s(LE$1b=eu`i?`nk;DI?jtch1>4GqZd5zB02}+w9$-)%t1HvD1+}WJy7j0X8`u@mfjtzb6xrUYw zm-3<4^L6d19&Ghef0|A8tK$c6E=Blxe6&@L5g%;s@pBIAJHj3ZXH(a?Q0{>d8&1A% zEB-zCPGa5PW?f+O!k`RO5#xZeR<=fFtWq#6Q&JYFKN1>n3b4bBz4qtIkwYu1UT}!lPI7kBw$v z)B;D=UwT~54%&>44bB|Pwa^DI_laO*$I3nUqcch@42<=h+e`QLl#g4V9N8!Jv~rOv zdC3xXebiuZcjdxfqF3#ypNBFRFmm}Cx$HN&Ov+sR`L4O7bKtp@c~j?D8uaHx<6ZM! zmU(MW>65JLA#uwd(gU=R=*SY5YnIqrXC7m}1Ec@U=NftU z7z3lm3iCTJ?p4u}96d>#j1_mZZpqMKIL-!#Dh6d+QQ3fLhh@2Z#y;~i`9GKZag5{pU%1Q-sYnv6Z5uY?oJPq@>tW| zavIF?>e!Z_$v#8Ta;$&P@rG|_wx^Y1l-!)|{g*$_{mCbG=-%`vf5G!Vtl_)AHkca? C{Ws?T literal 0 HcmV?d00001 diff --git a/mlir/test/Target/DXSA/hlsl/inputs/sample_b1.bin b/mlir/test/Target/DXSA/hlsl/inputs/sample_b1.bin new file mode 100644 index 0000000000000000000000000000000000000000..877652d94dbba21a1e460f48168dfbd22bb8ab34 GIT binary patch literal 644 zcmWGwU|?7X#915+j8O~>%nS(v46HzYgaiW%LxBKLfPo=2lz|}$$TSiV0P+|ZQi19| zDL~j63=B*lHC_x1y@wbW8k|E#89p&Uecv zpb~bt9ehx`fHX+&a|VWqj24(?GF%{RE~5j`00stoAjW6@Bw#>cxLFA3XC|OVLT-oJ z0kQ|D9j_P|SV882{KEw`Hw;Y-BnJc-X0So^0mFeJcXC1F2%8;l(6A=SoeGF}0y!M! JPCEt$MgV>hIVu1E literal 0 HcmV?d00001 diff --git a/mlir/test/Target/DXSA/hlsl/inputs/sample_cmp1.bin b/mlir/test/Target/DXSA/hlsl/inputs/sample_cmp1.bin new file mode 100644 index 0000000000000000000000000000000000000000..32b19175e83d357515369737661a764191cf06c7 GIT binary patch literal 712 zcma))u}T9$6h+S@*=$I)2!aHQU}(LO`tY3Hbp9{S-gJFYq_Cw6OMF zcWx9-SQmz!x$nI*cjnC{@D$^AK$;EcGOs9NeYHoAWfcO{HC)H^sH$QG3+TR&oB0iN zdS5E#4vjX~H8e+@}v#t~ z?{S!GM*05=59#=uDep;Ve1SGU=}d{7##r;sm1l8+|CnZf`P!!w@qg~IkrU;JqrSCq z+^0z0>h&%9U|@yILDhs|5p!o?=sm>1(BK>@%Af>Q=LR){ ztpMT{nESY(@<2U(jNcd>!yFlR!6NC8=*$kK%%nXnm%)RL5gXCcGy^ISI$86BB JvSVOi1OQ_FB^>|& literal 0 HcmV?d00001 diff --git a/mlir/test/Target/DXSA/hlsl/inputs/sample_grad1.bin b/mlir/test/Target/DXSA/hlsl/inputs/sample_grad1.bin new file mode 100644 index 0000000000000000000000000000000000000000..97ecdcba24cbc9cbd852a805d38473367bdfd927 GIT binary patch literal 684 zcmb`E%L+kJ6o$X;o`Ft^49_zd8KKlEGm|43Nhuk50(k?9x9}F8z+=eJz}UY#+a(7b zW!G+B)>_}cElxi_2n=57Tt{BX$5WuKjrH` M=4T7I<=X^v1@i$rs{jB1 literal 0 HcmV?d00001 diff --git a/mlir/test/Target/DXSA/hlsl/inputs/sample_l1.bin b/mlir/test/Target/DXSA/hlsl/inputs/sample_l1.bin new file mode 100644 index 0000000000000000000000000000000000000000..5a2a94195b6824f8bc1740b092a9e731ae5a92a5 GIT binary patch literal 840 zcmcgpI|{-;6r8L^MMQ!ih=t?~R#p-af@PYBScxErl_!v3@8?V&!82G{rm%K4yK6#J zQYaR?$@|Q_eKP@o3(vX+YX+1scVIJ~c2LH~VFCz4#(|1uO~wnBV#i?wEQyO<^}hmy z#EgOc8Hh$<8!=SP*Zuxh@tRp(ohRmC-4SJR7P*RWY^gqHH1#ZgB{tz4{Fd_yoG8}I zJ6qgSeEHrRU>lyg=9|39z1z8>`}4I#L#<1;X8L_ylb-EF>RE#8X+7zg^gi!dA82H? lml)ykg2y{OW(Ku8=4Y6F{eoE}{pj;wbaRy!dEJJ9^#F9{Ne2J` literal 0 HcmV?d00001 diff --git a/mlir/test/Target/DXSA/hlsl/inputs/samplecount.bin b/mlir/test/Target/DXSA/hlsl/inputs/samplecount.bin new file mode 100644 index 0000000000000000000000000000000000000000..f0206d87e99d7711e958e30a69dd73ffd38d753f GIT binary patch literal 76 zcmWGwU|6S>F`mT2+Ot@A4z=(Ap1^s&1*GsL zyTi;d!($0x%d?5$RT%>8Q!=0|foh@LbG%OBKU4Krfd9_=&+^_HFork*!UNQQjTCo4 zd~#ZJR4s9w5s06YOHaW)1jl_ps+;@+n0DTv?Hy`w6lk8EQQLV3Jj=z|%lVrTPcky+ wQ1RyYjQ^EqsukV$6VbkVJIz>0UwF&WVK%_Q9> zF)pY&Mh6B4U!a^8P)-Sp95YZ(4oROBObwI{MbamQWF`jzeIU1>+ouK9kIz1A?j%MZ SHg}@vQ-FjEy8rAL7#IP20u2@b literal 0 HcmV?d00001 diff --git a/mlir/test/Target/DXSA/hlsl/inputs/sincos.bin b/mlir/test/Target/DXSA/hlsl/inputs/sincos.bin new file mode 100644 index 0000000000000000000000000000000000000000..2ebbf25c01fc02c4ec02d5540487474553d9dccb GIT binary patch literal 188 zcmX|(y9t0W6h%)|qF6|907-4*29|b$8(1n%>nxeTm%PO4{toxRumDeoIiU{DNrDTS z;ME(+H&k_6Xh*c4Gh1{ATQ*+kGbeo;#K)hgmFPCen@QDE;=LS{pRtGT`W*1DYvkMDD5l}57 dP(QL-kex8KKo&d9E;l}ixyu+Kdh8e&7y&+j6cPXc literal 0 HcmV?d00001 diff --git a/mlir/test/Target/DXSA/hlsl/inputs/srv_ms_load1.bin b/mlir/test/Target/DXSA/hlsl/inputs/srv_ms_load1.bin new file mode 100644 index 0000000000000000000000000000000000000000..40ce56d6d799b1f770cbef66a4deb216ec426adf GIT binary patch literal 756 zcmWGwU|`q_#915+j1dY9EDQw#49q}&Xea|i5(fjbk$?b@2VpxQu|eXDK=D)t2Ie9K zh?)!r1|}Aum>B~Ds}Tc4%nhmzD8_LJD#qjhRD=ff7#O;l7#SLzLq!>iV0!tWX4FC4 z#OMIg1T!CGKgfI#fSC^xV{!lzXaL=OCZN0fb3Rs&3eGV(1*<|A)x<3aX^myUID|t2^xM}P;pV4HA3UYgmr$BNTsVQd?a1pMob2 z@3a5axC57O8cllD`}uyzKflk@KH`?drLSVYAG|;K9_o|dnw>TGFx40z`&VqAUn^$Y bcX#^2q%VI?-(mVPV)qZoze4(|jey_3Z5I|oNU4w{(1$!^BjRz1vu(eIZS`fs_6UesWA?+>q1kR8|WCN3#$-H^w z0Bj|09&_@HxCfl{F~Zs7>JX%Z3%Gun>MK}f8hGxY+s6exX;x*veI(BtUjK}dy;@i+ rdC0C{Ry^%I`RqnO(EArUQ_ly+>e70eoyWnO&g4wW-;1}(duuRXl>!w) literal 0 HcmV?d00001 diff --git a/mlir/test/Target/DXSA/hlsl/inputs/struct_buf1.bin b/mlir/test/Target/DXSA/hlsl/inputs/struct_buf1.bin new file mode 100644 index 0000000000000000000000000000000000000000..3b32d4ccdff91f1b601ade7a564f010ce01440f0 GIT binary patch literal 4392 zcmb`LziVVw6vxlZB=04&zmib{u8Ry)xoZ;!Sw%!25eBhQEandwP{eAP&PJA4s*S~h zjl~M1wSU4E*8T}gA{G`FQ`kxTe(t>|oVy`Op&jzEtEN46^<4?^7>v3NH+^m0q0kh%M^4hH6`VGq; zyr2IVo4sPTeU2;mpUuAM|I~Z<^$#!Gld?7}eXmJsR{fFVidgIrYsBtoJ}Y~O*rN_C z(N-PUrLg^$-50TY@@x!iVFxYj80_EAVkg3i`U~+MYVI+dntkUyu(xf=M(Sy|OYeNR z{ip+X*hi4+=)hg{gXbE=)qy93;TtC(0GV3eO8vo>CHOw)tu4Q{J zgY)@z-e=XzvUh^syvq9YU|*Gtm?Bri{qNb?+1(<8ALkJnJh@(5M!avD?Yd1kggf+T z*uhtfmp#A*c|o=*-mzjjDmJkdZAUIAlC^VjDBIP8i(JA1Tw({l(Anhw^-=@mz`69g zMA!EjW0`iuBB;$uED?JmEHP0ZUIVG#N)1U=|0)@0;L(kYo$chfk$qo$tvt`W8B2`L z3HK=ar{Nx2YYk>b`rTJg-rT>YHv1~`reQsm4E+Pu8GD{-j`Xim-*AZ!?BEwX@;}8h zecLZM{EpN|zhK=jwuzsZunm?PI@TC}UJK4!+Xr}jyr4e%7;El6q7GPUnf|4g&Y|XB zNA0+e$^U&yk_Cp zbERRuly0i6I@_Q1bIxM@z%dx`9!GUO`>a%N_y$jIz+pd~4dE9Wr?XS;sFmd{v_KZl$v8t2gS;&~*0;=|~X!3}$* zRoWxZJ%3&xn@R@$GuhS_aS#N2FC0k88L7s$j|d)c%BS9Msi8p6#u+~GpVHW0moIb!TDfLPT-$7s7;S2@a4VH`Z{nA8<~=q~FOkehck1^Ibb%{^Er?|JU*|x>E&?Z}5ymrOUdoBL_nWW+Qel<+b zBx;st5siC|xmr434BF>Q?-}W?!S1kpcl8>OO>?K@FUiVYf6+I=^lAQ9h7)8NuUgZb m24>lT;rwx~X#Nd`KKZ1P7ymy6=bzT)j~t-KGl%|Nh43GGKT(zd literal 0 HcmV?d00001 diff --git a/mlir/test/Target/DXSA/hlsl/inputs/sub1.bin b/mlir/test/Target/DXSA/hlsl/inputs/sub1.bin new file mode 100644 index 0000000000000000000000000000000000000000..dfd6de95476f36833a9454a9fbddbe8057e17f9e GIT binary patch literal 400 zcmZ8dI}XAy41G;dDVeG+NK82Z0~2G_sS^V$D*_2PMNiN(aK@g1_nJl+A~~`BKDKfO zaAUkG6c=FCkC7EnFs?OxQ`d8S2mBOM{s5ftC;0*^hLRJXFhpkQl++Ym%87ftlitxj zWAe$Ea$$jyd#vZ)mc1iTHb@>jGl%_k-mPz=RzX;JEp>Y{o7~NGh@!|BuH%J)_cyFY dJ87=fl*^x3p1kaS_8-^})c@?|IPw3;?*mIN8JqwB literal 0 HcmV?d00001 diff --git a/mlir/test/Target/DXSA/hlsl/inputs/switch1.bin b/mlir/test/Target/DXSA/hlsl/inputs/switch1.bin new file mode 100644 index 0000000000000000000000000000000000000000..8ad7ed348c397833a5207422e7f5a6736415954b GIT binary patch literal 196 zcmYk0K?;B{3%y)vKP`LTN69sc`c GmHq(0NC<}j literal 0 HcmV?d00001 diff --git a/mlir/test/Target/DXSA/hlsl/inputs/switch2.bin b/mlir/test/Target/DXSA/hlsl/inputs/switch2.bin new file mode 100644 index 0000000000000000000000000000000000000000..563dbbc39848d542ab8a9f7afabc1752a521448a GIT binary patch literal 304 zcmZ{fO$x#=5QV=q{*>q<6h!F8;1OK7lpMf?XDA5bsXRiD=u0|XX#)c<@0-b+Jb=6E z-QtFb?_$&qh8BO3cG6Ger^$aoQ#{T1V0s$Vu%Hs`31w2-qG^9wm;-*QS$_?we!&T(e;=U{u@lrXaj8&r4rb#VUqDyET!{-zo~%pc$T?G=43eLrhub~(~>!H|2{kNB&P X>_6n@K56z4dx%f$p?_#~za9BEQDzdn literal 0 HcmV?d00001 diff --git a/mlir/test/Target/DXSA/hlsl/inputs/swizzle1.bin b/mlir/test/Target/DXSA/hlsl/inputs/swizzle1.bin new file mode 100644 index 0000000000000000000000000000000000000000..5b022cf6866f3c84e3743248ad9d8f6c4faeb101 GIT binary patch literal 168 zcmWGwU|`S!;w%mZ#v}m-<{|+BAdi6o#J&V%GeX%$KsFPQoyx$#{7C_#CWC>22_z2$ y?4KAQVr*g%`k639FS48)A4JYg5MmZkjtgcMOpeI`C<+D*_CU%3h#c$~7#IP}5e>iq literal 0 HcmV?d00001 diff --git a/mlir/test/Target/DXSA/hlsl/inputs/temp1.bin b/mlir/test/Target/DXSA/hlsl/inputs/temp1.bin new file mode 100644 index 0000000000000000000000000000000000000000..87446dfcef511e89d80c4d4ed9d39ecfdac71c07 GIT binary patch literal 128 zcmWGwU|>)H;w%mZ#v}m-=1&3wKpq1FjLisSr!oM=6(Hgn3=B*lF(6?7!~hXe3u*uW literal 0 HcmV?d00001 diff --git a/mlir/test/Target/DXSA/hlsl/inputs/temp2.bin b/mlir/test/Target/DXSA/hlsl/inputs/temp2.bin new file mode 100644 index 0000000000000000000000000000000000000000..043878a3be5ac55920a54047a4e757c96ece4a44 GIT binary patch literal 128 zcmWGwU|>)H;w%mZ#v~2~=1&3wKpq1FjLisSr!oM=6(Hgn3=B*lF*ybX_D>8DF*i8` d4VB}9sdwXp$T2wpH30!go(YJVf!Gen1ppx>3LO9d literal 0 HcmV?d00001 diff --git a/mlir/test/Target/DXSA/hlsl/inputs/uav_counter_dec.bin b/mlir/test/Target/DXSA/hlsl/inputs/uav_counter_dec.bin new file mode 100644 index 0000000000000000000000000000000000000000..e8ce92c606d84efc895c22f5e1a1c120160072ab GIT binary patch literal 60 zcmWGwU|`?};w%mZ#(4}4EDR3>fjkBV0U*v`U|?bd(wi9=ScSkMKn_&ij)8#@0J-G_ AYXATM literal 0 HcmV?d00001 diff --git a/mlir/test/Target/DXSA/hlsl/inputs/uav_counter_inc.bin b/mlir/test/Target/DXSA/hlsl/inputs/uav_counter_inc.bin new file mode 100644 index 0000000000000000000000000000000000000000..8baa63b91e9c6c4c636e6f8b1e345435bc18f151 GIT binary patch literal 60 zcmWGwU|`?};w%mZ#(4}4EDR3>fjkBV0U*v`U|?bd(wi6g(%nT0%fdm6X5(fjbkbnS?1z{^e*{MJ^pA;bC84L_eOhEai z3=Exzm>3$GXG$^%F+k+Fpz7J6=7ljZu)^h_Y928#biwp7Twnm}WdxdsuJ;vCuM*5$ zAPrIjG7lyu1(h>mVBq-#Wrwjs+`;4kRLsBtBH@?~szwItCXjhnP%$&07|efed=N91 WF)*-yg8D-W<}aXnkUl#G21Wpq_Z!s! literal 0 HcmV?d00001 diff --git a/mlir/test/Target/DXSA/hlsl/inputs/uav_typed_load_store1.bin b/mlir/test/Target/DXSA/hlsl/inputs/uav_typed_load_store1.bin new file mode 100644 index 0000000000000000000000000000000000000000..a3068362bf87eae891fbe9a5c832fd1be10045f8 GIT binary patch literal 352 zcmWGwU|@&<;w%mZ#yJuUEDR3>8JL0m&`<`3Bn}2~jh-WY` zFfjq;7c($)9%5i;4%6?(2bBZTAhiz} z7`k9~FkE0@5CYnR&5TzJ46HCYE~uI?EMi6s3_LKq*r4i|9Do)vFn~xnhPh)2$ZgQ@ Vf%^^WMl+!KurPtCw_{*n1OQomCSU*n literal 0 HcmV?d00001 diff --git a/mlir/test/Target/DXSA/hlsl/inputs/uav_typed_load_store2.bin b/mlir/test/Target/DXSA/hlsl/inputs/uav_typed_load_store2.bin new file mode 100644 index 0000000000000000000000000000000000000000..0e1476bbd04877464158a4d1e31e329127159831 GIT binary patch literal 456 zcmWGwU|=W$;w%nE#yK1eEDR3>8JK~5V`Bz}Bn}2}&jC{pb2CsFmNH FBLKkEFb4nt literal 0 HcmV?d00001 diff --git a/mlir/test/Target/DXSA/hlsl/inputs/ubfeu16.bin b/mlir/test/Target/DXSA/hlsl/inputs/ubfeu16.bin new file mode 100644 index 0000000000000000000000000000000000000000..e38cb085a32557c0a00a5fc455c939e474a8f01e GIT binary patch literal 224 zcmWGwU|_HS;w%nE#z+PR7PmeHAdi885r|WPd?5va21W-EkAWeBfq@Cc>SAEv5n@1y zGdeIZNCU+|G%JwiYEXdd0dhfRaVa6G$B+l=`}6<*|8Sr>WOKQY^hhDG +// CHECK: dxsa.dcl_constant_buffer , +// CHECK: dxsa.unknown +// CHECK: dxsa.unknown +// CHECK: dxsa.unknown +// CHECK: dxsa.unknown +// CHECK: dxsa.unknown +// CHECK: dxsa.dcl_output o<0, > +// CHECK: dxsa.dcl_temps 2 +// CHECK: %[[INDEX_0:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_0:.*]] = dxsa.operand %[[INDEX_0]] {mask = 16 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_1:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[INDEX_2:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_1:.*]] = dxsa.operand %[[INDEX_1]], %[[INDEX_2]] {num_components = 4 : i32, one = 0 : i32, type = 8 : i32} +// CHECK: dxsa.instruction "mov" %[[OPERAND_0]], %[[OPERAND_1]] +// CHECK: dxsa.unknown +// CHECK: %[[INDEX_3:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_2:.*]] = dxsa.operand %[[INDEX_3]] {mask = 16 : i32, num_components = 4 : i32, type = 2 : i32} +// CHECK: %[[INDEX_4:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_3:.*]] = dxsa.operand %[[INDEX_4]] {num_components = 4 : i32, one = 1 : i32, type = 0 : i32} +// CHECK: dxsa.instruction "mov" %[[OPERAND_2]], %[[OPERAND_3]] +// CHECK: dxsa.instruction "ret" +// CHECK: %[[INDEX_5:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_4:.*]] = dxsa.operand %[[INDEX_5]] {num_components = 0 : i32, type = 17 : i32} +// CHECK: dxsa.instruction "label" %[[OPERAND_4]] +// CHECK: %[[INDEX_6:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_5:.*]] = dxsa.operand %[[INDEX_6]] {mask = 192 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_7:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_6:.*]] = dxsa.operand %[[INDEX_7]] {num_components = 4 : i32, one = 0 : i32, type = 0 : i32} +// CHECK: %[[INDEX_8:.*]] = dxsa.index.rel %[[OPERAND_6]] +// CHECK: %[[OPERAND_7:.*]] = dxsa.operand %[[INDEX_8]] {num_components = 4 : i32, swizzle = dense<[2, 2, 2, 3]> : vector<4xi32>, type = 29 : i32} +// CHECK: dxsa.instruction "mov" %[[OPERAND_5]], %[[OPERAND_7]] +// CHECK: dxsa.unknown +// CHECK: %[[INDEX_9:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_8:.*]] = dxsa.operand %[[INDEX_9]] {mask = 128 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_10:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_9:.*]] = dxsa.operand %[[INDEX_10]] {num_components = 4 : i32, one = 0 : i32, type = 0 : i32} +// CHECK: %[[INDEX_11:.*]] = dxsa.index.rel %[[OPERAND_9]] +// CHECK: %[[OPERAND_10:.*]] = dxsa.operand %[[INDEX_11]] {num_components = 4 : i32, one = 1 : i32, type = 29 : i32} +// CHECK: dxsa.instruction "mov" %[[OPERAND_8]], %[[OPERAND_10]] +// CHECK: %[[INDEX_12:.*]] = dxsa.index.imm {imm = 1 : i32} +// CHECK: %[[OPERAND_11:.*]] = dxsa.operand %[[INDEX_12]] {mask = 16 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_13:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_12:.*]] = dxsa.operand %[[INDEX_13]] {num_components = 4 : i32, one = 0 : i32, type = 0 : i32} +// CHECK: %[[INDEX_14:.*]] = dxsa.index.rel %[[OPERAND_12]] +// CHECK: %[[OPERAND_13:.*]] = dxsa.operand %[[INDEX_14]] {num_components = 4 : i32, one = 0 : i32, type = 29 : i32} +// CHECK: dxsa.instruction "mov" %[[OPERAND_11]], %[[OPERAND_13]] +// CHECK: dxsa.add r<0, >, r<0, >, cb<[r<1, >, r<0, >], vector, > +// CHECK: dxsa.instruction "ret" +// CHECK: %[[INDEX_15:.*]] = dxsa.index.imm {imm = 1 : i32} +// CHECK: %[[OPERAND_14:.*]] = dxsa.operand %[[INDEX_15]] {num_components = 0 : i32, type = 17 : i32} +// CHECK: dxsa.instruction "label" %[[OPERAND_14]] +// CHECK: %[[INDEX_16:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_15:.*]] = dxsa.operand %[[INDEX_16]] {mask = 192 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_17:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_16:.*]] = dxsa.operand %[[INDEX_17]] {num_components = 4 : i32, one = 0 : i32, type = 0 : i32} +// CHECK: %[[INDEX_18:.*]] = dxsa.index.rel %[[OPERAND_16]] +// CHECK: %[[OPERAND_17:.*]] = dxsa.operand %[[INDEX_18]] {num_components = 4 : i32, swizzle = dense<[2, 2, 2, 3]> : vector<4xi32>, type = 29 : i32} +// CHECK: dxsa.instruction "mov" %[[OPERAND_15]], %[[OPERAND_17]] +// CHECK: dxsa.unknown +// CHECK: %[[INDEX_19:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_18:.*]] = dxsa.operand %[[INDEX_19]] {mask = 128 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_20:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_19:.*]] = dxsa.operand %[[INDEX_20]] {num_components = 4 : i32, one = 0 : i32, type = 0 : i32} +// CHECK: %[[INDEX_21:.*]] = dxsa.index.rel %[[OPERAND_19]] +// CHECK: %[[OPERAND_20:.*]] = dxsa.operand %[[INDEX_21]] {num_components = 4 : i32, one = 1 : i32, type = 29 : i32} +// CHECK: dxsa.instruction "mov" %[[OPERAND_18]], %[[OPERAND_20]] +// CHECK: %[[INDEX_22:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_21:.*]] = dxsa.operand %[[INDEX_22]] {mask = 16 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_23:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_22:.*]] = dxsa.operand %[[INDEX_23]] {num_components = 4 : i32, one = 0 : i32, type = 0 : i32} +// CHECK: %[[INDEX_24:.*]] = dxsa.index.rel %[[OPERAND_22]] +// CHECK: %[[OPERAND_23:.*]] = dxsa.operand %[[INDEX_24]] {num_components = 4 : i32, one = 0 : i32, type = 29 : i32} +// CHECK: dxsa.instruction "mov" %[[OPERAND_21]], %[[OPERAND_23]] +// CHECK: dxsa.mul r<0, >, r<0, >, cb<[r<0, >, r<0, >], vector, > +// CHECK: dxsa.instruction "ret" + diff --git a/mlir/test/Target/DXSA/hlsl/liveness1.test b/mlir/test/Target/DXSA/hlsl/liveness1.test new file mode 100644 index 000000000000..30e5c7a14d3e --- /dev/null +++ b/mlir/test/Target/DXSA/hlsl/liveness1.test @@ -0,0 +1,28 @@ +// RUN: mlir-translate --import-dxsa-bin %S/inputs/liveness1.bin | FileCheck %s +// NOTE: Assertions have been autogenerated by utils/generate-test-checks.py + +// This script is intended to make adding checks to a test case quick and easy. +// It is *not* authoritative about what constitutes a good test. After using the +// script, be sure to review and refine the generated checks. For example, +// CHECK lines should be minimized and named to reflect the test’s intent. +// For comprehensive guidelines, see: +// * https://mlir.llvm.org/getting_started/TestingGuide/ + + +// CHECK-LABEL: dxsa.dcl_global_flags +// CHECK: dxsa.dcl_input_ps linear v<0> +// CHECK: dxsa.dcl_input_ps constant v<1, > +// CHECK: dxsa.dcl_output o<0, > +// CHECK: dxsa.dcl_temps 1 +// CHECK: dxsa.dp2 r<0, >, v<0, >, v<0, > +// CHECK: dxsa.ieq r<0, >, v<1, >, l(0x1) +// CHECK: %[[INDEX_0:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_0:.*]] = dxsa.operand %[[INDEX_0]] {num_components = 4 : i32, one = 1 : i32, type = 0 : i32} +// CHECK: dxsa.instruction "if" %[[OPERAND_0]] +// CHECK: dxsa.add r<0, >, r<0, >, l(0x42300000) +// CHECK: dxsa.instruction "else" +// CHECK: dxsa.add r<0, >, v<0, >, l(0xC29A0000) +// CHECK: dxsa.instruction "endif" +// CHECK: dxsa.mul o<0, >, r<0, >, r<0, > +// CHECK: dxsa.instruction "ret" + diff --git a/mlir/test/Target/DXSA/hlsl/loop1.test b/mlir/test/Target/DXSA/hlsl/loop1.test new file mode 100644 index 000000000000..4612de44172a --- /dev/null +++ b/mlir/test/Target/DXSA/hlsl/loop1.test @@ -0,0 +1,40 @@ +// RUN: mlir-translate --import-dxsa-bin %S/inputs/loop1.bin | FileCheck %s +// NOTE: Assertions have been autogenerated by utils/generate-test-checks.py + +// This script is intended to make adding checks to a test case quick and easy. +// It is *not* authoritative about what constitutes a good test. After using the +// script, be sure to review and refine the generated checks. For example, +// CHECK lines should be minimized and named to reflect the test’s intent. +// For comprehensive guidelines, see: +// * https://mlir.llvm.org/getting_started/TestingGuide/ + + +// CHECK-LABEL: dxsa.dcl_global_flags +// CHECK: dxsa.dcl_input_ps linear v<0, > +// CHECK: dxsa.dcl_input_ps constant v<1, > +// CHECK: dxsa.dcl_output o<0, > +// CHECK: dxsa.dcl_temps 1 +// CHECK: %[[INDEX_0:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_0:.*]] = dxsa.operand %[[INDEX_0]] {mask = 48 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[OPERAND_1:.*]] = dxsa.operand.imm {imm = dense<0> : vector<4xi32>} +// CHECK: dxsa.instruction "mov" %[[OPERAND_0]], %[[OPERAND_1]] +// CHECK: dxsa.instruction "loop" +// CHECK: dxsa.ige r<0, >, r<0, >, v<1, > +// CHECK: %[[INDEX_1:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_2:.*]] = dxsa.operand %[[INDEX_1]] {num_components = 4 : i32, one = 2 : i32, type = 0 : i32} +// CHECK: dxsa.instruction "breakc" %[[OPERAND_2]] +// CHECK: dxsa.add r<0, >, r<0, >, v<0, > +// CHECK: %[[INDEX_2:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_3:.*]] = dxsa.operand %[[INDEX_2]] {mask = 32 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_3:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_4:.*]] = dxsa.operand %[[INDEX_3]] {num_components = 4 : i32, one = 1 : i32, type = 0 : i32} +// CHECK: %[[OPERAND_5:.*]] = dxsa.operand.imm {imm = dense<1> : vector<1xi32>} +// CHECK: dxsa.instruction "iadd" %[[OPERAND_3]], %[[OPERAND_4]], %[[OPERAND_5]] +// CHECK: dxsa.instruction "endloop" +// CHECK: %[[INDEX_4:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_6:.*]] = dxsa.operand %[[INDEX_4]] {mask = 16 : i32, num_components = 4 : i32, type = 2 : i32} +// CHECK: %[[INDEX_5:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_7:.*]] = dxsa.operand %[[INDEX_5]] {num_components = 4 : i32, one = 0 : i32, type = 0 : i32} +// CHECK: dxsa.instruction "mov" %[[OPERAND_6]], %[[OPERAND_7]] +// CHECK: dxsa.instruction "ret" + diff --git a/mlir/test/Target/DXSA/hlsl/loop2.test b/mlir/test/Target/DXSA/hlsl/loop2.test new file mode 100644 index 000000000000..0136db8f5777 --- /dev/null +++ b/mlir/test/Target/DXSA/hlsl/loop2.test @@ -0,0 +1,56 @@ +// RUN: mlir-translate --import-dxsa-bin %S/inputs/loop2.bin | FileCheck %s +// NOTE: Assertions have been autogenerated by utils/generate-test-checks.py + +// This script is intended to make adding checks to a test case quick and easy. +// It is *not* authoritative about what constitutes a good test. After using the +// script, be sure to review and refine the generated checks. For example, +// CHECK lines should be minimized and named to reflect the test’s intent. +// For comprehensive guidelines, see: +// * https://mlir.llvm.org/getting_started/TestingGuide/ + + +// CHECK-LABEL: dxsa.dcl_global_flags +// CHECK: dxsa.dcl_input_ps linear v<0, > +// CHECK: dxsa.dcl_input_ps constant v<1, > +// CHECK: dxsa.dcl_output o<0, > +// CHECK: dxsa.dcl_temps 1 +// CHECK: %[[INDEX_0:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_0:.*]] = dxsa.operand %[[INDEX_0]] {mask = 48 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[OPERAND_1:.*]] = dxsa.operand.imm {imm = dense<0> : vector<4xi32>} +// CHECK: dxsa.instruction "mov" %[[OPERAND_0]], %[[OPERAND_1]] +// CHECK: %[[INDEX_1:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_2:.*]] = dxsa.operand %[[INDEX_1]] {mask = 64 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_2:.*]] = dxsa.index.imm {imm = 1 : i32} +// CHECK: %[[OPERAND_3:.*]] = dxsa.operand %[[INDEX_2]] {num_components = 4 : i32, one = 1 : i32, type = 1 : i32} +// CHECK: dxsa.instruction "mov" %[[OPERAND_2]], %[[OPERAND_3]] +// CHECK: dxsa.instruction "loop" +// CHECK: dxsa.ige r<0, >, r<0, >, v<1, > +// CHECK: %[[INDEX_3:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_4:.*]] = dxsa.operand %[[INDEX_3]] {num_components = 4 : i32, one = 3 : i32, type = 0 : i32} +// CHECK: dxsa.instruction "breakc" %[[OPERAND_4]] +// CHECK: %[[INDEX_4:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_5:.*]] = dxsa.operand %[[INDEX_4]] {num_components = 4 : i32, one = 2 : i32, type = 0 : i32} +// CHECK: dxsa.instruction "if" %[[OPERAND_5]] +// CHECK: dxsa.add r<0, >, r<0, >, l(0x43480000) +// CHECK: %[[INDEX_5:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_6:.*]] = dxsa.operand %[[INDEX_5]] {mask = 16 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_6:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_7:.*]] = dxsa.operand %[[INDEX_6]] {num_components = 4 : i32, one = 3 : i32, type = 0 : i32} +// CHECK: dxsa.instruction "mov" %[[OPERAND_6]], %[[OPERAND_7]] +// CHECK: dxsa.instruction "break" +// CHECK: dxsa.instruction "endif" +// CHECK: dxsa.add r<0, >, r<0, >, v<0, > +// CHECK: %[[INDEX_7:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_8:.*]] = dxsa.operand %[[INDEX_7]] {mask = 32 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_8:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_9:.*]] = dxsa.operand %[[INDEX_8]] {num_components = 4 : i32, one = 1 : i32, type = 0 : i32} +// CHECK: %[[OPERAND_10:.*]] = dxsa.operand.imm {imm = dense<1> : vector<1xi32>} +// CHECK: dxsa.instruction "iadd" %[[OPERAND_8]], %[[OPERAND_9]], %[[OPERAND_10]] +// CHECK: dxsa.instruction "endloop" +// CHECK: %[[INDEX_9:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_11:.*]] = dxsa.operand %[[INDEX_9]] {mask = 16 : i32, num_components = 4 : i32, type = 2 : i32} +// CHECK: %[[INDEX_10:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_12:.*]] = dxsa.operand %[[INDEX_10]] {num_components = 4 : i32, one = 0 : i32, type = 0 : i32} +// CHECK: dxsa.instruction "mov" %[[OPERAND_11]], %[[OPERAND_12]] +// CHECK: dxsa.instruction "ret" + diff --git a/mlir/test/Target/DXSA/hlsl/loop3.test b/mlir/test/Target/DXSA/hlsl/loop3.test new file mode 100644 index 000000000000..03f073538a2c --- /dev/null +++ b/mlir/test/Target/DXSA/hlsl/loop3.test @@ -0,0 +1,101 @@ +// RUN: mlir-translate --import-dxsa-bin %S/inputs/loop3.bin | FileCheck %s +// NOTE: Assertions have been autogenerated by utils/generate-test-checks.py + +// This script is intended to make adding checks to a test case quick and easy. +// It is *not* authoritative about what constitutes a good test. After using the +// script, be sure to review and refine the generated checks. For example, +// CHECK lines should be minimized and named to reflect the test’s intent. +// For comprehensive guidelines, see: +// * https://mlir.llvm.org/getting_started/TestingGuide/ + + +// CHECK-LABEL: dxsa.dcl_global_flags +// CHECK: dxsa.dcl_input_ps linear v<0, > +// CHECK: dxsa.dcl_input_ps constant v<1, > +// CHECK: dxsa.dcl_output o<0, > +// CHECK: dxsa.dcl_temps 3 +// CHECK: %[[INDEX_0:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_0:.*]] = dxsa.operand %[[INDEX_0]] {mask = 16 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[OPERAND_1:.*]] = dxsa.operand.imm {imm = dense<16> : vector<1xi32>} +// CHECK: dxsa.instruction "mov" %[[OPERAND_0]], %[[OPERAND_1]] +// CHECK: %[[INDEX_1:.*]] = dxsa.index.imm {imm = 1 : i32} +// CHECK: %[[OPERAND_2:.*]] = dxsa.operand %[[INDEX_1]] {mask = 16 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_2:.*]] = dxsa.index.imm {imm = 1 : i32} +// CHECK: %[[OPERAND_3:.*]] = dxsa.operand %[[INDEX_2]] {num_components = 4 : i32, one = 2 : i32, type = 1 : i32} +// CHECK: dxsa.instruction "mov" %[[OPERAND_2]], %[[OPERAND_3]] +// CHECK: %[[INDEX_3:.*]] = dxsa.index.imm {imm = 1 : i32} +// CHECK: %[[OPERAND_4:.*]] = dxsa.operand %[[INDEX_3]] {mask = 32 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[OPERAND_5:.*]] = dxsa.operand.imm {imm = dense<0> : vector<1xi32>} +// CHECK: dxsa.instruction "mov" %[[OPERAND_4]], %[[OPERAND_5]] +// CHECK: %[[INDEX_4:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_6:.*]] = dxsa.operand %[[INDEX_4]] {mask = 64 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[OPERAND_7:.*]] = dxsa.operand.imm {imm = dense<0> : vector<1xi32>} +// CHECK: dxsa.instruction "mov" %[[OPERAND_6]], %[[OPERAND_7]] +// CHECK: dxsa.instruction "loop" +// CHECK: dxsa.ige r<0, >, r<0, >, v<1, > +// CHECK: %[[INDEX_5:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_8:.*]] = dxsa.operand %[[INDEX_5]] {num_components = 4 : i32, one = 3 : i32, type = 0 : i32} +// CHECK: dxsa.instruction "breakc" %[[OPERAND_8]] +// CHECK: dxsa.ieq r<0, >, r<1, >, l(0x9) +// CHECK: %[[INDEX_6:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_9:.*]] = dxsa.operand %[[INDEX_6]] {num_components = 4 : i32, one = 3 : i32, type = 0 : i32} +// CHECK: dxsa.instruction "if" %[[OPERAND_9]] +// CHECK: dxsa.instruction "break" +// CHECK: dxsa.instruction "endif" +// CHECK: %[[INDEX_7:.*]] = dxsa.index.imm {imm = 1 : i32} +// CHECK: %[[OPERAND_10:.*]] = dxsa.operand %[[INDEX_7]] {mask = 192 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_8:.*]] = dxsa.index.imm {imm = 1 : i32} +// CHECK: %[[OPERAND_11:.*]] = dxsa.operand %[[INDEX_8]] {num_components = 4 : i32, swizzle = dense<[0, 0, 0, 1]> : vector<4xi32>, type = 0 : i32} +// CHECK: dxsa.instruction "mov" %[[OPERAND_10]], %[[OPERAND_11]] +// CHECK: %[[INDEX_9:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_12:.*]] = dxsa.operand %[[INDEX_9]] {mask = 128 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[OPERAND_13:.*]] = dxsa.operand.imm {imm = dense<0> : vector<1xi32>} +// CHECK: dxsa.instruction "mov" %[[OPERAND_12]], %[[OPERAND_13]] +// CHECK: dxsa.instruction "loop" +// CHECK: dxsa.ige r<2, >, r<0, >, v<1, > +// CHECK: %[[INDEX_10:.*]] = dxsa.index.imm {imm = 2 : i32} +// CHECK: %[[OPERAND_14:.*]] = dxsa.operand %[[INDEX_10]] {num_components = 4 : i32, one = 0 : i32, type = 0 : i32} +// CHECK: dxsa.instruction "breakc" %[[OPERAND_14]] +// CHECK: dxsa.ieq r<2, >, r<1, >, l(0x10) +// CHECK: %[[INDEX_11:.*]] = dxsa.index.imm {imm = 2 : i32} +// CHECK: %[[OPERAND_15:.*]] = dxsa.operand %[[INDEX_11]] {num_components = 4 : i32, one = 0 : i32, type = 0 : i32} +// CHECK: dxsa.instruction "if" %[[OPERAND_15]] +// CHECK: %[[INDEX_12:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_16:.*]] = dxsa.operand %[[INDEX_12]] {mask = 32 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_13:.*]] = dxsa.index.imm {imm = 1 : i32} +// CHECK: %[[OPERAND_17:.*]] = dxsa.operand %[[INDEX_13]] {num_components = 4 : i32, one = 3 : i32, type = 0 : i32} +// CHECK: dxsa.instruction "mov" %[[OPERAND_16]], %[[OPERAND_17]] +// CHECK: %[[INDEX_14:.*]] = dxsa.index.imm {imm = 1 : i32} +// CHECK: %[[OPERAND_18:.*]] = dxsa.operand %[[INDEX_14]] {mask = 192 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_15:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_19:.*]] = dxsa.operand %[[INDEX_15]] {num_components = 4 : i32, swizzle = dense<[0, 0, 0, 1]> : vector<4xi32>, type = 0 : i32} +// CHECK: dxsa.instruction "mov" %[[OPERAND_18]], %[[OPERAND_19]] +// CHECK: dxsa.instruction "break" +// CHECK: dxsa.instruction "endif" +// CHECK: dxsa.add r<1, >, r<1, >, v<0, > +// CHECK: %[[INDEX_16:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_20:.*]] = dxsa.operand %[[INDEX_16]] {mask = 128 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_17:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_21:.*]] = dxsa.operand %[[INDEX_17]] {num_components = 4 : i32, one = 3 : i32, type = 0 : i32} +// CHECK: %[[OPERAND_22:.*]] = dxsa.operand.imm {imm = dense<1> : vector<1xi32>} +// CHECK: dxsa.instruction "iadd" %[[OPERAND_20]], %[[OPERAND_21]], %[[OPERAND_22]] +// CHECK: dxsa.instruction "endloop" +// CHECK: %[[INDEX_18:.*]] = dxsa.index.imm {imm = 1 : i32} +// CHECK: %[[OPERAND_23:.*]] = dxsa.operand %[[INDEX_18]] {mask = 48 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_19:.*]] = dxsa.index.imm {imm = 1 : i32} +// CHECK: %[[OPERAND_24:.*]] = dxsa.operand %[[INDEX_19]] {num_components = 4 : i32, swizzle = dense<[2, 3, 2, 2]> : vector<4xi32>, type = 0 : i32} +// CHECK: dxsa.instruction "mov" %[[OPERAND_23]], %[[OPERAND_24]] +// CHECK: %[[INDEX_20:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_25:.*]] = dxsa.operand %[[INDEX_20]] {mask = 64 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_21:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_26:.*]] = dxsa.operand %[[INDEX_21]] {num_components = 4 : i32, one = 2 : i32, type = 0 : i32} +// CHECK: %[[OPERAND_27:.*]] = dxsa.operand.imm {imm = dense<1> : vector<1xi32>} +// CHECK: dxsa.instruction "iadd" %[[OPERAND_25]], %[[OPERAND_26]], %[[OPERAND_27]] +// CHECK: dxsa.instruction "endloop" +// CHECK: %[[INDEX_22:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_28:.*]] = dxsa.operand %[[INDEX_22]] {mask = 16 : i32, num_components = 4 : i32, type = 2 : i32} +// CHECK: %[[INDEX_23:.*]] = dxsa.index.imm {imm = 1 : i32} +// CHECK: %[[OPERAND_29:.*]] = dxsa.operand %[[INDEX_23]] {num_components = 4 : i32, one = 1 : i32, type = 0 : i32} +// CHECK: dxsa.instruction "mov" %[[OPERAND_28]], %[[OPERAND_29]] +// CHECK: dxsa.instruction "ret" + diff --git a/mlir/test/Target/DXSA/hlsl/loop4.test b/mlir/test/Target/DXSA/hlsl/loop4.test new file mode 100644 index 000000000000..ddc0a2fb933b --- /dev/null +++ b/mlir/test/Target/DXSA/hlsl/loop4.test @@ -0,0 +1,88 @@ +// RUN: mlir-translate --import-dxsa-bin %S/inputs/loop4.bin | FileCheck %s +// NOTE: Assertions have been autogenerated by utils/generate-test-checks.py + +// This script is intended to make adding checks to a test case quick and easy. +// It is *not* authoritative about what constitutes a good test. After using the +// script, be sure to review and refine the generated checks. For example, +// CHECK lines should be minimized and named to reflect the test’s intent. +// For comprehensive guidelines, see: +// * https://mlir.llvm.org/getting_started/TestingGuide/ + + +// CHECK-LABEL: dxsa.dcl_global_flags +// CHECK: dxsa.dcl_input_ps linear v<0, > +// CHECK: dxsa.dcl_input_ps constant v<1, > +// CHECK: dxsa.dcl_output o<0, > +// CHECK: dxsa.dcl_temps 3 +// CHECK: %[[INDEX_0:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_0:.*]] = dxsa.operand %[[INDEX_0]] {mask = 96 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[OPERAND_1:.*]] = dxsa.operand.imm {imm = dense<[0, 5, 7, 0]> : vector<4xi32>} +// CHECK: dxsa.instruction "mov" %[[OPERAND_0]], %[[OPERAND_1]] +// CHECK: %[[INDEX_1:.*]] = dxsa.index.imm {imm = 1 : i32} +// CHECK: %[[OPERAND_2:.*]] = dxsa.operand %[[INDEX_1]] {mask = 32 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_2:.*]] = dxsa.index.imm {imm = 1 : i32} +// CHECK: %[[OPERAND_3:.*]] = dxsa.operand %[[INDEX_2]] {num_components = 4 : i32, one = 2 : i32, type = 1 : i32} +// CHECK: dxsa.instruction "mov" %[[OPERAND_2]], %[[OPERAND_3]] +// CHECK: %[[INDEX_3:.*]] = dxsa.index.imm {imm = 1 : i32} +// CHECK: %[[OPERAND_4:.*]] = dxsa.operand %[[INDEX_3]] {mask = 16 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[OPERAND_5:.*]] = dxsa.operand.imm {imm = dense<0> : vector<1xi32>} +// CHECK: dxsa.instruction "mov" %[[OPERAND_4]], %[[OPERAND_5]] +// CHECK: %[[INDEX_4:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_6:.*]] = dxsa.operand %[[INDEX_4]] {mask = 128 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[OPERAND_7:.*]] = dxsa.operand.imm {imm = dense<0> : vector<1xi32>} +// CHECK: dxsa.instruction "mov" %[[OPERAND_6]], %[[OPERAND_7]] +// CHECK: dxsa.instruction "loop" +// CHECK: dxsa.ige r<1, >, r<1, >, v<1, > +// CHECK: %[[INDEX_5:.*]] = dxsa.index.imm {imm = 1 : i32} +// CHECK: %[[OPERAND_8:.*]] = dxsa.operand %[[INDEX_5]] {num_components = 4 : i32, one = 2 : i32, type = 0 : i32} +// CHECK: dxsa.instruction "breakc" %[[OPERAND_8]] +// CHECK: dxsa.ieq r<1, >, r<1, >, l(0x5) +// CHECK: %[[INDEX_6:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_9:.*]] = dxsa.operand %[[INDEX_6]] {mask = 16 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_7:.*]] = dxsa.index.imm {imm = 1 : i32} +// CHECK: %[[OPERAND_10:.*]] = dxsa.operand %[[INDEX_7]] {num_components = 4 : i32, one = 0 : i32, type = 0 : i32} +// CHECK: %[[OPERAND_11:.*]] = dxsa.operand.imm {imm = dense<1> : vector<1xi32>} +// CHECK: dxsa.instruction "iadd" %[[OPERAND_9]], %[[OPERAND_10]], %[[OPERAND_11]] +// CHECK: %[[INDEX_8:.*]] = dxsa.index.imm {imm = 2 : i32} +// CHECK: %[[OPERAND_12:.*]] = dxsa.operand %[[INDEX_8]] {mask = 48 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_9:.*]] = dxsa.index.imm {imm = 1 : i32} +// CHECK: %[[OPERAND_13:.*]] = dxsa.operand %[[INDEX_9]] {num_components = 4 : i32, swizzle = dense<2> : vector<4xi32>, type = 0 : i32} +// CHECK: %[[INDEX_10:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_14:.*]] = dxsa.operand %[[INDEX_10]] {num_components = 4 : i32, swizzle = dense<[1, 0, 1, 1]> : vector<4xi32>, type = 0 : i32} +// CHECK: %[[INDEX_11:.*]] = dxsa.index.imm {imm = 1 : i32} +// CHECK: %[[OPERAND_15:.*]] = dxsa.operand %[[INDEX_11]] {num_components = 4 : i32, swizzle = dense<[1, 0, 1, 1]> : vector<4xi32>, type = 0 : i32} +// CHECK: dxsa.instruction "movc" %[[OPERAND_12]], %[[OPERAND_13]], %[[OPERAND_14]], %[[OPERAND_15]] +// CHECK: %[[INDEX_12:.*]] = dxsa.index.imm {imm = 1 : i32} +// CHECK: %[[OPERAND_16:.*]] = dxsa.operand %[[INDEX_12]] {mask = 48 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_13:.*]] = dxsa.index.imm {imm = 2 : i32} +// CHECK: %[[OPERAND_17:.*]] = dxsa.operand %[[INDEX_13]] {num_components = 4 : i32, swizzle = dense<[1, 0, 1, 1]> : vector<4xi32>, type = 0 : i32} +// CHECK: dxsa.instruction "mov" %[[OPERAND_16]], %[[OPERAND_17]] +// CHECK: %[[INDEX_14:.*]] = dxsa.index.imm {imm = 1 : i32} +// CHECK: %[[OPERAND_18:.*]] = dxsa.operand %[[INDEX_14]] {num_components = 4 : i32, one = 2 : i32, type = 0 : i32} +// CHECK: dxsa.instruction "continuec" %[[OPERAND_18]] +// CHECK: dxsa.ieq r<1, >, r<1, >, l(0x7) +// CHECK: %[[INDEX_15:.*]] = dxsa.index.imm {imm = 1 : i32} +// CHECK: %[[OPERAND_19:.*]] = dxsa.operand %[[INDEX_15]] {num_components = 4 : i32, one = 2 : i32, type = 0 : i32} +// CHECK: dxsa.instruction "if" %[[OPERAND_19]] +// CHECK: %[[INDEX_16:.*]] = dxsa.index.imm {imm = 1 : i32} +// CHECK: %[[OPERAND_20:.*]] = dxsa.operand %[[INDEX_16]] {mask = 48 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_17:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_21:.*]] = dxsa.operand %[[INDEX_17]] {num_components = 4 : i32, swizzle = dense<[0, 2, 0, 0]> : vector<4xi32>, type = 0 : i32} +// CHECK: dxsa.instruction "mov" %[[OPERAND_20]], %[[OPERAND_21]] +// CHECK: dxsa.instruction "continue" +// CHECK: dxsa.instruction "endif" +// CHECK: dxsa.add r<0, >, r<0, >, v<0, > +// CHECK: %[[INDEX_18:.*]] = dxsa.index.imm {imm = 1 : i32} +// CHECK: %[[OPERAND_22:.*]] = dxsa.operand %[[INDEX_18]] {mask = 16 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_19:.*]] = dxsa.index.imm {imm = 1 : i32} +// CHECK: %[[OPERAND_23:.*]] = dxsa.operand %[[INDEX_19]] {num_components = 4 : i32, one = 0 : i32, type = 0 : i32} +// CHECK: %[[OPERAND_24:.*]] = dxsa.operand.imm {imm = dense<1> : vector<1xi32>} +// CHECK: dxsa.instruction "iadd" %[[OPERAND_22]], %[[OPERAND_23]], %[[OPERAND_24]] +// CHECK: dxsa.instruction "endloop" +// CHECK: %[[INDEX_20:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_25:.*]] = dxsa.operand %[[INDEX_20]] {mask = 16 : i32, num_components = 4 : i32, type = 2 : i32} +// CHECK: %[[INDEX_21:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_26:.*]] = dxsa.operand %[[INDEX_21]] {num_components = 4 : i32, one = 3 : i32, type = 0 : i32} +// CHECK: dxsa.instruction "mov" %[[OPERAND_25]], %[[OPERAND_26]] +// CHECK: dxsa.instruction "ret" + diff --git a/mlir/test/Target/DXSA/hlsl/loop5.test b/mlir/test/Target/DXSA/hlsl/loop5.test new file mode 100644 index 000000000000..bbf63e1a11dd --- /dev/null +++ b/mlir/test/Target/DXSA/hlsl/loop5.test @@ -0,0 +1,65 @@ +// RUN: mlir-translate --import-dxsa-bin %S/inputs/loop5.bin | FileCheck %s +// NOTE: Assertions have been autogenerated by utils/generate-test-checks.py + +// This script is intended to make adding checks to a test case quick and easy. +// It is *not* authoritative about what constitutes a good test. After using the +// script, be sure to review and refine the generated checks. For example, +// CHECK lines should be minimized and named to reflect the test’s intent. +// For comprehensive guidelines, see: +// * https://mlir.llvm.org/getting_started/TestingGuide/ + + +// CHECK-LABEL: dxsa.dcl_global_flags +// CHECK: dxsa.dcl_input_ps linear v<0, > +// CHECK: dxsa.dcl_input_ps constant v<1, > +// CHECK: dxsa.dcl_output o<0, > +// CHECK: dxsa.dcl_temps 1 +// CHECK: %[[INDEX_0:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_0:.*]] = dxsa.operand %[[INDEX_0]] {mask = 16 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_1:.*]] = dxsa.index.imm {imm = 1 : i32} +// CHECK: %[[OPERAND_1:.*]] = dxsa.operand %[[INDEX_1]] {num_components = 4 : i32, one = 2 : i32, type = 1 : i32} +// CHECK: dxsa.instruction "mov" %[[OPERAND_0]], %[[OPERAND_1]] +// CHECK: %[[INDEX_2:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_2:.*]] = dxsa.operand %[[INDEX_2]] {mask = 96 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[OPERAND_3:.*]] = dxsa.operand.imm {imm = dense<0> : vector<4xi32>} +// CHECK: dxsa.instruction "mov" %[[OPERAND_2]], %[[OPERAND_3]] +// CHECK: dxsa.instruction "loop" +// CHECK: dxsa.ige r<0, >, r<0, >, v<1, > +// CHECK: %[[INDEX_3:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_4:.*]] = dxsa.operand %[[INDEX_3]] {num_components = 4 : i32, one = 3 : i32, type = 0 : i32} +// CHECK: dxsa.instruction "breakc" %[[OPERAND_4]] +// CHECK: dxsa.ieq r<0, >, r<0, >, l(0x5) +// CHECK: %[[INDEX_4:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_5:.*]] = dxsa.operand %[[INDEX_4]] {mask = 16 : i32, num_components = 4 : i32, type = 2 : i32} +// CHECK: %[[INDEX_5:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_6:.*]] = dxsa.operand %[[INDEX_5]] {num_components = 4 : i32, one = 1 : i32, type = 0 : i32} +// CHECK: dxsa.instruction "mov" %[[OPERAND_5]], %[[OPERAND_6]] +// CHECK: %[[INDEX_6:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_7:.*]] = dxsa.operand %[[INDEX_6]] {num_components = 4 : i32, one = 3 : i32, type = 0 : i32} +// CHECK: dxsa.instruction "retc" %[[OPERAND_7]] +// CHECK: dxsa.ieq r<0, >, r<0, >, l(0x7) +// CHECK: %[[INDEX_7:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_8:.*]] = dxsa.operand %[[INDEX_7]] {num_components = 4 : i32, one = 3 : i32, type = 0 : i32} +// CHECK: dxsa.instruction "if" %[[OPERAND_8]] +// CHECK: %[[INDEX_8:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_9:.*]] = dxsa.operand %[[INDEX_8]] {mask = 16 : i32, num_components = 4 : i32, type = 2 : i32} +// CHECK: %[[INDEX_9:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_10:.*]] = dxsa.operand %[[INDEX_9]] {num_components = 4 : i32, one = 1 : i32, type = 0 : i32} +// CHECK: dxsa.instruction "mov" %[[OPERAND_9]], %[[OPERAND_10]] +// CHECK: dxsa.instruction "ret" +// CHECK: dxsa.instruction "endif" +// CHECK: dxsa.add r<0, >, r<0, >, v<0, > +// CHECK: %[[INDEX_10:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_11:.*]] = dxsa.operand %[[INDEX_10]] {mask = 64 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_11:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_12:.*]] = dxsa.operand %[[INDEX_11]] {num_components = 4 : i32, one = 2 : i32, type = 0 : i32} +// CHECK: %[[OPERAND_13:.*]] = dxsa.operand.imm {imm = dense<1> : vector<1xi32>} +// CHECK: dxsa.instruction "iadd" %[[OPERAND_11]], %[[OPERAND_12]], %[[OPERAND_13]] +// CHECK: dxsa.instruction "endloop" +// CHECK: %[[INDEX_12:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_14:.*]] = dxsa.operand %[[INDEX_12]] {mask = 16 : i32, num_components = 4 : i32, type = 2 : i32} +// CHECK: %[[INDEX_13:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_15:.*]] = dxsa.operand %[[INDEX_13]] {num_components = 4 : i32, one = 1 : i32, type = 0 : i32} +// CHECK: dxsa.instruction "mov" %[[OPERAND_14]], %[[OPERAND_15]] +// CHECK: dxsa.instruction "ret" + diff --git a/mlir/test/Target/DXSA/hlsl/minprec1.test b/mlir/test/Target/DXSA/hlsl/minprec1.test new file mode 100644 index 000000000000..b3fcd845cf2a --- /dev/null +++ b/mlir/test/Target/DXSA/hlsl/minprec1.test @@ -0,0 +1,23 @@ +// RUN: mlir-translate --import-dxsa-bin %S/inputs/minprec1.bin | FileCheck %s +// NOTE: Assertions have been autogenerated by utils/generate-test-checks.py + +// This script is intended to make adding checks to a test case quick and easy. +// It is *not* authoritative about what constitutes a good test. After using the +// script, be sure to review and refine the generated checks. For example, +// CHECK lines should be minimized and named to reflect the test’s intent. +// For comprehensive guidelines, see: +// * https://mlir.llvm.org/getting_started/TestingGuide/ + + +// CHECK-LABEL: dxsa.dcl_global_flags +// CHECK: dxsa.dcl_input_ps linear v<0, min16f, > +// CHECK: dxsa.dcl_output o<0, > +// CHECK: dxsa.dcl_temps 1 +// CHECK: dxsa.add r<0, min16f, >, v<0, min16f, >, l(0x40000000) +// CHECK: %[[INDEX_0:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_0:.*]] = dxsa.operand %[[INDEX_0]] {mask = 16 : i32, num_components = 4 : i32, type = 2 : i32} +// CHECK: %[[INDEX_1:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_1:.*]] = dxsa.operand %[[INDEX_1]] {min_precision = 1 : i32, num_components = 4 : i32, one = 0 : i32, type = 0 : i32} +// CHECK: dxsa.instruction "mov" %[[OPERAND_0]], %[[OPERAND_1]] +// CHECK: dxsa.instruction "ret" + diff --git a/mlir/test/Target/DXSA/hlsl/minprec2.test b/mlir/test/Target/DXSA/hlsl/minprec2.test new file mode 100644 index 000000000000..b2fb75d5bbb1 --- /dev/null +++ b/mlir/test/Target/DXSA/hlsl/minprec2.test @@ -0,0 +1,21 @@ +// RUN: mlir-translate --import-dxsa-bin %S/inputs/minprec2.bin | FileCheck %s +// NOTE: Assertions have been autogenerated by utils/generate-test-checks.py + +// This script is intended to make adding checks to a test case quick and easy. +// It is *not* authoritative about what constitutes a good test. After using the +// script, be sure to review and refine the generated checks. For example, +// CHECK lines should be minimized and named to reflect the test’s intent. +// For comprehensive guidelines, see: +// * https://mlir.llvm.org/getting_started/TestingGuide/ + + +// CHECK-LABEL: dxsa.dcl_global_flags +// CHECK: dxsa.dcl_input_ps linear v<0, min16f, > +// CHECK: dxsa.dcl_output o<0, > +// CHECK: %[[INDEX_0:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_0:.*]] = dxsa.operand %[[INDEX_0]] {mask = 16 : i32, num_components = 4 : i32, type = 2 : i32} +// CHECK: %[[INDEX_1:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_1:.*]] = dxsa.operand %[[INDEX_1]] {min_precision = 1 : i32, num_components = 4 : i32, one = 0 : i32, type = 1 : i32} +// CHECK: dxsa.instruction "mov" %[[OPERAND_0]], %[[OPERAND_1]] +// CHECK: dxsa.instruction "ret" + diff --git a/mlir/test/Target/DXSA/hlsl/minprec3.test b/mlir/test/Target/DXSA/hlsl/minprec3.test new file mode 100644 index 000000000000..bcec0105fcee --- /dev/null +++ b/mlir/test/Target/DXSA/hlsl/minprec3.test @@ -0,0 +1,39 @@ +// RUN: mlir-translate --import-dxsa-bin %S/inputs/minprec3.bin | FileCheck %s +// NOTE: Assertions have been autogenerated by utils/generate-test-checks.py + +// This script is intended to make adding checks to a test case quick and easy. +// It is *not* authoritative about what constitutes a good test. After using the +// script, be sure to review and refine the generated checks. For example, +// CHECK lines should be minimized and named to reflect the test’s intent. +// For comprehensive guidelines, see: +// * https://mlir.llvm.org/getting_started/TestingGuide/ + + +// CHECK-LABEL: dxsa.dcl_global_flags +// CHECK: dxsa.dcl_input_ps constant v<0, min16i, > +// CHECK: dxsa.dcl_output o<0, > +// CHECK: dxsa.dcl_temps 2 +// CHECK: %[[INDEX_0:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_0:.*]] = dxsa.operand %[[INDEX_0]] {mask = 16 : i32, min_precision = 4 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_1:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_1:.*]] = dxsa.operand %[[INDEX_1]] {min_precision = 4 : i32, num_components = 4 : i32, one = 0 : i32, type = 1 : i32} +// CHECK: %[[OPERAND_2:.*]] = dxsa.operand.imm {imm = dense<2> : vector<1xi32>} +// CHECK: dxsa.instruction "iadd" %[[OPERAND_0]], %[[OPERAND_1]], %[[OPERAND_2]] +// CHECK: dxsa.ieq r<1, >, r<0, min16i, >, l(0x7) +// CHECK: %[[INDEX_2:.*]] = dxsa.index.imm {imm = 1 : i32} +// CHECK: %[[OPERAND_3:.*]] = dxsa.operand %[[INDEX_2]] {num_components = 4 : i32, one = 0 : i32, type = 0 : i32} +// CHECK: dxsa.instruction "if" %[[OPERAND_3]] +// CHECK: %[[INDEX_3:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_4:.*]] = dxsa.operand %[[INDEX_3]] {mask = 16 : i32, num_components = 4 : i32, type = 2 : i32} +// CHECK: %[[OPERAND_5:.*]] = dxsa.operand.imm {imm = dense<4> : vector<1xi32>} +// CHECK: dxsa.instruction "mov" %[[OPERAND_4]], %[[OPERAND_5]] +// CHECK: dxsa.instruction "ret" +// CHECK: dxsa.instruction "else" +// CHECK: %[[INDEX_4:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_6:.*]] = dxsa.operand %[[INDEX_4]] {mask = 16 : i32, num_components = 4 : i32, type = 2 : i32} +// CHECK: %[[OPERAND_7:.*]] = dxsa.operand.imm {imm = dense<1> : vector<1xi32>} +// CHECK: dxsa.instruction "mov" %[[OPERAND_6]], %[[OPERAND_7]] +// CHECK: dxsa.instruction "ret" +// CHECK: dxsa.instruction "endif" +// CHECK: dxsa.instruction "ret" + diff --git a/mlir/test/Target/DXSA/hlsl/minprec4.test b/mlir/test/Target/DXSA/hlsl/minprec4.test new file mode 100644 index 000000000000..019a32f2f8a2 --- /dev/null +++ b/mlir/test/Target/DXSA/hlsl/minprec4.test @@ -0,0 +1,28 @@ +// RUN: mlir-translate --import-dxsa-bin %S/inputs/minprec4.bin | FileCheck %s +// NOTE: Assertions have been autogenerated by utils/generate-test-checks.py + +// This script is intended to make adding checks to a test case quick and easy. +// It is *not* authoritative about what constitutes a good test. After using the +// script, be sure to review and refine the generated checks. For example, +// CHECK lines should be minimized and named to reflect the test’s intent. +// For comprehensive guidelines, see: +// * https://mlir.llvm.org/getting_started/TestingGuide/ + + +// CHECK-LABEL: dxsa.dcl_global_flags +// CHECK: dxsa.dcl_input_ps constant v<0, min16u, > +// CHECK: dxsa.dcl_output o<0, > +// CHECK: dxsa.dcl_temps 1 +// CHECK: %[[INDEX_0:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_0:.*]] = dxsa.operand %[[INDEX_0]] {mask = 16 : i32, min_precision = 5 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_1:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_1:.*]] = dxsa.operand %[[INDEX_1]] {min_precision = 5 : i32, num_components = 4 : i32, one = 0 : i32, type = 1 : i32} +// CHECK: %[[OPERAND_2:.*]] = dxsa.operand.imm {imm = dense<-3> : vector<1xi32>} +// CHECK: dxsa.instruction "iadd" %[[OPERAND_0]], %[[OPERAND_1]], %[[OPERAND_2]] +// CHECK: %[[INDEX_2:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_3:.*]] = dxsa.operand %[[INDEX_2]] {mask = 16 : i32, num_components = 4 : i32, type = 2 : i32} +// CHECK: %[[INDEX_3:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_4:.*]] = dxsa.operand %[[INDEX_3]] {min_precision = 5 : i32, num_components = 4 : i32, one = 0 : i32, type = 0 : i32} +// CHECK: dxsa.instruction "mov" %[[OPERAND_3]], %[[OPERAND_4]] +// CHECK: dxsa.instruction "ret" + diff --git a/mlir/test/Target/DXSA/hlsl/minprec5.test b/mlir/test/Target/DXSA/hlsl/minprec5.test new file mode 100644 index 000000000000..3dec93335ec5 --- /dev/null +++ b/mlir/test/Target/DXSA/hlsl/minprec5.test @@ -0,0 +1,17 @@ +// RUN: mlir-translate --import-dxsa-bin %S/inputs/minprec5.bin | FileCheck %s +// NOTE: Assertions have been autogenerated by utils/generate-test-checks.py + +// This script is intended to make adding checks to a test case quick and easy. +// It is *not* authoritative about what constitutes a good test. After using the +// script, be sure to review and refine the generated checks. For example, +// CHECK lines should be minimized and named to reflect the test’s intent. +// For comprehensive guidelines, see: +// * https://mlir.llvm.org/getting_started/TestingGuide/ + + +// CHECK-LABEL: dxsa.dcl_global_flags +// CHECK: dxsa.dcl_input_ps linear v<0, > +// CHECK: dxsa.dcl_output o<0, min16f, > +// CHECK: dxsa.add o<0, min16f, >, v<0, >, l(0x40A00000) +// CHECK: dxsa.instruction "ret" + diff --git a/mlir/test/Target/DXSA/hlsl/minprec6.test b/mlir/test/Target/DXSA/hlsl/minprec6.test new file mode 100644 index 000000000000..99a2309d3c18 --- /dev/null +++ b/mlir/test/Target/DXSA/hlsl/minprec6.test @@ -0,0 +1,47 @@ +// RUN: mlir-translate --import-dxsa-bin %S/inputs/minprec6.bin | FileCheck %s +// NOTE: Assertions have been autogenerated by utils/generate-test-checks.py + +// This script is intended to make adding checks to a test case quick and easy. +// It is *not* authoritative about what constitutes a good test. After using the +// script, be sure to review and refine the generated checks. For example, +// CHECK lines should be minimized and named to reflect the test’s intent. +// For comprehensive guidelines, see: +// * https://mlir.llvm.org/getting_started/TestingGuide/ + + +// CHECK-LABEL: dxsa.dcl_global_flags +// CHECK: dxsa.dcl_constant_buffer , +// CHECK: dxsa.dcl_input_ps constant v<0, min16i, > +// CHECK: dxsa.dcl_output o<0, > +// CHECK: dxsa.dcl_temps 2 +// CHECK: %[[INDEX_0:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_0:.*]] = dxsa.operand %[[INDEX_0]] {mask = 16 : i32, min_precision = 4 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_1:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_1:.*]] = dxsa.operand %[[INDEX_1]] {min_precision = 4 : i32, num_components = 4 : i32, one = 0 : i32, type = 1 : i32} +// CHECK: %[[OPERAND_2:.*]] = dxsa.operand.imm {imm = dense<2> : vector<1xi32>} +// CHECK: dxsa.instruction "iadd" %[[OPERAND_0]], %[[OPERAND_1]], %[[OPERAND_2]] +// CHECK: dxsa.ieq r<1, >, r<0, min16i, >, cb<[0, 0], vector, min16i, > +// CHECK: %[[INDEX_2:.*]] = dxsa.index.imm {imm = 1 : i32} +// CHECK: %[[OPERAND_3:.*]] = dxsa.operand %[[INDEX_2]] {num_components = 4 : i32, one = 0 : i32, type = 0 : i32} +// CHECK: dxsa.instruction "if" %[[OPERAND_3]] +// CHECK: %[[INDEX_3:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_4:.*]] = dxsa.operand %[[INDEX_3]] {mask = 16 : i32, min_precision = 4 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_4:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_5:.*]] = dxsa.operand %[[INDEX_4]] {min_precision = 4 : i32, num_components = 4 : i32, one = 0 : i32, type = 1 : i32} +// CHECK: %[[OPERAND_6:.*]] = dxsa.operand.imm {imm = dense<-1> : vector<1xi32>} +// CHECK: dxsa.instruction "iadd" %[[OPERAND_4]], %[[OPERAND_5]], %[[OPERAND_6]] +// CHECK: %[[INDEX_5:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_7:.*]] = dxsa.operand %[[INDEX_5]] {mask = 16 : i32, num_components = 4 : i32, type = 2 : i32} +// CHECK: %[[INDEX_6:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_8:.*]] = dxsa.operand %[[INDEX_6]] {min_precision = 4 : i32, num_components = 4 : i32, one = 0 : i32, type = 0 : i32} +// CHECK: dxsa.instruction "mov" %[[OPERAND_7]], %[[OPERAND_8]] +// CHECK: dxsa.instruction "ret" +// CHECK: dxsa.instruction "else" +// CHECK: %[[INDEX_7:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_9:.*]] = dxsa.operand %[[INDEX_7]] {mask = 16 : i32, num_components = 4 : i32, type = 2 : i32} +// CHECK: %[[OPERAND_10:.*]] = dxsa.operand.imm {imm = dense<1> : vector<1xi32>} +// CHECK: dxsa.instruction "mov" %[[OPERAND_9]], %[[OPERAND_10]] +// CHECK: dxsa.instruction "ret" +// CHECK: dxsa.instruction "endif" +// CHECK: dxsa.instruction "ret" + diff --git a/mlir/test/Target/DXSA/hlsl/minprec7.test b/mlir/test/Target/DXSA/hlsl/minprec7.test new file mode 100644 index 000000000000..5420de2a8d48 --- /dev/null +++ b/mlir/test/Target/DXSA/hlsl/minprec7.test @@ -0,0 +1,23 @@ +// RUN: mlir-translate --import-dxsa-bin %S/inputs/minprec7.bin | FileCheck %s +// NOTE: Assertions have been autogenerated by utils/generate-test-checks.py + +// This script is intended to make adding checks to a test case quick and easy. +// It is *not* authoritative about what constitutes a good test. After using the +// script, be sure to review and refine the generated checks. For example, +// CHECK lines should be minimized and named to reflect the test’s intent. +// For comprehensive guidelines, see: +// * https://mlir.llvm.org/getting_started/TestingGuide/ + + +// CHECK-LABEL: dxsa.dcl_global_flags +// CHECK: dxsa.dcl_input_ps linear v<0, > +// CHECK: dxsa.dcl_output o<0, > +// CHECK: dxsa.dcl_temps 1 +// CHECK: dxsa.add r<0, min16f, >, v<0, >, l(0x40A00000) +// CHECK: %[[INDEX_0:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_0:.*]] = dxsa.operand %[[INDEX_0]] {mask = 16 : i32, num_components = 4 : i32, type = 2 : i32} +// CHECK: %[[INDEX_1:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_1:.*]] = dxsa.operand %[[INDEX_1]] {min_precision = 1 : i32, num_components = 4 : i32, one = 0 : i32, type = 0 : i32} +// CHECK: dxsa.instruction "mov" %[[OPERAND_0]], %[[OPERAND_1]] +// CHECK: dxsa.instruction "ret" + diff --git a/mlir/test/Target/DXSA/hlsl/neg1.test b/mlir/test/Target/DXSA/hlsl/neg1.test new file mode 100644 index 000000000000..a6bbcae8d794 --- /dev/null +++ b/mlir/test/Target/DXSA/hlsl/neg1.test @@ -0,0 +1,21 @@ +// RUN: mlir-translate --import-dxsa-bin %S/inputs/neg1.bin | FileCheck %s +// NOTE: Assertions have been autogenerated by utils/generate-test-checks.py + +// This script is intended to make adding checks to a test case quick and easy. +// It is *not* authoritative about what constitutes a good test. After using the +// script, be sure to review and refine the generated checks. For example, +// CHECK lines should be minimized and named to reflect the test’s intent. +// For comprehensive guidelines, see: +// * https://mlir.llvm.org/getting_started/TestingGuide/ + + +// CHECK-LABEL: dxsa.dcl_global_flags +// CHECK: dxsa.dcl_input_ps linear v<0, > +// CHECK: dxsa.dcl_output o<0> +// CHECK: %[[INDEX_0:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_0:.*]] = dxsa.operand %[[INDEX_0]] {mask = 240 : i32, num_components = 4 : i32, type = 2 : i32} +// CHECK: %[[INDEX_1:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_1:.*]] = dxsa.operand %[[INDEX_1]] {modifier = 1 : i32, num_components = 4 : i32, swizzle = dense<[1, 0, 0, 0]> : vector<4xi32>, type = 1 : i32} +// CHECK: dxsa.instruction "mov" %[[OPERAND_0]], %[[OPERAND_1]] +// CHECK: dxsa.instruction "ret" + diff --git a/mlir/test/Target/DXSA/hlsl/neg2.test b/mlir/test/Target/DXSA/hlsl/neg2.test new file mode 100644 index 000000000000..a8a79bd354d3 --- /dev/null +++ b/mlir/test/Target/DXSA/hlsl/neg2.test @@ -0,0 +1,21 @@ +// RUN: mlir-translate --import-dxsa-bin %S/inputs/neg2.bin | FileCheck %s +// NOTE: Assertions have been autogenerated by utils/generate-test-checks.py + +// This script is intended to make adding checks to a test case quick and easy. +// It is *not* authoritative about what constitutes a good test. After using the +// script, be sure to review and refine the generated checks. For example, +// CHECK lines should be minimized and named to reflect the test’s intent. +// For comprehensive guidelines, see: +// * https://mlir.llvm.org/getting_started/TestingGuide/ + + +// CHECK-LABEL: dxsa.dcl_global_flags +// CHECK: dxsa.dcl_input_ps constant v<0, > +// CHECK: dxsa.dcl_output o<0> +// CHECK: %[[INDEX_0:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_0:.*]] = dxsa.operand %[[INDEX_0]] {mask = 240 : i32, num_components = 4 : i32, type = 2 : i32} +// CHECK: %[[INDEX_1:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_1:.*]] = dxsa.operand %[[INDEX_1]] {num_components = 4 : i32, swizzle = dense<[1, 0, 0, 0]> : vector<4xi32>, type = 1 : i32} +// CHECK: dxsa.instruction "ineg" %[[OPERAND_0]], %[[OPERAND_1]] +// CHECK: dxsa.instruction "ret" + diff --git a/mlir/test/Target/DXSA/hlsl/negabs1.test b/mlir/test/Target/DXSA/hlsl/negabs1.test new file mode 100644 index 000000000000..058367287d83 --- /dev/null +++ b/mlir/test/Target/DXSA/hlsl/negabs1.test @@ -0,0 +1,21 @@ +// RUN: mlir-translate --import-dxsa-bin %S/inputs/negabs1.bin | FileCheck %s +// NOTE: Assertions have been autogenerated by utils/generate-test-checks.py + +// This script is intended to make adding checks to a test case quick and easy. +// It is *not* authoritative about what constitutes a good test. After using the +// script, be sure to review and refine the generated checks. For example, +// CHECK lines should be minimized and named to reflect the test’s intent. +// For comprehensive guidelines, see: +// * https://mlir.llvm.org/getting_started/TestingGuide/ + + +// CHECK-LABEL: dxsa.dcl_global_flags +// CHECK: dxsa.dcl_input_ps linear v<0, > +// CHECK: dxsa.dcl_output o<0> +// CHECK: %[[INDEX_0:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_0:.*]] = dxsa.operand %[[INDEX_0]] {mask = 240 : i32, num_components = 4 : i32, type = 2 : i32} +// CHECK: %[[INDEX_1:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_1:.*]] = dxsa.operand %[[INDEX_1]] {modifier = 3 : i32, num_components = 4 : i32, swizzle = dense<[1, 0, 0, 0]> : vector<4xi32>, type = 1 : i32} +// CHECK: dxsa.instruction "mov" %[[OPERAND_0]], %[[OPERAND_1]] +// CHECK: dxsa.instruction "ret" + diff --git a/mlir/test/Target/DXSA/hlsl/nonuniform1.test b/mlir/test/Target/DXSA/hlsl/nonuniform1.test new file mode 100644 index 000000000000..6b71481be569 --- /dev/null +++ b/mlir/test/Target/DXSA/hlsl/nonuniform1.test @@ -0,0 +1,59 @@ +// RUN: mlir-translate --import-dxsa-bin %S/inputs/nonuniform1.bin | FileCheck %s +// NOTE: Assertions have been autogenerated by utils/generate-test-checks.py + +// This script is intended to make adding checks to a test case quick and easy. +// It is *not* authoritative about what constitutes a good test. After using the +// script, be sure to review and refine the generated checks. For example, +// CHECK lines should be minimized and named to reflect the test’s intent. +// For comprehensive guidelines, see: +// * https://mlir.llvm.org/getting_started/TestingGuide/ + + +// CHECK-LABEL: dxsa.dcl_global_flags +// CHECK: dxsa.dcl_sampler +// CHECK: dxsa.dcl_resource , , +// CHECK: dxsa.dcl_input_ps constant v<0, > +// CHECK: dxsa.dcl_input_ps linear v<1, > +// CHECK: dxsa.dcl_output o<0> +// CHECK: dxsa.dcl_temps 2 +// CHECK: dxsa.itof r<0, >, v<0, > +// CHECK: %[[INDEX_0:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_0:.*]] = dxsa.operand %[[INDEX_0]] {mask = 32 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_1:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_1:.*]] = dxsa.operand %[[INDEX_1]] {num_components = 4 : i32, one = 0 : i32, type = 1 : i32} +// CHECK: dxsa.instruction "mov" %[[OPERAND_0]], %[[OPERAND_1]] +// CHECK: %[[INDEX_2:.*]] = dxsa.index.imm {imm = 1 : i32} +// CHECK: %[[OPERAND_2:.*]] = dxsa.operand %[[INDEX_2]] {mask = 240 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_3:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_3:.*]] = dxsa.operand %[[INDEX_3]] {num_components = 4 : i32, swizzle = dense<0> : vector<4xi32>, type = 0 : i32} +// CHECK: %[[INDEX_4:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[INDEX_5:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_4:.*]] = dxsa.operand %[[INDEX_5]] {num_components = 4 : i32, one = 1 : i32, type = 0 : i32} +// CHECK: %[[INDEX_6:.*]] = dxsa.index.rel.imm %[[OPERAND_4]] {imm = 3 : i32, op = "add"} +// CHECK: %[[OPERAND_5:.*]] = dxsa.operand %[[INDEX_4]], %[[INDEX_6]] {non_uniform = 1 : i32, num_components = 4 : i32, swizzle = dense<[0, 1, 2, 3]> : vector<4xi32>, type = 7 : i32} +// CHECK: %[[INDEX_7:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[INDEX_8:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_6:.*]] = dxsa.operand %[[INDEX_8]] {num_components = 4 : i32, one = 1 : i32, type = 0 : i32} +// CHECK: %[[INDEX_9:.*]] = dxsa.index.rel.imm %[[OPERAND_6]] {imm = 2 : i32, op = "add"} +// CHECK: %[[OPERAND_7:.*]] = dxsa.operand %[[INDEX_7]], %[[INDEX_9]] {non_uniform = 1 : i32, num_components = 0 : i32, type = 6 : i32} +// CHECK: dxsa.instruction "sample" %[[OPERAND_2]], %[[OPERAND_3]], %[[OPERAND_5]], %[[OPERAND_7]] +// CHECK: dxsa.ftou r<0, >, v<1, > +// CHECK: dxsa.add r<0, >, v<1, >, l(0x40000000) +// CHECK: %[[INDEX_10:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_8:.*]] = dxsa.operand %[[INDEX_10]] {mask = 240 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_11:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_9:.*]] = dxsa.operand %[[INDEX_11]] {num_components = 4 : i32, swizzle = dense<2> : vector<4xi32>, type = 0 : i32} +// CHECK: %[[INDEX_12:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[INDEX_13:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_10:.*]] = dxsa.operand %[[INDEX_13]] {num_components = 4 : i32, one = 0 : i32, type = 0 : i32} +// CHECK: %[[INDEX_14:.*]] = dxsa.index.rel.imm %[[OPERAND_10]] {imm = 3 : i32, op = "add"} +// CHECK: %[[OPERAND_11:.*]] = dxsa.operand %[[INDEX_12]], %[[INDEX_14]] {non_uniform = 1 : i32, num_components = 4 : i32, swizzle = dense<[0, 1, 2, 3]> : vector<4xi32>, type = 7 : i32} +// CHECK: %[[INDEX_15:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[INDEX_16:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_12:.*]] = dxsa.operand %[[INDEX_16]] {num_components = 4 : i32, one = 1 : i32, type = 0 : i32} +// CHECK: %[[INDEX_17:.*]] = dxsa.index.rel.imm %[[OPERAND_12]] {imm = 2 : i32, op = "add"} +// CHECK: %[[OPERAND_13:.*]] = dxsa.operand %[[INDEX_15]], %[[INDEX_17]] {num_components = 0 : i32, type = 6 : i32} +// CHECK: dxsa.instruction "sample" %[[OPERAND_8]], %[[OPERAND_9]], %[[OPERAND_11]], %[[OPERAND_13]] +// CHECK: dxsa.add o<0>, r<0>, r<1> +// CHECK: dxsa.instruction "ret" + diff --git a/mlir/test/Target/DXSA/hlsl/output1.test b/mlir/test/Target/DXSA/hlsl/output1.test new file mode 100644 index 000000000000..573cbc1bcaf5 --- /dev/null +++ b/mlir/test/Target/DXSA/hlsl/output1.test @@ -0,0 +1,39 @@ +// RUN: mlir-translate --import-dxsa-bin %S/inputs/output1.bin | FileCheck %s +// NOTE: Assertions have been autogenerated by utils/generate-test-checks.py + +// This script is intended to make adding checks to a test case quick and easy. +// It is *not* authoritative about what constitutes a good test. After using the +// script, be sure to review and refine the generated checks. For example, +// CHECK lines should be minimized and named to reflect the test’s intent. +// For comprehensive guidelines, see: +// * https://mlir.llvm.org/getting_started/TestingGuide/ + + +// CHECK-LABEL: dxsa.dcl_global_flags +// CHECK: dxsa.dcl_input_ps linear v<0> +// CHECK: dxsa.dcl_input_ps_sgv v<1, >, +// CHECK: dxsa.dcl_input_ps_sgv v<1, >, +// CHECK: dxsa.dcl_output o<0> +// CHECK: dxsa.dcl_output o<5> +// CHECK: dxsa.dcl_output oDepth +// CHECK: dxsa.dcl_temps 2 +// CHECK: dxsa.utof r<0, >, v<1, > +// CHECK: dxsa.add r<0>, r<0, >, v<0> +// CHECK: dxsa.and r<1, >, v<1, >, l(0x3F800000) +// CHECK: dxsa.add r<0>, r<0>, r<1, > +// CHECK: %[[OPERAND_0:.*]] = dxsa.operand {num_components = 1 : i32, type = 12 : i32} +// CHECK: %[[INDEX_0:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_1:.*]] = dxsa.operand %[[INDEX_0]] {num_components = 4 : i32, one = 0 : i32, type = 0 : i32} +// CHECK: dxsa.instruction "mov" %[[OPERAND_0]], %[[OPERAND_1]] +// CHECK: %[[INDEX_1:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_2:.*]] = dxsa.operand %[[INDEX_1]] {mask = 240 : i32, num_components = 4 : i32, type = 2 : i32} +// CHECK: %[[INDEX_2:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_3:.*]] = dxsa.operand %[[INDEX_2]] {num_components = 4 : i32, swizzle = dense<[0, 1, 2, 3]> : vector<4xi32>, type = 0 : i32} +// CHECK: dxsa.instruction "mov" %[[OPERAND_2]], %[[OPERAND_3]] +// CHECK: %[[INDEX_3:.*]] = dxsa.index.imm {imm = 5 : i32} +// CHECK: %[[OPERAND_4:.*]] = dxsa.operand %[[INDEX_3]] {mask = 240 : i32, num_components = 4 : i32, type = 2 : i32} +// CHECK: %[[INDEX_4:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_5:.*]] = dxsa.operand %[[INDEX_4]] {num_components = 4 : i32, swizzle = dense<[0, 1, 2, 3]> : vector<4xi32>, type = 0 : i32} +// CHECK: dxsa.instruction "mov" %[[OPERAND_4]], %[[OPERAND_5]] +// CHECK: dxsa.instruction "ret" + diff --git a/mlir/test/Target/DXSA/hlsl/output2.test b/mlir/test/Target/DXSA/hlsl/output2.test new file mode 100644 index 000000000000..7252692e947c --- /dev/null +++ b/mlir/test/Target/DXSA/hlsl/output2.test @@ -0,0 +1,35 @@ +// RUN: mlir-translate --import-dxsa-bin %S/inputs/output2.bin | FileCheck %s +// NOTE: Assertions have been autogenerated by utils/generate-test-checks.py + +// This script is intended to make adding checks to a test case quick and easy. +// It is *not* authoritative about what constitutes a good test. After using the +// script, be sure to review and refine the generated checks. For example, +// CHECK lines should be minimized and named to reflect the test’s intent. +// For comprehensive guidelines, see: +// * https://mlir.llvm.org/getting_started/TestingGuide/ + + +// CHECK-LABEL: dxsa.dcl_global_flags +// CHECK: dxsa.dcl_input_ps linear v<0> +// CHECK: dxsa.dcl_input_ps linear v<1> +// CHECK: dxsa.dcl_output o<0> +// CHECK: dxsa.dcl_output o<5> +// CHECK: dxsa.dcl_output oDepthGE +// CHECK: dxsa.dcl_temps 1 +// CHECK: dxsa.add r<0>, v<0>, v<1> +// CHECK: %[[OPERAND_0:.*]] = dxsa.operand {num_components = 1 : i32, type = 38 : i32} +// CHECK: %[[INDEX_0:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_1:.*]] = dxsa.operand %[[INDEX_0]] {num_components = 4 : i32, one = 0 : i32, type = 0 : i32} +// CHECK: dxsa.instruction "mov" %[[OPERAND_0]], %[[OPERAND_1]] +// CHECK: %[[INDEX_1:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_2:.*]] = dxsa.operand %[[INDEX_1]] {mask = 240 : i32, num_components = 4 : i32, type = 2 : i32} +// CHECK: %[[INDEX_2:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_3:.*]] = dxsa.operand %[[INDEX_2]] {num_components = 4 : i32, swizzle = dense<[0, 1, 2, 3]> : vector<4xi32>, type = 0 : i32} +// CHECK: dxsa.instruction "mov" %[[OPERAND_2]], %[[OPERAND_3]] +// CHECK: %[[INDEX_3:.*]] = dxsa.index.imm {imm = 5 : i32} +// CHECK: %[[OPERAND_4:.*]] = dxsa.operand %[[INDEX_3]] {mask = 240 : i32, num_components = 4 : i32, type = 2 : i32} +// CHECK: %[[INDEX_4:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_5:.*]] = dxsa.operand %[[INDEX_4]] {num_components = 4 : i32, swizzle = dense<[0, 1, 2, 3]> : vector<4xi32>, type = 0 : i32} +// CHECK: dxsa.instruction "mov" %[[OPERAND_4]], %[[OPERAND_5]] +// CHECK: dxsa.instruction "ret" + diff --git a/mlir/test/Target/DXSA/hlsl/output3.test b/mlir/test/Target/DXSA/hlsl/output3.test new file mode 100644 index 000000000000..0fdcdef9111d --- /dev/null +++ b/mlir/test/Target/DXSA/hlsl/output3.test @@ -0,0 +1,34 @@ +// RUN: mlir-translate --import-dxsa-bin %S/inputs/output3.bin | FileCheck %s +// NOTE: Assertions have been autogenerated by utils/generate-test-checks.py + +// This script is intended to make adding checks to a test case quick and easy. +// It is *not* authoritative about what constitutes a good test. After using the +// script, be sure to review and refine the generated checks. For example, +// CHECK lines should be minimized and named to reflect the test’s intent. +// For comprehensive guidelines, see: +// * https://mlir.llvm.org/getting_started/TestingGuide/ + + +// CHECK-LABEL: dxsa.dcl_global_flags +// CHECK: dxsa.dcl_input_ps linear v<0> +// CHECK: dxsa.dcl_output o<0> +// CHECK: dxsa.dcl_output o<5> +// CHECK: dxsa.dcl_output oDepthLE +// CHECK: dxsa.dcl_output oStencilRef +// CHECK: %[[OPERAND_0:.*]] = dxsa.operand {num_components = 1 : i32, type = 39 : i32} +// CHECK: %[[INDEX_0:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_1:.*]] = dxsa.operand %[[INDEX_0]] {num_components = 4 : i32, one = 0 : i32, type = 1 : i32} +// CHECK: dxsa.instruction "mov" %[[OPERAND_0]], %[[OPERAND_1]] +// CHECK: dxsa.ftou oStencilRef, v<0, > +// CHECK: %[[INDEX_1:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_2:.*]] = dxsa.operand %[[INDEX_1]] {mask = 240 : i32, num_components = 4 : i32, type = 2 : i32} +// CHECK: %[[INDEX_2:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_3:.*]] = dxsa.operand %[[INDEX_2]] {num_components = 4 : i32, swizzle = dense<[0, 1, 2, 3]> : vector<4xi32>, type = 1 : i32} +// CHECK: dxsa.instruction "mov" %[[OPERAND_2]], %[[OPERAND_3]] +// CHECK: %[[INDEX_3:.*]] = dxsa.index.imm {imm = 5 : i32} +// CHECK: %[[OPERAND_4:.*]] = dxsa.operand %[[INDEX_3]] {mask = 240 : i32, num_components = 4 : i32, type = 2 : i32} +// CHECK: %[[INDEX_4:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_5:.*]] = dxsa.operand %[[INDEX_4]] {num_components = 4 : i32, swizzle = dense<[0, 1, 2, 3]> : vector<4xi32>, type = 1 : i32} +// CHECK: dxsa.instruction "mov" %[[OPERAND_4]], %[[OPERAND_5]] +// CHECK: dxsa.instruction "ret" + diff --git a/mlir/test/Target/DXSA/hlsl/output4.test b/mlir/test/Target/DXSA/hlsl/output4.test new file mode 100644 index 000000000000..44b6b1de74bb --- /dev/null +++ b/mlir/test/Target/DXSA/hlsl/output4.test @@ -0,0 +1,39 @@ +// RUN: mlir-translate --import-dxsa-bin %S/inputs/output4.bin | FileCheck %s +// NOTE: Assertions have been autogenerated by utils/generate-test-checks.py + +// This script is intended to make adding checks to a test case quick and easy. +// It is *not* authoritative about what constitutes a good test. After using the +// script, be sure to review and refine the generated checks. For example, +// CHECK lines should be minimized and named to reflect the test’s intent. +// For comprehensive guidelines, see: +// * https://mlir.llvm.org/getting_started/TestingGuide/ + + +// CHECK-LABEL: dxsa.dcl_global_flags +// CHECK: dxsa.dcl_input v<0> +// CHECK: dxsa.dcl_output_siv o<0>, +// CHECK: dxsa.dcl_output_siv o<1, min16f, >, +// CHECK: dxsa.dcl_output_siv o<1, >, +// CHECK: dxsa.dcl_output_siv o<2, min16f, >, +// CHECK: %[[INDEX_0:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_0:.*]] = dxsa.operand %[[INDEX_0]] {mask = 240 : i32, num_components = 4 : i32, type = 2 : i32} +// CHECK: %[[INDEX_1:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_1:.*]] = dxsa.operand %[[INDEX_1]] {num_components = 4 : i32, swizzle = dense<[0, 1, 2, 3]> : vector<4xi32>, type = 1 : i32} +// CHECK: dxsa.instruction "mov" %[[OPERAND_0]], %[[OPERAND_1]] +// CHECK: %[[INDEX_2:.*]] = dxsa.index.imm {imm = 1 : i32} +// CHECK: %[[OPERAND_2:.*]] = dxsa.operand %[[INDEX_2]] {mask = 16 : i32, min_precision = 1 : i32, num_components = 4 : i32, type = 2 : i32} +// CHECK: %[[INDEX_3:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_3:.*]] = dxsa.operand %[[INDEX_3]] {num_components = 4 : i32, one = 0 : i32, type = 1 : i32} +// CHECK: dxsa.instruction "mov" %[[OPERAND_2]], %[[OPERAND_3]] +// CHECK: %[[INDEX_4:.*]] = dxsa.index.imm {imm = 1 : i32} +// CHECK: %[[OPERAND_4:.*]] = dxsa.operand %[[INDEX_4]] {mask = 96 : i32, num_components = 4 : i32, type = 2 : i32} +// CHECK: %[[INDEX_5:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_5:.*]] = dxsa.operand %[[INDEX_5]] {num_components = 4 : i32, swizzle = dense<[0, 0, 3, 0]> : vector<4xi32>, type = 1 : i32} +// CHECK: dxsa.instruction "mov" %[[OPERAND_4]], %[[OPERAND_5]] +// CHECK: %[[INDEX_6:.*]] = dxsa.index.imm {imm = 2 : i32} +// CHECK: %[[OPERAND_6:.*]] = dxsa.operand %[[INDEX_6]] {mask = 48 : i32, min_precision = 1 : i32, num_components = 4 : i32, type = 2 : i32} +// CHECK: %[[INDEX_7:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_7:.*]] = dxsa.operand %[[INDEX_7]] {num_components = 4 : i32, swizzle = dense<[1, 2, 1, 1]> : vector<4xi32>, type = 1 : i32} +// CHECK: dxsa.instruction "mov" %[[OPERAND_6]], %[[OPERAND_7]] +// CHECK: dxsa.instruction "ret" + diff --git a/mlir/test/Target/DXSA/hlsl/passthrough1.test b/mlir/test/Target/DXSA/hlsl/passthrough1.test new file mode 100644 index 000000000000..76b62a0a97d4 --- /dev/null +++ b/mlir/test/Target/DXSA/hlsl/passthrough1.test @@ -0,0 +1,21 @@ +// RUN: mlir-translate --import-dxsa-bin %S/inputs/passthrough1.bin | FileCheck %s +// NOTE: Assertions have been autogenerated by utils/generate-test-checks.py + +// This script is intended to make adding checks to a test case quick and easy. +// It is *not* authoritative about what constitutes a good test. After using the +// script, be sure to review and refine the generated checks. For example, +// CHECK lines should be minimized and named to reflect the test’s intent. +// For comprehensive guidelines, see: +// * https://mlir.llvm.org/getting_started/TestingGuide/ + + +// CHECK-LABEL: dxsa.dcl_global_flags +// CHECK: dxsa.dcl_input v<0> +// CHECK: dxsa.dcl_output_siv o<0>, +// CHECK: %[[INDEX_0:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_0:.*]] = dxsa.operand %[[INDEX_0]] {mask = 240 : i32, num_components = 4 : i32, type = 2 : i32} +// CHECK: %[[INDEX_1:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_1:.*]] = dxsa.operand %[[INDEX_1]] {num_components = 4 : i32, swizzle = dense<[0, 1, 2, 3]> : vector<4xi32>, type = 1 : i32} +// CHECK: dxsa.instruction "mov" %[[OPERAND_0]], %[[OPERAND_1]] +// CHECK: dxsa.instruction "ret" + diff --git a/mlir/test/Target/DXSA/hlsl/passthrough2.test b/mlir/test/Target/DXSA/hlsl/passthrough2.test new file mode 100644 index 000000000000..681501b21f4d --- /dev/null +++ b/mlir/test/Target/DXSA/hlsl/passthrough2.test @@ -0,0 +1,21 @@ +// RUN: mlir-translate --import-dxsa-bin %S/inputs/passthrough2.bin | FileCheck %s +// NOTE: Assertions have been autogenerated by utils/generate-test-checks.py + +// This script is intended to make adding checks to a test case quick and easy. +// It is *not* authoritative about what constitutes a good test. After using the +// script, be sure to review and refine the generated checks. For example, +// CHECK lines should be minimized and named to reflect the test’s intent. +// For comprehensive guidelines, see: +// * https://mlir.llvm.org/getting_started/TestingGuide/ + + +// CHECK-LABEL: dxsa.dcl_global_flags +// CHECK: dxsa.dcl_input_ps linear v<0, > +// CHECK: dxsa.dcl_output o<0> +// CHECK: %[[INDEX_0:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_0:.*]] = dxsa.operand %[[INDEX_0]] {mask = 240 : i32, num_components = 4 : i32, type = 2 : i32} +// CHECK: %[[INDEX_1:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_1:.*]] = dxsa.operand %[[INDEX_1]] {num_components = 4 : i32, swizzle = dense<[0, 0, 0, 1]> : vector<4xi32>, type = 1 : i32} +// CHECK: dxsa.instruction "mov" %[[OPERAND_0]], %[[OPERAND_1]] +// CHECK: dxsa.instruction "ret" + diff --git a/mlir/test/Target/DXSA/hlsl/precise1.test b/mlir/test/Target/DXSA/hlsl/precise1.test new file mode 100644 index 000000000000..ad4bcf552542 --- /dev/null +++ b/mlir/test/Target/DXSA/hlsl/precise1.test @@ -0,0 +1,28 @@ +// RUN: mlir-translate --import-dxsa-bin %S/inputs/precise1.bin | FileCheck %s +// NOTE: Assertions have been autogenerated by utils/generate-test-checks.py + +// This script is intended to make adding checks to a test case quick and easy. +// It is *not* authoritative about what constitutes a good test. After using the +// script, be sure to review and refine the generated checks. For example, +// CHECK lines should be minimized and named to reflect the test’s intent. +// For comprehensive guidelines, see: +// * https://mlir.llvm.org/getting_started/TestingGuide/ + + +// CHECK-LABEL: dxsa.dcl_global_flags +// CHECK: dxsa.dcl_constant_buffer , +// CHECK: dxsa.dcl_sampler +// CHECK: dxsa.dcl_resource , , +// CHECK: dxsa.dcl_input_ps linear v<0, > +// CHECK: dxsa.dcl_output o<0> +// CHECK: dxsa.dcl_temps 1 +// CHECK: dxsa.unknown +// CHECK: dxsa.mul precise r<0>, r<0>, cb<[0, 0], vector> +// CHECK: dxsa.mad precise r<0>, r<0>, cb<[0, 1], vector>, cb<[0, 2], vector> +// CHECK: %[[INDEX_0:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_0:.*]] = dxsa.operand %[[INDEX_0]] {mask = 240 : i32, num_components = 4 : i32, type = 2 : i32} +// CHECK: %[[INDEX_1:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_1:.*]] = dxsa.operand %[[INDEX_1]] {modifier = 1 : i32, num_components = 4 : i32, swizzle = dense<[0, 1, 2, 3]> : vector<4xi32>, type = 0 : i32} +// CHECK: dxsa.instruction "mov" %[[OPERAND_0]], %[[OPERAND_1]] +// CHECK: dxsa.instruction "ret" + diff --git a/mlir/test/Target/DXSA/hlsl/raw_buf1.test b/mlir/test/Target/DXSA/hlsl/raw_buf1.test new file mode 100644 index 000000000000..44907891c766 --- /dev/null +++ b/mlir/test/Target/DXSA/hlsl/raw_buf1.test @@ -0,0 +1,161 @@ +// RUN: mlir-translate --import-dxsa-bin %S/inputs/raw_buf1.bin | FileCheck %s +// NOTE: Assertions have been autogenerated by utils/generate-test-checks.py + +// This script is intended to make adding checks to a test case quick and easy. +// It is *not* authoritative about what constitutes a good test. After using the +// script, be sure to review and refine the generated checks. For example, +// CHECK lines should be minimized and named to reflect the test’s intent. +// For comprehensive guidelines, see: +// * https://mlir.llvm.org/getting_started/TestingGuide/ + + +// CHECK-LABEL: dxsa.dcl_global_flags +// CHECK: dxsa.dcl_resource_raw +// CHECK: dxsa.dcl_uav_raw +// CHECK: dxsa.dcl_input_ps linear v<0, > +// CHECK: dxsa.dcl_input_ps linear v<0, > +// CHECK: dxsa.dcl_output o<0> +// CHECK: dxsa.dcl_temps 16 +// CHECK: dxsa.ftou r<0, >, v<0, > +// CHECK: dxsa.unknown +// CHECK: dxsa.add r<1, >, v<0, >, l(0x3F800000, 0x40000000, 0x40400000, 0x0) +// CHECK: dxsa.ftou r<1, >, r<1, > +// CHECK: dxsa.unknown +// CHECK: dxsa.unknown +// CHECK: dxsa.utof r<3, >, r<3, > +// CHECK: dxsa.unknown +// CHECK: dxsa.utof r<4>, r<4> +// CHECK: dxsa.unknown +// CHECK: dxsa.unknown +// CHECK: dxsa.unknown +// CHECK: dxsa.unknown +// CHECK: dxsa.unknown +// CHECK: dxsa.utof r<13, min16f, >, r<0, > +// CHECK: dxsa.unknown +// CHECK: dxsa.utof r<2>, r<2> +// CHECK: dxsa.add r<2, >, r<2, >, r<13, min16f, > +// CHECK: dxsa.unknown +// CHECK: dxsa.utof r<5, >, r<5, > +// CHECK: dxsa.add r<14, >, r<2, >, r<5, > +// CHECK: dxsa.add r<14, >, r<5, >, r<13, min16f, > +// CHECK: dxsa.unknown +// CHECK: dxsa.utof r<15>, r<15> +// CHECK: dxsa.add r<14, >, r<14, >, r<15, > +// CHECK: dxsa.add r<14, >, r<13, min16f, >, r<15, > +// CHECK: dxsa.unknown +// CHECK: %[[INDEX_0:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_0:.*]] = dxsa.operand %[[INDEX_0]] {mask = 128 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_1:.*]] = dxsa.index.imm {imm = 15 : i32} +// CHECK: %[[OPERAND_1:.*]] = dxsa.operand %[[INDEX_1]] {num_components = 4 : i32, one = 0 : i32, type = 0 : i32} +// CHECK: dxsa.instruction "check_access_fully_mapped" %[[OPERAND_0]], %[[OPERAND_1]] +// CHECK: dxsa.utof r<0, >, r<0, > +// CHECK: dxsa.add r<13>, r<0, >, r<14> +// CHECK: dxsa.add r<13>, r<0, >, r<13> +// CHECK: dxsa.unknown +// CHECK: %[[INDEX_2:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_2:.*]] = dxsa.operand %[[INDEX_2]] {mask = 128 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_3:.*]] = dxsa.index.imm {imm = 1 : i32} +// CHECK: %[[OPERAND_3:.*]] = dxsa.operand %[[INDEX_3]] {num_components = 4 : i32, one = 0 : i32, type = 0 : i32} +// CHECK: dxsa.instruction "check_access_fully_mapped" %[[OPERAND_2]], %[[OPERAND_3]] +// CHECK: dxsa.utof r<0, >, r<0, > +// CHECK: dxsa.add r<13, >, r<0, >, r<13, > +// CHECK: dxsa.add r<13>, r<0, >, r<13> +// CHECK: dxsa.unknown +// CHECK: dxsa.unknown +// CHECK: %[[INDEX_4:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_4:.*]] = dxsa.operand %[[INDEX_4]] {mask = 128 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_5:.*]] = dxsa.index.imm {imm = 1 : i32} +// CHECK: %[[OPERAND_5:.*]] = dxsa.operand %[[INDEX_5]] {num_components = 4 : i32, one = 0 : i32, type = 0 : i32} +// CHECK: dxsa.instruction "check_access_fully_mapped" %[[OPERAND_4]], %[[OPERAND_5]] +// CHECK: dxsa.utof r<0, >, r<0, > +// CHECK: dxsa.add r<13, >, r<0, >, r<13, > +// CHECK: dxsa.add r<1>, r<0, >, r<13> +// CHECK: dxsa.utof r<0, >, r<14, > +// CHECK: %[[INDEX_6:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_6:.*]] = dxsa.operand %[[INDEX_6]] {mask = 128 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_7:.*]] = dxsa.index.imm {imm = 15 : i32} +// CHECK: %[[OPERAND_7:.*]] = dxsa.operand %[[INDEX_7]] {num_components = 4 : i32, one = 0 : i32, type = 0 : i32} +// CHECK: dxsa.instruction "check_access_fully_mapped" %[[OPERAND_6]], %[[OPERAND_7]] +// CHECK: dxsa.utof r<0, >, r<0, > +// CHECK: dxsa.add r<1>, r<0, >, r<1> +// CHECK: dxsa.add r<1>, r<0, >, r<1> +// CHECK: dxsa.add r<1>, r<0, >, r<1> +// CHECK: dxsa.add r<1, >, r<2, >, r<1, > +// CHECK: dxsa.add r<1, >, r<3, >, r<1, > +// CHECK: dxsa.add r<1>, r<4>, r<1> +// CHECK: dxsa.utof r<0, >, r<5, > +// CHECK: %[[INDEX_8:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_8:.*]] = dxsa.operand %[[INDEX_8]] {mask = 64 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_9:.*]] = dxsa.index.imm {imm = 6 : i32} +// CHECK: %[[OPERAND_9:.*]] = dxsa.operand %[[INDEX_9]] {num_components = 4 : i32, one = 0 : i32, type = 0 : i32} +// CHECK: dxsa.instruction "check_access_fully_mapped" %[[OPERAND_8]], %[[OPERAND_9]] +// CHECK: dxsa.utof r<0, >, r<0, > +// CHECK: dxsa.add r<1>, r<0, >, r<1> +// CHECK: dxsa.add r<1>, r<0, >, r<1> +// CHECK: dxsa.utof r<0, >, r<7, > +// CHECK: %[[INDEX_10:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_10:.*]] = dxsa.operand %[[INDEX_10]] {mask = 64 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_11:.*]] = dxsa.index.imm {imm = 8 : i32} +// CHECK: %[[OPERAND_11:.*]] = dxsa.operand %[[INDEX_11]] {num_components = 4 : i32, one = 0 : i32, type = 0 : i32} +// CHECK: dxsa.instruction "check_access_fully_mapped" %[[OPERAND_10]], %[[OPERAND_11]] +// CHECK: dxsa.utof r<0, >, r<0, > +// CHECK: dxsa.add r<1, >, r<0, >, r<1, > +// CHECK: dxsa.add r<1>, r<0, >, r<1> +// CHECK: dxsa.utof r<0, >, r<9, > +// CHECK: %[[INDEX_12:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_12:.*]] = dxsa.operand %[[INDEX_12]] {mask = 64 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_13:.*]] = dxsa.index.imm {imm = 10 : i32} +// CHECK: %[[OPERAND_13:.*]] = dxsa.operand %[[INDEX_13]] {num_components = 4 : i32, one = 0 : i32, type = 0 : i32} +// CHECK: dxsa.instruction "check_access_fully_mapped" %[[OPERAND_12]], %[[OPERAND_13]] +// CHECK: dxsa.utof r<0, >, r<0, > +// CHECK: dxsa.add r<1, >, r<0, >, r<1, > +// CHECK: dxsa.add r<1>, r<0, >, r<1> +// CHECK: dxsa.utof r<0, >, r<11, > +// CHECK: %[[INDEX_14:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_14:.*]] = dxsa.operand %[[INDEX_14]] {mask = 64 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_15:.*]] = dxsa.index.imm {imm = 12 : i32} +// CHECK: %[[OPERAND_15:.*]] = dxsa.operand %[[INDEX_15]] {num_components = 4 : i32, one = 0 : i32, type = 0 : i32} +// CHECK: dxsa.instruction "check_access_fully_mapped" %[[OPERAND_14]], %[[OPERAND_15]] +// CHECK: dxsa.utof r<0, >, r<0, > +// CHECK: dxsa.add r<1>, r<0, >, r<1> +// CHECK: dxsa.add r<1>, r<0, >, r<1> +// CHECK: dxsa.ftou r<0, >, r<1, > +// CHECK: %[[INDEX_16:.*]] = dxsa.index.imm {imm = 1 : i32} +// CHECK: %[[OPERAND_16:.*]] = dxsa.operand %[[INDEX_16]] {mask = 16 : i32, num_components = 4 : i32, type = 30 : i32} +// CHECK: %[[INDEX_17:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_17:.*]] = dxsa.operand %[[INDEX_17]] {num_components = 4 : i32, one = 1 : i32, type = 0 : i32} +// CHECK: %[[INDEX_18:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_18:.*]] = dxsa.operand %[[INDEX_18]] {num_components = 4 : i32, one = 0 : i32, type = 0 : i32} +// CHECK: dxsa.instruction "store_raw" %[[OPERAND_16]], %[[OPERAND_17]], %[[OPERAND_18]] +// CHECK: dxsa.add r<2, >, v<0, >, l(0x3F800000, 0x40000000, 0x40400000, 0x0) +// CHECK: dxsa.ftou r<2, >, r<2, > +// CHECK: %[[INDEX_19:.*]] = dxsa.index.imm {imm = 1 : i32} +// CHECK: %[[OPERAND_19:.*]] = dxsa.operand %[[INDEX_19]] {mask = 48 : i32, num_components = 4 : i32, type = 30 : i32} +// CHECK: %[[INDEX_20:.*]] = dxsa.index.imm {imm = 2 : i32} +// CHECK: %[[OPERAND_20:.*]] = dxsa.operand %[[INDEX_20]] {num_components = 4 : i32, one = 0 : i32, type = 0 : i32} +// CHECK: %[[INDEX_21:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_21:.*]] = dxsa.operand %[[INDEX_21]] {num_components = 4 : i32, swizzle = dense<[2, 3, 2, 2]> : vector<4xi32>, type = 0 : i32} +// CHECK: dxsa.instruction "store_raw" %[[OPERAND_19]], %[[OPERAND_20]], %[[OPERAND_21]] +// CHECK: dxsa.ftou r<0, >, r<1, > +// CHECK: %[[INDEX_22:.*]] = dxsa.index.imm {imm = 1 : i32} +// CHECK: %[[OPERAND_22:.*]] = dxsa.operand %[[INDEX_22]] {mask = 112 : i32, num_components = 4 : i32, type = 30 : i32} +// CHECK: %[[INDEX_23:.*]] = dxsa.index.imm {imm = 2 : i32} +// CHECK: %[[OPERAND_23:.*]] = dxsa.operand %[[INDEX_23]] {num_components = 4 : i32, one = 1 : i32, type = 0 : i32} +// CHECK: %[[INDEX_24:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_24:.*]] = dxsa.operand %[[INDEX_24]] {num_components = 4 : i32, swizzle = dense<[0, 1, 2, 0]> : vector<4xi32>, type = 0 : i32} +// CHECK: dxsa.instruction "store_raw" %[[OPERAND_22]], %[[OPERAND_23]], %[[OPERAND_24]] +// CHECK: dxsa.ftou r<0>, r<1, > +// CHECK: %[[INDEX_25:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_25:.*]] = dxsa.operand %[[INDEX_25]] {mask = 240 : i32, num_components = 4 : i32, type = 2 : i32} +// CHECK: %[[INDEX_26:.*]] = dxsa.index.imm {imm = 1 : i32} +// CHECK: %[[OPERAND_26:.*]] = dxsa.operand %[[INDEX_26]] {num_components = 4 : i32, swizzle = dense<[0, 1, 2, 3]> : vector<4xi32>, type = 0 : i32} +// CHECK: dxsa.instruction "mov" %[[OPERAND_25]], %[[OPERAND_26]] +// CHECK: %[[INDEX_27:.*]] = dxsa.index.imm {imm = 1 : i32} +// CHECK: %[[OPERAND_27:.*]] = dxsa.operand %[[INDEX_27]] {mask = 240 : i32, num_components = 4 : i32, type = 30 : i32} +// CHECK: %[[INDEX_28:.*]] = dxsa.index.imm {imm = 2 : i32} +// CHECK: %[[OPERAND_28:.*]] = dxsa.operand %[[INDEX_28]] {num_components = 4 : i32, one = 2 : i32, type = 0 : i32} +// CHECK: %[[INDEX_29:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_29:.*]] = dxsa.operand %[[INDEX_29]] {num_components = 4 : i32, swizzle = dense<[0, 1, 2, 3]> : vector<4xi32>, type = 0 : i32} +// CHECK: dxsa.instruction "store_raw" %[[OPERAND_27]], %[[OPERAND_28]], %[[OPERAND_29]] +// CHECK: dxsa.instruction "ret" + diff --git a/mlir/test/Target/DXSA/hlsl/rcp1.test b/mlir/test/Target/DXSA/hlsl/rcp1.test new file mode 100644 index 000000000000..fe297fd1500a --- /dev/null +++ b/mlir/test/Target/DXSA/hlsl/rcp1.test @@ -0,0 +1,17 @@ +// RUN: mlir-translate --import-dxsa-bin %S/inputs/rcp1.bin | FileCheck %s +// NOTE: Assertions have been autogenerated by utils/generate-test-checks.py + +// This script is intended to make adding checks to a test case quick and easy. +// It is *not* authoritative about what constitutes a good test. After using the +// script, be sure to review and refine the generated checks. For example, +// CHECK lines should be minimized and named to reflect the test’s intent. +// For comprehensive guidelines, see: +// * https://mlir.llvm.org/getting_started/TestingGuide/ + + +// CHECK-LABEL: dxsa.dcl_global_flags +// CHECK: dxsa.dcl_input_ps linear v<0, > +// CHECK: dxsa.dcl_output o<0, > +// CHECK: dxsa.rcp o<0, >, v<0, > +// CHECK: dxsa.instruction "ret" + diff --git a/mlir/test/Target/DXSA/hlsl/redundantinput1.test b/mlir/test/Target/DXSA/hlsl/redundantinput1.test new file mode 100644 index 000000000000..4fb22ef308f4 --- /dev/null +++ b/mlir/test/Target/DXSA/hlsl/redundantinput1.test @@ -0,0 +1,17 @@ +// RUN: mlir-translate --import-dxsa-bin %S/inputs/redundantinput1.bin | FileCheck %s +// NOTE: Assertions have been autogenerated by utils/generate-test-checks.py + +// This script is intended to make adding checks to a test case quick and easy. +// It is *not* authoritative about what constitutes a good test. After using the +// script, be sure to review and refine the generated checks. For example, +// CHECK lines should be minimized and named to reflect the test’s intent. +// For comprehensive guidelines, see: +// * https://mlir.llvm.org/getting_started/TestingGuide/ + + +// CHECK-LABEL: dxsa.dcl_global_flags +// CHECK: dxsa.dcl_input_ps linear v<0> +// CHECK: dxsa.dcl_output o<0> +// CHECK: dxsa.add o<0>, |v<0>|, v<0> +// CHECK: dxsa.instruction "ret" + diff --git a/mlir/test/Target/DXSA/hlsl/sample1.test b/mlir/test/Target/DXSA/hlsl/sample1.test new file mode 100644 index 000000000000..abc9e8ab8dae --- /dev/null +++ b/mlir/test/Target/DXSA/hlsl/sample1.test @@ -0,0 +1,22 @@ +// RUN: mlir-translate --import-dxsa-bin %S/inputs/sample1.bin | FileCheck %s +// NOTE: Assertions have been autogenerated by utils/generate-test-checks.py + +// This script is intended to make adding checks to a test case quick and easy. +// It is *not* authoritative about what constitutes a good test. After using the +// script, be sure to review and refine the generated checks. For example, +// CHECK lines should be minimized and named to reflect the test’s intent. +// For comprehensive guidelines, see: +// * https://mlir.llvm.org/getting_started/TestingGuide/ + + +// CHECK-LABEL: dxsa.dcl_global_flags +// CHECK: dxsa.dcl_constant_buffer , +// CHECK: dxsa.dcl_sampler +// CHECK: dxsa.dcl_resource , , +// CHECK: dxsa.dcl_input_ps linear v<0, > +// CHECK: dxsa.dcl_output o<0> +// CHECK: dxsa.dcl_temps 1 +// CHECK: dxsa.unknown +// CHECK: dxsa.add o<0>, r<0>, cb<[0, 2], vector> +// CHECK: dxsa.instruction "ret" + diff --git a/mlir/test/Target/DXSA/hlsl/sample2.test b/mlir/test/Target/DXSA/hlsl/sample2.test new file mode 100644 index 000000000000..7ab8c9cc1c1d --- /dev/null +++ b/mlir/test/Target/DXSA/hlsl/sample2.test @@ -0,0 +1,22 @@ +// RUN: mlir-translate --import-dxsa-bin %S/inputs/sample2.bin | FileCheck %s +// NOTE: Assertions have been autogenerated by utils/generate-test-checks.py + +// This script is intended to make adding checks to a test case quick and easy. +// It is *not* authoritative about what constitutes a good test. After using the +// script, be sure to review and refine the generated checks. For example, +// CHECK lines should be minimized and named to reflect the test’s intent. +// For comprehensive guidelines, see: +// * https://mlir.llvm.org/getting_started/TestingGuide/ + + +// CHECK-LABEL: dxsa.dcl_global_flags +// CHECK: dxsa.dcl_constant_buffer , +// CHECK: dxsa.dcl_sampler +// CHECK: dxsa.dcl_resource , , +// CHECK: dxsa.dcl_input_ps linear v<0, > +// CHECK: dxsa.dcl_output o<0, > +// CHECK: dxsa.dcl_temps 1 +// CHECK: dxsa.unknown +// CHECK: dxsa.add o<0, >, r<0, >, cb<[0, 2], vector, > +// CHECK: dxsa.instruction "ret" + diff --git a/mlir/test/Target/DXSA/hlsl/sample3.test b/mlir/test/Target/DXSA/hlsl/sample3.test new file mode 100644 index 000000000000..7c63c36f8cbe --- /dev/null +++ b/mlir/test/Target/DXSA/hlsl/sample3.test @@ -0,0 +1,42 @@ +// RUN: mlir-translate --import-dxsa-bin %S/inputs/sample3.bin | FileCheck %s +// NOTE: Assertions have been autogenerated by utils/generate-test-checks.py + +// This script is intended to make adding checks to a test case quick and easy. +// It is *not* authoritative about what constitutes a good test. After using the +// script, be sure to review and refine the generated checks. For example, +// CHECK lines should be minimized and named to reflect the test’s intent. +// For comprehensive guidelines, see: +// * https://mlir.llvm.org/getting_started/TestingGuide/ + + +// CHECK-LABEL: dxsa.dcl_global_flags +// CHECK: dxsa.dcl_sampler +// CHECK: dxsa.dcl_resource , , +// CHECK: dxsa.dcl_input_ps linear v<0, > +// CHECK: dxsa.dcl_output o<0> +// CHECK: dxsa.dcl_temps 3 +// CHECK: dxsa.unknown +// CHECK: dxsa.unknown +// CHECK: dxsa.add r<0>, r<0>, r<1> +// CHECK: dxsa.unknown +// CHECK: dxsa.add r<0>, r<0>, r<1> +// CHECK: dxsa.unknown +// CHECK: dxsa.add r<0>, r<0>, r<1> +// CHECK: %[[INDEX_0:.*]] = dxsa.index.imm {imm = 1 : i32} +// CHECK: %[[OPERAND_0:.*]] = dxsa.operand %[[INDEX_0]] {mask = 16 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_1:.*]] = dxsa.index.imm {imm = 2 : i32} +// CHECK: %[[OPERAND_1:.*]] = dxsa.operand %[[INDEX_1]] {num_components = 4 : i32, one = 0 : i32, type = 0 : i32} +// CHECK: dxsa.instruction "check_access_fully_mapped" %[[OPERAND_0]], %[[OPERAND_1]] +// CHECK: dxsa.utof r<1, >, r<1, > +// CHECK: dxsa.add r<0>, r<0>, r<1, > +// CHECK: dxsa.unknown +// CHECK: dxsa.add r<0>, r<0>, r<1> +// CHECK: %[[INDEX_2:.*]] = dxsa.index.imm {imm = 1 : i32} +// CHECK: %[[OPERAND_2:.*]] = dxsa.operand %[[INDEX_2]] {mask = 16 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_3:.*]] = dxsa.index.imm {imm = 2 : i32} +// CHECK: %[[OPERAND_3:.*]] = dxsa.operand %[[INDEX_3]] {num_components = 4 : i32, one = 0 : i32, type = 0 : i32} +// CHECK: dxsa.instruction "check_access_fully_mapped" %[[OPERAND_2]], %[[OPERAND_3]] +// CHECK: dxsa.utof r<1, >, r<1, > +// CHECK: dxsa.add o<0>, r<0>, r<1, > +// CHECK: dxsa.instruction "ret" + diff --git a/mlir/test/Target/DXSA/hlsl/sample_b1.test b/mlir/test/Target/DXSA/hlsl/sample_b1.test new file mode 100644 index 000000000000..29aa8d117d0e --- /dev/null +++ b/mlir/test/Target/DXSA/hlsl/sample_b1.test @@ -0,0 +1,42 @@ +// RUN: mlir-translate --import-dxsa-bin %S/inputs/sample_b1.bin | FileCheck %s +// NOTE: Assertions have been autogenerated by utils/generate-test-checks.py + +// This script is intended to make adding checks to a test case quick and easy. +// It is *not* authoritative about what constitutes a good test. After using the +// script, be sure to review and refine the generated checks. For example, +// CHECK lines should be minimized and named to reflect the test’s intent. +// For comprehensive guidelines, see: +// * https://mlir.llvm.org/getting_started/TestingGuide/ + + +// CHECK-LABEL: dxsa.dcl_global_flags +// CHECK: dxsa.dcl_sampler +// CHECK: dxsa.dcl_resource , , +// CHECK: dxsa.dcl_input_ps linear v<0, > +// CHECK: dxsa.dcl_output o<0> +// CHECK: dxsa.dcl_temps 3 +// CHECK: dxsa.unknown +// CHECK: dxsa.unknown +// CHECK: dxsa.add r<0>, r<0>, r<1> +// CHECK: dxsa.unknown +// CHECK: dxsa.add r<0>, r<0>, r<1> +// CHECK: dxsa.unknown +// CHECK: dxsa.add r<0>, r<0>, r<1> +// CHECK: %[[INDEX_0:.*]] = dxsa.index.imm {imm = 1 : i32} +// CHECK: %[[OPERAND_0:.*]] = dxsa.operand %[[INDEX_0]] {mask = 16 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_1:.*]] = dxsa.index.imm {imm = 2 : i32} +// CHECK: %[[OPERAND_1:.*]] = dxsa.operand %[[INDEX_1]] {num_components = 4 : i32, one = 0 : i32, type = 0 : i32} +// CHECK: dxsa.instruction "check_access_fully_mapped" %[[OPERAND_0]], %[[OPERAND_1]] +// CHECK: dxsa.utof r<1, >, r<1, > +// CHECK: dxsa.add r<0>, r<0>, r<1, > +// CHECK: dxsa.unknown +// CHECK: dxsa.add r<0>, r<0>, r<1> +// CHECK: %[[INDEX_2:.*]] = dxsa.index.imm {imm = 1 : i32} +// CHECK: %[[OPERAND_2:.*]] = dxsa.operand %[[INDEX_2]] {mask = 16 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_3:.*]] = dxsa.index.imm {imm = 2 : i32} +// CHECK: %[[OPERAND_3:.*]] = dxsa.operand %[[INDEX_3]] {num_components = 4 : i32, one = 0 : i32, type = 0 : i32} +// CHECK: dxsa.instruction "check_access_fully_mapped" %[[OPERAND_2]], %[[OPERAND_3]] +// CHECK: dxsa.utof r<1, >, r<1, > +// CHECK: dxsa.add o<0>, r<0>, r<1, > +// CHECK: dxsa.instruction "ret" + diff --git a/mlir/test/Target/DXSA/hlsl/sample_cmp1.test b/mlir/test/Target/DXSA/hlsl/sample_cmp1.test new file mode 100644 index 000000000000..a4129610835f --- /dev/null +++ b/mlir/test/Target/DXSA/hlsl/sample_cmp1.test @@ -0,0 +1,45 @@ +// RUN: mlir-translate --import-dxsa-bin %S/inputs/sample_cmp1.bin | FileCheck %s +// NOTE: Assertions have been autogenerated by utils/generate-test-checks.py + +// This script is intended to make adding checks to a test case quick and easy. +// It is *not* authoritative about what constitutes a good test. After using the +// script, be sure to review and refine the generated checks. For example, +// CHECK lines should be minimized and named to reflect the test’s intent. +// For comprehensive guidelines, see: +// * https://mlir.llvm.org/getting_started/TestingGuide/ + + +// CHECK-LABEL: dxsa.dcl_global_flags +// CHECK: dxsa.dcl_sampler +// CHECK: dxsa.dcl_resource , , +// CHECK: dxsa.dcl_input_ps linear v<0, > +// CHECK: dxsa.dcl_output o<0> +// CHECK: dxsa.dcl_temps 4 +// CHECK: dxsa.add r<0, >, v<0, >, v<0, > +// CHECK: dxsa.ftou r<0, >, r<0, > +// CHECK: dxsa.utof r<0, >, r<0, > +// CHECK: dxsa.unknown +// CHECK: dxsa.unknown +// CHECK: dxsa.add r<0, >, r<0, >, r<0, > +// CHECK: dxsa.unknown +// CHECK: dxsa.add r<0, >, r<0, >, r<1, > +// CHECK: dxsa.unknown +// CHECK: dxsa.unknown +// CHECK: dxsa.add r<0, >, r<0, >, r<1, > +// CHECK: %[[INDEX_0:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_0:.*]] = dxsa.operand %[[INDEX_0]] {mask = 64 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_1:.*]] = dxsa.index.imm {imm = 2 : i32} +// CHECK: %[[OPERAND_1:.*]] = dxsa.operand %[[INDEX_1]] {num_components = 4 : i32, one = 0 : i32, type = 0 : i32} +// CHECK: dxsa.instruction "check_access_fully_mapped" %[[OPERAND_0]], %[[OPERAND_1]] +// CHECK: dxsa.utof r<0, >, r<0, > +// CHECK: dxsa.add r<0, >, r<0, >, r<0, > +// CHECK: dxsa.add r<0, >, r<0, >, r<0, > +// CHECK: %[[INDEX_2:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_2:.*]] = dxsa.operand %[[INDEX_2]] {mask = 32 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_3:.*]] = dxsa.index.imm {imm = 3 : i32} +// CHECK: %[[OPERAND_3:.*]] = dxsa.operand %[[INDEX_3]] {num_components = 4 : i32, one = 0 : i32, type = 0 : i32} +// CHECK: dxsa.instruction "check_access_fully_mapped" %[[OPERAND_2]], %[[OPERAND_3]] +// CHECK: dxsa.utof r<0, >, r<0, > +// CHECK: dxsa.add o<0>, r<0, >, r<0, > +// CHECK: dxsa.instruction "ret" + diff --git a/mlir/test/Target/DXSA/hlsl/sample_cmp2.test b/mlir/test/Target/DXSA/hlsl/sample_cmp2.test new file mode 100644 index 000000000000..00aeaac4f279 --- /dev/null +++ b/mlir/test/Target/DXSA/hlsl/sample_cmp2.test @@ -0,0 +1,38 @@ +// RUN: mlir-translate --import-dxsa-bin %S/inputs/sample_cmp2.bin | FileCheck %s +// NOTE: Assertions have been autogenerated by utils/generate-test-checks.py + +// This script is intended to make adding checks to a test case quick and easy. +// It is *not* authoritative about what constitutes a good test. After using the +// script, be sure to review and refine the generated checks. For example, +// CHECK lines should be minimized and named to reflect the test’s intent. +// For comprehensive guidelines, see: +// * https://mlir.llvm.org/getting_started/TestingGuide/ + + +// CHECK-LABEL: dxsa.dcl_global_flags +// CHECK: dxsa.dcl_sampler +// CHECK: dxsa.dcl_resource , , +// CHECK: dxsa.dcl_input_ps linear v<0, > +// CHECK: dxsa.dcl_output o<0> +// CHECK: dxsa.dcl_temps 2 +// CHECK: dxsa.add r<0, >, v<0, >, v<0, > +// CHECK: dxsa.ftou r<0, >, r<0, > +// CHECK: dxsa.utof r<0, >, r<0, > +// CHECK: dxsa.unknown +// CHECK: dxsa.unknown +// CHECK: dxsa.add r<0, >, r<0, >, r<0, > +// CHECK: dxsa.unknown +// CHECK: dxsa.unknown +// CHECK: dxsa.add r<0, >, r<0, >, r<0, > +// CHECK: dxsa.add r<0, >, r<0, >, r<0, > +// CHECK: %[[INDEX_0:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_0:.*]] = dxsa.operand %[[INDEX_0]] {mask = 64 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_1:.*]] = dxsa.index.imm {imm = 1 : i32} +// CHECK: %[[OPERAND_1:.*]] = dxsa.operand %[[INDEX_1]] {num_components = 4 : i32, one = 0 : i32, type = 0 : i32} +// CHECK: dxsa.instruction "check_access_fully_mapped" %[[OPERAND_0]], %[[OPERAND_1]] +// CHECK: dxsa.utof r<0, >, r<0, > +// CHECK: dxsa.add r<0, >, r<0, >, r<0, > +// CHECK: dxsa.add r<0, >, r<0, >, r<0, > +// CHECK: dxsa.add o<0>, r<0, >, r<0, > +// CHECK: dxsa.instruction "ret" + diff --git a/mlir/test/Target/DXSA/hlsl/sample_grad1.test b/mlir/test/Target/DXSA/hlsl/sample_grad1.test new file mode 100644 index 000000000000..54930da05061 --- /dev/null +++ b/mlir/test/Target/DXSA/hlsl/sample_grad1.test @@ -0,0 +1,42 @@ +// RUN: mlir-translate --import-dxsa-bin %S/inputs/sample_grad1.bin | FileCheck %s +// NOTE: Assertions have been autogenerated by utils/generate-test-checks.py + +// This script is intended to make adding checks to a test case quick and easy. +// It is *not* authoritative about what constitutes a good test. After using the +// script, be sure to review and refine the generated checks. For example, +// CHECK lines should be minimized and named to reflect the test’s intent. +// For comprehensive guidelines, see: +// * https://mlir.llvm.org/getting_started/TestingGuide/ + + +// CHECK-LABEL: dxsa.dcl_global_flags +// CHECK: dxsa.dcl_sampler +// CHECK: dxsa.dcl_resource , , +// CHECK: dxsa.dcl_input_ps linear v<0, > +// CHECK: dxsa.dcl_output o<0> +// CHECK: dxsa.dcl_temps 3 +// CHECK: dxsa.unknown +// CHECK: dxsa.unknown +// CHECK: dxsa.add r<0>, r<0>, r<1> +// CHECK: dxsa.unknown +// CHECK: dxsa.add r<0>, r<0>, r<1> +// CHECK: dxsa.unknown +// CHECK: dxsa.add r<0>, r<0>, r<1> +// CHECK: %[[INDEX_0:.*]] = dxsa.index.imm {imm = 1 : i32} +// CHECK: %[[OPERAND_0:.*]] = dxsa.operand %[[INDEX_0]] {mask = 16 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_1:.*]] = dxsa.index.imm {imm = 2 : i32} +// CHECK: %[[OPERAND_1:.*]] = dxsa.operand %[[INDEX_1]] {num_components = 4 : i32, one = 0 : i32, type = 0 : i32} +// CHECK: dxsa.instruction "check_access_fully_mapped" %[[OPERAND_0]], %[[OPERAND_1]] +// CHECK: dxsa.utof r<1, >, r<1, > +// CHECK: dxsa.add r<0>, r<0>, r<1, > +// CHECK: dxsa.unknown +// CHECK: dxsa.add r<0>, r<0>, r<1> +// CHECK: %[[INDEX_2:.*]] = dxsa.index.imm {imm = 1 : i32} +// CHECK: %[[OPERAND_2:.*]] = dxsa.operand %[[INDEX_2]] {mask = 16 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_3:.*]] = dxsa.index.imm {imm = 2 : i32} +// CHECK: %[[OPERAND_3:.*]] = dxsa.operand %[[INDEX_3]] {num_components = 4 : i32, one = 0 : i32, type = 0 : i32} +// CHECK: dxsa.instruction "check_access_fully_mapped" %[[OPERAND_2]], %[[OPERAND_3]] +// CHECK: dxsa.utof r<1, >, r<1, > +// CHECK: dxsa.add o<0>, r<0>, r<1, > +// CHECK: dxsa.instruction "ret" + diff --git a/mlir/test/Target/DXSA/hlsl/sample_l1.test b/mlir/test/Target/DXSA/hlsl/sample_l1.test new file mode 100644 index 000000000000..ce27dd701c27 --- /dev/null +++ b/mlir/test/Target/DXSA/hlsl/sample_l1.test @@ -0,0 +1,49 @@ +// RUN: mlir-translate --import-dxsa-bin %S/inputs/sample_l1.bin | FileCheck %s +// NOTE: Assertions have been autogenerated by utils/generate-test-checks.py + +// This script is intended to make adding checks to a test case quick and easy. +// It is *not* authoritative about what constitutes a good test. After using the +// script, be sure to review and refine the generated checks. For example, +// CHECK lines should be minimized and named to reflect the test’s intent. +// For comprehensive guidelines, see: +// * https://mlir.llvm.org/getting_started/TestingGuide/ + + +// CHECK-LABEL: dxsa.dcl_global_flags +// CHECK: dxsa.dcl_sampler +// CHECK: dxsa.dcl_resource , , +// CHECK: dxsa.dcl_resource , , +// CHECK: dxsa.dcl_input_ps linear v<0> +// CHECK: dxsa.dcl_output o<0> +// CHECK: dxsa.dcl_temps 3 +// CHECK: dxsa.unknown +// CHECK: dxsa.unknown +// CHECK: dxsa.add r<0>, r<0>, r<1> +// CHECK: dxsa.unknown +// CHECK: dxsa.add r<0>, r<0>, r<1> +// CHECK: dxsa.unknown +// CHECK: dxsa.add r<0>, r<0>, r<1> +// CHECK: %[[INDEX_0:.*]] = dxsa.index.imm {imm = 2 : i32} +// CHECK: %[[OPERAND_0:.*]] = dxsa.operand %[[INDEX_0]] {mask = 16 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_1:.*]] = dxsa.index.imm {imm = 2 : i32} +// CHECK: %[[OPERAND_1:.*]] = dxsa.operand %[[INDEX_1]] {num_components = 4 : i32, one = 0 : i32, type = 0 : i32} +// CHECK: dxsa.instruction "check_access_fully_mapped" %[[OPERAND_0]], %[[OPERAND_1]] +// CHECK: dxsa.utof r<2, >, r<2, > +// CHECK: dxsa.add r<0>, r<0>, r<2, > +// CHECK: dxsa.add r<0>, r<1>, r<0> +// CHECK: dxsa.add r<0>, r<2, >, r<0> +// CHECK: dxsa.unknown +// CHECK: dxsa.mad r<0>, r<1>, l(0x40400000, 0x40400000, 0x40400000, 0x40400000), r<0> +// CHECK: dxsa.unknown +// CHECK: dxsa.add r<0>, r<0>, r<1> +// CHECK: %[[INDEX_2:.*]] = dxsa.index.imm {imm = 2 : i32} +// CHECK: %[[OPERAND_2:.*]] = dxsa.operand %[[INDEX_2]] {mask = 16 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_3:.*]] = dxsa.index.imm {imm = 2 : i32} +// CHECK: %[[OPERAND_3:.*]] = dxsa.operand %[[INDEX_3]] {num_components = 4 : i32, one = 0 : i32, type = 0 : i32} +// CHECK: dxsa.instruction "check_access_fully_mapped" %[[OPERAND_2]], %[[OPERAND_3]] +// CHECK: dxsa.utof r<2, >, r<2, > +// CHECK: dxsa.add r<0>, r<0>, r<2, > +// CHECK: dxsa.add r<0>, r<1>, r<0> +// CHECK: dxsa.add o<0>, r<2, >, r<0> +// CHECK: dxsa.instruction "ret" + diff --git a/mlir/test/Target/DXSA/hlsl/samplecount.test b/mlir/test/Target/DXSA/hlsl/samplecount.test new file mode 100644 index 000000000000..65bd246aed6d --- /dev/null +++ b/mlir/test/Target/DXSA/hlsl/samplecount.test @@ -0,0 +1,23 @@ +// RUN: mlir-translate --import-dxsa-bin %S/inputs/samplecount.bin | FileCheck %s +// NOTE: Assertions have been autogenerated by utils/generate-test-checks.py + +// This script is intended to make adding checks to a test case quick and easy. +// It is *not* authoritative about what constitutes a good test. After using the +// script, be sure to review and refine the generated checks. For example, +// CHECK lines should be minimized and named to reflect the test’s intent. +// For comprehensive guidelines, see: +// * https://mlir.llvm.org/getting_started/TestingGuide/ + + +// CHECK-LABEL: dxsa.dcl_global_flags +// CHECK: dxsa.dcl_output o<0> +// CHECK: %[[INDEX_0:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_0:.*]] = dxsa.operand %[[INDEX_0]] {mask = 48 : i32, num_components = 4 : i32, type = 2 : i32} +// CHECK: %[[OPERAND_1:.*]] = dxsa.operand {num_components = 4 : i32, one = 0 : i32, type = 14 : i32} +// CHECK: dxsa.instruction "sampleinfo" %[[OPERAND_0]], %[[OPERAND_1]] +// CHECK: %[[INDEX_1:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_2:.*]] = dxsa.operand %[[INDEX_1]] {mask = 192 : i32, num_components = 4 : i32, type = 2 : i32} +// CHECK: %[[OPERAND_3:.*]] = dxsa.operand.imm {imm = dense<0> : vector<4xi32>} +// CHECK: dxsa.instruction "mov" %[[OPERAND_2]], %[[OPERAND_3]] +// CHECK: dxsa.instruction "ret" + diff --git a/mlir/test/Target/DXSA/hlsl/samplepos.test b/mlir/test/Target/DXSA/hlsl/samplepos.test new file mode 100644 index 000000000000..4161bb9f4ffd --- /dev/null +++ b/mlir/test/Target/DXSA/hlsl/samplepos.test @@ -0,0 +1,51 @@ +// RUN: mlir-translate --import-dxsa-bin %S/inputs/samplepos.bin | FileCheck %s +// NOTE: Assertions have been autogenerated by utils/generate-test-checks.py + +// This script is intended to make adding checks to a test case quick and easy. +// It is *not* authoritative about what constitutes a good test. After using the +// script, be sure to review and refine the generated checks. For example, +// CHECK lines should be minimized and named to reflect the test’s intent. +// For comprehensive guidelines, see: +// * https://mlir.llvm.org/getting_started/TestingGuide/ + + +// CHECK-LABEL: dxsa.dcl_global_flags +// CHECK: dxsa.unknown +// CHECK: dxsa.unknown +// CHECK: dxsa.dcl_input_ps linear v<0, > +// CHECK: dxsa.dcl_output o<0> +// CHECK: dxsa.dcl_output o<1> +// CHECK: dxsa.dcl_temps 2 +// CHECK: dxsa.ftoi r<0, >, v<0, > +// CHECK: dxsa.unknown +// CHECK: dxsa.unknown +// CHECK: %[[INDEX_0:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_0:.*]] = dxsa.operand %[[INDEX_0]] {mask = 96 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[OPERAND_1:.*]] = dxsa.operand {num_components = 4 : i32, swizzle = dense<[0, 0, 1, 0]> : vector<4xi32>, type = 14 : i32} +// CHECK: %[[INDEX_1:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_2:.*]] = dxsa.operand %[[INDEX_1]] {num_components = 4 : i32, one = 2 : i32, type = 0 : i32} +// CHECK: dxsa.instruction "samplepos" %[[OPERAND_0]], %[[OPERAND_1]], %[[OPERAND_2]] +// CHECK: dxsa.add r<0, >, r<0, >, r<1, > +// CHECK: %[[INDEX_2:.*]] = dxsa.index.imm {imm = 1 : i32} +// CHECK: %[[OPERAND_3:.*]] = dxsa.operand %[[INDEX_2]] {mask = 48 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[OPERAND_4:.*]] = dxsa.operand {num_components = 4 : i32, swizzle = dense<[0, 1, 0, 0]> : vector<4xi32>, type = 14 : i32} +// CHECK: %[[OPERAND_5:.*]] = dxsa.operand.imm {imm = dense<3> : vector<1xi32>} +// CHECK: dxsa.instruction "samplepos" %[[OPERAND_3]], %[[OPERAND_4]], %[[OPERAND_5]] +// CHECK: dxsa.add r<0, >, r<0, >, r<1, > +// CHECK: dxsa.add r<0, >, r<0, >, r<0, > +// CHECK: %[[INDEX_3:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_6:.*]] = dxsa.operand %[[INDEX_3]] {mask = 48 : i32, num_components = 4 : i32, type = 2 : i32} +// CHECK: %[[INDEX_4:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_7:.*]] = dxsa.operand %[[INDEX_4]] {num_components = 4 : i32, swizzle = dense<[0, 1, 0, 0]> : vector<4xi32>, type = 0 : i32} +// CHECK: dxsa.instruction "mov" %[[OPERAND_6]], %[[OPERAND_7]] +// CHECK: dxsa.add o<1, >, r<0, >, l(0x40A00000, 0x40A00000, 0x0, 0x0) +// CHECK: %[[INDEX_5:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_8:.*]] = dxsa.operand %[[INDEX_5]] {mask = 192 : i32, num_components = 4 : i32, type = 2 : i32} +// CHECK: %[[OPERAND_9:.*]] = dxsa.operand.imm {imm = dense<0> : vector<4xi32>} +// CHECK: dxsa.instruction "mov" %[[OPERAND_8]], %[[OPERAND_9]] +// CHECK: %[[INDEX_6:.*]] = dxsa.index.imm {imm = 1 : i32} +// CHECK: %[[OPERAND_10:.*]] = dxsa.operand %[[INDEX_6]] {mask = 192 : i32, num_components = 4 : i32, type = 2 : i32} +// CHECK: %[[OPERAND_11:.*]] = dxsa.operand.imm {imm = dense<[0, 0, 1084227584, 1084227584]> : vector<4xi32>} +// CHECK: dxsa.instruction "mov" %[[OPERAND_10]], %[[OPERAND_11]] +// CHECK: dxsa.instruction "ret" + diff --git a/mlir/test/Target/DXSA/hlsl/saturate1.test b/mlir/test/Target/DXSA/hlsl/saturate1.test new file mode 100644 index 000000000000..487c3918283f --- /dev/null +++ b/mlir/test/Target/DXSA/hlsl/saturate1.test @@ -0,0 +1,21 @@ +// RUN: mlir-translate --import-dxsa-bin %S/inputs/saturate1.bin | FileCheck %s +// NOTE: Assertions have been autogenerated by utils/generate-test-checks.py + +// This script is intended to make adding checks to a test case quick and easy. +// It is *not* authoritative about what constitutes a good test. After using the +// script, be sure to review and refine the generated checks. For example, +// CHECK lines should be minimized and named to reflect the test’s intent. +// For comprehensive guidelines, see: +// * https://mlir.llvm.org/getting_started/TestingGuide/ + + +// CHECK-LABEL: dxsa.dcl_global_flags +// CHECK: dxsa.dcl_input_ps linear v<0, > +// CHECK: dxsa.dcl_output o<0, > +// CHECK: %[[INDEX_0:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_0:.*]] = dxsa.operand %[[INDEX_0]] {mask = 112 : i32, num_components = 4 : i32, type = 2 : i32} +// CHECK: %[[INDEX_1:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_1:.*]] = dxsa.operand %[[INDEX_1]] {num_components = 4 : i32, swizzle = dense<[0, 2, 0, 0]> : vector<4xi32>, type = 1 : i32} +// CHECK: dxsa.instruction "mov" %[[OPERAND_0]], %[[OPERAND_1]] +// CHECK: dxsa.instruction "ret" + diff --git a/mlir/test/Target/DXSA/hlsl/shift1.test b/mlir/test/Target/DXSA/hlsl/shift1.test new file mode 100644 index 000000000000..80bcfeff5634 --- /dev/null +++ b/mlir/test/Target/DXSA/hlsl/shift1.test @@ -0,0 +1,60 @@ +// RUN: mlir-translate --import-dxsa-bin %S/inputs/shift1.bin | FileCheck %s +// NOTE: Assertions have been autogenerated by utils/generate-test-checks.py + +// This script is intended to make adding checks to a test case quick and easy. +// It is *not* authoritative about what constitutes a good test. After using the +// script, be sure to review and refine the generated checks. For example, +// CHECK lines should be minimized and named to reflect the test’s intent. +// For comprehensive guidelines, see: +// * https://mlir.llvm.org/getting_started/TestingGuide/ + + +// CHECK-LABEL: dxsa.dcl_global_flags +// CHECK: dxsa.dcl_input_ps constant v<0, > +// CHECK: dxsa.dcl_input_ps constant v<0, > +// CHECK: dxsa.dcl_input_ps constant v<0, > +// CHECK: dxsa.dcl_output o<0, > +// CHECK: dxsa.dcl_temps 1 +// CHECK: dxsa.ishl r<0, >, v<0, >, l(0x4D) +// CHECK: dxsa.ishr r<0, >, v<0, >, l(0x3) +// CHECK: %[[INDEX_0:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_0:.*]] = dxsa.operand %[[INDEX_0]] {mask = 16 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_1:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_1:.*]] = dxsa.operand %[[INDEX_1]] {num_components = 4 : i32, one = 1 : i32, type = 0 : i32} +// CHECK: %[[INDEX_2:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_2:.*]] = dxsa.operand %[[INDEX_2]] {num_components = 4 : i32, one = 0 : i32, type = 0 : i32} +// CHECK: dxsa.instruction "iadd" %[[OPERAND_0]], %[[OPERAND_1]], %[[OPERAND_2]] +// CHECK: dxsa.ushr r<0, >, v<0, >, l(0x8) +// CHECK: %[[INDEX_3:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_3:.*]] = dxsa.operand %[[INDEX_3]] {mask = 16 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_4:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_4:.*]] = dxsa.operand %[[INDEX_4]] {num_components = 4 : i32, one = 1 : i32, type = 0 : i32} +// CHECK: %[[INDEX_5:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_5:.*]] = dxsa.operand %[[INDEX_5]] {num_components = 4 : i32, one = 0 : i32, type = 0 : i32} +// CHECK: dxsa.instruction "iadd" %[[OPERAND_3]], %[[OPERAND_4]], %[[OPERAND_5]] +// CHECK: dxsa.ishl r<0, >, v<0, >, v<0, > +// CHECK: %[[INDEX_6:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_6:.*]] = dxsa.operand %[[INDEX_6]] {mask = 16 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_7:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_7:.*]] = dxsa.operand %[[INDEX_7]] {num_components = 4 : i32, one = 1 : i32, type = 0 : i32} +// CHECK: %[[INDEX_8:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_8:.*]] = dxsa.operand %[[INDEX_8]] {num_components = 4 : i32, one = 0 : i32, type = 0 : i32} +// CHECK: dxsa.instruction "iadd" %[[OPERAND_6]], %[[OPERAND_7]], %[[OPERAND_8]] +// CHECK: dxsa.ishr r<0, >, v<0, >, v<0, > +// CHECK: %[[INDEX_9:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_9:.*]] = dxsa.operand %[[INDEX_9]] {mask = 16 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_10:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_10:.*]] = dxsa.operand %[[INDEX_10]] {num_components = 4 : i32, one = 1 : i32, type = 0 : i32} +// CHECK: %[[INDEX_11:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_11:.*]] = dxsa.operand %[[INDEX_11]] {num_components = 4 : i32, one = 0 : i32, type = 0 : i32} +// CHECK: dxsa.instruction "iadd" %[[OPERAND_9]], %[[OPERAND_10]], %[[OPERAND_11]] +// CHECK: dxsa.ushr r<0, >, v<0, >, v<0, > +// CHECK: %[[INDEX_12:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_12:.*]] = dxsa.operand %[[INDEX_12]] {mask = 16 : i32, num_components = 4 : i32, type = 2 : i32} +// CHECK: %[[INDEX_13:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_13:.*]] = dxsa.operand %[[INDEX_13]] {num_components = 4 : i32, one = 1 : i32, type = 0 : i32} +// CHECK: %[[INDEX_14:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_14:.*]] = dxsa.operand %[[INDEX_14]] {num_components = 4 : i32, one = 0 : i32, type = 0 : i32} +// CHECK: dxsa.instruction "iadd" %[[OPERAND_12]], %[[OPERAND_13]], %[[OPERAND_14]] +// CHECK: dxsa.instruction "ret" + diff --git a/mlir/test/Target/DXSA/hlsl/sincos.test b/mlir/test/Target/DXSA/hlsl/sincos.test new file mode 100644 index 000000000000..6b27752e0579 --- /dev/null +++ b/mlir/test/Target/DXSA/hlsl/sincos.test @@ -0,0 +1,22 @@ +// RUN: mlir-translate --import-dxsa-bin %S/inputs/sincos.bin | FileCheck %s +// NOTE: Assertions have been autogenerated by utils/generate-test-checks.py + +// This script is intended to make adding checks to a test case quick and easy. +// It is *not* authoritative about what constitutes a good test. After using the +// script, be sure to review and refine the generated checks. For example, +// CHECK lines should be minimized and named to reflect the test’s intent. +// For comprehensive guidelines, see: +// * https://mlir.llvm.org/getting_started/TestingGuide/ + + +// CHECK-LABEL: dxsa.dcl_global_flags +// CHECK: dxsa.dcl_input v<0> +// CHECK: dxsa.dcl_output_siv o<0>, +// CHECK: dxsa.dcl_temps 3 +// CHECK: dxsa.add r<0, >, v<0, >, v<0, > +// CHECK: dxsa.sincos r<0, >, null, r<0, > +// CHECK: dxsa.sincos r<1>, r<2>, v<0> +// CHECK: dxsa.add r<1>, r<1>, r<2> +// CHECK: dxsa.add o<0>, r<0, >, r<1> +// CHECK: dxsa.instruction "ret" + diff --git a/mlir/test/Target/DXSA/hlsl/snorm1.test b/mlir/test/Target/DXSA/hlsl/snorm1.test new file mode 100644 index 000000000000..b5704f41195f --- /dev/null +++ b/mlir/test/Target/DXSA/hlsl/snorm1.test @@ -0,0 +1,23 @@ +// RUN: mlir-translate --import-dxsa-bin %S/inputs/snorm1.bin | FileCheck %s +// NOTE: Assertions have been autogenerated by utils/generate-test-checks.py + +// This script is intended to make adding checks to a test case quick and easy. +// It is *not* authoritative about what constitutes a good test. After using the +// script, be sure to review and refine the generated checks. For example, +// CHECK lines should be minimized and named to reflect the test’s intent. +// For comprehensive guidelines, see: +// * https://mlir.llvm.org/getting_started/TestingGuide/ + + +// CHECK-LABEL: dxsa.dcl_global_flags +// CHECK: dxsa.dcl_sampler +// CHECK: dxsa.dcl_resource , , +// CHECK: dxsa.dcl_resource , , +// CHECK: dxsa.dcl_input_ps linear v<0, > +// CHECK: dxsa.dcl_output o<0> +// CHECK: dxsa.dcl_temps 2 +// CHECK: dxsa.unknown +// CHECK: dxsa.unknown +// CHECK: dxsa.add o<0>, r<0>, r<1, > +// CHECK: dxsa.instruction "ret" + diff --git a/mlir/test/Target/DXSA/hlsl/srv_ms_load1.test b/mlir/test/Target/DXSA/hlsl/srv_ms_load1.test new file mode 100644 index 000000000000..061f0fb1a1af --- /dev/null +++ b/mlir/test/Target/DXSA/hlsl/srv_ms_load1.test @@ -0,0 +1,63 @@ +// RUN: mlir-translate --import-dxsa-bin %S/inputs/srv_ms_load1.bin | FileCheck %s +// NOTE: Assertions have been autogenerated by utils/generate-test-checks.py + +// This script is intended to make adding checks to a test case quick and easy. +// It is *not* authoritative about what constitutes a good test. After using the +// script, be sure to review and refine the generated checks. For example, +// CHECK lines should be minimized and named to reflect the test’s intent. +// For comprehensive guidelines, see: +// * https://mlir.llvm.org/getting_started/TestingGuide/ + + +// CHECK-LABEL: dxsa.dcl_global_flags +// CHECK: dxsa.unknown +// CHECK: dxsa.dcl_input_ps constant v<0, > +// CHECK: dxsa.dcl_input_ps constant v<0, > +// CHECK: dxsa.dcl_input_ps constant v<1, > +// CHECK: dxsa.dcl_output o<0, > +// CHECK: dxsa.dcl_temps 4 +// CHECK: %[[INDEX_0:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_0:.*]] = dxsa.operand %[[INDEX_0]] {mask = 48 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_1:.*]] = dxsa.index.imm {imm = 1 : i32} +// CHECK: %[[OPERAND_1:.*]] = dxsa.operand %[[INDEX_1]] {num_components = 4 : i32, swizzle = dense<[0, 1, 0, 0]> : vector<4xi32>, type = 1 : i32} +// CHECK: dxsa.instruction "mov" %[[OPERAND_0]], %[[OPERAND_1]] +// CHECK: %[[INDEX_2:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_2:.*]] = dxsa.operand %[[INDEX_2]] {mask = 192 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[OPERAND_3:.*]] = dxsa.operand.imm {imm = dense<0> : vector<4xi32>} +// CHECK: dxsa.instruction "mov" %[[OPERAND_2]], %[[OPERAND_3]] +// CHECK: dxsa.unknown +// CHECK: %[[INDEX_3:.*]] = dxsa.index.imm {imm = 1 : i32} +// CHECK: %[[OPERAND_4:.*]] = dxsa.operand %[[INDEX_3]] {mask = 48 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_4:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_5:.*]] = dxsa.operand %[[INDEX_4]] {num_components = 4 : i32, swizzle = dense<[0, 1, 0, 0]> : vector<4xi32>, type = 1 : i32} +// CHECK: dxsa.instruction "mov" %[[OPERAND_4]], %[[OPERAND_5]] +// CHECK: %[[INDEX_5:.*]] = dxsa.index.imm {imm = 1 : i32} +// CHECK: %[[OPERAND_6:.*]] = dxsa.operand %[[INDEX_5]] {mask = 192 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[OPERAND_7:.*]] = dxsa.operand.imm {imm = dense<0> : vector<4xi32>} +// CHECK: dxsa.instruction "mov" %[[OPERAND_6]], %[[OPERAND_7]] +// CHECK: dxsa.unknown +// CHECK: dxsa.add r<0, >, r<0, >, r<2, > +// CHECK: dxsa.unknown +// CHECK: dxsa.add r<0, >, r<0, >, r<2, > +// CHECK: dxsa.unknown +// CHECK: dxsa.add r<0, >, r<0, >, r<2, > +// CHECK: %[[INDEX_6:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_8:.*]] = dxsa.operand %[[INDEX_6]] {mask = 128 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_7:.*]] = dxsa.index.imm {imm = 3 : i32} +// CHECK: %[[OPERAND_9:.*]] = dxsa.operand %[[INDEX_7]] {num_components = 4 : i32, one = 0 : i32, type = 0 : i32} +// CHECK: dxsa.instruction "check_access_fully_mapped" %[[OPERAND_8]], %[[OPERAND_9]] +// CHECK: dxsa.utof r<0, >, r<0, > +// CHECK: dxsa.add r<0, >, r<0, >, r<0, > +// CHECK: dxsa.unknown +// CHECK: dxsa.unknown +// CHECK: dxsa.add r<0, >, r<0, >, r<2, > +// CHECK: %[[INDEX_8:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_10:.*]] = dxsa.operand %[[INDEX_8]] {mask = 128 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_9:.*]] = dxsa.index.imm {imm = 3 : i32} +// CHECK: %[[OPERAND_11:.*]] = dxsa.operand %[[INDEX_9]] {num_components = 4 : i32, one = 0 : i32, type = 0 : i32} +// CHECK: dxsa.instruction "check_access_fully_mapped" %[[OPERAND_10]], %[[OPERAND_11]] +// CHECK: dxsa.utof r<0, >, r<0, > +// CHECK: dxsa.add r<0, >, r<0, >, r<0, > +// CHECK: dxsa.add o<0, >, r<1, >, r<0, > +// CHECK: dxsa.instruction "ret" + diff --git a/mlir/test/Target/DXSA/hlsl/srv_typed_load1.test b/mlir/test/Target/DXSA/hlsl/srv_typed_load1.test new file mode 100644 index 000000000000..accb67047544 --- /dev/null +++ b/mlir/test/Target/DXSA/hlsl/srv_typed_load1.test @@ -0,0 +1,48 @@ +// RUN: mlir-translate --import-dxsa-bin %S/inputs/srv_typed_load1.bin | FileCheck %s +// NOTE: Assertions have been autogenerated by utils/generate-test-checks.py + +// This script is intended to make adding checks to a test case quick and easy. +// It is *not* authoritative about what constitutes a good test. After using the +// script, be sure to review and refine the generated checks. For example, +// CHECK lines should be minimized and named to reflect the test’s intent. +// For comprehensive guidelines, see: +// * https://mlir.llvm.org/getting_started/TestingGuide/ + + +// CHECK-LABEL: dxsa.dcl_global_flags +// CHECK: dxsa.dcl_resource , , +// CHECK: dxsa.dcl_input_ps linear v<0, > +// CHECK: dxsa.dcl_input_ps linear v<1, > +// CHECK: dxsa.dcl_output o<0> +// CHECK: dxsa.dcl_temps 5 +// CHECK: dxsa.ftou r<0, >, v<1, > +// CHECK: %[[INDEX_0:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_0:.*]] = dxsa.operand %[[INDEX_0]] {mask = 192 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[OPERAND_1:.*]] = dxsa.operand.imm {imm = dense<0> : vector<4xi32>} +// CHECK: dxsa.instruction "mov" %[[OPERAND_0]], %[[OPERAND_1]] +// CHECK: dxsa.unknown +// CHECK: dxsa.ftoi r<1>, v<0, > +// CHECK: dxsa.unknown +// CHECK: dxsa.add r<0>, r<0>, r<2> +// CHECK: dxsa.unknown +// CHECK: dxsa.add r<0>, r<0>, r<2> +// CHECK: dxsa.unknown +// CHECK: dxsa.unknown +// CHECK: dxsa.add r<0>, r<0>, r<2> +// CHECK: %[[INDEX_1:.*]] = dxsa.index.imm {imm = 2 : i32} +// CHECK: %[[OPERAND_2:.*]] = dxsa.operand %[[INDEX_1]] {mask = 16 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_2:.*]] = dxsa.index.imm {imm = 3 : i32} +// CHECK: %[[OPERAND_3:.*]] = dxsa.operand %[[INDEX_2]] {num_components = 4 : i32, one = 0 : i32, type = 0 : i32} +// CHECK: dxsa.instruction "check_access_fully_mapped" %[[OPERAND_2]], %[[OPERAND_3]] +// CHECK: dxsa.utof r<2, >, r<2, > +// CHECK: dxsa.add r<0>, r<0>, r<2, > +// CHECK: dxsa.add r<0>, r<1>, r<0> +// CHECK: %[[INDEX_3:.*]] = dxsa.index.imm {imm = 1 : i32} +// CHECK: %[[OPERAND_4:.*]] = dxsa.operand %[[INDEX_3]] {mask = 16 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_4:.*]] = dxsa.index.imm {imm = 4 : i32} +// CHECK: %[[OPERAND_5:.*]] = dxsa.operand %[[INDEX_4]] {num_components = 4 : i32, one = 0 : i32, type = 0 : i32} +// CHECK: dxsa.instruction "check_access_fully_mapped" %[[OPERAND_4]], %[[OPERAND_5]] +// CHECK: dxsa.utof r<1, >, r<1, > +// CHECK: dxsa.add o<0>, r<0>, r<1, > +// CHECK: dxsa.instruction "ret" + diff --git a/mlir/test/Target/DXSA/hlsl/srv_typed_load2.test b/mlir/test/Target/DXSA/hlsl/srv_typed_load2.test new file mode 100644 index 000000000000..eed1cabbc9aa --- /dev/null +++ b/mlir/test/Target/DXSA/hlsl/srv_typed_load2.test @@ -0,0 +1,28 @@ +// RUN: mlir-translate --import-dxsa-bin %S/inputs/srv_typed_load2.bin | FileCheck %s +// NOTE: Assertions have been autogenerated by utils/generate-test-checks.py + +// This script is intended to make adding checks to a test case quick and easy. +// It is *not* authoritative about what constitutes a good test. After using the +// script, be sure to review and refine the generated checks. For example, +// CHECK lines should be minimized and named to reflect the test’s intent. +// For comprehensive guidelines, see: +// * https://mlir.llvm.org/getting_started/TestingGuide/ + + +// CHECK-LABEL: dxsa.dcl_global_flags +// CHECK: dxsa.dcl_resource , , +// CHECK: dxsa.dcl_input_ps constant v<0, > +// CHECK: dxsa.dcl_output o<0> +// CHECK: dxsa.dcl_temps 3 +// CHECK: dxsa.unknown +// CHECK: dxsa.unknown +// CHECK: dxsa.mad r<0>, r<0>, l(0x40000000, 0x40000000, 0x40000000, 0x40000000), r<1> +// CHECK: %[[INDEX_0:.*]] = dxsa.index.imm {imm = 1 : i32} +// CHECK: %[[OPERAND_0:.*]] = dxsa.operand %[[INDEX_0]] {mask = 16 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_1:.*]] = dxsa.index.imm {imm = 2 : i32} +// CHECK: %[[OPERAND_1:.*]] = dxsa.operand %[[INDEX_1]] {num_components = 4 : i32, one = 0 : i32, type = 0 : i32} +// CHECK: dxsa.instruction "check_access_fully_mapped" %[[OPERAND_0]], %[[OPERAND_1]] +// CHECK: dxsa.utof r<1, >, r<1, > +// CHECK: dxsa.add o<0>, r<0>, r<1, > +// CHECK: dxsa.instruction "ret" + diff --git a/mlir/test/Target/DXSA/hlsl/struct_buf1.test b/mlir/test/Target/DXSA/hlsl/struct_buf1.test new file mode 100644 index 000000000000..ffa897cdb829 --- /dev/null +++ b/mlir/test/Target/DXSA/hlsl/struct_buf1.test @@ -0,0 +1,347 @@ +// RUN: mlir-translate --import-dxsa-bin %S/inputs/struct_buf1.bin | FileCheck %s +// NOTE: Assertions have been autogenerated by utils/generate-test-checks.py + +// This script is intended to make adding checks to a test case quick and easy. +// It is *not* authoritative about what constitutes a good test. After using the +// script, be sure to review and refine the generated checks. For example, +// CHECK lines should be minimized and named to reflect the test’s intent. +// For comprehensive guidelines, see: +// * https://mlir.llvm.org/getting_started/TestingGuide/ + + +// CHECK-LABEL: dxsa.dcl_global_flags +// CHECK: dxsa.dcl_resource_structured +// CHECK: dxsa.dcl_uav_structured +// CHECK: dxsa.dcl_input_ps linear v<0, > +// CHECK: dxsa.dcl_input_ps linear v<0, > +// CHECK: dxsa.dcl_output o<0> +// CHECK: dxsa.dcl_temps 22 +// CHECK: dxsa.add r<0, >, v<0, >, l(0x43480000, 0x43480000, 0x0, 0x0) +// CHECK: dxsa.ftoi r<0, >, r<0, > +// CHECK: dxsa.unknown +// CHECK: dxsa.unknown +// CHECK: dxsa.unknown +// CHECK: dxsa.unknown +// CHECK: dxsa.unknown +// CHECK: dxsa.unknown +// CHECK: dxsa.unknown +// CHECK: dxsa.unknown +// CHECK: dxsa.unknown +// CHECK: dxsa.unknown +// CHECK: dxsa.unknown +// CHECK: dxsa.unknown +// CHECK: %[[INDEX_0:.*]] = dxsa.index.imm {imm = 14 : i32} +// CHECK: %[[OPERAND_0:.*]] = dxsa.operand %[[INDEX_0]] {mask = 64 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[OPERAND_1:.*]] = dxsa.operand.imm {imm = dense<0> : vector<1xi32>} +// CHECK: dxsa.instruction "mov" %[[OPERAND_0]], %[[OPERAND_1]] +// CHECK: dxsa.ftou r<1, >, v<0, > +// CHECK: %[[INDEX_1:.*]] = dxsa.index.imm {imm = 5 : i32} +// CHECK: %[[OPERAND_2:.*]] = dxsa.operand %[[INDEX_1]] {mask = 64 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_2:.*]] = dxsa.index.imm {imm = 1 : i32} +// CHECK: %[[OPERAND_3:.*]] = dxsa.operand %[[INDEX_2]] {num_components = 4 : i32, one = 3 : i32, type = 0 : i32} +// CHECK: dxsa.instruction "ineg" %[[OPERAND_2]], %[[OPERAND_3]] +// CHECK: dxsa.ult r<7, >, r<1, >, l(0x0, 0x1, 0x2, 0x3) +// CHECK: dxsa.and r<5, >, r<5, >, r<7, > +// CHECK: dxsa.ftoi r<8, >, v<0, > +// CHECK: dxsa.unknown +// CHECK: %[[INDEX_3:.*]] = dxsa.index.imm {imm = 16 : i32} +// CHECK: %[[OPERAND_4:.*]] = dxsa.operand %[[INDEX_3]] {mask = 128 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_4:.*]] = dxsa.index.imm {imm = 15 : i32} +// CHECK: %[[OPERAND_5:.*]] = dxsa.operand %[[INDEX_4]] {num_components = 4 : i32, one = 1 : i32, type = 0 : i32} +// CHECK: dxsa.instruction "mov" %[[OPERAND_4]], %[[OPERAND_5]] +// CHECK: dxsa.unknown +// CHECK: dxsa.and r<9, >, r<5, >, r<16, > +// CHECK: dxsa.and r<11, >, r<7, >, r<16, > +// CHECK: dxsa.or r<9, >, r<9, >, r<11, > +// CHECK: %[[INDEX_5:.*]] = dxsa.index.imm {imm = 5 : i32} +// CHECK: %[[OPERAND_6:.*]] = dxsa.operand %[[INDEX_5]] {mask = 128 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_6:.*]] = dxsa.index.imm {imm = 1 : i32} +// CHECK: %[[OPERAND_7:.*]] = dxsa.operand %[[INDEX_6]] {num_components = 4 : i32, one = 3 : i32, type = 0 : i32} +// CHECK: %[[OPERAND_8:.*]] = dxsa.operand.imm {imm = dense<-3> : vector<1xi32>} +// CHECK: dxsa.instruction "iadd" %[[OPERAND_6]], %[[OPERAND_7]], %[[OPERAND_8]] +// CHECK: dxsa.ishl r<1, >, r<1, >, l(0x3) +// CHECK: %[[INDEX_7:.*]] = dxsa.index.imm {imm = 1 : i32} +// CHECK: %[[OPERAND_9:.*]] = dxsa.operand %[[INDEX_7]] {mask = 128 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_8:.*]] = dxsa.index.imm {imm = 1 : i32} +// CHECK: %[[OPERAND_10:.*]] = dxsa.operand %[[INDEX_8]] {num_components = 4 : i32, one = 3 : i32, type = 0 : i32} +// CHECK: %[[OPERAND_11:.*]] = dxsa.operand.imm {imm = dense<20> : vector<1xi32>} +// CHECK: dxsa.instruction "iadd" %[[OPERAND_9]], %[[OPERAND_10]], %[[OPERAND_11]] +// CHECK: %[[INDEX_9:.*]] = dxsa.index.imm {imm = 5 : i32} +// CHECK: %[[OPERAND_12:.*]] = dxsa.operand %[[INDEX_9]] {mask = 128 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_10:.*]] = dxsa.index.imm {imm = 7 : i32} +// CHECK: %[[OPERAND_13:.*]] = dxsa.operand %[[INDEX_10]] {num_components = 4 : i32, one = 2 : i32, type = 0 : i32} +// CHECK: %[[OPERAND_14:.*]] = dxsa.operand.imm {imm = dense<0> : vector<1xi32>} +// CHECK: %[[INDEX_11:.*]] = dxsa.index.imm {imm = 5 : i32} +// CHECK: %[[OPERAND_15:.*]] = dxsa.operand %[[INDEX_11]] {num_components = 4 : i32, one = 3 : i32, type = 0 : i32} +// CHECK: dxsa.instruction "movc" %[[OPERAND_12]], %[[OPERAND_13]], %[[OPERAND_14]], %[[OPERAND_15]] +// CHECK: dxsa.and r<11, >, r<15, >, r<5, > +// CHECK: dxsa.or r<9, >, r<9, >, r<11, > +// CHECK: dxsa.ieq r<7, >, r<7, >, l(0x0) +// CHECK: dxsa.unknown +// CHECK: dxsa.and r<11, >, r<7, >, r<15, > +// CHECK: dxsa.or r<9, >, r<9, >, r<11, > +// CHECK: dxsa.itof r<9, >, r<9, > +// CHECK: %[[INDEX_12:.*]] = dxsa.index.imm {imm = 15 : i32} +// CHECK: %[[OPERAND_16:.*]] = dxsa.operand %[[INDEX_12]] {mask = 64 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[OPERAND_17:.*]] = dxsa.operand.imm {imm = dense<0> : vector<1xi32>} +// CHECK: dxsa.instruction "mov" %[[OPERAND_16]], %[[OPERAND_17]] +// CHECK: dxsa.unknown +// CHECK: dxsa.unknown +// CHECK: dxsa.add r<14, >, r<11, >, r<15, > +// CHECK: dxsa.add r<15, >, r<9, >, r<14, > +// CHECK: %[[INDEX_13:.*]] = dxsa.index.imm {imm = 15 : i32} +// CHECK: %[[OPERAND_18:.*]] = dxsa.operand %[[INDEX_13]] {mask = 32 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_14:.*]] = dxsa.index.imm {imm = 14 : i32} +// CHECK: %[[OPERAND_19:.*]] = dxsa.operand %[[INDEX_14]] {num_components = 4 : i32, one = 0 : i32, type = 0 : i32} +// CHECK: dxsa.instruction "mov" %[[OPERAND_18]], %[[OPERAND_19]] +// CHECK: dxsa.unknown +// CHECK: dxsa.add r<14, >, r<15, >, r<16, > +// CHECK: %[[INDEX_15:.*]] = dxsa.index.imm {imm = 7 : i32} +// CHECK: %[[OPERAND_20:.*]] = dxsa.operand %[[INDEX_15]] {mask = 128 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_16:.*]] = dxsa.index.imm {imm = 17 : i32} +// CHECK: %[[OPERAND_21:.*]] = dxsa.operand %[[INDEX_16]] {num_components = 4 : i32, one = 0 : i32, type = 0 : i32} +// CHECK: dxsa.instruction "check_access_fully_mapped" %[[OPERAND_20]], %[[OPERAND_21]] +// CHECK: %[[INDEX_17:.*]] = dxsa.index.imm {imm = 16 : i32} +// CHECK: %[[OPERAND_22:.*]] = dxsa.operand %[[INDEX_17]] {mask = 48 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_18:.*]] = dxsa.index.imm {imm = 16 : i32} +// CHECK: %[[OPERAND_23:.*]] = dxsa.operand %[[INDEX_18]] {num_components = 4 : i32, swizzle = dense<[2, 3, 2, 2]> : vector<4xi32>, type = 0 : i32} +// CHECK: dxsa.instruction "mov" %[[OPERAND_22]], %[[OPERAND_23]] +// CHECK: dxsa.unknown +// CHECK: %[[INDEX_19:.*]] = dxsa.index.imm {imm = 8 : i32} +// CHECK: %[[OPERAND_24:.*]] = dxsa.operand %[[INDEX_19]] {mask = 32 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_20:.*]] = dxsa.index.imm {imm = 18 : i32} +// CHECK: %[[OPERAND_25:.*]] = dxsa.operand %[[INDEX_20]] {num_components = 4 : i32, one = 0 : i32, type = 0 : i32} +// CHECK: dxsa.instruction "check_access_fully_mapped" %[[OPERAND_24]], %[[OPERAND_25]] +// CHECK: dxsa.and r<7, >, r<7, >, r<8, > +// CHECK: dxsa.unknown +// CHECK: dxsa.unknown +// CHECK: %[[INDEX_21:.*]] = dxsa.index.imm {imm = 8 : i32} +// CHECK: %[[OPERAND_26:.*]] = dxsa.operand %[[INDEX_21]] {mask = 32 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_22:.*]] = dxsa.index.imm {imm = 19 : i32} +// CHECK: %[[OPERAND_27:.*]] = dxsa.operand %[[INDEX_22]] {num_components = 4 : i32, one = 0 : i32, type = 0 : i32} +// CHECK: dxsa.instruction "check_access_fully_mapped" %[[OPERAND_26]], %[[OPERAND_27]] +// CHECK: dxsa.and r<7, >, r<7, >, r<8, > +// CHECK: %[[INDEX_23:.*]] = dxsa.index.imm {imm = 8 : i32} +// CHECK: %[[OPERAND_28:.*]] = dxsa.operand %[[INDEX_23]] {mask = 32 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_24:.*]] = dxsa.index.imm {imm = 21 : i32} +// CHECK: %[[OPERAND_29:.*]] = dxsa.operand %[[INDEX_24]] {num_components = 4 : i32, one = 0 : i32, type = 0 : i32} +// CHECK: dxsa.instruction "check_access_fully_mapped" %[[OPERAND_28]], %[[OPERAND_29]] +// CHECK: dxsa.and r<7, >, r<7, >, r<8, > +// CHECK: dxsa.utof r<7, >, r<7, > +// CHECK: dxsa.add r<8, >, r<7, >, r<14, > +// CHECK: dxsa.mul r<15, >, r<7, >, l(0x3F800000, 0x0, 0x40000000, 0x0) +// CHECK: %[[INDEX_25:.*]] = dxsa.index.imm {imm = 16 : i32} +// CHECK: %[[OPERAND_30:.*]] = dxsa.operand %[[INDEX_25]] {mask = 64 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_26:.*]] = dxsa.index.imm {imm = 17 : i32} +// CHECK: %[[OPERAND_31:.*]] = dxsa.operand %[[INDEX_26]] {num_components = 4 : i32, one = 0 : i32, type = 0 : i32} +// CHECK: dxsa.instruction "mov" %[[OPERAND_30]], %[[OPERAND_31]] +// CHECK: dxsa.add r<14, >, r<8, >, r<16, > +// CHECK: %[[INDEX_27:.*]] = dxsa.index.imm {imm = 15 : i32} +// CHECK: %[[OPERAND_32:.*]] = dxsa.operand %[[INDEX_27]] {mask = 32 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_28:.*]] = dxsa.index.imm {imm = 14 : i32} +// CHECK: %[[OPERAND_33:.*]] = dxsa.operand %[[INDEX_28]] {num_components = 4 : i32, one = 1 : i32, type = 0 : i32} +// CHECK: dxsa.instruction "mov" %[[OPERAND_32]], %[[OPERAND_33]] +// CHECK: dxsa.add r<8, >, r<15, >, r<15, > +// CHECK: %[[INDEX_29:.*]] = dxsa.index.imm {imm = 14 : i32} +// CHECK: %[[OPERAND_34:.*]] = dxsa.operand %[[INDEX_29]] {mask = 128 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_30:.*]] = dxsa.index.imm {imm = 15 : i32} +// CHECK: %[[OPERAND_35:.*]] = dxsa.operand %[[INDEX_30]] {num_components = 4 : i32, one = 0 : i32, type = 0 : i32} +// CHECK: dxsa.instruction "mov" %[[OPERAND_34]], %[[OPERAND_35]] +// CHECK: dxsa.and r<9, >, r<7, >, r<17, > +// CHECK: %[[INDEX_31:.*]] = dxsa.index.imm {imm = 17 : i32} +// CHECK: %[[OPERAND_36:.*]] = dxsa.operand %[[INDEX_31]] {mask = 32 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_32:.*]] = dxsa.index.imm {imm = 18 : i32} +// CHECK: %[[OPERAND_37:.*]] = dxsa.operand %[[INDEX_32]] {num_components = 4 : i32, one = 0 : i32, type = 0 : i32} +// CHECK: dxsa.instruction "mov" %[[OPERAND_36]], %[[OPERAND_37]] +// CHECK: dxsa.and r<11, >, r<5, >, r<17, > +// CHECK: dxsa.or r<9, >, r<9, >, r<11, > +// CHECK: dxsa.and r<11, >, r<5, >, r<18, > +// CHECK: %[[INDEX_33:.*]] = dxsa.index.imm {imm = 20 : i32} +// CHECK: %[[OPERAND_38:.*]] = dxsa.operand %[[INDEX_33]] {mask = 32 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_34:.*]] = dxsa.index.imm {imm = 18 : i32} +// CHECK: %[[OPERAND_39:.*]] = dxsa.operand %[[INDEX_34]] {num_components = 4 : i32, one = 3 : i32, type = 0 : i32} +// CHECK: dxsa.instruction "mov" %[[OPERAND_38]], %[[OPERAND_39]] +// CHECK: dxsa.and r<12, >, r<7, >, r<20, > +// CHECK: dxsa.or r<9, >, r<9, >, r<11, > +// CHECK: dxsa.or r<9, >, r<9, >, r<12, > +// CHECK: dxsa.itof r<9, >, r<9, > +// CHECK: dxsa.add r<15, >, r<8, >, r<9, > +// CHECK: %[[INDEX_35:.*]] = dxsa.index.imm {imm = 15 : i32} +// CHECK: %[[OPERAND_40:.*]] = dxsa.operand %[[INDEX_35]] {mask = 80 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_36:.*]] = dxsa.index.imm {imm = 8 : i32} +// CHECK: %[[OPERAND_41:.*]] = dxsa.operand %[[INDEX_36]] {num_components = 4 : i32, swizzle = dense<1> : vector<4xi32>, type = 0 : i32} +// CHECK: dxsa.instruction "mov" %[[OPERAND_40]], %[[OPERAND_41]] +// CHECK: dxsa.add r<14>, r<14, >, r<15> +// CHECK: dxsa.add r<14, >, r<0, >, r<14, > +// CHECK: dxsa.add r<14, >, r<1, >, r<14, > +// CHECK: dxsa.and r<0, >, r<2, >, r<7, > +// CHECK: dxsa.and r<1, >, r<6, >, r<7, > +// CHECK: %[[INDEX_37:.*]] = dxsa.index.imm {imm = 2 : i32} +// CHECK: %[[OPERAND_42:.*]] = dxsa.operand %[[INDEX_37]] {mask = 128 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_38:.*]] = dxsa.index.imm {imm = 3 : i32} +// CHECK: %[[OPERAND_43:.*]] = dxsa.operand %[[INDEX_38]] {num_components = 4 : i32, one = 0 : i32, type = 0 : i32} +// CHECK: dxsa.instruction "mov" %[[OPERAND_42]], %[[OPERAND_43]] +// CHECK: dxsa.and r<2, >, r<2, >, r<5, > +// CHECK: dxsa.or r<0, >, r<0, >, r<2, > +// CHECK: dxsa.and r<2, >, r<3, >, r<5, > +// CHECK: dxsa.and r<2, >, r<10, >, r<5, > +// CHECK: %[[INDEX_39:.*]] = dxsa.index.imm {imm = 4 : i32} +// CHECK: %[[OPERAND_44:.*]] = dxsa.operand %[[INDEX_39]] {mask = 16 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_40:.*]] = dxsa.index.imm {imm = 3 : i32} +// CHECK: %[[OPERAND_45:.*]] = dxsa.operand %[[INDEX_40]] {num_components = 4 : i32, one = 3 : i32, type = 0 : i32} +// CHECK: dxsa.instruction "mov" %[[OPERAND_44]], %[[OPERAND_45]] +// CHECK: dxsa.and r<3, >, r<4, >, r<7, > +// CHECK: dxsa.or r<0, >, r<0, >, r<2, > +// CHECK: dxsa.or r<0, >, r<0, >, r<3, > +// CHECK: dxsa.itof r<0, >, r<0, > +// CHECK: dxsa.add r<3, >, r<0, >, r<14, > +// CHECK: %[[INDEX_41:.*]] = dxsa.index.imm {imm = 3 : i32} +// CHECK: %[[OPERAND_46:.*]] = dxsa.operand %[[INDEX_41]] {mask = 96 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_42:.*]] = dxsa.index.imm {imm = 14 : i32} +// CHECK: %[[OPERAND_47:.*]] = dxsa.operand %[[INDEX_42]] {num_components = 4 : i32, swizzle = dense<[0, 0, 2, 0]> : vector<4xi32>, type = 0 : i32} +// CHECK: dxsa.instruction "mov" %[[OPERAND_46]], %[[OPERAND_47]] +// CHECK: dxsa.add r<3, >, r<5, >, r<3, > +// CHECK: %[[INDEX_43:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_48:.*]] = dxsa.operand %[[INDEX_43]] {mask = 16 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_44:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_49:.*]] = dxsa.operand %[[INDEX_44]] {num_components = 4 : i32, one = 0 : i32, type = 0 : i32} +// CHECK: dxsa.instruction "check_access_fully_mapped" %[[OPERAND_48]], %[[OPERAND_49]] +// CHECK: dxsa.unknown +// CHECK: %[[INDEX_45:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_50:.*]] = dxsa.operand %[[INDEX_45]] {mask = 64 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_46:.*]] = dxsa.index.imm {imm = 2 : i32} +// CHECK: %[[OPERAND_51:.*]] = dxsa.operand %[[INDEX_46]] {num_components = 4 : i32, one = 0 : i32, type = 0 : i32} +// CHECK: dxsa.instruction "check_access_fully_mapped" %[[OPERAND_50]], %[[OPERAND_51]] +// CHECK: dxsa.and r<0, >, r<0, >, r<0, > +// CHECK: dxsa.unknown +// CHECK: dxsa.unknown +// CHECK: %[[INDEX_47:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_52:.*]] = dxsa.operand %[[INDEX_47]] {mask = 64 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_48:.*]] = dxsa.index.imm {imm = 4 : i32} +// CHECK: %[[OPERAND_53:.*]] = dxsa.operand %[[INDEX_48]] {num_components = 4 : i32, one = 0 : i32, type = 0 : i32} +// CHECK: dxsa.instruction "check_access_fully_mapped" %[[OPERAND_52]], %[[OPERAND_53]] +// CHECK: %[[INDEX_49:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_54:.*]] = dxsa.operand %[[INDEX_49]] {mask = 128 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_50:.*]] = dxsa.index.imm {imm = 2 : i32} +// CHECK: %[[OPERAND_55:.*]] = dxsa.operand %[[INDEX_50]] {num_components = 4 : i32, one = 0 : i32, type = 0 : i32} +// CHECK: dxsa.instruction "check_access_fully_mapped" %[[OPERAND_54]], %[[OPERAND_55]] +// CHECK: dxsa.and r<0, >, r<0, >, r<0, > +// CHECK: dxsa.and r<0, >, r<0, >, r<0, > +// CHECK: dxsa.utof r<0, >, r<0, > +// CHECK: dxsa.add r<3>, r<0, >, r<3> +// CHECK: %[[INDEX_51:.*]] = dxsa.index.imm {imm = 4 : i32} +// CHECK: %[[OPERAND_56:.*]] = dxsa.operand %[[INDEX_51]] {mask = 48 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_52:.*]] = dxsa.index.imm {imm = 4 : i32} +// CHECK: %[[OPERAND_57:.*]] = dxsa.operand %[[INDEX_52]] {num_components = 4 : i32, swizzle = dense<[2, 3, 2, 2]> : vector<4xi32>, type = 0 : i32} +// CHECK: dxsa.instruction "mov" %[[OPERAND_56]], %[[OPERAND_57]] +// CHECK: %[[INDEX_53:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_58:.*]] = dxsa.operand %[[INDEX_53]] {mask = 16 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_54:.*]] = dxsa.index.imm {imm = 6 : i32} +// CHECK: %[[OPERAND_59:.*]] = dxsa.operand %[[INDEX_54]] {num_components = 4 : i32, one = 0 : i32, type = 0 : i32} +// CHECK: dxsa.instruction "check_access_fully_mapped" %[[OPERAND_58]], %[[OPERAND_59]] +// CHECK: %[[INDEX_55:.*]] = dxsa.index.imm {imm = 4 : i32} +// CHECK: %[[OPERAND_60:.*]] = dxsa.operand %[[INDEX_55]] {mask = 64 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_56:.*]] = dxsa.index.imm {imm = 7 : i32} +// CHECK: %[[OPERAND_61:.*]] = dxsa.operand %[[INDEX_56]] {num_components = 4 : i32, one = 0 : i32, type = 0 : i32} +// CHECK: dxsa.instruction "mov" %[[OPERAND_60]], %[[OPERAND_61]] +// CHECK: %[[INDEX_57:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_62:.*]] = dxsa.operand %[[INDEX_57]] {mask = 64 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_58:.*]] = dxsa.index.imm {imm = 8 : i32} +// CHECK: %[[OPERAND_63:.*]] = dxsa.operand %[[INDEX_58]] {num_components = 4 : i32, one = 0 : i32, type = 0 : i32} +// CHECK: dxsa.instruction "check_access_fully_mapped" %[[OPERAND_62]], %[[OPERAND_63]] +// CHECK: dxsa.and r<0, >, r<0, >, r<0, > +// CHECK: dxsa.add r<3, >, r<3, >, r<4, > +// CHECK: dxsa.unknown +// CHECK: %[[INDEX_59:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_64:.*]] = dxsa.operand %[[INDEX_59]] {mask = 64 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_60:.*]] = dxsa.index.imm {imm = 2 : i32} +// CHECK: %[[OPERAND_65:.*]] = dxsa.operand %[[INDEX_60]] {num_components = 4 : i32, one = 0 : i32, type = 0 : i32} +// CHECK: dxsa.instruction "check_access_fully_mapped" %[[OPERAND_64]], %[[OPERAND_65]] +// CHECK: dxsa.and r<0, >, r<0, >, r<0, > +// CHECK: dxsa.unknown +// CHECK: dxsa.unknown +// CHECK: %[[INDEX_61:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_66:.*]] = dxsa.operand %[[INDEX_61]] {mask = 32 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_62:.*]] = dxsa.index.imm {imm = 4 : i32} +// CHECK: %[[OPERAND_67:.*]] = dxsa.operand %[[INDEX_62]] {num_components = 4 : i32, one = 0 : i32, type = 0 : i32} +// CHECK: dxsa.instruction "check_access_fully_mapped" %[[OPERAND_66]], %[[OPERAND_67]] +// CHECK: %[[INDEX_63:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_68:.*]] = dxsa.operand %[[INDEX_63]] {mask = 64 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_64:.*]] = dxsa.index.imm {imm = 2 : i32} +// CHECK: %[[OPERAND_69:.*]] = dxsa.operand %[[INDEX_64]] {num_components = 4 : i32, one = 0 : i32, type = 0 : i32} +// CHECK: dxsa.instruction "check_access_fully_mapped" %[[OPERAND_68]], %[[OPERAND_69]] +// CHECK: dxsa.and r<0, >, r<0, >, r<0, > +// CHECK: dxsa.utof r<0, >, r<0, > +// CHECK: dxsa.add r<3>, r<0, >, r<3> +// CHECK: %[[INDEX_65:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_70:.*]] = dxsa.operand %[[INDEX_65]] {mask = 16 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_66:.*]] = dxsa.index.imm {imm = 9 : i32} +// CHECK: %[[OPERAND_71:.*]] = dxsa.operand %[[INDEX_66]] {num_components = 4 : i32, one = 0 : i32, type = 0 : i32} +// CHECK: dxsa.instruction "check_access_fully_mapped" %[[OPERAND_70]], %[[OPERAND_71]] +// CHECK: dxsa.and r<0, >, r<0, >, r<0, > +// CHECK: %[[INDEX_67:.*]] = dxsa.index.imm {imm = 6 : i32} +// CHECK: %[[OPERAND_72:.*]] = dxsa.operand %[[INDEX_67]] {mask = 32 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_68:.*]] = dxsa.index.imm {imm = 10 : i32} +// CHECK: %[[OPERAND_73:.*]] = dxsa.operand %[[INDEX_68]] {num_components = 4 : i32, one = 0 : i32, type = 0 : i32} +// CHECK: dxsa.instruction "mov" %[[OPERAND_72]], %[[OPERAND_73]] +// CHECK: dxsa.and r<0, >, r<5, >, r<6, > +// CHECK: dxsa.or r<0, >, r<1, >, r<0, > +// CHECK: dxsa.or r<0, >, r<0, >, r<2, > +// CHECK: %[[INDEX_69:.*]] = dxsa.index.imm {imm = 12 : i32} +// CHECK: %[[OPERAND_74:.*]] = dxsa.operand %[[INDEX_69]] {mask = 32 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_70:.*]] = dxsa.index.imm {imm = 10 : i32} +// CHECK: %[[OPERAND_75:.*]] = dxsa.operand %[[INDEX_70]] {num_components = 4 : i32, one = 3 : i32, type = 0 : i32} +// CHECK: dxsa.instruction "mov" %[[OPERAND_74]], %[[OPERAND_75]] +// CHECK: %[[INDEX_71:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_76:.*]] = dxsa.operand %[[INDEX_71]] {mask = 128 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_72:.*]] = dxsa.index.imm {imm = 11 : i32} +// CHECK: %[[OPERAND_77:.*]] = dxsa.operand %[[INDEX_72]] {num_components = 4 : i32, one = 0 : i32, type = 0 : i32} +// CHECK: dxsa.instruction "check_access_fully_mapped" %[[OPERAND_76]], %[[OPERAND_77]] +// CHECK: dxsa.and r<0, >, r<0, >, r<0, > +// CHECK: dxsa.and r<1, >, r<7, >, r<12, > +// CHECK: %[[INDEX_73:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_78:.*]] = dxsa.operand %[[INDEX_73]] {mask = 128 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_74:.*]] = dxsa.index.imm {imm = 13 : i32} +// CHECK: %[[OPERAND_79:.*]] = dxsa.operand %[[INDEX_74]] {num_components = 4 : i32, one = 0 : i32, type = 0 : i32} +// CHECK: dxsa.instruction "check_access_fully_mapped" %[[OPERAND_78]], %[[OPERAND_79]] +// CHECK: dxsa.and r<0, >, r<0, >, r<0, > +// CHECK: dxsa.utof r<0, >, r<0, > +// CHECK: dxsa.or r<0, >, r<0, >, r<1, > +// CHECK: dxsa.itof r<0, >, r<0, > +// CHECK: dxsa.add r<3, >, r<0, >, r<3, > +// CHECK: dxsa.add r<0>, r<0, >, r<3> +// CHECK: dxsa.mul r<1, >, v<0, >, l(0x40400000) +// CHECK: dxsa.ftou r<1, >, r<1, > +// CHECK: %[[INDEX_75:.*]] = dxsa.index.imm {imm = 1 : i32} +// CHECK: %[[OPERAND_80:.*]] = dxsa.operand %[[INDEX_75]] {mask = 48 : i32, num_components = 4 : i32, type = 30 : i32} +// CHECK: %[[INDEX_76:.*]] = dxsa.index.imm {imm = 1 : i32} +// CHECK: %[[OPERAND_81:.*]] = dxsa.operand %[[INDEX_76]] {num_components = 4 : i32, one = 0 : i32, type = 0 : i32} +// CHECK: %[[OPERAND_82:.*]] = dxsa.operand.imm {imm = dense<0> : vector<1xi32>} +// CHECK: %[[INDEX_77:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_83:.*]] = dxsa.operand %[[INDEX_77]] {num_components = 4 : i32, swizzle = dense<[0, 1, 0, 0]> : vector<4xi32>, type = 0 : i32} +// CHECK: dxsa.instruction "store_structured" %[[OPERAND_80]], %[[OPERAND_81]], %[[OPERAND_82]], %[[OPERAND_83]] +// CHECK: %[[INDEX_78:.*]] = dxsa.index.imm {imm = 1 : i32} +// CHECK: %[[OPERAND_84:.*]] = dxsa.operand %[[INDEX_78]] {mask = 112 : i32, num_components = 4 : i32, type = 30 : i32} +// CHECK: %[[INDEX_79:.*]] = dxsa.index.imm {imm = 1 : i32} +// CHECK: %[[OPERAND_85:.*]] = dxsa.operand %[[INDEX_79]] {num_components = 4 : i32, one = 0 : i32, type = 0 : i32} +// CHECK: %[[OPERAND_86:.*]] = dxsa.operand.imm {imm = dense<8> : vector<1xi32>} +// CHECK: %[[INDEX_80:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_87:.*]] = dxsa.operand %[[INDEX_80]] {num_components = 4 : i32, swizzle = dense<[0, 1, 2, 0]> : vector<4xi32>, type = 0 : i32} +// CHECK: dxsa.instruction "store_structured" %[[OPERAND_84]], %[[OPERAND_85]], %[[OPERAND_86]], %[[OPERAND_87]] +// CHECK: dxsa.ftoi r<1, >, r<0, > +// CHECK: %[[INDEX_81:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_88:.*]] = dxsa.operand %[[INDEX_81]] {mask = 240 : i32, num_components = 4 : i32, type = 2 : i32} +// CHECK: %[[INDEX_82:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_89:.*]] = dxsa.operand %[[INDEX_82]] {num_components = 4 : i32, swizzle = dense<[0, 1, 2, 3]> : vector<4xi32>, type = 0 : i32} +// CHECK: dxsa.instruction "mov" %[[OPERAND_88]], %[[OPERAND_89]] +// CHECK: %[[INDEX_83:.*]] = dxsa.index.imm {imm = 1 : i32} +// CHECK: %[[OPERAND_90:.*]] = dxsa.operand %[[INDEX_83]] {mask = 48 : i32, num_components = 4 : i32, type = 30 : i32} +// CHECK: %[[INDEX_84:.*]] = dxsa.index.imm {imm = 1 : i32} +// CHECK: %[[OPERAND_91:.*]] = dxsa.operand %[[INDEX_84]] {num_components = 4 : i32, one = 0 : i32, type = 0 : i32} +// CHECK: %[[INDEX_85:.*]] = dxsa.index.imm {imm = 1 : i32} +// CHECK: %[[OPERAND_92:.*]] = dxsa.operand %[[INDEX_85]] {num_components = 4 : i32, one = 3 : i32, type = 0 : i32} +// CHECK: %[[INDEX_86:.*]] = dxsa.index.imm {imm = 1 : i32} +// CHECK: %[[OPERAND_93:.*]] = dxsa.operand %[[INDEX_86]] {num_components = 4 : i32, swizzle = dense<[1, 2, 1, 1]> : vector<4xi32>, type = 0 : i32} +// CHECK: dxsa.instruction "store_structured" %[[OPERAND_90]], %[[OPERAND_91]], %[[OPERAND_92]], %[[OPERAND_93]] +// CHECK: dxsa.instruction "ret" + diff --git a/mlir/test/Target/DXSA/hlsl/sub1.test b/mlir/test/Target/DXSA/hlsl/sub1.test new file mode 100644 index 000000000000..1b0c1883c21f --- /dev/null +++ b/mlir/test/Target/DXSA/hlsl/sub1.test @@ -0,0 +1,91 @@ +// RUN: mlir-translate --import-dxsa-bin %S/inputs/sub1.bin | FileCheck %s +// NOTE: Assertions have been autogenerated by utils/generate-test-checks.py + +// This script is intended to make adding checks to a test case quick and easy. +// It is *not* authoritative about what constitutes a good test. After using the +// script, be sure to review and refine the generated checks. For example, +// CHECK lines should be minimized and named to reflect the test’s intent. +// For comprehensive guidelines, see: +// * https://mlir.llvm.org/getting_started/TestingGuide/ + + +// CHECK-LABEL: dxsa.dcl_global_flags +// CHECK: dxsa.dcl_constant_buffer , +// CHECK: dxsa.dcl_input_ps linear v<0, > +// CHECK: dxsa.dcl_output o<0> +// CHECK: dxsa.dcl_temps 1 +// CHECK: dxsa.dcl_indexable_temp x<0>[8] +// CHECK: %[[INDEX_0:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[INDEX_1:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_0:.*]] = dxsa.operand %[[INDEX_0]], %[[INDEX_1]] {num_components = 4 : i32, one = 0 : i32, type = 8 : i32} +// CHECK: dxsa.instruction "switch" %[[OPERAND_0]] +// CHECK: %[[OPERAND_1:.*]] = dxsa.operand.imm {imm = dense<0> : vector<1xi32>} +// CHECK: dxsa.instruction "case" %[[OPERAND_1]] +// CHECK: %[[INDEX_2:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_2:.*]] = dxsa.operand %[[INDEX_2]] {num_components = 0 : i32, type = 10 : i32} +// CHECK: dxsa.instruction "call" %[[OPERAND_2]] +// CHECK: dxsa.instruction "break" +// CHECK: %[[OPERAND_3:.*]] = dxsa.operand.imm {imm = dense<1> : vector<1xi32>} +// CHECK: dxsa.instruction "case" %[[OPERAND_3]] +// CHECK: %[[INDEX_3:.*]] = dxsa.index.imm {imm = 1 : i32} +// CHECK: %[[OPERAND_4:.*]] = dxsa.operand %[[INDEX_3]] {num_components = 0 : i32, type = 10 : i32} +// CHECK: dxsa.instruction "call" %[[OPERAND_4]] +// CHECK: dxsa.instruction "break" +// CHECK: dxsa.instruction "default" +// CHECK: %[[INDEX_4:.*]] = dxsa.index.imm {imm = 2 : i32} +// CHECK: %[[OPERAND_5:.*]] = dxsa.operand %[[INDEX_4]] {num_components = 0 : i32, type = 10 : i32} +// CHECK: dxsa.instruction "call" %[[OPERAND_5]] +// CHECK: dxsa.instruction "break" +// CHECK: dxsa.instruction "endswitch" +// CHECK: %[[INDEX_5:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_6:.*]] = dxsa.operand %[[INDEX_5]] {mask = 16 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_6:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[INDEX_7:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_7:.*]] = dxsa.operand %[[INDEX_6]], %[[INDEX_7]] {num_components = 4 : i32, one = 1 : i32, type = 8 : i32} +// CHECK: dxsa.instruction "mov" %[[OPERAND_6]], %[[OPERAND_7]] +// CHECK: %[[INDEX_8:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_8:.*]] = dxsa.operand %[[INDEX_8]] {mask = 240 : i32, num_components = 4 : i32, type = 2 : i32} +// CHECK: %[[INDEX_9:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[INDEX_10:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_9:.*]] = dxsa.operand %[[INDEX_10]] {num_components = 4 : i32, one = 0 : i32, type = 0 : i32} +// CHECK: %[[INDEX_11:.*]] = dxsa.index.rel %[[OPERAND_9]] +// CHECK: %[[OPERAND_10:.*]] = dxsa.operand %[[INDEX_9]], %[[INDEX_11]] {num_components = 4 : i32, swizzle = dense<[0, 1, 2, 3]> : vector<4xi32>, type = 3 : i32} +// CHECK: dxsa.instruction "mov" %[[OPERAND_8]], %[[OPERAND_10]] +// CHECK: dxsa.instruction "ret" +// CHECK: %[[INDEX_12:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_11:.*]] = dxsa.operand %[[INDEX_12]] {num_components = 0 : i32, type = 10 : i32} +// CHECK: dxsa.instruction "label" %[[OPERAND_11]] +// CHECK: %[[INDEX_13:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[INDEX_14:.*]] = dxsa.index.imm {imm = 2 : i32} +// CHECK: %[[OPERAND_12:.*]] = dxsa.operand %[[INDEX_13]], %[[INDEX_14]] {mask = 240 : i32, num_components = 4 : i32, type = 3 : i32} +// CHECK: %[[OPERAND_13:.*]] = dxsa.operand.imm {imm = dense<1082130432> : vector<4xi32>} +// CHECK: dxsa.instruction "mov" %[[OPERAND_12]], %[[OPERAND_13]] +// CHECK: dxsa.instruction "ret" +// CHECK: %[[INDEX_15:.*]] = dxsa.index.imm {imm = 1 : i32} +// CHECK: %[[OPERAND_14:.*]] = dxsa.operand %[[INDEX_15]] {num_components = 0 : i32, type = 10 : i32} +// CHECK: dxsa.instruction "label" %[[OPERAND_14]] +// CHECK: %[[INDEX_16:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[INDEX_17:.*]] = dxsa.index.imm {imm = 2 : i32} +// CHECK: %[[OPERAND_15:.*]] = dxsa.operand %[[INDEX_16]], %[[INDEX_17]] {mask = 240 : i32, num_components = 4 : i32, type = 3 : i32} +// CHECK: %[[INDEX_18:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_16:.*]] = dxsa.operand %[[INDEX_18]] {num_components = 4 : i32, swizzle = dense<0> : vector<4xi32>, type = 1 : i32} +// CHECK: dxsa.instruction "mov" %[[OPERAND_15]], %[[OPERAND_16]] +// CHECK: dxsa.instruction "ret" +// CHECK: %[[INDEX_19:.*]] = dxsa.index.imm {imm = 2 : i32} +// CHECK: %[[OPERAND_17:.*]] = dxsa.operand %[[INDEX_19]] {num_components = 0 : i32, type = 10 : i32} +// CHECK: dxsa.instruction "label" %[[OPERAND_17]] +// CHECK: %[[INDEX_20:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_18:.*]] = dxsa.operand %[[INDEX_20]] {mask = 16 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_21:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[INDEX_22:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_19:.*]] = dxsa.operand %[[INDEX_21]], %[[INDEX_22]] {num_components = 4 : i32, one = 0 : i32, type = 8 : i32} +// CHECK: dxsa.instruction "mov" %[[OPERAND_18]], %[[OPERAND_19]] +// CHECK: %[[INDEX_23:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[INDEX_24:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_20:.*]] = dxsa.operand %[[INDEX_24]] {num_components = 4 : i32, one = 0 : i32, type = 0 : i32} +// CHECK: %[[INDEX_25:.*]] = dxsa.index.rel %[[OPERAND_20]] +// CHECK: %[[OPERAND_21:.*]] = dxsa.operand %[[INDEX_23]], %[[INDEX_25]] {mask = 240 : i32, num_components = 4 : i32, type = 3 : i32} +// CHECK: %[[OPERAND_22:.*]] = dxsa.operand.imm {imm = dense<0> : vector<4xi32>} +// CHECK: dxsa.instruction "mov" %[[OPERAND_21]], %[[OPERAND_22]] +// CHECK: dxsa.instruction "ret" + diff --git a/mlir/test/Target/DXSA/hlsl/switch1.test b/mlir/test/Target/DXSA/hlsl/switch1.test new file mode 100644 index 000000000000..cad60a375c13 --- /dev/null +++ b/mlir/test/Target/DXSA/hlsl/switch1.test @@ -0,0 +1,48 @@ +// RUN: mlir-translate --import-dxsa-bin %S/inputs/switch1.bin | FileCheck %s +// NOTE: Assertions have been autogenerated by utils/generate-test-checks.py + +// This script is intended to make adding checks to a test case quick and easy. +// It is *not* authoritative about what constitutes a good test. After using the +// script, be sure to review and refine the generated checks. For example, +// CHECK lines should be minimized and named to reflect the test’s intent. +// For comprehensive guidelines, see: +// * https://mlir.llvm.org/getting_started/TestingGuide/ + + +// CHECK-LABEL: dxsa.dcl_global_flags +// CHECK: dxsa.dcl_input_ps linear v<0, > +// CHECK: dxsa.dcl_input_ps constant v<1, > +// CHECK: dxsa.dcl_output o<0, > +// CHECK: dxsa.dcl_temps 1 +// CHECK: %[[INDEX_0:.*]] = dxsa.index.imm {imm = 1 : i32} +// CHECK: %[[OPERAND_0:.*]] = dxsa.operand %[[INDEX_0]] {num_components = 4 : i32, one = 0 : i32, type = 1 : i32} +// CHECK: dxsa.instruction "switch" %[[OPERAND_0]] +// CHECK: %[[OPERAND_1:.*]] = dxsa.operand.imm {imm = dense<1> : vector<1xi32>} +// CHECK: dxsa.instruction "case" %[[OPERAND_1]] +// CHECK: %[[INDEX_1:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_2:.*]] = dxsa.operand %[[INDEX_1]] {mask = 16 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[OPERAND_3:.*]] = dxsa.operand.imm {imm = dense<1084227584> : vector<1xi32>} +// CHECK: dxsa.instruction "mov" %[[OPERAND_2]], %[[OPERAND_3]] +// CHECK: dxsa.instruction "break" +// CHECK: %[[OPERAND_4:.*]] = dxsa.operand.imm {imm = dense<2> : vector<1xi32>} +// CHECK: dxsa.instruction "case" %[[OPERAND_4]] +// CHECK: %[[INDEX_2:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_5:.*]] = dxsa.operand %[[INDEX_2]] {mask = 16 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_3:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_6:.*]] = dxsa.operand %[[INDEX_3]] {num_components = 4 : i32, one = 0 : i32, type = 1 : i32} +// CHECK: dxsa.instruction "mov" %[[OPERAND_5]], %[[OPERAND_6]] +// CHECK: dxsa.instruction "break" +// CHECK: dxsa.instruction "default" +// CHECK: %[[INDEX_4:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_7:.*]] = dxsa.operand %[[INDEX_4]] {mask = 16 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[OPERAND_8:.*]] = dxsa.operand.imm {imm = dense<1077936128> : vector<1xi32>} +// CHECK: dxsa.instruction "mov" %[[OPERAND_7]], %[[OPERAND_8]] +// CHECK: dxsa.instruction "break" +// CHECK: dxsa.instruction "endswitch" +// CHECK: %[[INDEX_5:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_9:.*]] = dxsa.operand %[[INDEX_5]] {mask = 16 : i32, num_components = 4 : i32, type = 2 : i32} +// CHECK: %[[INDEX_6:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_10:.*]] = dxsa.operand %[[INDEX_6]] {num_components = 4 : i32, one = 0 : i32, type = 0 : i32} +// CHECK: dxsa.instruction "mov" %[[OPERAND_9]], %[[OPERAND_10]] +// CHECK: dxsa.instruction "ret" + diff --git a/mlir/test/Target/DXSA/hlsl/switch2.test b/mlir/test/Target/DXSA/hlsl/switch2.test new file mode 100644 index 000000000000..1ee74063cc18 --- /dev/null +++ b/mlir/test/Target/DXSA/hlsl/switch2.test @@ -0,0 +1,62 @@ +// RUN: mlir-translate --import-dxsa-bin %S/inputs/switch2.bin | FileCheck %s +// NOTE: Assertions have been autogenerated by utils/generate-test-checks.py + +// This script is intended to make adding checks to a test case quick and easy. +// It is *not* authoritative about what constitutes a good test. After using the +// script, be sure to review and refine the generated checks. For example, +// CHECK lines should be minimized and named to reflect the test’s intent. +// For comprehensive guidelines, see: +// * https://mlir.llvm.org/getting_started/TestingGuide/ + + +// CHECK-LABEL: dxsa.dcl_global_flags +// CHECK: dxsa.dcl_input_ps linear v<0, > +// CHECK: dxsa.dcl_input_ps constant v<1, > +// CHECK: dxsa.dcl_output o<0, > +// CHECK: dxsa.dcl_temps 1 +// CHECK: %[[INDEX_0:.*]] = dxsa.index.imm {imm = 1 : i32} +// CHECK: %[[OPERAND_0:.*]] = dxsa.operand %[[INDEX_0]] {num_components = 4 : i32, one = 0 : i32, type = 1 : i32} +// CHECK: dxsa.instruction "switch" %[[OPERAND_0]] +// CHECK: %[[OPERAND_1:.*]] = dxsa.operand.imm {imm = dense<1> : vector<1xi32>} +// CHECK: dxsa.instruction "case" %[[OPERAND_1]] +// CHECK: dxsa.ieq r<0, >, v<1, >, l(0xB) +// CHECK: %[[INDEX_1:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_2:.*]] = dxsa.operand %[[INDEX_1]] {num_components = 4 : i32, one = 1 : i32, type = 0 : i32} +// CHECK: dxsa.instruction "if" %[[OPERAND_2]] +// CHECK: %[[INDEX_2:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_3:.*]] = dxsa.operand %[[INDEX_2]] {mask = 16 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[OPERAND_4:.*]] = dxsa.operand.imm {imm = dense<1084227584> : vector<1xi32>} +// CHECK: dxsa.instruction "mov" %[[OPERAND_3]], %[[OPERAND_4]] +// CHECK: dxsa.instruction "break" +// CHECK: dxsa.instruction "endif" +// CHECK: %[[INDEX_3:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_5:.*]] = dxsa.operand %[[INDEX_3]] {mask = 16 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[OPERAND_6:.*]] = dxsa.operand.imm {imm = dense<1085276160> : vector<1xi32>} +// CHECK: dxsa.instruction "mov" %[[OPERAND_5]], %[[OPERAND_6]] +// CHECK: dxsa.instruction "break" +// CHECK: %[[OPERAND_7:.*]] = dxsa.operand.imm {imm = dense<2> : vector<1xi32>} +// CHECK: dxsa.instruction "case" %[[OPERAND_7]] +// CHECK: dxsa.ieq r<0, >, v<1, >, l(0xC) +// CHECK: %[[INDEX_4:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_8:.*]] = dxsa.operand %[[INDEX_4]] {num_components = 4 : i32, one = 1 : i32, type = 0 : i32} +// CHECK: dxsa.instruction "breakc" %[[OPERAND_8]] +// CHECK: %[[INDEX_5:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_9:.*]] = dxsa.operand %[[INDEX_5]] {mask = 16 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_6:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_10:.*]] = dxsa.operand %[[INDEX_6]] {num_components = 4 : i32, one = 0 : i32, type = 1 : i32} +// CHECK: dxsa.instruction "mov" %[[OPERAND_9]], %[[OPERAND_10]] +// CHECK: dxsa.instruction "break" +// CHECK: dxsa.instruction "default" +// CHECK: %[[INDEX_7:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_11:.*]] = dxsa.operand %[[INDEX_7]] {mask = 16 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[OPERAND_12:.*]] = dxsa.operand.imm {imm = dense<1077936128> : vector<1xi32>} +// CHECK: dxsa.instruction "mov" %[[OPERAND_11]], %[[OPERAND_12]] +// CHECK: dxsa.instruction "break" +// CHECK: dxsa.instruction "endswitch" +// CHECK: %[[INDEX_8:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_13:.*]] = dxsa.operand %[[INDEX_8]] {mask = 16 : i32, num_components = 4 : i32, type = 2 : i32} +// CHECK: %[[INDEX_9:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_14:.*]] = dxsa.operand %[[INDEX_9]] {num_components = 4 : i32, one = 0 : i32, type = 0 : i32} +// CHECK: dxsa.instruction "mov" %[[OPERAND_13]], %[[OPERAND_14]] +// CHECK: dxsa.instruction "ret" + diff --git a/mlir/test/Target/DXSA/hlsl/switch3.test b/mlir/test/Target/DXSA/hlsl/switch3.test new file mode 100644 index 000000000000..671a30018e8b --- /dev/null +++ b/mlir/test/Target/DXSA/hlsl/switch3.test @@ -0,0 +1,80 @@ +// RUN: mlir-translate --import-dxsa-bin %S/inputs/switch3.bin | FileCheck %s +// NOTE: Assertions have been autogenerated by utils/generate-test-checks.py + +// This script is intended to make adding checks to a test case quick and easy. +// It is *not* authoritative about what constitutes a good test. After using the +// script, be sure to review and refine the generated checks. For example, +// CHECK lines should be minimized and named to reflect the test’s intent. +// For comprehensive guidelines, see: +// * https://mlir.llvm.org/getting_started/TestingGuide/ + + +// CHECK-LABEL: dxsa.dcl_global_flags +// CHECK: dxsa.dcl_input_ps linear v<0, > +// CHECK: dxsa.dcl_input_ps constant v<1, > +// CHECK: dxsa.dcl_output o<0, > +// CHECK: dxsa.dcl_temps 1 +// CHECK: %[[INDEX_0:.*]] = dxsa.index.imm {imm = 1 : i32} +// CHECK: %[[OPERAND_0:.*]] = dxsa.operand %[[INDEX_0]] {num_components = 4 : i32, one = 0 : i32, type = 1 : i32} +// CHECK: dxsa.instruction "switch" %[[OPERAND_0]] +// CHECK: %[[OPERAND_1:.*]] = dxsa.operand.imm {imm = dense<1> : vector<1xi32>} +// CHECK: dxsa.instruction "case" %[[OPERAND_1]] +// CHECK: %[[INDEX_1:.*]] = dxsa.index.imm {imm = 1 : i32} +// CHECK: %[[OPERAND_2:.*]] = dxsa.operand %[[INDEX_1]] {num_components = 4 : i32, one = 1 : i32, type = 1 : i32} +// CHECK: dxsa.instruction "switch" %[[OPERAND_2]] +// CHECK: %[[OPERAND_3:.*]] = dxsa.operand.imm {imm = dense<20> : vector<1xi32>} +// CHECK: dxsa.instruction "case" %[[OPERAND_3]] +// CHECK: dxsa.ieq r<0, >, v<1, >, l(0x1E) +// CHECK: %[[INDEX_2:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_4:.*]] = dxsa.operand %[[INDEX_2]] {num_components = 4 : i32, one = 1 : i32, type = 0 : i32} +// CHECK: dxsa.instruction "if" %[[OPERAND_4]] +// CHECK: %[[INDEX_3:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_5:.*]] = dxsa.operand %[[INDEX_3]] {mask = 16 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[OPERAND_6:.*]] = dxsa.operand.imm {imm = dense<1085276160> : vector<1xi32>} +// CHECK: dxsa.instruction "mov" %[[OPERAND_5]], %[[OPERAND_6]] +// CHECK: dxsa.instruction "break" +// CHECK: dxsa.instruction "endif" +// CHECK: dxsa.ieq r<0, >, v<1, >, l(0x1F) +// CHECK: %[[INDEX_4:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_7:.*]] = dxsa.operand %[[INDEX_4]] {mask = 16 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[OPERAND_8:.*]] = dxsa.operand.imm {imm = dense<1085695590> : vector<1xi32>} +// CHECK: dxsa.instruction "mov" %[[OPERAND_7]], %[[OPERAND_8]] +// CHECK: %[[INDEX_5:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_9:.*]] = dxsa.operand %[[INDEX_5]] {num_components = 4 : i32, one = 1 : i32, type = 0 : i32} +// CHECK: dxsa.instruction "breakc" %[[OPERAND_9]] +// CHECK: %[[INDEX_6:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_10:.*]] = dxsa.operand %[[INDEX_6]] {mask = 16 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[OPERAND_11:.*]] = dxsa.operand.imm {imm = dense<1085905306> : vector<1xi32>} +// CHECK: dxsa.instruction "mov" %[[OPERAND_10]], %[[OPERAND_11]] +// CHECK: dxsa.instruction "break" +// CHECK: dxsa.instruction "default" +// CHECK: %[[INDEX_7:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_12:.*]] = dxsa.operand %[[INDEX_7]] {mask = 16 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_8:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_13:.*]] = dxsa.operand %[[INDEX_8]] {num_components = 4 : i32, one = 1 : i32, type = 1 : i32} +// CHECK: dxsa.instruction "mov" %[[OPERAND_12]], %[[OPERAND_13]] +// CHECK: dxsa.instruction "break" +// CHECK: dxsa.instruction "endswitch" +// CHECK: dxsa.instruction "break" +// CHECK: %[[OPERAND_14:.*]] = dxsa.operand.imm {imm = dense<2> : vector<1xi32>} +// CHECK: dxsa.instruction "case" %[[OPERAND_14]] +// CHECK: %[[INDEX_9:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_15:.*]] = dxsa.operand %[[INDEX_9]] {mask = 16 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_10:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_16:.*]] = dxsa.operand %[[INDEX_10]] {num_components = 4 : i32, one = 0 : i32, type = 1 : i32} +// CHECK: dxsa.instruction "mov" %[[OPERAND_15]], %[[OPERAND_16]] +// CHECK: dxsa.instruction "break" +// CHECK: dxsa.instruction "default" +// CHECK: %[[INDEX_11:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_17:.*]] = dxsa.operand %[[INDEX_11]] {mask = 16 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[OPERAND_18:.*]] = dxsa.operand.imm {imm = dense<1077936128> : vector<1xi32>} +// CHECK: dxsa.instruction "mov" %[[OPERAND_17]], %[[OPERAND_18]] +// CHECK: dxsa.instruction "break" +// CHECK: dxsa.instruction "endswitch" +// CHECK: %[[INDEX_12:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_19:.*]] = dxsa.operand %[[INDEX_12]] {mask = 16 : i32, num_components = 4 : i32, type = 2 : i32} +// CHECK: %[[INDEX_13:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_20:.*]] = dxsa.operand %[[INDEX_13]] {num_components = 4 : i32, one = 0 : i32, type = 0 : i32} +// CHECK: dxsa.instruction "mov" %[[OPERAND_19]], %[[OPERAND_20]] +// CHECK: dxsa.instruction "ret" + diff --git a/mlir/test/Target/DXSA/hlsl/swizzle1.test b/mlir/test/Target/DXSA/hlsl/swizzle1.test new file mode 100644 index 000000000000..5b821f16c2c6 --- /dev/null +++ b/mlir/test/Target/DXSA/hlsl/swizzle1.test @@ -0,0 +1,22 @@ +// RUN: mlir-translate --import-dxsa-bin %S/inputs/swizzle1.bin | FileCheck %s +// NOTE: Assertions have been autogenerated by utils/generate-test-checks.py + +// This script is intended to make adding checks to a test case quick and easy. +// It is *not* authoritative about what constitutes a good test. After using the +// script, be sure to review and refine the generated checks. For example, +// CHECK lines should be minimized and named to reflect the test’s intent. +// For comprehensive guidelines, see: +// * https://mlir.llvm.org/getting_started/TestingGuide/ + + +// CHECK-LABEL: dxsa.dcl_global_flags +// CHECK: dxsa.dcl_input_ps linear v<0, > +// CHECK: dxsa.dcl_input_ps linear v<1, > +// CHECK: dxsa.dcl_input_ps linear v<2, > +// CHECK: dxsa.dcl_output o<0> +// CHECK: dxsa.dcl_temps 1 +// CHECK: dxsa.add r<0>, v<0, >, v<1, > +// CHECK: dxsa.add r<0>, r<0>, v<2, > +// CHECK: dxsa.add o<0>, r<0>, l(0x0, 0x3F800000, 0x40000000, 0x40400000) +// CHECK: dxsa.instruction "ret" + diff --git a/mlir/test/Target/DXSA/hlsl/temp1.test b/mlir/test/Target/DXSA/hlsl/temp1.test new file mode 100644 index 000000000000..a44d25042e1f --- /dev/null +++ b/mlir/test/Target/DXSA/hlsl/temp1.test @@ -0,0 +1,20 @@ +// RUN: mlir-translate --import-dxsa-bin %S/inputs/temp1.bin | FileCheck %s +// NOTE: Assertions have been autogenerated by utils/generate-test-checks.py + +// This script is intended to make adding checks to a test case quick and easy. +// It is *not* authoritative about what constitutes a good test. After using the +// script, be sure to review and refine the generated checks. For example, +// CHECK lines should be minimized and named to reflect the test’s intent. +// For comprehensive guidelines, see: +// * https://mlir.llvm.org/getting_started/TestingGuide/ + + +// CHECK-LABEL: dxsa.dcl_global_flags +// CHECK: dxsa.dcl_input_ps linear v<0> +// CHECK: dxsa.dcl_input_ps linear v<1> +// CHECK: dxsa.dcl_output o<0> +// CHECK: dxsa.dcl_temps 1 +// CHECK: dxsa.add r<0>, v<0>, v<1> +// CHECK: dxsa.add o<0>, r<0>, l(0x0, 0x3F800000, 0x40000000, 0x40400000) +// CHECK: dxsa.instruction "ret" + diff --git a/mlir/test/Target/DXSA/hlsl/temp2.test b/mlir/test/Target/DXSA/hlsl/temp2.test new file mode 100644 index 000000000000..8c77330a4d1f --- /dev/null +++ b/mlir/test/Target/DXSA/hlsl/temp2.test @@ -0,0 +1,31 @@ +// RUN: mlir-translate --import-dxsa-bin %S/inputs/temp2.bin | FileCheck %s +// NOTE: Assertions have been autogenerated by utils/generate-test-checks.py + +// This script is intended to make adding checks to a test case quick and easy. +// It is *not* authoritative about what constitutes a good test. After using the +// script, be sure to review and refine the generated checks. For example, +// CHECK lines should be minimized and named to reflect the test’s intent. +// For comprehensive guidelines, see: +// * https://mlir.llvm.org/getting_started/TestingGuide/ + + +// CHECK-LABEL: dxsa.dcl_global_flags +// CHECK: dxsa.dcl_input_ps constant v<0> +// CHECK: dxsa.dcl_input_ps constant v<1> +// CHECK: dxsa.dcl_output o<0> +// CHECK: dxsa.dcl_temps 1 +// CHECK: %[[INDEX_0:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_0:.*]] = dxsa.operand %[[INDEX_0]] {mask = 240 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_1:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_1:.*]] = dxsa.operand %[[INDEX_1]] {num_components = 4 : i32, swizzle = dense<[0, 1, 2, 3]> : vector<4xi32>, type = 1 : i32} +// CHECK: %[[INDEX_2:.*]] = dxsa.index.imm {imm = 1 : i32} +// CHECK: %[[OPERAND_2:.*]] = dxsa.operand %[[INDEX_2]] {num_components = 4 : i32, swizzle = dense<[0, 1, 2, 3]> : vector<4xi32>, type = 1 : i32} +// CHECK: dxsa.instruction "iadd" %[[OPERAND_0]], %[[OPERAND_1]], %[[OPERAND_2]] +// CHECK: %[[INDEX_3:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_3:.*]] = dxsa.operand %[[INDEX_3]] {mask = 240 : i32, num_components = 4 : i32, type = 2 : i32} +// CHECK: %[[INDEX_4:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_4:.*]] = dxsa.operand %[[INDEX_4]] {num_components = 4 : i32, swizzle = dense<[0, 1, 2, 3]> : vector<4xi32>, type = 0 : i32} +// CHECK: %[[OPERAND_5:.*]] = dxsa.operand.imm {imm = dense<[0, 1, 2, 3]> : vector<4xi32>} +// CHECK: dxsa.instruction "iadd" %[[OPERAND_3]], %[[OPERAND_4]], %[[OPERAND_5]] +// CHECK: dxsa.instruction "ret" + diff --git a/mlir/test/Target/DXSA/hlsl/uav_counter_dec.test b/mlir/test/Target/DXSA/hlsl/uav_counter_dec.test new file mode 100644 index 000000000000..ccd042841d5f --- /dev/null +++ b/mlir/test/Target/DXSA/hlsl/uav_counter_dec.test @@ -0,0 +1,21 @@ +// RUN: mlir-translate --import-dxsa-bin %S/inputs/uav_counter_dec.bin | FileCheck %s +// NOTE: Assertions have been autogenerated by utils/generate-test-checks.py + +// This script is intended to make adding checks to a test case quick and easy. +// It is *not* authoritative about what constitutes a good test. After using the +// script, be sure to review and refine the generated checks. For example, +// CHECK lines should be minimized and named to reflect the test’s intent. +// For comprehensive guidelines, see: +// * https://mlir.llvm.org/getting_started/TestingGuide/ + + +// CHECK-LABEL: dxsa.dcl_global_flags +// CHECK: dxsa.dcl_uav_structured , +// CHECK: dxsa.dcl_temps 1 +// CHECK: %[[INDEX_0:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_0:.*]] = dxsa.operand %[[INDEX_0]] {mask = 16 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_1:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_1:.*]] = dxsa.operand %[[INDEX_1]] {num_components = 0 : i32, type = 30 : i32} +// CHECK: dxsa.instruction "imm_atomic_consume" %[[OPERAND_0]], %[[OPERAND_1]] +// CHECK: dxsa.instruction "ret" + diff --git a/mlir/test/Target/DXSA/hlsl/uav_counter_inc.test b/mlir/test/Target/DXSA/hlsl/uav_counter_inc.test new file mode 100644 index 000000000000..fdcc29efbc6e --- /dev/null +++ b/mlir/test/Target/DXSA/hlsl/uav_counter_inc.test @@ -0,0 +1,21 @@ +// RUN: mlir-translate --import-dxsa-bin %S/inputs/uav_counter_inc.bin | FileCheck %s +// NOTE: Assertions have been autogenerated by utils/generate-test-checks.py + +// This script is intended to make adding checks to a test case quick and easy. +// It is *not* authoritative about what constitutes a good test. After using the +// script, be sure to review and refine the generated checks. For example, +// CHECK lines should be minimized and named to reflect the test’s intent. +// For comprehensive guidelines, see: +// * https://mlir.llvm.org/getting_started/TestingGuide/ + + +// CHECK-LABEL: dxsa.dcl_global_flags +// CHECK: dxsa.dcl_uav_structured , +// CHECK: dxsa.dcl_temps 1 +// CHECK: %[[INDEX_0:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_0:.*]] = dxsa.operand %[[INDEX_0]] {mask = 16 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_1:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_1:.*]] = dxsa.operand %[[INDEX_1]] {num_components = 0 : i32, type = 30 : i32} +// CHECK: dxsa.instruction "imm_atomic_alloc" %[[OPERAND_0]], %[[OPERAND_1]] +// CHECK: dxsa.instruction "ret" + diff --git a/mlir/test/Target/DXSA/hlsl/uav_raw1.test b/mlir/test/Target/DXSA/hlsl/uav_raw1.test new file mode 100644 index 000000000000..69437bbec3a4 --- /dev/null +++ b/mlir/test/Target/DXSA/hlsl/uav_raw1.test @@ -0,0 +1,42 @@ +// RUN: mlir-translate --import-dxsa-bin %S/inputs/uav_raw1.bin | FileCheck %s +// NOTE: Assertions have been autogenerated by utils/generate-test-checks.py + +// This script is intended to make adding checks to a test case quick and easy. +// It is *not* authoritative about what constitutes a good test. After using the +// script, be sure to review and refine the generated checks. For example, +// CHECK lines should be minimized and named to reflect the test’s intent. +// For comprehensive guidelines, see: +// * https://mlir.llvm.org/getting_started/TestingGuide/ + + +// CHECK-LABEL: dxsa.dcl_global_flags +// CHECK: dxsa.dcl_uav_raw +// CHECK: dxsa.dcl_input_ps constant v<0, > +// CHECK: dxsa.dcl_input_ps constant v<0, > +// CHECK: dxsa.dcl_output o<0> +// CHECK: dxsa.dcl_temps 2 +// CHECK: dxsa.unknown +// CHECK: dxsa.utof r<0, >, r<0, > +// CHECK: dxsa.unknown +// CHECK: %[[INDEX_0:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_0:.*]] = dxsa.operand %[[INDEX_0]] {mask = 32 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_1:.*]] = dxsa.index.imm {imm = 1 : i32} +// CHECK: %[[OPERAND_1:.*]] = dxsa.operand %[[INDEX_1]] {num_components = 4 : i32, one = 0 : i32, type = 0 : i32} +// CHECK: dxsa.instruction "check_access_fully_mapped" %[[OPERAND_0]], %[[OPERAND_1]] +// CHECK: dxsa.utof r<0, >, r<0, > +// CHECK: dxsa.mad r<0>, r<0, >, l(0x40000000, 0x40000000, 0x40000000, 0x40000000), r<0, > +// CHECK: dxsa.ftou r<1, >, r<0, > +// CHECK: %[[INDEX_2:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_2:.*]] = dxsa.operand %[[INDEX_2]] {mask = 240 : i32, num_components = 4 : i32, type = 2 : i32} +// CHECK: %[[INDEX_3:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_3:.*]] = dxsa.operand %[[INDEX_3]] {num_components = 4 : i32, swizzle = dense<[0, 1, 2, 3]> : vector<4xi32>, type = 0 : i32} +// CHECK: dxsa.instruction "mov" %[[OPERAND_2]], %[[OPERAND_3]] +// CHECK: %[[INDEX_4:.*]] = dxsa.index.imm {imm = 3 : i32} +// CHECK: %[[OPERAND_4:.*]] = dxsa.operand %[[INDEX_4]] {mask = 240 : i32, num_components = 4 : i32, type = 30 : i32} +// CHECK: %[[INDEX_5:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_5:.*]] = dxsa.operand %[[INDEX_5]] {num_components = 4 : i32, one = 1 : i32, type = 1 : i32} +// CHECK: %[[INDEX_6:.*]] = dxsa.index.imm {imm = 1 : i32} +// CHECK: %[[OPERAND_6:.*]] = dxsa.operand %[[INDEX_6]] {num_components = 4 : i32, swizzle = dense<0> : vector<4xi32>, type = 0 : i32} +// CHECK: dxsa.instruction "store_raw" %[[OPERAND_4]], %[[OPERAND_5]], %[[OPERAND_6]] +// CHECK: dxsa.instruction "ret" + diff --git a/mlir/test/Target/DXSA/hlsl/uav_typed_load_store1.test b/mlir/test/Target/DXSA/hlsl/uav_typed_load_store1.test new file mode 100644 index 000000000000..aa524fbd91f6 --- /dev/null +++ b/mlir/test/Target/DXSA/hlsl/uav_typed_load_store1.test @@ -0,0 +1,42 @@ +// RUN: mlir-translate --import-dxsa-bin %S/inputs/uav_typed_load_store1.bin | FileCheck %s +// NOTE: Assertions have been autogenerated by utils/generate-test-checks.py + +// This script is intended to make adding checks to a test case quick and easy. +// It is *not* authoritative about what constitutes a good test. After using the +// script, be sure to review and refine the generated checks. For example, +// CHECK lines should be minimized and named to reflect the test’s intent. +// For comprehensive guidelines, see: +// * https://mlir.llvm.org/getting_started/TestingGuide/ + + +// CHECK-LABEL: dxsa.dcl_global_flags +// CHECK: dxsa.dcl_uav_typed , +// CHECK: dxsa.dcl_input_ps constant v<0, > +// CHECK: dxsa.dcl_input_ps constant v<0, > +// CHECK: dxsa.dcl_output o<0> +// CHECK: dxsa.dcl_temps 2 +// CHECK: dxsa.unknown +// CHECK: dxsa.unknown +// CHECK: dxsa.add r<0>, r<0>, r<1> +// CHECK: dxsa.unknown +// CHECK: %[[INDEX_0:.*]] = dxsa.index.imm {imm = 1 : i32} +// CHECK: %[[OPERAND_0:.*]] = dxsa.operand %[[INDEX_0]] {mask = 16 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_1:.*]] = dxsa.index.imm {imm = 1 : i32} +// CHECK: %[[OPERAND_1:.*]] = dxsa.operand %[[INDEX_1]] {num_components = 4 : i32, one = 0 : i32, type = 0 : i32} +// CHECK: dxsa.instruction "check_access_fully_mapped" %[[OPERAND_0]], %[[OPERAND_1]] +// CHECK: dxsa.utof r<1, >, r<1, > +// CHECK: dxsa.mad r<0>, r<1, >, l(0x40000000, 0x40000000, 0x40000000, 0x40000000), r<0> +// CHECK: %[[INDEX_2:.*]] = dxsa.index.imm {imm = 3 : i32} +// CHECK: %[[OPERAND_2:.*]] = dxsa.operand %[[INDEX_2]] {mask = 240 : i32, num_components = 4 : i32, type = 30 : i32} +// CHECK: %[[INDEX_3:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_3:.*]] = dxsa.operand %[[INDEX_3]] {num_components = 4 : i32, swizzle = dense<[2, 3, 3, 3]> : vector<4xi32>, type = 1 : i32} +// CHECK: %[[INDEX_4:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_4:.*]] = dxsa.operand %[[INDEX_4]] {num_components = 4 : i32, swizzle = dense<[0, 1, 2, 3]> : vector<4xi32>, type = 0 : i32} +// CHECK: dxsa.instruction "store_uav_typed" %[[OPERAND_2]], %[[OPERAND_3]], %[[OPERAND_4]] +// CHECK: %[[INDEX_5:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_5:.*]] = dxsa.operand %[[INDEX_5]] {mask = 240 : i32, num_components = 4 : i32, type = 2 : i32} +// CHECK: %[[INDEX_6:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_6:.*]] = dxsa.operand %[[INDEX_6]] {num_components = 4 : i32, swizzle = dense<[0, 1, 2, 3]> : vector<4xi32>, type = 0 : i32} +// CHECK: dxsa.instruction "mov" %[[OPERAND_5]], %[[OPERAND_6]] +// CHECK: dxsa.instruction "ret" + diff --git a/mlir/test/Target/DXSA/hlsl/uav_typed_load_store2.test b/mlir/test/Target/DXSA/hlsl/uav_typed_load_store2.test new file mode 100644 index 000000000000..ca8800a3dbe4 --- /dev/null +++ b/mlir/test/Target/DXSA/hlsl/uav_typed_load_store2.test @@ -0,0 +1,73 @@ +// RUN: mlir-translate --import-dxsa-bin %S/inputs/uav_typed_load_store2.bin | FileCheck %s +// NOTE: Assertions have been autogenerated by utils/generate-test-checks.py + +// This script is intended to make adding checks to a test case quick and easy. +// It is *not* authoritative about what constitutes a good test. After using the +// script, be sure to review and refine the generated checks. For example, +// CHECK lines should be minimized and named to reflect the test’s intent. +// For comprehensive guidelines, see: +// * https://mlir.llvm.org/getting_started/TestingGuide/ + + +// CHECK-LABEL: dxsa.dcl_global_flags +// CHECK: dxsa.dcl_uav_typed , +// CHECK: dxsa.dcl_input_ps constant v<0, > +// CHECK: dxsa.dcl_input_ps constant v<0, > +// CHECK: dxsa.dcl_output o<0, > +// CHECK: dxsa.dcl_temps 5 +// CHECK: dxsa.unknown +// CHECK: dxsa.unknown +// CHECK: %[[INDEX_0:.*]] = dxsa.index.imm {imm = 2 : i32} +// CHECK: %[[OPERAND_0:.*]] = dxsa.operand %[[INDEX_0]] {mask = 112 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_1:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_1:.*]] = dxsa.operand %[[INDEX_1]] {min_precision = 4 : i32, num_components = 4 : i32, swizzle = dense<[0, 1, 2, 0]> : vector<4xi32>, type = 0 : i32} +// CHECK: %[[INDEX_2:.*]] = dxsa.index.imm {imm = 1 : i32} +// CHECK: %[[OPERAND_2:.*]] = dxsa.operand %[[INDEX_2]] {min_precision = 4 : i32, num_components = 4 : i32, swizzle = dense<[0, 1, 2, 0]> : vector<4xi32>, type = 0 : i32} +// CHECK: dxsa.instruction "iadd" %[[OPERAND_0]], %[[OPERAND_1]], %[[OPERAND_2]] +// CHECK: dxsa.unknown +// CHECK: dxsa.unknown +// CHECK: %[[INDEX_3:.*]] = dxsa.index.imm {imm = 2 : i32} +// CHECK: %[[OPERAND_3:.*]] = dxsa.operand %[[INDEX_3]] {mask = 128 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_4:.*]] = dxsa.index.imm {imm = 3 : i32} +// CHECK: %[[OPERAND_4:.*]] = dxsa.operand %[[INDEX_4]] {num_components = 4 : i32, one = 0 : i32, type = 0 : i32} +// CHECK: dxsa.instruction "check_access_fully_mapped" %[[OPERAND_3]], %[[OPERAND_4]] +// CHECK: %[[INDEX_5:.*]] = dxsa.index.imm {imm = 2 : i32} +// CHECK: %[[OPERAND_5:.*]] = dxsa.operand %[[INDEX_5]] {mask = 112 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_6:.*]] = dxsa.index.imm {imm = 2 : i32} +// CHECK: %[[OPERAND_6:.*]] = dxsa.operand %[[INDEX_6]] {num_components = 4 : i32, swizzle = dense<3> : vector<4xi32>, type = 0 : i32} +// CHECK: %[[INDEX_7:.*]] = dxsa.index.imm {imm = 2 : i32} +// CHECK: %[[OPERAND_7:.*]] = dxsa.operand %[[INDEX_7]] {num_components = 4 : i32, swizzle = dense<[0, 1, 2, 0]> : vector<4xi32>, type = 0 : i32} +// CHECK: dxsa.instruction "iadd" %[[OPERAND_5]], %[[OPERAND_6]], %[[OPERAND_7]] +// CHECK: %[[INDEX_8:.*]] = dxsa.index.imm {imm = 2 : i32} +// CHECK: %[[OPERAND_8:.*]] = dxsa.operand %[[INDEX_8]] {mask = 128 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_9:.*]] = dxsa.index.imm {imm = 4 : i32} +// CHECK: %[[OPERAND_9:.*]] = dxsa.operand %[[INDEX_9]] {num_components = 4 : i32, one = 0 : i32, type = 0 : i32} +// CHECK: dxsa.instruction "check_access_fully_mapped" %[[OPERAND_8]], %[[OPERAND_9]] +// CHECK: %[[INDEX_10:.*]] = dxsa.index.imm {imm = 2 : i32} +// CHECK: %[[OPERAND_10:.*]] = dxsa.operand %[[INDEX_10]] {mask = 112 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_11:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_11:.*]] = dxsa.operand %[[INDEX_11]] {min_precision = 4 : i32, num_components = 4 : i32, swizzle = dense<[0, 1, 2, 0]> : vector<4xi32>, type = 0 : i32} +// CHECK: %[[INDEX_12:.*]] = dxsa.index.imm {imm = 2 : i32} +// CHECK: %[[OPERAND_12:.*]] = dxsa.operand %[[INDEX_12]] {num_components = 4 : i32, swizzle = dense<[0, 1, 2, 0]> : vector<4xi32>, type = 0 : i32} +// CHECK: dxsa.instruction "iadd" %[[OPERAND_10]], %[[OPERAND_11]], %[[OPERAND_12]] +// CHECK: %[[INDEX_13:.*]] = dxsa.index.imm {imm = 2 : i32} +// CHECK: %[[OPERAND_13:.*]] = dxsa.operand %[[INDEX_13]] {mask = 112 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_14:.*]] = dxsa.index.imm {imm = 2 : i32} +// CHECK: %[[OPERAND_14:.*]] = dxsa.operand %[[INDEX_14]] {num_components = 4 : i32, swizzle = dense<3> : vector<4xi32>, type = 0 : i32} +// CHECK: %[[INDEX_15:.*]] = dxsa.index.imm {imm = 2 : i32} +// CHECK: %[[OPERAND_15:.*]] = dxsa.operand %[[INDEX_15]] {num_components = 4 : i32, swizzle = dense<[0, 1, 2, 0]> : vector<4xi32>, type = 0 : i32} +// CHECK: dxsa.instruction "iadd" %[[OPERAND_13]], %[[OPERAND_14]], %[[OPERAND_15]] +// CHECK: %[[INDEX_16:.*]] = dxsa.index.imm {imm = 3 : i32} +// CHECK: %[[OPERAND_16:.*]] = dxsa.operand %[[INDEX_16]] {mask = 240 : i32, num_components = 4 : i32, type = 30 : i32} +// CHECK: %[[INDEX_17:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_17:.*]] = dxsa.operand %[[INDEX_17]] {num_components = 4 : i32, swizzle = dense<1> : vector<4xi32>, type = 1 : i32} +// CHECK: %[[INDEX_18:.*]] = dxsa.index.imm {imm = 2 : i32} +// CHECK: %[[OPERAND_18:.*]] = dxsa.operand %[[INDEX_18]] {num_components = 4 : i32, swizzle = dense<[0, 1, 2, 0]> : vector<4xi32>, type = 0 : i32} +// CHECK: dxsa.instruction "store_uav_typed" %[[OPERAND_16]], %[[OPERAND_17]], %[[OPERAND_18]] +// CHECK: %[[INDEX_19:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_19:.*]] = dxsa.operand %[[INDEX_19]] {mask = 112 : i32, num_components = 4 : i32, type = 2 : i32} +// CHECK: %[[INDEX_20:.*]] = dxsa.index.imm {imm = 2 : i32} +// CHECK: %[[OPERAND_20:.*]] = dxsa.operand %[[INDEX_20]] {num_components = 4 : i32, swizzle = dense<[0, 1, 2, 0]> : vector<4xi32>, type = 0 : i32} +// CHECK: dxsa.instruction "mov" %[[OPERAND_19]], %[[OPERAND_20]] +// CHECK: dxsa.instruction "ret" + diff --git a/mlir/test/Target/DXSA/hlsl/ubfeu16.test b/mlir/test/Target/DXSA/hlsl/ubfeu16.test new file mode 100644 index 000000000000..49a583f4e55e --- /dev/null +++ b/mlir/test/Target/DXSA/hlsl/ubfeu16.test @@ -0,0 +1,34 @@ +// RUN: mlir-translate --import-dxsa-bin %S/inputs/ubfeu16.bin | FileCheck %s +// NOTE: Assertions have been autogenerated by utils/generate-test-checks.py + +// This script is intended to make adding checks to a test case quick and easy. +// It is *not* authoritative about what constitutes a good test. After using the +// script, be sure to review and refine the generated checks. For example, +// CHECK lines should be minimized and named to reflect the test’s intent. +// For comprehensive guidelines, see: +// * https://mlir.llvm.org/getting_started/TestingGuide/ + + +// CHECK-LABEL: dxsa.dcl_global_flags +// CHECK: dxsa.dcl_constant_buffer , +// CHECK: dxsa.dcl_output o<0, min16u, > +// CHECK: dxsa.dcl_temps 1 +// CHECK: %[[INDEX_0:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_0:.*]] = dxsa.operand %[[INDEX_0]] {mask = 16 : i32, min_precision = 5 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[OPERAND_1:.*]] = dxsa.operand.imm {imm = dense<27> : vector<1xi32>} +// CHECK: %[[OPERAND_2:.*]] = dxsa.operand.imm {imm = dense<5> : vector<1xi32>} +// CHECK: %[[INDEX_1:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[INDEX_2:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_3:.*]] = dxsa.operand %[[INDEX_1]], %[[INDEX_2]] {min_precision = 5 : i32, num_components = 4 : i32, one = 0 : i32, type = 8 : i32} +// CHECK: dxsa.instruction "ubfe" %[[OPERAND_0]], %[[OPERAND_1]], %[[OPERAND_2]], %[[OPERAND_3]] +// CHECK: dxsa.and r<0, min16u, >, cb<[0, 0], vector, min16u, >, l(0xFFFFFFFC) +// CHECK: dxsa.xor r<0, min16u, >, r<0, min16u, >, r<0, min16u, > +// CHECK: %[[INDEX_3:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_4:.*]] = dxsa.operand %[[INDEX_3]] {mask = 16 : i32, min_precision = 5 : i32, num_components = 4 : i32, type = 2 : i32} +// CHECK: %[[INDEX_4:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_5:.*]] = dxsa.operand %[[INDEX_4]] {min_precision = 5 : i32, num_components = 4 : i32, one = 0 : i32, type = 0 : i32} +// CHECK: %[[INDEX_5:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_6:.*]] = dxsa.operand %[[INDEX_5]] {min_precision = 5 : i32, num_components = 4 : i32, one = 1 : i32, type = 0 : i32} +// CHECK: dxsa.instruction "iadd" %[[OPERAND_4]], %[[OPERAND_5]], %[[OPERAND_6]] +// CHECK: dxsa.instruction "ret" + From b75f7d3f73ba8eeb19d2a6bab9615c707e4b236c Mon Sep 17 00:00:00 2001 From: Andrew Savonichev Date: Thu, 25 Jun 2026 16:31:32 +0900 Subject: [PATCH 2/2] Remove disclaimers, rename *.bin to *.shex --- mlir/test/Target/DXSA/asm/call2.test | 9 +-------- mlir/test/Target/DXSA/asm/cs3.test | 9 +-------- mlir/test/Target/DXSA/asm/cyclecounter.test | 9 +-------- mlir/test/Target/DXSA/asm/hs3.test | 9 +-------- mlir/test/Target/DXSA/asm/indexabletemp4.test | 9 +-------- mlir/test/Target/DXSA/asm/indexabletemp6.test | 9 +-------- .../DXSA/asm/inputs/{call2.bin => call2.shex} | Bin .../Target/DXSA/asm/inputs/{cs3.bin => cs3.shex} | Bin .../inputs/{cyclecounter.bin => cyclecounter.shex} | Bin .../Target/DXSA/asm/inputs/{hs3.bin => hs3.shex} | Bin .../{indexabletemp4.bin => indexabletemp4.shex} | Bin .../{indexabletemp6.bin => indexabletemp6.shex} | Bin mlir/test/Target/DXSA/hlsl/abs1.test | 9 +-------- mlir/test/Target/DXSA/hlsl/abs2.test | 9 +-------- mlir/test/Target/DXSA/hlsl/atomics.test | 9 +-------- mlir/test/Target/DXSA/hlsl/bad_ftoi.test | 9 +-------- mlir/test/Target/DXSA/hlsl/binary1.test | 9 +-------- mlir/test/Target/DXSA/hlsl/bool1.test | 9 +-------- mlir/test/Target/DXSA/hlsl/bool2.test | 9 +-------- mlir/test/Target/DXSA/hlsl/bufinfo.test | 9 +-------- mlir/test/Target/DXSA/hlsl/calc_lod.test | 9 +-------- mlir/test/Target/DXSA/hlsl/call1.test | 9 +-------- mlir/test/Target/DXSA/hlsl/call3.test | 9 +-------- mlir/test/Target/DXSA/hlsl/cast1.test | 9 +-------- mlir/test/Target/DXSA/hlsl/cast2.test | 9 +-------- mlir/test/Target/DXSA/hlsl/cast3.test | 9 +-------- mlir/test/Target/DXSA/hlsl/cast4.test | 9 +-------- mlir/test/Target/DXSA/hlsl/cast5.test | 9 +-------- mlir/test/Target/DXSA/hlsl/cast6.test | 9 +-------- mlir/test/Target/DXSA/hlsl/cbuffer1.50.test | 9 +-------- mlir/test/Target/DXSA/hlsl/cbuffer1.51.test | 9 +-------- mlir/test/Target/DXSA/hlsl/cbuffer2.50.test | 9 +-------- mlir/test/Target/DXSA/hlsl/cbuffer2.51.test | 9 +-------- mlir/test/Target/DXSA/hlsl/cbuffer3.50.test | 9 +-------- mlir/test/Target/DXSA/hlsl/cbuffer3.51.test | 9 +-------- mlir/test/Target/DXSA/hlsl/cmp1.test | 9 +-------- mlir/test/Target/DXSA/hlsl/constoperand1.test | 9 +-------- mlir/test/Target/DXSA/hlsl/cs1.test | 9 +-------- mlir/test/Target/DXSA/hlsl/cs2.test | 9 +-------- mlir/test/Target/DXSA/hlsl/cs4.test | 9 +-------- mlir/test/Target/DXSA/hlsl/cs5.test | 9 +-------- mlir/test/Target/DXSA/hlsl/derivatives.test | 9 +-------- mlir/test/Target/DXSA/hlsl/discard.test | 9 +-------- mlir/test/Target/DXSA/hlsl/dot1.test | 9 +-------- mlir/test/Target/DXSA/hlsl/double1.test | 9 +-------- mlir/test/Target/DXSA/hlsl/double2.test | 9 +-------- mlir/test/Target/DXSA/hlsl/double3.test | 9 +-------- mlir/test/Target/DXSA/hlsl/double4.test | 9 +-------- mlir/test/Target/DXSA/hlsl/double5.test | 9 +-------- mlir/test/Target/DXSA/hlsl/double6.test | 9 +-------- mlir/test/Target/DXSA/hlsl/ds1.test | 9 +-------- mlir/test/Target/DXSA/hlsl/empty.test | 9 +-------- mlir/test/Target/DXSA/hlsl/eval.test | 9 +-------- mlir/test/Target/DXSA/hlsl/f32f16.test | 9 +-------- mlir/test/Target/DXSA/hlsl/gather.test | 9 +-------- mlir/test/Target/DXSA/hlsl/gather_cmp.test | 9 +-------- mlir/test/Target/DXSA/hlsl/gather_po.test | 9 +-------- mlir/test/Target/DXSA/hlsl/gather_po_cmp.test | 9 +-------- mlir/test/Target/DXSA/hlsl/getdim.test | 9 +-------- mlir/test/Target/DXSA/hlsl/gs1.test | 9 +-------- mlir/test/Target/DXSA/hlsl/gs2.test | 9 +-------- mlir/test/Target/DXSA/hlsl/half_rcp.test | 9 +-------- mlir/test/Target/DXSA/hlsl/hs1.test | 9 +-------- mlir/test/Target/DXSA/hlsl/hs2.test | 9 +-------- mlir/test/Target/DXSA/hlsl/icb1.test | 9 +-------- mlir/test/Target/DXSA/hlsl/if1.test | 9 +-------- mlir/test/Target/DXSA/hlsl/if2.test | 9 +-------- mlir/test/Target/DXSA/hlsl/if3.test | 9 +-------- mlir/test/Target/DXSA/hlsl/if4.test | 9 +-------- mlir/test/Target/DXSA/hlsl/if5.test | 9 +-------- mlir/test/Target/DXSA/hlsl/indexableinput1.test | 9 +-------- mlir/test/Target/DXSA/hlsl/indexableinput2.test | 9 +-------- mlir/test/Target/DXSA/hlsl/indexableoutput1.test | 9 +-------- mlir/test/Target/DXSA/hlsl/indexabletemp1.test | 9 +-------- mlir/test/Target/DXSA/hlsl/indexabletemp2.test | 9 +-------- mlir/test/Target/DXSA/hlsl/indexabletemp3.test | 9 +-------- mlir/test/Target/DXSA/hlsl/indexabletemp5.test | 9 +-------- mlir/test/Target/DXSA/hlsl/input1.test | 9 +-------- mlir/test/Target/DXSA/hlsl/input2.test | 9 +-------- mlir/test/Target/DXSA/hlsl/input3.test | 9 +-------- .../Target/DXSA/hlsl/inputs/{abs1.bin => abs1.shex} | Bin .../Target/DXSA/hlsl/inputs/{abs2.bin => abs2.shex} | Bin .../DXSA/hlsl/inputs/{atomics.bin => atomics.shex} | Bin .../hlsl/inputs/{bad_ftoi.bin => bad_ftoi.shex} | Bin .../DXSA/hlsl/inputs/{binary1.bin => binary1.shex} | Bin .../DXSA/hlsl/inputs/{bool1.bin => bool1.shex} | Bin .../DXSA/hlsl/inputs/{bool2.bin => bool2.shex} | Bin .../DXSA/hlsl/inputs/{bufinfo.bin => bufinfo.shex} | Bin .../hlsl/inputs/{calc_lod.bin => calc_lod.shex} | Bin .../DXSA/hlsl/inputs/{call1.bin => call1.shex} | Bin .../DXSA/hlsl/inputs/{call3.bin => call3.shex} | Bin .../DXSA/hlsl/inputs/{cast1.bin => cast1.shex} | Bin .../DXSA/hlsl/inputs/{cast2.bin => cast2.shex} | Bin .../DXSA/hlsl/inputs/{cast3.bin => cast3.shex} | Bin .../DXSA/hlsl/inputs/{cast4.bin => cast4.shex} | Bin .../DXSA/hlsl/inputs/{cast5.bin => cast5.shex} | Bin .../DXSA/hlsl/inputs/{cast6.bin => cast6.shex} | Bin .../inputs/{cbuffer1.50.bin => cbuffer1.50.shex} | Bin .../inputs/{cbuffer1.51.bin => cbuffer1.51.shex} | Bin .../inputs/{cbuffer2.50.bin => cbuffer2.50.shex} | Bin .../inputs/{cbuffer2.51.bin => cbuffer2.51.shex} | Bin .../inputs/{cbuffer3.50.bin => cbuffer3.50.shex} | Bin .../inputs/{cbuffer3.51.bin => cbuffer3.51.shex} | Bin .../Target/DXSA/hlsl/inputs/{cmp1.bin => cmp1.shex} | Bin .../{constoperand1.bin => constoperand1.shex} | Bin .../Target/DXSA/hlsl/inputs/{cs1.bin => cs1.shex} | Bin .../Target/DXSA/hlsl/inputs/{cs2.bin => cs2.shex} | Bin .../Target/DXSA/hlsl/inputs/{cs4.bin => cs4.shex} | Bin .../Target/DXSA/hlsl/inputs/{cs5.bin => cs5.shex} | Bin .../inputs/{derivatives.bin => derivatives.shex} | Bin .../DXSA/hlsl/inputs/{discard.bin => discard.shex} | Bin .../Target/DXSA/hlsl/inputs/{dot1.bin => dot1.shex} | Bin .../DXSA/hlsl/inputs/{double1.bin => double1.shex} | Bin .../DXSA/hlsl/inputs/{double2.bin => double2.shex} | Bin .../DXSA/hlsl/inputs/{double3.bin => double3.shex} | Bin .../DXSA/hlsl/inputs/{double4.bin => double4.shex} | Bin .../DXSA/hlsl/inputs/{double5.bin => double5.shex} | Bin .../DXSA/hlsl/inputs/{double6.bin => double6.shex} | Bin .../Target/DXSA/hlsl/inputs/{ds1.bin => ds1.shex} | Bin .../DXSA/hlsl/inputs/{empty.bin => empty.shex} | Bin .../Target/DXSA/hlsl/inputs/{eval.bin => eval.shex} | Bin .../DXSA/hlsl/inputs/{f32f16.bin => f32f16.shex} | Bin .../DXSA/hlsl/inputs/{gather.bin => gather.shex} | Bin .../hlsl/inputs/{gather_cmp.bin => gather_cmp.shex} | Bin .../hlsl/inputs/{gather_po.bin => gather_po.shex} | Bin .../{gather_po_cmp.bin => gather_po_cmp.shex} | Bin .../DXSA/hlsl/inputs/{getdim.bin => getdim.shex} | Bin .../Target/DXSA/hlsl/inputs/{gs1.bin => gs1.shex} | Bin .../Target/DXSA/hlsl/inputs/{gs2.bin => gs2.shex} | Bin .../hlsl/inputs/{half_rcp.bin => half_rcp.shex} | Bin .../Target/DXSA/hlsl/inputs/{hs1.bin => hs1.shex} | Bin .../Target/DXSA/hlsl/inputs/{hs2.bin => hs2.shex} | Bin .../Target/DXSA/hlsl/inputs/{icb1.bin => icb1.shex} | Bin .../Target/DXSA/hlsl/inputs/{if1.bin => if1.shex} | Bin .../Target/DXSA/hlsl/inputs/{if2.bin => if2.shex} | Bin .../Target/DXSA/hlsl/inputs/{if3.bin => if3.shex} | Bin .../Target/DXSA/hlsl/inputs/{if4.bin => if4.shex} | Bin .../Target/DXSA/hlsl/inputs/{if5.bin => if5.shex} | Bin .../{indexableinput1.bin => indexableinput1.shex} | Bin .../{indexableinput2.bin => indexableinput2.shex} | Bin .../{indexableoutput1.bin => indexableoutput1.shex} | Bin .../{indexabletemp1.bin => indexabletemp1.shex} | Bin .../{indexabletemp2.bin => indexabletemp2.shex} | Bin .../{indexabletemp3.bin => indexabletemp3.shex} | Bin .../{indexabletemp5.bin => indexabletemp5.shex} | Bin .../DXSA/hlsl/inputs/{input1.bin => input1.shex} | Bin .../DXSA/hlsl/inputs/{input2.bin => input2.shex} | Bin .../DXSA/hlsl/inputs/{input3.bin => input3.shex} | Bin .../hlsl/inputs/{interface1.bin => interface1.shex} | Bin .../hlsl/inputs/{liveness1.bin => liveness1.shex} | Bin .../DXSA/hlsl/inputs/{loop1.bin => loop1.shex} | Bin .../DXSA/hlsl/inputs/{loop2.bin => loop2.shex} | Bin .../DXSA/hlsl/inputs/{loop3.bin => loop3.shex} | Bin .../DXSA/hlsl/inputs/{loop4.bin => loop4.shex} | Bin .../DXSA/hlsl/inputs/{loop5.bin => loop5.shex} | Bin .../hlsl/inputs/{minprec1.bin => minprec1.shex} | Bin .../hlsl/inputs/{minprec2.bin => minprec2.shex} | Bin .../hlsl/inputs/{minprec3.bin => minprec3.shex} | Bin .../hlsl/inputs/{minprec4.bin => minprec4.shex} | Bin .../hlsl/inputs/{minprec5.bin => minprec5.shex} | Bin .../hlsl/inputs/{minprec6.bin => minprec6.shex} | Bin .../hlsl/inputs/{minprec7.bin => minprec7.shex} | Bin .../Target/DXSA/hlsl/inputs/{neg1.bin => neg1.shex} | Bin .../Target/DXSA/hlsl/inputs/{neg2.bin => neg2.shex} | Bin .../DXSA/hlsl/inputs/{negabs1.bin => negabs1.shex} | Bin .../inputs/{nonuniform1.bin => nonuniform1.shex} | Bin .../DXSA/hlsl/inputs/{output1.bin => output1.shex} | Bin .../DXSA/hlsl/inputs/{output2.bin => output2.shex} | Bin .../DXSA/hlsl/inputs/{output3.bin => output3.shex} | Bin .../DXSA/hlsl/inputs/{output4.bin => output4.shex} | Bin .../inputs/{passthrough1.bin => passthrough1.shex} | Bin .../inputs/{passthrough2.bin => passthrough2.shex} | Bin .../hlsl/inputs/{precise1.bin => precise1.shex} | Bin .../hlsl/inputs/{raw_buf1.bin => raw_buf1.shex} | Bin .../Target/DXSA/hlsl/inputs/{rcp1.bin => rcp1.shex} | Bin .../{redundantinput1.bin => redundantinput1.shex} | Bin .../DXSA/hlsl/inputs/{sample1.bin => sample1.shex} | Bin .../DXSA/hlsl/inputs/{sample2.bin => sample2.shex} | Bin .../DXSA/hlsl/inputs/{sample3.bin => sample3.shex} | Bin .../hlsl/inputs/{sample_b1.bin => sample_b1.shex} | Bin .../inputs/{sample_cmp1.bin => sample_cmp1.shex} | Bin .../inputs/{sample_cmp2.bin => sample_cmp2.shex} | Bin .../inputs/{sample_grad1.bin => sample_grad1.shex} | Bin .../hlsl/inputs/{sample_l1.bin => sample_l1.shex} | Bin .../inputs/{samplecount.bin => samplecount.shex} | Bin .../hlsl/inputs/{samplepos.bin => samplepos.shex} | Bin .../hlsl/inputs/{saturate1.bin => saturate1.shex} | Bin .../DXSA/hlsl/inputs/{shift1.bin => shift1.shex} | Bin .../DXSA/hlsl/inputs/{sincos.bin => sincos.shex} | Bin .../DXSA/hlsl/inputs/{snorm1.bin => snorm1.shex} | Bin .../inputs/{srv_ms_load1.bin => srv_ms_load1.shex} | Bin .../{srv_typed_load1.bin => srv_typed_load1.shex} | Bin .../{srv_typed_load2.bin => srv_typed_load2.shex} | Bin .../inputs/{struct_buf1.bin => struct_buf1.shex} | Bin .../Target/DXSA/hlsl/inputs/{sub1.bin => sub1.shex} | Bin .../DXSA/hlsl/inputs/{switch1.bin => switch1.shex} | Bin .../DXSA/hlsl/inputs/{switch2.bin => switch2.shex} | Bin .../DXSA/hlsl/inputs/{switch3.bin => switch3.shex} | Bin .../hlsl/inputs/{swizzle1.bin => swizzle1.shex} | Bin .../DXSA/hlsl/inputs/{temp1.bin => temp1.shex} | Bin .../DXSA/hlsl/inputs/{temp2.bin => temp2.shex} | Bin .../{uav_counter_dec.bin => uav_counter_dec.shex} | Bin .../{uav_counter_inc.bin => uav_counter_inc.shex} | Bin .../hlsl/inputs/{uav_raw1.bin => uav_raw1.shex} | Bin ...d_load_store1.bin => uav_typed_load_store1.shex} | Bin ...d_load_store2.bin => uav_typed_load_store2.shex} | Bin .../DXSA/hlsl/inputs/{ubfeu16.bin => ubfeu16.shex} | Bin mlir/test/Target/DXSA/hlsl/interface1.test | 9 +-------- mlir/test/Target/DXSA/hlsl/liveness1.test | 9 +-------- mlir/test/Target/DXSA/hlsl/loop1.test | 9 +-------- mlir/test/Target/DXSA/hlsl/loop2.test | 9 +-------- mlir/test/Target/DXSA/hlsl/loop3.test | 9 +-------- mlir/test/Target/DXSA/hlsl/loop4.test | 9 +-------- mlir/test/Target/DXSA/hlsl/loop5.test | 9 +-------- mlir/test/Target/DXSA/hlsl/minprec1.test | 9 +-------- mlir/test/Target/DXSA/hlsl/minprec2.test | 9 +-------- mlir/test/Target/DXSA/hlsl/minprec3.test | 9 +-------- mlir/test/Target/DXSA/hlsl/minprec4.test | 9 +-------- mlir/test/Target/DXSA/hlsl/minprec5.test | 9 +-------- mlir/test/Target/DXSA/hlsl/minprec6.test | 9 +-------- mlir/test/Target/DXSA/hlsl/minprec7.test | 9 +-------- mlir/test/Target/DXSA/hlsl/neg1.test | 9 +-------- mlir/test/Target/DXSA/hlsl/neg2.test | 9 +-------- mlir/test/Target/DXSA/hlsl/negabs1.test | 9 +-------- mlir/test/Target/DXSA/hlsl/nonuniform1.test | 9 +-------- mlir/test/Target/DXSA/hlsl/output1.test | 9 +-------- mlir/test/Target/DXSA/hlsl/output2.test | 9 +-------- mlir/test/Target/DXSA/hlsl/output3.test | 9 +-------- mlir/test/Target/DXSA/hlsl/output4.test | 9 +-------- mlir/test/Target/DXSA/hlsl/passthrough1.test | 9 +-------- mlir/test/Target/DXSA/hlsl/passthrough2.test | 9 +-------- mlir/test/Target/DXSA/hlsl/precise1.test | 9 +-------- mlir/test/Target/DXSA/hlsl/raw_buf1.test | 9 +-------- mlir/test/Target/DXSA/hlsl/rcp1.test | 9 +-------- mlir/test/Target/DXSA/hlsl/redundantinput1.test | 9 +-------- mlir/test/Target/DXSA/hlsl/sample1.test | 9 +-------- mlir/test/Target/DXSA/hlsl/sample2.test | 9 +-------- mlir/test/Target/DXSA/hlsl/sample3.test | 9 +-------- mlir/test/Target/DXSA/hlsl/sample_b1.test | 9 +-------- mlir/test/Target/DXSA/hlsl/sample_cmp1.test | 9 +-------- mlir/test/Target/DXSA/hlsl/sample_cmp2.test | 9 +-------- mlir/test/Target/DXSA/hlsl/sample_grad1.test | 9 +-------- mlir/test/Target/DXSA/hlsl/sample_l1.test | 9 +-------- mlir/test/Target/DXSA/hlsl/samplecount.test | 9 +-------- mlir/test/Target/DXSA/hlsl/samplepos.test | 9 +-------- mlir/test/Target/DXSA/hlsl/saturate1.test | 9 +-------- mlir/test/Target/DXSA/hlsl/shift1.test | 9 +-------- mlir/test/Target/DXSA/hlsl/sincos.test | 9 +-------- mlir/test/Target/DXSA/hlsl/snorm1.test | 9 +-------- mlir/test/Target/DXSA/hlsl/srv_ms_load1.test | 9 +-------- mlir/test/Target/DXSA/hlsl/srv_typed_load1.test | 9 +-------- mlir/test/Target/DXSA/hlsl/srv_typed_load2.test | 9 +-------- mlir/test/Target/DXSA/hlsl/struct_buf1.test | 9 +-------- mlir/test/Target/DXSA/hlsl/sub1.test | 9 +-------- mlir/test/Target/DXSA/hlsl/switch1.test | 9 +-------- mlir/test/Target/DXSA/hlsl/switch2.test | 9 +-------- mlir/test/Target/DXSA/hlsl/switch3.test | 9 +-------- mlir/test/Target/DXSA/hlsl/swizzle1.test | 9 +-------- mlir/test/Target/DXSA/hlsl/temp1.test | 9 +-------- mlir/test/Target/DXSA/hlsl/temp2.test | 9 +-------- mlir/test/Target/DXSA/hlsl/uav_counter_dec.test | 9 +-------- mlir/test/Target/DXSA/hlsl/uav_counter_inc.test | 9 +-------- mlir/test/Target/DXSA/hlsl/uav_raw1.test | 9 +-------- .../Target/DXSA/hlsl/uav_typed_load_store1.test | 9 +-------- .../Target/DXSA/hlsl/uav_typed_load_store2.test | 9 +-------- mlir/test/Target/DXSA/hlsl/ubfeu16.test | 9 +-------- 266 files changed, 133 insertions(+), 1064 deletions(-) rename mlir/test/Target/DXSA/asm/inputs/{call2.bin => call2.shex} (100%) rename mlir/test/Target/DXSA/asm/inputs/{cs3.bin => cs3.shex} (100%) rename mlir/test/Target/DXSA/asm/inputs/{cyclecounter.bin => cyclecounter.shex} (100%) rename mlir/test/Target/DXSA/asm/inputs/{hs3.bin => hs3.shex} (100%) rename mlir/test/Target/DXSA/asm/inputs/{indexabletemp4.bin => indexabletemp4.shex} (100%) rename mlir/test/Target/DXSA/asm/inputs/{indexabletemp6.bin => indexabletemp6.shex} (100%) rename mlir/test/Target/DXSA/hlsl/inputs/{abs1.bin => abs1.shex} (100%) rename mlir/test/Target/DXSA/hlsl/inputs/{abs2.bin => abs2.shex} (100%) rename mlir/test/Target/DXSA/hlsl/inputs/{atomics.bin => atomics.shex} (100%) rename mlir/test/Target/DXSA/hlsl/inputs/{bad_ftoi.bin => bad_ftoi.shex} (100%) rename mlir/test/Target/DXSA/hlsl/inputs/{binary1.bin => binary1.shex} (100%) rename mlir/test/Target/DXSA/hlsl/inputs/{bool1.bin => bool1.shex} (100%) rename mlir/test/Target/DXSA/hlsl/inputs/{bool2.bin => bool2.shex} (100%) rename mlir/test/Target/DXSA/hlsl/inputs/{bufinfo.bin => bufinfo.shex} (100%) rename mlir/test/Target/DXSA/hlsl/inputs/{calc_lod.bin => calc_lod.shex} (100%) rename mlir/test/Target/DXSA/hlsl/inputs/{call1.bin => call1.shex} (100%) rename mlir/test/Target/DXSA/hlsl/inputs/{call3.bin => call3.shex} (100%) rename mlir/test/Target/DXSA/hlsl/inputs/{cast1.bin => cast1.shex} (100%) rename mlir/test/Target/DXSA/hlsl/inputs/{cast2.bin => cast2.shex} (100%) rename mlir/test/Target/DXSA/hlsl/inputs/{cast3.bin => cast3.shex} (100%) rename mlir/test/Target/DXSA/hlsl/inputs/{cast4.bin => cast4.shex} (100%) rename mlir/test/Target/DXSA/hlsl/inputs/{cast5.bin => cast5.shex} (100%) rename mlir/test/Target/DXSA/hlsl/inputs/{cast6.bin => cast6.shex} (100%) rename mlir/test/Target/DXSA/hlsl/inputs/{cbuffer1.50.bin => cbuffer1.50.shex} (100%) rename mlir/test/Target/DXSA/hlsl/inputs/{cbuffer1.51.bin => cbuffer1.51.shex} (100%) rename mlir/test/Target/DXSA/hlsl/inputs/{cbuffer2.50.bin => cbuffer2.50.shex} (100%) rename mlir/test/Target/DXSA/hlsl/inputs/{cbuffer2.51.bin => cbuffer2.51.shex} (100%) rename mlir/test/Target/DXSA/hlsl/inputs/{cbuffer3.50.bin => cbuffer3.50.shex} (100%) rename mlir/test/Target/DXSA/hlsl/inputs/{cbuffer3.51.bin => cbuffer3.51.shex} (100%) rename mlir/test/Target/DXSA/hlsl/inputs/{cmp1.bin => cmp1.shex} (100%) rename mlir/test/Target/DXSA/hlsl/inputs/{constoperand1.bin => constoperand1.shex} (100%) rename mlir/test/Target/DXSA/hlsl/inputs/{cs1.bin => cs1.shex} (100%) rename mlir/test/Target/DXSA/hlsl/inputs/{cs2.bin => cs2.shex} (100%) rename mlir/test/Target/DXSA/hlsl/inputs/{cs4.bin => cs4.shex} (100%) rename mlir/test/Target/DXSA/hlsl/inputs/{cs5.bin => cs5.shex} (100%) rename mlir/test/Target/DXSA/hlsl/inputs/{derivatives.bin => derivatives.shex} (100%) rename mlir/test/Target/DXSA/hlsl/inputs/{discard.bin => discard.shex} (100%) rename mlir/test/Target/DXSA/hlsl/inputs/{dot1.bin => dot1.shex} (100%) rename mlir/test/Target/DXSA/hlsl/inputs/{double1.bin => double1.shex} (100%) rename mlir/test/Target/DXSA/hlsl/inputs/{double2.bin => double2.shex} (100%) rename mlir/test/Target/DXSA/hlsl/inputs/{double3.bin => double3.shex} (100%) rename mlir/test/Target/DXSA/hlsl/inputs/{double4.bin => double4.shex} (100%) rename mlir/test/Target/DXSA/hlsl/inputs/{double5.bin => double5.shex} (100%) rename mlir/test/Target/DXSA/hlsl/inputs/{double6.bin => double6.shex} (100%) rename mlir/test/Target/DXSA/hlsl/inputs/{ds1.bin => ds1.shex} (100%) rename mlir/test/Target/DXSA/hlsl/inputs/{empty.bin => empty.shex} (100%) rename mlir/test/Target/DXSA/hlsl/inputs/{eval.bin => eval.shex} (100%) rename mlir/test/Target/DXSA/hlsl/inputs/{f32f16.bin => f32f16.shex} (100%) rename mlir/test/Target/DXSA/hlsl/inputs/{gather.bin => gather.shex} (100%) rename mlir/test/Target/DXSA/hlsl/inputs/{gather_cmp.bin => gather_cmp.shex} (100%) rename mlir/test/Target/DXSA/hlsl/inputs/{gather_po.bin => gather_po.shex} (100%) rename mlir/test/Target/DXSA/hlsl/inputs/{gather_po_cmp.bin => gather_po_cmp.shex} (100%) rename mlir/test/Target/DXSA/hlsl/inputs/{getdim.bin => getdim.shex} (100%) rename mlir/test/Target/DXSA/hlsl/inputs/{gs1.bin => gs1.shex} (100%) rename mlir/test/Target/DXSA/hlsl/inputs/{gs2.bin => gs2.shex} (100%) rename mlir/test/Target/DXSA/hlsl/inputs/{half_rcp.bin => half_rcp.shex} (100%) rename mlir/test/Target/DXSA/hlsl/inputs/{hs1.bin => hs1.shex} (100%) rename mlir/test/Target/DXSA/hlsl/inputs/{hs2.bin => hs2.shex} (100%) rename mlir/test/Target/DXSA/hlsl/inputs/{icb1.bin => icb1.shex} (100%) rename mlir/test/Target/DXSA/hlsl/inputs/{if1.bin => if1.shex} (100%) rename mlir/test/Target/DXSA/hlsl/inputs/{if2.bin => if2.shex} (100%) rename mlir/test/Target/DXSA/hlsl/inputs/{if3.bin => if3.shex} (100%) rename mlir/test/Target/DXSA/hlsl/inputs/{if4.bin => if4.shex} (100%) rename mlir/test/Target/DXSA/hlsl/inputs/{if5.bin => if5.shex} (100%) rename mlir/test/Target/DXSA/hlsl/inputs/{indexableinput1.bin => indexableinput1.shex} (100%) rename mlir/test/Target/DXSA/hlsl/inputs/{indexableinput2.bin => indexableinput2.shex} (100%) rename mlir/test/Target/DXSA/hlsl/inputs/{indexableoutput1.bin => indexableoutput1.shex} (100%) rename mlir/test/Target/DXSA/hlsl/inputs/{indexabletemp1.bin => indexabletemp1.shex} (100%) rename mlir/test/Target/DXSA/hlsl/inputs/{indexabletemp2.bin => indexabletemp2.shex} (100%) rename mlir/test/Target/DXSA/hlsl/inputs/{indexabletemp3.bin => indexabletemp3.shex} (100%) rename mlir/test/Target/DXSA/hlsl/inputs/{indexabletemp5.bin => indexabletemp5.shex} (100%) rename mlir/test/Target/DXSA/hlsl/inputs/{input1.bin => input1.shex} (100%) rename mlir/test/Target/DXSA/hlsl/inputs/{input2.bin => input2.shex} (100%) rename mlir/test/Target/DXSA/hlsl/inputs/{input3.bin => input3.shex} (100%) rename mlir/test/Target/DXSA/hlsl/inputs/{interface1.bin => interface1.shex} (100%) rename mlir/test/Target/DXSA/hlsl/inputs/{liveness1.bin => liveness1.shex} (100%) rename mlir/test/Target/DXSA/hlsl/inputs/{loop1.bin => loop1.shex} (100%) rename mlir/test/Target/DXSA/hlsl/inputs/{loop2.bin => loop2.shex} (100%) rename mlir/test/Target/DXSA/hlsl/inputs/{loop3.bin => loop3.shex} (100%) rename mlir/test/Target/DXSA/hlsl/inputs/{loop4.bin => loop4.shex} (100%) rename mlir/test/Target/DXSA/hlsl/inputs/{loop5.bin => loop5.shex} (100%) rename mlir/test/Target/DXSA/hlsl/inputs/{minprec1.bin => minprec1.shex} (100%) rename mlir/test/Target/DXSA/hlsl/inputs/{minprec2.bin => minprec2.shex} (100%) rename mlir/test/Target/DXSA/hlsl/inputs/{minprec3.bin => minprec3.shex} (100%) rename mlir/test/Target/DXSA/hlsl/inputs/{minprec4.bin => minprec4.shex} (100%) rename mlir/test/Target/DXSA/hlsl/inputs/{minprec5.bin => minprec5.shex} (100%) rename mlir/test/Target/DXSA/hlsl/inputs/{minprec6.bin => minprec6.shex} (100%) rename mlir/test/Target/DXSA/hlsl/inputs/{minprec7.bin => minprec7.shex} (100%) rename mlir/test/Target/DXSA/hlsl/inputs/{neg1.bin => neg1.shex} (100%) rename mlir/test/Target/DXSA/hlsl/inputs/{neg2.bin => neg2.shex} (100%) rename mlir/test/Target/DXSA/hlsl/inputs/{negabs1.bin => negabs1.shex} (100%) rename mlir/test/Target/DXSA/hlsl/inputs/{nonuniform1.bin => nonuniform1.shex} (100%) rename mlir/test/Target/DXSA/hlsl/inputs/{output1.bin => output1.shex} (100%) rename mlir/test/Target/DXSA/hlsl/inputs/{output2.bin => output2.shex} (100%) rename mlir/test/Target/DXSA/hlsl/inputs/{output3.bin => output3.shex} (100%) rename mlir/test/Target/DXSA/hlsl/inputs/{output4.bin => output4.shex} (100%) rename mlir/test/Target/DXSA/hlsl/inputs/{passthrough1.bin => passthrough1.shex} (100%) rename mlir/test/Target/DXSA/hlsl/inputs/{passthrough2.bin => passthrough2.shex} (100%) rename mlir/test/Target/DXSA/hlsl/inputs/{precise1.bin => precise1.shex} (100%) rename mlir/test/Target/DXSA/hlsl/inputs/{raw_buf1.bin => raw_buf1.shex} (100%) rename mlir/test/Target/DXSA/hlsl/inputs/{rcp1.bin => rcp1.shex} (100%) rename mlir/test/Target/DXSA/hlsl/inputs/{redundantinput1.bin => redundantinput1.shex} (100%) rename mlir/test/Target/DXSA/hlsl/inputs/{sample1.bin => sample1.shex} (100%) rename mlir/test/Target/DXSA/hlsl/inputs/{sample2.bin => sample2.shex} (100%) rename mlir/test/Target/DXSA/hlsl/inputs/{sample3.bin => sample3.shex} (100%) rename mlir/test/Target/DXSA/hlsl/inputs/{sample_b1.bin => sample_b1.shex} (100%) rename mlir/test/Target/DXSA/hlsl/inputs/{sample_cmp1.bin => sample_cmp1.shex} (100%) rename mlir/test/Target/DXSA/hlsl/inputs/{sample_cmp2.bin => sample_cmp2.shex} (100%) rename mlir/test/Target/DXSA/hlsl/inputs/{sample_grad1.bin => sample_grad1.shex} (100%) rename mlir/test/Target/DXSA/hlsl/inputs/{sample_l1.bin => sample_l1.shex} (100%) rename mlir/test/Target/DXSA/hlsl/inputs/{samplecount.bin => samplecount.shex} (100%) rename mlir/test/Target/DXSA/hlsl/inputs/{samplepos.bin => samplepos.shex} (100%) rename mlir/test/Target/DXSA/hlsl/inputs/{saturate1.bin => saturate1.shex} (100%) rename mlir/test/Target/DXSA/hlsl/inputs/{shift1.bin => shift1.shex} (100%) rename mlir/test/Target/DXSA/hlsl/inputs/{sincos.bin => sincos.shex} (100%) rename mlir/test/Target/DXSA/hlsl/inputs/{snorm1.bin => snorm1.shex} (100%) rename mlir/test/Target/DXSA/hlsl/inputs/{srv_ms_load1.bin => srv_ms_load1.shex} (100%) rename mlir/test/Target/DXSA/hlsl/inputs/{srv_typed_load1.bin => srv_typed_load1.shex} (100%) rename mlir/test/Target/DXSA/hlsl/inputs/{srv_typed_load2.bin => srv_typed_load2.shex} (100%) rename mlir/test/Target/DXSA/hlsl/inputs/{struct_buf1.bin => struct_buf1.shex} (100%) rename mlir/test/Target/DXSA/hlsl/inputs/{sub1.bin => sub1.shex} (100%) rename mlir/test/Target/DXSA/hlsl/inputs/{switch1.bin => switch1.shex} (100%) rename mlir/test/Target/DXSA/hlsl/inputs/{switch2.bin => switch2.shex} (100%) rename mlir/test/Target/DXSA/hlsl/inputs/{switch3.bin => switch3.shex} (100%) rename mlir/test/Target/DXSA/hlsl/inputs/{swizzle1.bin => swizzle1.shex} (100%) rename mlir/test/Target/DXSA/hlsl/inputs/{temp1.bin => temp1.shex} (100%) rename mlir/test/Target/DXSA/hlsl/inputs/{temp2.bin => temp2.shex} (100%) rename mlir/test/Target/DXSA/hlsl/inputs/{uav_counter_dec.bin => uav_counter_dec.shex} (100%) rename mlir/test/Target/DXSA/hlsl/inputs/{uav_counter_inc.bin => uav_counter_inc.shex} (100%) rename mlir/test/Target/DXSA/hlsl/inputs/{uav_raw1.bin => uav_raw1.shex} (100%) rename mlir/test/Target/DXSA/hlsl/inputs/{uav_typed_load_store1.bin => uav_typed_load_store1.shex} (100%) rename mlir/test/Target/DXSA/hlsl/inputs/{uav_typed_load_store2.bin => uav_typed_load_store2.shex} (100%) rename mlir/test/Target/DXSA/hlsl/inputs/{ubfeu16.bin => ubfeu16.shex} (100%) diff --git a/mlir/test/Target/DXSA/asm/call2.test b/mlir/test/Target/DXSA/asm/call2.test index 6204c7f4d601..3fca3f1e3d23 100644 --- a/mlir/test/Target/DXSA/asm/call2.test +++ b/mlir/test/Target/DXSA/asm/call2.test @@ -1,13 +1,6 @@ -// RUN: mlir-translate --import-dxsa-bin %S/inputs/call2.bin | FileCheck %s +// RUN: mlir-translate --import-dxsa-bin %S/inputs/call2.shex | FileCheck %s // NOTE: Assertions have been autogenerated by utils/generate-test-checks.py -// This script is intended to make adding checks to a test case quick and easy. -// It is *not* authoritative about what constitutes a good test. After using the -// script, be sure to review and refine the generated checks. For example, -// CHECK lines should be minimized and named to reflect the test’s intent. -// For comprehensive guidelines, see: -// * https://mlir.llvm.org/getting_started/TestingGuide/ - // CHECK-LABEL: dxsa.dcl_global_flags // CHECK: dxsa.dcl_input_ps linear v<0, > diff --git a/mlir/test/Target/DXSA/asm/cs3.test b/mlir/test/Target/DXSA/asm/cs3.test index 1942c5044224..6c2956b732f8 100644 --- a/mlir/test/Target/DXSA/asm/cs3.test +++ b/mlir/test/Target/DXSA/asm/cs3.test @@ -1,13 +1,6 @@ -// RUN: mlir-translate --import-dxsa-bin %S/inputs/cs3.bin | FileCheck %s +// RUN: mlir-translate --import-dxsa-bin %S/inputs/cs3.shex | FileCheck %s // NOTE: Assertions have been autogenerated by utils/generate-test-checks.py -// This script is intended to make adding checks to a test case quick and easy. -// It is *not* authoritative about what constitutes a good test. After using the -// script, be sure to review and refine the generated checks. For example, -// CHECK lines should be minimized and named to reflect the test’s intent. -// For comprehensive guidelines, see: -// * https://mlir.llvm.org/getting_started/TestingGuide/ - // CHECK-LABEL: dxsa.dcl_global_flags // CHECK: dxsa.dcl_constant_buffer , diff --git a/mlir/test/Target/DXSA/asm/cyclecounter.test b/mlir/test/Target/DXSA/asm/cyclecounter.test index 308e5a316157..f5d8ffdb90bb 100644 --- a/mlir/test/Target/DXSA/asm/cyclecounter.test +++ b/mlir/test/Target/DXSA/asm/cyclecounter.test @@ -1,13 +1,6 @@ -// RUN: mlir-translate --import-dxsa-bin %S/inputs/cyclecounter.bin | FileCheck %s +// RUN: mlir-translate --import-dxsa-bin %S/inputs/cyclecounter.shex | FileCheck %s // NOTE: Assertions have been autogenerated by utils/generate-test-checks.py -// This script is intended to make adding checks to a test case quick and easy. -// It is *not* authoritative about what constitutes a good test. After using the -// script, be sure to review and refine the generated checks. For example, -// CHECK lines should be minimized and named to reflect the test’s intent. -// For comprehensive guidelines, see: -// * https://mlir.llvm.org/getting_started/TestingGuide/ - // CHECK-LABEL: dxsa.dcl_temps 1 // CHECK: dxsa.dcl_output o<0> diff --git a/mlir/test/Target/DXSA/asm/hs3.test b/mlir/test/Target/DXSA/asm/hs3.test index 38bf63bc5154..785a22cc1244 100644 --- a/mlir/test/Target/DXSA/asm/hs3.test +++ b/mlir/test/Target/DXSA/asm/hs3.test @@ -1,13 +1,6 @@ -// RUN: mlir-translate --import-dxsa-bin %S/inputs/hs3.bin | FileCheck %s +// RUN: mlir-translate --import-dxsa-bin %S/inputs/hs3.shex | FileCheck %s // NOTE: Assertions have been autogenerated by utils/generate-test-checks.py -// This script is intended to make adding checks to a test case quick and easy. -// It is *not* authoritative about what constitutes a good test. After using the -// script, be sure to review and refine the generated checks. For example, -// CHECK lines should be minimized and named to reflect the test’s intent. -// For comprehensive guidelines, see: -// * https://mlir.llvm.org/getting_started/TestingGuide/ - // CHECK-LABEL: dxsa.instruction "hs_decls" // CHECK: dxsa.dcl_input_control_point_count 4 diff --git a/mlir/test/Target/DXSA/asm/indexabletemp4.test b/mlir/test/Target/DXSA/asm/indexabletemp4.test index 7646e2d3bf02..60bb8372393a 100644 --- a/mlir/test/Target/DXSA/asm/indexabletemp4.test +++ b/mlir/test/Target/DXSA/asm/indexabletemp4.test @@ -1,13 +1,6 @@ -// RUN: mlir-translate --import-dxsa-bin %S/inputs/indexabletemp4.bin | FileCheck %s +// RUN: mlir-translate --import-dxsa-bin %S/inputs/indexabletemp4.shex | FileCheck %s // NOTE: Assertions have been autogenerated by utils/generate-test-checks.py -// This script is intended to make adding checks to a test case quick and easy. -// It is *not* authoritative about what constitutes a good test. After using the -// script, be sure to review and refine the generated checks. For example, -// CHECK lines should be minimized and named to reflect the test’s intent. -// For comprehensive guidelines, see: -// * https://mlir.llvm.org/getting_started/TestingGuide/ - // CHECK-LABEL: dxsa.dcl_global_flags // CHECK: dxsa.dcl_constant_buffer , diff --git a/mlir/test/Target/DXSA/asm/indexabletemp6.test b/mlir/test/Target/DXSA/asm/indexabletemp6.test index 8785ecc63bf5..3b3eea3ef872 100644 --- a/mlir/test/Target/DXSA/asm/indexabletemp6.test +++ b/mlir/test/Target/DXSA/asm/indexabletemp6.test @@ -1,13 +1,6 @@ -// RUN: mlir-translate --import-dxsa-bin %S/inputs/indexabletemp6.bin | FileCheck %s +// RUN: mlir-translate --import-dxsa-bin %S/inputs/indexabletemp6.shex | FileCheck %s // NOTE: Assertions have been autogenerated by utils/generate-test-checks.py -// This script is intended to make adding checks to a test case quick and easy. -// It is *not* authoritative about what constitutes a good test. After using the -// script, be sure to review and refine the generated checks. For example, -// CHECK lines should be minimized and named to reflect the test’s intent. -// For comprehensive guidelines, see: -// * https://mlir.llvm.org/getting_started/TestingGuide/ - // CHECK-LABEL: dxsa.dcl_global_flags // CHECK: dxsa.dcl_constant_buffer , diff --git a/mlir/test/Target/DXSA/asm/inputs/call2.bin b/mlir/test/Target/DXSA/asm/inputs/call2.shex similarity index 100% rename from mlir/test/Target/DXSA/asm/inputs/call2.bin rename to mlir/test/Target/DXSA/asm/inputs/call2.shex diff --git a/mlir/test/Target/DXSA/asm/inputs/cs3.bin b/mlir/test/Target/DXSA/asm/inputs/cs3.shex similarity index 100% rename from mlir/test/Target/DXSA/asm/inputs/cs3.bin rename to mlir/test/Target/DXSA/asm/inputs/cs3.shex diff --git a/mlir/test/Target/DXSA/asm/inputs/cyclecounter.bin b/mlir/test/Target/DXSA/asm/inputs/cyclecounter.shex similarity index 100% rename from mlir/test/Target/DXSA/asm/inputs/cyclecounter.bin rename to mlir/test/Target/DXSA/asm/inputs/cyclecounter.shex diff --git a/mlir/test/Target/DXSA/asm/inputs/hs3.bin b/mlir/test/Target/DXSA/asm/inputs/hs3.shex similarity index 100% rename from mlir/test/Target/DXSA/asm/inputs/hs3.bin rename to mlir/test/Target/DXSA/asm/inputs/hs3.shex diff --git a/mlir/test/Target/DXSA/asm/inputs/indexabletemp4.bin b/mlir/test/Target/DXSA/asm/inputs/indexabletemp4.shex similarity index 100% rename from mlir/test/Target/DXSA/asm/inputs/indexabletemp4.bin rename to mlir/test/Target/DXSA/asm/inputs/indexabletemp4.shex diff --git a/mlir/test/Target/DXSA/asm/inputs/indexabletemp6.bin b/mlir/test/Target/DXSA/asm/inputs/indexabletemp6.shex similarity index 100% rename from mlir/test/Target/DXSA/asm/inputs/indexabletemp6.bin rename to mlir/test/Target/DXSA/asm/inputs/indexabletemp6.shex diff --git a/mlir/test/Target/DXSA/hlsl/abs1.test b/mlir/test/Target/DXSA/hlsl/abs1.test index ec96a99e2774..ccb96e5efe5e 100644 --- a/mlir/test/Target/DXSA/hlsl/abs1.test +++ b/mlir/test/Target/DXSA/hlsl/abs1.test @@ -1,13 +1,6 @@ -// RUN: mlir-translate --import-dxsa-bin %S/inputs/abs1.bin | FileCheck %s +// RUN: mlir-translate --import-dxsa-bin %S/inputs/abs1.shex | FileCheck %s // NOTE: Assertions have been autogenerated by utils/generate-test-checks.py -// This script is intended to make adding checks to a test case quick and easy. -// It is *not* authoritative about what constitutes a good test. After using the -// script, be sure to review and refine the generated checks. For example, -// CHECK lines should be minimized and named to reflect the test’s intent. -// For comprehensive guidelines, see: -// * https://mlir.llvm.org/getting_started/TestingGuide/ - // CHECK-LABEL: dxsa.dcl_global_flags // CHECK: dxsa.dcl_input_ps linear v<0, > diff --git a/mlir/test/Target/DXSA/hlsl/abs2.test b/mlir/test/Target/DXSA/hlsl/abs2.test index 66b66e14fb49..c18d477e3056 100644 --- a/mlir/test/Target/DXSA/hlsl/abs2.test +++ b/mlir/test/Target/DXSA/hlsl/abs2.test @@ -1,13 +1,6 @@ -// RUN: mlir-translate --import-dxsa-bin %S/inputs/abs2.bin | FileCheck %s +// RUN: mlir-translate --import-dxsa-bin %S/inputs/abs2.shex | FileCheck %s // NOTE: Assertions have been autogenerated by utils/generate-test-checks.py -// This script is intended to make adding checks to a test case quick and easy. -// It is *not* authoritative about what constitutes a good test. After using the -// script, be sure to review and refine the generated checks. For example, -// CHECK lines should be minimized and named to reflect the test’s intent. -// For comprehensive guidelines, see: -// * https://mlir.llvm.org/getting_started/TestingGuide/ - // CHECK-LABEL: dxsa.dcl_global_flags // CHECK: dxsa.dcl_input_ps constant v<0, > diff --git a/mlir/test/Target/DXSA/hlsl/atomics.test b/mlir/test/Target/DXSA/hlsl/atomics.test index 0a700e93f5ec..7a86e545469f 100644 --- a/mlir/test/Target/DXSA/hlsl/atomics.test +++ b/mlir/test/Target/DXSA/hlsl/atomics.test @@ -1,13 +1,6 @@ -// RUN: mlir-translate --import-dxsa-bin %S/inputs/atomics.bin | FileCheck %s +// RUN: mlir-translate --import-dxsa-bin %S/inputs/atomics.shex | FileCheck %s // NOTE: Assertions have been autogenerated by utils/generate-test-checks.py -// This script is intended to make adding checks to a test case quick and easy. -// It is *not* authoritative about what constitutes a good test. After using the -// script, be sure to review and refine the generated checks. For example, -// CHECK lines should be minimized and named to reflect the test’s intent. -// For comprehensive guidelines, see: -// * https://mlir.llvm.org/getting_started/TestingGuide/ - // CHECK-LABEL: dxsa.dcl_global_flags // CHECK: dxsa.dcl_uav_typed , diff --git a/mlir/test/Target/DXSA/hlsl/bad_ftoi.test b/mlir/test/Target/DXSA/hlsl/bad_ftoi.test index 194ad7f38fbe..730c09e53a99 100644 --- a/mlir/test/Target/DXSA/hlsl/bad_ftoi.test +++ b/mlir/test/Target/DXSA/hlsl/bad_ftoi.test @@ -1,13 +1,6 @@ -// RUN: mlir-translate --import-dxsa-bin %S/inputs/bad_ftoi.bin | FileCheck %s +// RUN: mlir-translate --import-dxsa-bin %S/inputs/bad_ftoi.shex | FileCheck %s // NOTE: Assertions have been autogenerated by utils/generate-test-checks.py -// This script is intended to make adding checks to a test case quick and easy. -// It is *not* authoritative about what constitutes a good test. After using the -// script, be sure to review and refine the generated checks. For example, -// CHECK lines should be minimized and named to reflect the test’s intent. -// For comprehensive guidelines, see: -// * https://mlir.llvm.org/getting_started/TestingGuide/ - // CHECK-LABEL: dxsa.dcl_global_flags // CHECK: dxsa.dcl_output o<0> diff --git a/mlir/test/Target/DXSA/hlsl/binary1.test b/mlir/test/Target/DXSA/hlsl/binary1.test index 4a4b09be54b6..233bc82f6d0d 100644 --- a/mlir/test/Target/DXSA/hlsl/binary1.test +++ b/mlir/test/Target/DXSA/hlsl/binary1.test @@ -1,13 +1,6 @@ -// RUN: mlir-translate --import-dxsa-bin %S/inputs/binary1.bin | FileCheck %s +// RUN: mlir-translate --import-dxsa-bin %S/inputs/binary1.shex | FileCheck %s // NOTE: Assertions have been autogenerated by utils/generate-test-checks.py -// This script is intended to make adding checks to a test case quick and easy. -// It is *not* authoritative about what constitutes a good test. After using the -// script, be sure to review and refine the generated checks. For example, -// CHECK lines should be minimized and named to reflect the test’s intent. -// For comprehensive guidelines, see: -// * https://mlir.llvm.org/getting_started/TestingGuide/ - // CHECK-LABEL: dxsa.dcl_global_flags // CHECK: dxsa.dcl_input_ps linear v<0, > diff --git a/mlir/test/Target/DXSA/hlsl/bool1.test b/mlir/test/Target/DXSA/hlsl/bool1.test index b5e35f27036e..5412f59c8b8e 100644 --- a/mlir/test/Target/DXSA/hlsl/bool1.test +++ b/mlir/test/Target/DXSA/hlsl/bool1.test @@ -1,13 +1,6 @@ -// RUN: mlir-translate --import-dxsa-bin %S/inputs/bool1.bin | FileCheck %s +// RUN: mlir-translate --import-dxsa-bin %S/inputs/bool1.shex | FileCheck %s // NOTE: Assertions have been autogenerated by utils/generate-test-checks.py -// This script is intended to make adding checks to a test case quick and easy. -// It is *not* authoritative about what constitutes a good test. After using the -// script, be sure to review and refine the generated checks. For example, -// CHECK lines should be minimized and named to reflect the test’s intent. -// For comprehensive guidelines, see: -// * https://mlir.llvm.org/getting_started/TestingGuide/ - // CHECK-LABEL: dxsa.dcl_global_flags // CHECK: dxsa.dcl_input_ps constant v<0, > diff --git a/mlir/test/Target/DXSA/hlsl/bool2.test b/mlir/test/Target/DXSA/hlsl/bool2.test index 8208dd27b201..453b1cf7bd71 100644 --- a/mlir/test/Target/DXSA/hlsl/bool2.test +++ b/mlir/test/Target/DXSA/hlsl/bool2.test @@ -1,13 +1,6 @@ -// RUN: mlir-translate --import-dxsa-bin %S/inputs/bool2.bin | FileCheck %s +// RUN: mlir-translate --import-dxsa-bin %S/inputs/bool2.shex | FileCheck %s // NOTE: Assertions have been autogenerated by utils/generate-test-checks.py -// This script is intended to make adding checks to a test case quick and easy. -// It is *not* authoritative about what constitutes a good test. After using the -// script, be sure to review and refine the generated checks. For example, -// CHECK lines should be minimized and named to reflect the test’s intent. -// For comprehensive guidelines, see: -// * https://mlir.llvm.org/getting_started/TestingGuide/ - // CHECK-LABEL: dxsa.dcl_global_flags // CHECK: dxsa.dcl_input_ps linear v<0, > diff --git a/mlir/test/Target/DXSA/hlsl/bufinfo.test b/mlir/test/Target/DXSA/hlsl/bufinfo.test index 2ef0154b7deb..791d8f5ba964 100644 --- a/mlir/test/Target/DXSA/hlsl/bufinfo.test +++ b/mlir/test/Target/DXSA/hlsl/bufinfo.test @@ -1,13 +1,6 @@ -// RUN: mlir-translate --import-dxsa-bin %S/inputs/bufinfo.bin | FileCheck %s +// RUN: mlir-translate --import-dxsa-bin %S/inputs/bufinfo.shex | FileCheck %s // NOTE: Assertions have been autogenerated by utils/generate-test-checks.py -// This script is intended to make adding checks to a test case quick and easy. -// It is *not* authoritative about what constitutes a good test. After using the -// script, be sure to review and refine the generated checks. For example, -// CHECK lines should be minimized and named to reflect the test’s intent. -// For comprehensive guidelines, see: -// * https://mlir.llvm.org/getting_started/TestingGuide/ - // CHECK-LABEL: dxsa.dcl_global_flags // CHECK: dxsa.dcl_resource_structured diff --git a/mlir/test/Target/DXSA/hlsl/calc_lod.test b/mlir/test/Target/DXSA/hlsl/calc_lod.test index e83a32678605..a732fbcb0c8a 100644 --- a/mlir/test/Target/DXSA/hlsl/calc_lod.test +++ b/mlir/test/Target/DXSA/hlsl/calc_lod.test @@ -1,13 +1,6 @@ -// RUN: mlir-translate --import-dxsa-bin %S/inputs/calc_lod.bin | FileCheck %s +// RUN: mlir-translate --import-dxsa-bin %S/inputs/calc_lod.shex | FileCheck %s // NOTE: Assertions have been autogenerated by utils/generate-test-checks.py -// This script is intended to make adding checks to a test case quick and easy. -// It is *not* authoritative about what constitutes a good test. After using the -// script, be sure to review and refine the generated checks. For example, -// CHECK lines should be minimized and named to reflect the test’s intent. -// For comprehensive guidelines, see: -// * https://mlir.llvm.org/getting_started/TestingGuide/ - // CHECK-LABEL: dxsa.dcl_global_flags // CHECK: dxsa.dcl_sampler diff --git a/mlir/test/Target/DXSA/hlsl/call1.test b/mlir/test/Target/DXSA/hlsl/call1.test index 66973a03503a..5c39a694d183 100644 --- a/mlir/test/Target/DXSA/hlsl/call1.test +++ b/mlir/test/Target/DXSA/hlsl/call1.test @@ -1,13 +1,6 @@ -// RUN: mlir-translate --import-dxsa-bin %S/inputs/call1.bin | FileCheck %s +// RUN: mlir-translate --import-dxsa-bin %S/inputs/call1.shex | FileCheck %s // NOTE: Assertions have been autogenerated by utils/generate-test-checks.py -// This script is intended to make adding checks to a test case quick and easy. -// It is *not* authoritative about what constitutes a good test. After using the -// script, be sure to review and refine the generated checks. For example, -// CHECK lines should be minimized and named to reflect the test’s intent. -// For comprehensive guidelines, see: -// * https://mlir.llvm.org/getting_started/TestingGuide/ - // CHECK-LABEL: dxsa.dcl_global_flags // CHECK: dxsa.dcl_input_ps linear v<0, > diff --git a/mlir/test/Target/DXSA/hlsl/call3.test b/mlir/test/Target/DXSA/hlsl/call3.test index ff6d0fdca9bb..ef7d2ea3965a 100644 --- a/mlir/test/Target/DXSA/hlsl/call3.test +++ b/mlir/test/Target/DXSA/hlsl/call3.test @@ -1,13 +1,6 @@ -// RUN: mlir-translate --import-dxsa-bin %S/inputs/call3.bin | FileCheck %s +// RUN: mlir-translate --import-dxsa-bin %S/inputs/call3.shex | FileCheck %s // NOTE: Assertions have been autogenerated by utils/generate-test-checks.py -// This script is intended to make adding checks to a test case quick and easy. -// It is *not* authoritative about what constitutes a good test. After using the -// script, be sure to review and refine the generated checks. For example, -// CHECK lines should be minimized and named to reflect the test’s intent. -// For comprehensive guidelines, see: -// * https://mlir.llvm.org/getting_started/TestingGuide/ - // CHECK-LABEL: dxsa.dcl_global_flags // CHECK: dxsa.dcl_input_ps linear v<0, > diff --git a/mlir/test/Target/DXSA/hlsl/cast1.test b/mlir/test/Target/DXSA/hlsl/cast1.test index 6c10516efbe9..1956d71511d3 100644 --- a/mlir/test/Target/DXSA/hlsl/cast1.test +++ b/mlir/test/Target/DXSA/hlsl/cast1.test @@ -1,13 +1,6 @@ -// RUN: mlir-translate --import-dxsa-bin %S/inputs/cast1.bin | FileCheck %s +// RUN: mlir-translate --import-dxsa-bin %S/inputs/cast1.shex | FileCheck %s // NOTE: Assertions have been autogenerated by utils/generate-test-checks.py -// This script is intended to make adding checks to a test case quick and easy. -// It is *not* authoritative about what constitutes a good test. After using the -// script, be sure to review and refine the generated checks. For example, -// CHECK lines should be minimized and named to reflect the test’s intent. -// For comprehensive guidelines, see: -// * https://mlir.llvm.org/getting_started/TestingGuide/ - // CHECK-LABEL: dxsa.dcl_global_flags // CHECK: dxsa.dcl_input_ps constant v<0, > diff --git a/mlir/test/Target/DXSA/hlsl/cast2.test b/mlir/test/Target/DXSA/hlsl/cast2.test index 2c73e3397dff..34f09b816fa7 100644 --- a/mlir/test/Target/DXSA/hlsl/cast2.test +++ b/mlir/test/Target/DXSA/hlsl/cast2.test @@ -1,13 +1,6 @@ -// RUN: mlir-translate --import-dxsa-bin %S/inputs/cast2.bin | FileCheck %s +// RUN: mlir-translate --import-dxsa-bin %S/inputs/cast2.shex | FileCheck %s // NOTE: Assertions have been autogenerated by utils/generate-test-checks.py -// This script is intended to make adding checks to a test case quick and easy. -// It is *not* authoritative about what constitutes a good test. After using the -// script, be sure to review and refine the generated checks. For example, -// CHECK lines should be minimized and named to reflect the test’s intent. -// For comprehensive guidelines, see: -// * https://mlir.llvm.org/getting_started/TestingGuide/ - // CHECK-LABEL: dxsa.dcl_global_flags // CHECK: dxsa.dcl_input_ps constant v<0, > diff --git a/mlir/test/Target/DXSA/hlsl/cast3.test b/mlir/test/Target/DXSA/hlsl/cast3.test index 0e25e0ed0162..c3fe4baacf81 100644 --- a/mlir/test/Target/DXSA/hlsl/cast3.test +++ b/mlir/test/Target/DXSA/hlsl/cast3.test @@ -1,13 +1,6 @@ -// RUN: mlir-translate --import-dxsa-bin %S/inputs/cast3.bin | FileCheck %s +// RUN: mlir-translate --import-dxsa-bin %S/inputs/cast3.shex | FileCheck %s // NOTE: Assertions have been autogenerated by utils/generate-test-checks.py -// This script is intended to make adding checks to a test case quick and easy. -// It is *not* authoritative about what constitutes a good test. After using the -// script, be sure to review and refine the generated checks. For example, -// CHECK lines should be minimized and named to reflect the test’s intent. -// For comprehensive guidelines, see: -// * https://mlir.llvm.org/getting_started/TestingGuide/ - // CHECK-LABEL: dxsa.dcl_global_flags // CHECK: dxsa.dcl_input_ps linear v<0, > diff --git a/mlir/test/Target/DXSA/hlsl/cast4.test b/mlir/test/Target/DXSA/hlsl/cast4.test index df9f4359fc9f..a6145a6ab167 100644 --- a/mlir/test/Target/DXSA/hlsl/cast4.test +++ b/mlir/test/Target/DXSA/hlsl/cast4.test @@ -1,13 +1,6 @@ -// RUN: mlir-translate --import-dxsa-bin %S/inputs/cast4.bin | FileCheck %s +// RUN: mlir-translate --import-dxsa-bin %S/inputs/cast4.shex | FileCheck %s // NOTE: Assertions have been autogenerated by utils/generate-test-checks.py -// This script is intended to make adding checks to a test case quick and easy. -// It is *not* authoritative about what constitutes a good test. After using the -// script, be sure to review and refine the generated checks. For example, -// CHECK lines should be minimized and named to reflect the test’s intent. -// For comprehensive guidelines, see: -// * https://mlir.llvm.org/getting_started/TestingGuide/ - // CHECK-LABEL: dxsa.dcl_global_flags // CHECK: dxsa.dcl_input_ps linear v<0, > diff --git a/mlir/test/Target/DXSA/hlsl/cast5.test b/mlir/test/Target/DXSA/hlsl/cast5.test index a7061094e09d..eb1abcfc9ff0 100644 --- a/mlir/test/Target/DXSA/hlsl/cast5.test +++ b/mlir/test/Target/DXSA/hlsl/cast5.test @@ -1,13 +1,6 @@ -// RUN: mlir-translate --import-dxsa-bin %S/inputs/cast5.bin | FileCheck %s +// RUN: mlir-translate --import-dxsa-bin %S/inputs/cast5.shex | FileCheck %s // NOTE: Assertions have been autogenerated by utils/generate-test-checks.py -// This script is intended to make adding checks to a test case quick and easy. -// It is *not* authoritative about what constitutes a good test. After using the -// script, be sure to review and refine the generated checks. For example, -// CHECK lines should be minimized and named to reflect the test’s intent. -// For comprehensive guidelines, see: -// * https://mlir.llvm.org/getting_started/TestingGuide/ - // CHECK-LABEL: dxsa.dcl_global_flags // CHECK: dxsa.dcl_input_ps linear v<0, min16f, > diff --git a/mlir/test/Target/DXSA/hlsl/cast6.test b/mlir/test/Target/DXSA/hlsl/cast6.test index a9d5687069c9..f8c764a8ad13 100644 --- a/mlir/test/Target/DXSA/hlsl/cast6.test +++ b/mlir/test/Target/DXSA/hlsl/cast6.test @@ -1,13 +1,6 @@ -// RUN: mlir-translate --import-dxsa-bin %S/inputs/cast6.bin | FileCheck %s +// RUN: mlir-translate --import-dxsa-bin %S/inputs/cast6.shex | FileCheck %s // NOTE: Assertions have been autogenerated by utils/generate-test-checks.py -// This script is intended to make adding checks to a test case quick and easy. -// It is *not* authoritative about what constitutes a good test. After using the -// script, be sure to review and refine the generated checks. For example, -// CHECK lines should be minimized and named to reflect the test’s intent. -// For comprehensive guidelines, see: -// * https://mlir.llvm.org/getting_started/TestingGuide/ - // CHECK-LABEL: dxsa.dcl_global_flags // CHECK: dxsa.dcl_input_ps linear v<0, > diff --git a/mlir/test/Target/DXSA/hlsl/cbuffer1.50.test b/mlir/test/Target/DXSA/hlsl/cbuffer1.50.test index 118713206653..bb47f9904b5f 100644 --- a/mlir/test/Target/DXSA/hlsl/cbuffer1.50.test +++ b/mlir/test/Target/DXSA/hlsl/cbuffer1.50.test @@ -1,13 +1,6 @@ -// RUN: mlir-translate --import-dxsa-bin %S/inputs/cbuffer1.50.bin | FileCheck %s +// RUN: mlir-translate --import-dxsa-bin %S/inputs/cbuffer1.50.shex | FileCheck %s // NOTE: Assertions have been autogenerated by utils/generate-test-checks.py -// This script is intended to make adding checks to a test case quick and easy. -// It is *not* authoritative about what constitutes a good test. After using the -// script, be sure to review and refine the generated checks. For example, -// CHECK lines should be minimized and named to reflect the test’s intent. -// For comprehensive guidelines, see: -// * https://mlir.llvm.org/getting_started/TestingGuide/ - // CHECK-LABEL: dxsa.dcl_global_flags // CHECK: dxsa.dcl_constant_buffer , diff --git a/mlir/test/Target/DXSA/hlsl/cbuffer1.51.test b/mlir/test/Target/DXSA/hlsl/cbuffer1.51.test index edc689932965..1f03d9b16f87 100644 --- a/mlir/test/Target/DXSA/hlsl/cbuffer1.51.test +++ b/mlir/test/Target/DXSA/hlsl/cbuffer1.51.test @@ -1,13 +1,6 @@ -// RUN: mlir-translate --import-dxsa-bin %S/inputs/cbuffer1.51.bin | FileCheck %s +// RUN: mlir-translate --import-dxsa-bin %S/inputs/cbuffer1.51.shex | FileCheck %s // NOTE: Assertions have been autogenerated by utils/generate-test-checks.py -// This script is intended to make adding checks to a test case quick and easy. -// It is *not* authoritative about what constitutes a good test. After using the -// script, be sure to review and refine the generated checks. For example, -// CHECK lines should be minimized and named to reflect the test’s intent. -// For comprehensive guidelines, see: -// * https://mlir.llvm.org/getting_started/TestingGuide/ - // CHECK-LABEL: dxsa.dcl_global_flags // CHECK: dxsa.dcl_constant_buffer , diff --git a/mlir/test/Target/DXSA/hlsl/cbuffer2.50.test b/mlir/test/Target/DXSA/hlsl/cbuffer2.50.test index af3489a1fdb3..6dcc15990f42 100644 --- a/mlir/test/Target/DXSA/hlsl/cbuffer2.50.test +++ b/mlir/test/Target/DXSA/hlsl/cbuffer2.50.test @@ -1,13 +1,6 @@ -// RUN: mlir-translate --import-dxsa-bin %S/inputs/cbuffer2.50.bin | FileCheck %s +// RUN: mlir-translate --import-dxsa-bin %S/inputs/cbuffer2.50.shex | FileCheck %s // NOTE: Assertions have been autogenerated by utils/generate-test-checks.py -// This script is intended to make adding checks to a test case quick and easy. -// It is *not* authoritative about what constitutes a good test. After using the -// script, be sure to review and refine the generated checks. For example, -// CHECK lines should be minimized and named to reflect the test’s intent. -// For comprehensive guidelines, see: -// * https://mlir.llvm.org/getting_started/TestingGuide/ - // CHECK-LABEL: dxsa.dcl_global_flags // CHECK: dxsa.dcl_constant_buffer , diff --git a/mlir/test/Target/DXSA/hlsl/cbuffer2.51.test b/mlir/test/Target/DXSA/hlsl/cbuffer2.51.test index aa029652dca5..4bcb8351a9e2 100644 --- a/mlir/test/Target/DXSA/hlsl/cbuffer2.51.test +++ b/mlir/test/Target/DXSA/hlsl/cbuffer2.51.test @@ -1,13 +1,6 @@ -// RUN: mlir-translate --import-dxsa-bin %S/inputs/cbuffer2.51.bin | FileCheck %s +// RUN: mlir-translate --import-dxsa-bin %S/inputs/cbuffer2.51.shex | FileCheck %s // NOTE: Assertions have been autogenerated by utils/generate-test-checks.py -// This script is intended to make adding checks to a test case quick and easy. -// It is *not* authoritative about what constitutes a good test. After using the -// script, be sure to review and refine the generated checks. For example, -// CHECK lines should be minimized and named to reflect the test’s intent. -// For comprehensive guidelines, see: -// * https://mlir.llvm.org/getting_started/TestingGuide/ - // CHECK-LABEL: dxsa.dcl_global_flags // CHECK: dxsa.dcl_constant_buffer , diff --git a/mlir/test/Target/DXSA/hlsl/cbuffer3.50.test b/mlir/test/Target/DXSA/hlsl/cbuffer3.50.test index 4677489c6818..bc1dd5d73bd6 100644 --- a/mlir/test/Target/DXSA/hlsl/cbuffer3.50.test +++ b/mlir/test/Target/DXSA/hlsl/cbuffer3.50.test @@ -1,13 +1,6 @@ -// RUN: mlir-translate --import-dxsa-bin %S/inputs/cbuffer3.50.bin | FileCheck %s +// RUN: mlir-translate --import-dxsa-bin %S/inputs/cbuffer3.50.shex | FileCheck %s // NOTE: Assertions have been autogenerated by utils/generate-test-checks.py -// This script is intended to make adding checks to a test case quick and easy. -// It is *not* authoritative about what constitutes a good test. After using the -// script, be sure to review and refine the generated checks. For example, -// CHECK lines should be minimized and named to reflect the test’s intent. -// For comprehensive guidelines, see: -// * https://mlir.llvm.org/getting_started/TestingGuide/ - // CHECK-LABEL: dxsa.dcl_global_flags // CHECK: dxsa.dcl_constant_buffer , diff --git a/mlir/test/Target/DXSA/hlsl/cbuffer3.51.test b/mlir/test/Target/DXSA/hlsl/cbuffer3.51.test index 3d370b0d61ea..2f8c9058af9e 100644 --- a/mlir/test/Target/DXSA/hlsl/cbuffer3.51.test +++ b/mlir/test/Target/DXSA/hlsl/cbuffer3.51.test @@ -1,13 +1,6 @@ -// RUN: mlir-translate --import-dxsa-bin %S/inputs/cbuffer3.51.bin | FileCheck %s +// RUN: mlir-translate --import-dxsa-bin %S/inputs/cbuffer3.51.shex | FileCheck %s // NOTE: Assertions have been autogenerated by utils/generate-test-checks.py -// This script is intended to make adding checks to a test case quick and easy. -// It is *not* authoritative about what constitutes a good test. After using the -// script, be sure to review and refine the generated checks. For example, -// CHECK lines should be minimized and named to reflect the test’s intent. -// For comprehensive guidelines, see: -// * https://mlir.llvm.org/getting_started/TestingGuide/ - // CHECK-LABEL: dxsa.dcl_global_flags // CHECK: dxsa.dcl_constant_buffer , diff --git a/mlir/test/Target/DXSA/hlsl/cmp1.test b/mlir/test/Target/DXSA/hlsl/cmp1.test index 1152b8ae17cd..2f6548c3084c 100644 --- a/mlir/test/Target/DXSA/hlsl/cmp1.test +++ b/mlir/test/Target/DXSA/hlsl/cmp1.test @@ -1,13 +1,6 @@ -// RUN: mlir-translate --import-dxsa-bin %S/inputs/cmp1.bin | FileCheck %s +// RUN: mlir-translate --import-dxsa-bin %S/inputs/cmp1.shex | FileCheck %s // NOTE: Assertions have been autogenerated by utils/generate-test-checks.py -// This script is intended to make adding checks to a test case quick and easy. -// It is *not* authoritative about what constitutes a good test. After using the -// script, be sure to review and refine the generated checks. For example, -// CHECK lines should be minimized and named to reflect the test’s intent. -// For comprehensive guidelines, see: -// * https://mlir.llvm.org/getting_started/TestingGuide/ - // CHECK-LABEL: dxsa.dcl_global_flags // CHECK: dxsa.dcl_input_ps linear v<0, > diff --git a/mlir/test/Target/DXSA/hlsl/constoperand1.test b/mlir/test/Target/DXSA/hlsl/constoperand1.test index 1bfbc4393dd9..72fefcdef7b9 100644 --- a/mlir/test/Target/DXSA/hlsl/constoperand1.test +++ b/mlir/test/Target/DXSA/hlsl/constoperand1.test @@ -1,13 +1,6 @@ -// RUN: mlir-translate --import-dxsa-bin %S/inputs/constoperand1.bin | FileCheck %s +// RUN: mlir-translate --import-dxsa-bin %S/inputs/constoperand1.shex | FileCheck %s // NOTE: Assertions have been autogenerated by utils/generate-test-checks.py -// This script is intended to make adding checks to a test case quick and easy. -// It is *not* authoritative about what constitutes a good test. After using the -// script, be sure to review and refine the generated checks. For example, -// CHECK lines should be minimized and named to reflect the test’s intent. -// For comprehensive guidelines, see: -// * https://mlir.llvm.org/getting_started/TestingGuide/ - // CHECK-LABEL: dxsa.dcl_global_flags // CHECK: dxsa.dcl_output_siv o<0>, diff --git a/mlir/test/Target/DXSA/hlsl/cs1.test b/mlir/test/Target/DXSA/hlsl/cs1.test index 3a9013e420f8..a0421cd28860 100644 --- a/mlir/test/Target/DXSA/hlsl/cs1.test +++ b/mlir/test/Target/DXSA/hlsl/cs1.test @@ -1,13 +1,6 @@ -// RUN: mlir-translate --import-dxsa-bin %S/inputs/cs1.bin | FileCheck %s +// RUN: mlir-translate --import-dxsa-bin %S/inputs/cs1.shex | FileCheck %s // NOTE: Assertions have been autogenerated by utils/generate-test-checks.py -// This script is intended to make adding checks to a test case quick and easy. -// It is *not* authoritative about what constitutes a good test. After using the -// script, be sure to review and refine the generated checks. For example, -// CHECK lines should be minimized and named to reflect the test’s intent. -// For comprehensive guidelines, see: -// * https://mlir.llvm.org/getting_started/TestingGuide/ - // CHECK-LABEL: dxsa.dcl_global_flags // CHECK: dxsa.dcl_uav_raw diff --git a/mlir/test/Target/DXSA/hlsl/cs2.test b/mlir/test/Target/DXSA/hlsl/cs2.test index a5dc33a053a2..03b99ca7eefd 100644 --- a/mlir/test/Target/DXSA/hlsl/cs2.test +++ b/mlir/test/Target/DXSA/hlsl/cs2.test @@ -1,13 +1,6 @@ -// RUN: mlir-translate --import-dxsa-bin %S/inputs/cs2.bin | FileCheck %s +// RUN: mlir-translate --import-dxsa-bin %S/inputs/cs2.shex | FileCheck %s // NOTE: Assertions have been autogenerated by utils/generate-test-checks.py -// This script is intended to make adding checks to a test case quick and easy. -// It is *not* authoritative about what constitutes a good test. After using the -// script, be sure to review and refine the generated checks. For example, -// CHECK lines should be minimized and named to reflect the test’s intent. -// For comprehensive guidelines, see: -// * https://mlir.llvm.org/getting_started/TestingGuide/ - // CHECK-LABEL: dxsa.dcl_global_flags // CHECK: dxsa.dcl_constant_buffer , diff --git a/mlir/test/Target/DXSA/hlsl/cs4.test b/mlir/test/Target/DXSA/hlsl/cs4.test index 7ad619584340..74aea79d045b 100644 --- a/mlir/test/Target/DXSA/hlsl/cs4.test +++ b/mlir/test/Target/DXSA/hlsl/cs4.test @@ -1,13 +1,6 @@ -// RUN: mlir-translate --import-dxsa-bin %S/inputs/cs4.bin | FileCheck %s +// RUN: mlir-translate --import-dxsa-bin %S/inputs/cs4.shex | FileCheck %s // NOTE: Assertions have been autogenerated by utils/generate-test-checks.py -// This script is intended to make adding checks to a test case quick and easy. -// It is *not* authoritative about what constitutes a good test. After using the -// script, be sure to review and refine the generated checks. For example, -// CHECK lines should be minimized and named to reflect the test’s intent. -// For comprehensive guidelines, see: -// * https://mlir.llvm.org/getting_started/TestingGuide/ - // CHECK-LABEL: dxsa.dcl_global_flags // CHECK: dxsa.dcl_constant_buffer , diff --git a/mlir/test/Target/DXSA/hlsl/cs5.test b/mlir/test/Target/DXSA/hlsl/cs5.test index efb1b13e6935..b23cd681146a 100644 --- a/mlir/test/Target/DXSA/hlsl/cs5.test +++ b/mlir/test/Target/DXSA/hlsl/cs5.test @@ -1,13 +1,6 @@ -// RUN: mlir-translate --import-dxsa-bin %S/inputs/cs5.bin | FileCheck %s +// RUN: mlir-translate --import-dxsa-bin %S/inputs/cs5.shex | FileCheck %s // NOTE: Assertions have been autogenerated by utils/generate-test-checks.py -// This script is intended to make adding checks to a test case quick and easy. -// It is *not* authoritative about what constitutes a good test. After using the -// script, be sure to review and refine the generated checks. For example, -// CHECK lines should be minimized and named to reflect the test’s intent. -// For comprehensive guidelines, see: -// * https://mlir.llvm.org/getting_started/TestingGuide/ - // CHECK-LABEL: dxsa.dcl_global_flags // CHECK: dxsa.dcl_constant_buffer , diff --git a/mlir/test/Target/DXSA/hlsl/derivatives.test b/mlir/test/Target/DXSA/hlsl/derivatives.test index ebfd5c4d464e..67f68e01e02d 100644 --- a/mlir/test/Target/DXSA/hlsl/derivatives.test +++ b/mlir/test/Target/DXSA/hlsl/derivatives.test @@ -1,13 +1,6 @@ -// RUN: mlir-translate --import-dxsa-bin %S/inputs/derivatives.bin | FileCheck %s +// RUN: mlir-translate --import-dxsa-bin %S/inputs/derivatives.shex | FileCheck %s // NOTE: Assertions have been autogenerated by utils/generate-test-checks.py -// This script is intended to make adding checks to a test case quick and easy. -// It is *not* authoritative about what constitutes a good test. After using the -// script, be sure to review and refine the generated checks. For example, -// CHECK lines should be minimized and named to reflect the test’s intent. -// For comprehensive guidelines, see: -// * https://mlir.llvm.org/getting_started/TestingGuide/ - // CHECK-LABEL: dxsa.dcl_global_flags // CHECK: dxsa.dcl_input_ps linear v<0> diff --git a/mlir/test/Target/DXSA/hlsl/discard.test b/mlir/test/Target/DXSA/hlsl/discard.test index bcd54ecfcd3e..18ae05c61835 100644 --- a/mlir/test/Target/DXSA/hlsl/discard.test +++ b/mlir/test/Target/DXSA/hlsl/discard.test @@ -1,13 +1,6 @@ -// RUN: mlir-translate --import-dxsa-bin %S/inputs/discard.bin | FileCheck %s +// RUN: mlir-translate --import-dxsa-bin %S/inputs/discard.shex | FileCheck %s // NOTE: Assertions have been autogenerated by utils/generate-test-checks.py -// This script is intended to make adding checks to a test case quick and easy. -// It is *not* authoritative about what constitutes a good test. After using the -// script, be sure to review and refine the generated checks. For example, -// CHECK lines should be minimized and named to reflect the test’s intent. -// For comprehensive guidelines, see: -// * https://mlir.llvm.org/getting_started/TestingGuide/ - // CHECK-LABEL: dxsa.dcl_global_flags // CHECK: dxsa.dcl_input_ps linear v<0, > diff --git a/mlir/test/Target/DXSA/hlsl/dot1.test b/mlir/test/Target/DXSA/hlsl/dot1.test index 8af54616e298..4bfeac07ab74 100644 --- a/mlir/test/Target/DXSA/hlsl/dot1.test +++ b/mlir/test/Target/DXSA/hlsl/dot1.test @@ -1,13 +1,6 @@ -// RUN: mlir-translate --import-dxsa-bin %S/inputs/dot1.bin | FileCheck %s +// RUN: mlir-translate --import-dxsa-bin %S/inputs/dot1.shex | FileCheck %s // NOTE: Assertions have been autogenerated by utils/generate-test-checks.py -// This script is intended to make adding checks to a test case quick and easy. -// It is *not* authoritative about what constitutes a good test. After using the -// script, be sure to review and refine the generated checks. For example, -// CHECK lines should be minimized and named to reflect the test’s intent. -// For comprehensive guidelines, see: -// * https://mlir.llvm.org/getting_started/TestingGuide/ - // CHECK-LABEL: dxsa.dcl_global_flags // CHECK: dxsa.dcl_input_ps linear v<0> diff --git a/mlir/test/Target/DXSA/hlsl/double1.test b/mlir/test/Target/DXSA/hlsl/double1.test index 52d7cfe722cf..2c880f6815d5 100644 --- a/mlir/test/Target/DXSA/hlsl/double1.test +++ b/mlir/test/Target/DXSA/hlsl/double1.test @@ -1,13 +1,6 @@ -// RUN: mlir-translate --import-dxsa-bin %S/inputs/double1.bin | FileCheck %s +// RUN: mlir-translate --import-dxsa-bin %S/inputs/double1.shex | FileCheck %s // NOTE: Assertions have been autogenerated by utils/generate-test-checks.py -// This script is intended to make adding checks to a test case quick and easy. -// It is *not* authoritative about what constitutes a good test. After using the -// script, be sure to review and refine the generated checks. For example, -// CHECK lines should be minimized and named to reflect the test’s intent. -// For comprehensive guidelines, see: -// * https://mlir.llvm.org/getting_started/TestingGuide/ - // CHECK-LABEL: dxsa.dcl_global_flags // CHECK: dxsa.dcl_input_ps constant v<0, > diff --git a/mlir/test/Target/DXSA/hlsl/double2.test b/mlir/test/Target/DXSA/hlsl/double2.test index dbcbfd8ecab1..d658176c9e6b 100644 --- a/mlir/test/Target/DXSA/hlsl/double2.test +++ b/mlir/test/Target/DXSA/hlsl/double2.test @@ -1,13 +1,6 @@ -// RUN: mlir-translate --import-dxsa-bin %S/inputs/double2.bin | FileCheck %s +// RUN: mlir-translate --import-dxsa-bin %S/inputs/double2.shex | FileCheck %s // NOTE: Assertions have been autogenerated by utils/generate-test-checks.py -// This script is intended to make adding checks to a test case quick and easy. -// It is *not* authoritative about what constitutes a good test. After using the -// script, be sure to review and refine the generated checks. For example, -// CHECK lines should be minimized and named to reflect the test’s intent. -// For comprehensive guidelines, see: -// * https://mlir.llvm.org/getting_started/TestingGuide/ - // CHECK-LABEL: dxsa.dcl_global_flags // CHECK: dxsa.dcl_constant_buffer , diff --git a/mlir/test/Target/DXSA/hlsl/double3.test b/mlir/test/Target/DXSA/hlsl/double3.test index 98339a36cfa6..889c12592b58 100644 --- a/mlir/test/Target/DXSA/hlsl/double3.test +++ b/mlir/test/Target/DXSA/hlsl/double3.test @@ -1,13 +1,6 @@ -// RUN: mlir-translate --import-dxsa-bin %S/inputs/double3.bin | FileCheck %s +// RUN: mlir-translate --import-dxsa-bin %S/inputs/double3.shex | FileCheck %s // NOTE: Assertions have been autogenerated by utils/generate-test-checks.py -// This script is intended to make adding checks to a test case quick and easy. -// It is *not* authoritative about what constitutes a good test. After using the -// script, be sure to review and refine the generated checks. For example, -// CHECK lines should be minimized and named to reflect the test’s intent. -// For comprehensive guidelines, see: -// * https://mlir.llvm.org/getting_started/TestingGuide/ - // CHECK-LABEL: dxsa.dcl_global_flags // CHECK: dxsa.dcl_input_ps constant v<0, > diff --git a/mlir/test/Target/DXSA/hlsl/double4.test b/mlir/test/Target/DXSA/hlsl/double4.test index 08bfd41d4293..7f6e6a67aca7 100644 --- a/mlir/test/Target/DXSA/hlsl/double4.test +++ b/mlir/test/Target/DXSA/hlsl/double4.test @@ -1,13 +1,6 @@ -// RUN: mlir-translate --import-dxsa-bin %S/inputs/double4.bin | FileCheck %s +// RUN: mlir-translate --import-dxsa-bin %S/inputs/double4.shex | FileCheck %s // NOTE: Assertions have been autogenerated by utils/generate-test-checks.py -// This script is intended to make adding checks to a test case quick and easy. -// It is *not* authoritative about what constitutes a good test. After using the -// script, be sure to review and refine the generated checks. For example, -// CHECK lines should be minimized and named to reflect the test’s intent. -// For comprehensive guidelines, see: -// * https://mlir.llvm.org/getting_started/TestingGuide/ - // CHECK-LABEL: dxsa.dcl_global_flags // CHECK: dxsa.dcl_input_ps constant v<0> diff --git a/mlir/test/Target/DXSA/hlsl/double5.test b/mlir/test/Target/DXSA/hlsl/double5.test index c719f0fb3f81..d2300837788a 100644 --- a/mlir/test/Target/DXSA/hlsl/double5.test +++ b/mlir/test/Target/DXSA/hlsl/double5.test @@ -1,13 +1,6 @@ -// RUN: mlir-translate --import-dxsa-bin %S/inputs/double5.bin | FileCheck %s +// RUN: mlir-translate --import-dxsa-bin %S/inputs/double5.shex | FileCheck %s // NOTE: Assertions have been autogenerated by utils/generate-test-checks.py -// This script is intended to make adding checks to a test case quick and easy. -// It is *not* authoritative about what constitutes a good test. After using the -// script, be sure to review and refine the generated checks. For example, -// CHECK lines should be minimized and named to reflect the test’s intent. -// For comprehensive guidelines, see: -// * https://mlir.llvm.org/getting_started/TestingGuide/ - // CHECK-LABEL: dxsa.dcl_global_flags // CHECK: dxsa.dcl_input_ps constant v<0, > diff --git a/mlir/test/Target/DXSA/hlsl/double6.test b/mlir/test/Target/DXSA/hlsl/double6.test index d082fc9ed7fc..91641c7ac8f9 100644 --- a/mlir/test/Target/DXSA/hlsl/double6.test +++ b/mlir/test/Target/DXSA/hlsl/double6.test @@ -1,13 +1,6 @@ -// RUN: mlir-translate --import-dxsa-bin %S/inputs/double6.bin | FileCheck %s +// RUN: mlir-translate --import-dxsa-bin %S/inputs/double6.shex | FileCheck %s // NOTE: Assertions have been autogenerated by utils/generate-test-checks.py -// This script is intended to make adding checks to a test case quick and easy. -// It is *not* authoritative about what constitutes a good test. After using the -// script, be sure to review and refine the generated checks. For example, -// CHECK lines should be minimized and named to reflect the test’s intent. -// For comprehensive guidelines, see: -// * https://mlir.llvm.org/getting_started/TestingGuide/ - // CHECK-LABEL: dxsa.dcl_global_flags // CHECK: dxsa.dcl_constant_buffer , diff --git a/mlir/test/Target/DXSA/hlsl/ds1.test b/mlir/test/Target/DXSA/hlsl/ds1.test index ddca404c8ef7..ada5176147d3 100644 --- a/mlir/test/Target/DXSA/hlsl/ds1.test +++ b/mlir/test/Target/DXSA/hlsl/ds1.test @@ -1,13 +1,6 @@ -// RUN: mlir-translate --import-dxsa-bin %S/inputs/ds1.bin | FileCheck %s +// RUN: mlir-translate --import-dxsa-bin %S/inputs/ds1.shex | FileCheck %s // NOTE: Assertions have been autogenerated by utils/generate-test-checks.py -// This script is intended to make adding checks to a test case quick and easy. -// It is *not* authoritative about what constitutes a good test. After using the -// script, be sure to review and refine the generated checks. For example, -// CHECK lines should be minimized and named to reflect the test’s intent. -// For comprehensive guidelines, see: -// * https://mlir.llvm.org/getting_started/TestingGuide/ - // CHECK-LABEL: dxsa.dcl_input_control_point_count 16 // CHECK: dxsa.dcl_tessellator_domain domain_quad diff --git a/mlir/test/Target/DXSA/hlsl/empty.test b/mlir/test/Target/DXSA/hlsl/empty.test index a1e6d3887751..3a2987054899 100644 --- a/mlir/test/Target/DXSA/hlsl/empty.test +++ b/mlir/test/Target/DXSA/hlsl/empty.test @@ -1,13 +1,6 @@ -// RUN: mlir-translate --import-dxsa-bin %S/inputs/empty.bin | FileCheck %s +// RUN: mlir-translate --import-dxsa-bin %S/inputs/empty.shex | FileCheck %s // NOTE: Assertions have been autogenerated by utils/generate-test-checks.py -// This script is intended to make adding checks to a test case quick and easy. -// It is *not* authoritative about what constitutes a good test. After using the -// script, be sure to review and refine the generated checks. For example, -// CHECK lines should be minimized and named to reflect the test’s intent. -// For comprehensive guidelines, see: -// * https://mlir.llvm.org/getting_started/TestingGuide/ - // CHECK-LABEL: dxsa.dcl_global_flags // CHECK: dxsa.instruction "ret" diff --git a/mlir/test/Target/DXSA/hlsl/eval.test b/mlir/test/Target/DXSA/hlsl/eval.test index 1f738fd78a6e..60ea9de77e92 100644 --- a/mlir/test/Target/DXSA/hlsl/eval.test +++ b/mlir/test/Target/DXSA/hlsl/eval.test @@ -1,13 +1,6 @@ -// RUN: mlir-translate --import-dxsa-bin %S/inputs/eval.bin | FileCheck %s +// RUN: mlir-translate --import-dxsa-bin %S/inputs/eval.shex | FileCheck %s // NOTE: Assertions have been autogenerated by utils/generate-test-checks.py -// This script is intended to make adding checks to a test case quick and easy. -// It is *not* authoritative about what constitutes a good test. After using the -// script, be sure to review and refine the generated checks. For example, -// CHECK lines should be minimized and named to reflect the test’s intent. -// For comprehensive guidelines, see: -// * https://mlir.llvm.org/getting_started/TestingGuide/ - // CHECK-LABEL: dxsa.dcl_global_flags // CHECK: dxsa.dcl_input_ps linear v<0> diff --git a/mlir/test/Target/DXSA/hlsl/f32f16.test b/mlir/test/Target/DXSA/hlsl/f32f16.test index 3b191bca454b..9b2f52c137d5 100644 --- a/mlir/test/Target/DXSA/hlsl/f32f16.test +++ b/mlir/test/Target/DXSA/hlsl/f32f16.test @@ -1,13 +1,6 @@ -// RUN: mlir-translate --import-dxsa-bin %S/inputs/f32f16.bin | FileCheck %s +// RUN: mlir-translate --import-dxsa-bin %S/inputs/f32f16.shex | FileCheck %s // NOTE: Assertions have been autogenerated by utils/generate-test-checks.py -// This script is intended to make adding checks to a test case quick and easy. -// It is *not* authoritative about what constitutes a good test. After using the -// script, be sure to review and refine the generated checks. For example, -// CHECK lines should be minimized and named to reflect the test’s intent. -// For comprehensive guidelines, see: -// * https://mlir.llvm.org/getting_started/TestingGuide/ - // CHECK-LABEL: dxsa.dcl_global_flags // CHECK: dxsa.dcl_input_ps linear v<0, > diff --git a/mlir/test/Target/DXSA/hlsl/gather.test b/mlir/test/Target/DXSA/hlsl/gather.test index afe46ee6ec7f..a7bd7ac5a15f 100644 --- a/mlir/test/Target/DXSA/hlsl/gather.test +++ b/mlir/test/Target/DXSA/hlsl/gather.test @@ -1,13 +1,6 @@ -// RUN: mlir-translate --import-dxsa-bin %S/inputs/gather.bin | FileCheck %s +// RUN: mlir-translate --import-dxsa-bin %S/inputs/gather.shex | FileCheck %s // NOTE: Assertions have been autogenerated by utils/generate-test-checks.py -// This script is intended to make adding checks to a test case quick and easy. -// It is *not* authoritative about what constitutes a good test. After using the -// script, be sure to review and refine the generated checks. For example, -// CHECK lines should be minimized and named to reflect the test’s intent. -// For comprehensive guidelines, see: -// * https://mlir.llvm.org/getting_started/TestingGuide/ - // CHECK-LABEL: dxsa.dcl_global_flags // CHECK: dxsa.dcl_sampler diff --git a/mlir/test/Target/DXSA/hlsl/gather_cmp.test b/mlir/test/Target/DXSA/hlsl/gather_cmp.test index ead4e4302d29..6f335842becf 100644 --- a/mlir/test/Target/DXSA/hlsl/gather_cmp.test +++ b/mlir/test/Target/DXSA/hlsl/gather_cmp.test @@ -1,13 +1,6 @@ -// RUN: mlir-translate --import-dxsa-bin %S/inputs/gather_cmp.bin | FileCheck %s +// RUN: mlir-translate --import-dxsa-bin %S/inputs/gather_cmp.shex | FileCheck %s // NOTE: Assertions have been autogenerated by utils/generate-test-checks.py -// This script is intended to make adding checks to a test case quick and easy. -// It is *not* authoritative about what constitutes a good test. After using the -// script, be sure to review and refine the generated checks. For example, -// CHECK lines should be minimized and named to reflect the test’s intent. -// For comprehensive guidelines, see: -// * https://mlir.llvm.org/getting_started/TestingGuide/ - // CHECK-LABEL: dxsa.dcl_global_flags // CHECK: dxsa.dcl_sampler diff --git a/mlir/test/Target/DXSA/hlsl/gather_po.test b/mlir/test/Target/DXSA/hlsl/gather_po.test index a8efd9b6296e..f4e283497849 100644 --- a/mlir/test/Target/DXSA/hlsl/gather_po.test +++ b/mlir/test/Target/DXSA/hlsl/gather_po.test @@ -1,13 +1,6 @@ -// RUN: mlir-translate --import-dxsa-bin %S/inputs/gather_po.bin | FileCheck %s +// RUN: mlir-translate --import-dxsa-bin %S/inputs/gather_po.shex | FileCheck %s // NOTE: Assertions have been autogenerated by utils/generate-test-checks.py -// This script is intended to make adding checks to a test case quick and easy. -// It is *not* authoritative about what constitutes a good test. After using the -// script, be sure to review and refine the generated checks. For example, -// CHECK lines should be minimized and named to reflect the test’s intent. -// For comprehensive guidelines, see: -// * https://mlir.llvm.org/getting_started/TestingGuide/ - // CHECK-LABEL: dxsa.dcl_global_flags // CHECK: dxsa.dcl_sampler diff --git a/mlir/test/Target/DXSA/hlsl/gather_po_cmp.test b/mlir/test/Target/DXSA/hlsl/gather_po_cmp.test index cf8f8ebaba4c..8b78501fe31c 100644 --- a/mlir/test/Target/DXSA/hlsl/gather_po_cmp.test +++ b/mlir/test/Target/DXSA/hlsl/gather_po_cmp.test @@ -1,13 +1,6 @@ -// RUN: mlir-translate --import-dxsa-bin %S/inputs/gather_po_cmp.bin | FileCheck %s +// RUN: mlir-translate --import-dxsa-bin %S/inputs/gather_po_cmp.shex | FileCheck %s // NOTE: Assertions have been autogenerated by utils/generate-test-checks.py -// This script is intended to make adding checks to a test case quick and easy. -// It is *not* authoritative about what constitutes a good test. After using the -// script, be sure to review and refine the generated checks. For example, -// CHECK lines should be minimized and named to reflect the test’s intent. -// For comprehensive guidelines, see: -// * https://mlir.llvm.org/getting_started/TestingGuide/ - // CHECK-LABEL: dxsa.dcl_global_flags // CHECK: dxsa.dcl_sampler diff --git a/mlir/test/Target/DXSA/hlsl/getdim.test b/mlir/test/Target/DXSA/hlsl/getdim.test index 94eb6adff1b3..49597c3d3436 100644 --- a/mlir/test/Target/DXSA/hlsl/getdim.test +++ b/mlir/test/Target/DXSA/hlsl/getdim.test @@ -1,13 +1,6 @@ -// RUN: mlir-translate --import-dxsa-bin %S/inputs/getdim.bin | FileCheck %s +// RUN: mlir-translate --import-dxsa-bin %S/inputs/getdim.shex | FileCheck %s // NOTE: Assertions have been autogenerated by utils/generate-test-checks.py -// This script is intended to make adding checks to a test case quick and easy. -// It is *not* authoritative about what constitutes a good test. After using the -// script, be sure to review and refine the generated checks. For example, -// CHECK lines should be minimized and named to reflect the test’s intent. -// For comprehensive guidelines, see: -// * https://mlir.llvm.org/getting_started/TestingGuide/ - // CHECK-LABEL: dxsa.dcl_global_flags // CHECK: dxsa.dcl_resource , , diff --git a/mlir/test/Target/DXSA/hlsl/gs1.test b/mlir/test/Target/DXSA/hlsl/gs1.test index df216b81912d..037318da35ef 100644 --- a/mlir/test/Target/DXSA/hlsl/gs1.test +++ b/mlir/test/Target/DXSA/hlsl/gs1.test @@ -1,13 +1,6 @@ -// RUN: mlir-translate --import-dxsa-bin %S/inputs/gs1.bin | FileCheck %s +// RUN: mlir-translate --import-dxsa-bin %S/inputs/gs1.shex | FileCheck %s // NOTE: Assertions have been autogenerated by utils/generate-test-checks.py -// This script is intended to make adding checks to a test case quick and easy. -// It is *not* authoritative about what constitutes a good test. After using the -// script, be sure to review and refine the generated checks. For example, -// CHECK lines should be minimized and named to reflect the test’s intent. -// For comprehensive guidelines, see: -// * https://mlir.llvm.org/getting_started/TestingGuide/ - // CHECK-LABEL: dxsa.dcl_global_flags // CHECK: dxsa.dcl_input v<[6, 0]> diff --git a/mlir/test/Target/DXSA/hlsl/gs2.test b/mlir/test/Target/DXSA/hlsl/gs2.test index 61778bd3fe1b..6f434cbb7ba8 100644 --- a/mlir/test/Target/DXSA/hlsl/gs2.test +++ b/mlir/test/Target/DXSA/hlsl/gs2.test @@ -1,13 +1,6 @@ -// RUN: mlir-translate --import-dxsa-bin %S/inputs/gs2.bin | FileCheck %s +// RUN: mlir-translate --import-dxsa-bin %S/inputs/gs2.shex | FileCheck %s // NOTE: Assertions have been autogenerated by utils/generate-test-checks.py -// This script is intended to make adding checks to a test case quick and easy. -// It is *not* authoritative about what constitutes a good test. After using the -// script, be sure to review and refine the generated checks. For example, -// CHECK lines should be minimized and named to reflect the test’s intent. -// For comprehensive guidelines, see: -// * https://mlir.llvm.org/getting_started/TestingGuide/ - // CHECK-LABEL: dxsa.dcl_global_flags // CHECK: dxsa.dcl_constant_buffer , diff --git a/mlir/test/Target/DXSA/hlsl/half_rcp.test b/mlir/test/Target/DXSA/hlsl/half_rcp.test index 2fa1e2e8acc5..1fb35a5b9670 100644 --- a/mlir/test/Target/DXSA/hlsl/half_rcp.test +++ b/mlir/test/Target/DXSA/hlsl/half_rcp.test @@ -1,13 +1,6 @@ -// RUN: mlir-translate --import-dxsa-bin %S/inputs/half_rcp.bin | FileCheck %s +// RUN: mlir-translate --import-dxsa-bin %S/inputs/half_rcp.shex | FileCheck %s // NOTE: Assertions have been autogenerated by utils/generate-test-checks.py -// This script is intended to make adding checks to a test case quick and easy. -// It is *not* authoritative about what constitutes a good test. After using the -// script, be sure to review and refine the generated checks. For example, -// CHECK lines should be minimized and named to reflect the test’s intent. -// For comprehensive guidelines, see: -// * https://mlir.llvm.org/getting_started/TestingGuide/ - // CHECK-LABEL: dxsa.dcl_global_flags // CHECK: dxsa.dcl_output o<0, > diff --git a/mlir/test/Target/DXSA/hlsl/hs1.test b/mlir/test/Target/DXSA/hlsl/hs1.test index 16f9ce4146cf..55bc4c04db4c 100644 --- a/mlir/test/Target/DXSA/hlsl/hs1.test +++ b/mlir/test/Target/DXSA/hlsl/hs1.test @@ -1,13 +1,6 @@ -// RUN: mlir-translate --import-dxsa-bin %S/inputs/hs1.bin | FileCheck %s +// RUN: mlir-translate --import-dxsa-bin %S/inputs/hs1.shex | FileCheck %s // NOTE: Assertions have been autogenerated by utils/generate-test-checks.py -// This script is intended to make adding checks to a test case quick and easy. -// It is *not* authoritative about what constitutes a good test. After using the -// script, be sure to review and refine the generated checks. For example, -// CHECK lines should be minimized and named to reflect the test’s intent. -// For comprehensive guidelines, see: -// * https://mlir.llvm.org/getting_started/TestingGuide/ - // CHECK-LABEL: dxsa.instruction "hs_decls" // CHECK: dxsa.dcl_input_control_point_count 16 diff --git a/mlir/test/Target/DXSA/hlsl/hs2.test b/mlir/test/Target/DXSA/hlsl/hs2.test index 212606437424..3b70fbfb26dc 100644 --- a/mlir/test/Target/DXSA/hlsl/hs2.test +++ b/mlir/test/Target/DXSA/hlsl/hs2.test @@ -1,13 +1,6 @@ -// RUN: mlir-translate --import-dxsa-bin %S/inputs/hs2.bin | FileCheck %s +// RUN: mlir-translate --import-dxsa-bin %S/inputs/hs2.shex | FileCheck %s // NOTE: Assertions have been autogenerated by utils/generate-test-checks.py -// This script is intended to make adding checks to a test case quick and easy. -// It is *not* authoritative about what constitutes a good test. After using the -// script, be sure to review and refine the generated checks. For example, -// CHECK lines should be minimized and named to reflect the test’s intent. -// For comprehensive guidelines, see: -// * https://mlir.llvm.org/getting_started/TestingGuide/ - // CHECK-LABEL: dxsa.instruction "hs_decls" // CHECK: dxsa.dcl_input_control_point_count 32 diff --git a/mlir/test/Target/DXSA/hlsl/icb1.test b/mlir/test/Target/DXSA/hlsl/icb1.test index 151b2500c7f0..72bd40ba022b 100644 --- a/mlir/test/Target/DXSA/hlsl/icb1.test +++ b/mlir/test/Target/DXSA/hlsl/icb1.test @@ -1,13 +1,6 @@ -// RUN: mlir-translate --import-dxsa-bin %S/inputs/icb1.bin | FileCheck %s +// RUN: mlir-translate --import-dxsa-bin %S/inputs/icb1.shex | FileCheck %s // NOTE: Assertions have been autogenerated by utils/generate-test-checks.py -// This script is intended to make adding checks to a test case quick and easy. -// It is *not* authoritative about what constitutes a good test. After using the -// script, be sure to review and refine the generated checks. For example, -// CHECK lines should be minimized and named to reflect the test’s intent. -// For comprehensive guidelines, see: -// * https://mlir.llvm.org/getting_started/TestingGuide/ - // CHECK-LABEL: dxsa.dcl_global_flags // CHECK: dxsa.unknown diff --git a/mlir/test/Target/DXSA/hlsl/if1.test b/mlir/test/Target/DXSA/hlsl/if1.test index c77a4d27551f..63b28be307c7 100644 --- a/mlir/test/Target/DXSA/hlsl/if1.test +++ b/mlir/test/Target/DXSA/hlsl/if1.test @@ -1,13 +1,6 @@ -// RUN: mlir-translate --import-dxsa-bin %S/inputs/if1.bin | FileCheck %s +// RUN: mlir-translate --import-dxsa-bin %S/inputs/if1.shex | FileCheck %s // NOTE: Assertions have been autogenerated by utils/generate-test-checks.py -// This script is intended to make adding checks to a test case quick and easy. -// It is *not* authoritative about what constitutes a good test. After using the -// script, be sure to review and refine the generated checks. For example, -// CHECK lines should be minimized and named to reflect the test’s intent. -// For comprehensive guidelines, see: -// * https://mlir.llvm.org/getting_started/TestingGuide/ - // CHECK-LABEL: dxsa.dcl_global_flags // CHECK: dxsa.dcl_input_ps linear v<0, > diff --git a/mlir/test/Target/DXSA/hlsl/if2.test b/mlir/test/Target/DXSA/hlsl/if2.test index f95c7240db04..435b9fc74987 100644 --- a/mlir/test/Target/DXSA/hlsl/if2.test +++ b/mlir/test/Target/DXSA/hlsl/if2.test @@ -1,13 +1,6 @@ -// RUN: mlir-translate --import-dxsa-bin %S/inputs/if2.bin | FileCheck %s +// RUN: mlir-translate --import-dxsa-bin %S/inputs/if2.shex | FileCheck %s // NOTE: Assertions have been autogenerated by utils/generate-test-checks.py -// This script is intended to make adding checks to a test case quick and easy. -// It is *not* authoritative about what constitutes a good test. After using the -// script, be sure to review and refine the generated checks. For example, -// CHECK lines should be minimized and named to reflect the test’s intent. -// For comprehensive guidelines, see: -// * https://mlir.llvm.org/getting_started/TestingGuide/ - // CHECK-LABEL: dxsa.dcl_global_flags // CHECK: dxsa.dcl_input_ps linear v<0, > diff --git a/mlir/test/Target/DXSA/hlsl/if3.test b/mlir/test/Target/DXSA/hlsl/if3.test index 79ffd4407de9..dc6e6f1343e4 100644 --- a/mlir/test/Target/DXSA/hlsl/if3.test +++ b/mlir/test/Target/DXSA/hlsl/if3.test @@ -1,13 +1,6 @@ -// RUN: mlir-translate --import-dxsa-bin %S/inputs/if3.bin | FileCheck %s +// RUN: mlir-translate --import-dxsa-bin %S/inputs/if3.shex | FileCheck %s // NOTE: Assertions have been autogenerated by utils/generate-test-checks.py -// This script is intended to make adding checks to a test case quick and easy. -// It is *not* authoritative about what constitutes a good test. After using the -// script, be sure to review and refine the generated checks. For example, -// CHECK lines should be minimized and named to reflect the test’s intent. -// For comprehensive guidelines, see: -// * https://mlir.llvm.org/getting_started/TestingGuide/ - // CHECK-LABEL: dxsa.dcl_global_flags // CHECK: dxsa.dcl_input_ps linear v<0, > diff --git a/mlir/test/Target/DXSA/hlsl/if4.test b/mlir/test/Target/DXSA/hlsl/if4.test index 1d7c76c27b57..93550ab4435e 100644 --- a/mlir/test/Target/DXSA/hlsl/if4.test +++ b/mlir/test/Target/DXSA/hlsl/if4.test @@ -1,13 +1,6 @@ -// RUN: mlir-translate --import-dxsa-bin %S/inputs/if4.bin | FileCheck %s +// RUN: mlir-translate --import-dxsa-bin %S/inputs/if4.shex | FileCheck %s // NOTE: Assertions have been autogenerated by utils/generate-test-checks.py -// This script is intended to make adding checks to a test case quick and easy. -// It is *not* authoritative about what constitutes a good test. After using the -// script, be sure to review and refine the generated checks. For example, -// CHECK lines should be minimized and named to reflect the test’s intent. -// For comprehensive guidelines, see: -// * https://mlir.llvm.org/getting_started/TestingGuide/ - // CHECK-LABEL: dxsa.dcl_global_flags // CHECK: dxsa.dcl_input_ps linear v<0, > diff --git a/mlir/test/Target/DXSA/hlsl/if5.test b/mlir/test/Target/DXSA/hlsl/if5.test index c033e9faee14..ae114b247d6e 100644 --- a/mlir/test/Target/DXSA/hlsl/if5.test +++ b/mlir/test/Target/DXSA/hlsl/if5.test @@ -1,13 +1,6 @@ -// RUN: mlir-translate --import-dxsa-bin %S/inputs/if5.bin | FileCheck %s +// RUN: mlir-translate --import-dxsa-bin %S/inputs/if5.shex | FileCheck %s // NOTE: Assertions have been autogenerated by utils/generate-test-checks.py -// This script is intended to make adding checks to a test case quick and easy. -// It is *not* authoritative about what constitutes a good test. After using the -// script, be sure to review and refine the generated checks. For example, -// CHECK lines should be minimized and named to reflect the test’s intent. -// For comprehensive guidelines, see: -// * https://mlir.llvm.org/getting_started/TestingGuide/ - // CHECK-LABEL: dxsa.dcl_global_flags // CHECK: dxsa.dcl_input_ps linear v<0, > diff --git a/mlir/test/Target/DXSA/hlsl/indexableinput1.test b/mlir/test/Target/DXSA/hlsl/indexableinput1.test index 91e226c53fc8..fbbcaeb84c7d 100644 --- a/mlir/test/Target/DXSA/hlsl/indexableinput1.test +++ b/mlir/test/Target/DXSA/hlsl/indexableinput1.test @@ -1,13 +1,6 @@ -// RUN: mlir-translate --import-dxsa-bin %S/inputs/indexableinput1.bin | FileCheck %s +// RUN: mlir-translate --import-dxsa-bin %S/inputs/indexableinput1.shex | FileCheck %s // NOTE: Assertions have been autogenerated by utils/generate-test-checks.py -// This script is intended to make adding checks to a test case quick and easy. -// It is *not* authoritative about what constitutes a good test. After using the -// script, be sure to review and refine the generated checks. For example, -// CHECK lines should be minimized and named to reflect the test’s intent. -// For comprehensive guidelines, see: -// * https://mlir.llvm.org/getting_started/TestingGuide/ - // CHECK-LABEL: dxsa.dcl_global_flags // CHECK: dxsa.dcl_input_ps linear v<0, > diff --git a/mlir/test/Target/DXSA/hlsl/indexableinput2.test b/mlir/test/Target/DXSA/hlsl/indexableinput2.test index f8bf3ab71e25..f827389ac0ce 100644 --- a/mlir/test/Target/DXSA/hlsl/indexableinput2.test +++ b/mlir/test/Target/DXSA/hlsl/indexableinput2.test @@ -1,13 +1,6 @@ -// RUN: mlir-translate --import-dxsa-bin %S/inputs/indexableinput2.bin | FileCheck %s +// RUN: mlir-translate --import-dxsa-bin %S/inputs/indexableinput2.shex | FileCheck %s // NOTE: Assertions have been autogenerated by utils/generate-test-checks.py -// This script is intended to make adding checks to a test case quick and easy. -// It is *not* authoritative about what constitutes a good test. After using the -// script, be sure to review and refine the generated checks. For example, -// CHECK lines should be minimized and named to reflect the test’s intent. -// For comprehensive guidelines, see: -// * https://mlir.llvm.org/getting_started/TestingGuide/ - // CHECK-LABEL: dxsa.dcl_global_flags // CHECK: dxsa.dcl_input_ps linear v<0, > diff --git a/mlir/test/Target/DXSA/hlsl/indexableoutput1.test b/mlir/test/Target/DXSA/hlsl/indexableoutput1.test index 6964e9de76fe..bb3e1ebc1f7d 100644 --- a/mlir/test/Target/DXSA/hlsl/indexableoutput1.test +++ b/mlir/test/Target/DXSA/hlsl/indexableoutput1.test @@ -1,13 +1,6 @@ -// RUN: mlir-translate --import-dxsa-bin %S/inputs/indexableoutput1.bin | FileCheck %s +// RUN: mlir-translate --import-dxsa-bin %S/inputs/indexableoutput1.shex | FileCheck %s // NOTE: Assertions have been autogenerated by utils/generate-test-checks.py -// This script is intended to make adding checks to a test case quick and easy. -// It is *not* authoritative about what constitutes a good test. After using the -// script, be sure to review and refine the generated checks. For example, -// CHECK lines should be minimized and named to reflect the test’s intent. -// For comprehensive guidelines, see: -// * https://mlir.llvm.org/getting_started/TestingGuide/ - // CHECK-LABEL: dxsa.dcl_global_flags // CHECK: dxsa.dcl_input v<0, > diff --git a/mlir/test/Target/DXSA/hlsl/indexabletemp1.test b/mlir/test/Target/DXSA/hlsl/indexabletemp1.test index e8144df2bd43..fad41c18260c 100644 --- a/mlir/test/Target/DXSA/hlsl/indexabletemp1.test +++ b/mlir/test/Target/DXSA/hlsl/indexabletemp1.test @@ -1,13 +1,6 @@ -// RUN: mlir-translate --import-dxsa-bin %S/inputs/indexabletemp1.bin | FileCheck %s +// RUN: mlir-translate --import-dxsa-bin %S/inputs/indexabletemp1.shex | FileCheck %s // NOTE: Assertions have been autogenerated by utils/generate-test-checks.py -// This script is intended to make adding checks to a test case quick and easy. -// It is *not* authoritative about what constitutes a good test. After using the -// script, be sure to review and refine the generated checks. For example, -// CHECK lines should be minimized and named to reflect the test’s intent. -// For comprehensive guidelines, see: -// * https://mlir.llvm.org/getting_started/TestingGuide/ - // CHECK-LABEL: dxsa.dcl_global_flags // CHECK: dxsa.dcl_constant_buffer , diff --git a/mlir/test/Target/DXSA/hlsl/indexabletemp2.test b/mlir/test/Target/DXSA/hlsl/indexabletemp2.test index 4f30151ffe3e..5a51583aa7b3 100644 --- a/mlir/test/Target/DXSA/hlsl/indexabletemp2.test +++ b/mlir/test/Target/DXSA/hlsl/indexabletemp2.test @@ -1,13 +1,6 @@ -// RUN: mlir-translate --import-dxsa-bin %S/inputs/indexabletemp2.bin | FileCheck %s +// RUN: mlir-translate --import-dxsa-bin %S/inputs/indexabletemp2.shex | FileCheck %s // NOTE: Assertions have been autogenerated by utils/generate-test-checks.py -// This script is intended to make adding checks to a test case quick and easy. -// It is *not* authoritative about what constitutes a good test. After using the -// script, be sure to review and refine the generated checks. For example, -// CHECK lines should be minimized and named to reflect the test’s intent. -// For comprehensive guidelines, see: -// * https://mlir.llvm.org/getting_started/TestingGuide/ - // CHECK-LABEL: dxsa.dcl_global_flags // CHECK: dxsa.dcl_constant_buffer , diff --git a/mlir/test/Target/DXSA/hlsl/indexabletemp3.test b/mlir/test/Target/DXSA/hlsl/indexabletemp3.test index 75e350240aaf..c17bec8b6b64 100644 --- a/mlir/test/Target/DXSA/hlsl/indexabletemp3.test +++ b/mlir/test/Target/DXSA/hlsl/indexabletemp3.test @@ -1,13 +1,6 @@ -// RUN: mlir-translate --import-dxsa-bin %S/inputs/indexabletemp3.bin | FileCheck %s +// RUN: mlir-translate --import-dxsa-bin %S/inputs/indexabletemp3.shex | FileCheck %s // NOTE: Assertions have been autogenerated by utils/generate-test-checks.py -// This script is intended to make adding checks to a test case quick and easy. -// It is *not* authoritative about what constitutes a good test. After using the -// script, be sure to review and refine the generated checks. For example, -// CHECK lines should be minimized and named to reflect the test’s intent. -// For comprehensive guidelines, see: -// * https://mlir.llvm.org/getting_started/TestingGuide/ - // CHECK-LABEL: dxsa.dcl_global_flags // CHECK: dxsa.dcl_constant_buffer , diff --git a/mlir/test/Target/DXSA/hlsl/indexabletemp5.test b/mlir/test/Target/DXSA/hlsl/indexabletemp5.test index fd9bed1d8b5e..43737b806c87 100644 --- a/mlir/test/Target/DXSA/hlsl/indexabletemp5.test +++ b/mlir/test/Target/DXSA/hlsl/indexabletemp5.test @@ -1,13 +1,6 @@ -// RUN: mlir-translate --import-dxsa-bin %S/inputs/indexabletemp5.bin | FileCheck %s +// RUN: mlir-translate --import-dxsa-bin %S/inputs/indexabletemp5.shex | FileCheck %s // NOTE: Assertions have been autogenerated by utils/generate-test-checks.py -// This script is intended to make adding checks to a test case quick and easy. -// It is *not* authoritative about what constitutes a good test. After using the -// script, be sure to review and refine the generated checks. For example, -// CHECK lines should be minimized and named to reflect the test’s intent. -// For comprehensive guidelines, see: -// * https://mlir.llvm.org/getting_started/TestingGuide/ - // CHECK-LABEL: dxsa.dcl_global_flags // CHECK: dxsa.dcl_constant_buffer , diff --git a/mlir/test/Target/DXSA/hlsl/input1.test b/mlir/test/Target/DXSA/hlsl/input1.test index 5b4504c9d254..f5431776dfc1 100644 --- a/mlir/test/Target/DXSA/hlsl/input1.test +++ b/mlir/test/Target/DXSA/hlsl/input1.test @@ -1,13 +1,6 @@ -// RUN: mlir-translate --import-dxsa-bin %S/inputs/input1.bin | FileCheck %s +// RUN: mlir-translate --import-dxsa-bin %S/inputs/input1.shex | FileCheck %s // NOTE: Assertions have been autogenerated by utils/generate-test-checks.py -// This script is intended to make adding checks to a test case quick and easy. -// It is *not* authoritative about what constitutes a good test. After using the -// script, be sure to review and refine the generated checks. For example, -// CHECK lines should be minimized and named to reflect the test’s intent. -// For comprehensive guidelines, see: -// * https://mlir.llvm.org/getting_started/TestingGuide/ - // CHECK-LABEL: dxsa.dcl_global_flags // CHECK: dxsa.dcl_input_ps linear v<0> diff --git a/mlir/test/Target/DXSA/hlsl/input2.test b/mlir/test/Target/DXSA/hlsl/input2.test index e1eb1de138d1..53d390f97730 100644 --- a/mlir/test/Target/DXSA/hlsl/input2.test +++ b/mlir/test/Target/DXSA/hlsl/input2.test @@ -1,13 +1,6 @@ -// RUN: mlir-translate --import-dxsa-bin %S/inputs/input2.bin | FileCheck %s +// RUN: mlir-translate --import-dxsa-bin %S/inputs/input2.shex | FileCheck %s // NOTE: Assertions have been autogenerated by utils/generate-test-checks.py -// This script is intended to make adding checks to a test case quick and easy. -// It is *not* authoritative about what constitutes a good test. After using the -// script, be sure to review and refine the generated checks. For example, -// CHECK lines should be minimized and named to reflect the test’s intent. -// For comprehensive guidelines, see: -// * https://mlir.llvm.org/getting_started/TestingGuide/ - // CHECK-LABEL: dxsa.dcl_global_flags // CHECK: dxsa.dcl_input_ps linear v<0> diff --git a/mlir/test/Target/DXSA/hlsl/input3.test b/mlir/test/Target/DXSA/hlsl/input3.test index ec87ea7e7d4b..8fd2e117ad57 100644 --- a/mlir/test/Target/DXSA/hlsl/input3.test +++ b/mlir/test/Target/DXSA/hlsl/input3.test @@ -1,13 +1,6 @@ -// RUN: mlir-translate --import-dxsa-bin %S/inputs/input3.bin | FileCheck %s +// RUN: mlir-translate --import-dxsa-bin %S/inputs/input3.shex | FileCheck %s // NOTE: Assertions have been autogenerated by utils/generate-test-checks.py -// This script is intended to make adding checks to a test case quick and easy. -// It is *not* authoritative about what constitutes a good test. After using the -// script, be sure to review and refine the generated checks. For example, -// CHECK lines should be minimized and named to reflect the test’s intent. -// For comprehensive guidelines, see: -// * https://mlir.llvm.org/getting_started/TestingGuide/ - // CHECK-LABEL: dxsa.dcl_global_flags // CHECK: dxsa.dcl_input v<0> diff --git a/mlir/test/Target/DXSA/hlsl/inputs/abs1.bin b/mlir/test/Target/DXSA/hlsl/inputs/abs1.shex similarity index 100% rename from mlir/test/Target/DXSA/hlsl/inputs/abs1.bin rename to mlir/test/Target/DXSA/hlsl/inputs/abs1.shex diff --git a/mlir/test/Target/DXSA/hlsl/inputs/abs2.bin b/mlir/test/Target/DXSA/hlsl/inputs/abs2.shex similarity index 100% rename from mlir/test/Target/DXSA/hlsl/inputs/abs2.bin rename to mlir/test/Target/DXSA/hlsl/inputs/abs2.shex diff --git a/mlir/test/Target/DXSA/hlsl/inputs/atomics.bin b/mlir/test/Target/DXSA/hlsl/inputs/atomics.shex similarity index 100% rename from mlir/test/Target/DXSA/hlsl/inputs/atomics.bin rename to mlir/test/Target/DXSA/hlsl/inputs/atomics.shex diff --git a/mlir/test/Target/DXSA/hlsl/inputs/bad_ftoi.bin b/mlir/test/Target/DXSA/hlsl/inputs/bad_ftoi.shex similarity index 100% rename from mlir/test/Target/DXSA/hlsl/inputs/bad_ftoi.bin rename to mlir/test/Target/DXSA/hlsl/inputs/bad_ftoi.shex diff --git a/mlir/test/Target/DXSA/hlsl/inputs/binary1.bin b/mlir/test/Target/DXSA/hlsl/inputs/binary1.shex similarity index 100% rename from mlir/test/Target/DXSA/hlsl/inputs/binary1.bin rename to mlir/test/Target/DXSA/hlsl/inputs/binary1.shex diff --git a/mlir/test/Target/DXSA/hlsl/inputs/bool1.bin b/mlir/test/Target/DXSA/hlsl/inputs/bool1.shex similarity index 100% rename from mlir/test/Target/DXSA/hlsl/inputs/bool1.bin rename to mlir/test/Target/DXSA/hlsl/inputs/bool1.shex diff --git a/mlir/test/Target/DXSA/hlsl/inputs/bool2.bin b/mlir/test/Target/DXSA/hlsl/inputs/bool2.shex similarity index 100% rename from mlir/test/Target/DXSA/hlsl/inputs/bool2.bin rename to mlir/test/Target/DXSA/hlsl/inputs/bool2.shex diff --git a/mlir/test/Target/DXSA/hlsl/inputs/bufinfo.bin b/mlir/test/Target/DXSA/hlsl/inputs/bufinfo.shex similarity index 100% rename from mlir/test/Target/DXSA/hlsl/inputs/bufinfo.bin rename to mlir/test/Target/DXSA/hlsl/inputs/bufinfo.shex diff --git a/mlir/test/Target/DXSA/hlsl/inputs/calc_lod.bin b/mlir/test/Target/DXSA/hlsl/inputs/calc_lod.shex similarity index 100% rename from mlir/test/Target/DXSA/hlsl/inputs/calc_lod.bin rename to mlir/test/Target/DXSA/hlsl/inputs/calc_lod.shex diff --git a/mlir/test/Target/DXSA/hlsl/inputs/call1.bin b/mlir/test/Target/DXSA/hlsl/inputs/call1.shex similarity index 100% rename from mlir/test/Target/DXSA/hlsl/inputs/call1.bin rename to mlir/test/Target/DXSA/hlsl/inputs/call1.shex diff --git a/mlir/test/Target/DXSA/hlsl/inputs/call3.bin b/mlir/test/Target/DXSA/hlsl/inputs/call3.shex similarity index 100% rename from mlir/test/Target/DXSA/hlsl/inputs/call3.bin rename to mlir/test/Target/DXSA/hlsl/inputs/call3.shex diff --git a/mlir/test/Target/DXSA/hlsl/inputs/cast1.bin b/mlir/test/Target/DXSA/hlsl/inputs/cast1.shex similarity index 100% rename from mlir/test/Target/DXSA/hlsl/inputs/cast1.bin rename to mlir/test/Target/DXSA/hlsl/inputs/cast1.shex diff --git a/mlir/test/Target/DXSA/hlsl/inputs/cast2.bin b/mlir/test/Target/DXSA/hlsl/inputs/cast2.shex similarity index 100% rename from mlir/test/Target/DXSA/hlsl/inputs/cast2.bin rename to mlir/test/Target/DXSA/hlsl/inputs/cast2.shex diff --git a/mlir/test/Target/DXSA/hlsl/inputs/cast3.bin b/mlir/test/Target/DXSA/hlsl/inputs/cast3.shex similarity index 100% rename from mlir/test/Target/DXSA/hlsl/inputs/cast3.bin rename to mlir/test/Target/DXSA/hlsl/inputs/cast3.shex diff --git a/mlir/test/Target/DXSA/hlsl/inputs/cast4.bin b/mlir/test/Target/DXSA/hlsl/inputs/cast4.shex similarity index 100% rename from mlir/test/Target/DXSA/hlsl/inputs/cast4.bin rename to mlir/test/Target/DXSA/hlsl/inputs/cast4.shex diff --git a/mlir/test/Target/DXSA/hlsl/inputs/cast5.bin b/mlir/test/Target/DXSA/hlsl/inputs/cast5.shex similarity index 100% rename from mlir/test/Target/DXSA/hlsl/inputs/cast5.bin rename to mlir/test/Target/DXSA/hlsl/inputs/cast5.shex diff --git a/mlir/test/Target/DXSA/hlsl/inputs/cast6.bin b/mlir/test/Target/DXSA/hlsl/inputs/cast6.shex similarity index 100% rename from mlir/test/Target/DXSA/hlsl/inputs/cast6.bin rename to mlir/test/Target/DXSA/hlsl/inputs/cast6.shex diff --git a/mlir/test/Target/DXSA/hlsl/inputs/cbuffer1.50.bin b/mlir/test/Target/DXSA/hlsl/inputs/cbuffer1.50.shex similarity index 100% rename from mlir/test/Target/DXSA/hlsl/inputs/cbuffer1.50.bin rename to mlir/test/Target/DXSA/hlsl/inputs/cbuffer1.50.shex diff --git a/mlir/test/Target/DXSA/hlsl/inputs/cbuffer1.51.bin b/mlir/test/Target/DXSA/hlsl/inputs/cbuffer1.51.shex similarity index 100% rename from mlir/test/Target/DXSA/hlsl/inputs/cbuffer1.51.bin rename to mlir/test/Target/DXSA/hlsl/inputs/cbuffer1.51.shex diff --git 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to mlir/test/Target/DXSA/hlsl/inputs/rcp1.shex diff --git a/mlir/test/Target/DXSA/hlsl/inputs/redundantinput1.bin b/mlir/test/Target/DXSA/hlsl/inputs/redundantinput1.shex similarity index 100% rename from mlir/test/Target/DXSA/hlsl/inputs/redundantinput1.bin rename to mlir/test/Target/DXSA/hlsl/inputs/redundantinput1.shex diff --git a/mlir/test/Target/DXSA/hlsl/inputs/sample1.bin b/mlir/test/Target/DXSA/hlsl/inputs/sample1.shex similarity index 100% rename from mlir/test/Target/DXSA/hlsl/inputs/sample1.bin rename to mlir/test/Target/DXSA/hlsl/inputs/sample1.shex diff --git a/mlir/test/Target/DXSA/hlsl/inputs/sample2.bin b/mlir/test/Target/DXSA/hlsl/inputs/sample2.shex similarity index 100% rename from mlir/test/Target/DXSA/hlsl/inputs/sample2.bin rename to mlir/test/Target/DXSA/hlsl/inputs/sample2.shex diff --git a/mlir/test/Target/DXSA/hlsl/inputs/sample3.bin b/mlir/test/Target/DXSA/hlsl/inputs/sample3.shex similarity index 100% rename from mlir/test/Target/DXSA/hlsl/inputs/sample3.bin rename to mlir/test/Target/DXSA/hlsl/inputs/sample3.shex diff --git a/mlir/test/Target/DXSA/hlsl/inputs/sample_b1.bin b/mlir/test/Target/DXSA/hlsl/inputs/sample_b1.shex similarity index 100% rename from mlir/test/Target/DXSA/hlsl/inputs/sample_b1.bin rename to mlir/test/Target/DXSA/hlsl/inputs/sample_b1.shex diff --git a/mlir/test/Target/DXSA/hlsl/inputs/sample_cmp1.bin b/mlir/test/Target/DXSA/hlsl/inputs/sample_cmp1.shex similarity index 100% rename from mlir/test/Target/DXSA/hlsl/inputs/sample_cmp1.bin rename to mlir/test/Target/DXSA/hlsl/inputs/sample_cmp1.shex diff --git a/mlir/test/Target/DXSA/hlsl/inputs/sample_cmp2.bin b/mlir/test/Target/DXSA/hlsl/inputs/sample_cmp2.shex similarity index 100% rename from mlir/test/Target/DXSA/hlsl/inputs/sample_cmp2.bin rename to mlir/test/Target/DXSA/hlsl/inputs/sample_cmp2.shex diff --git a/mlir/test/Target/DXSA/hlsl/inputs/sample_grad1.bin b/mlir/test/Target/DXSA/hlsl/inputs/sample_grad1.shex similarity index 100% rename from mlir/test/Target/DXSA/hlsl/inputs/sample_grad1.bin rename to mlir/test/Target/DXSA/hlsl/inputs/sample_grad1.shex diff --git a/mlir/test/Target/DXSA/hlsl/inputs/sample_l1.bin b/mlir/test/Target/DXSA/hlsl/inputs/sample_l1.shex similarity index 100% rename from mlir/test/Target/DXSA/hlsl/inputs/sample_l1.bin rename to mlir/test/Target/DXSA/hlsl/inputs/sample_l1.shex diff --git a/mlir/test/Target/DXSA/hlsl/inputs/samplecount.bin b/mlir/test/Target/DXSA/hlsl/inputs/samplecount.shex similarity index 100% rename from mlir/test/Target/DXSA/hlsl/inputs/samplecount.bin rename to mlir/test/Target/DXSA/hlsl/inputs/samplecount.shex diff --git a/mlir/test/Target/DXSA/hlsl/inputs/samplepos.bin b/mlir/test/Target/DXSA/hlsl/inputs/samplepos.shex similarity index 100% rename from mlir/test/Target/DXSA/hlsl/inputs/samplepos.bin rename to mlir/test/Target/DXSA/hlsl/inputs/samplepos.shex diff --git a/mlir/test/Target/DXSA/hlsl/inputs/saturate1.bin b/mlir/test/Target/DXSA/hlsl/inputs/saturate1.shex similarity index 100% rename from mlir/test/Target/DXSA/hlsl/inputs/saturate1.bin rename to mlir/test/Target/DXSA/hlsl/inputs/saturate1.shex diff --git a/mlir/test/Target/DXSA/hlsl/inputs/shift1.bin b/mlir/test/Target/DXSA/hlsl/inputs/shift1.shex similarity index 100% rename from mlir/test/Target/DXSA/hlsl/inputs/shift1.bin rename to mlir/test/Target/DXSA/hlsl/inputs/shift1.shex diff --git a/mlir/test/Target/DXSA/hlsl/inputs/sincos.bin b/mlir/test/Target/DXSA/hlsl/inputs/sincos.shex similarity index 100% rename from mlir/test/Target/DXSA/hlsl/inputs/sincos.bin rename to mlir/test/Target/DXSA/hlsl/inputs/sincos.shex diff --git a/mlir/test/Target/DXSA/hlsl/inputs/snorm1.bin b/mlir/test/Target/DXSA/hlsl/inputs/snorm1.shex similarity index 100% rename from mlir/test/Target/DXSA/hlsl/inputs/snorm1.bin rename to mlir/test/Target/DXSA/hlsl/inputs/snorm1.shex diff --git a/mlir/test/Target/DXSA/hlsl/inputs/srv_ms_load1.bin b/mlir/test/Target/DXSA/hlsl/inputs/srv_ms_load1.shex similarity index 100% rename from mlir/test/Target/DXSA/hlsl/inputs/srv_ms_load1.bin rename to mlir/test/Target/DXSA/hlsl/inputs/srv_ms_load1.shex diff --git a/mlir/test/Target/DXSA/hlsl/inputs/srv_typed_load1.bin b/mlir/test/Target/DXSA/hlsl/inputs/srv_typed_load1.shex similarity index 100% rename from mlir/test/Target/DXSA/hlsl/inputs/srv_typed_load1.bin rename to mlir/test/Target/DXSA/hlsl/inputs/srv_typed_load1.shex diff --git a/mlir/test/Target/DXSA/hlsl/inputs/srv_typed_load2.bin b/mlir/test/Target/DXSA/hlsl/inputs/srv_typed_load2.shex similarity index 100% rename from mlir/test/Target/DXSA/hlsl/inputs/srv_typed_load2.bin rename to mlir/test/Target/DXSA/hlsl/inputs/srv_typed_load2.shex diff --git a/mlir/test/Target/DXSA/hlsl/inputs/struct_buf1.bin b/mlir/test/Target/DXSA/hlsl/inputs/struct_buf1.shex similarity index 100% rename from mlir/test/Target/DXSA/hlsl/inputs/struct_buf1.bin rename to mlir/test/Target/DXSA/hlsl/inputs/struct_buf1.shex diff --git a/mlir/test/Target/DXSA/hlsl/inputs/sub1.bin b/mlir/test/Target/DXSA/hlsl/inputs/sub1.shex similarity index 100% rename from mlir/test/Target/DXSA/hlsl/inputs/sub1.bin rename to mlir/test/Target/DXSA/hlsl/inputs/sub1.shex diff --git a/mlir/test/Target/DXSA/hlsl/inputs/switch1.bin b/mlir/test/Target/DXSA/hlsl/inputs/switch1.shex similarity index 100% rename from mlir/test/Target/DXSA/hlsl/inputs/switch1.bin rename to mlir/test/Target/DXSA/hlsl/inputs/switch1.shex diff --git a/mlir/test/Target/DXSA/hlsl/inputs/switch2.bin b/mlir/test/Target/DXSA/hlsl/inputs/switch2.shex similarity index 100% rename from mlir/test/Target/DXSA/hlsl/inputs/switch2.bin rename to mlir/test/Target/DXSA/hlsl/inputs/switch2.shex diff --git a/mlir/test/Target/DXSA/hlsl/inputs/switch3.bin b/mlir/test/Target/DXSA/hlsl/inputs/switch3.shex similarity index 100% rename from mlir/test/Target/DXSA/hlsl/inputs/switch3.bin rename to mlir/test/Target/DXSA/hlsl/inputs/switch3.shex diff --git a/mlir/test/Target/DXSA/hlsl/inputs/swizzle1.bin b/mlir/test/Target/DXSA/hlsl/inputs/swizzle1.shex similarity index 100% rename from mlir/test/Target/DXSA/hlsl/inputs/swizzle1.bin rename to mlir/test/Target/DXSA/hlsl/inputs/swizzle1.shex diff --git a/mlir/test/Target/DXSA/hlsl/inputs/temp1.bin b/mlir/test/Target/DXSA/hlsl/inputs/temp1.shex similarity index 100% rename from mlir/test/Target/DXSA/hlsl/inputs/temp1.bin rename to mlir/test/Target/DXSA/hlsl/inputs/temp1.shex diff --git a/mlir/test/Target/DXSA/hlsl/inputs/temp2.bin b/mlir/test/Target/DXSA/hlsl/inputs/temp2.shex similarity index 100% rename from mlir/test/Target/DXSA/hlsl/inputs/temp2.bin rename to mlir/test/Target/DXSA/hlsl/inputs/temp2.shex diff --git a/mlir/test/Target/DXSA/hlsl/inputs/uav_counter_dec.bin b/mlir/test/Target/DXSA/hlsl/inputs/uav_counter_dec.shex similarity index 100% rename from mlir/test/Target/DXSA/hlsl/inputs/uav_counter_dec.bin rename to mlir/test/Target/DXSA/hlsl/inputs/uav_counter_dec.shex diff --git a/mlir/test/Target/DXSA/hlsl/inputs/uav_counter_inc.bin b/mlir/test/Target/DXSA/hlsl/inputs/uav_counter_inc.shex similarity index 100% rename from mlir/test/Target/DXSA/hlsl/inputs/uav_counter_inc.bin rename to mlir/test/Target/DXSA/hlsl/inputs/uav_counter_inc.shex diff --git a/mlir/test/Target/DXSA/hlsl/inputs/uav_raw1.bin b/mlir/test/Target/DXSA/hlsl/inputs/uav_raw1.shex similarity index 100% rename from mlir/test/Target/DXSA/hlsl/inputs/uav_raw1.bin rename to mlir/test/Target/DXSA/hlsl/inputs/uav_raw1.shex diff --git a/mlir/test/Target/DXSA/hlsl/inputs/uav_typed_load_store1.bin b/mlir/test/Target/DXSA/hlsl/inputs/uav_typed_load_store1.shex similarity index 100% rename from mlir/test/Target/DXSA/hlsl/inputs/uav_typed_load_store1.bin rename to mlir/test/Target/DXSA/hlsl/inputs/uav_typed_load_store1.shex diff --git a/mlir/test/Target/DXSA/hlsl/inputs/uav_typed_load_store2.bin b/mlir/test/Target/DXSA/hlsl/inputs/uav_typed_load_store2.shex similarity index 100% rename from mlir/test/Target/DXSA/hlsl/inputs/uav_typed_load_store2.bin rename to mlir/test/Target/DXSA/hlsl/inputs/uav_typed_load_store2.shex diff --git a/mlir/test/Target/DXSA/hlsl/inputs/ubfeu16.bin b/mlir/test/Target/DXSA/hlsl/inputs/ubfeu16.shex similarity index 100% rename from mlir/test/Target/DXSA/hlsl/inputs/ubfeu16.bin rename to mlir/test/Target/DXSA/hlsl/inputs/ubfeu16.shex diff --git a/mlir/test/Target/DXSA/hlsl/interface1.test b/mlir/test/Target/DXSA/hlsl/interface1.test index 9c83ff710f0d..9b18dc14ddd9 100644 --- a/mlir/test/Target/DXSA/hlsl/interface1.test +++ b/mlir/test/Target/DXSA/hlsl/interface1.test @@ -1,13 +1,6 @@ -// RUN: mlir-translate --import-dxsa-bin %S/inputs/interface1.bin | FileCheck %s +// RUN: mlir-translate --import-dxsa-bin %S/inputs/interface1.shex | FileCheck %s // NOTE: Assertions have been autogenerated by utils/generate-test-checks.py -// This script is intended to make adding checks to a test case quick and easy. -// It is *not* authoritative about what constitutes a good test. After using the -// script, be sure to review and refine the generated checks. For example, -// CHECK lines should be minimized and named to reflect the test’s intent. -// For comprehensive guidelines, see: -// * https://mlir.llvm.org/getting_started/TestingGuide/ - // CHECK-LABEL: dxsa.dcl_global_flags // CHECK: dxsa.dcl_constant_buffer , diff --git a/mlir/test/Target/DXSA/hlsl/liveness1.test b/mlir/test/Target/DXSA/hlsl/liveness1.test index 30e5c7a14d3e..d4f88953dff8 100644 --- a/mlir/test/Target/DXSA/hlsl/liveness1.test +++ b/mlir/test/Target/DXSA/hlsl/liveness1.test @@ -1,13 +1,6 @@ -// RUN: mlir-translate --import-dxsa-bin %S/inputs/liveness1.bin | FileCheck %s +// RUN: mlir-translate --import-dxsa-bin %S/inputs/liveness1.shex | FileCheck %s // NOTE: Assertions have been autogenerated by utils/generate-test-checks.py -// This script is intended to make adding checks to a test case quick and easy. -// It is *not* authoritative about what constitutes a good test. After using the -// script, be sure to review and refine the generated checks. For example, -// CHECK lines should be minimized and named to reflect the test’s intent. -// For comprehensive guidelines, see: -// * https://mlir.llvm.org/getting_started/TestingGuide/ - // CHECK-LABEL: dxsa.dcl_global_flags // CHECK: dxsa.dcl_input_ps linear v<0> diff --git a/mlir/test/Target/DXSA/hlsl/loop1.test b/mlir/test/Target/DXSA/hlsl/loop1.test index 4612de44172a..c6d08fd8dc05 100644 --- a/mlir/test/Target/DXSA/hlsl/loop1.test +++ b/mlir/test/Target/DXSA/hlsl/loop1.test @@ -1,13 +1,6 @@ -// RUN: mlir-translate --import-dxsa-bin %S/inputs/loop1.bin | FileCheck %s +// RUN: mlir-translate --import-dxsa-bin %S/inputs/loop1.shex | FileCheck %s // NOTE: Assertions have been autogenerated by utils/generate-test-checks.py -// This script is intended to make adding checks to a test case quick and easy. -// It is *not* authoritative about what constitutes a good test. After using the -// script, be sure to review and refine the generated checks. For example, -// CHECK lines should be minimized and named to reflect the test’s intent. -// For comprehensive guidelines, see: -// * https://mlir.llvm.org/getting_started/TestingGuide/ - // CHECK-LABEL: dxsa.dcl_global_flags // CHECK: dxsa.dcl_input_ps linear v<0, > diff --git a/mlir/test/Target/DXSA/hlsl/loop2.test b/mlir/test/Target/DXSA/hlsl/loop2.test index 0136db8f5777..efdf3f62d115 100644 --- a/mlir/test/Target/DXSA/hlsl/loop2.test +++ b/mlir/test/Target/DXSA/hlsl/loop2.test @@ -1,13 +1,6 @@ -// RUN: mlir-translate --import-dxsa-bin %S/inputs/loop2.bin | FileCheck %s +// RUN: mlir-translate --import-dxsa-bin %S/inputs/loop2.shex | FileCheck %s // NOTE: Assertions have been autogenerated by utils/generate-test-checks.py -// This script is intended to make adding checks to a test case quick and easy. -// It is *not* authoritative about what constitutes a good test. After using the -// script, be sure to review and refine the generated checks. For example, -// CHECK lines should be minimized and named to reflect the test’s intent. -// For comprehensive guidelines, see: -// * https://mlir.llvm.org/getting_started/TestingGuide/ - // CHECK-LABEL: dxsa.dcl_global_flags // CHECK: dxsa.dcl_input_ps linear v<0, > diff --git a/mlir/test/Target/DXSA/hlsl/loop3.test b/mlir/test/Target/DXSA/hlsl/loop3.test index 03f073538a2c..72affaf370f5 100644 --- a/mlir/test/Target/DXSA/hlsl/loop3.test +++ b/mlir/test/Target/DXSA/hlsl/loop3.test @@ -1,13 +1,6 @@ -// RUN: mlir-translate --import-dxsa-bin %S/inputs/loop3.bin | FileCheck %s +// RUN: mlir-translate --import-dxsa-bin %S/inputs/loop3.shex | FileCheck %s // NOTE: Assertions have been autogenerated by utils/generate-test-checks.py -// This script is intended to make adding checks to a test case quick and easy. -// It is *not* authoritative about what constitutes a good test. After using the -// script, be sure to review and refine the generated checks. For example, -// CHECK lines should be minimized and named to reflect the test’s intent. -// For comprehensive guidelines, see: -// * https://mlir.llvm.org/getting_started/TestingGuide/ - // CHECK-LABEL: dxsa.dcl_global_flags // CHECK: dxsa.dcl_input_ps linear v<0, > diff --git a/mlir/test/Target/DXSA/hlsl/loop4.test b/mlir/test/Target/DXSA/hlsl/loop4.test index ddc0a2fb933b..446502f0a802 100644 --- a/mlir/test/Target/DXSA/hlsl/loop4.test +++ b/mlir/test/Target/DXSA/hlsl/loop4.test @@ -1,13 +1,6 @@ -// RUN: mlir-translate --import-dxsa-bin %S/inputs/loop4.bin | FileCheck %s +// RUN: mlir-translate --import-dxsa-bin %S/inputs/loop4.shex | FileCheck %s // NOTE: Assertions have been autogenerated by utils/generate-test-checks.py -// This script is intended to make adding checks to a test case quick and easy. -// It is *not* authoritative about what constitutes a good test. After using the -// script, be sure to review and refine the generated checks. For example, -// CHECK lines should be minimized and named to reflect the test’s intent. -// For comprehensive guidelines, see: -// * https://mlir.llvm.org/getting_started/TestingGuide/ - // CHECK-LABEL: dxsa.dcl_global_flags // CHECK: dxsa.dcl_input_ps linear v<0, > diff --git a/mlir/test/Target/DXSA/hlsl/loop5.test b/mlir/test/Target/DXSA/hlsl/loop5.test index bbf63e1a11dd..e4bf6bcbe919 100644 --- a/mlir/test/Target/DXSA/hlsl/loop5.test +++ b/mlir/test/Target/DXSA/hlsl/loop5.test @@ -1,13 +1,6 @@ -// RUN: mlir-translate --import-dxsa-bin %S/inputs/loop5.bin | FileCheck %s +// RUN: mlir-translate --import-dxsa-bin %S/inputs/loop5.shex | FileCheck %s // NOTE: Assertions have been autogenerated by utils/generate-test-checks.py -// This script is intended to make adding checks to a test case quick and easy. -// It is *not* authoritative about what constitutes a good test. After using the -// script, be sure to review and refine the generated checks. For example, -// CHECK lines should be minimized and named to reflect the test’s intent. -// For comprehensive guidelines, see: -// * https://mlir.llvm.org/getting_started/TestingGuide/ - // CHECK-LABEL: dxsa.dcl_global_flags // CHECK: dxsa.dcl_input_ps linear v<0, > diff --git a/mlir/test/Target/DXSA/hlsl/minprec1.test b/mlir/test/Target/DXSA/hlsl/minprec1.test index b3fcd845cf2a..b55edeaec763 100644 --- a/mlir/test/Target/DXSA/hlsl/minprec1.test +++ b/mlir/test/Target/DXSA/hlsl/minprec1.test @@ -1,13 +1,6 @@ -// RUN: mlir-translate --import-dxsa-bin %S/inputs/minprec1.bin | FileCheck %s +// RUN: mlir-translate --import-dxsa-bin %S/inputs/minprec1.shex | FileCheck %s // NOTE: Assertions have been autogenerated by utils/generate-test-checks.py -// This script is intended to make adding checks to a test case quick and easy. -// It is *not* authoritative about what constitutes a good test. After using the -// script, be sure to review and refine the generated checks. For example, -// CHECK lines should be minimized and named to reflect the test’s intent. -// For comprehensive guidelines, see: -// * https://mlir.llvm.org/getting_started/TestingGuide/ - // CHECK-LABEL: dxsa.dcl_global_flags // CHECK: dxsa.dcl_input_ps linear v<0, min16f, > diff --git a/mlir/test/Target/DXSA/hlsl/minprec2.test b/mlir/test/Target/DXSA/hlsl/minprec2.test index b2fb75d5bbb1..6a12031b48b0 100644 --- a/mlir/test/Target/DXSA/hlsl/minprec2.test +++ b/mlir/test/Target/DXSA/hlsl/minprec2.test @@ -1,13 +1,6 @@ -// RUN: mlir-translate --import-dxsa-bin %S/inputs/minprec2.bin | FileCheck %s +// RUN: mlir-translate --import-dxsa-bin %S/inputs/minprec2.shex | FileCheck %s // NOTE: Assertions have been autogenerated by utils/generate-test-checks.py -// This script is intended to make adding checks to a test case quick and easy. -// It is *not* authoritative about what constitutes a good test. After using the -// script, be sure to review and refine the generated checks. For example, -// CHECK lines should be minimized and named to reflect the test’s intent. -// For comprehensive guidelines, see: -// * https://mlir.llvm.org/getting_started/TestingGuide/ - // CHECK-LABEL: dxsa.dcl_global_flags // CHECK: dxsa.dcl_input_ps linear v<0, min16f, > diff --git a/mlir/test/Target/DXSA/hlsl/minprec3.test b/mlir/test/Target/DXSA/hlsl/minprec3.test index bcec0105fcee..0a30f8b9124f 100644 --- a/mlir/test/Target/DXSA/hlsl/minprec3.test +++ b/mlir/test/Target/DXSA/hlsl/minprec3.test @@ -1,13 +1,6 @@ -// RUN: mlir-translate --import-dxsa-bin %S/inputs/minprec3.bin | FileCheck %s +// RUN: mlir-translate --import-dxsa-bin %S/inputs/minprec3.shex | FileCheck %s // NOTE: Assertions have been autogenerated by utils/generate-test-checks.py -// This script is intended to make adding checks to a test case quick and easy. -// It is *not* authoritative about what constitutes a good test. After using the -// script, be sure to review and refine the generated checks. For example, -// CHECK lines should be minimized and named to reflect the test’s intent. -// For comprehensive guidelines, see: -// * https://mlir.llvm.org/getting_started/TestingGuide/ - // CHECK-LABEL: dxsa.dcl_global_flags // CHECK: dxsa.dcl_input_ps constant v<0, min16i, > diff --git a/mlir/test/Target/DXSA/hlsl/minprec4.test b/mlir/test/Target/DXSA/hlsl/minprec4.test index 019a32f2f8a2..c7b5076995c8 100644 --- a/mlir/test/Target/DXSA/hlsl/minprec4.test +++ b/mlir/test/Target/DXSA/hlsl/minprec4.test @@ -1,13 +1,6 @@ -// RUN: mlir-translate --import-dxsa-bin %S/inputs/minprec4.bin | FileCheck %s +// RUN: mlir-translate --import-dxsa-bin %S/inputs/minprec4.shex | FileCheck %s // NOTE: Assertions have been autogenerated by utils/generate-test-checks.py -// This script is intended to make adding checks to a test case quick and easy. -// It is *not* authoritative about what constitutes a good test. After using the -// script, be sure to review and refine the generated checks. For example, -// CHECK lines should be minimized and named to reflect the test’s intent. -// For comprehensive guidelines, see: -// * https://mlir.llvm.org/getting_started/TestingGuide/ - // CHECK-LABEL: dxsa.dcl_global_flags // CHECK: dxsa.dcl_input_ps constant v<0, min16u, > diff --git a/mlir/test/Target/DXSA/hlsl/minprec5.test b/mlir/test/Target/DXSA/hlsl/minprec5.test index 3dec93335ec5..f8ea38ac6eab 100644 --- a/mlir/test/Target/DXSA/hlsl/minprec5.test +++ b/mlir/test/Target/DXSA/hlsl/minprec5.test @@ -1,13 +1,6 @@ -// RUN: mlir-translate --import-dxsa-bin %S/inputs/minprec5.bin | FileCheck %s +// RUN: mlir-translate --import-dxsa-bin %S/inputs/minprec5.shex | FileCheck %s // NOTE: Assertions have been autogenerated by utils/generate-test-checks.py -// This script is intended to make adding checks to a test case quick and easy. -// It is *not* authoritative about what constitutes a good test. After using the -// script, be sure to review and refine the generated checks. For example, -// CHECK lines should be minimized and named to reflect the test’s intent. -// For comprehensive guidelines, see: -// * https://mlir.llvm.org/getting_started/TestingGuide/ - // CHECK-LABEL: dxsa.dcl_global_flags // CHECK: dxsa.dcl_input_ps linear v<0, > diff --git a/mlir/test/Target/DXSA/hlsl/minprec6.test b/mlir/test/Target/DXSA/hlsl/minprec6.test index 99a2309d3c18..cdbb154703cc 100644 --- a/mlir/test/Target/DXSA/hlsl/minprec6.test +++ b/mlir/test/Target/DXSA/hlsl/minprec6.test @@ -1,13 +1,6 @@ -// RUN: mlir-translate --import-dxsa-bin %S/inputs/minprec6.bin | FileCheck %s +// RUN: mlir-translate --import-dxsa-bin %S/inputs/minprec6.shex | FileCheck %s // NOTE: Assertions have been autogenerated by utils/generate-test-checks.py -// This script is intended to make adding checks to a test case quick and easy. -// It is *not* authoritative about what constitutes a good test. After using the -// script, be sure to review and refine the generated checks. For example, -// CHECK lines should be minimized and named to reflect the test’s intent. -// For comprehensive guidelines, see: -// * https://mlir.llvm.org/getting_started/TestingGuide/ - // CHECK-LABEL: dxsa.dcl_global_flags // CHECK: dxsa.dcl_constant_buffer , diff --git a/mlir/test/Target/DXSA/hlsl/minprec7.test b/mlir/test/Target/DXSA/hlsl/minprec7.test index 5420de2a8d48..e8f05fff92c6 100644 --- a/mlir/test/Target/DXSA/hlsl/minprec7.test +++ b/mlir/test/Target/DXSA/hlsl/minprec7.test @@ -1,13 +1,6 @@ -// RUN: mlir-translate --import-dxsa-bin %S/inputs/minprec7.bin | FileCheck %s +// RUN: mlir-translate --import-dxsa-bin %S/inputs/minprec7.shex | FileCheck %s // NOTE: Assertions have been autogenerated by utils/generate-test-checks.py -// This script is intended to make adding checks to a test case quick and easy. -// It is *not* authoritative about what constitutes a good test. After using the -// script, be sure to review and refine the generated checks. For example, -// CHECK lines should be minimized and named to reflect the test’s intent. -// For comprehensive guidelines, see: -// * https://mlir.llvm.org/getting_started/TestingGuide/ - // CHECK-LABEL: dxsa.dcl_global_flags // CHECK: dxsa.dcl_input_ps linear v<0, > diff --git a/mlir/test/Target/DXSA/hlsl/neg1.test b/mlir/test/Target/DXSA/hlsl/neg1.test index a6bbcae8d794..e9c28ce57c10 100644 --- a/mlir/test/Target/DXSA/hlsl/neg1.test +++ b/mlir/test/Target/DXSA/hlsl/neg1.test @@ -1,13 +1,6 @@ -// RUN: mlir-translate --import-dxsa-bin %S/inputs/neg1.bin | FileCheck %s +// RUN: mlir-translate --import-dxsa-bin %S/inputs/neg1.shex | FileCheck %s // NOTE: Assertions have been autogenerated by utils/generate-test-checks.py -// This script is intended to make adding checks to a test case quick and easy. -// It is *not* authoritative about what constitutes a good test. After using the -// script, be sure to review and refine the generated checks. For example, -// CHECK lines should be minimized and named to reflect the test’s intent. -// For comprehensive guidelines, see: -// * https://mlir.llvm.org/getting_started/TestingGuide/ - // CHECK-LABEL: dxsa.dcl_global_flags // CHECK: dxsa.dcl_input_ps linear v<0, > diff --git a/mlir/test/Target/DXSA/hlsl/neg2.test b/mlir/test/Target/DXSA/hlsl/neg2.test index a8a79bd354d3..465b9f79c789 100644 --- a/mlir/test/Target/DXSA/hlsl/neg2.test +++ b/mlir/test/Target/DXSA/hlsl/neg2.test @@ -1,13 +1,6 @@ -// RUN: mlir-translate --import-dxsa-bin %S/inputs/neg2.bin | FileCheck %s +// RUN: mlir-translate --import-dxsa-bin %S/inputs/neg2.shex | FileCheck %s // NOTE: Assertions have been autogenerated by utils/generate-test-checks.py -// This script is intended to make adding checks to a test case quick and easy. -// It is *not* authoritative about what constitutes a good test. After using the -// script, be sure to review and refine the generated checks. For example, -// CHECK lines should be minimized and named to reflect the test’s intent. -// For comprehensive guidelines, see: -// * https://mlir.llvm.org/getting_started/TestingGuide/ - // CHECK-LABEL: dxsa.dcl_global_flags // CHECK: dxsa.dcl_input_ps constant v<0, > diff --git a/mlir/test/Target/DXSA/hlsl/negabs1.test b/mlir/test/Target/DXSA/hlsl/negabs1.test index 058367287d83..ae9d5e8dc355 100644 --- a/mlir/test/Target/DXSA/hlsl/negabs1.test +++ b/mlir/test/Target/DXSA/hlsl/negabs1.test @@ -1,13 +1,6 @@ -// RUN: mlir-translate --import-dxsa-bin %S/inputs/negabs1.bin | FileCheck %s +// RUN: mlir-translate --import-dxsa-bin %S/inputs/negabs1.shex | FileCheck %s // NOTE: Assertions have been autogenerated by utils/generate-test-checks.py -// This script is intended to make adding checks to a test case quick and easy. -// It is *not* authoritative about what constitutes a good test. After using the -// script, be sure to review and refine the generated checks. For example, -// CHECK lines should be minimized and named to reflect the test’s intent. -// For comprehensive guidelines, see: -// * https://mlir.llvm.org/getting_started/TestingGuide/ - // CHECK-LABEL: dxsa.dcl_global_flags // CHECK: dxsa.dcl_input_ps linear v<0, > diff --git a/mlir/test/Target/DXSA/hlsl/nonuniform1.test b/mlir/test/Target/DXSA/hlsl/nonuniform1.test index 6b71481be569..ba2bdda8c5ba 100644 --- a/mlir/test/Target/DXSA/hlsl/nonuniform1.test +++ b/mlir/test/Target/DXSA/hlsl/nonuniform1.test @@ -1,13 +1,6 @@ -// RUN: mlir-translate --import-dxsa-bin %S/inputs/nonuniform1.bin | FileCheck %s +// RUN: mlir-translate --import-dxsa-bin %S/inputs/nonuniform1.shex | FileCheck %s // NOTE: Assertions have been autogenerated by utils/generate-test-checks.py -// This script is intended to make adding checks to a test case quick and easy. -// It is *not* authoritative about what constitutes a good test. After using the -// script, be sure to review and refine the generated checks. For example, -// CHECK lines should be minimized and named to reflect the test’s intent. -// For comprehensive guidelines, see: -// * https://mlir.llvm.org/getting_started/TestingGuide/ - // CHECK-LABEL: dxsa.dcl_global_flags // CHECK: dxsa.dcl_sampler diff --git a/mlir/test/Target/DXSA/hlsl/output1.test b/mlir/test/Target/DXSA/hlsl/output1.test index 573cbc1bcaf5..dcc754fd2961 100644 --- a/mlir/test/Target/DXSA/hlsl/output1.test +++ b/mlir/test/Target/DXSA/hlsl/output1.test @@ -1,13 +1,6 @@ -// RUN: mlir-translate --import-dxsa-bin %S/inputs/output1.bin | FileCheck %s +// RUN: mlir-translate --import-dxsa-bin %S/inputs/output1.shex | FileCheck %s // NOTE: Assertions have been autogenerated by utils/generate-test-checks.py -// This script is intended to make adding checks to a test case quick and easy. -// It is *not* authoritative about what constitutes a good test. After using the -// script, be sure to review and refine the generated checks. For example, -// CHECK lines should be minimized and named to reflect the test’s intent. -// For comprehensive guidelines, see: -// * https://mlir.llvm.org/getting_started/TestingGuide/ - // CHECK-LABEL: dxsa.dcl_global_flags // CHECK: dxsa.dcl_input_ps linear v<0> diff --git a/mlir/test/Target/DXSA/hlsl/output2.test b/mlir/test/Target/DXSA/hlsl/output2.test index 7252692e947c..6c7a856d1f08 100644 --- a/mlir/test/Target/DXSA/hlsl/output2.test +++ b/mlir/test/Target/DXSA/hlsl/output2.test @@ -1,13 +1,6 @@ -// RUN: mlir-translate --import-dxsa-bin %S/inputs/output2.bin | FileCheck %s +// RUN: mlir-translate --import-dxsa-bin %S/inputs/output2.shex | FileCheck %s // NOTE: Assertions have been autogenerated by utils/generate-test-checks.py -// This script is intended to make adding checks to a test case quick and easy. -// It is *not* authoritative about what constitutes a good test. After using the -// script, be sure to review and refine the generated checks. For example, -// CHECK lines should be minimized and named to reflect the test’s intent. -// For comprehensive guidelines, see: -// * https://mlir.llvm.org/getting_started/TestingGuide/ - // CHECK-LABEL: dxsa.dcl_global_flags // CHECK: dxsa.dcl_input_ps linear v<0> diff --git a/mlir/test/Target/DXSA/hlsl/output3.test b/mlir/test/Target/DXSA/hlsl/output3.test index 0fdcdef9111d..a71375e9dc27 100644 --- a/mlir/test/Target/DXSA/hlsl/output3.test +++ b/mlir/test/Target/DXSA/hlsl/output3.test @@ -1,13 +1,6 @@ -// RUN: mlir-translate --import-dxsa-bin %S/inputs/output3.bin | FileCheck %s +// RUN: mlir-translate --import-dxsa-bin %S/inputs/output3.shex | FileCheck %s // NOTE: Assertions have been autogenerated by utils/generate-test-checks.py -// This script is intended to make adding checks to a test case quick and easy. -// It is *not* authoritative about what constitutes a good test. After using the -// script, be sure to review and refine the generated checks. For example, -// CHECK lines should be minimized and named to reflect the test’s intent. -// For comprehensive guidelines, see: -// * https://mlir.llvm.org/getting_started/TestingGuide/ - // CHECK-LABEL: dxsa.dcl_global_flags // CHECK: dxsa.dcl_input_ps linear v<0> diff --git a/mlir/test/Target/DXSA/hlsl/output4.test b/mlir/test/Target/DXSA/hlsl/output4.test index 44b6b1de74bb..d8cf1d10df69 100644 --- a/mlir/test/Target/DXSA/hlsl/output4.test +++ b/mlir/test/Target/DXSA/hlsl/output4.test @@ -1,13 +1,6 @@ -// RUN: mlir-translate --import-dxsa-bin %S/inputs/output4.bin | FileCheck %s +// RUN: mlir-translate --import-dxsa-bin %S/inputs/output4.shex | FileCheck %s // NOTE: Assertions have been autogenerated by utils/generate-test-checks.py -// This script is intended to make adding checks to a test case quick and easy. -// It is *not* authoritative about what constitutes a good test. After using the -// script, be sure to review and refine the generated checks. For example, -// CHECK lines should be minimized and named to reflect the test’s intent. -// For comprehensive guidelines, see: -// * https://mlir.llvm.org/getting_started/TestingGuide/ - // CHECK-LABEL: dxsa.dcl_global_flags // CHECK: dxsa.dcl_input v<0> diff --git a/mlir/test/Target/DXSA/hlsl/passthrough1.test b/mlir/test/Target/DXSA/hlsl/passthrough1.test index 76b62a0a97d4..b388f28d3eef 100644 --- a/mlir/test/Target/DXSA/hlsl/passthrough1.test +++ b/mlir/test/Target/DXSA/hlsl/passthrough1.test @@ -1,13 +1,6 @@ -// RUN: mlir-translate --import-dxsa-bin %S/inputs/passthrough1.bin | FileCheck %s +// RUN: mlir-translate --import-dxsa-bin %S/inputs/passthrough1.shex | FileCheck %s // NOTE: Assertions have been autogenerated by utils/generate-test-checks.py -// This script is intended to make adding checks to a test case quick and easy. -// It is *not* authoritative about what constitutes a good test. After using the -// script, be sure to review and refine the generated checks. For example, -// CHECK lines should be minimized and named to reflect the test’s intent. -// For comprehensive guidelines, see: -// * https://mlir.llvm.org/getting_started/TestingGuide/ - // CHECK-LABEL: dxsa.dcl_global_flags // CHECK: dxsa.dcl_input v<0> diff --git a/mlir/test/Target/DXSA/hlsl/passthrough2.test b/mlir/test/Target/DXSA/hlsl/passthrough2.test index 681501b21f4d..7645d86e88a7 100644 --- a/mlir/test/Target/DXSA/hlsl/passthrough2.test +++ b/mlir/test/Target/DXSA/hlsl/passthrough2.test @@ -1,13 +1,6 @@ -// RUN: mlir-translate --import-dxsa-bin %S/inputs/passthrough2.bin | FileCheck %s +// RUN: mlir-translate --import-dxsa-bin %S/inputs/passthrough2.shex | FileCheck %s // NOTE: Assertions have been autogenerated by utils/generate-test-checks.py -// This script is intended to make adding checks to a test case quick and easy. -// It is *not* authoritative about what constitutes a good test. After using the -// script, be sure to review and refine the generated checks. For example, -// CHECK lines should be minimized and named to reflect the test’s intent. -// For comprehensive guidelines, see: -// * https://mlir.llvm.org/getting_started/TestingGuide/ - // CHECK-LABEL: dxsa.dcl_global_flags // CHECK: dxsa.dcl_input_ps linear v<0, > diff --git a/mlir/test/Target/DXSA/hlsl/precise1.test b/mlir/test/Target/DXSA/hlsl/precise1.test index ad4bcf552542..97ad1d4cf980 100644 --- a/mlir/test/Target/DXSA/hlsl/precise1.test +++ b/mlir/test/Target/DXSA/hlsl/precise1.test @@ -1,13 +1,6 @@ -// RUN: mlir-translate --import-dxsa-bin %S/inputs/precise1.bin | FileCheck %s +// RUN: mlir-translate --import-dxsa-bin %S/inputs/precise1.shex | FileCheck %s // NOTE: Assertions have been autogenerated by utils/generate-test-checks.py -// This script is intended to make adding checks to a test case quick and easy. -// It is *not* authoritative about what constitutes a good test. After using the -// script, be sure to review and refine the generated checks. For example, -// CHECK lines should be minimized and named to reflect the test’s intent. -// For comprehensive guidelines, see: -// * https://mlir.llvm.org/getting_started/TestingGuide/ - // CHECK-LABEL: dxsa.dcl_global_flags // CHECK: dxsa.dcl_constant_buffer , diff --git a/mlir/test/Target/DXSA/hlsl/raw_buf1.test b/mlir/test/Target/DXSA/hlsl/raw_buf1.test index 44907891c766..7cc2bb1bcf0e 100644 --- a/mlir/test/Target/DXSA/hlsl/raw_buf1.test +++ b/mlir/test/Target/DXSA/hlsl/raw_buf1.test @@ -1,13 +1,6 @@ -// RUN: mlir-translate --import-dxsa-bin %S/inputs/raw_buf1.bin | FileCheck %s +// RUN: mlir-translate --import-dxsa-bin %S/inputs/raw_buf1.shex | FileCheck %s // NOTE: Assertions have been autogenerated by utils/generate-test-checks.py -// This script is intended to make adding checks to a test case quick and easy. -// It is *not* authoritative about what constitutes a good test. After using the -// script, be sure to review and refine the generated checks. For example, -// CHECK lines should be minimized and named to reflect the test’s intent. -// For comprehensive guidelines, see: -// * https://mlir.llvm.org/getting_started/TestingGuide/ - // CHECK-LABEL: dxsa.dcl_global_flags // CHECK: dxsa.dcl_resource_raw diff --git a/mlir/test/Target/DXSA/hlsl/rcp1.test b/mlir/test/Target/DXSA/hlsl/rcp1.test index fe297fd1500a..c4e3b8e835c4 100644 --- a/mlir/test/Target/DXSA/hlsl/rcp1.test +++ b/mlir/test/Target/DXSA/hlsl/rcp1.test @@ -1,13 +1,6 @@ -// RUN: mlir-translate --import-dxsa-bin %S/inputs/rcp1.bin | FileCheck %s +// RUN: mlir-translate --import-dxsa-bin %S/inputs/rcp1.shex | FileCheck %s // NOTE: Assertions have been autogenerated by utils/generate-test-checks.py -// This script is intended to make adding checks to a test case quick and easy. -// It is *not* authoritative about what constitutes a good test. After using the -// script, be sure to review and refine the generated checks. For example, -// CHECK lines should be minimized and named to reflect the test’s intent. -// For comprehensive guidelines, see: -// * https://mlir.llvm.org/getting_started/TestingGuide/ - // CHECK-LABEL: dxsa.dcl_global_flags // CHECK: dxsa.dcl_input_ps linear v<0, > diff --git a/mlir/test/Target/DXSA/hlsl/redundantinput1.test b/mlir/test/Target/DXSA/hlsl/redundantinput1.test index 4fb22ef308f4..1ac5b2116773 100644 --- a/mlir/test/Target/DXSA/hlsl/redundantinput1.test +++ b/mlir/test/Target/DXSA/hlsl/redundantinput1.test @@ -1,13 +1,6 @@ -// RUN: mlir-translate --import-dxsa-bin %S/inputs/redundantinput1.bin | FileCheck %s +// RUN: mlir-translate --import-dxsa-bin %S/inputs/redundantinput1.shex | FileCheck %s // NOTE: Assertions have been autogenerated by utils/generate-test-checks.py -// This script is intended to make adding checks to a test case quick and easy. -// It is *not* authoritative about what constitutes a good test. After using the -// script, be sure to review and refine the generated checks. For example, -// CHECK lines should be minimized and named to reflect the test’s intent. -// For comprehensive guidelines, see: -// * https://mlir.llvm.org/getting_started/TestingGuide/ - // CHECK-LABEL: dxsa.dcl_global_flags // CHECK: dxsa.dcl_input_ps linear v<0> diff --git a/mlir/test/Target/DXSA/hlsl/sample1.test b/mlir/test/Target/DXSA/hlsl/sample1.test index abc9e8ab8dae..f07edf4f3f76 100644 --- a/mlir/test/Target/DXSA/hlsl/sample1.test +++ b/mlir/test/Target/DXSA/hlsl/sample1.test @@ -1,13 +1,6 @@ -// RUN: mlir-translate --import-dxsa-bin %S/inputs/sample1.bin | FileCheck %s +// RUN: mlir-translate --import-dxsa-bin %S/inputs/sample1.shex | FileCheck %s // NOTE: Assertions have been autogenerated by utils/generate-test-checks.py -// This script is intended to make adding checks to a test case quick and easy. -// It is *not* authoritative about what constitutes a good test. After using the -// script, be sure to review and refine the generated checks. For example, -// CHECK lines should be minimized and named to reflect the test’s intent. -// For comprehensive guidelines, see: -// * https://mlir.llvm.org/getting_started/TestingGuide/ - // CHECK-LABEL: dxsa.dcl_global_flags // CHECK: dxsa.dcl_constant_buffer , diff --git a/mlir/test/Target/DXSA/hlsl/sample2.test b/mlir/test/Target/DXSA/hlsl/sample2.test index 7ab8c9cc1c1d..92171a975b22 100644 --- a/mlir/test/Target/DXSA/hlsl/sample2.test +++ b/mlir/test/Target/DXSA/hlsl/sample2.test @@ -1,13 +1,6 @@ -// RUN: mlir-translate --import-dxsa-bin %S/inputs/sample2.bin | FileCheck %s +// RUN: mlir-translate --import-dxsa-bin %S/inputs/sample2.shex | FileCheck %s // NOTE: Assertions have been autogenerated by utils/generate-test-checks.py -// This script is intended to make adding checks to a test case quick and easy. -// It is *not* authoritative about what constitutes a good test. After using the -// script, be sure to review and refine the generated checks. For example, -// CHECK lines should be minimized and named to reflect the test’s intent. -// For comprehensive guidelines, see: -// * https://mlir.llvm.org/getting_started/TestingGuide/ - // CHECK-LABEL: dxsa.dcl_global_flags // CHECK: dxsa.dcl_constant_buffer , diff --git a/mlir/test/Target/DXSA/hlsl/sample3.test b/mlir/test/Target/DXSA/hlsl/sample3.test index 7c63c36f8cbe..82d77bd469ea 100644 --- a/mlir/test/Target/DXSA/hlsl/sample3.test +++ b/mlir/test/Target/DXSA/hlsl/sample3.test @@ -1,13 +1,6 @@ -// RUN: mlir-translate --import-dxsa-bin %S/inputs/sample3.bin | FileCheck %s +// RUN: mlir-translate --import-dxsa-bin %S/inputs/sample3.shex | FileCheck %s // NOTE: Assertions have been autogenerated by utils/generate-test-checks.py -// This script is intended to make adding checks to a test case quick and easy. -// It is *not* authoritative about what constitutes a good test. After using the -// script, be sure to review and refine the generated checks. For example, -// CHECK lines should be minimized and named to reflect the test’s intent. -// For comprehensive guidelines, see: -// * https://mlir.llvm.org/getting_started/TestingGuide/ - // CHECK-LABEL: dxsa.dcl_global_flags // CHECK: dxsa.dcl_sampler diff --git a/mlir/test/Target/DXSA/hlsl/sample_b1.test b/mlir/test/Target/DXSA/hlsl/sample_b1.test index 29aa8d117d0e..a077add057f4 100644 --- a/mlir/test/Target/DXSA/hlsl/sample_b1.test +++ b/mlir/test/Target/DXSA/hlsl/sample_b1.test @@ -1,13 +1,6 @@ -// RUN: mlir-translate --import-dxsa-bin %S/inputs/sample_b1.bin | FileCheck %s +// RUN: mlir-translate --import-dxsa-bin %S/inputs/sample_b1.shex | FileCheck %s // NOTE: Assertions have been autogenerated by utils/generate-test-checks.py -// This script is intended to make adding checks to a test case quick and easy. -// It is *not* authoritative about what constitutes a good test. After using the -// script, be sure to review and refine the generated checks. For example, -// CHECK lines should be minimized and named to reflect the test’s intent. -// For comprehensive guidelines, see: -// * https://mlir.llvm.org/getting_started/TestingGuide/ - // CHECK-LABEL: dxsa.dcl_global_flags // CHECK: dxsa.dcl_sampler diff --git a/mlir/test/Target/DXSA/hlsl/sample_cmp1.test b/mlir/test/Target/DXSA/hlsl/sample_cmp1.test index a4129610835f..88fac5d4d1e1 100644 --- a/mlir/test/Target/DXSA/hlsl/sample_cmp1.test +++ b/mlir/test/Target/DXSA/hlsl/sample_cmp1.test @@ -1,13 +1,6 @@ -// RUN: mlir-translate --import-dxsa-bin %S/inputs/sample_cmp1.bin | FileCheck %s +// RUN: mlir-translate --import-dxsa-bin %S/inputs/sample_cmp1.shex | FileCheck %s // NOTE: Assertions have been autogenerated by utils/generate-test-checks.py -// This script is intended to make adding checks to a test case quick and easy. -// It is *not* authoritative about what constitutes a good test. After using the -// script, be sure to review and refine the generated checks. For example, -// CHECK lines should be minimized and named to reflect the test’s intent. -// For comprehensive guidelines, see: -// * https://mlir.llvm.org/getting_started/TestingGuide/ - // CHECK-LABEL: dxsa.dcl_global_flags // CHECK: dxsa.dcl_sampler diff --git a/mlir/test/Target/DXSA/hlsl/sample_cmp2.test b/mlir/test/Target/DXSA/hlsl/sample_cmp2.test index 00aeaac4f279..a394d3e6a879 100644 --- a/mlir/test/Target/DXSA/hlsl/sample_cmp2.test +++ b/mlir/test/Target/DXSA/hlsl/sample_cmp2.test @@ -1,13 +1,6 @@ -// RUN: mlir-translate --import-dxsa-bin %S/inputs/sample_cmp2.bin | FileCheck %s +// RUN: mlir-translate --import-dxsa-bin %S/inputs/sample_cmp2.shex | FileCheck %s // NOTE: Assertions have been autogenerated by utils/generate-test-checks.py -// This script is intended to make adding checks to a test case quick and easy. -// It is *not* authoritative about what constitutes a good test. After using the -// script, be sure to review and refine the generated checks. For example, -// CHECK lines should be minimized and named to reflect the test’s intent. -// For comprehensive guidelines, see: -// * https://mlir.llvm.org/getting_started/TestingGuide/ - // CHECK-LABEL: dxsa.dcl_global_flags // CHECK: dxsa.dcl_sampler diff --git a/mlir/test/Target/DXSA/hlsl/sample_grad1.test b/mlir/test/Target/DXSA/hlsl/sample_grad1.test index 54930da05061..55bd3cc1e834 100644 --- a/mlir/test/Target/DXSA/hlsl/sample_grad1.test +++ b/mlir/test/Target/DXSA/hlsl/sample_grad1.test @@ -1,13 +1,6 @@ -// RUN: mlir-translate --import-dxsa-bin %S/inputs/sample_grad1.bin | FileCheck %s +// RUN: mlir-translate --import-dxsa-bin %S/inputs/sample_grad1.shex | FileCheck %s // NOTE: Assertions have been autogenerated by utils/generate-test-checks.py -// This script is intended to make adding checks to a test case quick and easy. -// It is *not* authoritative about what constitutes a good test. After using the -// script, be sure to review and refine the generated checks. For example, -// CHECK lines should be minimized and named to reflect the test’s intent. -// For comprehensive guidelines, see: -// * https://mlir.llvm.org/getting_started/TestingGuide/ - // CHECK-LABEL: dxsa.dcl_global_flags // CHECK: dxsa.dcl_sampler diff --git a/mlir/test/Target/DXSA/hlsl/sample_l1.test b/mlir/test/Target/DXSA/hlsl/sample_l1.test index ce27dd701c27..8b010f19d46a 100644 --- a/mlir/test/Target/DXSA/hlsl/sample_l1.test +++ b/mlir/test/Target/DXSA/hlsl/sample_l1.test @@ -1,13 +1,6 @@ -// RUN: mlir-translate --import-dxsa-bin %S/inputs/sample_l1.bin | FileCheck %s +// RUN: mlir-translate --import-dxsa-bin %S/inputs/sample_l1.shex | FileCheck %s // NOTE: Assertions have been autogenerated by utils/generate-test-checks.py -// This script is intended to make adding checks to a test case quick and easy. -// It is *not* authoritative about what constitutes a good test. After using the -// script, be sure to review and refine the generated checks. For example, -// CHECK lines should be minimized and named to reflect the test’s intent. -// For comprehensive guidelines, see: -// * https://mlir.llvm.org/getting_started/TestingGuide/ - // CHECK-LABEL: dxsa.dcl_global_flags // CHECK: dxsa.dcl_sampler diff --git a/mlir/test/Target/DXSA/hlsl/samplecount.test b/mlir/test/Target/DXSA/hlsl/samplecount.test index 65bd246aed6d..88818895ffe5 100644 --- a/mlir/test/Target/DXSA/hlsl/samplecount.test +++ b/mlir/test/Target/DXSA/hlsl/samplecount.test @@ -1,13 +1,6 @@ -// RUN: mlir-translate --import-dxsa-bin %S/inputs/samplecount.bin | FileCheck %s +// RUN: mlir-translate --import-dxsa-bin %S/inputs/samplecount.shex | FileCheck %s // NOTE: Assertions have been autogenerated by utils/generate-test-checks.py -// This script is intended to make adding checks to a test case quick and easy. -// It is *not* authoritative about what constitutes a good test. After using the -// script, be sure to review and refine the generated checks. For example, -// CHECK lines should be minimized and named to reflect the test’s intent. -// For comprehensive guidelines, see: -// * https://mlir.llvm.org/getting_started/TestingGuide/ - // CHECK-LABEL: dxsa.dcl_global_flags // CHECK: dxsa.dcl_output o<0> diff --git a/mlir/test/Target/DXSA/hlsl/samplepos.test b/mlir/test/Target/DXSA/hlsl/samplepos.test index 4161bb9f4ffd..b7f3cab7da87 100644 --- a/mlir/test/Target/DXSA/hlsl/samplepos.test +++ b/mlir/test/Target/DXSA/hlsl/samplepos.test @@ -1,13 +1,6 @@ -// RUN: mlir-translate --import-dxsa-bin %S/inputs/samplepos.bin | FileCheck %s +// RUN: mlir-translate --import-dxsa-bin %S/inputs/samplepos.shex | FileCheck %s // NOTE: Assertions have been autogenerated by utils/generate-test-checks.py -// This script is intended to make adding checks to a test case quick and easy. -// It is *not* authoritative about what constitutes a good test. After using the -// script, be sure to review and refine the generated checks. For example, -// CHECK lines should be minimized and named to reflect the test’s intent. -// For comprehensive guidelines, see: -// * https://mlir.llvm.org/getting_started/TestingGuide/ - // CHECK-LABEL: dxsa.dcl_global_flags // CHECK: dxsa.unknown diff --git a/mlir/test/Target/DXSA/hlsl/saturate1.test b/mlir/test/Target/DXSA/hlsl/saturate1.test index 487c3918283f..a5ebcce31861 100644 --- a/mlir/test/Target/DXSA/hlsl/saturate1.test +++ b/mlir/test/Target/DXSA/hlsl/saturate1.test @@ -1,13 +1,6 @@ -// RUN: mlir-translate --import-dxsa-bin %S/inputs/saturate1.bin | FileCheck %s +// RUN: mlir-translate --import-dxsa-bin %S/inputs/saturate1.shex | FileCheck %s // NOTE: Assertions have been autogenerated by utils/generate-test-checks.py -// This script is intended to make adding checks to a test case quick and easy. -// It is *not* authoritative about what constitutes a good test. After using the -// script, be sure to review and refine the generated checks. For example, -// CHECK lines should be minimized and named to reflect the test’s intent. -// For comprehensive guidelines, see: -// * https://mlir.llvm.org/getting_started/TestingGuide/ - // CHECK-LABEL: dxsa.dcl_global_flags // CHECK: dxsa.dcl_input_ps linear v<0, > diff --git a/mlir/test/Target/DXSA/hlsl/shift1.test b/mlir/test/Target/DXSA/hlsl/shift1.test index 80bcfeff5634..a91b55621b9c 100644 --- a/mlir/test/Target/DXSA/hlsl/shift1.test +++ b/mlir/test/Target/DXSA/hlsl/shift1.test @@ -1,13 +1,6 @@ -// RUN: mlir-translate --import-dxsa-bin %S/inputs/shift1.bin | FileCheck %s +// RUN: mlir-translate --import-dxsa-bin %S/inputs/shift1.shex | FileCheck %s // NOTE: Assertions have been autogenerated by utils/generate-test-checks.py -// This script is intended to make adding checks to a test case quick and easy. -// It is *not* authoritative about what constitutes a good test. After using the -// script, be sure to review and refine the generated checks. For example, -// CHECK lines should be minimized and named to reflect the test’s intent. -// For comprehensive guidelines, see: -// * https://mlir.llvm.org/getting_started/TestingGuide/ - // CHECK-LABEL: dxsa.dcl_global_flags // CHECK: dxsa.dcl_input_ps constant v<0, > diff --git a/mlir/test/Target/DXSA/hlsl/sincos.test b/mlir/test/Target/DXSA/hlsl/sincos.test index 6b27752e0579..3489db595ad3 100644 --- a/mlir/test/Target/DXSA/hlsl/sincos.test +++ b/mlir/test/Target/DXSA/hlsl/sincos.test @@ -1,13 +1,6 @@ -// RUN: mlir-translate --import-dxsa-bin %S/inputs/sincos.bin | FileCheck %s +// RUN: mlir-translate --import-dxsa-bin %S/inputs/sincos.shex | FileCheck %s // NOTE: Assertions have been autogenerated by utils/generate-test-checks.py -// This script is intended to make adding checks to a test case quick and easy. -// It is *not* authoritative about what constitutes a good test. After using the -// script, be sure to review and refine the generated checks. For example, -// CHECK lines should be minimized and named to reflect the test’s intent. -// For comprehensive guidelines, see: -// * https://mlir.llvm.org/getting_started/TestingGuide/ - // CHECK-LABEL: dxsa.dcl_global_flags // CHECK: dxsa.dcl_input v<0> diff --git a/mlir/test/Target/DXSA/hlsl/snorm1.test b/mlir/test/Target/DXSA/hlsl/snorm1.test index b5704f41195f..5c782b910919 100644 --- a/mlir/test/Target/DXSA/hlsl/snorm1.test +++ b/mlir/test/Target/DXSA/hlsl/snorm1.test @@ -1,13 +1,6 @@ -// RUN: mlir-translate --import-dxsa-bin %S/inputs/snorm1.bin | FileCheck %s +// RUN: mlir-translate --import-dxsa-bin %S/inputs/snorm1.shex | FileCheck %s // NOTE: Assertions have been autogenerated by utils/generate-test-checks.py -// This script is intended to make adding checks to a test case quick and easy. -// It is *not* authoritative about what constitutes a good test. After using the -// script, be sure to review and refine the generated checks. For example, -// CHECK lines should be minimized and named to reflect the test’s intent. -// For comprehensive guidelines, see: -// * https://mlir.llvm.org/getting_started/TestingGuide/ - // CHECK-LABEL: dxsa.dcl_global_flags // CHECK: dxsa.dcl_sampler diff --git a/mlir/test/Target/DXSA/hlsl/srv_ms_load1.test b/mlir/test/Target/DXSA/hlsl/srv_ms_load1.test index 061f0fb1a1af..f9444868484e 100644 --- a/mlir/test/Target/DXSA/hlsl/srv_ms_load1.test +++ b/mlir/test/Target/DXSA/hlsl/srv_ms_load1.test @@ -1,13 +1,6 @@ -// RUN: mlir-translate --import-dxsa-bin %S/inputs/srv_ms_load1.bin | FileCheck %s +// RUN: mlir-translate --import-dxsa-bin %S/inputs/srv_ms_load1.shex | FileCheck %s // NOTE: Assertions have been autogenerated by utils/generate-test-checks.py -// This script is intended to make adding checks to a test case quick and easy. -// It is *not* authoritative about what constitutes a good test. After using the -// script, be sure to review and refine the generated checks. For example, -// CHECK lines should be minimized and named to reflect the test’s intent. -// For comprehensive guidelines, see: -// * https://mlir.llvm.org/getting_started/TestingGuide/ - // CHECK-LABEL: dxsa.dcl_global_flags // CHECK: dxsa.unknown diff --git a/mlir/test/Target/DXSA/hlsl/srv_typed_load1.test b/mlir/test/Target/DXSA/hlsl/srv_typed_load1.test index accb67047544..5621621dcdbb 100644 --- a/mlir/test/Target/DXSA/hlsl/srv_typed_load1.test +++ b/mlir/test/Target/DXSA/hlsl/srv_typed_load1.test @@ -1,13 +1,6 @@ -// RUN: mlir-translate --import-dxsa-bin %S/inputs/srv_typed_load1.bin | FileCheck %s +// RUN: mlir-translate --import-dxsa-bin %S/inputs/srv_typed_load1.shex | FileCheck %s // NOTE: Assertions have been autogenerated by utils/generate-test-checks.py -// This script is intended to make adding checks to a test case quick and easy. -// It is *not* authoritative about what constitutes a good test. After using the -// script, be sure to review and refine the generated checks. For example, -// CHECK lines should be minimized and named to reflect the test’s intent. -// For comprehensive guidelines, see: -// * https://mlir.llvm.org/getting_started/TestingGuide/ - // CHECK-LABEL: dxsa.dcl_global_flags // CHECK: dxsa.dcl_resource , , diff --git a/mlir/test/Target/DXSA/hlsl/srv_typed_load2.test b/mlir/test/Target/DXSA/hlsl/srv_typed_load2.test index eed1cabbc9aa..2c97440b7978 100644 --- a/mlir/test/Target/DXSA/hlsl/srv_typed_load2.test +++ b/mlir/test/Target/DXSA/hlsl/srv_typed_load2.test @@ -1,13 +1,6 @@ -// RUN: mlir-translate --import-dxsa-bin %S/inputs/srv_typed_load2.bin | FileCheck %s +// RUN: mlir-translate --import-dxsa-bin %S/inputs/srv_typed_load2.shex | FileCheck %s // NOTE: Assertions have been autogenerated by utils/generate-test-checks.py -// This script is intended to make adding checks to a test case quick and easy. -// It is *not* authoritative about what constitutes a good test. After using the -// script, be sure to review and refine the generated checks. For example, -// CHECK lines should be minimized and named to reflect the test’s intent. -// For comprehensive guidelines, see: -// * https://mlir.llvm.org/getting_started/TestingGuide/ - // CHECK-LABEL: dxsa.dcl_global_flags // CHECK: dxsa.dcl_resource , , diff --git a/mlir/test/Target/DXSA/hlsl/struct_buf1.test b/mlir/test/Target/DXSA/hlsl/struct_buf1.test index ffa897cdb829..e7fe0ccafcd6 100644 --- a/mlir/test/Target/DXSA/hlsl/struct_buf1.test +++ b/mlir/test/Target/DXSA/hlsl/struct_buf1.test @@ -1,13 +1,6 @@ -// RUN: mlir-translate --import-dxsa-bin %S/inputs/struct_buf1.bin | FileCheck %s +// RUN: mlir-translate --import-dxsa-bin %S/inputs/struct_buf1.shex | FileCheck %s // NOTE: Assertions have been autogenerated by utils/generate-test-checks.py -// This script is intended to make adding checks to a test case quick and easy. -// It is *not* authoritative about what constitutes a good test. After using the -// script, be sure to review and refine the generated checks. For example, -// CHECK lines should be minimized and named to reflect the test’s intent. -// For comprehensive guidelines, see: -// * https://mlir.llvm.org/getting_started/TestingGuide/ - // CHECK-LABEL: dxsa.dcl_global_flags // CHECK: dxsa.dcl_resource_structured diff --git a/mlir/test/Target/DXSA/hlsl/sub1.test b/mlir/test/Target/DXSA/hlsl/sub1.test index 1b0c1883c21f..e96a3b87b931 100644 --- a/mlir/test/Target/DXSA/hlsl/sub1.test +++ b/mlir/test/Target/DXSA/hlsl/sub1.test @@ -1,13 +1,6 @@ -// RUN: mlir-translate --import-dxsa-bin %S/inputs/sub1.bin | FileCheck %s +// RUN: mlir-translate --import-dxsa-bin %S/inputs/sub1.shex | FileCheck %s // NOTE: Assertions have been autogenerated by utils/generate-test-checks.py -// This script is intended to make adding checks to a test case quick and easy. -// It is *not* authoritative about what constitutes a good test. After using the -// script, be sure to review and refine the generated checks. For example, -// CHECK lines should be minimized and named to reflect the test’s intent. -// For comprehensive guidelines, see: -// * https://mlir.llvm.org/getting_started/TestingGuide/ - // CHECK-LABEL: dxsa.dcl_global_flags // CHECK: dxsa.dcl_constant_buffer , diff --git a/mlir/test/Target/DXSA/hlsl/switch1.test b/mlir/test/Target/DXSA/hlsl/switch1.test index cad60a375c13..e77032402536 100644 --- a/mlir/test/Target/DXSA/hlsl/switch1.test +++ b/mlir/test/Target/DXSA/hlsl/switch1.test @@ -1,13 +1,6 @@ -// RUN: mlir-translate --import-dxsa-bin %S/inputs/switch1.bin | FileCheck %s +// RUN: mlir-translate --import-dxsa-bin %S/inputs/switch1.shex | FileCheck %s // NOTE: Assertions have been autogenerated by utils/generate-test-checks.py -// This script is intended to make adding checks to a test case quick and easy. -// It is *not* authoritative about what constitutes a good test. After using the -// script, be sure to review and refine the generated checks. For example, -// CHECK lines should be minimized and named to reflect the test’s intent. -// For comprehensive guidelines, see: -// * https://mlir.llvm.org/getting_started/TestingGuide/ - // CHECK-LABEL: dxsa.dcl_global_flags // CHECK: dxsa.dcl_input_ps linear v<0, > diff --git a/mlir/test/Target/DXSA/hlsl/switch2.test b/mlir/test/Target/DXSA/hlsl/switch2.test index 1ee74063cc18..440ec3da9df4 100644 --- a/mlir/test/Target/DXSA/hlsl/switch2.test +++ b/mlir/test/Target/DXSA/hlsl/switch2.test @@ -1,13 +1,6 @@ -// RUN: mlir-translate --import-dxsa-bin %S/inputs/switch2.bin | FileCheck %s +// RUN: mlir-translate --import-dxsa-bin %S/inputs/switch2.shex | FileCheck %s // NOTE: Assertions have been autogenerated by utils/generate-test-checks.py -// This script is intended to make adding checks to a test case quick and easy. -// It is *not* authoritative about what constitutes a good test. After using the -// script, be sure to review and refine the generated checks. For example, -// CHECK lines should be minimized and named to reflect the test’s intent. -// For comprehensive guidelines, see: -// * https://mlir.llvm.org/getting_started/TestingGuide/ - // CHECK-LABEL: dxsa.dcl_global_flags // CHECK: dxsa.dcl_input_ps linear v<0, > diff --git a/mlir/test/Target/DXSA/hlsl/switch3.test b/mlir/test/Target/DXSA/hlsl/switch3.test index 671a30018e8b..9215a3517b7b 100644 --- a/mlir/test/Target/DXSA/hlsl/switch3.test +++ b/mlir/test/Target/DXSA/hlsl/switch3.test @@ -1,13 +1,6 @@ -// RUN: mlir-translate --import-dxsa-bin %S/inputs/switch3.bin | FileCheck %s +// RUN: mlir-translate --import-dxsa-bin %S/inputs/switch3.shex | FileCheck %s // NOTE: Assertions have been autogenerated by utils/generate-test-checks.py -// This script is intended to make adding checks to a test case quick and easy. -// It is *not* authoritative about what constitutes a good test. After using the -// script, be sure to review and refine the generated checks. For example, -// CHECK lines should be minimized and named to reflect the test’s intent. -// For comprehensive guidelines, see: -// * https://mlir.llvm.org/getting_started/TestingGuide/ - // CHECK-LABEL: dxsa.dcl_global_flags // CHECK: dxsa.dcl_input_ps linear v<0, > diff --git a/mlir/test/Target/DXSA/hlsl/swizzle1.test b/mlir/test/Target/DXSA/hlsl/swizzle1.test index 5b821f16c2c6..04b4be354f42 100644 --- a/mlir/test/Target/DXSA/hlsl/swizzle1.test +++ b/mlir/test/Target/DXSA/hlsl/swizzle1.test @@ -1,13 +1,6 @@ -// RUN: mlir-translate --import-dxsa-bin %S/inputs/swizzle1.bin | FileCheck %s +// RUN: mlir-translate --import-dxsa-bin %S/inputs/swizzle1.shex | FileCheck %s // NOTE: Assertions have been autogenerated by utils/generate-test-checks.py -// This script is intended to make adding checks to a test case quick and easy. -// It is *not* authoritative about what constitutes a good test. After using the -// script, be sure to review and refine the generated checks. For example, -// CHECK lines should be minimized and named to reflect the test’s intent. -// For comprehensive guidelines, see: -// * https://mlir.llvm.org/getting_started/TestingGuide/ - // CHECK-LABEL: dxsa.dcl_global_flags // CHECK: dxsa.dcl_input_ps linear v<0, > diff --git a/mlir/test/Target/DXSA/hlsl/temp1.test b/mlir/test/Target/DXSA/hlsl/temp1.test index a44d25042e1f..03c3d8ddd830 100644 --- a/mlir/test/Target/DXSA/hlsl/temp1.test +++ b/mlir/test/Target/DXSA/hlsl/temp1.test @@ -1,13 +1,6 @@ -// RUN: mlir-translate --import-dxsa-bin %S/inputs/temp1.bin | FileCheck %s +// RUN: mlir-translate --import-dxsa-bin %S/inputs/temp1.shex | FileCheck %s // NOTE: Assertions have been autogenerated by utils/generate-test-checks.py -// This script is intended to make adding checks to a test case quick and easy. -// It is *not* authoritative about what constitutes a good test. After using the -// script, be sure to review and refine the generated checks. For example, -// CHECK lines should be minimized and named to reflect the test’s intent. -// For comprehensive guidelines, see: -// * https://mlir.llvm.org/getting_started/TestingGuide/ - // CHECK-LABEL: dxsa.dcl_global_flags // CHECK: dxsa.dcl_input_ps linear v<0> diff --git a/mlir/test/Target/DXSA/hlsl/temp2.test b/mlir/test/Target/DXSA/hlsl/temp2.test index 8c77330a4d1f..fbe2fd8c935d 100644 --- a/mlir/test/Target/DXSA/hlsl/temp2.test +++ b/mlir/test/Target/DXSA/hlsl/temp2.test @@ -1,13 +1,6 @@ -// RUN: mlir-translate --import-dxsa-bin %S/inputs/temp2.bin | FileCheck %s +// RUN: mlir-translate --import-dxsa-bin %S/inputs/temp2.shex | FileCheck %s // NOTE: Assertions have been autogenerated by utils/generate-test-checks.py -// This script is intended to make adding checks to a test case quick and easy. -// It is *not* authoritative about what constitutes a good test. After using the -// script, be sure to review and refine the generated checks. For example, -// CHECK lines should be minimized and named to reflect the test’s intent. -// For comprehensive guidelines, see: -// * https://mlir.llvm.org/getting_started/TestingGuide/ - // CHECK-LABEL: dxsa.dcl_global_flags // CHECK: dxsa.dcl_input_ps constant v<0> diff --git a/mlir/test/Target/DXSA/hlsl/uav_counter_dec.test b/mlir/test/Target/DXSA/hlsl/uav_counter_dec.test index ccd042841d5f..139bab0a43da 100644 --- a/mlir/test/Target/DXSA/hlsl/uav_counter_dec.test +++ b/mlir/test/Target/DXSA/hlsl/uav_counter_dec.test @@ -1,13 +1,6 @@ -// RUN: mlir-translate --import-dxsa-bin %S/inputs/uav_counter_dec.bin | FileCheck %s +// RUN: mlir-translate --import-dxsa-bin %S/inputs/uav_counter_dec.shex | FileCheck %s // NOTE: Assertions have been autogenerated by utils/generate-test-checks.py -// This script is intended to make adding checks to a test case quick and easy. -// It is *not* authoritative about what constitutes a good test. After using the -// script, be sure to review and refine the generated checks. For example, -// CHECK lines should be minimized and named to reflect the test’s intent. -// For comprehensive guidelines, see: -// * https://mlir.llvm.org/getting_started/TestingGuide/ - // CHECK-LABEL: dxsa.dcl_global_flags // CHECK: dxsa.dcl_uav_structured , diff --git a/mlir/test/Target/DXSA/hlsl/uav_counter_inc.test b/mlir/test/Target/DXSA/hlsl/uav_counter_inc.test index fdcc29efbc6e..7b70fbe19e03 100644 --- a/mlir/test/Target/DXSA/hlsl/uav_counter_inc.test +++ b/mlir/test/Target/DXSA/hlsl/uav_counter_inc.test @@ -1,13 +1,6 @@ -// RUN: mlir-translate --import-dxsa-bin %S/inputs/uav_counter_inc.bin | FileCheck %s +// RUN: mlir-translate --import-dxsa-bin %S/inputs/uav_counter_inc.shex | FileCheck %s // NOTE: Assertions have been autogenerated by utils/generate-test-checks.py -// This script is intended to make adding checks to a test case quick and easy. -// It is *not* authoritative about what constitutes a good test. After using the -// script, be sure to review and refine the generated checks. For example, -// CHECK lines should be minimized and named to reflect the test’s intent. -// For comprehensive guidelines, see: -// * https://mlir.llvm.org/getting_started/TestingGuide/ - // CHECK-LABEL: dxsa.dcl_global_flags // CHECK: dxsa.dcl_uav_structured , diff --git a/mlir/test/Target/DXSA/hlsl/uav_raw1.test b/mlir/test/Target/DXSA/hlsl/uav_raw1.test index 69437bbec3a4..90256701cd89 100644 --- a/mlir/test/Target/DXSA/hlsl/uav_raw1.test +++ b/mlir/test/Target/DXSA/hlsl/uav_raw1.test @@ -1,13 +1,6 @@ -// RUN: mlir-translate --import-dxsa-bin %S/inputs/uav_raw1.bin | FileCheck %s +// RUN: mlir-translate --import-dxsa-bin %S/inputs/uav_raw1.shex | FileCheck %s // NOTE: Assertions have been autogenerated by utils/generate-test-checks.py -// This script is intended to make adding checks to a test case quick and easy. -// It is *not* authoritative about what constitutes a good test. After using the -// script, be sure to review and refine the generated checks. For example, -// CHECK lines should be minimized and named to reflect the test’s intent. -// For comprehensive guidelines, see: -// * https://mlir.llvm.org/getting_started/TestingGuide/ - // CHECK-LABEL: dxsa.dcl_global_flags // CHECK: dxsa.dcl_uav_raw diff --git a/mlir/test/Target/DXSA/hlsl/uav_typed_load_store1.test b/mlir/test/Target/DXSA/hlsl/uav_typed_load_store1.test index aa524fbd91f6..b66349001864 100644 --- a/mlir/test/Target/DXSA/hlsl/uav_typed_load_store1.test +++ b/mlir/test/Target/DXSA/hlsl/uav_typed_load_store1.test @@ -1,13 +1,6 @@ -// RUN: mlir-translate --import-dxsa-bin %S/inputs/uav_typed_load_store1.bin | FileCheck %s +// RUN: mlir-translate --import-dxsa-bin %S/inputs/uav_typed_load_store1.shex | FileCheck %s // NOTE: Assertions have been autogenerated by utils/generate-test-checks.py -// This script is intended to make adding checks to a test case quick and easy. -// It is *not* authoritative about what constitutes a good test. After using the -// script, be sure to review and refine the generated checks. For example, -// CHECK lines should be minimized and named to reflect the test’s intent. -// For comprehensive guidelines, see: -// * https://mlir.llvm.org/getting_started/TestingGuide/ - // CHECK-LABEL: dxsa.dcl_global_flags // CHECK: dxsa.dcl_uav_typed , diff --git a/mlir/test/Target/DXSA/hlsl/uav_typed_load_store2.test b/mlir/test/Target/DXSA/hlsl/uav_typed_load_store2.test index ca8800a3dbe4..3a68ac55c9cc 100644 --- a/mlir/test/Target/DXSA/hlsl/uav_typed_load_store2.test +++ b/mlir/test/Target/DXSA/hlsl/uav_typed_load_store2.test @@ -1,13 +1,6 @@ -// RUN: mlir-translate --import-dxsa-bin %S/inputs/uav_typed_load_store2.bin | FileCheck %s +// RUN: mlir-translate --import-dxsa-bin %S/inputs/uav_typed_load_store2.shex | FileCheck %s // NOTE: Assertions have been autogenerated by utils/generate-test-checks.py -// This script is intended to make adding checks to a test case quick and easy. -// It is *not* authoritative about what constitutes a good test. After using the -// script, be sure to review and refine the generated checks. For example, -// CHECK lines should be minimized and named to reflect the test’s intent. -// For comprehensive guidelines, see: -// * https://mlir.llvm.org/getting_started/TestingGuide/ - // CHECK-LABEL: dxsa.dcl_global_flags // CHECK: dxsa.dcl_uav_typed , diff --git a/mlir/test/Target/DXSA/hlsl/ubfeu16.test b/mlir/test/Target/DXSA/hlsl/ubfeu16.test index 49a583f4e55e..0edd46526d0a 100644 --- a/mlir/test/Target/DXSA/hlsl/ubfeu16.test +++ b/mlir/test/Target/DXSA/hlsl/ubfeu16.test @@ -1,13 +1,6 @@ -// RUN: mlir-translate --import-dxsa-bin %S/inputs/ubfeu16.bin | FileCheck %s +// RUN: mlir-translate --import-dxsa-bin %S/inputs/ubfeu16.shex | FileCheck %s // NOTE: Assertions have been autogenerated by utils/generate-test-checks.py -// This script is intended to make adding checks to a test case quick and easy. -// It is *not* authoritative about what constitutes a good test. After using the -// script, be sure to review and refine the generated checks. For example, -// CHECK lines should be minimized and named to reflect the test’s intent. -// For comprehensive guidelines, see: -// * https://mlir.llvm.org/getting_started/TestingGuide/ - // CHECK-LABEL: dxsa.dcl_global_flags // CHECK: dxsa.dcl_constant_buffer ,