diff --git a/mlir/include/mlir/Dialect/DXSA/IR/DXSAMoveOps.td b/mlir/include/mlir/Dialect/DXSA/IR/DXSAMoveOps.td new file mode 100644 index 000000000000..061a16628a13 --- /dev/null +++ b/mlir/include/mlir/Dialect/DXSA/IR/DXSAMoveOps.td @@ -0,0 +1,207 @@ +//===- DXSAMoveOps.td - DXSA move ops --------------------*- tablegen -*-===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// +// +// Move instructions of the DXSA dialect. +// +//===----------------------------------------------------------------------===// + +#ifndef MLIR_DIALECT_DXSA_IR_DXSAMOVEOPS +#define MLIR_DIALECT_DXSA_IR_DXSAMOVEOPS + +include "mlir/Dialect/DXSA/IR/DXSAOpBase.td" + +//===----------------------------------------------------------------------===// +// dxsa.mov +//===----------------------------------------------------------------------===// + +def DXSA_Mov : DXSA_UnaryOp<"mov"> { + let summary = "component-wise move"; + let description = [{ + The `dxsa.mov` operation copies each component of `$src` to `$dst`. + Source modifiers other than swizzle assume floating-point data; without + modifiers the bits are copied unaltered. + + Example: + + ```mlir + dxsa.mov r<0>, r<1> + dxsa.mov r<0>, -|r<1>| + dxsa.mov r<0, >, r<1, > + ``` + }]; +} + +//===----------------------------------------------------------------------===// +// dxsa.mov_sat +//===----------------------------------------------------------------------===// + +def DXSA_MovSat : DXSA_UnaryOp<"mov_sat"> { + let summary = "component-wise move, saturated to [0, 1]"; + let description = [{ + The `dxsa.mov_sat` operation copies each component of `$src`, clamps the + result to `[0.0, 1.0]`, and writes it to `$dst`. + + Example: + + ```mlir + dxsa.mov_sat r<0>, r<1> + dxsa.mov_sat r<0>, -|r<1>| + ``` + }]; +} + +//===----------------------------------------------------------------------===// +// dxsa.dmov +//===----------------------------------------------------------------------===// + +def DXSA_DMov : DXSA_UnaryOp<"dmov"> { + let summary = "component-wise double-precision move"; + let description = [{ + The `dxsa.dmov` operation copies each double-precision component of + `$src` to `$dst`. Source modifiers other than swizzle assume + floating-point data; without modifiers the bits are copied unaltered. + + The source encodes double values as component pairs: (x,y) holds the + first double (x = low 32 bits, y = high 32 bits) and (z,w) holds the + second. Valid source swizzles are .xyzw, .xyxy, .zwxy, and .zwzw. + Valid destination write masks are .xy, .zw, and .xyzw. + + Example: + + ```mlir + dxsa.dmov r<0>, r<1> + dxsa.dmov r<0, >, r<1, > + ``` + }]; +} + +//===----------------------------------------------------------------------===// +// dxsa.dmov_sat +//===----------------------------------------------------------------------===// + +def DXSA_DMovSat : DXSA_UnaryOp<"dmov_sat"> { + let summary = "component-wise double-precision move, saturated to [0, 1]"; + let description = [{ + The `dxsa.dmov_sat` operation copies each double-precision component of + `$src`, clamps the result to `[0.0, 1.0]`, and writes it to `$dst`. + + Example: + + ```mlir + dxsa.dmov_sat r<0>, r<1> + ``` + }]; +} + +//===----------------------------------------------------------------------===// +// dxsa.dmovc +//===----------------------------------------------------------------------===// + +class DXSA_DMovConditionalOp : DXSA_Op { + let arguments = (ins + DXSA_DstOperandAttr:$dst, + DXSA_SrcOperandAttr:$condition, + DXSA_SrcOperandAttr:$src1, + DXSA_SrcOperandAttr:$src2, + OptionalAttr:$precise); + let results = (outs); + let assemblyFormat = + "(`precise` $precise^)? $dst `,` $condition `,` $src1 `,` $src2 attr-dict"; +} + +def DXSA_DMovC : DXSA_DMovConditionalOp<"dmovc"> { + let summary = "component-wise double-precision conditional move"; + let description = [{ + The `dxsa.dmovc` operation performs a component-wise double-precision + conditional move: + + ``` + $dst = ($condition != 0) ? $src1 : $src2 + ``` + + The first two post-swizzle components of `$condition` are treated as two + independent 32-bit boolean values, one per output double. Doubles are + encoded as component pairs (x = low 32 bits, y = high 32 bits) and + (z = low 32 bits, w = high 32 bits). Valid `$dst` write masks are + `.xy`, `.zw`, and `.xyzw`; valid `$src1`/`$src2` swizzles are `.xyzw`, + `.xyxy`, `.zwxy`, and `.zwzw`. + + Example: + + ```mlir + dxsa.dmovc r<0>, r<1>, r<2>, r<3> + dxsa.dmovc r<0, >, r<1>, r<2, >, r<3> + ``` + }]; +} + +//===----------------------------------------------------------------------===// +// dxsa.dmovc_sat +//===----------------------------------------------------------------------===// + +def DXSA_DMovCSat : DXSA_DMovConditionalOp<"dmovc_sat"> { + let summary = + "component-wise double-precision conditional move, saturated to [0, 1]"; + let description = [{ + The `dxsa.dmovc_sat` operation performs a component-wise double-precision + conditional move, clamps the result to `[0.0, 1.0]`, and writes it to + `$dst`: + + ``` + $dst = clamp(($condition != 0) ? $src1 : $src2, 0.0, 1.0) + ``` + + Example: + + ```mlir + dxsa.dmovc_sat r<0>, r<1>, r<2>, r<3> + ``` + }]; +} + +//===----------------------------------------------------------------------===// +// dxsa.swapc +//===----------------------------------------------------------------------===// + +def DXSA_SwapC : DXSA_Op<"swapc"> { + let summary = "component-wise conditional swap of two values"; + let description = [{ + The `dxsa.swapc` operation performs a component-wise conditional swap of + the values in `$src1` and `$src2`: + + ``` + $dst0 = ($condition != 0) ? $src2 : $src1 + $dst1 = ($condition != 0) ? $src1 : $src2 + ``` + + Both destinations are updated atomically with respect to the source + values, so reading and writing the same register is well-defined. + + Example: + + ```mlir + dxsa.swapc r<0>, r<1>, r<2>, r<3>, r<4> + dxsa.swapc r<0, >, r<1, >, r<2>, r<3>, r<4> + ``` + }]; + + let arguments = (ins + DXSA_DstOperandAttr:$dst0, + DXSA_DstOperandAttr:$dst1, + DXSA_SrcOperandAttr:$condition, + DXSA_SrcOperandAttr:$src1, + DXSA_SrcOperandAttr:$src2, + OptionalAttr:$precise); + let results = (outs); + let assemblyFormat = [{ + (`precise` $precise^)? $dst0 `,` $dst1 `,` $condition `,` $src1 `,` $src2 + attr-dict + }]; +} + +#endif // MLIR_DIALECT_DXSA_IR_DXSAMOVEOPS diff --git a/mlir/include/mlir/Dialect/DXSA/IR/DXSAOps.td b/mlir/include/mlir/Dialect/DXSA/IR/DXSAOps.td index dc72b4f6fc4a..a0ce54dc34f1 100644 --- a/mlir/include/mlir/Dialect/DXSA/IR/DXSAOps.td +++ b/mlir/include/mlir/Dialect/DXSA/IR/DXSAOps.td @@ -13,6 +13,7 @@ include "mlir/Dialect/DXSA/IR/DXSAOpBase.td" include "mlir/Dialect/DXSA/IR/DXSATypes.td" include "mlir/Dialect/DXSA/IR/DXSAFPArithOps.td" include "mlir/Dialect/DXSA/IR/DXSAIntArithOps.td" +include "mlir/Dialect/DXSA/IR/DXSAMoveOps.td" include "mlir/Dialect/DXSA/IR/DXSAConditionOps.td" include "mlir/Dialect/DXSA/IR/DXSABitwiseOps.td" include "mlir/Dialect/DXSA/IR/DXSATypeConversionOps.td" diff --git a/mlir/lib/Target/DXSA/BinaryParser.cpp b/mlir/lib/Target/DXSA/BinaryParser.cpp index 976322f05f8c..44d8a0de628c 100644 --- a/mlir/lib/Target/DXSA/BinaryParser.cpp +++ b/mlir/lib/Target/DXSA/BinaryParser.cpp @@ -2346,6 +2346,15 @@ class Parser { return SATURABLE_OP(Sincos, 2, 1, HasPreciseAttr::Yes); case D3D10_SB_OPCODE_SQRT: return SATURABLE_OP(Sqrt, 1, 1, HasPreciseAttr::Yes); + // Move instructions + case D3D10_SB_OPCODE_MOV: + return SATURABLE_OP(Mov, 1, 1, HasPreciseAttr::Yes); + case D3D11_SB_OPCODE_DMOV: + return SATURABLE_OP(DMov, 1, 1, HasPreciseAttr::Yes); + case D3D11_SB_OPCODE_DMOVC: + return SATURABLE_OP(DMovC, 1, 3, HasPreciseAttr::Yes); + case D3D11_SB_OPCODE_SWAPC: + return PLAIN_OP(SwapC, 2, 3, HasPreciseAttr::Yes); // Type conversion instructions case D3D11_SB_OPCODE_DTOF: return PLAIN_OP(DToF, 1, 1, HasPreciseAttr::Yes); diff --git a/mlir/test/Target/DXSA/inputs/mov-index.bin b/mlir/test/Target/DXSA/inputs/mov-index.bin deleted file mode 100644 index b6aca99f0781..000000000000 Binary files a/mlir/test/Target/DXSA/inputs/mov-index.bin and /dev/null differ diff --git a/mlir/test/Target/DXSA/inputs/mov.bin b/mlir/test/Target/DXSA/inputs/mov.bin deleted file mode 100644 index 06ed19a5e976..000000000000 Binary files a/mlir/test/Target/DXSA/inputs/mov.bin and /dev/null differ diff --git a/mlir/test/Target/DXSA/inputs/mov_index_rel_imm.bin b/mlir/test/Target/DXSA/inputs/mov_index_rel_imm.bin deleted file mode 100644 index 4ae0ee3cdbb2..000000000000 Binary files a/mlir/test/Target/DXSA/inputs/mov_index_rel_imm.bin and /dev/null differ diff --git a/mlir/test/Target/DXSA/mov-index.mlir b/mlir/test/Target/DXSA/mov-index.mlir deleted file mode 100644 index b5695edc0eda..000000000000 --- a/mlir/test/Target/DXSA/mov-index.mlir +++ /dev/null @@ -1,14 +0,0 @@ -// RUN: mlir-translate --import-dxsa-bin %S/inputs/mov-index.bin | FileCheck %s -// RUN: mlir-translate --import-dxsa-bin %S/inputs/mov-index.bin | mlir-opt --verify-roundtrip -// mov o0.xyzw, v[r0.x][0].xyzw - -// CHECK: dxsa.module { -// CHECK-NEXT: %0 = dxsa.index.imm {imm = 0 : i32} -// CHECK-NEXT: %1 = dxsa.operand %0 {mask = 240 : i32, num_components = 4 : i32, type = 2 : i32} -// CHECK-NEXT: %2 = dxsa.index.imm {imm = 0 : i32} -// CHECK-NEXT: %3 = dxsa.operand %2 {num_components = 4 : i32, one = 0 : i32, type = 0 : i32} -// CHECK-NEXT: %4 = dxsa.index.rel %3 -// CHECK-NEXT: %5 = dxsa.index.imm {imm = 0 : i32} -// CHECK-NEXT: %6 = dxsa.operand %4, %5 {num_components = 4 : i32, swizzle = dense<[0, 1, 2, 3]> : vector<4xi32>, type = 1 : i32} -// CHECK-NEXT: dxsa.instruction "mov" %1, %6 -// CHECK-NEXT: } diff --git a/mlir/test/Target/DXSA/mov.mlir b/mlir/test/Target/DXSA/mov.mlir deleted file mode 100644 index cf5d5ef54845..000000000000 --- a/mlir/test/Target/DXSA/mov.mlir +++ /dev/null @@ -1,17 +0,0 @@ -// RUN: mlir-translate --import-dxsa-bin %S/inputs/mov.bin | FileCheck %s -// RUN: mlir-translate --import-dxsa-bin %S/inputs/mov.bin | mlir-opt --verify-roundtrip -// mov r0.x, l(3.000000) - -// CHECK: dxsa.module { -// CHECK-NEXT: %0 = dxsa.index.imm {imm = 0 : i32} -// CHECK-NEXT: %1 = dxsa.operand %0 {mask = 16 : i32, num_components = 4 : i32, type = 0 : i32} -// CHECK-NEXT: %2 = dxsa.operand.imm {imm = dense<1077936128> : vector<1xi32>} -// CHECK-NEXT: dxsa.instruction "mov" %1, %2 -// CHECK-NEXT: } - -module { - %0 = dxsa.index.imm {imm = 0 : i32} - %1 = dxsa.operand %0 {mask = 16 : i32, num_components = 4 : i32, type = 0 : i32} - %2 = dxsa.operand.imm {imm = dense<1077936128> : vector<1xi32>} - dxsa.instruction "mov" %1, %2 -} diff --git a/mlir/test/Target/DXSA/mov_index_rel_imm.mlir b/mlir/test/Target/DXSA/mov_index_rel_imm.mlir deleted file mode 100644 index 108bd8decdbf..000000000000 --- a/mlir/test/Target/DXSA/mov_index_rel_imm.mlir +++ /dev/null @@ -1,13 +0,0 @@ -// RUN: mlir-translate --import-dxsa-bin %S/inputs/mov_index_rel_imm.bin | FileCheck %s -// mov o0.xyzw, v[r0.x + 66][0].xyzw - -// CHECK: module { -// CHECK-NEXT: %0 = dxsa.index.imm {imm = 0 : i32} -// CHECK-NEXT: %1 = dxsa.operand %0 {mask = 240 : i32, num_components = 4 : i32, type = 2 : i32} -// CHECK-NEXT: %2 = dxsa.index.imm {imm = 0 : i32} -// CHECK-NEXT: %3 = dxsa.operand %2 {num_components = 4 : i32, one = 0 : i32, type = 0 : i32} -// CHECK-NEXT: %4 = dxsa.index.rel.imm %3 {imm = 66 : i32, op = "add"} -// CHECK-NEXT: %5 = dxsa.index.imm {imm = 0 : i32} -// CHECK-NEXT: %6 = dxsa.operand %4, %5 {num_components = 4 : i32, swizzle = dense<[0, 1, 2, 3]> : vector<4xi32>, type = 1 : i32} -// CHECK-NEXT: dxsa.instruction "mov" %1, %6 -// CHECK-NEXT: } diff --git a/mlir/test/Target/DXSA/mov_ops.test b/mlir/test/Target/DXSA/mov_ops.test new file mode 100644 index 000000000000..9ff0485e66d6 --- /dev/null +++ b/mlir/test/Target/DXSA/mov_ops.test @@ -0,0 +1,105 @@ +// RUN: mlir-translate --split-input-file --import-dxsa-hex %s | FileCheck %s +// RUN: mlir-translate --split-input-file --import-dxsa-hex %s | mlir-opt --split-input-file --verify-roundtrip + +// CHECK-LABEL: dxsa.module { +// CHECK-NEXT: dxsa.mov r<0, >, -|r<1, >| +// CHECK-NEXT: } +0x06000036, 0x00100012, 0x00000000, 0x80100796, 0x000000c1, 0x00000001 + +// ----- + +// CHECK-LABEL: dxsa.module { +// CHECK-NEXT: dxsa.mov precise r<0>, r<1> +// CHECK-NEXT: } +0x05180036, 0x001000f2, 0x00000000, 0x00100e46, 0x00000001 + +// ----- + +// CHECK-LABEL: dxsa.module { +// CHECK-NEXT: dxsa.mov_sat r<0, >, -|r<1, >| +// CHECK-NEXT: } +0x06002036, 0x00100012, 0x00000000, 0x80100796, 0x000000c1, 0x00000001 + +// ----- + +// CHECK-LABEL: dxsa.module { +// CHECK-NEXT: dxsa.mov_sat precise r<0>, r<1> +// CHECK-NEXT: } +0x05182036, 0x001000f2, 0x00000000, 0x00100e46, 0x00000001 + +// ----- + +// CHECK-LABEL: dxsa.module { +// CHECK-NEXT: dxsa.dmov r<0, >, -|r<1, >| +// CHECK-NEXT: } +0x060000c7, 0x00100032, 0x00000000, 0x801004e6, 0x000000c1, 0x00000001 + +// ----- + +// CHECK-LABEL: dxsa.module { +// CHECK-NEXT: dxsa.dmov precise r<0, >, r<1> +// CHECK-NEXT: } +0x051800c7, 0x00100032, 0x00000000, 0x00100e46, 0x00000001 + +// ----- + +// CHECK-LABEL: dxsa.module { +// CHECK-NEXT: dxsa.dmov_sat r<0, >, -|r<1, >| +// CHECK-NEXT: } +0x060020c7, 0x00100032, 0x00000000, 0x801004e6, 0x000000c1, 0x00000001 + +// ----- + +// CHECK-LABEL: dxsa.module { +// CHECK-NEXT: dxsa.dmov_sat precise r<0, >, r<1> +// CHECK-NEXT: } +0x051820c7, 0x00100032, 0x00000000, 0x00100e46, 0x00000001 + +// ----- + +// CHECK-LABEL: dxsa.module { +// CHECK-NEXT: dxsa.dmovc r<0>, r<1>, r<2>, r<3> +// CHECK-NEXT: } +0x090000c8, 0x001000f2, 0x00000000, 0x00100e46, 0x00000001, 0x00100e46, 0x00000002, 0x00100e46, 0x00000003 + +// ----- + +// CHECK-LABEL: dxsa.module { +// CHECK-NEXT: dxsa.dmovc_sat r<0, >, r<1>, -|r<2, >|, r<3> +// CHECK-NEXT: } +0x0a0020c8, 0x00100032, 0x00000000, 0x00100e46, 0x00000001, 0x801004e6, 0x000000c1, 0x00000002, 0x00100e46, 0x00000003 + +// ----- + +// CHECK-LABEL: dxsa.module { +// CHECK-NEXT: dxsa.dmovc precise r<0>, r<1>, r<2>, r<3> +// CHECK-NEXT: } +0x097800c8, 0x001000f2, 0x00000000, 0x00100e46, 0x00000001, 0x00100e46, 0x00000002, 0x00100e46, 0x00000003 + +// ----- + +// CHECK-LABEL: dxsa.module { +// CHECK-NEXT: dxsa.dmovc_sat precise r<0>, r<1>, r<2>, r<3> +// CHECK-NEXT: } +0x091820c8, 0x001000f2, 0x00000000, 0x00100e46, 0x00000001, 0x00100e46, 0x00000002, 0x00100e46, 0x00000003 + +// ----- + +// CHECK-LABEL: dxsa.module { +// CHECK-NEXT: dxsa.swapc r<0>, r<1>, r<2>, r<3>, r<4> +// CHECK-NEXT: } +0x0b00008e, 0x001000f2, 0x00000000, 0x001000f2, 0x00000001, 0x00100e46, 0x00000002, 0x00100e46, 0x00000003, 0x00100e46, 0x00000004 + +// ----- + +// CHECK-LABEL: dxsa.module { +// CHECK-NEXT: dxsa.swapc r<0, >, r<1, >, r<2>, -r<3>, |r<4>| +// CHECK-NEXT: } +0x0d00008e, 0x00100032, 0x00000000, 0x001000c2, 0x00000001, 0x00100e46, 0x00000002, 0x80100e46, 0x00000041, 0x00000003, 0x80100e46, 0x00000081, 0x00000004 + +// ----- + +// CHECK-LABEL: dxsa.module { +// CHECK-NEXT: dxsa.swapc precise r<0>, r<1>, r<2>, r<3>, r<4> +// CHECK-NEXT: } +0x0b78008e, 0x001000f2, 0x00000000, 0x001000f2, 0x00000001, 0x00100e46, 0x00000002, 0x00100e46, 0x00000003, 0x00100e46, 0x00000004