diff --git a/Documentation/platforms/arm/imxrt/boards/imxrt1180-evk/MIMXRT1180-EVK-TOP-IMG.jpg b/Documentation/platforms/arm/imxrt/boards/imxrt1180-evk/MIMXRT1180-EVK-TOP-IMG.jpg new file mode 100644 index 0000000000000..1a1e5fd1506d8 Binary files /dev/null and b/Documentation/platforms/arm/imxrt/boards/imxrt1180-evk/MIMXRT1180-EVK-TOP-IMG.jpg differ diff --git a/Documentation/platforms/arm/imxrt/boards/imxrt1180-evk/index.rst b/Documentation/platforms/arm/imxrt/boards/imxrt1180-evk/index.rst new file mode 100644 index 0000000000000..cc25288300994 --- /dev/null +++ b/Documentation/platforms/arm/imxrt/boards/imxrt1180-evk/index.rst @@ -0,0 +1,261 @@ +================ +i.MX RT1180 EVK +================ + +.. tags:: arch:arm, arch:armv7m, arch:armv8m, arch:cm7, arch:cm33, chip:imxrt, chip:imxrt1180, vendor:nxp, ethernet, usb + +The `i.MX RT1180 EVK +`_ +is an evaluation kit from NXP. It is based on the MIMXRT1189 crossover +microcontroller, which combines Arm Cortex-M33 and Cortex-M7 cores. +See the `MIMXRT1180-EVK Quick Start Guide +`_ for +an overview of the board and its connectors. + +.. figure:: https://www.nxp.com/assets/images/en/dev-board-image/MIMXRT1180-EVK-TOP-IMG.jpg + :align: center + :alt: Top view of the i.MX RT1180 EVK + :width: 80% + + i.MX RT1180 EVK top view. Image source: NXP. + +Features +======== + +- MIMXRT1189CVM8C microcontroller + - Cortex-M33 running at 266 MHz with NuttX + - Cortex-M7 running at 798 MHz with NuttX +- Memory + - On-chip TCM and OCRAM + - 512-Mbit external SDRAM + - 128-Mbit FlexSPI1 QSPI NOR flash + - 512-Mbit HyperRAM + - MicroSD card socket +- Connectivity and expansion + - MCU-Link debug interface with a virtual COM port + - 20-pin external JTAG/SWD connector + - Ethernet connectors + - USB host and device connectors + - CAN connector + - Arduino-compatible expansion headers +- Audio codec, microphone, headphone jack, and speaker connections +- Two software-controlled user LEDs + +The current NuttX configurations provide the serial console, USB device +support, image generation, and multicore boot flow. The other on-board +interfaces listed above are not enabled by the supplied configurations. + +Buttons and LEDs +================ + +The board port configures the following user LEDs during early +initialization: + +=== ===== ========== ========= +LED Color Signal GPIO +=== ===== ========== ========= +D6 Green GPIO_AD_27 RGPIO4.27 +D7 Red GPIO_AD_26 RGPIO4.26 +=== ===== ========== ========= + +D7 is turned on during board initialization. The supplied configurations do +not enable the NuttX automatic LED or user-button interfaces. + +Serial Console +============== + +The default serial console is LPUART1 through the MCU-Link virtual COM port: + +============ ============ ============= +Function Signal Pad +============ ============ ============= +Console TX LPUART1_TX GPIO_AON_08 +Console RX LPUART1_RX GPIO_AON_09 +============ ============ ============= + +Connect the host to the MCU-Link USB connector J53. On Linux, the console is +normally available as ``/dev/ttyACM0``. + +Pin Mapping +=========== + +The board port currently defines these on-board connections: + +============ ============= ============================== +Pad Function Board connection +============ ============= ============================== +GPIO_AON_04 LPSPI1_SCK On-board LPSPI NOR flash +GPIO_AON_05 LPSPI1_PCS0 On-board LPSPI NOR flash +GPIO_AON_06 LPSPI1_SDO On-board LPSPI NOR flash +GPIO_AON_07 LPSPI1_SDI On-board LPSPI NOR flash +GPIO_AON_08 LPUART1_TX MCU-Link virtual COM port +GPIO_AON_09 LPUART1_RX MCU-Link virtual COM port +GPIO_AON_15 LPI2C2_SDA On-board peripherals +GPIO_AON_16 LPI2C2_SCL On-board peripherals +GPIO_AD_26 GPIO4_IO26 Red user LED D7 +GPIO_AD_27 GPIO4_IO27 Green user LED D6 +============ ============= ============================== + +Consult the MIMXRT1180-EVK user manual (UM12021) and schematic, available from +the NXP product page linked above, for the complete expansion-header pinout and +any signal-sharing restrictions. + +Power Supply +============ + +The board requires a 5 V supply. It can be powered from the external 5 V input +J2, or from a supported USB connector when the power-selection jumpers are +configured accordingly. Use SW1 to turn the board on. Refer to the board user +manual before changing the factory jumper settings or powering the board from +more than one source. + +Installation +============ + +All testing has been conducted using the following Arm GNU Toolchain for the +``arm-none-eabi`` target, available from the `Arm GNU Toolchain downloads page +`_: + +.. code-block:: console + + $ arm-none-eabi-gcc --version + arm-none-eabi-gcc (Arm GNU Toolchain 13.2.rel1 (Build arm-13.7)) 13.2.1 20231009 + +Building a Cortex-M33 image also requires ``python3`` with the ``venv`` +module, ``pip``, and either ``curl`` or ``wget``. The image-building helper +creates a private Python environment and installs the pinned NXP SPSDK +version automatically. + +Flashing requires the `SEGGER J-Link Software and Documentation Pack +`_ version 7.98a or later, one of: + +- a SEGGER J-Link probe connected to the 20-pin JTAG/SWD connector J37; or +- the on-board MCU-Link probe, reflashed with SEGGER MCU-Link J-Link firmware + and connected through J53, + +and the boot-mode DIP switch SW5 set to ``0100`` (FlexSPI Quad SPI NOR boot). + +Building NuttX +============== + +Select a configuration and build it from the NuttX repository root: + +.. code:: console + + $ ./tools/configure.sh imxrt1180-evk: + $ make -j$(nproc) + +The first Cortex-M33 build downloads the pinned NXP EdgeLock Enclave (ELE) +firmware after displaying its license and installs SPSDK into +``tools/imxrt1180/.cache``. Running the build implies acceptance of the NXP +firmware license described in `License Exceptions`_. + +Flash Layout +============ + +The Cortex-M33 image is the bootable image. It contains the FlexSPI +Configuration Block (FCB) at offset ``0x400`` and the AHAB container at offset +``0x1000``. The Cortex-M7 image is programmed separately as a raw XIP payload. + +========== ======== ====== ============================== +Address Offset Size Contents +========== ======== ====== ============================== +0x28000000 0x0 512 KB Cortex-M33 image, ``flash.bin`` +0x28080000 0x80000 Rest Cortex-M7 image, ``nuttx.bin`` +========== ======== ====== ============================== + +Flashing +======== + +Set the boot-mode DIP switch SW5 to ``0100`` for FlexSPI Quad SPI NOR boot. +The ``flash-jlink.sh`` helper takes an image name and either a flash offset or +an absolute address. + +The helper programs through the Cortex-M33 device profile because the RT1180 +ROM starts the Cortex-M33 first and initializes FlexSPI1 before the SEGGER +flash loader runs. Always use the supplied helper for programming. The +Cortex-M7 J-Link device profile is intended for debugging the running +Cortex-M7 image, not for programming. + +To flash a standalone Cortex-M33 NSH image: + +.. code:: console + + $ ./tools/configure.sh imxrt1180-evk:nsh-m33 + $ make -j$(nproc) + $ boards/arm/imxrt/imxrt1180-evk/tools/flash-jlink.sh flash.bin 0x0 + +To flash the Cortex-M33 bootloader and Cortex-M7 NSH images: + +.. code:: console + + $ ./tools/configure.sh imxrt1180-evk:bl + $ make -j$(nproc) + $ cp flash.bin flash-bl.bin + $ make distclean + $ ./tools/configure.sh imxrt1180-evk:nsh + $ make -j$(nproc) + $ cp nuttx.bin nuttx-m7.bin + $ boards/arm/imxrt/imxrt1180-evk/tools/flash-jlink.sh flash-bl.bin 0x0 + $ boards/arm/imxrt/imxrt1180-evk/tools/flash-jlink.sh nuttx-m7.bin 0x80000 + +J-Link Debugging +================ + +The board port also supplies a J-Link GDB server helper for Cortex-M7: + +.. code:: console + + $ boards/arm/imxrt/imxrt1180-evk/tools/gdbserver-jlink.sh + +Connect from another terminal: + +.. code:: console + + $ arm-none-eabi-gdb nuttx + (gdb) target extended-remote localhost:2331 + (gdb) monitor reset + (gdb) continue + +Configurations +============== + +The board identifier for use with ``tools/configure.sh`` is +``imxrt1180-evk``. + +nsh-m33 +------- + +Runs NuttShell (NSH) directly on the Cortex-M33. The RT1180 ROM boots +``flash.bin`` from FlexSPI1 QSPI NOR. NSH is available on LPUART1 at +the MCU-Link virtual COM port. This configuration also enables USB CDC/ACM +and the ``ostest`` application. + +bl +-- + +Builds a minimal Cortex-M33 bootloader as ``flash.bin``. It sets the +Cortex-M7 boot address to ``0x28080000``, releases that core, and then remains +in an indefinite loop that periodically calls ``usleep``. Use this +configuration together with ``nsh``; it does not provide an interactive shell +itself. + +nsh +--- + +Runs NSH on the Cortex-M7. The output ``nuttx.bin`` is a raw XIP payload that +must be programmed at offset ``0x80000`` and started by the ``bl`` +configuration. NSH is available on LPUART1 at the MCU-Link virtual COM port. +This configuration also enables USB CDC/ACM and the ``ostest`` application. + +License Exceptions +================== + +The Cortex-M33 image build downloads +``mxrt1180b0-ahab-container.img`` from NXP's MCUXpresso SDK at a pinned commit. +This proprietary EdgeLock Enclave firmware is covered by the LA_OPT NXP +Software License, version 56 (April 2024). The download helper displays the +source URL, license URL, and expected SHA-256 digest before downloading it. + +The NXP SPSDK Python package used to assemble the boot image is distributed +under the BSD-3-Clause license. diff --git a/Documentation/platforms/arm/imxrt/index.rst b/Documentation/platforms/arm/imxrt/index.rst index f1d0c425cba14..9a22d8016b52d 100644 --- a/Documentation/platforms/arm/imxrt/index.rst +++ b/Documentation/platforms/arm/imxrt/index.rst @@ -25,9 +25,33 @@ RT1060 Yes Cortex-M7 600 MHz RT1064 Yes Cortex-M7 600 MHz RT1160 No Cortex-M7 + M4 600 Mhz + 240 MHz RT1170 Yes (Only M7) Cortex-M7 + M4 1 GHz + 400 MHz -RT1180 No Cortex-M7 + M33 800 Mhz + 300 MHz +RT1180 Yes Cortex-M7 + M33 800 Mhz + 300 MHz ====== ============== =============== ================= +i.MX RT118x +=========== + +The i.MX RT118x family is supported on both the Cortex-M33 and Cortex-M7 +cores. The Cortex-M33 is the boot core; it can run NuttX directly, or it +can run a small bootloader that releases the Cortex-M7 to run a separate +NuttX image. + +The current clock configuration runs the Cortex-M7 at 798 MHz and the +Cortex-M33 at 266 MHz due to ARM_PLL and divider setting limitations. + +RT118x uses the generation 3 clock configuration driver for the clock +roots found on this family. It also uses the generation 3 IOMUXC driver +for the RT118x pinmux layout and GPIO mode selection. + +RT118x uses the RGPIO driver and the matching RGPIO interrupt driver +instead of the legacy i.MX RT GPIO block. The version 2 eDMA driver is +selected for the newer RT118x eDMA IP. + +The EdgeLock Enclave driver provides the messaging path used for RT118x +ELE firmware, and the TRDC driver configures access to RT118x memory and +peripheral resources. The Cortex-M7 release helper is used by Cortex-M33 +firmware to set the Cortex-M7 boot vector and start the M7 core. + Data and Instruction Cache ========================== diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 8c67fd0240687..eeb8fee95dc1b 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -198,16 +198,14 @@ config ARCH_CHIP_IMX9_CORTEX_M config ARCH_CHIP_IMXRT bool "NXP/Freescale iMX.RT" - select ARCH_CORTEXM7 select ARCH_HAVE_MPU select ARCH_HAVE_RAMFUNCS select ARCH_HAVE_TICKLESS select ARCH_HAVE_I2CRESET select ARCH_HAVE_SPI_CS_CONTROL select ARM_HAVE_MPU_UNIFIED - select ARMV7M_HAVE_STACKCHECK ---help--- - NXP i.MX RT (ARM Cortex-M7) architectures + NXP i.MX RT (ARM Cortex-M7 or Cortex-M33) architectures. config ARCH_CHIP_KINETIS bool "NXP/Freescale Kinetis" diff --git a/arch/arm/include/imxrt/chip.h b/arch/arm/include/imxrt/chip.h index 40cdc557049fb..82e2218bbe0e1 100644 --- a/arch/arm/include/imxrt/chip.h +++ b/arch/arm/include/imxrt/chip.h @@ -84,6 +84,11 @@ /* MIMXRT1170DVMA TODO */ # define IMXRT_GPIO_NPORTS 13 /* Thirteen total ports */ +#elif defined(CONFIG_ARCH_CHIP_MIMXRT1189CVM8C) || \ + defined(CONFIG_ARCH_CHIP_MIMXRT1189CVM8C_CM33) +/* MIMXRT1189CVM8C - Dual-core Cortex-M33 + Cortex-M7 */ + +# define IMXRT_GPIO_NPORTS 6 /* Six general purpose GPIO ports */ #else # error "Unknown i.MX RT chip type" #endif diff --git a/arch/arm/include/imxrt/imxrt118x_irq.h b/arch/arm/include/imxrt/imxrt118x_irq.h new file mode 100644 index 0000000000000..5b3ffc273855d --- /dev/null +++ b/arch/arm/include/imxrt/imxrt118x_irq.h @@ -0,0 +1,293 @@ +/**************************************************************************** + * arch/arm/include/imxrt/imxrt118x_irq.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/* This file should never be included directly but, rather, + * only indirectly through nuttx/irq.h + */ + +#ifndef __ARCH_ARM_INCLUDE_IMXRT_IMXRT118X_IRQ_H +#define __ARCH_ARM_INCLUDE_IMXRT_IMXRT118X_IRQ_H + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* External interrupts (from IMXRT1180RM Ch. 4 Interrupts, Table 11). + * Names extracted from the NXP MCUXpresso SDK IRQn_Type enumeration. + */ + +#define IMXRT_IRQ_TMR1 (IMXRT_IRQ_EXTINT + 0) +#define IMXRT_IRQ_DAP (IMXRT_IRQ_EXTINT + 1) +#define IMXRT_IRQ_M7_CTI_TRIGGER_OUTPUT (IMXRT_IRQ_EXTINT + 2) +#define IMXRT_IRQ_M33_CTI_TRIGGER_OUTPUT (IMXRT_IRQ_EXTINT + 3) +#define IMXRT_IRQ_TMR5 (IMXRT_IRQ_EXTINT + 4) +#define IMXRT_IRQ_TMR6 (IMXRT_IRQ_EXTINT + 5) +#define IMXRT_IRQ_TMR7 (IMXRT_IRQ_EXTINT + 6) +#define IMXRT_IRQ_TMR8 (IMXRT_IRQ_EXTINT + 7) +#define IMXRT_IRQ_CAN1 (IMXRT_IRQ_EXTINT + 8) +#define IMXRT_IRQ_CAN1_ERROR (IMXRT_IRQ_EXTINT + 9) +#define IMXRT_IRQ_GPIO1_0 (IMXRT_IRQ_EXTINT + 10) +#define IMXRT_IRQ_GPIO1_1 (IMXRT_IRQ_EXTINT + 11) +#define IMXRT_IRQ_I3C1 (IMXRT_IRQ_EXTINT + 12) +#define IMXRT_IRQ_LPI2C1 (IMXRT_IRQ_EXTINT + 13) +#define IMXRT_IRQ_LPI2C2 (IMXRT_IRQ_EXTINT + 14) +#define IMXRT_IRQ_LPIT1 (IMXRT_IRQ_EXTINT + 15) +#define IMXRT_IRQ_LPSPI1 (IMXRT_IRQ_EXTINT + 16) +#define IMXRT_IRQ_LPSPI2 (IMXRT_IRQ_EXTINT + 17) +#define IMXRT_IRQ_LPTMR1 (IMXRT_IRQ_EXTINT + 18) +#define IMXRT_IRQ_LPUART1 (IMXRT_IRQ_EXTINT + 19) +#define IMXRT_IRQ_LPUART2 (IMXRT_IRQ_EXTINT + 20) +#define IMXRT_IRQ_MU1 (IMXRT_IRQ_EXTINT + 21) +#define IMXRT_IRQ_MU2 (IMXRT_IRQ_EXTINT + 22) +#define IMXRT_IRQ_PWM1_FAULT (IMXRT_IRQ_EXTINT + 23) +#define IMXRT_IRQ_PWM1_0 (IMXRT_IRQ_EXTINT + 24) +#define IMXRT_IRQ_PWM1_1 (IMXRT_IRQ_EXTINT + 25) +#define IMXRT_IRQ_PWM1_2 (IMXRT_IRQ_EXTINT + 26) +#define IMXRT_IRQ_PWM1_3 (IMXRT_IRQ_EXTINT + 27) +#define IMXRT_IRQ_EDGELOCK_TRUST_MUA_RX_FULL (IMXRT_IRQ_EXTINT + 28) +#define IMXRT_IRQ_EDGELOCK_TRUST_MUA_TX_EMPTY (IMXRT_IRQ_EXTINT + 29) +#define IMXRT_IRQ_EDGELOCK_APPS_CORE_MUA_RX_FULL (IMXRT_IRQ_EXTINT + 30) +#define IMXRT_IRQ_EDGELOCK_APPS_CORE_MUA_TX_EMPTY (IMXRT_IRQ_EXTINT + 31) +#define IMXRT_IRQ_EDGELOCK_REALTIME_CORE_MUA_RX_FULL (IMXRT_IRQ_EXTINT + 32) +#define IMXRT_IRQ_EDGELOCK_REALTIME_CORE_MUA_TX_EMPTY (IMXRT_IRQ_EXTINT + 33) +#define IMXRT_IRQ_EDGELOCK_SECURE (IMXRT_IRQ_EXTINT + 34) +#define IMXRT_IRQ_EDGELOCK_NONSECURE (IMXRT_IRQ_EXTINT + 35) +#define IMXRT_IRQ_TPM1 (IMXRT_IRQ_EXTINT + 36) +#define IMXRT_IRQ_TPM2 (IMXRT_IRQ_EXTINT + 37) +#define IMXRT_IRQ_RTWDOG1 (IMXRT_IRQ_EXTINT + 38) +#define IMXRT_IRQ_RTWDOG2 (IMXRT_IRQ_EXTINT + 39) +#define IMXRT_IRQ_TRDC_MGR_AON (IMXRT_IRQ_EXTINT + 40) +#define IMXRT_IRQ_PDM_HWVAD_EVENT (IMXRT_IRQ_EXTINT + 41) +#define IMXRT_IRQ_PDM_HWVAD_ERROR (IMXRT_IRQ_EXTINT + 42) +#define IMXRT_IRQ_PDM_EVENT (IMXRT_IRQ_EXTINT + 43) +#define IMXRT_IRQ_PDM_ERROR (IMXRT_IRQ_EXTINT + 44) +#define IMXRT_IRQ_SAI1 (IMXRT_IRQ_EXTINT + 45) +#define IMXRT_IRQ_CM33_PS (IMXRT_IRQ_EXTINT + 46) +#define IMXRT_IRQ_CM33_TCM_ECC (IMXRT_IRQ_EXTINT + 47) +#define IMXRT_IRQ_CM33_TCM_ERROR (IMXRT_IRQ_EXTINT + 48) +#define IMXRT_IRQ_CM7_TCM_ECC (IMXRT_IRQ_EXTINT + 49) +#define IMXRT_IRQ_CM7_TCM_ERROR (IMXRT_IRQ_EXTINT + 50) +#define IMXRT_IRQ_CAN2 (IMXRT_IRQ_EXTINT + 51) +#define IMXRT_IRQ_CAN2_ERROR (IMXRT_IRQ_EXTINT + 52) +#define IMXRT_IRQ_FLEXIO1 (IMXRT_IRQ_EXTINT + 53) +#define IMXRT_IRQ_FLEXIO2 (IMXRT_IRQ_EXTINT + 54) +#define IMXRT_IRQ_FLEXSPI1 (IMXRT_IRQ_EXTINT + 55) +#define IMXRT_IRQ_FLEXSPI2 (IMXRT_IRQ_EXTINT + 56) +#define IMXRT_IRQ_GPIO2_0 (IMXRT_IRQ_EXTINT + 57) +#define IMXRT_IRQ_GPIO2_1 (IMXRT_IRQ_EXTINT + 58) +#define IMXRT_IRQ_GPIO3_0 (IMXRT_IRQ_EXTINT + 59) +#define IMXRT_IRQ_GPIO3_1 (IMXRT_IRQ_EXTINT + 60) +#define IMXRT_IRQ_I3C2 (IMXRT_IRQ_EXTINT + 61) +#define IMXRT_IRQ_LPI2C3 (IMXRT_IRQ_EXTINT + 62) +#define IMXRT_IRQ_LPI2C4 (IMXRT_IRQ_EXTINT + 63) +#define IMXRT_IRQ_LPIT2 (IMXRT_IRQ_EXTINT + 64) +#define IMXRT_IRQ_LPSPI3 (IMXRT_IRQ_EXTINT + 65) +#define IMXRT_IRQ_LPSPI4 (IMXRT_IRQ_EXTINT + 66) +#define IMXRT_IRQ_LPTMR2 (IMXRT_IRQ_EXTINT + 67) +#define IMXRT_IRQ_LPUART3 (IMXRT_IRQ_EXTINT + 68) +#define IMXRT_IRQ_LPUART4 (IMXRT_IRQ_EXTINT + 69) +#define IMXRT_IRQ_LPUART5 (IMXRT_IRQ_EXTINT + 70) +#define IMXRT_IRQ_LPUART6 (IMXRT_IRQ_EXTINT + 71) +#define IMXRT_IRQ_Reserved88 (IMXRT_IRQ_EXTINT + 72) +#define IMXRT_IRQ_BBNSM (IMXRT_IRQ_EXTINT + 73) +#define IMXRT_IRQ_SYS_CTR1 (IMXRT_IRQ_EXTINT + 74) +#define IMXRT_IRQ_TPM3 (IMXRT_IRQ_EXTINT + 75) +#define IMXRT_IRQ_TPM4 (IMXRT_IRQ_EXTINT + 76) +#define IMXRT_IRQ_TPM5 (IMXRT_IRQ_EXTINT + 77) +#define IMXRT_IRQ_TPM6 (IMXRT_IRQ_EXTINT + 78) +#define IMXRT_IRQ_RTWDOG3 (IMXRT_IRQ_EXTINT + 79) +#define IMXRT_IRQ_RTWDOG4 (IMXRT_IRQ_EXTINT + 80) +#define IMXRT_IRQ_RTWDOG5 (IMXRT_IRQ_EXTINT + 81) +#define IMXRT_IRQ_TRDC_MGR_WKUP (IMXRT_IRQ_EXTINT + 82) +#define IMXRT_IRQ_TMPSNS_INT (IMXRT_IRQ_EXTINT + 83) +#define IMXRT_IRQ_BBSM (IMXRT_IRQ_EXTINT + 84) +#define IMXRT_IRQ_LDO_AON_ANA (IMXRT_IRQ_EXTINT + 85) +#define IMXRT_IRQ_USDHC1 (IMXRT_IRQ_EXTINT + 86) +#define IMXRT_IRQ_USDHC2 (IMXRT_IRQ_EXTINT + 87) +#define IMXRT_IRQ_TRDC_MGR_MEGA (IMXRT_IRQ_EXTINT + 88) +#define IMXRT_IRQ_SFA (IMXRT_IRQ_EXTINT + 89) +#define IMXRT_IRQ_LDO_AON_DIG (IMXRT_IRQ_EXTINT + 90) +#define IMXRT_IRQ_MECC1 (IMXRT_IRQ_EXTINT + 91) +#define IMXRT_IRQ_MECC2 (IMXRT_IRQ_EXTINT + 92) +#define IMXRT_IRQ_ADC1 (IMXRT_IRQ_EXTINT + 93) +#define IMXRT_IRQ_DMA_ERROR (IMXRT_IRQ_EXTINT + 94) +#define IMXRT_IRQ_DMA3_CH0 (IMXRT_IRQ_EXTINT + 95) +#define IMXRT_IRQ_DMA3_CH1 (IMXRT_IRQ_EXTINT + 96) +#define IMXRT_IRQ_DMA3_CH2 (IMXRT_IRQ_EXTINT + 97) +#define IMXRT_IRQ_DMA3_CH3 (IMXRT_IRQ_EXTINT + 98) +#define IMXRT_IRQ_DMA3_CH4 (IMXRT_IRQ_EXTINT + 99) +#define IMXRT_IRQ_DMA3_CH5 (IMXRT_IRQ_EXTINT + 100) +#define IMXRT_IRQ_DMA3_CH6 (IMXRT_IRQ_EXTINT + 101) +#define IMXRT_IRQ_DMA3_CH7 (IMXRT_IRQ_EXTINT + 102) +#define IMXRT_IRQ_DMA3_CH8 (IMXRT_IRQ_EXTINT + 103) +#define IMXRT_IRQ_DMA3_CH9 (IMXRT_IRQ_EXTINT + 104) +#define IMXRT_IRQ_DMA3_CH10 (IMXRT_IRQ_EXTINT + 105) +#define IMXRT_IRQ_DMA3_CH11 (IMXRT_IRQ_EXTINT + 106) +#define IMXRT_IRQ_DMA3_CH12 (IMXRT_IRQ_EXTINT + 107) +#define IMXRT_IRQ_DMA3_CH13 (IMXRT_IRQ_EXTINT + 108) +#define IMXRT_IRQ_DMA3_CH14 (IMXRT_IRQ_EXTINT + 109) +#define IMXRT_IRQ_DMA3_CH15 (IMXRT_IRQ_EXTINT + 110) +#define IMXRT_IRQ_DMA3_CH16 (IMXRT_IRQ_EXTINT + 111) +#define IMXRT_IRQ_DMA3_CH17 (IMXRT_IRQ_EXTINT + 112) +#define IMXRT_IRQ_DMA3_CH18 (IMXRT_IRQ_EXTINT + 113) +#define IMXRT_IRQ_DMA3_CH19 (IMXRT_IRQ_EXTINT + 114) +#define IMXRT_IRQ_DMA3_CH20 (IMXRT_IRQ_EXTINT + 115) +#define IMXRT_IRQ_DMA3_CH21 (IMXRT_IRQ_EXTINT + 116) +#define IMXRT_IRQ_DMA3_CH22 (IMXRT_IRQ_EXTINT + 117) +#define IMXRT_IRQ_DMA3_CH23 (IMXRT_IRQ_EXTINT + 118) +#define IMXRT_IRQ_DMA3_CH24 (IMXRT_IRQ_EXTINT + 119) +#define IMXRT_IRQ_DMA3_CH25 (IMXRT_IRQ_EXTINT + 120) +#define IMXRT_IRQ_DMA3_CH26 (IMXRT_IRQ_EXTINT + 121) +#define IMXRT_IRQ_DMA3_CH27 (IMXRT_IRQ_EXTINT + 122) +#define IMXRT_IRQ_DMA3_CH28 (IMXRT_IRQ_EXTINT + 123) +#define IMXRT_IRQ_DMA3_CH29 (IMXRT_IRQ_EXTINT + 124) +#define IMXRT_IRQ_DMA3_CH30 (IMXRT_IRQ_EXTINT + 125) +#define IMXRT_IRQ_DMA3_CH31 (IMXRT_IRQ_EXTINT + 126) +#define IMXRT_IRQ_DMA4_ERROR (IMXRT_IRQ_EXTINT + 127) +#define IMXRT_IRQ_DMA4_CH0_CH1_CH32_CH33 (IMXRT_IRQ_EXTINT + 128) +#define IMXRT_IRQ_DMA4_CH2_CH3_CH34_CH35 (IMXRT_IRQ_EXTINT + 129) +#define IMXRT_IRQ_DMA4_CH4_CH5_CH36_CH37 (IMXRT_IRQ_EXTINT + 130) +#define IMXRT_IRQ_DMA4_CH6_CH7_CH38_CH39 (IMXRT_IRQ_EXTINT + 131) +#define IMXRT_IRQ_DMA4_CH8_CH9_CH40_CH41 (IMXRT_IRQ_EXTINT + 132) +#define IMXRT_IRQ_DMA4_CH10_CH11_CH42_CH43 (IMXRT_IRQ_EXTINT + 133) +#define IMXRT_IRQ_DMA4_CH12_CH13_CH44_CH45 (IMXRT_IRQ_EXTINT + 134) +#define IMXRT_IRQ_DMA4_CH14_CH15_CH46_CH47 (IMXRT_IRQ_EXTINT + 135) +#define IMXRT_IRQ_DMA4_CH16_CH17_CH48_CH49 (IMXRT_IRQ_EXTINT + 136) +#define IMXRT_IRQ_DMA4_CH18_CH19_CH50_CH51 (IMXRT_IRQ_EXTINT + 137) +#define IMXRT_IRQ_DMA4_CH20_CH21_CH52_CH53 (IMXRT_IRQ_EXTINT + 138) +#define IMXRT_IRQ_DMA4_CH22_CH23_CH54_CH55 (IMXRT_IRQ_EXTINT + 139) +#define IMXRT_IRQ_DMA4_CH24_CH25_CH56_CH57 (IMXRT_IRQ_EXTINT + 140) +#define IMXRT_IRQ_DMA4_CH26_CH27_CH58_CH59 (IMXRT_IRQ_EXTINT + 141) +#define IMXRT_IRQ_DMA4_CH28_CH29_CH60_CH61 (IMXRT_IRQ_EXTINT + 142) +#define IMXRT_IRQ_DMA4_CH30_CH31_CH62_CH63 (IMXRT_IRQ_EXTINT + 143) +#define IMXRT_IRQ_XBAR1_CH0_CH1 (IMXRT_IRQ_EXTINT + 144) +#define IMXRT_IRQ_XBAR1_CH2_CH3 (IMXRT_IRQ_EXTINT + 145) +#define IMXRT_IRQ_SINC3_CH0_CH1_CH2_CH3 (IMXRT_IRQ_EXTINT + 146) +#define IMXRT_IRQ_EWM (IMXRT_IRQ_EXTINT + 147) +#define IMXRT_IRQ_SEMC (IMXRT_IRQ_EXTINT + 148) +#define IMXRT_IRQ_LPIT3 (IMXRT_IRQ_EXTINT + 149) +#define IMXRT_IRQ_LPTMR3 (IMXRT_IRQ_EXTINT + 150) +#define IMXRT_IRQ_TMR4 (IMXRT_IRQ_EXTINT + 151) +#define IMXRT_IRQ_LPI2C5 (IMXRT_IRQ_EXTINT + 152) +#define IMXRT_IRQ_LPI2C6 (IMXRT_IRQ_EXTINT + 153) +#define IMXRT_IRQ_SAI4 (IMXRT_IRQ_EXTINT + 154) +#define IMXRT_IRQ_SPDIF (IMXRT_IRQ_EXTINT + 155) +#define IMXRT_IRQ_LPUART9 (IMXRT_IRQ_EXTINT + 156) +#define IMXRT_IRQ_LPUART10 (IMXRT_IRQ_EXTINT + 157) +#define IMXRT_IRQ_LPUART11 (IMXRT_IRQ_EXTINT + 158) +#define IMXRT_IRQ_LPUART12 (IMXRT_IRQ_EXTINT + 159) +#define IMXRT_IRQ_INTG_BOOTROM_DEBUG_CTRL (IMXRT_IRQ_EXTINT + 160) +#define IMXRT_IRQ_EDGELOCK_REQ1 (IMXRT_IRQ_EXTINT + 161) +#define IMXRT_IRQ_EDGELOCK_REQ2 (IMXRT_IRQ_EXTINT + 162) +#define IMXRT_IRQ_EDGELOCK_REQ3 (IMXRT_IRQ_EXTINT + 163) +#define IMXRT_IRQ_TMR3 (IMXRT_IRQ_EXTINT + 164) +#define IMXRT_IRQ_JTAGC (IMXRT_IRQ_EXTINT + 165) +#define IMXRT_IRQ_M33_SYSRESET_REQ (IMXRT_IRQ_EXTINT + 166) +#define IMXRT_IRQ_M33_LOCKUP (IMXRT_IRQ_EXTINT + 167) +#define IMXRT_IRQ_M7_SYSRESET_REQ (IMXRT_IRQ_EXTINT + 168) +#define IMXRT_IRQ_M7_LOCKUP (IMXRT_IRQ_EXTINT + 169) +#define IMXRT_IRQ_PWM2_FAULT (IMXRT_IRQ_EXTINT + 170) +#define IMXRT_IRQ_PWM2_0 (IMXRT_IRQ_EXTINT + 171) +#define IMXRT_IRQ_PWM2_1 (IMXRT_IRQ_EXTINT + 172) +#define IMXRT_IRQ_PWM2_2 (IMXRT_IRQ_EXTINT + 173) +#define IMXRT_IRQ_PWM2_3 (IMXRT_IRQ_EXTINT + 174) +#define IMXRT_IRQ_PWM3_FAULT (IMXRT_IRQ_EXTINT + 175) +#define IMXRT_IRQ_PWM3_0 (IMXRT_IRQ_EXTINT + 176) +#define IMXRT_IRQ_PWM3_1 (IMXRT_IRQ_EXTINT + 177) +#define IMXRT_IRQ_PWM3_2 (IMXRT_IRQ_EXTINT + 178) +#define IMXRT_IRQ_PWM3_3 (IMXRT_IRQ_EXTINT + 179) +#define IMXRT_IRQ_PWM4_FAULT (IMXRT_IRQ_EXTINT + 180) +#define IMXRT_IRQ_PWM4_0 (IMXRT_IRQ_EXTINT + 181) +#define IMXRT_IRQ_PWM4_1 (IMXRT_IRQ_EXTINT + 182) +#define IMXRT_IRQ_PWM4_2 (IMXRT_IRQ_EXTINT + 183) +#define IMXRT_IRQ_PWM4_3 (IMXRT_IRQ_EXTINT + 184) +#define IMXRT_IRQ_EQDC1 (IMXRT_IRQ_EXTINT + 185) +#define IMXRT_IRQ_EQDC2 (IMXRT_IRQ_EXTINT + 186) +#define IMXRT_IRQ_EQDC3 (IMXRT_IRQ_EXTINT + 187) +#define IMXRT_IRQ_EQDC4 (IMXRT_IRQ_EXTINT + 188) +#define IMXRT_IRQ_ADC2 (IMXRT_IRQ_EXTINT + 189) +#define IMXRT_IRQ_DCDC (IMXRT_IRQ_EXTINT + 190) +#define IMXRT_IRQ_CAN3 (IMXRT_IRQ_EXTINT + 191) +#define IMXRT_IRQ_CAN3_ERROR (IMXRT_IRQ_EXTINT + 192) +#define IMXRT_IRQ_DAC (IMXRT_IRQ_EXTINT + 193) +#define IMXRT_IRQ_LPSPI5 (IMXRT_IRQ_EXTINT + 194) +#define IMXRT_IRQ_LPSPI6 (IMXRT_IRQ_EXTINT + 195) +#define IMXRT_IRQ_LPUART7 (IMXRT_IRQ_EXTINT + 196) +#define IMXRT_IRQ_LPUART8 (IMXRT_IRQ_EXTINT + 197) +#define IMXRT_IRQ_SAI2 (IMXRT_IRQ_EXTINT + 198) +#define IMXRT_IRQ_SAI3 (IMXRT_IRQ_EXTINT + 199) +#define IMXRT_IRQ_ACMP1 (IMXRT_IRQ_EXTINT + 200) +#define IMXRT_IRQ_ACMP2 (IMXRT_IRQ_EXTINT + 201) +#define IMXRT_IRQ_ACMP3 (IMXRT_IRQ_EXTINT + 202) +#define IMXRT_IRQ_ACMP4 (IMXRT_IRQ_EXTINT + 203) +#define IMXRT_IRQ_CM7_PS (IMXRT_IRQ_EXTINT + 204) +#define IMXRT_IRQ_CM7_MCM (IMXRT_IRQ_EXTINT + 205) +#define IMXRT_IRQ_CM33_MCM (IMXRT_IRQ_EXTINT + 206) +#define IMXRT_IRQ_ECAT_INT (IMXRT_IRQ_EXTINT + 207) +#define IMXRT_IRQ_SAFETY_CLK_MON (IMXRT_IRQ_EXTINT + 208) +#define IMXRT_IRQ_GPT1 (IMXRT_IRQ_EXTINT + 209) +#define IMXRT_IRQ_GPT2 (IMXRT_IRQ_EXTINT + 210) +#define IMXRT_IRQ_KPP (IMXRT_IRQ_EXTINT + 211) +#define IMXRT_IRQ_USBPHY1 (IMXRT_IRQ_EXTINT + 212) +#define IMXRT_IRQ_USBPHY2 (IMXRT_IRQ_EXTINT + 213) +#define IMXRT_IRQ_USB_OTG2 (IMXRT_IRQ_EXTINT + 214) +#define IMXRT_IRQ_USBOTG1 (IMXRT_IRQ_EXTINT + 215) +#define IMXRT_IRQ_FLEXSPI_SLV (IMXRT_IRQ_EXTINT + 216) +#define IMXRT_IRQ_NETC (IMXRT_IRQ_EXTINT + 217) +#define IMXRT_IRQ_MSGINTR1 (IMXRT_IRQ_EXTINT + 218) +#define IMXRT_IRQ_MSGINTR2 (IMXRT_IRQ_EXTINT + 219) +#define IMXRT_IRQ_MSGINTR3 (IMXRT_IRQ_EXTINT + 220) +#define IMXRT_IRQ_MSGINTR4 (IMXRT_IRQ_EXTINT + 221) +#define IMXRT_IRQ_MSGINTR5 (IMXRT_IRQ_EXTINT + 222) +#define IMXRT_IRQ_MSGINTR6 (IMXRT_IRQ_EXTINT + 223) +#define IMXRT_IRQ_SINC1_CH0 (IMXRT_IRQ_EXTINT + 224) +#define IMXRT_IRQ_SINC1_CH1 (IMXRT_IRQ_EXTINT + 225) +#define IMXRT_IRQ_SINC1_CH2 (IMXRT_IRQ_EXTINT + 226) +#define IMXRT_IRQ_SINC1_CH3 (IMXRT_IRQ_EXTINT + 227) +#define IMXRT_IRQ_SINC2_CH0 (IMXRT_IRQ_EXTINT + 228) +#define IMXRT_IRQ_SINC2_CH1 (IMXRT_IRQ_EXTINT + 229) +#define IMXRT_IRQ_SINC2_CH2 (IMXRT_IRQ_EXTINT + 230) +#define IMXRT_IRQ_SINC2_CH3 (IMXRT_IRQ_EXTINT + 231) +#define IMXRT_IRQ_GPIO4 (IMXRT_IRQ_EXTINT + 232) +#define IMXRT_IRQ_TMR2 (IMXRT_IRQ_EXTINT + 233) +#define IMXRT_IRQ_GPIO5 (IMXRT_IRQ_EXTINT + 234) +#define IMXRT_IRQ_ASRC (IMXRT_IRQ_EXTINT + 235) +#define IMXRT_IRQ_GPIO6 (IMXRT_IRQ_EXTINT + 236) +#define IMXRT_IRQ_DBG_TRACE (IMXRT_IRQ_EXTINT + 237) + +/* Total number of external interrupts (matches the SDK IRQn_Type range). */ + +#define IMXRT_IRQ_NEXTINT (238) + +/* Interrupt count for the M33 core on imxrt118x. */ + +#define ARMV8M_PERIPHERAL_INTERRUPTS IMXRT_IRQ_NEXTINT + +/* No GPIO interrupts are wired up in the minimal port. */ + +#define IMXRT_GPIO_IRQ_FIRST (IMXRT_IRQ_EXTINT + IMXRT_IRQ_NEXTINT) +#define IMXRT_GPIO_NIRQS (0) + +#define NR_IRQS (IMXRT_IRQ_EXTINT + IMXRT_IRQ_NEXTINT + \ + IMXRT_GPIO_NIRQS) + +#endif /* __ARCH_ARM_INCLUDE_IMXRT_IMXRT118X_IRQ_H */ diff --git a/arch/arm/include/imxrt/irq.h b/arch/arm/include/imxrt/irq.h index 8778e34f32644..d858df5f070fc 100644 --- a/arch/arm/include/imxrt/irq.h +++ b/arch/arm/include/imxrt/irq.h @@ -42,6 +42,8 @@ # include #elif defined(CONFIG_ARCH_FAMILY_IMXRT117x) # include +#elif defined(CONFIG_ARCH_FAMILY_IMXRT118x) +# include #else # error Unrecognized i.MX RT architecture #endif diff --git a/arch/arm/src/imxrt/CMakeLists.txt b/arch/arm/src/imxrt/CMakeLists.txt index 9db635e40b0f1..f16722d8def94 100644 --- a/arch/arm/src/imxrt/CMakeLists.txt +++ b/arch/arm/src/imxrt/CMakeLists.txt @@ -24,7 +24,11 @@ # Required i.MX RT files -set(SRCS imxrt_allocateheap.c imxrt_start.c imxrt_periphclks.c) +set(SRCS imxrt_allocateheap.c imxrt_start.c) + +if(NOT CONFIG_IMXRT_RGPIO) + list(APPEND SRCS imxrt_periphclks.c) +endif() if(CONFIG_IMXRT_PROGMEM) list(APPEND SRCS imxrt_flash.c) @@ -35,23 +39,31 @@ list( SRCS imxrt_irq.c imxrt_clrpend.c - imxrt_gpio.c - imxrt_daisy.c imxrt_wdog.c imxrt_serial.c imxrt_xbar.c imxrt_ocotp.c imxrt_lowputc.c) +if(CONFIG_IMXRT_RGPIO) + list(APPEND SRCS imxrt_rgpio.c) +else() + list(APPEND SRCS imxrt_gpio.c imxrt_daisy.c) +endif() + # Configuration-dependent i.MX RT files -if(CONFIG_IMXRT_CLOCKCONFIG_VER2) +if(CONFIG_IMXRT_CLOCKCONFIG_VER3) + list(APPEND SRCS imxrt_clockconfig_ver3.c) +elseif(CONFIG_IMXRT_CLOCKCONFIG_VER2) list(APPEND SRCS imxrt_clockconfig_ver2.c imxrt_pmu.c) else() list(APPEND SRCS imxrt_clockconfig_ver1.c) endif() -if(CONFIG_IMXRT_IOMUX_VER2) +if(CONFIG_IMXRT_IOMUX_VER3) + list(APPEND SRCS imxrt_iomuxc_ver3.c) +elseif(CONFIG_IMXRT_IOMUX_VER2) list(APPEND SRCS imxrt_iomuxc_ver2.c) else() list(APPEND SRCS imxrt_iomuxc_ver1.c) @@ -68,7 +80,11 @@ else() endif() if(CONFIG_IMXRT_GPIO_IRQ) - list(APPEND SRCS imxrt_gpioirq.c) + if(CONFIG_IMXRT_RGPIO) + list(APPEND SRCS imxrt_rgpioirq.c) + else() + list(APPEND SRCS imxrt_gpioirq.c) + endif() endif() if(CONFIG_ARM_MPU) @@ -80,7 +96,11 @@ if(CONFIG_BUILD_PROTECTED) endif() if(CONFIG_IMXRT_EDMA) - list(APPEND SRCS imxrt_edma.c) + if(CONFIG_IMXRT_EDMA_VER2) + list(APPEND SRCS imxrt_edma_ver2.c) + else() + list(APPEND SRCS imxrt_edma.c) + endif() endif() if(CONFIG_IMXRT_USDHC) @@ -149,4 +169,12 @@ if(CONFIG_IMXRT_ADC) endif() endif() +if(CONFIG_IMXRT_TRDC) + list(APPEND SRCS imxrt118x_trdc.c) +endif() + +if(CONFIG_IMXRT_ELE) + list(APPEND SRCS imxrt118x_ele.c) +endif() + target_sources(arch PRIVATE ${SRCS}) diff --git a/arch/arm/src/imxrt/Kconfig b/arch/arm/src/imxrt/Kconfig index f440e57b667a1..a6dc82c2f5342 100644 --- a/arch/arm/src/imxrt/Kconfig +++ b/arch/arm/src/imxrt/Kconfig @@ -105,6 +105,34 @@ config ARCH_CHIP_MIMXRT1176DVMAA select IMXRT_HAVE_USBOTG1 select IMXRT_HAVE_USBOTG2 +config ARCH_CHIP_MIMXRT1189CVM8C + bool "MIMXRT1189CVM8C (Cortex-M7 core)" + select ARCH_FAMILY_IMXRT118x + select ARCH_CORTEXM7 + select ARCH_HAVE_DPFPU + select ARMV7M_HAVE_ICACHE + select ARMV7M_HAVE_DCACHE + select ARMV7M_HAVE_ITCM + select ARMV7M_HAVE_DTCM + select ARMV7M_HAVE_STACKCHECK + select ARMV7M_ITCM + select ARMV7M_DTCM + select ARM_MPU + ---help--- + Target the Cortex-M7 core on the RT1189 SoC. + +config ARCH_CHIP_MIMXRT1189CVM8C_CM33 + bool "MIMXRT1189CVM8C (Cortex-M33 core)" + select ARCH_FAMILY_IMXRT118x + select ARCH_CORTEXM33 + select ARMV8M_HAVE_STACKCHECK + select IMXRT_TRDC + select IMXRT_ELE + ---help--- + Target the Cortex-M33 core on the RT1189 SoC. Used to build a + NuttX bootloader / minimal application that runs on the M33 out + of reset. + endchoice # i.MX RT Chip Selection # i.MX RT Families @@ -126,12 +154,14 @@ config ARCH_FAMILY_MIMXRT1021C config ARCH_FAMILY_IMXRT102x bool default n + select ARCH_CORTEXM7 select ARCH_HAVE_FPU select ARCH_HAVE_DPFPU # REVISIT select ARMV7M_HAVE_ICACHE select ARMV7M_HAVE_DCACHE select ARMV7M_HAVE_ITCM select ARMV7M_HAVE_DTCM + select ARMV7M_HAVE_STACKCHECK config ARCH_FAMILY_MIMXRT105xDVL6A bool @@ -150,12 +180,14 @@ config ARCH_FAMILY_MIMXRT105xCVL5A config ARCH_FAMILY_IMXRT105x bool default n + select ARCH_CORTEXM7 select ARCH_HAVE_FPU select ARCH_HAVE_DPFPU # REVISIT select ARMV7M_HAVE_ICACHE select ARMV7M_HAVE_DCACHE select ARMV7M_HAVE_ITCM select ARMV7M_HAVE_DTCM + select ARMV7M_HAVE_STACKCHECK config ARCH_FAMILY_MXRT106xDVL6A bool @@ -174,12 +206,14 @@ config ARCH_FAMILY_MIMXRT106xCVL5A config ARCH_FAMILY_IMXRT117x bool default n + select ARCH_CORTEXM7 select ARCH_HAVE_FPU select ARCH_HAVE_DPFPU # REVISIT select ARMV7M_HAVE_ICACHE select ARMV7M_HAVE_DCACHE select ARMV7M_HAVE_ITCM select ARMV7M_HAVE_DTCM + select ARMV7M_HAVE_STACKCHECK select IMXRT_HIGHSPEED_GPIO select IMXRT_HAVE_FLEXSPI2 select IMXRT_ADC_VER2 @@ -193,15 +227,32 @@ config ARCH_FAMILY_IMXRT117x select IMXRT_FLEXCAN1_FD select IMXRT_FLEXCAN2_FD +config ARCH_FAMILY_IMXRT118x + bool + default n + select ARCH_HAVE_FPU + select IMXRT_HAVE_LPUART9 + select IMXRT_HAVE_LPUART10 + select IMXRT_HAVE_LPUART11 + select IMXRT_HAVE_LPUART12 + select IMXRT_CLOCKCONFIG_VER3 + select IMXRT_IOMUX_VER3 + select IMXRT_RGPIO + select IMXRT_EDMA_VER2 + ---help--- + i.MX RT1180 dual-core Crossover Processors (Cortex-M33 + Cortex-M7). + config ARCH_FAMILY_IMXRT106x bool default n + select ARCH_CORTEXM7 select ARCH_HAVE_FPU select ARCH_HAVE_DPFPU # REVISIT select ARMV7M_HAVE_ICACHE select ARMV7M_HAVE_DCACHE select ARMV7M_HAVE_ITCM select ARMV7M_HAVE_DTCM + select ARMV7M_HAVE_STACKCHECK select IMXRT_HIGHSPEED_GPIO select IMXRT_HAVE_FLEXSPI2 select IMXRT_HAVE_FLEXIO3 @@ -359,10 +410,78 @@ config IMXRT_CLOCKCONFIG_VER2 bool default n +config IMXRT_CLOCKCONFIG_VER3 + bool + default n + ---help--- + Selects the RT118x-family clock configuration + (arch/arm/src/imxrt/imxrt_clockconfig_ver3.c). + config IMXRT_IOMUX_VER2 bool default n +config IMXRT_IOMUX_VER3 + bool + default n + ---help--- + Selects the "generation 3" IOMUXC driver used by RT118x. + +config IMXRT_RGPIO + bool + default n + ---help--- + Selects the RGPIO driver (arch/arm/src/imxrt/imxrt_rgpio.c) that + targets the RGPIO IP block used on RT118x. + +config IMXRT_EDMA_VER2 + bool + default n + ---help--- + Selects the RT118x eDMA driver variant + (arch/arm/src/imxrt/imxrt_edma_ver2.c) used by RT118x. + +config IMXRT_TRDC + bool + default n + ---help--- + Enable the Trusted Resource Domain Controller driver + (arch/arm/src/imxrt/imxrt118x_trdc.c). Present on RT118x-class + SoCs. + +config IMXRT_ELE + bool + default n + ---help--- + Enable the NXP EdgeLock Enclave (ELE) messaging driver + (arch/arm/src/imxrt/imxrt118x_ele.c). Present on RT118x-class + SoCs. + +config IMXRT_ELE_LOAD_FW + bool "Load ELE firmware from NuttX at boot" + depends on IMXRT_ELE + default n + ---help--- + Embed the ELE firmware AHAB container (CONFIG_IMXRT_ELE_FW_PATH) + in the NuttX image and hand it to the EdgeLock Enclave with a + LOAD_FW command early in imxrt118x_ele_init(). + + When disabled, the ELE firmware is instead packed as its own + AHAB container in the boot image, loaded by ROM code. + +config IMXRT_ELE_FW_PATH + string "ELE firmware AHAB container path" + depends on IMXRT_ELE + default "tools/imxrt1180/.cache/ele-fw/mxrt1180b0-ahab-container.img" + ---help--- + Path (relative to the NuttX top-level directory, or absolute) to + the NXP EdgeLock Enclave firmware AHAB container. + +config IMXRT_CM7_BOOT + bool + default n + depends on ARCH_CHIP_MIMXRT1189CVM8C_CM33 + menu "i.MX RT Peripheral Selection" config IMXRT_EDMA @@ -2375,6 +2494,7 @@ endmenu # i.MX RT Peripheral Selection menuconfig IMXRT_GPIO_IRQ bool "GPIO Interrupt Support" default n + depends on !IMXRT_RGPIO if IMXRT_GPIO_IRQ @@ -2626,6 +2746,7 @@ endchoice # i.MX RT Boot Configuration choice prompt "i.MX RT Primary RAM" + default IMXRT_TCM_PRIMARY if ARCH_CORTEXM33 default IMXRT_OCRAM_PRIMARY ---help--- The primary RAM is the RAM that contains the system BLOB's .data and @@ -2643,6 +2764,13 @@ config IMXRT_SRAM_PRIMARY bool "External SRAM primary" depends on IMXRT_SEMC_SRAM +config IMXRT_TCM_PRIMARY + bool "TCM primary" + ---help--- + Place the primary RAM in the core-local TCM (M7 DTCM or M33 + System TCM, both aliased at IMXRT_DTCM_BASE). The size is taken + from the linker script's _ram_size symbol. + endchoice # i.MX RT Primary RAM menu "i.MX RT Heap Configuration" diff --git a/arch/arm/src/imxrt/Make.defs b/arch/arm/src/imxrt/Make.defs index 7c26dc8179145..999f756efb8cd 100644 --- a/arch/arm/src/imxrt/Make.defs +++ b/arch/arm/src/imxrt/Make.defs @@ -20,29 +20,46 @@ # ############################################################################ -# Common ARM and Cortex-M7 files +# Common ARM and Cortex-M7/M33 files +ifeq ($(CONFIG_ARCH_CORTEXM33),y) +include armv8-m/Make.defs +else include armv7-m/Make.defs +endif # Required i.MX RT files -CHIP_CSRCS = imxrt_allocateheap.c imxrt_start.c imxrt_periphclks.c +CHIP_CSRCS = imxrt_allocateheap.c imxrt_start.c +ifneq ($(CONFIG_IMXRT_RGPIO),y) +CHIP_CSRCS += imxrt_periphclks.c +endif ifeq ($(CONFIG_IMXRT_PROGMEM),y) CHIP_CSRCS += imxrt_flash.c endif -CHIP_CSRCS += imxrt_irq.c imxrt_clrpend.c imxrt_gpio.c -CHIP_CSRCS += imxrt_daisy.c imxrt_wdog.c imxrt_serial.c -CHIP_CSRCS += imxrt_xbar.c imxrt_ocotp.c imxrt_lowputc.c +CHIP_CSRCS += imxrt_irq.c imxrt_clrpend.c +ifeq ($(CONFIG_IMXRT_RGPIO),y) +CHIP_CSRCS += imxrt_rgpio.c +else +CHIP_CSRCS += imxrt_gpio.c +CHIP_CSRCS += imxrt_daisy.c +endif +CHIP_CSRCS += imxrt_wdog.c imxrt_serial.c imxrt_xbar.c imxrt_ocotp.c +CHIP_CSRCS += imxrt_lowputc.c # Configuration-dependent i.MX RT files -ifeq ($(CONFIG_IMXRT_CLOCKCONFIG_VER2),y) +ifeq ($(CONFIG_IMXRT_CLOCKCONFIG_VER3),y) +CHIP_CSRCS += imxrt_clockconfig_ver3.c +else ifeq ($(CONFIG_IMXRT_CLOCKCONFIG_VER2),y) CHIP_CSRCS += imxrt_clockconfig_ver2.c imxrt_pmu.c else CHIP_CSRCS += imxrt_clockconfig_ver1.c endif -ifeq ($(CONFIG_IMXRT_IOMUX_VER2),y) +ifeq ($(CONFIG_IMXRT_IOMUX_VER3),y) +CHIP_CSRCS += imxrt_iomuxc_ver3.c +else ifeq ($(CONFIG_IMXRT_IOMUX_VER2),y) CHIP_CSRCS += imxrt_iomuxc_ver2.c else CHIP_CSRCS += imxrt_iomuxc_ver1.c @@ -59,8 +76,12 @@ CHIP_CSRCS += imxrt_tickless.c endif ifeq ($(CONFIG_IMXRT_GPIO_IRQ),y) +ifeq ($(CONFIG_IMXRT_RGPIO),y) +CHIP_CSRCS += imxrt_rgpioirq.c +else CHIP_CSRCS += imxrt_gpioirq.c endif +endif ifeq ($(CONFIG_ARM_MPU),y) CHIP_CSRCS += imxrt_mpuinit.c @@ -71,8 +92,12 @@ CHIP_CSRCS += imxrt_userspace.c endif ifeq ($(CONFIG_IMXRT_EDMA),y) +ifeq ($(CONFIG_IMXRT_EDMA_VER2),y) +CHIP_CSRCS += imxrt_edma_ver2.c +else CHIP_CSRCS += imxrt_edma.c endif +endif ifdef CONFIG_IMXRT_USDHC CHIP_CSRCS += imxrt_usdhc.c @@ -140,3 +165,24 @@ else CHIP_CSRCS += imxrt_adc_ver1.c endif endif + +ifeq ($(CONFIG_IMXRT_TRDC),y) +CHIP_CSRCS += imxrt118x_trdc.c +endif + +ifeq ($(CONFIG_IMXRT_ELE),y) +CHIP_CSRCS += imxrt118x_ele.c + +ifeq ($(CONFIG_IMXRT_ELE_LOAD_FW),y) +# Pass CONFIG_IMXRT_ELE_FW_PATH back to imxrt118x_ele.c via a -D override +# so the .incbin directive can find the file no matter what the +# compiler's CWD happens to be. +CFLAGS += -DIMXRT_ELE_FW_ABS_PATH=\"$(IMXRT_ELE_FW_ABS)\" + +imxrt118x_ele.o: $(IMXRT_ELE_FW_ABS) +endif +endif + +ifeq ($(CONFIG_IMXRT_CM7_BOOT),y) +CHIP_CSRCS += imxrt118x_start_cm7.c +endif diff --git a/arch/arm/src/imxrt/chip.h b/arch/arm/src/imxrt/chip.h index c31b4427e27ba..7cde382f5fcb8 100644 --- a/arch/arm/src/imxrt/chip.h +++ b/arch/arm/src/imxrt/chip.h @@ -45,10 +45,15 @@ #define ARMV7M_PERIPHERAL_INTERRUPTS IMXRT_IRQ_NEXTINT -/* Cache line sizes (in bytes)for the i.MX RT */ +/* Cache line sizes (in bytes) for the i.MX RT. */ -#define ARMV7M_DCACHE_LINESIZE 32 /* 32 bytes (8 words) */ -#define ARMV7M_ICACHE_LINESIZE 32 /* 32 bytes (8 words) */ +#ifdef CONFIG_ARCH_CORTEXM33 +# define ARMV8M_DCACHE_LINESIZE 32 /* 32 bytes (8 words) */ +# define ARMV8M_ICACHE_LINESIZE 32 /* 32 bytes (8 words) */ +#else +# define ARMV7M_DCACHE_LINESIZE 32 /* 32 bytes (8 words) */ +# define ARMV7M_ICACHE_LINESIZE 32 /* 32 bytes (8 words) */ +#endif /**************************************************************************** * Pre-processor Definitions diff --git a/arch/arm/src/imxrt/hardware/imxrt_ccm.h b/arch/arm/src/imxrt/hardware/imxrt_ccm.h index e09544f02a235..4775c73c7b321 100644 --- a/arch/arm/src/imxrt/hardware/imxrt_ccm.h +++ b/arch/arm/src/imxrt/hardware/imxrt_ccm.h @@ -38,6 +38,8 @@ # include "hardware/rt106x/imxrt106x_ccm.h" #elif defined(CONFIG_ARCH_FAMILY_IMXRT117x) # include "hardware/rt117x/imxrt117x_ccm.h" +#elif defined(CONFIG_ARCH_FAMILY_IMXRT118x) +# include "hardware/rt118x/imxrt118x_ccm.h" #else # error Unrecognized i.MX RT architecture #endif diff --git a/arch/arm/src/imxrt/hardware/imxrt_dcdc.h b/arch/arm/src/imxrt/hardware/imxrt_dcdc.h index 2569b4f05f246..e7ef6a1bf9377 100644 --- a/arch/arm/src/imxrt/hardware/imxrt_dcdc.h +++ b/arch/arm/src/imxrt/hardware/imxrt_dcdc.h @@ -136,4 +136,44 @@ #define DCDC_REG3_DISABLE_STEP (1 << 30) /* Bit 30: Disable stepping */ /* Bit 31: Reserved */ +#ifdef CONFIG_ARCH_FAMILY_IMXRT118x + +/* i.MX RT118x adds per-core target control registers (IMXRT1180RM Rev. 10 + * sec. 22.7.1.11 / 22.7.1.13). Both cores share a single VDD1P0 rail: the + * DCDC applies the *higher* of the TRG_SW_0 and TRG_SW_1 voltage targets, + * so a core that needs the higher voltage must raise both. + */ + +#define IMXRT_DCDC_TRG_SW_0_OFFSET 0x0024 /* Target SW control, CORE 0 */ +#define IMXRT_DCDC_TRG_SW_1_OFFSET 0x0034 /* Target SW control, CORE 1 */ +#define IMXRT_DCDC_CURRENT_TRG_OFFSET 0x0018 /* Arbitrated target in use */ + +#define IMXRT_DCDC_TRG_SW_0 (IMXRT_DCDC_BASE + IMXRT_DCDC_TRG_SW_0_OFFSET) +#define IMXRT_DCDC_TRG_SW_1 (IMXRT_DCDC_BASE + IMXRT_DCDC_TRG_SW_1_OFFSET) +#define IMXRT_DCDC_CURRENT_TRG (IMXRT_DCDC_BASE + IMXRT_DCDC_CURRENT_TRG_OFFSET) + +/* TRG_SW_0 / TRG_SW_1 (reset value 0010_0C10h) */ + +#define DCDC_TRG_SW_VDD1P0CTRL_TRG_SHIFT (0) /* Bits 0-4: VDD1P0 run mode target */ +#define DCDC_TRG_SW_VDD1P0CTRL_TRG_MASK (0x1f << DCDC_TRG_SW_VDD1P0CTRL_TRG_SHIFT) +# define DCDC_TRG_SW_VDD1P0CTRL_TRG(n) ((uint32_t)(n) << DCDC_TRG_SW_VDD1P0CTRL_TRG_SHIFT) +#define DCDC_TRG_SW_VDD1P8CTRL_TRG_SHIFT (8) /* Bits 8-12: VDD1P8 run mode target */ +#define DCDC_TRG_SW_VDD1P8CTRL_TRG_MASK (0x1f << DCDC_TRG_SW_VDD1P8CTRL_TRG_SHIFT) +#define DCDC_TRG_SW_VDD1P0CTRL_LP_TRG_SHIFT (16) /* Bits 16-20: VDD1P0 low power target */ +#define DCDC_TRG_SW_VDD1P0CTRL_LP_TRG_MASK (0x1f << DCDC_TRG_SW_VDD1P0CTRL_LP_TRG_SHIFT) +#define DCDC_TRG_SW_LP_EN_1P0 (1 << 31) /* Bit 31: Low power enable */ + +/* CURRENT_TRG: arbitrated target actually applied by the DCDC analog */ + +#define DCDC_CURRENT_TRG_VDD1P0CTRL_TRG_SHIFT (0) /* Bits 0-4 */ +#define DCDC_CURRENT_TRG_VDD1P0CTRL_TRG_MASK (0x1f << DCDC_CURRENT_TRG_VDD1P0CTRL_TRG_SHIFT) +#define DCDC_CURRENT_TRG_DCDC_UPDATING (1 << 15) /* Bit 15: change in progress */ + +/* VDD1P0 target encoding: 25 mV per step, 0x00 = 0.6 V, 0x10 = 1.0 V */ + +#define DCDC_1P0_TARGET_1P000V (0x10) +#define DCDC_1P0_TARGET_1P125V (0x15) /* HSRUN / OverDrive */ + +#endif /* CONFIG_ARCH_FAMILY_IMXRT118x */ + #endif /* __ARCH_ARM_SRC_IMXRT_HARDWARE_IMXRT_DCDC_H */ diff --git a/arch/arm/src/imxrt/hardware/imxrt_dmamux.h b/arch/arm/src/imxrt/hardware/imxrt_dmamux.h index 70742bcd236a6..03b43b154b513 100644 --- a/arch/arm/src/imxrt/hardware/imxrt_dmamux.h +++ b/arch/arm/src/imxrt/hardware/imxrt_dmamux.h @@ -39,6 +39,8 @@ #elif defined(CONFIG_ARCH_FAMILY_IMXRT117x) # include "hardware/rt117x/imxrt117x_dmamux.h" #define IMXRT_DMAMUX_BASE IMXRT_DMAMUX0_BASE +#elif defined(CONFIG_ARCH_FAMILY_IMXRT118x) +# include "hardware/rt118x/imxrt118x_dmamux.h" #else # error Unrecognized i.MX RT architecture #endif diff --git a/arch/arm/src/imxrt/hardware/imxrt_gpio.h b/arch/arm/src/imxrt/hardware/imxrt_gpio.h index 41b439f19f81a..a522be745e01c 100644 --- a/arch/arm/src/imxrt/hardware/imxrt_gpio.h +++ b/arch/arm/src/imxrt/hardware/imxrt_gpio.h @@ -37,6 +37,8 @@ # include "hardware/rt106x/imxrt106x_gpio.h" #elif defined(CONFIG_ARCH_FAMILY_IMXRT117x) # include "hardware/rt117x/imxrt117x_gpio.h" +#elif defined(CONFIG_ARCH_FAMILY_IMXRT118x) +# include "hardware/imxrt_memorymap.h" #else # error Unrecognized i.MX RT architecture #endif diff --git a/arch/arm/src/imxrt/hardware/imxrt_iomuxc.h b/arch/arm/src/imxrt/hardware/imxrt_iomuxc.h index 8d307b47e00d1..091006564507f 100644 --- a/arch/arm/src/imxrt/hardware/imxrt_iomuxc.h +++ b/arch/arm/src/imxrt/hardware/imxrt_iomuxc.h @@ -30,10 +30,13 @@ #include /* IMXRT117X IOMUX Differs too much from IMXRT10XX - * hence we use a VER2 driver + * hence we use a VER2 driver. IMXRT118x uses another (generation 3) + * IOMUXC IP; that is IMXRT_IOMUX_VER3. */ -#ifdef CONFIG_IMXRT_IOMUX_VER2 +#ifdef CONFIG_IMXRT_IOMUX_VER3 +#include "imxrt_iomuxc_ver3.h" +#elif defined(CONFIG_IMXRT_IOMUX_VER2) #include "imxrt_iomuxc_ver2.h" #else #include "imxrt_iomuxc_ver1.h" diff --git a/arch/arm/src/imxrt/hardware/imxrt_memorymap.h b/arch/arm/src/imxrt/hardware/imxrt_memorymap.h index 0aaa60c2d2d6e..be9fb92135c7e 100644 --- a/arch/arm/src/imxrt/hardware/imxrt_memorymap.h +++ b/arch/arm/src/imxrt/hardware/imxrt_memorymap.h @@ -37,6 +37,8 @@ # include "hardware/rt106x/imxrt106x_memorymap.h" #elif defined(CONFIG_ARCH_FAMILY_IMXRT117x) # include "hardware/rt117x/imxrt117x_memorymap.h" +#elif defined(CONFIG_ARCH_FAMILY_IMXRT118x) +# include "hardware/rt118x/imxrt118x_memorymap.h" #else # error Unrecognized i.MX RT architecture #endif diff --git a/arch/arm/src/imxrt/hardware/imxrt_ocotp.h b/arch/arm/src/imxrt/hardware/imxrt_ocotp.h index 6a310a7b483cc..18dda8053abbd 100644 --- a/arch/arm/src/imxrt/hardware/imxrt_ocotp.h +++ b/arch/arm/src/imxrt/hardware/imxrt_ocotp.h @@ -36,6 +36,17 @@ #include #include "hardware/imxrt_memorymap.h" +#ifdef CONFIG_ARCH_FAMILY_IMXRT118x + +/* On chips fronted by the EdgeLock Enclave (e.g. RT1180) the OCOTP + * register layout differs and only a shadow-read window is exposed to + * the SoC; see hardware/rt118x/imxrt118x_ocotp.h for details. + */ + +# include "hardware/rt118x/imxrt118x_ocotp.h" + +#else + /**************************************************************************** * Pre-processor Definitions ****************************************************************************/ @@ -425,4 +436,6 @@ #define OCOTP_LOCK_FIELD_RETURN_MASK (15 << OCOTP_LOCK_FIELD_RETURN_SHIFT) # define OCOTP_LOCK_FIELD_RETURN(n) ((uint32_t)(n) << OCOTP_LOCK_FIELD_RETURN_SHIFT) +#endif /* CONFIG_ARCH_FAMILY_IMXRT118x */ + #endif /* __ARCH_ARM_SRC_IMXRT_HARDWARE_IMXRT_OCOTP_H */ diff --git a/arch/arm/src/imxrt/hardware/imxrt_pinmux.h b/arch/arm/src/imxrt/hardware/imxrt_pinmux.h index 2518ea4f4fa15..1c66fb1edc71c 100644 --- a/arch/arm/src/imxrt/hardware/imxrt_pinmux.h +++ b/arch/arm/src/imxrt/hardware/imxrt_pinmux.h @@ -37,6 +37,8 @@ # include "hardware/rt106x/imxrt106x_pinmux.h" #elif defined(CONFIG_ARCH_FAMILY_IMXRT117x) # include "hardware/rt117x/imxrt117x_pinmux.h" +#elif defined(CONFIG_ARCH_FAMILY_IMXRT118x) +# include "hardware/rt118x/imxrt118x_pinmux.h" #else # error Unrecognized i.MX RT architecture #endif diff --git a/arch/arm/src/imxrt/hardware/imxrt_usbphy.h b/arch/arm/src/imxrt/hardware/imxrt_usbphy.h index 0e703a5ac8107..ea6d4ef932d69 100644 --- a/arch/arm/src/imxrt/hardware/imxrt_usbphy.h +++ b/arch/arm/src/imxrt/hardware/imxrt_usbphy.h @@ -36,11 +36,14 @@ #define IMXRT_USBPHY_BASE_OFFSET 0x1000 /* USB1 PHY Base */ -/* Simple hack to get iMXRT117x working with same macro */ +/* Simple hack to get iMXRT117x/iMXRT118x working with same macro */ #ifdef CONFIG_ARCH_FAMILY_IMXRT117x # define IMXRT_ANATOP_BASE 0x40433000 /* ANATOP doesn't exist on rt117x, it is used this way here only to make the code compatible */ # define IMXRT_USBPHY_SHIFT 0x4000 +#elif defined(CONFIG_ARCH_FAMILY_IMXRT118x) +# define IMXRT_ANATOP_BASE (IMXRT_USBPHY1_BASE - IMXRT_USBPHY_BASE_OFFSET) /* ANATOP doesn't exist on rt118x */ +# define IMXRT_USBPHY_SHIFT 0x10000 #else # define IMXRT_USBPHY_SHIFT 0x1000 #endif diff --git a/arch/arm/src/imxrt/hardware/imxrt_xbar.h b/arch/arm/src/imxrt/hardware/imxrt_xbar.h index 675f5191960ec..27bc237bbbf22 100644 --- a/arch/arm/src/imxrt/hardware/imxrt_xbar.h +++ b/arch/arm/src/imxrt/hardware/imxrt_xbar.h @@ -39,6 +39,8 @@ # include "hardware/rt106x/imxrt106x_xbar.h" #elif defined(CONFIG_ARCH_FAMILY_IMXRT117x) # include "hardware/rt117x/imxrt117x_xbar.h" +#elif defined(CONFIG_ARCH_FAMILY_IMXRT118x) +# include "hardware/rt118x/imxrt118x_xbar.h" #else # error Unrecognized i.MX RT architecture #endif diff --git a/arch/arm/src/imxrt/hardware/rt118x/imxrt118x_anadig.h b/arch/arm/src/imxrt/hardware/rt118x/imxrt118x_anadig.h new file mode 100644 index 0000000000000..bf4bb09316e77 --- /dev/null +++ b/arch/arm/src/imxrt/hardware/rt118x/imxrt118x_anadig.h @@ -0,0 +1,200 @@ +/**************************************************************************** + * arch/arm/src/imxrt/hardware/rt118x/imxrt118x_anadig.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_IMXRT_HARDWARE_RT118X_IMXRT118X_ANADIG_H +#define __ARCH_ARM_SRC_IMXRT_HARDWARE_RT118X_IMXRT118X_ANADIG_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include "hardware/imxrt_memorymap.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* ANADIG PLL registers (IMXRT1180RM Ch. 41). Offsets are relative to + * IMXRT_ANADIG_PLL_BASE (0x4448_0000). The M7 core clock is fed from + * ARM_PLL; the CM33 side and most peripherals are fed from SYS_PLL2/3. + */ + +#define IMXRT_ANADIG_PLL_ARM_CTRL (IMXRT_ANADIG_PLL_BASE + 0x4000) +#define IMXRT_ANADIG_PLL_SYS3_CTRL (IMXRT_ANADIG_PLL_BASE + 0x4010) +#define IMXRT_ANADIG_PLL_SYS3_UPDATE (IMXRT_ANADIG_PLL_BASE + 0x4020) +#define IMXRT_ANADIG_PLL_SYS3_PFD (IMXRT_ANADIG_PLL_BASE + 0x4030) +#define IMXRT_ANADIG_PLL_SYS2_CTRL (IMXRT_ANADIG_PLL_BASE + 0x4040) +#define IMXRT_ANADIG_PLL_SYS2_UPDATE (IMXRT_ANADIG_PLL_BASE + 0x4050) +#define IMXRT_ANADIG_PLL_SYS2_SS (IMXRT_ANADIG_PLL_BASE + 0x4060) +#define IMXRT_ANADIG_PLL_SYS2_PFD (IMXRT_ANADIG_PLL_BASE + 0x4070) +#define IMXRT_ANADIG_PLL_SYS2_MFN (IMXRT_ANADIG_PLL_BASE + 0x4080) +#define IMXRT_ANADIG_PLL_SYS2_MFI (IMXRT_ANADIG_PLL_BASE + 0x4090) +#define IMXRT_ANADIG_PLL_SYS2_MFD (IMXRT_ANADIG_PLL_BASE + 0x40a0) +#define IMXRT_ANADIG_PLL_SYS1_CTRL (IMXRT_ANADIG_PLL_BASE + 0x4100) +#define IMXRT_ANADIG_PLL_AUDIO_CTRL (IMXRT_ANADIG_PLL_BASE + 0x4200) +#define IMXRT_ANADIG_PLL_VIDEO_CTRL (IMXRT_ANADIG_PLL_BASE + 0x4300) + +/* ARM_PLL_CTRL bit fields (IMXRT1180RM Rev. 10 sec. 24.5.1.1, reset + * value 4000_00A6h). + * + * Fout = 24 MHz * DIV_SELECT / (2 * post_div) + * + * where post_div is the divider selected by POST_DIV_SEL and DIV_SELECT + * has a valid range of 104-208. + */ + +#define ANADIG_PLL_ARM_DIV_SELECT_SHIFT (0) +#define ANADIG_PLL_ARM_DIV_SELECT_MASK (0xffu << ANADIG_PLL_ARM_DIV_SELECT_SHIFT) +#define ANADIG_PLL_ARM_DIV_SELECT(x) (((x) << ANADIG_PLL_ARM_DIV_SELECT_SHIFT) & \ + ANADIG_PLL_ARM_DIV_SELECT_MASK) +#define ANADIG_PLL_ARM_HOLD_RING_OFF (1u << 12) +#define ANADIG_PLL_ARM_POWERUP (1u << 13) +#define ANADIG_PLL_ARM_ENABLE_CLK (1u << 14) +#define ANADIG_PLL_ARM_POST_DIV_SEL_SHIFT (15) +#define ANADIG_PLL_ARM_POST_DIV_SEL_MASK (0x3u << ANADIG_PLL_ARM_POST_DIV_SEL_SHIFT) +#define ANADIG_PLL_ARM_POST_DIV_SEL(x) (((x) << ANADIG_PLL_ARM_POST_DIV_SEL_SHIFT) & \ + ANADIG_PLL_ARM_POST_DIV_SEL_MASK) +# define ANADIG_PLL_ARM_POST_DIV_2 (0) /* post_div = 2 */ +# define ANADIG_PLL_ARM_POST_DIV_4 (1) /* post_div = 4 */ +# define ANADIG_PLL_ARM_POST_DIV_8 (2) /* post_div = 8 */ +# define ANADIG_PLL_ARM_POST_DIV_1 (3) /* post_div = 1 */ +#define ANADIG_PLL_ARM_BYPASS (1u << 17) +#define ANADIG_PLL_ARM_STABLE (1u << 29) +#define ANADIG_PLL_ARM_GATE (1u << 30) +#define ANADIG_PLL_ARM_CONTROL_MODE (1u << 31) /* 0: software, 1: GPC */ + +/* ANADIG PMU registers (IMXRT1180RM Rev. 10 sec. 24.5.1). Offsets are + * relative to the ANADIG base 0x4448_0000, same as the PLL block above. + */ + +#define IMXRT_ANADIG_PMU_BIAS_CTRL (IMXRT_ANADIG_PLL_BASE + 0x4600) +#define IMXRT_ANADIG_PMU_BIAS_CTRL2 (IMXRT_ANADIG_PLL_BASE + 0x4610) +#define IMXRT_ANADIG_PMU_LDO_PLL (IMXRT_ANADIG_PLL_BASE + 0x4640) + +/* PMU_BIAS_CTRL bit fields (reset value 0000_8000h) */ + +#define ANADIG_PMU_BIAS_CTRL_WB_CFG_1P8_SHIFT (0) +#define ANADIG_PMU_BIAS_CTRL_WB_CFG_1P8_MASK (0x1fffu << 0) +#define ANADIG_PMU_BIAS_CTRL_WB_CFG_1P8(x) (((x) << 0) & \ + ANADIG_PMU_BIAS_CTRL_WB_CFG_1P8_MASK) + +/* WB_CFG_1P8 sub-fields. Each bit range below is described individually by + * IMXRT1180RM Rev. 10 sec. 24.4.1.25 under the WB_CFG_1P8 field. + */ + +# define ANADIG_PMU_WB_CFG_PWELL_ONLY (1u << 0) /* 0: PWELL and NWELL on + * 1: PWELL only, NWELL + * kept disabled */ +# define ANADIG_PMU_WB_CFG_NWELL_FBB (1u << 1) /* 0: NWELL to supply, + * RVT CORE (RBB) + * 1: NWELL to supply, + * LVT CORE (FBB) */ + +/* Bits 4-2: size of the bias area, i.e. the charge pump current budget. */ + +# define ANADIG_PMU_WB_CFG_AREA_SHIFT (2) +# define ANADIG_PMU_WB_CFG_AREA_MASK (0x7u << 2) +# define ANADIG_PMU_WB_CFG_AREA(x) (((x) << 2) & \ + ANADIG_PMU_WB_CFG_AREA_MASK) +# define ANADIG_PMU_WB_AREA_180UA (0) /* 6.00 mm2 at 125C */ +# define ANADIG_PMU_WB_AREA_150UA (1) /* 5.00 mm2 at 125C */ +# define ANADIG_PMU_WB_AREA_120UA (2) /* 4.00 mm2 at 125C */ +# define ANADIG_PMU_WB_AREA_90UA (3) /* 3.00 mm2 at 125C */ +# define ANADIG_PMU_WB_AREA_60UA (4) /* 2.00 mm2 at 125C */ +# define ANADIG_PMU_WB_AREA_45UA (5) /* 0.15 mm2 at 125C */ +# define ANADIG_PMU_WB_AREA_30UA (6) /* 1.00 mm2 at 125C */ +# define ANADIG_PMU_WB_AREA_15UA (7) /* 0.50 mm2 at 125C */ + +/* Bit 5: when clear the charge pump frequency adapts each half cycle and + * bits 8-6 give only the minimum. When set the frequency is fixed at the + * value selected by bits 8-6. + */ + +# define ANADIG_PMU_WB_CFG_ADAPTIVE_DIS (1u << 5) + +/* Bits 8-6: charge pump oscillator frequency. */ + +# define ANADIG_PMU_WB_CFG_OSC_SHIFT (6) +# define ANADIG_PMU_WB_CFG_OSC_MASK (0x7u << 6) +# define ANADIG_PMU_WB_CFG_OSC(x) (((x) << 6) & \ + ANADIG_PMU_WB_CFG_OSC_MASK) +# define ANADIG_PMU_WB_OSC_DIV128 (0) +# define ANADIG_PMU_WB_OSC_DIV64 (1) +# define ANADIG_PMU_WB_OSC_DIV32 (2) +# define ANADIG_PMU_WB_OSC_DIV16 (3) +# define ANADIG_PMU_WB_OSC_DIV8 (4) +# define ANADIG_PMU_WB_OSC_DIV2 (6) +# define ANADIG_PMU_WB_OSC_FULL (7) /* osc_freq */ + +/* Bit 9 and bits 11-10: adaptive clock source and frequency reduction. */ + +# define ANADIG_PMU_WB_CFG_TRIM_SYNC (1u << 9) +# define ANADIG_PMU_WB_CFG_FREQ_RED_SHIFT (10) +# define ANADIG_PMU_WB_CFG_FREQ_RED_MASK (0x3u << 10) +# define ANADIG_PMU_WB_CFG_PULLDOWN_EN (1u << 12) /* Pull-down option */ +#define ANADIG_PMU_BIAS_CTRL_WB_VDD_SEL_1P8 (1u << 14) +#define ANADIG_PMU_BIAS_CTRL_FBB_M7_STBY_EN (1u << 15) +#define ANADIG_PMU_BIAS_CTRL_WB_PW_LVL_1P8_SHIFT (24) +#define ANADIG_PMU_BIAS_CTRL_WB_PW_LVL_1P8_MASK (0xfu << 24) +#define ANADIG_PMU_BIAS_CTRL_WB_PW_LVL_1P8(x) (((x) << 24) & \ + ANADIG_PMU_BIAS_CTRL_WB_PW_LVL_1P8_MASK) +#define ANADIG_PMU_BIAS_CTRL_WB_NW_LVL_1P8_SHIFT (28) +#define ANADIG_PMU_BIAS_CTRL_WB_NW_LVL_1P8_MASK (0xfu << 28) +#define ANADIG_PMU_BIAS_CTRL_WB_NW_LVL_1P8(x) (((x) << 28) & \ + ANADIG_PMU_BIAS_CTRL_WB_NW_LVL_1P8_MASK) + +/* PMU_BIAS_CTRL2 bit fields (reset value 0000_0000h) */ + +#define ANADIG_PMU_BIAS_CTRL2_WB_PWR_SW_EN_1P8 (1u << 12) +#define ANADIG_PMU_BIAS_CTRL2_WB_ADJ_1P8_SHIFT (13) +#define ANADIG_PMU_BIAS_CTRL2_WB_ADJ_1P8_MASK (0xffu << 13) +#define ANADIG_PMU_BIAS_CTRL2_WB_EN (1u << 24) +#define ANADIG_PMU_BIAS_CTRL2_WB_OK (1u << 26) + +/* ANADIG OSC registers (IMXRT1180RM Ch. 41) */ + +#define IMXRT_ANADIG_OSC_RC24M_CTRL (IMXRT_ANADIG_OSC_BASE + 0x3310) +#define IMXRT_ANADIG_OSC_24M_CTRL (IMXRT_ANADIG_OSC_BASE + 0x3320) +#define IMXRT_ANADIG_OSC_400M_CTRL1 (IMXRT_ANADIG_OSC_BASE + 0x3350) + +/* PHY_LDO registers (IMXRT1180RM Ch. 41. Physical: 0x4448_4680). Each + * has RW/SET/CLR/TOG aliases. + */ + +#define IMXRT_PHY_LDO_CTRL0_BASE (IMXRT_ANADIG_LDO_BASE + 0x680) +#define IMXRT_PHY_LDO_CTRL0_RW (IMXRT_PHY_LDO_CTRL0_BASE + 0x0) +#define IMXRT_PHY_LDO_CTRL0_SET (IMXRT_PHY_LDO_CTRL0_BASE + 0x4) +#define IMXRT_PHY_LDO_CTRL0_CLR (IMXRT_PHY_LDO_CTRL0_BASE + 0x8) +#define IMXRT_PHY_LDO_CTRL0_TOG (IMXRT_PHY_LDO_CTRL0_BASE + 0xc) + +/* PHY_LDO_CTRL0 bit fields */ + +#define PHY_LDO_CTRL0_LINREG_EN (1u << 0) /* Enable linear regulator */ +#define PHY_LDO_CTRL0_LINREG_PWRUPLOAD_DIS (1u << 1) +#define PHY_LDO_CTRL0_LINREG_ILIMIT_EN (1u << 2) /* Enable current-limit protection */ +#define PHY_LDO_CTRL0_LINREG_OUTPUT_TRG_SHIFT (4) /* Output voltage trim */ +#define PHY_LDO_CTRL0_LINREG_OUTPUT_TRG_MASK (0x1fu << PHY_LDO_CTRL0_LINREG_OUTPUT_TRG_SHIFT) +#define PHY_LDO_CTRL0_LINREG_OUTPUT_TRG(x) (((x) << PHY_LDO_CTRL0_LINREG_OUTPUT_TRG_SHIFT) & \ + PHY_LDO_CTRL0_LINREG_OUTPUT_TRG_MASK) +#define PHY_LDO_CTRL0_LINREG_PHY_ISO_B (1u << 15) /* Release PHY isolation */ + +#endif /* __ARCH_ARM_SRC_IMXRT_HARDWARE_RT118X_IMXRT118X_ANADIG_H */ diff --git a/arch/arm/src/imxrt/hardware/rt118x/imxrt118x_blkctrl.h b/arch/arm/src/imxrt/hardware/rt118x/imxrt118x_blkctrl.h new file mode 100644 index 0000000000000..3e3208939f52a --- /dev/null +++ b/arch/arm/src/imxrt/hardware/rt118x/imxrt118x_blkctrl.h @@ -0,0 +1,137 @@ +/**************************************************************************** + * arch/arm/src/imxrt/hardware/rt118x/imxrt118x_blkctrl.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_IMXRT_HARDWARE_RT118X_IMXRT118X_BLKCTRL_H +#define __ARCH_ARM_SRC_IMXRT_HARDWARE_RT118X_IMXRT118X_BLKCTRL_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include "hardware/imxrt_memorymap.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* BLK_CTRL_S_AONMIX registers (IMXRT1180RM Ch. 15.4.1). + * + * The AON secure block controls the CM33 and CM7 interrupt masks, initial + * vector table pointers, low-power handshakes, DAP access sticky bits and + * NMI routing. Bases for the non-secure alias are provided in + * hardware/rt118x/imxrt118x_memorymap.h. + */ + +#define IMXRT_AON_CM33_IRQ_MASK(n) (IMXRT_BLK_CTRL_S_AONMIX_BASE + 0x000 + \ + ((n) << 2)) /* 8 x 32b IRQ mask */ +#define IMXRT_AON_CM7_IRQ_MASK(n) (IMXRT_BLK_CTRL_S_AONMIX_BASE + 0x020 + \ + ((n) << 2)) +#define IMXRT_AON_EDGELOCK_RESET_MASK (IMXRT_BLK_CTRL_S_AONMIX_BASE + 0x058) +#define IMXRT_AON_EDGELOCK_IRQ_MASK (IMXRT_BLK_CTRL_S_AONMIX_BASE + 0x05c) +#define IMXRT_AON_M33_CFG (IMXRT_BLK_CTRL_S_AONMIX_BASE + 0x060) +#define IMXRT_AON_M33_INITSVTOR (IMXRT_BLK_CTRL_S_AONMIX_BASE + 0x064) +#define IMXRT_AON_M33_INITNSVTOR (IMXRT_BLK_CTRL_S_AONMIX_BASE + 0x068) +#define IMXRT_AON_M7_CFG (IMXRT_BLK_CTRL_S_AONMIX_BASE + 0x080) +#define IMXRT_AON_AXBS_AON_CTRL (IMXRT_BLK_CTRL_S_AONMIX_BASE + 0x090) +#define IMXRT_AON_DAP_ACCESS_STKYBIT (IMXRT_BLK_CTRL_S_AONMIX_BASE + 0x100) +#define IMXRT_AON_LP_HANDSHAKE (IMXRT_BLK_CTRL_S_AONMIX_BASE + 0x110) +#define IMXRT_AON_EDGELOCK_HALT_ST (IMXRT_BLK_CTRL_S_AONMIX_BASE + 0x114) +#define IMXRT_AON_ECC_MEM_INIT (IMXRT_BLK_CTRL_S_AONMIX_BASE + 0x120) +#define IMXRT_AON_IOMUXC_DOMAIN_CFG (IMXRT_BLK_CTRL_S_AONMIX_BASE + 0x148) +#define IMXRT_AON_IOMUXC_AON_DOMAIN_CFG (IMXRT_BLK_CTRL_S_AONMIX_BASE + 0x14c) +#define IMXRT_AON_NMI_CTRL (IMXRT_BLK_CTRL_S_AONMIX_BASE + 0x154) + +/* M33_CFG bit fields */ + +#define AON_M33_CFG_LOCK_NSVTOR (1u << 0) +#define AON_M33_CFG_LOCK_SVTOR (1u << 1) +#define AON_M33_CFG_TCM_SIZE_SHIFT (3) +#define AON_M33_CFG_TCM_SIZE_MASK (0x3u << AON_M33_CFG_TCM_SIZE_SHIFT) + +/* M7_CFG bit fields */ + +#define AON_M7_CFG_TCM_SIZE_SHIFT (0) +#define AON_M7_CFG_TCM_SIZE_MASK (0x7u) +#define AON_M7_CFG_WAIT (1u << 4) +#define AON_M7_CFG_CORECLK_FORCE_ON (1u << 5) +#define AON_M7_CFG_HCLK_FORCE_ON (1u << 6) +#define AON_M7_CFG_INITVTOR_SHIFT (7) +#define AON_M7_CFG_INITVTOR_MASK (0x01ffffffu << AON_M7_CFG_INITVTOR_SHIFT) +#define AON_M7_CFG_INITVTOR(x) (((x) << AON_M7_CFG_INITVTOR_SHIFT) & \ + AON_M7_CFG_INITVTOR_MASK) + +/* NMI_CTRL bit fields */ + +#define AON_NMI_CTRL_M7_NMI_MASK (1u << 0) +#define AON_NMI_CTRL_M33_NMI_MASK (1u << 1) + +/* SRC general registers (IMXRT1180RM Ch. 27) *******************************/ + +#define IMXRT_SRC_AUTHEN_CTRL (IMXRT_SRC_BASE + 0x004) +#define IMXRT_SRC_SCR (IMXRT_SRC_BASE + 0x010) /* Control */ +#define IMXRT_SRC_SRTMR (IMXRT_SRC_BASE + 0x014) /* Reset Trigger */ +#define IMXRT_SRC_SRMASK (IMXRT_SRC_BASE + 0x018) /* Reset Mask */ +#define IMXRT_SRC_SBMR1 (IMXRT_SRC_BASE + 0x040) /* Boot Mode 1 */ +#define IMXRT_SRC_SBMR2 (IMXRT_SRC_BASE + 0x044) /* Boot Mode 2 */ +#define IMXRT_SRC_SRSR_BBSM (IMXRT_SRC_BASE + 0x04c) +#define IMXRT_SRC_SRSR (IMXRT_SRC_BASE + 0x050) /* Reset Status */ + +/* SRC.SCR bit fields */ + +#define SRC_SCR_BT_RELEASE_M7 (1u << 0) /* Release M7 from boot hold */ + +/* SRC MIX_SLICE registers (IMXRT1180RM Ch. 27, per power domain slice). + * Bases for each slice (AON/WAKEUP/MEGA/NETC/CM33/CM7 platforms) are in + * hardware/rt118x/imxrt118x_memorymap.h. + */ + +#define IMXRT_SRC_SLICE_AUTHEN_CTRL(base) ((base) + 0x004) +#define IMXRT_SRC_SLICE_SW_CTRL(base) ((base) + 0x010) +#define IMXRT_SRC_SLICE_FUNC_STAT(base) ((base) + 0x014) +#define IMXRT_SRC_SLICE_UPI_STAT_0(base) ((base) + 0x020) +#define IMXRT_SRC_SLICE_UPI_STAT_1(base) ((base) + 0x024) +#define IMXRT_SRC_SLICE_LPM_SETTING_0(base) ((base) + 0x030) +#define IMXRT_SRC_SLICE_LPM_SETTING_1(base) ((base) + 0x034) +#define IMXRT_SRC_SLICE_LPM_SETTING_2(base) ((base) + 0x038) +#define IMXRT_SRC_SLICE_EDGELOCK_HDSK_CTRL(base) ((base) + 0x040) +#define IMXRT_SRC_SLICE_EDGELOCK_HDSK_STAT(base) ((base) + 0x044) +#define IMXRT_SRC_SLICE_PSW_CTRL(base) ((base) + 0x05c) +#define IMXRT_SRC_SLICE_PSW_STAT(base) ((base) + 0x060) +#define IMXRT_SRC_SLICE_MLPL_CFG(base) ((base) + 0x084) +#define IMXRT_SRC_SLICE_MLPL_STAT(base) ((base) + 0x088) + +/* SLICE_SW_CTRL bit fields */ + +#define SRC_SLICE_SW_CTRL_PSW_OFF_SOFT (1u << 0) /* 1 = software power off */ +#define SRC_SLICE_SW_CTRL_RST_CTRL_SOFT (1u << 2) /* 1 = software reset assert */ +#define SRC_SLICE_SW_CTRL_ISO_ON_SOFT (1u << 4) /* 1 = software isolation on */ +#define SRC_SLICE_SW_CTRL_EDGELOCK_HDSK_SOFT (1u << 6) /* Edgelock handshake */ +#define SRC_SLICE_SW_CTRL_PDN_SOFT (1u << 31) /* 1 = SW power-down sequence */ + +/* FUNC_STAT bit fields (all read-only) */ + +#define SRC_SLICE_FUNC_STAT_PSW_STAT (1u << 0) /* 0 = power on, 1 = power off */ +#define SRC_SLICE_FUNC_STAT_RST_STAT (1u << 2) /* 0 = reset held, 1 = released */ +#define SRC_SLICE_FUNC_STAT_ISO_STAT (1u << 4) /* 0 = isolation off */ +#define SRC_SLICE_FUNC_STAT_EDGELOCK_HDSK (1u << 6) /* Edgelock handshake done */ + +#endif /* __ARCH_ARM_SRC_IMXRT_HARDWARE_RT118X_IMXRT118X_BLKCTRL_H */ diff --git a/arch/arm/src/imxrt/hardware/rt118x/imxrt118x_ccm.h b/arch/arm/src/imxrt/hardware/rt118x/imxrt118x_ccm.h new file mode 100644 index 0000000000000..8928c5e58262a --- /dev/null +++ b/arch/arm/src/imxrt/hardware/rt118x/imxrt118x_ccm.h @@ -0,0 +1,495 @@ +/**************************************************************************** + * arch/arm/src/imxrt/hardware/rt118x/imxrt118x_ccm.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_IMXRT_HARDWARE_RT118X_IMXRT118X_CCM_H +#define __ARCH_ARM_SRC_IMXRT_HARDWARE_RT118X_IMXRT118X_CCM_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include "hardware/imxrt_memorymap.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Register offsets *********************************************************/ + +#define IMXRT_CCM_CR_CTRL_OFFSET(n) (0x0000 + ((n) << 7)) +#define IMXRT_CCM_CR_CTRL_SET_OFFSET(n) (0x0004 + ((n) << 7)) +#define IMXRT_CCM_CR_CTRL_CLR_OFFSET(n) (0x0008 + ((n) << 7)) +#define IMXRT_CCM_CR_CTRL_TOG_OFFSET(n) (0x000c + ((n) << 7)) +#define IMXRT_CCM_CR_STAT0_OFFSET(n) (0x0020 + ((n) << 7)) +#define IMXRT_CCM_CR_AUTH_OFFSET(n) (0x0030 + ((n) << 7)) + +#define IMXRT_CCM_LPCG_DIR_OFFSET(n) (0x8000 + ((n) << 6)) +#define IMXRT_CCM_LPCG_STAT0_OFFSET(n) (0x8020 + ((n) << 6)) +#define IMXRT_CCM_LPCG_AUTH_OFFSET(n) (0x8030 + ((n) << 6)) + +/* Register addresses *******************************************************/ + +#define IMXRT_CCM_CR_CTRL(n) \ + (IMXRT_CCM_BASE + IMXRT_CCM_CR_CTRL_OFFSET(n)) +#define IMXRT_CCM_CR_CTRL_SET(n) \ + (IMXRT_CCM_BASE + IMXRT_CCM_CR_CTRL_SET_OFFSET(n)) +#define IMXRT_CCM_CR_CTRL_CLR(n) \ + (IMXRT_CCM_BASE + IMXRT_CCM_CR_CTRL_CLR_OFFSET(n)) +#define IMXRT_CCM_CR_CTRL_TOG(n) \ + (IMXRT_CCM_BASE + IMXRT_CCM_CR_CTRL_TOG_OFFSET(n)) +#define IMXRT_CCM_CR_STAT0(n) \ + (IMXRT_CCM_BASE + IMXRT_CCM_CR_STAT0_OFFSET(n)) +#define IMXRT_CCM_CR_AUTH(n) \ + (IMXRT_CCM_BASE + IMXRT_CCM_CR_AUTH_OFFSET(n)) + +#define IMXRT_CCM_LPCG_DIR(n) \ + (IMXRT_CCM_BASE + IMXRT_CCM_LPCG_DIR_OFFSET(n)) +#define IMXRT_CCM_LPCG_STAT0(n) \ + (IMXRT_CCM_BASE + IMXRT_CCM_LPCG_STAT0_OFFSET(n)) +#define IMXRT_CCM_LPCG_AUTH(n) \ + (IMXRT_CCM_BASE + IMXRT_CCM_LPCG_AUTH_OFFSET(n)) + +/* Register bit definitions *************************************************/ + +/* Clock root control (CLOCK_ROOTn_CONTROL) */ + +#define CCM_CR_CTRL_DIV_SHIFT (0) +#define CCM_CR_CTRL_DIV_MASK (0xff << CCM_CR_CTRL_DIV_SHIFT) +# define CCM_CR_CTRL_DIV(n) (((n) - 1) << CCM_CR_CTRL_DIV_SHIFT) +#define CCM_CR_CTRL_MUX_SHIFT (8) +#define CCM_CR_CTRL_MUX_MASK (0x03 << CCM_CR_CTRL_MUX_SHIFT) +# define CCM_CR_CTRL_MUX_SRCSEL(n) ((n) << CCM_CR_CTRL_MUX_SHIFT) +#define CCM_CR_CTRL_OFF (1 << 24) + +/* Clock root working status (CLOCK_ROOTn_STATUS0) */ + +#define CCM_CR_STAT0_DIV_SHIFT (0) +#define CCM_CR_STAT0_DIV_MASK (0xff << CCM_CR_STAT0_DIV_SHIFT) +#define CCM_CR_STAT0_MUX_SHIFT (8) +#define CCM_CR_STAT0_MUX_MASK (0x03 << CCM_CR_STAT0_MUX_SHIFT) +#define CCM_CR_STAT0_OFF (1 << 24) +#define CCM_CR_STAT0_SLICE_BUSY (1 << 28) +#define CCM_CR_STAT0_CHANGING (1 << 31) + +/* Clock root access control (CLOCK_ROOTn_AUTHEN) */ + +#define CCM_CR_AUTH_TZ_USER (1u << 8) +#define CCM_CR_AUTH_TZ_NS (1u << 9) +#define CCM_CR_AUTH_LOCK_TZ (1u << 11) +#define CCM_CR_AUTH_LOCK_LIST (1u << 15) +#define CCM_CR_AUTH_WHITE_LIST_SHIFT (16) +#define CCM_CR_AUTH_WHITE_LIST_MASK (0xffffu << \ + CCM_CR_AUTH_WHITE_LIST_SHIFT) +# define CCM_CR_AUTH_DOMAIN(n) (1u << \ + (CCM_CR_AUTH_WHITE_LIST_SHIFT + (n))) + +/* Low-power clock gate (LPCGn_DIRECT / LPCGn_STATUS0) */ + +#define CCM_LPCG_DIR_ON (1 << 0) +#define CCM_LPCG_STAT0_ON (1 << 0) + +/* Clock roots (IMXRT1180RM Ch. 20, extracted from NXP MCUXpresso SDK + * clock_root_t enumeration). + */ + +#define CCM_CR_M7 (0) +#define CCM_CR_M33 (1) +#define CCM_CR_EDGELOCK (2) +#define CCM_CR_BUS_AON (3) +#define CCM_CR_BUS_WAKEUP (4) +#define CCM_CR_WAKEUP_AXI (5) +#define CCM_CR_SWO_TRACE (6) +#define CCM_CR_M33_SYSTICK (7) +#define CCM_CR_M7_SYSTICK (8) +#define CCM_CR_FLEXIO1 (9) +#define CCM_CR_FLEXIO2 (10) +#define CCM_CR_LPIT3 (11) +#define CCM_CR_LPTIMER1 (12) +#define CCM_CR_LPTIMER2 (13) +#define CCM_CR_LPTIMER3 (14) +#define CCM_CR_TPM2 (15) +#define CCM_CR_TPM4 (16) +#define CCM_CR_TPM5 (17) +#define CCM_CR_TPM6 (18) +#define CCM_CR_GPT1 (19) +#define CCM_CR_GPT2 (20) +#define CCM_CR_FLEXSPI1 (21) +#define CCM_CR_FLEXSPI2 (22) +#define CCM_CR_FLEXSPI_SLV (23) +#define CCM_CR_CAN1 (24) +#define CCM_CR_CAN2 (25) +#define CCM_CR_CAN3 (26) +#define CCM_CR_LPUART0102 (27) +#define CCM_CR_LPUART0304 (28) +#define CCM_CR_LPUART0506 (29) +#define CCM_CR_LPUART0708 (30) +#define CCM_CR_LPUART0910 (31) +#define CCM_CR_LPUART1112 (32) +#define CCM_CR_LPI2C0102 (33) +#define CCM_CR_LPI2C0304 (34) +#define CCM_CR_LPI2C0506 (35) +#define CCM_CR_LPSPI0102 (36) +#define CCM_CR_LPSPI0304 (37) +#define CCM_CR_LPSPI0506 (38) + +/* On RT1180 the LPUART / LPI2C / LPSPI clock roots are shared between + * pairs of instances. Per-instance aliases keep source code that names + * individual LPUART1..12, LPI2C1..6 or LPSPI1..6 roots compatible with + * both RT117x and RT118x. + */ + +#define CCM_CR_LPUART1 CCM_CR_LPUART0102 +#define CCM_CR_LPUART2 CCM_CR_LPUART0102 +#define CCM_CR_LPUART3 CCM_CR_LPUART0304 +#define CCM_CR_LPUART4 CCM_CR_LPUART0304 +#define CCM_CR_LPUART5 CCM_CR_LPUART0506 +#define CCM_CR_LPUART6 CCM_CR_LPUART0506 +#define CCM_CR_LPUART7 CCM_CR_LPUART0708 +#define CCM_CR_LPUART8 CCM_CR_LPUART0708 +#define CCM_CR_LPUART9 CCM_CR_LPUART0910 +#define CCM_CR_LPUART10 CCM_CR_LPUART0910 +#define CCM_CR_LPUART11 CCM_CR_LPUART1112 +#define CCM_CR_LPUART12 CCM_CR_LPUART1112 + +#define CCM_CR_LPI2C1 CCM_CR_LPI2C0102 +#define CCM_CR_LPI2C2 CCM_CR_LPI2C0102 +#define CCM_CR_LPI2C3 CCM_CR_LPI2C0304 +#define CCM_CR_LPI2C4 CCM_CR_LPI2C0304 +#define CCM_CR_LPI2C5 CCM_CR_LPI2C0506 +#define CCM_CR_LPI2C6 CCM_CR_LPI2C0506 + +#define CCM_CR_LPSPI1 CCM_CR_LPSPI0102 +#define CCM_CR_LPSPI2 CCM_CR_LPSPI0102 +#define CCM_CR_LPSPI3 CCM_CR_LPSPI0304 +#define CCM_CR_LPSPI4 CCM_CR_LPSPI0304 +#define CCM_CR_LPSPI5 CCM_CR_LPSPI0506 +#define CCM_CR_LPSPI6 CCM_CR_LPSPI0506 +#define CCM_CR_I3C1 (39) +#define CCM_CR_I3C2 (40) +#define CCM_CR_USDHC1 (41) +#define CCM_CR_USDHC2 (42) +#define CCM_CR_SEMC (43) +#define CCM_CR_ADC1 (44) +#define CCM_CR_ADC2 (45) +#define CCM_CR_ACMP (46) +#define CCM_CR_ECAT (47) +#define CCM_CR_ENET (48) +#define CCM_CR_TMR_1588 (49) +#define CCM_CR_NETC (50) +#define CCM_CR_MAC0 (51) +#define CCM_CR_MAC1 (52) +#define CCM_CR_MAC2 (53) +#define CCM_CR_MAC3 (54) +#define CCM_CR_MAC4 (55) +#define CCM_CR_SERDES0 (56) +#define CCM_CR_SERDES1 (57) +#define CCM_CR_SERDES2 (58) +#define CCM_CR_SERDES0_1G (59) +#define CCM_CR_SERDES1_1G (60) +#define CCM_CR_SERDES2_1G (61) +#define CCM_CR_XCELBUSX (62) +#define CCM_CR_XRIOCU4 (63) +#define CCM_CR_MCTRL (64) +#define CCM_CR_SAI1 (65) +#define CCM_CR_SAI2 (66) +#define CCM_CR_SAI3 (67) +#define CCM_CR_SAI4 (68) +#define CCM_CR_SPDIF (69) +#define CCM_CR_ASRC (70) +#define CCM_CR_MIC (71) +#define CCM_CR_CKO1 (72) +#define CCM_CR_CKO2 (73) + +/* Low-power clock gates (IMXRT1180RM Ch. 20, extracted from NXP MCUXpresso + * SDK clock_lpcg_t enumeration). + */ + +#define CCM_LPCG_M7 (0) +#define CCM_LPCG_M33 (1) +#define CCM_LPCG_EDGELOCK (2) +#define CCM_LPCG_SIM_AON (3) +#define CCM_LPCG_SIM_WAKEUP (4) +#define CCM_LPCG_SIM_MEGA (5) +#define CCM_LPCG_SIM_R (6) +#define CCM_LPCG_ANADIG (7) +#define CCM_LPCG_DCDC (8) +#define CCM_LPCG_SRC (9) +#define CCM_LPCG_CCM (10) +#define CCM_LPCG_GPC (11) +#define CCM_LPCG_ADC1 (12) +#define CCM_LPCG_ADC2 (13) +#define CCM_LPCG_DAC (14) +#define CCM_LPCG_ACMP1 (15) +#define CCM_LPCG_ACMP2 (16) +#define CCM_LPCG_ACMP3 (17) +#define CCM_LPCG_ACMP4 (18) +#define CCM_LPCG_WDOG1 (19) +#define CCM_LPCG_WDOG2 (20) +#define CCM_LPCG_WDOG3 (21) +#define CCM_LPCG_WDOG4 (22) +#define CCM_LPCG_WDOG5 (23) +#define CCM_LPCG_EWM0 (24) +#define CCM_LPCG_SEMA1 (25) +#define CCM_LPCG_SEMA2 (26) +#define CCM_LPCG_MU_A (27) +#define CCM_LPCG_MU_B (28) +#define CCM_LPCG_EDMA3 (29) +#define CCM_LPCG_EDMA4 (30) +#define CCM_LPCG_ROMCP (31) +#define CCM_LPCG_OCRAM1 (32) +#define CCM_LPCG_OCRAM2 (33) +#define CCM_LPCG_FLEXSPI1 (34) +#define CCM_LPCG_FLEXSPI2 (35) +#define CCM_LPCG_FLEXSPI_SLV (36) +#define CCM_LPCG_TRDC (37) +#define CCM_LPCG_OCOTP (38) +#define CCM_LPCG_SEMC (39) +#define CCM_LPCG_IEE (40) +#define CCM_LPCG_CSTRACE (41) +#define CCM_LPCG_CSSWO (42) +#define CCM_LPCG_IOMUXC1 (43) +#define CCM_LPCG_IOMUXC2 (44) +#define CCM_LPCG_GPIO1 (45) +#define CCM_LPCG_GPIO2 (46) +#define CCM_LPCG_GPIO3 (47) +#define CCM_LPCG_GPIO4 (48) +#define CCM_LPCG_GPIO5 (49) +#define CCM_LPCG_GPIO6 (50) +#define CCM_LPCG_FLEXIO1 (51) +#define CCM_LPCG_FLEXIO2 (52) +#define CCM_LPCG_LPIT1 (53) +#define CCM_LPCG_LPIT2 (54) +#define CCM_LPCG_LPIT3 (55) +#define CCM_LPCG_LPTMR1 (56) +#define CCM_LPCG_LPTMR2 (57) +#define CCM_LPCG_LPTMR3 (58) +#define CCM_LPCG_TPM1 (59) +#define CCM_LPCG_TPM2 (60) +#define CCM_LPCG_TPM3 (61) +#define CCM_LPCG_TPM4 (62) +#define CCM_LPCG_TPM5 (63) +#define CCM_LPCG_TPM6 (64) +#define CCM_LPCG_QTIMER1 (65) +#define CCM_LPCG_QTIMER2 (66) +#define CCM_LPCG_QTIMER3 (67) +#define CCM_LPCG_QTIMER4 (68) +#define CCM_LPCG_QTIMER5 (69) +#define CCM_LPCG_QTIMER6 (70) +#define CCM_LPCG_QTIMER7 (71) +#define CCM_LPCG_QTIMER8 (72) +#define CCM_LPCG_GPT1 (73) +#define CCM_LPCG_GPT2 (74) +#define CCM_LPCG_SYSCOUNT (75) +#define CCM_LPCG_CAN1 (76) +#define CCM_LPCG_CAN2 (77) +#define CCM_LPCG_CAN3 (78) +#define CCM_LPCG_LPUART1 (79) +#define CCM_LPCG_LPUART2 (80) +#define CCM_LPCG_LPUART3 (81) +#define CCM_LPCG_LPUART4 (82) +#define CCM_LPCG_LPUART5 (83) +#define CCM_LPCG_LPUART6 (84) +#define CCM_LPCG_LPUART7 (85) +#define CCM_LPCG_LPUART8 (86) +#define CCM_LPCG_LPUART9 (87) +#define CCM_LPCG_LPUART10 (88) +#define CCM_LPCG_LPUART11 (89) +#define CCM_LPCG_LPUART12 (90) +#define CCM_LPCG_LPI2C1 (91) +#define CCM_LPCG_LPI2C2 (92) +#define CCM_LPCG_LPI2C3 (93) +#define CCM_LPCG_LPI2C4 (94) +#define CCM_LPCG_LPI2C5 (95) +#define CCM_LPCG_LPI2C6 (96) +#define CCM_LPCG_LPSPI1 (97) +#define CCM_LPCG_LPSPI2 (98) +#define CCM_LPCG_LPSPI3 (99) +#define CCM_LPCG_LPSPI4 (100) +#define CCM_LPCG_LPSPI5 (101) +#define CCM_LPCG_LPSPI6 (102) +#define CCM_LPCG_I3C1 (103) +#define CCM_LPCG_I3C2 (104) +#define CCM_LPCG_USDHC1 (105) +#define CCM_LPCG_USDHC2 (106) +#define CCM_LPCG_USB (107) +#define CCM_LPCG_SINC1 (108) +#define CCM_LPCG_SINC2 (109) +#define CCM_LPCG_SINC3 (110) +#define CCM_LPCG_XBAR1 (111) +#define CCM_LPCG_XBAR2 (112) +#define CCM_LPCG_XBAR3 (113) +#define CCM_LPCG_AOI1 (114) +#define CCM_LPCG_AOI2 (115) +#define CCM_LPCG_AOI3 (116) +#define CCM_LPCG_AOI4 (117) +#define CCM_LPCG_ENC1 (118) +#define CCM_LPCG_ENC2 (119) +#define CCM_LPCG_ENC3 (120) +#define CCM_LPCG_ENC4 (121) +#define CCM_LPCG_KPP (122) +#define CCM_LPCG_PWM1 (123) +#define CCM_LPCG_PWM2 (124) +#define CCM_LPCG_PWM3 (125) +#define CCM_LPCG_PWM4 (126) +#define CCM_LPCG_ECAT (127) +#define CCM_LPCG_NETC (128) +#define CCM_LPCG_SERDES1 (129) +#define CCM_LPCG_SERDES2 (130) +#define CCM_LPCG_SERDES3 (131) +#define CCM_LPCG_XCELBUSX (132) +#define CCM_LPCG_XRIOCU4 (133) +#define CCM_LPCG_SPTP (134) +#define CCM_LPCG_MCTRL (135) +#define CCM_LPCG_SAI1 (136) +#define CCM_LPCG_SAI2 (137) +#define CCM_LPCG_SAI3 (138) +#define CCM_LPCG_SAI4 (139) +#define CCM_LPCG_SPDIF (140) +#define CCM_LPCG_ASRC (141) +#define CCM_LPCG_PDM (142) +#define CCM_LPCG_VREF (143) +#define CCM_LPCG_BIST (144) +#define CCM_LPCG_SSI_W2M7 (145) +#define CCM_LPCG_SSI_M72W (146) +#define CCM_LPCG_SSI_W2AO (147) +#define CCM_LPCG_SSI_AO2W (148) + +/* Counts */ + +#define ROOT_MUX_MAX (4) +#define CCM_CR_COUNT (74) +#define CCM_LPCG_COUNT (149) + +/**************************************************************************** + * Public Types + ****************************************************************************/ + +/* Clock source names used by the g_ccm_root_mux[] LUT and consumed by + * imxrt_get_clock() to return each source's frequency. The M33 boot ROM + * has already brought up ARM_PLL, SYS_PLL1/2/3 and their PFDs; NuttX only + * reads their frequencies (see imxrt_clockconfig_ver3.c). + */ + +enum ccm_clock_name_e +{ + OSC_RC_24M = 0, + OSC_RC_400M = 1, + OSC_24M = 2, + ARM_PLL_OUT = 3, + SYS_PLL1_OUT = 4, + SYS_PLL1_DIV2 = 5, + SYS_PLL1_DIV5 = 6, + SYS_PLL2_OUT = 7, + SYS_PLL2_PFD0 = 8, + SYS_PLL2_PFD1 = 9, + SYS_PLL2_PFD2 = 10, + SYS_PLL2_PFD3 = 11, + SYS_PLL3_OUT = 12, + SYS_PLL3_DIV2 = 13, + SYS_PLL3_PFD0 = 14, + SYS_PLL3_PFD1 = 15, + SYS_PLL3_PFD2 = 16, + SYS_PLL3_PFD3 = 17, + AUDIO_PLL_OUT = 18, +}; + +/* LUT mapping root -> { MUX 0, MUX 1, MUX 2, MUX 3 } clock sources. */ + +static const int g_ccm_root_mux[CCM_CR_COUNT][ROOT_MUX_MAX] = +{ + { OSC_RC_24M, OSC_RC_400M, ARM_PLL_OUT, SYS_PLL3_OUT }, /* M7 */ + { OSC_RC_24M, OSC_RC_400M, SYS_PLL3_OUT, ARM_PLL_OUT }, /* M33 */ + { OSC_RC_24M, OSC_RC_400M, SYS_PLL1_OUT, SYS_PLL2_PFD1 }, /* Edgelock */ + { OSC_RC_24M, OSC_RC_400M, SYS_PLL2_OUT, SYS_PLL3_PFD2 }, /* Bus_Aon */ + { OSC_RC_24M, OSC_RC_400M, SYS_PLL2_OUT, SYS_PLL3_PFD1 }, /* Bus_Wakeup */ + { OSC_RC_24M, OSC_RC_400M, SYS_PLL3_OUT, SYS_PLL2_PFD1 }, /* Wakeup_Axi */ + { OSC_RC_24M, OSC_RC_400M, SYS_PLL3_DIV2, SYS_PLL1_DIV5 }, /* Swo_Trace */ + { OSC_RC_24M, OSC_RC_400M, OSC_24M, SYS_PLL3_DIV2 }, /* M33_Systick */ + { OSC_RC_24M, OSC_RC_400M, OSC_24M, SYS_PLL3_DIV2 }, /* M7_Systick */ + { OSC_RC_24M, OSC_RC_400M, SYS_PLL3_DIV2, SYS_PLL1_DIV5 }, /* Flexio1 */ + { OSC_RC_24M, OSC_RC_400M, SYS_PLL3_DIV2, SYS_PLL1_DIV5 }, /* Flexio2 */ + { OSC_RC_24M, OSC_RC_400M, SYS_PLL3_DIV2, SYS_PLL2_PFD3 }, /* Lpit3 */ + { OSC_RC_24M, OSC_RC_400M, SYS_PLL3_DIV2, SYS_PLL2_PFD3 }, /* Lptimer1 */ + { OSC_RC_24M, OSC_RC_400M, SYS_PLL3_DIV2, SYS_PLL2_PFD3 }, /* Lptimer2 */ + { OSC_RC_24M, OSC_RC_400M, SYS_PLL3_DIV2, SYS_PLL2_PFD3 }, /* Lptimer3 */ + { OSC_RC_24M, OSC_RC_400M, SYS_PLL3_DIV2, SYS_PLL2_PFD3 }, /* Tpm2 */ + { OSC_RC_24M, OSC_RC_400M, SYS_PLL3_DIV2, SYS_PLL2_PFD3 }, /* Tpm4 */ + { OSC_RC_24M, OSC_RC_400M, SYS_PLL3_DIV2, SYS_PLL2_PFD3 }, /* Tpm5 */ + { OSC_RC_24M, OSC_RC_400M, SYS_PLL3_DIV2, SYS_PLL2_PFD3 }, /* Tpm6 */ + { OSC_RC_24M, OSC_RC_400M, SYS_PLL3_DIV2, SYS_PLL2_PFD3 }, /* Gpt1 */ + { OSC_RC_24M, OSC_RC_400M, SYS_PLL3_DIV2, SYS_PLL2_PFD3 }, /* Gpt2 */ + { OSC_RC_24M, OSC_RC_400M, SYS_PLL3_PFD0, SYS_PLL2_PFD0 }, /* Flexspi1 */ + { OSC_RC_24M, OSC_RC_400M, SYS_PLL3_PFD2, SYS_PLL2_PFD1 }, /* Flexspi2 */ + { OSC_RC_24M, OSC_RC_400M, SYS_PLL2_OUT, SYS_PLL1_OUT }, /* Flexspi_Slv */ + { OSC_RC_24M, OSC_RC_400M, SYS_PLL3_OUT, OSC_24M }, /* Can1 */ + { OSC_RC_24M, OSC_RC_400M, SYS_PLL3_OUT, OSC_24M }, /* Can2 */ + { OSC_RC_24M, OSC_RC_400M, SYS_PLL3_OUT, OSC_24M }, /* Can3 */ + { OSC_RC_24M, OSC_RC_400M, SYS_PLL3_DIV2, SYS_PLL2_PFD3 }, /* Lpuart0102 */ + { OSC_RC_24M, OSC_RC_400M, SYS_PLL3_DIV2, SYS_PLL2_PFD3 }, /* Lpuart0304 */ + { OSC_RC_24M, OSC_RC_400M, SYS_PLL3_DIV2, SYS_PLL2_PFD3 }, /* Lpuart0506 */ + { OSC_RC_24M, OSC_RC_400M, SYS_PLL3_DIV2, SYS_PLL2_PFD3 }, /* Lpuart0708 */ + { OSC_RC_24M, OSC_RC_400M, SYS_PLL3_DIV2, SYS_PLL2_PFD3 }, /* Lpuart0910 */ + { OSC_RC_24M, OSC_RC_400M, SYS_PLL3_DIV2, SYS_PLL2_PFD3 }, /* Lpuart1112 */ + { OSC_RC_24M, OSC_RC_400M, SYS_PLL3_DIV2, SYS_PLL2_PFD3 }, /* Lpi2c0102 */ + { OSC_RC_24M, OSC_RC_400M, SYS_PLL3_DIV2, SYS_PLL2_PFD3 }, /* Lpi2c0304 */ + { OSC_RC_24M, OSC_RC_400M, SYS_PLL3_DIV2, SYS_PLL2_PFD3 }, /* Lpi2c0506 */ + { OSC_RC_24M, OSC_RC_400M, SYS_PLL3_PFD1, SYS_PLL2_OUT }, /* Lpspi0102 */ + { OSC_RC_24M, OSC_RC_400M, SYS_PLL3_PFD1, SYS_PLL2_OUT }, /* Lpspi0304 */ + { OSC_RC_24M, OSC_RC_400M, SYS_PLL3_PFD1, SYS_PLL2_OUT }, /* Lpspi0506 */ + { OSC_RC_24M, OSC_RC_400M, SYS_PLL3_DIV2, SYS_PLL2_PFD3 }, /* I3c1 */ + { OSC_RC_24M, OSC_RC_400M, SYS_PLL3_DIV2, SYS_PLL2_PFD3 }, /* I3c2 */ + { OSC_RC_24M, OSC_RC_400M, SYS_PLL2_PFD2, SYS_PLL1_DIV5 }, /* Usdhc1 */ + { OSC_RC_24M, OSC_RC_400M, SYS_PLL2_PFD2, SYS_PLL1_DIV5 }, /* Usdhc2 */ + { OSC_RC_24M, OSC_RC_400M, SYS_PLL1_OUT, SYS_PLL2_PFD0 }, /* Semc */ + { OSC_RC_24M, OSC_RC_400M, SYS_PLL3_DIV2, SYS_PLL2_PFD3 }, /* Adc1 */ + { OSC_RC_24M, OSC_RC_400M, SYS_PLL3_DIV2, SYS_PLL2_PFD3 }, /* Adc2 */ + { OSC_RC_24M, OSC_RC_400M, SYS_PLL3_OUT, SYS_PLL2_PFD3 }, /* Acmp */ + { OSC_RC_24M, OSC_RC_400M, SYS_PLL1_DIV2, SYS_PLL1_DIV5 }, /* Ecat */ + { OSC_RC_24M, OSC_RC_400M, SYS_PLL1_DIV2, SYS_PLL1_DIV5 }, /* Enet */ + { OSC_RC_24M, OSC_RC_400M, SYS_PLL3_OUT, SYS_PLL2_PFD3 }, /* Tmr_1588 */ + { OSC_RC_24M, OSC_RC_400M, SYS_PLL3_PFD3, SYS_PLL2_PFD1 }, /* Netc */ + { OSC_RC_24M, OSC_RC_400M, SYS_PLL1_DIV2, SYS_PLL1_DIV5 }, /* Mac0 */ + { OSC_RC_24M, OSC_RC_400M, SYS_PLL1_DIV2, SYS_PLL1_DIV5 }, /* Mac1 */ + { OSC_RC_24M, OSC_RC_400M, SYS_PLL1_DIV2, SYS_PLL1_DIV5 }, /* Mac2 */ + { OSC_RC_24M, OSC_RC_400M, SYS_PLL1_DIV2, SYS_PLL1_DIV5 }, /* Mac3 */ + { OSC_RC_24M, OSC_RC_400M, SYS_PLL1_DIV2, SYS_PLL1_DIV5 }, /* Mac4 */ + { OSC_RC_24M, OSC_RC_400M, SYS_PLL1_DIV2, SYS_PLL1_DIV5 }, /* Serdes0 */ + { OSC_RC_24M, OSC_RC_400M, SYS_PLL1_DIV2, SYS_PLL1_DIV5 }, /* Serdes1 */ + { OSC_RC_24M, OSC_RC_400M, SYS_PLL1_DIV2, SYS_PLL1_DIV5 }, /* Serdes2 */ + { OSC_RC_24M, OSC_RC_400M, SYS_PLL1_OUT, AUDIO_PLL_OUT }, /* Serdes0_1G */ + { OSC_RC_24M, OSC_RC_400M, SYS_PLL1_OUT, AUDIO_PLL_OUT }, /* Serdes1_1G */ + { OSC_RC_24M, OSC_RC_400M, SYS_PLL1_OUT, AUDIO_PLL_OUT }, /* Serdes2_1G */ + { OSC_RC_24M, OSC_RC_400M, SYS_PLL3_OUT, SYS_PLL3_PFD1 }, /* Xcelbusx */ + { OSC_RC_24M, OSC_RC_400M, OSC_24M, SYS_PLL3_DIV2 }, /* Xriocu4 */ + { OSC_RC_24M, OSC_RC_400M, SYS_PLL1_DIV5, AUDIO_PLL_OUT }, /* Mctrl */ + { OSC_RC_24M, OSC_RC_400M, AUDIO_PLL_OUT, SYS_PLL3_PFD2 }, /* Sai1 */ + { OSC_RC_24M, OSC_RC_400M, AUDIO_PLL_OUT, SYS_PLL3_PFD2 }, /* Sai2 */ + { OSC_RC_24M, OSC_RC_400M, AUDIO_PLL_OUT, SYS_PLL3_PFD2 }, /* Sai3 */ + { OSC_RC_24M, OSC_RC_400M, AUDIO_PLL_OUT, SYS_PLL3_PFD2 }, /* Sai4 */ + { OSC_RC_24M, OSC_RC_400M, AUDIO_PLL_OUT, SYS_PLL3_PFD2 }, /* Spdif */ + { OSC_RC_24M, OSC_RC_400M, SYS_PLL3_OUT, AUDIO_PLL_OUT }, /* Asrc */ + { OSC_RC_24M, OSC_RC_400M, SYS_PLL3_DIV2, AUDIO_PLL_OUT }, /* Mic */ + { OSC_RC_24M, OSC_RC_400M, SYS_PLL3_DIV2, SYS_PLL1_DIV2 }, /* Cko1 */ + { OSC_RC_24M, OSC_RC_400M, SYS_PLL1_DIV5, ARM_PLL_OUT }, /* Cko2 */ +}; + +#endif /* __ARCH_ARM_SRC_IMXRT_HARDWARE_RT118X_IMXRT118X_CCM_H */ diff --git a/arch/arm/src/imxrt/hardware/rt118x/imxrt118x_dmamux.h b/arch/arm/src/imxrt/hardware/rt118x/imxrt118x_dmamux.h new file mode 100644 index 0000000000000..3dc5519ba40fd --- /dev/null +++ b/arch/arm/src/imxrt/hardware/rt118x/imxrt118x_dmamux.h @@ -0,0 +1,329 @@ +/**************************************************************************** + * arch/arm/src/imxrt/hardware/rt118x/imxrt118x_dmamux.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_IMXRT_HARDWARE_RT118X_IMXRT118X_DMAMUX_H +#define __ARCH_ARM_SRC_IMXRT_HARDWARE_RT118X_IMXRT118X_DMAMUX_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include "hardware/imxrt_memorymap.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* eDMA3/eDMA4 request source constants (IMXRT1180RM Ch. 5) */ + +#define IMXRT_DMA_ENGINE_EDMA3 (0) +#define IMXRT_DMA_ENGINE_EDMA4 (1) + +#define IMXRT_DMA_SRC_ENGINE_SHIFT (8) +#define IMXRT_DMA_SRC_ENGINE_MASK (0xff << IMXRT_DMA_SRC_ENGINE_SHIFT) +#define IMXRT_DMA_SRC_MUX_SHIFT (0) +#define IMXRT_DMA_SRC_MUX_MASK (0xff << IMXRT_DMA_SRC_MUX_SHIFT) +#define EDMA_MUX_MASK IMXRT_DMA_SRC_MUX_MASK + +#define IMXRT_DMA_SRC(_engine, _mux) \ + (((_engine) << IMXRT_DMA_SRC_ENGINE_SHIFT) | \ + ((_mux) << IMXRT_DMA_SRC_MUX_SHIFT)) + +#define IMXRT_DMA_SRC_ENGINE(_v) \ + (((_v) & IMXRT_DMA_SRC_ENGINE_MASK) >> IMXRT_DMA_SRC_ENGINE_SHIFT) +#define IMXRT_DMA_SRC_MUX(_v) \ + (((_v) & IMXRT_DMA_SRC_MUX_MASK) >> IMXRT_DMA_SRC_MUX_SHIFT) + +/**************************************************************************** + * Inline Functions + ****************************************************************************/ + +#ifndef __ASSEMBLY__ + +static inline uintptr_t imxrt_dmamux_get_dmabase(uint16_t dmamux) +{ + return (IMXRT_DMA_SRC_ENGINE(dmamux) == IMXRT_DMA_ENGINE_EDMA3) ? + IMXRT_DMA3_BASE : IMXRT_DMA4_BASE; +} + +#endif /* __ASSEMBLY__ */ + +/* eDMA3 (AONMIX) request sources */ + +#define IMXRT_DMACHAN_CAN1 IMXRT_DMA_SRC(IMXRT_DMA_ENGINE_EDMA3, 1) +#define IMXRT_DMACHAN_GPIO1_REQUEST0 IMXRT_DMA_SRC(IMXRT_DMA_ENGINE_EDMA3, 3) +#define IMXRT_DMACHAN_GPIO1_REQUEST1 IMXRT_DMA_SRC(IMXRT_DMA_ENGINE_EDMA3, 4) +#define IMXRT_DMACHAN_I3_C1_TO_BUS_REQUEST IMXRT_DMA_SRC(IMXRT_DMA_ENGINE_EDMA3, 5) +#define IMXRT_DMACHAN_I3_C1_FROM_BUS_REQUEST IMXRT_DMA_SRC(IMXRT_DMA_ENGINE_EDMA3, 6) +#define IMXRT_DMACHAN_LPI2_C1_TX IMXRT_DMA_SRC(IMXRT_DMA_ENGINE_EDMA3, 7) +#define IMXRT_DMACHAN_LPI2_C1_RX IMXRT_DMA_SRC(IMXRT_DMA_ENGINE_EDMA3, 8) +#define IMXRT_DMACHAN_LPI2_C2_TX IMXRT_DMA_SRC(IMXRT_DMA_ENGINE_EDMA3, 9) +#define IMXRT_DMACHAN_LPI2_C2_RX IMXRT_DMA_SRC(IMXRT_DMA_ENGINE_EDMA3, 10) +#define IMXRT_DMACHAN_LPSPI1_TX IMXRT_DMA_SRC(IMXRT_DMA_ENGINE_EDMA3, 11) +#define IMXRT_DMACHAN_LPSPI1_RX IMXRT_DMA_SRC(IMXRT_DMA_ENGINE_EDMA3, 12) +#define IMXRT_DMACHAN_LPSPI2_TX IMXRT_DMA_SRC(IMXRT_DMA_ENGINE_EDMA3, 13) +#define IMXRT_DMACHAN_LPSPI2_RX IMXRT_DMA_SRC(IMXRT_DMA_ENGINE_EDMA3, 14) +#define IMXRT_DMACHAN_LPTMR1_REQUEST IMXRT_DMA_SRC(IMXRT_DMA_ENGINE_EDMA3, 15) +#define IMXRT_DMACHAN_LPUART1_TX IMXRT_DMA_SRC(IMXRT_DMA_ENGINE_EDMA3, 16) +#define IMXRT_DMACHAN_LPUART1_RX IMXRT_DMA_SRC(IMXRT_DMA_ENGINE_EDMA3, 17) +#define IMXRT_DMACHAN_LPUART2_TX IMXRT_DMA_SRC(IMXRT_DMA_ENGINE_EDMA3, 18) +#define IMXRT_DMACHAN_LPUART2_RX IMXRT_DMA_SRC(IMXRT_DMA_ENGINE_EDMA3, 19) +#define IMXRT_DMACHAN_EDGELOCK_REQUEST IMXRT_DMA_SRC(IMXRT_DMA_ENGINE_EDMA3, 20) +#define IMXRT_DMACHAN_SAI1_TX IMXRT_DMA_SRC(IMXRT_DMA_ENGINE_EDMA3, 21) +#define IMXRT_DMACHAN_SAI1_RX IMXRT_DMA_SRC(IMXRT_DMA_ENGINE_EDMA3, 22) +#define IMXRT_DMACHAN_TPM1_REQUEST0_REQUEST2 IMXRT_DMA_SRC(IMXRT_DMA_ENGINE_EDMA3, 23) +#define IMXRT_DMACHAN_TPM1_REQUEST1_REQUEST3 IMXRT_DMA_SRC(IMXRT_DMA_ENGINE_EDMA3, 24) +#define IMXRT_DMACHAN_TPM1_OVERFLOW_REQUEST IMXRT_DMA_SRC(IMXRT_DMA_ENGINE_EDMA3, 25) +#define IMXRT_DMACHAN_TPM2_REQUEST0_REQUEST2 IMXRT_DMA_SRC(IMXRT_DMA_ENGINE_EDMA3, 26) +#define IMXRT_DMACHAN_TPM2_REQUEST1_REQUEST3 IMXRT_DMA_SRC(IMXRT_DMA_ENGINE_EDMA3, 27) +#define IMXRT_DMACHAN_TPM2_OVERFLOW_REQUEST IMXRT_DMA_SRC(IMXRT_DMA_ENGINE_EDMA3, 28) +#define IMXRT_DMACHAN_LPUART7_TX IMXRT_DMA_SRC(IMXRT_DMA_ENGINE_EDMA3, 29) +#define IMXRT_DMACHAN_LPUART7_RX IMXRT_DMA_SRC(IMXRT_DMA_ENGINE_EDMA3, 30) +#define IMXRT_DMACHAN_FLEX_SPI2_TX IMXRT_DMA_SRC(IMXRT_DMA_ENGINE_EDMA3, 33) +#define IMXRT_DMACHAN_FLEX_SPI2_RX IMXRT_DMA_SRC(IMXRT_DMA_ENGINE_EDMA3, 34) +#define IMXRT_DMACHAN_CAN3 IMXRT_DMA_SRC(IMXRT_DMA_ENGINE_EDMA3, 38) +#define IMXRT_DMACHAN_LPUART12_TX IMXRT_DMA_SRC(IMXRT_DMA_ENGINE_EDMA3, 31) +#define IMXRT_DMACHAN_LPUART12_RX IMXRT_DMA_SRC(IMXRT_DMA_ENGINE_EDMA3, 32) + +/* eDMA4 (WAKEUPMIX / MEGAMIX) request sources */ + +#define IMXRT_DMACHAN_GPIO2_REQUEST0 IMXRT_DMA_SRC(IMXRT_DMA_ENGINE_EDMA4, 2) +#define IMXRT_DMACHAN_GPIO2_REQUEST1 IMXRT_DMA_SRC(IMXRT_DMA_ENGINE_EDMA4, 3) +#define IMXRT_DMACHAN_GPIO3_REQUEST0 IMXRT_DMA_SRC(IMXRT_DMA_ENGINE_EDMA4, 4) +#define IMXRT_DMACHAN_GPIO3_REQUEST1 IMXRT_DMA_SRC(IMXRT_DMA_ENGINE_EDMA4, 5) +#define IMXRT_DMACHAN_I3_C2_TO_BUS_REQUEST IMXRT_DMA_SRC(IMXRT_DMA_ENGINE_EDMA4, 6) +#define IMXRT_DMACHAN_I3_C2_FROM_BUS_REQUEST IMXRT_DMA_SRC(IMXRT_DMA_ENGINE_EDMA4, 7) +#define IMXRT_DMACHAN_LPI2_C3_TX IMXRT_DMA_SRC(IMXRT_DMA_ENGINE_EDMA4, 8) +#define IMXRT_DMACHAN_LPI2_C3_RX IMXRT_DMA_SRC(IMXRT_DMA_ENGINE_EDMA4, 9) +#define IMXRT_DMACHAN_LPI2_C4_TX IMXRT_DMA_SRC(IMXRT_DMA_ENGINE_EDMA4, 10) +#define IMXRT_DMACHAN_LPI2_C4_RX IMXRT_DMA_SRC(IMXRT_DMA_ENGINE_EDMA4, 11) +#define IMXRT_DMACHAN_LPSPI3_TX IMXRT_DMA_SRC(IMXRT_DMA_ENGINE_EDMA4, 12) +#define IMXRT_DMACHAN_LPSPI3_RX IMXRT_DMA_SRC(IMXRT_DMA_ENGINE_EDMA4, 13) +#define IMXRT_DMACHAN_LPSPI4_TX IMXRT_DMA_SRC(IMXRT_DMA_ENGINE_EDMA4, 14) +#define IMXRT_DMACHAN_LPSPI4_RX IMXRT_DMA_SRC(IMXRT_DMA_ENGINE_EDMA4, 15) +#define IMXRT_DMACHAN_LPUART3_TX IMXRT_DMA_SRC(IMXRT_DMA_ENGINE_EDMA4, 17) +#define IMXRT_DMACHAN_LPUART3_RX IMXRT_DMA_SRC(IMXRT_DMA_ENGINE_EDMA4, 18) +#define IMXRT_DMACHAN_LPUART4_TX IMXRT_DMA_SRC(IMXRT_DMA_ENGINE_EDMA4, 19) +#define IMXRT_DMACHAN_LPUART4_RX IMXRT_DMA_SRC(IMXRT_DMA_ENGINE_EDMA4, 20) +#define IMXRT_DMACHAN_LPUART5_TX IMXRT_DMA_SRC(IMXRT_DMA_ENGINE_EDMA4, 21) +#define IMXRT_DMACHAN_LPUART5_RX IMXRT_DMA_SRC(IMXRT_DMA_ENGINE_EDMA4, 22) +#define IMXRT_DMACHAN_LPUART6_TX IMXRT_DMA_SRC(IMXRT_DMA_ENGINE_EDMA4, 23) +#define IMXRT_DMACHAN_LPUART6_RX IMXRT_DMA_SRC(IMXRT_DMA_ENGINE_EDMA4, 24) +#define IMXRT_DMACHAN_TPM3_REQUEST0_REQUEST2 IMXRT_DMA_SRC(IMXRT_DMA_ENGINE_EDMA4, 25) +#define IMXRT_DMACHAN_TPM3_REQUEST1_REQUEST3 IMXRT_DMA_SRC(IMXRT_DMA_ENGINE_EDMA4, 26) +#define IMXRT_DMACHAN_TPM3_OVERFLOW_REQUEST IMXRT_DMA_SRC(IMXRT_DMA_ENGINE_EDMA4, 27) +#define IMXRT_DMACHAN_FLEX_IO1_REQUEST0 IMXRT_DMA_SRC(IMXRT_DMA_ENGINE_EDMA4, 37) +#define IMXRT_DMACHAN_FLEX_IO1_REQUEST1 IMXRT_DMA_SRC(IMXRT_DMA_ENGINE_EDMA4, 38) +#define IMXRT_DMACHAN_FLEX_IO1_REQUEST2 IMXRT_DMA_SRC(IMXRT_DMA_ENGINE_EDMA4, 39) +#define IMXRT_DMACHAN_FLEX_IO1_REQUEST3 IMXRT_DMA_SRC(IMXRT_DMA_ENGINE_EDMA4, 40) +#define IMXRT_DMACHAN_FLEX_IO1_REQUEST4 IMXRT_DMA_SRC(IMXRT_DMA_ENGINE_EDMA4, 41) +#define IMXRT_DMACHAN_FLEX_IO1_REQUEST5 IMXRT_DMA_SRC(IMXRT_DMA_ENGINE_EDMA4, 42) +#define IMXRT_DMACHAN_FLEX_IO1_REQUEST6 IMXRT_DMA_SRC(IMXRT_DMA_ENGINE_EDMA4, 43) +#define IMXRT_DMACHAN_FLEX_IO1_REQUEST7 IMXRT_DMA_SRC(IMXRT_DMA_ENGINE_EDMA4, 44) +#define IMXRT_DMACHAN_FLEX_IO2_REQUEST0 IMXRT_DMA_SRC(IMXRT_DMA_ENGINE_EDMA4, 45) +#define IMXRT_DMACHAN_FLEX_IO2_REQUEST1 IMXRT_DMA_SRC(IMXRT_DMA_ENGINE_EDMA4, 46) +#define IMXRT_DMACHAN_FLEX_IO2_REQUEST2 IMXRT_DMA_SRC(IMXRT_DMA_ENGINE_EDMA4, 47) +#define IMXRT_DMACHAN_FLEX_IO2_REQUEST3 IMXRT_DMA_SRC(IMXRT_DMA_ENGINE_EDMA4, 48) +#define IMXRT_DMACHAN_FLEX_IO2_REQUEST4 IMXRT_DMA_SRC(IMXRT_DMA_ENGINE_EDMA4, 49) +#define IMXRT_DMACHAN_FLEX_IO2_REQUEST5 IMXRT_DMA_SRC(IMXRT_DMA_ENGINE_EDMA4, 50) +#define IMXRT_DMACHAN_FLEX_IO2_REQUEST6 IMXRT_DMA_SRC(IMXRT_DMA_ENGINE_EDMA4, 51) +#define IMXRT_DMACHAN_FLEX_IO2_REQUEST7 IMXRT_DMA_SRC(IMXRT_DMA_ENGINE_EDMA4, 52) +#define IMXRT_DMACHAN_FLEX_SPI1_TX IMXRT_DMA_SRC(IMXRT_DMA_ENGINE_EDMA4, 53) +#define IMXRT_DMACHAN_FLEX_SPI1_RX IMXRT_DMA_SRC(IMXRT_DMA_ENGINE_EDMA4, 54) +#define IMXRT_DMACHAN_ADC1_REQUEST0 IMXRT_DMA_SRC(IMXRT_DMA_ENGINE_EDMA4, 57) +#define IMXRT_DMACHAN_FLEX_PWM3_CAPTURE_SUB0 IMXRT_DMA_SRC(IMXRT_DMA_ENGINE_EDMA4, 74) +#define IMXRT_DMACHAN_FLEX_PWM3_CAPTURE_SUB1 IMXRT_DMA_SRC(IMXRT_DMA_ENGINE_EDMA4, 75) +#define IMXRT_DMACHAN_FLEX_PWM3_CAPTURE_SUB2 IMXRT_DMA_SRC(IMXRT_DMA_ENGINE_EDMA4, 76) +#define IMXRT_DMACHAN_FLEX_PWM3_CAPTURE_SUB3 IMXRT_DMA_SRC(IMXRT_DMA_ENGINE_EDMA4, 77) +#define IMXRT_DMACHAN_FLEX_PWM3_VALUE_SUB0 IMXRT_DMA_SRC(IMXRT_DMA_ENGINE_EDMA4, 78) +#define IMXRT_DMACHAN_FLEX_PWM3_VALUE_SUB1 IMXRT_DMA_SRC(IMXRT_DMA_ENGINE_EDMA4, 79) +#define IMXRT_DMACHAN_FLEX_PWM3_VALUE_SUB2 IMXRT_DMA_SRC(IMXRT_DMA_ENGINE_EDMA4, 80) +#define IMXRT_DMACHAN_FLEX_PWM3_VALUE_SUB3 IMXRT_DMA_SRC(IMXRT_DMA_ENGINE_EDMA4, 81) +#define IMXRT_DMACHAN_FLEX_PWM4_CAPTURE_SUB0 IMXRT_DMA_SRC(IMXRT_DMA_ENGINE_EDMA4, 82) +#define IMXRT_DMACHAN_FLEX_PWM4_CAPTURE_SUB1 IMXRT_DMA_SRC(IMXRT_DMA_ENGINE_EDMA4, 83) +#define IMXRT_DMACHAN_FLEX_PWM4_CAPTURE_SUB2 IMXRT_DMA_SRC(IMXRT_DMA_ENGINE_EDMA4, 84) +#define IMXRT_DMACHAN_FLEX_PWM4_CAPTURE_SUB3 IMXRT_DMA_SRC(IMXRT_DMA_ENGINE_EDMA4, 85) +#define IMXRT_DMACHAN_FLEX_PWM4_VALUE_SUB0 IMXRT_DMA_SRC(IMXRT_DMA_ENGINE_EDMA4, 86) +#define IMXRT_DMACHAN_FLEX_PWM4_VALUE_SUB1 IMXRT_DMA_SRC(IMXRT_DMA_ENGINE_EDMA4, 87) +#define IMXRT_DMACHAN_FLEX_PWM4_VALUE_SUB2 IMXRT_DMA_SRC(IMXRT_DMA_ENGINE_EDMA4, 88) +#define IMXRT_DMACHAN_FLEX_PWM4_VALUE_SUB3 IMXRT_DMA_SRC(IMXRT_DMA_ENGINE_EDMA4, 89) +#define IMXRT_DMACHAN_QTIMER1_CAPT_TIMER0 IMXRT_DMA_SRC(IMXRT_DMA_ENGINE_EDMA4, 90) +#define IMXRT_DMACHAN_QTIMER1_CAPT_TIMER1 IMXRT_DMA_SRC(IMXRT_DMA_ENGINE_EDMA4, 91) +#define IMXRT_DMACHAN_QTIMER1_CAPT_TIMER2 IMXRT_DMA_SRC(IMXRT_DMA_ENGINE_EDMA4, 92) +#define IMXRT_DMACHAN_QTIMER1_CAPT_TIMER3 IMXRT_DMA_SRC(IMXRT_DMA_ENGINE_EDMA4, 93) +#define IMXRT_DMACHAN_QTIMER1_CMPLD1_TIMER0_CMPLD2_TIMER1 IMXRT_DMA_SRC(IMXRT_DMA_ENGINE_EDMA4, 94) +#define IMXRT_DMACHAN_QTIMER1_CMPLD1_TIMER1_CMPLD2_TIMER0 IMXRT_DMA_SRC(IMXRT_DMA_ENGINE_EDMA4, 95) +#define IMXRT_DMACHAN_QTIMER1_CMPLD1_TIMER2_CMPLD2_TIMER3 IMXRT_DMA_SRC(IMXRT_DMA_ENGINE_EDMA4, 96) +#define IMXRT_DMACHAN_QTIMER1_CMPLD1_TIMER3_CMPLD2_TIMER2 IMXRT_DMA_SRC(IMXRT_DMA_ENGINE_EDMA4, 97) +#define IMXRT_DMACHAN_QTIMER2_CAPT_TIMER0 IMXRT_DMA_SRC(IMXRT_DMA_ENGINE_EDMA4, 98) +#define IMXRT_DMACHAN_QTIMER2_CAPT_TIMER1 IMXRT_DMA_SRC(IMXRT_DMA_ENGINE_EDMA4, 99) +#define IMXRT_DMACHAN_QTIMER2_CAPT_TIMER2 IMXRT_DMA_SRC(IMXRT_DMA_ENGINE_EDMA4, 100) +#define IMXRT_DMACHAN_QTIMER2_CAPT_TIMER3 IMXRT_DMA_SRC(IMXRT_DMA_ENGINE_EDMA4, 101) +#define IMXRT_DMACHAN_QTIMER2_CMPLD1_TIMER0_CMPLD2_TIMER1 IMXRT_DMA_SRC(IMXRT_DMA_ENGINE_EDMA4, 102) +#define IMXRT_DMACHAN_QTIMER2_CMPLD1_TIMER1_CMPLD2_TIMER0 IMXRT_DMA_SRC(IMXRT_DMA_ENGINE_EDMA4, 103) +#define IMXRT_DMACHAN_QTIMER2_CMPLD1_TIMER2_CMPLD2_TIMER3 IMXRT_DMA_SRC(IMXRT_DMA_ENGINE_EDMA4, 104) +#define IMXRT_DMACHAN_QTIMER2_CMPLD1_TIMER3_CMPLD2_TIMER2 IMXRT_DMA_SRC(IMXRT_DMA_ENGINE_EDMA4, 105) +#define IMXRT_DMACHAN_QTIMER3_CAPT_TIMER0 IMXRT_DMA_SRC(IMXRT_DMA_ENGINE_EDMA4, 106) +#define IMXRT_DMACHAN_QTIMER3_CAPT_TIMER1 IMXRT_DMA_SRC(IMXRT_DMA_ENGINE_EDMA4, 107) +#define IMXRT_DMACHAN_QTIMER3_CAPT_TIMER2 IMXRT_DMA_SRC(IMXRT_DMA_ENGINE_EDMA4, 108) +#define IMXRT_DMACHAN_QTIMER3_CAPT_TIMER3 IMXRT_DMA_SRC(IMXRT_DMA_ENGINE_EDMA4, 109) +#define IMXRT_DMACHAN_QTIMER3_CMPLD1_TIMER0_CMPLD2_TIMER1 IMXRT_DMA_SRC(IMXRT_DMA_ENGINE_EDMA4, 110) +#define IMXRT_DMACHAN_QTIMER3_CMPLD1_TIMER1_CMPLD2_TIMER0 IMXRT_DMA_SRC(IMXRT_DMA_ENGINE_EDMA4, 111) +#define IMXRT_DMACHAN_QTIMER3_CMPLD1_TIMER2_CMPLD2_TIMER3 IMXRT_DMA_SRC(IMXRT_DMA_ENGINE_EDMA4, 112) +#define IMXRT_DMACHAN_QTIMER3_CMPLD1_TIMER3_CMPLD2_TIMER2 IMXRT_DMA_SRC(IMXRT_DMA_ENGINE_EDMA4, 113) +#define IMXRT_DMACHAN_QTIMER4_CAPT_TIMER0 IMXRT_DMA_SRC(IMXRT_DMA_ENGINE_EDMA4, 114) +#define IMXRT_DMACHAN_QTIMER4_CAPT_TIMER1 IMXRT_DMA_SRC(IMXRT_DMA_ENGINE_EDMA4, 115) +#define IMXRT_DMACHAN_QTIMER4_CAPT_TIMER2 IMXRT_DMA_SRC(IMXRT_DMA_ENGINE_EDMA4, 116) +#define IMXRT_DMACHAN_QTIMER4_CAPT_TIMER3 IMXRT_DMA_SRC(IMXRT_DMA_ENGINE_EDMA4, 117) +#define IMXRT_DMACHAN_QTIMER4_CMPLD1_TIMER0_CMPLD2_TIMER1 IMXRT_DMA_SRC(IMXRT_DMA_ENGINE_EDMA4, 118) +#define IMXRT_DMACHAN_QTIMER4_CMPLD1_TIMER1_CMPLD2_TIMER0 IMXRT_DMA_SRC(IMXRT_DMA_ENGINE_EDMA4, 119) +#define IMXRT_DMACHAN_QTIMER4_CMPLD1_TIMER2_CMPLD2_TIMER3 IMXRT_DMA_SRC(IMXRT_DMA_ENGINE_EDMA4, 120) +#define IMXRT_DMACHAN_QTIMER4_CMPLD1_TIMER3_CMPLD2_TIMER2 IMXRT_DMA_SRC(IMXRT_DMA_ENGINE_EDMA4, 121) +#define IMXRT_DMACHAN_XBAR1_REQUEST0 IMXRT_DMA_SRC(IMXRT_DMA_ENGINE_EDMA4, 154) +#define IMXRT_DMACHAN_XBAR1_REQUEST1 IMXRT_DMA_SRC(IMXRT_DMA_ENGINE_EDMA4, 155) +#define IMXRT_DMACHAN_XBAR1_REQUEST2 IMXRT_DMA_SRC(IMXRT_DMA_ENGINE_EDMA4, 156) +#define IMXRT_DMACHAN_XBAR1_REQUEST3 IMXRT_DMA_SRC(IMXRT_DMA_ENGINE_EDMA4, 157) +#define IMXRT_DMACHAN_ADC2_REQUEST0 IMXRT_DMA_SRC(IMXRT_DMA_ENGINE_EDMA4, 158) +#define IMXRT_DMACHAN_EQDC1 IMXRT_DMA_SRC(IMXRT_DMA_ENGINE_EDMA4, 159) +#define IMXRT_DMACHAN_EQDC2 IMXRT_DMA_SRC(IMXRT_DMA_ENGINE_EDMA4, 160) +#define IMXRT_DMACHAN_EQDC3 IMXRT_DMA_SRC(IMXRT_DMA_ENGINE_EDMA4, 161) +#define IMXRT_DMACHAN_EQDC4 IMXRT_DMA_SRC(IMXRT_DMA_ENGINE_EDMA4, 162) +#define IMXRT_DMACHAN_LPI2_C5_TX IMXRT_DMA_SRC(IMXRT_DMA_ENGINE_EDMA4, 163) +#define IMXRT_DMACHAN_LPI2_C5_RX IMXRT_DMA_SRC(IMXRT_DMA_ENGINE_EDMA4, 164) +#define IMXRT_DMACHAN_LPSPI5_TX IMXRT_DMA_SRC(IMXRT_DMA_ENGINE_EDMA4, 167) +#define IMXRT_DMACHAN_LPSPI5_RX IMXRT_DMA_SRC(IMXRT_DMA_ENGINE_EDMA4, 168) +#define IMXRT_DMACHAN_LPSPI6_TX IMXRT_DMA_SRC(IMXRT_DMA_ENGINE_EDMA4, 169) +#define IMXRT_DMACHAN_LPSPI6_RX IMXRT_DMA_SRC(IMXRT_DMA_ENGINE_EDMA4, 170) +#define IMXRT_DMACHAN_LPUART8_TX IMXRT_DMA_SRC(IMXRT_DMA_ENGINE_EDMA4, 178) +#define IMXRT_DMACHAN_LPUART8_RX IMXRT_DMA_SRC(IMXRT_DMA_ENGINE_EDMA4, 179) +#define IMXRT_DMACHAN_DAC IMXRT_DMA_SRC(IMXRT_DMA_ENGINE_EDMA4, 186) +#define IMXRT_DMACHAN_CMP3 IMXRT_DMA_SRC(IMXRT_DMA_ENGINE_EDMA4, 189) +#define IMXRT_DMACHAN_ASRC_REQUEST1 IMXRT_DMA_SRC(IMXRT_DMA_ENGINE_EDMA4, 191) +#define IMXRT_DMACHAN_ASRC_REQUEST2 IMXRT_DMA_SRC(IMXRT_DMA_ENGINE_EDMA4, 192) +#define IMXRT_DMACHAN_ASRC_REQUEST3 IMXRT_DMA_SRC(IMXRT_DMA_ENGINE_EDMA4, 193) +#define IMXRT_DMACHAN_ASRC_REQUEST4 IMXRT_DMA_SRC(IMXRT_DMA_ENGINE_EDMA4, 194) +#define IMXRT_DMACHAN_ASRC_REQUEST5 IMXRT_DMA_SRC(IMXRT_DMA_ENGINE_EDMA4, 195) +#define IMXRT_DMACHAN_ASRC_REQUEST6 IMXRT_DMA_SRC(IMXRT_DMA_ENGINE_EDMA4, 196) +#define IMXRT_DMACHAN_SPDIF_RX IMXRT_DMA_SRC(IMXRT_DMA_ENGINE_EDMA4, 197) +#define IMXRT_DMACHAN_SPDIF_TX IMXRT_DMA_SRC(IMXRT_DMA_ENGINE_EDMA4, 198) +#define IMXRT_DMACHAN_PDM_RX IMXRT_DMA_SRC(IMXRT_DMA_ENGINE_EDMA4, 199) +#define IMXRT_DMACHAN_GPIO4_REQUEST0 IMXRT_DMA_SRC(IMXRT_DMA_ENGINE_EDMA4, 200) +#define IMXRT_DMACHAN_GPIO4_REQUEST1 IMXRT_DMA_SRC(IMXRT_DMA_ENGINE_EDMA4, 201) +#define IMXRT_DMACHAN_GPIO5_REQUEST0 IMXRT_DMA_SRC(IMXRT_DMA_ENGINE_EDMA4, 202) +#define IMXRT_DMACHAN_GPIO5_REQUEST1 IMXRT_DMA_SRC(IMXRT_DMA_ENGINE_EDMA4, 203) +#define IMXRT_DMACHAN_GPIO6_REQUEST0 IMXRT_DMA_SRC(IMXRT_DMA_ENGINE_EDMA4, 204) +#define IMXRT_DMACHAN_GPIO6_REQUEST1 IMXRT_DMA_SRC(IMXRT_DMA_ENGINE_EDMA4, 205) +#define IMXRT_DMACHAN_SINC3_REQUEST0 IMXRT_DMA_SRC(IMXRT_DMA_ENGINE_EDMA4, 216) +#define IMXRT_DMACHAN_SINC3_REQUEST1 IMXRT_DMA_SRC(IMXRT_DMA_ENGINE_EDMA4, 217) +#define IMXRT_DMACHAN_SINC3_REQUEST2 IMXRT_DMA_SRC(IMXRT_DMA_ENGINE_EDMA4, 218) +#define IMXRT_DMACHAN_SINC3_REQUEST3 IMXRT_DMA_SRC(IMXRT_DMA_ENGINE_EDMA4, 219) +#define IMXRT_DMACHAN_ADC1_REQUEST1 IMXRT_DMA_SRC(IMXRT_DMA_ENGINE_EDMA4, 220) +#define IMXRT_DMACHAN_ADC2_REQUEST1 IMXRT_DMA_SRC(IMXRT_DMA_ENGINE_EDMA4, 221) +#define IMXRT_DMACHAN_LPTMR2_REQUEST IMXRT_DMA_SRC(IMXRT_DMA_ENGINE_EDMA4, 16) +#define IMXRT_DMACHAN_TPM4_REQUEST0_REQUEST2 IMXRT_DMA_SRC(IMXRT_DMA_ENGINE_EDMA4, 28) +#define IMXRT_DMACHAN_TPM4_REQUEST1_REQUEST3 IMXRT_DMA_SRC(IMXRT_DMA_ENGINE_EDMA4, 29) +#define IMXRT_DMACHAN_TPM4_OVERFLOW_REQUEST IMXRT_DMA_SRC(IMXRT_DMA_ENGINE_EDMA4, 30) +#define IMXRT_DMACHAN_FLEX_PWM1_CAPTURE_SUB0 IMXRT_DMA_SRC(IMXRT_DMA_ENGINE_EDMA4, 58) +#define IMXRT_DMACHAN_FLEX_PWM1_CAPTURE_SUB1 IMXRT_DMA_SRC(IMXRT_DMA_ENGINE_EDMA4, 59) +#define IMXRT_DMACHAN_FLEX_PWM1_CAPTURE_SUB2 IMXRT_DMA_SRC(IMXRT_DMA_ENGINE_EDMA4, 60) +#define IMXRT_DMACHAN_FLEX_PWM1_CAPTURE_SUB3 IMXRT_DMA_SRC(IMXRT_DMA_ENGINE_EDMA4, 61) +#define IMXRT_DMACHAN_FLEX_PWM1_VALUE_SUB0 IMXRT_DMA_SRC(IMXRT_DMA_ENGINE_EDMA4, 62) +#define IMXRT_DMACHAN_FLEX_PWM1_VALUE_SUB1 IMXRT_DMA_SRC(IMXRT_DMA_ENGINE_EDMA4, 63) +#define IMXRT_DMACHAN_FLEX_PWM1_VALUE_SUB2 IMXRT_DMA_SRC(IMXRT_DMA_ENGINE_EDMA4, 64) +#define IMXRT_DMACHAN_FLEX_PWM1_VALUE_SUB3 IMXRT_DMA_SRC(IMXRT_DMA_ENGINE_EDMA4, 65) +#define IMXRT_DMACHAN_FLEX_PWM2_CAPTURE_SUB0 IMXRT_DMA_SRC(IMXRT_DMA_ENGINE_EDMA4, 66) +#define IMXRT_DMACHAN_FLEX_PWM2_CAPTURE_SUB1 IMXRT_DMA_SRC(IMXRT_DMA_ENGINE_EDMA4, 67) +#define IMXRT_DMACHAN_FLEX_PWM2_CAPTURE_SUB2 IMXRT_DMA_SRC(IMXRT_DMA_ENGINE_EDMA4, 68) +#define IMXRT_DMACHAN_FLEX_PWM2_CAPTURE_SUB3 IMXRT_DMA_SRC(IMXRT_DMA_ENGINE_EDMA4, 69) +#define IMXRT_DMACHAN_FLEX_PWM2_VALUE_SUB0 IMXRT_DMA_SRC(IMXRT_DMA_ENGINE_EDMA4, 70) +#define IMXRT_DMACHAN_FLEX_PWM2_VALUE_SUB1 IMXRT_DMA_SRC(IMXRT_DMA_ENGINE_EDMA4, 71) +#define IMXRT_DMACHAN_FLEX_PWM2_VALUE_SUB2 IMXRT_DMA_SRC(IMXRT_DMA_ENGINE_EDMA4, 72) +#define IMXRT_DMACHAN_FLEX_PWM2_VALUE_SUB3 IMXRT_DMA_SRC(IMXRT_DMA_ENGINE_EDMA4, 73) +#define IMXRT_DMACHAN_QTIMER5_CAPT_TIMER0 IMXRT_DMA_SRC(IMXRT_DMA_ENGINE_EDMA4, 122) +#define IMXRT_DMACHAN_QTIMER5_CAPT_TIMER1 IMXRT_DMA_SRC(IMXRT_DMA_ENGINE_EDMA4, 123) +#define IMXRT_DMACHAN_QTIMER5_CAPT_TIMER2 IMXRT_DMA_SRC(IMXRT_DMA_ENGINE_EDMA4, 124) +#define IMXRT_DMACHAN_QTIMER5_CAPT_TIMER3 IMXRT_DMA_SRC(IMXRT_DMA_ENGINE_EDMA4, 125) +#define IMXRT_DMACHAN_QTIMER5_CMPLD1_TIMER0_CMPLD2_TIMER1 IMXRT_DMA_SRC(IMXRT_DMA_ENGINE_EDMA4, 126) +#define IMXRT_DMACHAN_QTIMER5_CMPLD1_TIMER1_CMPLD2_TIMER0 IMXRT_DMA_SRC(IMXRT_DMA_ENGINE_EDMA4, 127) +#define IMXRT_DMACHAN_QTIMER5_CMPLD1_TIMER2_CMPLD2_TIMER3 IMXRT_DMA_SRC(IMXRT_DMA_ENGINE_EDMA4, 128) +#define IMXRT_DMACHAN_QTIMER5_CMPLD1_TIMER3_CMPLD2_TIMER2 IMXRT_DMA_SRC(IMXRT_DMA_ENGINE_EDMA4, 129) +#define IMXRT_DMACHAN_QTIMER6_CAPT_TIMER0 IMXRT_DMA_SRC(IMXRT_DMA_ENGINE_EDMA4, 130) +#define IMXRT_DMACHAN_QTIMER6_CAPT_TIMER1 IMXRT_DMA_SRC(IMXRT_DMA_ENGINE_EDMA4, 131) +#define IMXRT_DMACHAN_QTIMER6_CAPT_TIMER2 IMXRT_DMA_SRC(IMXRT_DMA_ENGINE_EDMA4, 132) +#define IMXRT_DMACHAN_QTIMER6_CAPT_TIMER3 IMXRT_DMA_SRC(IMXRT_DMA_ENGINE_EDMA4, 133) +#define IMXRT_DMACHAN_QTIMER6_CMPLD1_TIMER0_CMPLD2_TIMER1 IMXRT_DMA_SRC(IMXRT_DMA_ENGINE_EDMA4, 134) +#define IMXRT_DMACHAN_QTIMER6_CMPLD1_TIMER1_CMPLD2_TIMER0 IMXRT_DMA_SRC(IMXRT_DMA_ENGINE_EDMA4, 135) +#define IMXRT_DMACHAN_QTIMER6_CMPLD1_TIMER2_CMPLD2_TIMER3 IMXRT_DMA_SRC(IMXRT_DMA_ENGINE_EDMA4, 136) +#define IMXRT_DMACHAN_QTIMER6_CMPLD1_TIMER3_CMPLD2_TIMER2 IMXRT_DMA_SRC(IMXRT_DMA_ENGINE_EDMA4, 137) +#define IMXRT_DMACHAN_QTIMER7_CAPT_TIMER0 IMXRT_DMA_SRC(IMXRT_DMA_ENGINE_EDMA4, 138) +#define IMXRT_DMACHAN_QTIMER7_CAPT_TIMER1 IMXRT_DMA_SRC(IMXRT_DMA_ENGINE_EDMA4, 139) +#define IMXRT_DMACHAN_QTIMER7_CAPT_TIMER2 IMXRT_DMA_SRC(IMXRT_DMA_ENGINE_EDMA4, 140) +#define IMXRT_DMACHAN_QTIMER7_CAPT_TIMER3 IMXRT_DMA_SRC(IMXRT_DMA_ENGINE_EDMA4, 141) +#define IMXRT_DMACHAN_QTIMER7_CMPLD1_TIMER0_CMPLD2_TIMER1 IMXRT_DMA_SRC(IMXRT_DMA_ENGINE_EDMA4, 142) +#define IMXRT_DMACHAN_QTIMER7_CMPLD1_TIMER1_CMPLD2_TIMER0 IMXRT_DMA_SRC(IMXRT_DMA_ENGINE_EDMA4, 143) +#define IMXRT_DMACHAN_QTIMER7_CMPLD1_TIMER2_CMPLD2_TIMER3 IMXRT_DMA_SRC(IMXRT_DMA_ENGINE_EDMA4, 144) +#define IMXRT_DMACHAN_QTIMER7_CMPLD1_TIMER3_CMPLD2_TIMER2 IMXRT_DMA_SRC(IMXRT_DMA_ENGINE_EDMA4, 145) +#define IMXRT_DMACHAN_QTIMER8_CAPT_TIMER0 IMXRT_DMA_SRC(IMXRT_DMA_ENGINE_EDMA4, 146) +#define IMXRT_DMACHAN_QTIMER8_CAPT_TIMER1 IMXRT_DMA_SRC(IMXRT_DMA_ENGINE_EDMA4, 147) +#define IMXRT_DMACHAN_QTIMER8_CAPT_TIMER2 IMXRT_DMA_SRC(IMXRT_DMA_ENGINE_EDMA4, 148) +#define IMXRT_DMACHAN_QTIMER8_CAPT_TIMER3 IMXRT_DMA_SRC(IMXRT_DMA_ENGINE_EDMA4, 149) +#define IMXRT_DMACHAN_QTIMER8_CMPLD1_TIMER0_CMPLD2_TIMER1 IMXRT_DMA_SRC(IMXRT_DMA_ENGINE_EDMA4, 150) +#define IMXRT_DMACHAN_QTIMER8_CMPLD1_TIMER1_CMPLD2_TIMER0 IMXRT_DMA_SRC(IMXRT_DMA_ENGINE_EDMA4, 151) +#define IMXRT_DMACHAN_QTIMER8_CMPLD1_TIMER2_CMPLD2_TIMER3 IMXRT_DMA_SRC(IMXRT_DMA_ENGINE_EDMA4, 152) +#define IMXRT_DMACHAN_QTIMER8_CMPLD1_TIMER3_CMPLD2_TIMER2 IMXRT_DMA_SRC(IMXRT_DMA_ENGINE_EDMA4, 153) +#define IMXRT_DMACHAN_LPI2_C6_TX IMXRT_DMA_SRC(IMXRT_DMA_ENGINE_EDMA4, 165) +#define IMXRT_DMACHAN_LPI2_C6_RX IMXRT_DMA_SRC(IMXRT_DMA_ENGINE_EDMA4, 166) +#define IMXRT_DMACHAN_LPTMR3_REQUEST IMXRT_DMA_SRC(IMXRT_DMA_ENGINE_EDMA4, 171) +#define IMXRT_DMACHAN_SAI2_TX IMXRT_DMA_SRC(IMXRT_DMA_ENGINE_EDMA4, 180) +#define IMXRT_DMACHAN_SAI2_RX IMXRT_DMA_SRC(IMXRT_DMA_ENGINE_EDMA4, 181) +#define IMXRT_DMACHAN_SAI4_TX IMXRT_DMA_SRC(IMXRT_DMA_ENGINE_EDMA4, 184) +#define IMXRT_DMACHAN_SAI4_RX IMXRT_DMA_SRC(IMXRT_DMA_ENGINE_EDMA4, 185) +#define IMXRT_DMACHAN_SINC1_REQUEST0 IMXRT_DMA_SRC(IMXRT_DMA_ENGINE_EDMA4, 208) +#define IMXRT_DMACHAN_SINC1_REQUEST1 IMXRT_DMA_SRC(IMXRT_DMA_ENGINE_EDMA4, 209) +#define IMXRT_DMACHAN_SINC1_REQUEST2 IMXRT_DMA_SRC(IMXRT_DMA_ENGINE_EDMA4, 210) +#define IMXRT_DMACHAN_SINC1_REQUEST3 IMXRT_DMA_SRC(IMXRT_DMA_ENGINE_EDMA4, 211) +#define IMXRT_DMACHAN_SINC2_REQUEST0 IMXRT_DMA_SRC(IMXRT_DMA_ENGINE_EDMA4, 212) +#define IMXRT_DMACHAN_SINC2_REQUEST1 IMXRT_DMA_SRC(IMXRT_DMA_ENGINE_EDMA4, 213) +#define IMXRT_DMACHAN_SINC2_REQUEST2 IMXRT_DMA_SRC(IMXRT_DMA_ENGINE_EDMA4, 214) +#define IMXRT_DMACHAN_SINC2_REQUEST3 IMXRT_DMA_SRC(IMXRT_DMA_ENGINE_EDMA4, 215) +#define IMXRT_DMACHAN_CAN2 IMXRT_DMA_SRC(IMXRT_DMA_ENGINE_EDMA4, 1) +#define IMXRT_DMACHAN_TPM5_REQUEST0_REQUEST2 IMXRT_DMA_SRC(IMXRT_DMA_ENGINE_EDMA4, 31) +#define IMXRT_DMACHAN_TPM5_REQUEST1_REQUEST3 IMXRT_DMA_SRC(IMXRT_DMA_ENGINE_EDMA4, 32) +#define IMXRT_DMACHAN_TPM5_OVERFLOW_REQUEST IMXRT_DMA_SRC(IMXRT_DMA_ENGINE_EDMA4, 33) +#define IMXRT_DMACHAN_TPM6_REQUEST0_REQUEST2 IMXRT_DMA_SRC(IMXRT_DMA_ENGINE_EDMA4, 34) +#define IMXRT_DMACHAN_TPM6_REQUEST1_REQUEST3 IMXRT_DMA_SRC(IMXRT_DMA_ENGINE_EDMA4, 35) +#define IMXRT_DMACHAN_TPM6_OVERFLOW_REQUEST IMXRT_DMA_SRC(IMXRT_DMA_ENGINE_EDMA4, 36) +#define IMXRT_DMACHAN_LPUART9_TX IMXRT_DMA_SRC(IMXRT_DMA_ENGINE_EDMA4, 172) +#define IMXRT_DMACHAN_LPUART9_RX IMXRT_DMA_SRC(IMXRT_DMA_ENGINE_EDMA4, 173) +#define IMXRT_DMACHAN_LPUART10_TX IMXRT_DMA_SRC(IMXRT_DMA_ENGINE_EDMA4, 174) +#define IMXRT_DMACHAN_LPUART10_RX IMXRT_DMA_SRC(IMXRT_DMA_ENGINE_EDMA4, 175) +#define IMXRT_DMACHAN_LPUART11_TX IMXRT_DMA_SRC(IMXRT_DMA_ENGINE_EDMA4, 176) +#define IMXRT_DMACHAN_LPUART11_RX IMXRT_DMA_SRC(IMXRT_DMA_ENGINE_EDMA4, 177) +#define IMXRT_DMACHAN_SAI3_TX IMXRT_DMA_SRC(IMXRT_DMA_ENGINE_EDMA4, 182) +#define IMXRT_DMACHAN_SAI3_RX IMXRT_DMA_SRC(IMXRT_DMA_ENGINE_EDMA4, 183) +#define IMXRT_DMACHAN_CMP1 IMXRT_DMA_SRC(IMXRT_DMA_ENGINE_EDMA4, 187) +#define IMXRT_DMACHAN_CMP2 IMXRT_DMA_SRC(IMXRT_DMA_ENGINE_EDMA4, 188) +#define IMXRT_DMACHAN_CMP4 IMXRT_DMA_SRC(IMXRT_DMA_ENGINE_EDMA4, 190) + +#endif /* __ARCH_ARM_SRC_IMXRT_HARDWARE_RT118X_IMXRT118X_DMAMUX_H */ diff --git a/arch/arm/src/imxrt/hardware/rt118x/imxrt118x_edma.h b/arch/arm/src/imxrt/hardware/rt118x/imxrt118x_edma.h new file mode 100644 index 0000000000000..32b94afb8e061 --- /dev/null +++ b/arch/arm/src/imxrt/hardware/rt118x/imxrt118x_edma.h @@ -0,0 +1,444 @@ +/**************************************************************************** + * arch/arm/src/imxrt/hardware/rt118x/imxrt118x_edma.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_IMXRT_HARDWARE_RT118X_IMXRT118X_EDMA_H +#define __ARCH_ARM_SRC_IMXRT_HARDWARE_RT118X_IMXRT118X_EDMA_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include + +#include "hardware/imxrt_memorymap.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#define EDMA_CONFIG_SWSTART (1 << 6) /* Start by software trigger */ + +/* eDMA3 / eDMA4 Register Offsets */ + +#define IMXRT_EDMA_CSR_OFFSET (0x000000) /* Management Page Control Register (CSR) */ +#define IMXRT_EDMA_ES_OFFSET (0x000004) /* Management Page Error Status Register (ES) */ +#define IMXRT_EDMA_CH_GRPRI_OFFSET(n) (0x000100 + ((n) << 2)) /* Channel n Arbitration Group Register (CHn_GRPRI) */ + +/* eDMA3 only */ + +#define IMXRT_EDMA_INT_OFFSET (0x000008) /* Management Page Interrupt Request Status Register (INT) */ +#define IMXRT_EDMA_HRS_OFFSET (0x00000c) /* Management Page Hardware Request Status Register (HRS) */ + +/* eDMA4 only */ + +#define IMXRT_EDMA_INT_LOW_OFFSET (0x000008) /* Management Page Interrupt Request Status Register (INT_LOW) */ +#define IMXRT_EDMA_INT_HIGH_OFFSET (0x00000c) /* Management Page Interrupt Request Status Register (INT_HIGH) */ +#define IMXRT_EDMA_HRS_LOW_OFFSET (0x000010) /* Management Page Hardware Request Status Register (HRS_LOW) */ +#define IMXRT_EDMA_HRS_HIGH_OFFSET (0x000014) /* Management Page Hardware Request Status Register (HRS_HIGH) */ + +/* eDMA3 / eDMA4 Register Addresses */ + +#define IMXRT_EDMA_CSR(n) ((n) + IMXRT_EDMA_CSR_OFFSET) +#define IMXRT_EDMA_ES(n) ((n) + IMXRT_EDMA_ES_OFFSET) +#define IMXRT_EDMA_CH_GRPRI(n,c) ((n) + IMXRT_EDMA_CH_GRPRI_OFFSET(c)) + +/* eDMA3 only */ + +#define IMXRT_EDMA_INT (IMXRT_DMA3_BASE + IMXRT_EDMA_INT_OFFSET) +#define IMXRT_EDMA_HRS (IMXRT_DMA3_BASE + IMXRT_EDMA_HRS_OFFSET) + +/* eDMA4 only */ + +#define IMXRT_EDMA_INT_LOW (IMXRT_DMA4_BASE + IMXRT_EDMA_INT_LOW_OFFSET) +#define IMXRT_EDMA_INT_HIGH (IMXRT_DMA4_BASE + IMXRT_EDMA_INT_HIGH_OFFSET) +#define IMXRT_EDMA_HRS_LOW (IMXRT_DMA4_BASE + IMXRT_EDMA_HRS_LOW_OFFSET) +#define IMXRT_EDMA_HRS_HIGH (IMXRT_DMA4_BASE + IMXRT_EDMA_HRS_HIGH_OFFSET) + +/* eDMA Transfer Control Descriptor (TCD) Register Offsets */ + +#define IMXRT_EDMA_CH_CSR_OFFSET (0x000000) /* Channel Control and Status Register (CH0_CSR) */ +#define IMXRT_EDMA_CH_ES_OFFSET (0x000004) /* Channel Error Status Register (CH0_ES) */ +#define IMXRT_EDMA_CH_INT_OFFSET (0x000008) /* Channel Interrupt Status Register (CH0_INT) */ +#define IMXRT_EDMA_CH_SBR_OFFSET (0x00000c) /* Channel System Bus Register (CH0_SBR) */ +#define IMXRT_EDMA_CH_PRI_OFFSET (0x000010) /* Channel Priority Register (CH0_PRI) */ +#define IMXRT_EDMA_CH_MUX_OFFSET (0x000014) /* Channel Multiplexor Configuration (CH0_MUX) (eDMA4 only) */ +#define IMXRT_EDMA_CH_MATTR_OFFSET (0x000018) /* Memory Attributes Register (CH0_MATTR) (eDMA4 only) */ +#define IMXRT_EDMA_TCD_SADDR_OFFSET (0x000020) /* TCD Source Address Register (TCD0_SADDR) */ +#define IMXRT_EDMA_TCD_SOFF_OFFSET (0x000024) /* TCD Signed Source Address Offset Register (TCD0_SOFF) */ +#define IMXRT_EDMA_TCD_ATTR_OFFSET (0x000026) /* TCD Transfer Attributes (TCD0_ATTR) */ +#define IMXRT_EDMA_TCD_NBYTES_OFFSET (0x000028) /* TCD Transfer Size (TCD0_NBYTES) */ +#define IMXRT_EDMA_TCD_SLAST_SDA_OFFSET (0x00002c) /* TCD Last Source Address Adjustment / Store DADDR Address Register (TCD0_SLAST_SDA) */ +#define IMXRT_EDMA_TCD_DADDR_OFFSET (0x000030) /* TCD Destination Address Register (TCD0_DADDR) */ +#define IMXRT_EDMA_TCD_DOFF_OFFSET (0x000034) /* TCD Signed Destination Address Offset Register (TCD0_DOFF) */ +#define IMXRT_EDMA_TCD_CITER_OFFSET (0x000036) /* TCD Current Major Loop Count Register (TCD0_CITER) */ +#define IMXRT_EDMA_TCD_DLAST_SGA_OFFSET (0x000038) /* TCD Last Destination Address Adjustment / Scatter Gather Address Register (TCD0_DLAST_SGA)*/ +#define IMXRT_EDMA_TCD_CSR_OFFSET (0x00003c) /* TCD Control and Status Register (TCD0_CSR) */ +#define IMXRT_EDMA_TCD_BITER_OFFSET (0x00003e) /* TCD Beginning Major Loop Count Register (TCD0_BITER) */ + +/* eDMA 3 and eDMA 4 have TCD instance offsets, but same base offset */ + +#define IMXRT_EDMA_TCD_BASE_OFFSET (0x10000) /* Offset to TCD for both eDMA3/4 */ +#define IMXRT_EDMA3_TCD_INST_OFFSET (0x10000) /* Per instance TCD offset for eDMA3 */ +#define IMXRT_EDMA4_TCD_INST_OFFSET (0x8000) /* Per instance TCD offset for eDMA4 */ +#define IMXRT_EDMA_TCD_BASE(n) ((n) + IMXRT_EDMA_TCD_BASE_OFFSET) +#define IMXRT_EDMA_TCD_INST_OFFSET(n) ((n) == IMXRT_DMA3_BASE ? IMXRT_EDMA3_TCD_INST_OFFSET : IMXRT_EDMA4_TCD_INST_OFFSET) +#define IMXRT_EDMA_TCD(n,t) (IMXRT_EDMA_TCD_BASE(n) + (t) * IMXRT_EDMA_TCD_INST_OFFSET(n)) + +/* eDMA Transfer Control Descriptor (TCD) Register Addresses ****************/ + +#define IMXRT_EDMA_CH_CSR(n,t) (IMXRT_EDMA_TCD(n,t) + IMXRT_EDMA_CH_CSR_OFFSET) +#define IMXRT_EDMA_CH_ES(n,t) (IMXRT_EDMA_TCD(n,t) + IMXRT_EDMA_CH_ES_OFFSET) +#define IMXRT_EDMA_CH_INT(n,t) (IMXRT_EDMA_TCD(n,t) + IMXRT_EDMA_CH_INT_OFFSET) +#define IMXRT_EDMA_CH_SBR(n,t) (IMXRT_EDMA_TCD(n,t) + IMXRT_EDMA_CH_SBR_OFFSET) +#define IMXRT_EDMA_CH_PRI(n,t) (IMXRT_EDMA_TCD(n,t) + IMXRT_EDMA_CH_PRI_OFFSET) +#define IMXRT_EDMA_CH_MUX(n,t) (IMXRT_EDMA_TCD(n,t) + IMXRT_EDMA_CH_MUX_OFFSET) +#define IMXRT_EDMA_TCD_SADDR(n,t) (IMXRT_EDMA_TCD(n,t) + IMXRT_EDMA_TCD_SADDR_OFFSET) +#define IMXRT_EDMA_TCD_SOFF(n,t) (IMXRT_EDMA_TCD(n,t) + IMXRT_EDMA_TCD_SOFF_OFFSET) +#define IMXRT_EDMA_TCD_ATTR(n,t) (IMXRT_EDMA_TCD(n,t) + IMXRT_EDMA_TCD_ATTR_OFFSET) +#define IMXRT_EDMA_TCD_NBYTES(n,t) (IMXRT_EDMA_TCD(n,t) + IMXRT_EDMA_TCD_NBYTES_OFFSET) +#define IMXRT_EDMA_TCD_SLAST_SDA(n,t) (IMXRT_EDMA_TCD(n,t) + IMXRT_EDMA_TCD_SLAST_SDA_OFFSET) +#define IMXRT_EDMA_TCD_DADDR(n,t) (IMXRT_EDMA_TCD(n,t) + IMXRT_EDMA_TCD_DADDR_OFFSET) +#define IMXRT_EDMA_TCD_DOFF(n,t) (IMXRT_EDMA_TCD(n,t) + IMXRT_EDMA_TCD_DOFF_OFFSET) +#define IMXRT_EDMA_TCD_CITER(n,t) (IMXRT_EDMA_TCD(n,t) + IMXRT_EDMA_TCD_CITER_OFFSET) +#define IMXRT_EDMA_TCD_DLAST_SGA(n,t) (IMXRT_EDMA_TCD(n,t) + IMXRT_EDMA_TCD_DLAST_SGA_OFFSET) +#define IMXRT_EDMA_TCD_CSR(n,t) (IMXRT_EDMA_TCD(n,t) + IMXRT_EDMA_TCD_CSR_OFFSET) +#define IMXRT_EDMA_TCD_BITER(n,t) (IMXRT_EDMA_TCD(n,t) + IMXRT_EDMA_TCD_BITER_OFFSET) + +/* eDMA Register Bitfield Definitions ***************************************/ + +/* Management Page Control Register (CSR) */ + + /* Bit 0: Reserved */ +#define EDMA_CSR_EDBG (1 << 1) /* Bit 1: Enable Debug (EDBG) */ +#define EDMA_CSR_ERCA (1 << 2) /* Bit 2: Enable Round Robin Channel Arbitration (ERCA) */ + /* Bit 3: Reserved */ +#define EDMA_CSR_HAE (1 << 4) /* Bit 4: Halt After Error (HAE) */ +#define EDMA_CSR_HALT (1 << 5) /* Bit 5: Halt DMA Operations (HALT) */ +#define EDMA_CSR_GCLC (1 << 6) /* Bit 6: Global Channel Linking Control (GCLC) */ +#define EDMA_CSR_GMRC (1 << 7) /* Bit 7: Global Master ID Replication Control (GMRC) */ +#define EDMA_CSR_ECX (1 << 8) /* Bit 8: Cancel Transfer With Error (ECX) */ +#define EDMA_CSR_CX (1 << 9) /* Bit 9: Cancel Transfer (CX) */ + /* Bits 10-23: Reserved */ +#define EDMA_CSR_ACTIVE_ID_SHIFT (24) /* Bits 24-28: Active Channel ID (ACTIVE_ID) */ +#define EDMA_CSR_ACTIVE_ID_MASK (0x1f << EDMA_CSR_ACTIVE_ID_SHIFT) + /* Bits 29-30: Reserved */ +#define EDMA_CSR_ACTIVE (1 << 31) /* Bit 31: DMA Active Status (ACTIVE) */ + +/* Management Page Error Status Register (ES) */ + +#define EDMA_ES_DBE (1 << 0) /* Bit 0: Destination Bus Error (DBE) */ +#define EDMA_ES_SBE (1 << 1) /* Bit 1: Source Bus Error (SBE) */ +#define EDMA_ES_SGE (1 << 2) /* Bit 2: Scatter/Gather Configuration Error (SGE) */ +#define EDMA_ES_NCE (1 << 3) /* Bit 3: NBYTES/CITER Configuration Error (NCE) */ +#define EDMA_ES_DOE (1 << 4) /* Bit 4: Destination Offset Error (DOE) */ +#define EDMA_ES_DAE (1 << 5) /* Bit 5: Destination Address Error (DAE) */ +#define EDMA_ES_SOE (1 << 6) /* Bit 6: Source Offset Error (SOE) */ +#define EDMA_ES_SAE (1 << 7) /* Bit 7: Source Address Error (SAE) */ +#define EDMA_ES_ECX (1 << 8) /* Bit 8: Transfer Canceled (ECX) */ + /* Bits 9-23: Reserved */ +#define EDMA_ES_ERRCHN_SHIFT (24) /* Bits 24-28: Error Channel Number or Canceled Channel Number (ERRCHN) */ +#define EDMA_ES_ERRCHN_MASK (0x1f << EDMA_ES_ERRCHN_SHIFT) + /* Bits 29-30: Reserved */ +#define EDMA_ES_VLD (1 << 31) /* Bit 31: Logical OR of all ERR status fields (VALID) */ + +/* Management Page Interrupt Request Status Register (INT) */ + +#define EDMA_INT(n) (1 << (n)) /* Bit n: Interrupt Request Status (INT) */ + +/* Management Page Hardware Request Status Register (HRS) */ + +#define EDMA_HRS(n) (1 << (n)) /* Bit n: Hardware Request Status (HRS) */ + +/* Channel n Arbitration Group Register (CHn_GRPRI) */ + +#define EDMA_CH_GRPRI_SHIFT (0) /* Bits 0-4: Arbitration Group For Channel n (GRPRI) */ +#define EDMA_CH_GRPRI_MASK (0x1f << EDMA_CH_GRPRI_SHIFT) + /* Bits 5-31: Reserved */ + +/* eDMA Transfer Control Descriptor (TCD) Bitfield Definitions **************/ + +/* Channel n Control and Status Register (CHn_CSR) */ + +#define EDMA_CH_CSR_ERQ (1 << 0) /* Bit 0: Enable DMA Request (ERQ) */ +#define EDMA_CH_CSR_EARQ (1 << 1) /* Bit 1: Enable Asynchronous DMA Request in Stop Mode for Channel (EARQ) */ +#define EDMA_CH_CSR_EEI (1 << 2) /* Bit 2: Enable Error Interrupt (EEI) */ +#define EDMA_CH_CSR_EBW (1 << 3) /* Bit 3: Enable Buffered Writes (EBW) */ + /* Bit 4-29: Reserved */ +#define EDMA_CH_CSR_DONE (1 << 30) /* Bit 30: Channel Done (DONE) */ +#define EDMA_CH_CSR_ACTIVE (1 << 31) /* Bit 31: CHannel Active (ACTIVE) */ + +/* Channel n Error Status Register (CHn_ES) */ + +#define EDMA_CH_ES_DBE (1 << 0) /* Bit 0: Destination Bus Error (DBE) */ +#define EDMA_CH_ES_SBE (1 << 1) /* Bit 1: Source Bus Error (SBE) */ +#define EDMA_CH_ES_SGE (1 << 2) /* Bit 2: Scatter/Gather Configuration Error (SGE) */ +#define EDMA_CH_ES_NCE (1 << 3) /* Bit 3: NBYTES/CITER Configuration Error (NCE) */ +#define EDMA_CH_ES_DOE (1 << 4) /* Bit 4: Destination Offset Error (DOE) */ +#define EDMA_CH_ES_DAE (1 << 5) /* Bit 5: Destination Address Error (DAE) */ +#define EDMA_CH_ES_SOE (1 << 6) /* Bit 6: Source Offset Error (SOE) */ +#define EDMA_CH_ES_SAE (1 << 7) /* Bit 7: Source Address Error (SAE) */ + /* Bit 8-30: Reserved */ +#define EDMA_CH_ES_ERR (1 << 31) /* Bit 31: Error in this channel (ERR) */ + +/* Channel n Interrupt Status Register (CHn_INT) */ + +#define EDMA_CH_INT (1 << 0) /* Bit 0: Interrupt Request (INT) */ + /* Bits 1-31: Reserved */ + +/* Channel n System Bus Register (CHn_SBR) */ + +#define EDMA_CH_SBR_MID_SHIFT (0) /* Bits 0-3: Master ID (MID) */ +#define EDMA_CH_SBR_MID_MASK (0x0f << EDMA_CH_SBR_MID_SHIFT) + /* Bits 4-13: Reserved */ +#define EDMA_CH_SBR_SEC (1 << 14) /* Bit 14: Security Level (SEC) */ +#define EDMA_CH_SBR_PAL (1 << 15) /* Bit 15: Privileged Access Level (PAL) */ +#define EDMA_CH_SBR_EMI (1 << 16) /* Bit 16: Enable Master ID Replication (EMI) */ +#define EDMA_CH_SBR_ATTR_SHIFT (17) /* Bits 17-19: Attribute Output (ATTR) */ +#define EDMA_CH_SBR_ATTR_MASK (0x07 << EDMA_CH_SBR_ATTR_SHIFT) + /* Bits 20-31: Reserved */ + +/* Channel n Priority Register (CHn_PRI) */ + +#define EDMA_CH_PRI_APL_SHIFT (0) /* Bits 0-2: Arbitration Priority Level (APL) */ +#define EDMA_CH_PRI_APL_MASK (0x07 << EDMA_CH_PRI_APL_SHIFT) + /* Bits 3-29: Reserved */ +#define EDMA_CH_PRI_DPA (1 << 30) /* Bit 30: Disable Preempt Ability (DPA) */ +#define EDMA_CH_PRI_ECP (1 << 31) /* Bit 31: Enable Channel Preemption (ECP) */ + +/* Channel Multiplexor Configuration (CHn_MUX). On RT1180 the mux source + * ID field is 8-bit for eDMA4 (up to 256 sources) and 6-bit for eDMA3. + * Using the wider mask is safe since unused high bits are reserved. + */ + +#define EDMA_CH_SRC_SHIFT (0) /* Bits 0-7: Service Request Source */ +#define EDMA_CH_SRC_MASK (0xff << EDMA_CH_SRC_SHIFT) + +/* TCDn Source Address Register (TCDn_SADDR) */ + +#define EDMA_TCD_SADDR_SHIFT (0) /* Bits 0-31: Source Address (SADDR) */ +#define EDMA_TCD_SADDR_MASK (0xffffffff << EDMA_TCD_SADDR_SHIFT) + +/* TCDn Signed Source Address Offset Register (TCDn_SOFF) */ + +#define EDMA_TCD_SOFF_SHIFT (0) /* Bits 0-31: Source Address Signed Offset (SOFF) */ +#define EDMA_TCD_SOFF_MASK (0xffffffff << EDMA_TCD_SOFF_SHIFT) + +/* TCDn Transfer Attributes (TCDn_ATTR) */ + +#define EDMA_TCD_ATTR_DSIZE_SHIFT (0) /* Bits 0-2: Destination Data Transfer Size (DSIZE) */ +#define EDMA_TCD_ATTR_DSIZE_MASK (0x07 << EDMA_TCD_ATTR_DSIZE_SHIFT) +#define EDMA_TCD_ATTR_DSIZE(n) (((n) << EDMA_TCD_ATTR_DSIZE_SHIFT) & EDMA_TCD_ATTR_DSIZE_MASK) +#define EDMA_TCD_ATTR_DMOD_SHIFT (3) /* Bits 3-7: Destination Address Modulo (DMOD) */ +#define EDMA_TCD_ATTR_DMOD_MASK (0x1f << EDMA_TCD_ATTR_DMOD_SHIFT) +#define EDMA_TCD_ATTR_DMOD(n) (((n) << EDMA_TCD_ATTR_DMOD_SHIFT) & EDMA_TCD_ATTR_DMOD_MASK) +#define EDMA_TCD_ATTR_SSIZE_SHIFT (8) /* Bits 8-10: Source Data Transfer Size (SSIZE) */ +#define EDMA_TCD_ATTR_SSIZE_MASK (0x07 << EDMA_TCD_ATTR_SSIZE_SHIFT) +#define EDMA_TCD_ATTR_SSIZE(n) (((n) << EDMA_TCD_ATTR_SSIZE_SHIFT) & EDMA_TCD_ATTR_SSIZE_MASK) +# define EDMA_TCD_ATTR_SSIZE_8BIT (0x00 << EDMA_TCD_ATTR_SSIZE_SHIFT) /* 8-bit */ +# define EDMA_TCD_ATTR_SSIZE_16BIT (0x01 << EDMA_TCD_ATTR_SSIZE_SHIFT) /* 16-bit */ +# define EDMA_TCD_ATTR_SSIZE_32BIT (0x02 << EDMA_TCD_ATTR_SSIZE_SHIFT) /* 32-bit */ +# define EDMA_TCD_ATTR_SSIZE_64BIT (0x03 << EDMA_TCD_ATTR_SSIZE_SHIFT) /* 64-bit */ +# define EDMA_TCD_ATTR_SSIZE_16BYTE (0x04 << EDMA_TCD_ATTR_SSIZE_SHIFT) /* 16-byte */ +# define EDMA_TCD_ATTR_SSIZE_32BYTE (0x05 << EDMA_TCD_ATTR_SSIZE_SHIFT) /* 32-byte */ +# define EDMA_TCD_ATTR_SSIZE_64BYTE (0x06 << EDMA_TCD_ATTR_SSIZE_SHIFT) /* 64-byte */ + +#define EDMA_TCD_ATTR_SMOD_SHIFT (11) /* Bits 11-15: Source Address Modulo (SMOD) */ +#define EDMA_TCD_ATTR_SMOD_MASK (0x1f << EDMA_TCD_ATTR_SMOD_SHIFT) +#define EDMA_TCD_ATTR_SMOD(n) (((n) << EDMA_TCD_ATTR_SMOD_SHIFT) & EDMA_TCD_ATTR_SMOD_MASK) + +/* TCDn Transfer Size (TCDn_NBYTES) */ + +#define EDMA_TCD_NBYTES_SHIFT (0) /* Bits 0-29: Number of Bytes to Transfer per Service Request (NBYTES) */ +#define EDMA_TCD_NBYTES_MASK (0x3fffffff << EDMA_TCD_NBYTES_SHIFT) +#define EDMA_TCD_NBYTES_MASK_MLOFF (0x03ff << EDMA_TCD_NBYTES_SHIFT) +#define EDMA_TCD_NBYTES_MLOFF_SHIFT (10) /* Bits 10-29: Minor Loop Offset (MLOFF) */ +#define EDMA_TCD_NBYTES_MLOFF_MASK (0x0fffff << EDMA_TCD_NBYTES_MLOFF_SHIFT) +#define EDMA_TCD_NBYTES_DMLOE (1 << 30) /* Bit 30: Destination Minor Loop Offset Enable (DMLOE) */ +#define EDMA_TCD_NBYTES_SMLOE (1 << 31) /* Bit 31: Source Minor Loop Offset Enable (SMLOE) */ + +/* TCDn Last Source Address Adjustment / Store DADDR Address Register + * (TCDn_SLAST_SDA) + */ + +#define EDMA_TCD_SLAST_SDA_SHIFT (0) /* Bits 0-31: Last Source Address Adjustment / Store DADDR Address (SLAST_SDA) */ +#define EDMA_TCD_SLAST_SDA_MASK (0xffffffff << EDMA_TCD_SLAST_SDA_SHIFT) + +/* TCDn Destination Address Register (TCDn_DADDR) */ + +#define EDMA_TCD_DADDR_SHIFT (0) /* Bits 0-31: Destination Address (DADDR) */ +#define EDMA_TCD_DADDR_MASK (0xffffffff << EDMA_TCD_DADDR_SHIFT) + +/* TCDn Signed Destination Address Offset Register (TCDn_DOFF) */ + +#define EDMA_TCD_DOFF_SHIFT (0) /* Bits 0-15: Destination Address Signed Offset (DOFF) */ +#define EDMA_TCD_DOFF_MASK (0xffff << EDMA_TCD_DOFF_SHIFT) + +/* TCDn Current Major Loop Count Register (TCDn_CITER) */ + +#define EDMA_TCD_CITER_SHIFT (0) /* Bits 0-14: Current Major Iteration Count (CITER) */ +#define EDMA_TCD_CITER_MASK (0x7fff << EDMA_TCD_CITER_SHIFT) +#define EDMA_TCD_CITER_MASK_ELINK (0x01ff << EDMA_TCD_CITER_SHIFT) +#define EDMA_TCD_CITER_LINKCH_SHIFT (9) /* Bits 9-13: Minor Loop Link Channel Number (LINKCH) */ +#define EDMA_TCD_CITER_LINKCH_MASK (0x1f << EDMA_TCD_CITER_LINKCH_SHIFT) +#define EDMA_TCD_CITER_LINKCH(n) (((n) << EDMA_TCD_CITER_LINKCH_SHIFT) & EDMA_TCD_CITER_LINKCH_SHIFT) +#define EDMA_TCD_CITER_ELINK (1 << 15) /* Bit 15: Enable Link (ELINK) */ + +/* TCDn Last Destination Address Adjustment / Scatter Gather Address Register + * (TCDn_DLAST_SGA) + */ + +#define EDMA_TCD_DLAST_SGA_SHIFT (0) /* Bits 0-31: Last Destination Address Adjustment / Scatter Gather Address (DLAST_SGA) */ +#define EDMA_TCD_DLAST_SGA_MASK (0xffffffff << EDMA_TCD_DLAST_SGA_SHIFT) + +/* TCDn Control and Status Register (TCDn_CSR) */ + +#define EDMA_TCD_CSR_START (1 << 0) /* Bit 0: Channel Start (START) */ +#define EDMA_TCD_CSR_INTMAJOR (1 << 1) /* Bit 1: Enable Interrupt if Major count complete (INTMAJOR) */ +#define EDMA_TCD_CSR_INTHALF (1 << 2) /* Bit 2: Enable Interrupt if Major Count Half-complete (INTHALF) */ +#define EDMA_TCD_CSR_DREQ (1 << 3) /* Bit 3: Disable Request (DREQ) */ +#define EDMA_TCD_CSR_ESG (1 << 4) /* Bit 4: Enable Scatter/Gather Processing (ESG) */ +#define EDMA_TCD_CSR_MAJORELINK (1 << 5) /* Bit 5: Enable Link When Major Loop Complete (MAJORELINK) */ +#define EDMA_TCD_CSR_EEOP (1 << 6) /* Bit 6: Enable End-Of-Packet Processing (EEOP) */ +#define EDMA_TCD_CSR_ESDA (1 << 7) /* Bit 7: Enable Store Destination Address (ESDA) */ +#define EDMA_TCD_CSR_MAJORLINKCH_SHIFT (8) /* Bits 8-12: Major Loop Link Channel Number (MAJORLINKCH) */ +#define EDMA_TCD_CSR_MAJORLINKCH_MASK (0x1f << EDMA_TCD_CSR_MAJORLINKCH_SHIFT) +#define EDMA_TCD_CSR_MAJORLINKCH(n) (((n) << EDMA_TCD_CSR_MAJORLINKCH_SHIFT) & EDMA_TCD_CSR_MAJORLINKCH_MASK) + /* Bit 13: Reserved */ +#define EDMA_TCD_CSR_BWC_SHIFT (14) /* Bits 14-15: Bandwidth Control (BWC) */ +#define EDMA_TCD_CSR_BWC_MASK (0x03 << EDMA_TCD_CSR_BWC_SHIFT) +# define EDMA_TCD_CSR_BWC_NOSTALL (0x00 << EDMA_TCD_CSR_BWC_SHIFT) /* No eDMA engine stalls */ +# define EDMA_TCD_CSR_BWC_HPE (0x01 << EDMA_TCD_CSR_BWC_SHIFT) /* Enable eDMA master high-priority elevation (HPE) mode */ +# define EDMA_TCD_CSR_BWC_4CYCLES (0x02 << EDMA_TCD_CSR_BWC_SHIFT) /* eDMA engine stalls for 4 cycles after each R/W */ +# define EDMA_TCD_CSR_BWC_8CYCLES (0x03 << EDMA_TCD_CSR_BWC_SHIFT) /* eDMA engine stalls for 8 cycles after each R/W */ + +/* TCDn Beginning Major Loop Count Register (TCDn_BITER) */ + +#define EDMA_TCD_BITER_SHIFT (0) /* Bits 0-14: Starting Major Iteration Count (BITER) */ +#define EDMA_TCD_BITER_MASK (0x7fff << EDMA_TCD_BITER_SHIFT) +#define EDMA_TCD_BITER_MASK_ELINK (0x01ff << EDMA_TCD_BITER_SHIFT) +#define EDMA_TCD_BITER_LINKCH_SHIFT (9) /* Bits 9-13: Link Channel Number (LINKCH) */ +#define EDMA_TCD_BITER_LINKCH_MASK (0x1f << EDMA_TCD_BITER_LINKCH_SHIFT) +#define EDMA_TCD_BITER_LINKCH(n) (((n) << EDMA_TCD_BITER_LINKCH_SHIFT) & EDMA_TCD_BITER_LINKCH_MASK) +#define EDMA_TCD_BITER_ELINK (1 << 15) /* Bit 15: Enable Link (ELINK) */ + +/* Amount of channels */ + +#define DMA3_CHANNEL_COUNT (32) +#define DMA4_CHANNEL_COUNT (64) +#define IMXRT_EDMA_NCHANNELS (DMA3_CHANNEL_COUNT + DMA4_CHANNEL_COUNT) + +/* Amount of interrupt sources */ + +#define DMA3_IRQ_COUNT (32) /* Error interrupt not counted */ +#define DMA4_IRQ_COUNT (16) /* Error interrupt not counted; + * 4 channels share one IRQ */ + +/**************************************************************************** + * Public Types + ****************************************************************************/ + +/* In-memory representation of the 32-byte Transfer Control Descriptor + * (TCD) + */ + +struct imxrt_edmatcd_s +{ + uint32_t saddr; /* Offset: 0x0000 TCD Source Address */ + uint16_t soff; /* Offset: 0x0004 TCD Signed Source Address Offset */ + uint16_t attr; /* Offset: 0x0006 TCD Transfer Attributes */ + uint32_t nbytes; /* Offset: 0x0008 TCD Signed Minor Loop Offset / Byte Count */ + uint32_t slast; /* Offset: 0x000c TCD Last Source Address Adjustment */ + uint32_t daddr; /* Offset: 0x0010 TCD Destination Address */ + uint16_t doff; /* Offset: 0x0014 TCD Signed Destination Address Offset */ + uint16_t citer; /* Offset: 0x0016 TCD Current Minor Loop Link, Major Loop Count */ + uint32_t dlastsga; /* Offset: 0x0018 TCD Last Destination Address Adjustment/Scatter Gather Address */ + uint16_t csr; /* Offset: 0x001c TCD Control and Status */ + uint16_t biter; /* Offset: 0x001e TCD Beginning Minor Loop Link, Major Loop Count */ +}; + +/**************************************************************************** + * Inline Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: imxrt_edma_tcdhasmux + * + * Description: + * Check if DMA TCD has TCD.MUX register. + * + * Input Parameters: + * dmabase - The eDMA base. + * + * Returned Value: + * true if TCD.MUX exists; false if not. + * + ****************************************************************************/ + +static inline bool imxrt_edma_tcdhasmux(uintptr_t dmabase) +{ + /* On RT1180 both eDMA3 and eDMA4 have per-channel CH_MUX registers. */ + + return true; +} + +/**************************************************************************** + * Name: imxrt_edma_choffset + * + * Description: + * Channel offset in global channel list for dma base. + * + * Input Parameters: + * base - The eDMA base. + * + * Returned Value: + * Channel offset. + * + ****************************************************************************/ + +static inline uint32_t imxrt_edma_choffset(uintptr_t base) +{ + return base == IMXRT_DMA3_BASE ? 0 : DMA3_CHANNEL_COUNT; +} + +/**************************************************************************** + * Name: imxrt_edma_chmax + * + * Description: + * Max channel in global channel list for dma base. + * + * Input Parameters: + * base - The eDMA base. + * + * Returned Value: + * Channel max. + * + ****************************************************************************/ + +static inline uint32_t imxrt_edma_chmax(uintptr_t base) +{ + return base == IMXRT_DMA3_BASE ? DMA3_CHANNEL_COUNT : IMXRT_EDMA_NCHANNELS; +} + +#endif /* __ARCH_ARM_SRC_IMXRT_HARDWARE_RT118X_IMXRT118X_EDMA_H */ diff --git a/arch/arm/src/imxrt/hardware/rt118x/imxrt118x_ele.h b/arch/arm/src/imxrt/hardware/rt118x/imxrt118x_ele.h new file mode 100644 index 0000000000000..ed050eac0d117 --- /dev/null +++ b/arch/arm/src/imxrt/hardware/rt118x/imxrt118x_ele.h @@ -0,0 +1,125 @@ +/**************************************************************************** + * arch/arm/src/imxrt/hardware/rt118x/imxrt118x_ele.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_IMXRT_HARDWARE_RT118X_IMXRT118X_ELE_H +#define __ARCH_ARM_SRC_IMXRT_HARDWARE_RT118X_IMXRT118X_ELE_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include "hardware/imxrt_memorymap.h" +#include + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#define ELE_MAX_MSG 255U + +#define ELE_CMD_TAG 0x17 +#define ELE_VERSION 0x6 +#define ELE_VERSION_FW 0x7 +#define ELE_RESP_TAG 0xe1 +#define ELE_OK 0xd6 + +/* ELE commands. */ + +#define ELE_LOAD_FW_REQ 0x02 +#define ELE_ENABLE_APC_REQ 0xd2 +#define ELE_RELEASE_RDC_REQ 0xc4 +#define ELE_GET_FW_VERSION_REQ 0x9d +#define ELE_DERIVE_KEY_REQ 0xa9 +#define ELE_GET_EVENTS_REQ 0xa2 +#define ELE_GET_TRNG_STATE_REQ 0xa4 +#define ELE_GET_RNG_REQ 0xcd +#define ELE_FWD_LIFECYCLE_UP_REQ 0x95 +#define ELE_OEM_CNTN_AUTH_REQ 0x87 +#define ELE_READ_FUSE_REQ 0x97 +#define ELE_RELEASE_CONTAINER_REQ 0x89 +#define ELE_START_RNG_REQ 0xa3 +#define ELE_VERIFY_IMAGE_REQ 0x88 +#define ELE_COMMIT_REQ 0xa8 +#define ELE_GET_INFO_REQ 0xda +#define ELE_VOLTAGE_CHANGE_START_REQ 0x12 +#define ELE_VOLTAGE_CHANGE_FINISH_REQ 0x13 + +/* RT118x RDC identifiers used by ELE_RELEASE_RDC_REQ, from NXP + * MCUXpresso SDK examples/_boards/evkmimxrt1180/board.c. + */ + +#define ELE_TRDC_AON_ID 0x74 +#define ELE_TRDC_WAKEUP_ID 0x78 +#define ELE_TRDC_MEGA_ID 0x82 + +#define ELE_CORE_CM33_ID 0x1 +#define ELE_CORE_CM7_ID 0x2 + +/* GET_INFO returned data. */ + +#define ELE_GET_INFO_BYTES 160 +#define ELE_GET_INFO_LC_WORD 2 +#define ELE_GET_INFO_LC_MASK 0xffff + +/* System 3 Messaging Unit A (IMXRT1180RM Ch. 65). + * The CM33 boots in Secure state and NXP's own SDK uses the Secure alias + * (0x57540000) rather than the Non-secure alias (0x47540000) for all ELE + * traffic — writes via the Non-secure alias may not reach the enclave + * even though reads mirror the same peripheral. + */ + +#define ELE_MU_TCR (IMXRT_S3MUA_BASE + 0x120) +#define ELE_MU_TSR (IMXRT_S3MUA_BASE + 0x124) +#define ELE_MU_RCR (IMXRT_S3MUA_BASE + 0x128) +#define ELE_MU_RSR (IMXRT_S3MUA_BASE + 0x12c) + +#define ELE_RR_NUM 4 +#define ELE_TR_NUM 8 +#define ELE_MU_TR(i) (IMXRT_S3MUA_BASE + 0x200 + (i) * 4) +#define ELE_MU_RR(i) (IMXRT_S3MUA_BASE + 0x280 + (i) * 4) + +/**************************************************************************** + * Public Types + ****************************************************************************/ + +struct ele_header_t +{ + union + { + uint32_t data; + struct + { + uint32_t version : 8; + uint32_t size : 8; + uint32_t command : 8; + uint32_t tag : 8; + }; + }; +}; + +struct ele_msg +{ + struct ele_header_t header; + uint32_t data[(ELE_MAX_MSG - 1)]; +}; + +#endif /* __ARCH_ARM_SRC_IMXRT_HARDWARE_RT118X_IMXRT118X_ELE_H */ diff --git a/arch/arm/src/imxrt/hardware/rt118x/imxrt118x_gpc.h b/arch/arm/src/imxrt/hardware/rt118x/imxrt118x_gpc.h new file mode 100644 index 0000000000000..aba509b0ab272 --- /dev/null +++ b/arch/arm/src/imxrt/hardware/rt118x/imxrt118x_gpc.h @@ -0,0 +1,85 @@ +/**************************************************************************** + * arch/arm/src/imxrt/hardware/rt118x/imxrt118x_gpc.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_IMXRT_HARDWARE_RT118X_IMXRT118X_GPC_H +#define __ARCH_ARM_SRC_IMXRT_HARDWARE_RT118X_IMXRT118X_GPC_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include "hardware/imxrt_memorymap.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* GPC_CPU_CTRL (IMXRT1180RM Ch. 34). Two instances share the same base: + * index 0 (offset 0x000) - Cortex-M33 + * index 1 (offset 0x800) - Cortex-M7 + */ + +#define IMXRT_GPC_CM_STEP (0x800) + +#define IMXRT_GPC_CM_AUTHEN_CTRL(idx) (IMXRT_GPC_CPU_CTRL_BASE + 0x004 + \ + (idx) * IMXRT_GPC_CM_STEP) +#define IMXRT_GPC_CM_MISC(idx) (IMXRT_GPC_CPU_CTRL_BASE + 0x00c + \ + (idx) * IMXRT_GPC_CM_STEP) +#define IMXRT_GPC_CM_MODE_CTRL(idx) (IMXRT_GPC_CPU_CTRL_BASE + 0x010 + \ + (idx) * IMXRT_GPC_CM_STEP) +#define IMXRT_GPC_CM_MODE_STAT(idx) (IMXRT_GPC_CPU_CTRL_BASE + 0x014 + \ + (idx) * IMXRT_GPC_CM_STEP) + +/* Convenience aliases */ + +#define IMXRT_GPC_CM33_MODE_CTRL IMXRT_GPC_CM_MODE_CTRL(0) +#define IMXRT_GPC_CM33_MODE_STAT IMXRT_GPC_CM_MODE_STAT(0) +#define IMXRT_GPC_CM7_MODE_CTRL IMXRT_GPC_CM_MODE_CTRL(1) +#define IMXRT_GPC_CM7_MODE_STAT IMXRT_GPC_CM_MODE_STAT(1) + +/* CM_MODE_CTRL bit fields */ + +#define GPC_CM_MODE_CTRL_TARGET_SHIFT (0) +#define GPC_CM_MODE_CTRL_TARGET_MASK (0x3u << GPC_CM_MODE_CTRL_TARGET_SHIFT) +#define GPC_CM_MODE_CTRL_TARGET(x) (((x) << GPC_CM_MODE_CTRL_TARGET_SHIFT) & \ + GPC_CM_MODE_CTRL_TARGET_MASK) +#define GPC_CM_MODE_TARGET_RUN (0) +#define GPC_CM_MODE_TARGET_WAIT (1) +#define GPC_CM_MODE_TARGET_STOP (2) +#define GPC_CM_MODE_TARGET_SUSPEND (3) + +#define GPC_CM_MODE_CTRL_WFE_EN (1u << 4) /* WFE can trigger low power */ + +/* CM_MODE_STAT bit fields */ + +#define GPC_CM_MODE_STAT_CURRENT_SHIFT (0) +#define GPC_CM_MODE_STAT_CURRENT_MASK (0x3u << GPC_CM_MODE_STAT_CURRENT_SHIFT) +#define GPC_CM_MODE_STAT_PREVIOUS_SHIFT (2) +#define GPC_CM_MODE_STAT_PREVIOUS_MASK (0x3u << GPC_CM_MODE_STAT_PREVIOUS_SHIFT) + +/* CM_MISC bit fields */ + +#define GPC_CM_MISC_NMI_STAT (1u << 0) +#define GPC_CM_MISC_SLEEP_HOLD_EN (1u << 1) +#define GPC_CM_MISC_SLEEP_HOLD_STAT (1u << 2) + +#endif /* __ARCH_ARM_SRC_IMXRT_HARDWARE_RT118X_IMXRT118X_GPC_H */ diff --git a/arch/arm/src/imxrt/hardware/rt118x/imxrt118x_gpio.h b/arch/arm/src/imxrt/hardware/rt118x/imxrt118x_gpio.h new file mode 100644 index 0000000000000..688b675ded820 --- /dev/null +++ b/arch/arm/src/imxrt/hardware/rt118x/imxrt118x_gpio.h @@ -0,0 +1,119 @@ +/**************************************************************************** + * arch/arm/src/imxrt/hardware/rt118x/imxrt118x_gpio.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_IMXRT_HARDWARE_RT118X_IMXRT118X_GPIO_H +#define __ARCH_ARM_SRC_IMXRT_HARDWARE_RT118X_IMXRT118X_GPIO_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include "hardware/imxrt_memorymap.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* RGPIO register offsets (IMXRT1180RM chapter 16) **************************/ + +#define IMXRT_GPIO_VERID_OFFSET (0x0000) /* Version ID */ +#define IMXRT_GPIO_PARAM_OFFSET (0x0004) /* Parameter */ +#define IMXRT_GPIO_LOCK_OFFSET (0x000c) /* Lock */ +#define IMXRT_GPIO_PCNS_OFFSET (0x0010) /* Pin Control Nonsecure */ +#define IMXRT_GPIO_ICNS_OFFSET (0x0014) /* Interrupt Control Nonsecure */ +#define IMXRT_GPIO_PCNP_OFFSET (0x0018) /* Pin Control Nonprivilege */ +#define IMXRT_GPIO_ICNP_OFFSET (0x001c) /* Interrupt Control Nonprivilege */ +#define IMXRT_GPIO_PDOR_OFFSET (0x0040) /* Port Data Output */ +#define IMXRT_GPIO_PSOR_OFFSET (0x0044) /* Port Set Output */ +#define IMXRT_GPIO_PCOR_OFFSET (0x0048) /* Port Clear Output */ +#define IMXRT_GPIO_PTOR_OFFSET (0x004c) /* Port Toggle Output */ +#define IMXRT_GPIO_PDIR_OFFSET (0x0050) /* Port Data Input */ +#define IMXRT_GPIO_PDDR_OFFSET (0x0054) /* Port Data Direction */ +#define IMXRT_GPIO_PIDR_OFFSET (0x0058) /* Port Input Disable */ +#define IMXRT_GPIO_P0DR_OFFSET (0x0060) /* Pin Data (0-31 at n * 4h) */ +#define IMXRT_GPIO_ICR0_OFFSET (0x0080) /* Interrupt Control (0-31 at n * 4h) */ +#define IMXRT_GPIO_GICLR_OFFSET (0x0100) /* Global Interrupt Control Low */ +#define IMXRT_GPIO_GICHR_OFFSET (0x0104) /* Global Interrupt Control High */ +#define IMXRT_GPIO_ISFR0_OFFSET (0x0120) /* Interrupt Status Flag 0 (0..15) */ +#define IMXRT_GPIO_ISFR1_OFFSET (0x0124) /* Interrupt Status Flag 1 (16..31) */ + +/* GPIO port enumeration ****************************************************/ + +#define GPIO1 0 +#define GPIO2 1 +#define GPIO3 2 +#define GPIO4 3 +#define GPIO5 4 +#define GPIO6 5 + +#define IMXRT_GPIO_NPORTS 6 +#define IMXRT_GPIO_NPINS 32 + +/* Register bit definitions *************************************************/ + +/* Most registers are laid out simply with one bit per pin */ + +#define GPIO_PIN(n) (1u << (n)) /* Bit n: Pin n, n=0-31 */ + +/* ICRN register (per-pin interrupt configuration) */ + +#define IMXRT_GPIO_ICRN_ISF (1u << 24) /* Bit 24: Interrupt Status Flag */ +#define IMXRT_GPIO_ICRN_LK (1u << 23) /* Bit 23: Lock */ +#define IMXRT_GPIO_ICRN_IRQS (1u << 20) /* Bit 20: Selects the interrupt/DMA channel */ +#define IMXRT_GPIO_ICRN_SHIFT (16) /* Bits 16-19: Interrupt Configuration */ +#define IMXRT_GPIO_ICRN_MASK (0xfu << IMXRT_GPIO_ICRN_SHIFT) +# define IMXRT_GPIO_ICRN_DISABLED (0u << IMXRT_GPIO_ICRN_SHIFT) /* ISF disabled */ +# define IMXRT_GPIO_ICRN_DMARISING (1u << IMXRT_GPIO_ICRN_SHIFT) /* DMA rising */ +# define IMXRT_GPIO_ICRN_DMAFALLING (2u << IMXRT_GPIO_ICRN_SHIFT) /* DMA falling */ +# define IMXRT_GPIO_ICRN_DMABOTH (3u << IMXRT_GPIO_ICRN_SHIFT) /* DMA both */ +# define IMXRT_GPIO_ICRN_ISFRISING (5u << IMXRT_GPIO_ICRN_SHIFT) /* ISF-only rising */ +# define IMXRT_GPIO_ICRN_ISFFALLING (6u << IMXRT_GPIO_ICRN_SHIFT) /* ISF-only falling */ +# define IMXRT_GPIO_ICRN_ISFBOTH (7u << IMXRT_GPIO_ICRN_SHIFT) /* ISF-only both */ +# define IMXRT_GPIO_ICRN_ZERO (8u << IMXRT_GPIO_ICRN_SHIFT) /* IRQ when 0 */ +# define IMXRT_GPIO_ICRN_RISING (9u << IMXRT_GPIO_ICRN_SHIFT) /* IRQ rising */ +# define IMXRT_GPIO_ICRN_FALLING (10u << IMXRT_GPIO_ICRN_SHIFT) /* IRQ falling */ +# define IMXRT_GPIO_ICRN_BOTH (11u << IMXRT_GPIO_ICRN_SHIFT) /* IRQ both */ +# define IMXRT_GPIO_ICRN_ONE (12u << IMXRT_GPIO_ICRN_SHIFT) /* IRQ when 1 */ + +/* Global Interrupt Control Low (pins 0..15) */ + +#define IMXRT_GPIO_GICLR_GIWD_SHIFT (0) +#define IMXRT_GPIO_GICLR_GIWD_MASK (0xffffu << IMXRT_GPIO_GICLR_GIWD_SHIFT) +# define IMXRT_GPIO_GICLR_GIWD_PIN(n) ((uint32_t)(n) << IMXRT_GPIO_GICLR_GIWD_SHIFT) +#define IMXRT_GPIO_GICLR_GIWE_SHIFT (16) +#define IMXRT_GPIO_GICLR_GIWE_MASK (0xffffu << IMXRT_GPIO_GICLR_GIWE_SHIFT) +# define IMXRT_GPIO_GICLR_GIWE_PIN(n) ((uint32_t)(n) << IMXRT_GPIO_GICLR_GIWE_SHIFT) + +/* Global Interrupt Control High (pins 16..31) */ + +#define IMXRT_GPIO_GICHR_GIWD_SHIFT (0) +#define IMXRT_GPIO_GICHR_GIWD_MASK (0xffffu << IMXRT_GPIO_GICHR_GIWD_SHIFT) +# define IMXRT_GPIO_GICHR_GIWD_PIN(n) ((uint32_t)((n) - 16) << IMXRT_GPIO_GICHR_GIWD_SHIFT) +#define IMXRT_GPIO_GICHR_GIWE_SHIFT (16) +#define IMXRT_GPIO_GICHR_GIWE_MASK (0xffffu << IMXRT_GPIO_GICHR_GIWE_SHIFT) +# define IMXRT_GPIO_GICHR_GIWE_PIN(n) ((uint32_t)((n) - 16) << IMXRT_GPIO_GICHR_GIWE_SHIFT) + +/* Interrupt Status Flag Register */ + +#define IMXRT_GPIO_ISFR(n) (1u << (n)) /* Interrupt Status Flag, n=0-31 */ + +#endif /* __ARCH_ARM_SRC_IMXRT_HARDWARE_RT118X_IMXRT118X_GPIO_H */ diff --git a/arch/arm/src/imxrt/hardware/rt118x/imxrt118x_iomuxc.h b/arch/arm/src/imxrt/hardware/rt118x/imxrt118x_iomuxc.h new file mode 100644 index 0000000000000..b21a534f338a6 --- /dev/null +++ b/arch/arm/src/imxrt/hardware/rt118x/imxrt118x_iomuxc.h @@ -0,0 +1,220 @@ +/**************************************************************************** + * arch/arm/src/imxrt/hardware/rt118x/imxrt118x_iomuxc.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_IMXRT_HARDWARE_RT118X_IMXRT118X_IOMUXC_H +#define __ARCH_ARM_SRC_IMXRT_HARDWARE_RT118X_IMXRT118X_IOMUXC_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#ifndef __ASSEMBLY__ +# include +#endif + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* IOMUXC register bit-fields (IMXRT1180RM chapter 17) + * + * SW_MUX_CTL_PAD register: + * [3:0] MUX_MODE (alternate function 0..12) + * [4] SION (force input path) + * + * SW_PAD_CTL_PAD register: + * [1] PDRV (0 = high driver, 1 = normal driver) + * [3:2] PULL (00 = keep, 01 = pull-up, 10 = pull-down, 11 = disabled) + * [4] ODE (open drain enable) + * [5] HYS (Schmitt trigger / hysteresis enable) + * [6] FSEL_APC (fast/slow slew select) + * [7] DDR_MODE (DDR input mode; only implemented on selected pads) + */ + +/* MUX_CTL fields */ + +#define IOMUXC_MUX_MODE_SHIFT (0) +#define IOMUXC_MUX_MODE_MASK (0x0fu << IOMUXC_MUX_MODE_SHIFT) +# define IOMUXC_MUX_MODE_ALT(n) (((n) & 0x0fu) << IOMUXC_MUX_MODE_SHIFT) +# define IOMUXC_MUX_MODE_ALT0 IOMUXC_MUX_MODE_ALT(0) +# define IOMUXC_MUX_MODE_ALT1 IOMUXC_MUX_MODE_ALT(1) +# define IOMUXC_MUX_MODE_ALT2 IOMUXC_MUX_MODE_ALT(2) +# define IOMUXC_MUX_MODE_ALT3 IOMUXC_MUX_MODE_ALT(3) +# define IOMUXC_MUX_MODE_ALT4 IOMUXC_MUX_MODE_ALT(4) +# define IOMUXC_MUX_MODE_ALT5 IOMUXC_MUX_MODE_ALT(5) +# define IOMUXC_MUX_MODE_ALT6 IOMUXC_MUX_MODE_ALT(6) +# define IOMUXC_MUX_MODE_ALT7 IOMUXC_MUX_MODE_ALT(7) +# define IOMUXC_MUX_MODE_ALT8 IOMUXC_MUX_MODE_ALT(8) +# define IOMUXC_MUX_MODE_ALT9 IOMUXC_MUX_MODE_ALT(9) +# define IOMUXC_MUX_MODE_ALT10 IOMUXC_MUX_MODE_ALT(10) +# define IOMUXC_MUX_MODE_ALT11 IOMUXC_MUX_MODE_ALT(11) +# define IOMUXC_MUX_MODE_ALT12 IOMUXC_MUX_MODE_ALT(12) + +#define IOMUXC_MUX_SION_SHIFT (4) +#define IOMUXC_MUX_SION_MASK (0x01u << IOMUXC_MUX_SION_SHIFT) +# define IOMUXC_MUX_SION_OFF (0u << IOMUXC_MUX_SION_SHIFT) +# define IOMUXC_MUX_SION_ON (1u << IOMUXC_MUX_SION_SHIFT) + +/* PAD_CTL fields */ + +#define IOMUXC_PAD_PDRV_SHIFT (1) +#define IOMUXC_PAD_PDRV_MASK (0x01u << IOMUXC_PAD_PDRV_SHIFT) +# define IOMUXC_PAD_PDRV_HIGH (0u << IOMUXC_PAD_PDRV_SHIFT) +# define IOMUXC_PAD_PDRV_NORMAL (1u << IOMUXC_PAD_PDRV_SHIFT) + +#define IOMUXC_PAD_PULL_SHIFT (2) +#define IOMUXC_PAD_PULL_MASK (0x03u << IOMUXC_PAD_PULL_SHIFT) +# define IOMUXC_PAD_PULL_KEEP (0u << IOMUXC_PAD_PULL_SHIFT) +# define IOMUXC_PAD_PULL_UP (1u << IOMUXC_PAD_PULL_SHIFT) +# define IOMUXC_PAD_PULL_DOWN (2u << IOMUXC_PAD_PULL_SHIFT) +# define IOMUXC_PAD_PULL_NONE (3u << IOMUXC_PAD_PULL_SHIFT) + +#define IOMUXC_PAD_ODE_SHIFT (4) +#define IOMUXC_PAD_ODE_MASK (0x01u << IOMUXC_PAD_ODE_SHIFT) +# define IOMUXC_PAD_ODE_OFF (0u << IOMUXC_PAD_ODE_SHIFT) +# define IOMUXC_PAD_ODE_ON (1u << IOMUXC_PAD_ODE_SHIFT) + +#define IOMUXC_PAD_HYS_SHIFT (5) +#define IOMUXC_PAD_HYS_MASK (0x01u << IOMUXC_PAD_HYS_SHIFT) +# define IOMUXC_PAD_HYS_OFF (0u << IOMUXC_PAD_HYS_SHIFT) +# define IOMUXC_PAD_HYS_ON (1u << IOMUXC_PAD_HYS_SHIFT) + +#define IOMUXC_PAD_FSEL_SHIFT (6) +#define IOMUXC_PAD_FSEL_MASK (0x01u << IOMUXC_PAD_FSEL_SHIFT) +# define IOMUXC_PAD_FSEL_SLOW (0u << IOMUXC_PAD_FSEL_SHIFT) +# define IOMUXC_PAD_FSEL_FAST (1u << IOMUXC_PAD_FSEL_SHIFT) + +#define IOMUXC_PAD_DDR_SHIFT (7) +#define IOMUXC_PAD_DDR_MASK (0x01u << IOMUXC_PAD_DDR_SHIFT) +# define IOMUXC_PAD_DDR_OFF (0u << IOMUXC_PAD_DDR_SHIFT) +# define IOMUXC_PAD_DDR_ON (1u << IOMUXC_PAD_DDR_SHIFT) + +/**************************************************************************** + * IMXRT_PADCFG packed encoding + **************************************************************************** + * + * The (mux/pad/daisy) register addresses for every RT1180 pin/alt combo can + * be derived from a single uint32_t using pure arithmetic, without any run- + * time look-up tables. The two IOMUXC instances on RT1180 (main IOMUXC at + * 0x42a1_0000 and AON IOMUXC at 0x443c_0000) each expose: + * + * MUX_CTL[i] = base + ctl_first + i * 4 (contiguous, verified) + * PAD_CTL[i] = MUX_CTL[i] + pad_delta (constant offset per bank) + * DAISY[j] = base + dsy_first + j * 4 (base offset differs; j + * may be sparse but is + * still expressible as an + * index into the daisy + * region) + * + * Constants per bank (from IMXRT1180RM Ch. 17): + * + * +---------------+---------+-----------+-----------+-----------+ + * | bank | ctl_bit | ctl_first | pad_delta | dsy_first | + * +---------------+---------+-----------+-----------+-----------+ + * | main IOMUXC | 0 | 0x010 | 0x248 | 0x4A0 | + * | AON IOMUXC | 1 | 0x000 | 0x074 | 0x0E8 | + * +---------------+---------+-----------+-----------+-----------+ + * + * PADCFG bit layout (LSB..MSB): + * + * bits 0- 2 dsy_val (3 b) value written to DAISY register + * bits 3- 8 reserved (6 b) must be zero + * bits 9-17 dsy_idx (9 b) DAISY[j]; IMXRT_PADCFG_NO_DSYIDX = none + * bits 18-21 mux_mode (4 b) ALT 0..12 + * bits 22-29 pad_idx (8 b) MUX_CTL[i] where i = pad_idx + * bit 30 dsy_bank (1 b) 0 = main IOMUXC, 1 = AON IOMUXC + * bit 31 pad_bank (1 b) 0 = main IOMUXC, 1 = AON IOMUXC + * + * Together with a two-entry bank descriptor (see imxrt_iomuxc.c) this + * encoding suffices to compute all three register addresses at run time + * with only shifts, masks, and a single indexed load of the descriptor + * struct. There is no per-pin ROM table. + */ + +#define IMXRT_PADCFG_PADBANK_SHIFT (31) +#define IMXRT_PADCFG_PADBANK_MASK (0x1u << IMXRT_PADCFG_PADBANK_SHIFT) + +#define IMXRT_PADCFG_DSYBANK_SHIFT (30) +#define IMXRT_PADCFG_DSYBANK_MASK (0x1u << IMXRT_PADCFG_DSYBANK_SHIFT) + +#define IMXRT_PADCFG_PADIDX_SHIFT (22) +#define IMXRT_PADCFG_PADIDX_MASK (0xffu << IMXRT_PADCFG_PADIDX_SHIFT) + +#define IMXRT_PADCFG_MUX_SHIFT (18) +#define IMXRT_PADCFG_MUX_MASK (0xfu << IMXRT_PADCFG_MUX_SHIFT) + +#define IMXRT_PADCFG_DSYIDX_SHIFT (9) +#define IMXRT_PADCFG_DSYIDX_MASK (0x1ffu << IMXRT_PADCFG_DSYIDX_SHIFT) + +/* Sentinel dsy_idx meaning "this pin/alt has no input daisy". */ + +#define IMXRT_PADCFG_NO_DSYIDX (0x1ffu) + +#define IMXRT_PADCFG_DSY_SHIFT (0) +#define IMXRT_PADCFG_DSY_MASK (0x7u << IMXRT_PADCFG_DSY_SHIFT) + +/* Compile-time packer used by the auto-generated imxrt118x_pinmux.h. */ + +#define IMXRT_PADCFG(_padbank, _padidx, _mux, _dsybank, _dsyidx, _dsy) \ + ((((uint32_t)(_padbank) & 0x1u) << IMXRT_PADCFG_PADBANK_SHIFT) | \ + (((uint32_t)(_dsybank) & 0x1u) << IMXRT_PADCFG_DSYBANK_SHIFT) | \ + (((uint32_t)(_padidx) & 0xffu) << IMXRT_PADCFG_PADIDX_SHIFT) | \ + (((uint32_t)(_mux) & 0xfu) << IMXRT_PADCFG_MUX_SHIFT) | \ + (((uint32_t)(_dsyidx) & 0x1ffu) << IMXRT_PADCFG_DSYIDX_SHIFT) | \ + (((uint32_t)(_dsy) & 0x7u) << IMXRT_PADCFG_DSY_SHIFT)) + +/* Field extraction helpers (used by the runtime driver). */ + +#define IMXRT_PADCFG_PADBANK(_v) \ + (((_v) & IMXRT_PADCFG_PADBANK_MASK) >> IMXRT_PADCFG_PADBANK_SHIFT) +#define IMXRT_PADCFG_DSYBANK(_v) \ + (((_v) & IMXRT_PADCFG_DSYBANK_MASK) >> IMXRT_PADCFG_DSYBANK_SHIFT) +#define IMXRT_PADCFG_PADIDX(_v) \ + (((_v) & IMXRT_PADCFG_PADIDX_MASK) >> IMXRT_PADCFG_PADIDX_SHIFT) +#define IMXRT_PADCFG_MUX(_v) \ + (((_v) & IMXRT_PADCFG_MUX_MASK) >> IMXRT_PADCFG_MUX_SHIFT) +#define IMXRT_PADCFG_DSYIDX(_v) \ + (((_v) & IMXRT_PADCFG_DSYIDX_MASK) >> IMXRT_PADCFG_DSYIDX_SHIFT) +#define IMXRT_PADCFG_DSY(_v) \ + (((_v) & IMXRT_PADCFG_DSY_MASK) >> IMXRT_PADCFG_DSY_SHIFT) + +/**************************************************************************** + * Bank descriptor type + ****************************************************************************/ + +#define IMXRT_PADCFG_NBANKS (2) +#define IMXRT_PADCFG_BANK_MAIN (0) +#define IMXRT_PADCFG_BANK_AON (1) + +#ifndef __ASSEMBLY__ + +struct imxrt_iomux_bank_s +{ + uint32_t base; /* IOMUXC instance base address */ + uint16_t ctl_first; /* Offset of MUX_CTL[0] within the bank */ + uint16_t pad_delta; /* pad_reg = mux_reg + pad_delta */ + uint16_t dsy_first; /* Offset of DAISY[0] within the bank */ +}; + +#endif /* __ASSEMBLY__ */ + +#endif /* __ARCH_ARM_SRC_IMXRT_HARDWARE_RT118X_IMXRT118X_IOMUXC_H */ diff --git a/arch/arm/src/imxrt/hardware/rt118x/imxrt118x_memorymap.h b/arch/arm/src/imxrt/hardware/rt118x/imxrt118x_memorymap.h new file mode 100644 index 0000000000000..d5232d9c583ab --- /dev/null +++ b/arch/arm/src/imxrt/hardware/rt118x/imxrt118x_memorymap.h @@ -0,0 +1,290 @@ +/**************************************************************************** + * arch/arm/src/imxrt/hardware/rt118x/imxrt118x_memorymap.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_IMXRT_HARDWARE_RT118X_IMXRT118X_MEMORYMAP_H +#define __ARCH_ARM_SRC_IMXRT_HARDWARE_RT118X_IMXRT118X_MEMORYMAP_H + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* i.MX RT118x memory map (IMXRT1180RM Ch. 3). Peripheral bases are non- + * secure aliases; the corresponding secure alias is at NS + 0x1000_0000 + * (e.g. TRDC1 non-secure 0x4427_0000, secure 0x5427_0000). + * + * The organisation follows the reference-manual "system memory map" table: + * memory regions first, then peripherals grouped by mix domain (AONMIX, + * WAKEUPMIX, MEGAMIX-in-WAKEUPMIX, NETCMIX) in ascending address order. + */ + +/* System Memory Map ********************************************************/ + +#define IMXRT_M7_SYSTEM_BASE (0x00000000ul) /* M7 lower system map 2 GB */ +#define IMXRT_M7_SYSTEM_SIZE (2ul * 1024 * 1024 * 1024) +#define IMXRT_ITCM_BASE (0x00000000ul) /* M7 ITCM 256 KB */ +#define IMXRT_M7_ROM_BASE (0x00100000ul) /* M7 ROM 256 KB */ +#define IMXRT_M7_ROM_SIZE (256 * 1024) +#define IMXRT_FLEXSPI2_XIP_BASE (0x04000000ul) /* FlexSPI2 XIP 64 MB */ +#define IMXRT_DTCM_BASE (0x20000000ul) /* M7 DTCM 256 KB */ +#define IMXRT_OCRAM1_BASE (0x20480000ul) /* OCRAM1 512 KB */ +#define IMXRT_OCRAM2_BASE (0x20500000ul) /* OCRAM2 256 KB */ +#define IMXRT_FLEXSPI1_XIP_BASE (0x28000000ul) /* FlexSPI1 XIP 128 MB */ + +/* System-view aliases (accessible from either core via the AXI backbone) */ + +#define IMXRT_M7_ITCM_ALIAS_BASE (0x303c0000ul) /* M7 ITCM (M33 view) 256 KB */ +#define IMXRT_M7_DTCM_ALIAS_BASE (0x30400000ul) /* M7 DTCM (M33 view) 256 KB */ + +/* The first 16 KB of OCRAM1 is reserved by the boot ROM */ + +#define IMXRT_OCRAM_BASE (IMXRT_OCRAM1_BASE + 0x4000) +#define IMXRT_OCRAM_SIZE (512 * 1024 - 0x4000) + +/* WAKEUPMIX Peripheral Domain (0x4200_0000 - 0x42FF_FFFF) ******************/ + +#define IMXRT_DMA4_BASE (0x42000000ul) /* eDMA4 (channels + TCDs) */ + +#define IMXRT_BLK_CTRL_WAKEUPMIX_BASE (0x42420000ul) /* Wakeup block control */ +#define IMXRT_MU2_MUB_BASE (0x42440000ul) /* Message Unit 2 side B */ +#define IMXRT_SEMA2_BASE (0x42450000ul) /* Semaphore 2 */ +#define IMXRT_TRDC2_BASE (0x42460000ul) /* TRDC2 (Wakeup/Mega) */ + +#define IMXRT_TSTMR2_BASE (0x42480000ul) /* Time Stamp Timer 2 */ +#define IMXRT_RTWDOG3_BASE (0x42490000ul) /* WDog 3 */ +#define IMXRT_RTWDOG4_BASE (0x424a0000ul) /* WDog 4 */ +#define IMXRT_RTWDOG5_BASE (0x424b0000ul) /* WDog 5 */ +#define IMXRT_LPIT2_BASE (0x424c0000ul) /* Periodic Interrupt Timer 2 */ +#define IMXRT_LPTMR2_BASE (0x424d0000ul) /* Low Power Timer 2 */ +#define IMXRT_TPM3_BASE (0x424e0000ul) /* Timer PWM Module 3 */ +#define IMXRT_TPM4_BASE (0x424f0000ul) /* Timer PWM Module 4 */ +#define IMXRT_TPM5_BASE (0x42500000ul) /* Timer PWM Module 5 */ +#define IMXRT_TPM6_BASE (0x42510000ul) /* Timer PWM Module 6 */ +#define IMXRT_I3C2_BASE (0x42520000ul) /* I3C 2 */ +#define IMXRT_LPI2C3_BASE (0x42530000ul) +#define IMXRT_LPI2C4_BASE (0x42540000ul) +#define IMXRT_LPSPI3_BASE (0x42550000ul) +#define IMXRT_LPSPI4_BASE (0x42560000ul) +#define IMXRT_LPUART3_BASE (0x42570000ul) +#define IMXRT_LPUART4_BASE (0x42580000ul) +#define IMXRT_LPUART5_BASE (0x42590000ul) +#define IMXRT_LPUART6_BASE (0x425a0000ul) +#define IMXRT_CAN2_BASE (0x425b0000ul) /* FlexCAN 2 */ +#define IMXRT_FLEXIO1_BASE (0x425c0000ul) +#define IMXRT_FLEXIO2_BASE (0x425d0000ul) +#define IMXRT_FLEXSPIC_BASE (0x425e0000ul) /* FlexSPI1 controller */ +#define IMXRT_OTFAD1_BASE (0x425e0000ul) /* On-The-Fly AES Decrypt 1 */ + +#define IMXRT_ADC1_BASE (0x42600000ul) /* LPADC 1 */ +#define IMXRT_FLEXPWM1_BASE (0x42650000ul) /* FlexPWM 1 */ +#define IMXRT_FLEXPWM2_BASE (0x42660000ul) /* FlexPWM 2 */ +#define IMXRT_FLEXPWM3_BASE (0x42670000ul) /* FlexPWM 3 */ +#define IMXRT_FLEXPWM4_BASE (0x42680000ul) /* FlexPWM 4 */ +#define IMXRT_TMR1_BASE (0x42690000ul) /* Quad Timer 1 */ +#define IMXRT_TMR2_BASE (0x426a0000ul) +#define IMXRT_TMR3_BASE (0x426b0000ul) +#define IMXRT_TMR4_BASE (0x426c0000ul) +#define IMXRT_TMR5_BASE (0x426d0000ul) +#define IMXRT_TMR6_BASE (0x426e0000ul) +#define IMXRT_TMR7_BASE (0x426f0000ul) +#define IMXRT_TMR8_BASE (0x42700000ul) +#define IMXRT_ENC1_BASE (0x42710000ul) /* Enhanced Quad Decoder 1 (eQDC) */ +#define IMXRT_ENC2_BASE (0x42720000ul) +#define IMXRT_ENC3_BASE (0x42730000ul) +#define IMXRT_ENC4_BASE (0x42740000ul) +#define IMXRT_XBAR1_BASE (0x42750000ul) /* Inter-Peripheral Crossbar 1 */ +#define IMXRT_XBAR2_BASE (0x42760000ul) +#define IMXRT_XBAR3_BASE (0x42770000ul) +#define IMXRT_AOI1_BASE (0x42780000ul) /* AND/OR Invert 1 */ +#define IMXRT_AOI2_BASE (0x42790000ul) +#define IMXRT_EWM_BASE (0x427b0000ul) /* External Watchdog Monitor */ +#define IMXRT_AOI3_BASE (0x427e0000ul) +#define IMXRT_AOI4_BASE (0x427f0000ul) + +#define IMXRT_TRDC3_BASE (0x42810000ul) /* TRDC3 (NIX/Media) */ +#define IMXRT_USDHC1_BASE (0x42850000ul) +#define IMXRT_USDHC2_BASE (0x42860000ul) + +#define IMXRT_MSGINTR1_BASE (0x428a0000ul) /* Message-signalled INTR 1 */ +#define IMXRT_MSGINTR2_BASE (0x428b0000ul) +#define IMXRT_MSGINTR3_BASE (0x428c0000ul) +#define IMXRT_MSGINTR4_BASE (0x428d0000ul) +#define IMXRT_MSGINTR5_BASE (0x428e0000ul) +#define IMXRT_MSGINTR6_BASE (0x428f0000ul) + +#define IMXRT_FLEXSPI_SLV_BASE (0x42900000ul) /* FlexSPI slave */ +#define IMXRT_SEMC_BASE (0x42910000ul) /* Smart External Mem Ctlr */ +#define IMXRT_SEMC0_BASE (0x80000000ul) /* SEMC external memory window */ +#define IMXRT_SEMC0_SIZE (512 * 1024 * 1024) +#define IMXRT_MECC1_BASE (0x42920000ul) /* Memory ECC 1 */ +#define IMXRT_MECC2_BASE (0x42930000ul) +#define IMXRT_ASRC_BASE (0x429a0000ul) /* Async Sample Rate Conv */ + +#define IMXRT_KPP_BASE (0x42a00000ul) /* Keypad Port */ +#define IMXRT_IOMUXC_WKUP_BASE (0x42a10000ul) /* IOMUX (wakeup pads) */ +#define IMXRT_ECAT_BASE (0x42a80000ul) /* EtherCAT slave controller */ + +#define IMXRT_SPDIF_BASE (0x42ba0000ul) /* SPDIF Tx/Rx */ +#define IMXRT_SAI2_BASE (0x42bb0000ul) /* Sync Audio Interface 2 */ +#define IMXRT_SAI3_BASE (0x42bc0000ul) +#define IMXRT_SAI4_BASE (0x42bd0000ul) +#define IMXRT_PDM_BASE (0x42be0000ul) /* Pulse Density Modulation */ +#define IMXRT_SINC1_BASE (0x42bf0000ul) /* Sinc Filter 1 */ +#define IMXRT_SINC2_BASE (0x42c00000ul) +#define IMXRT_SINC3_BASE (0x42c10000ul) + +/* IMXRT_USB_BASE is the generic name used by the shared USB device driver + * (arch/arm/src/imxrt/imxrt_usbdev.c) and hardware/imxrt_usbotg.h. On + * RT118x this is USB OTG1 (the only USB device-capable controller). + */ + +#define IMXRT_USB_BASE (0x42c80000ul) /* USB OTG1 controller */ +#define IMXRT_USBNC_OTG1_BASE (0x42c80200ul) /* USB OTG1 non-core */ +#define IMXRT_USB_OTG2_BASE (0x42c90000ul) +#define IMXRT_USBNC_OTG2_BASE (0x42c90200ul) + +#define IMXRT_USBPHY1_BASE (0x42ca0000ul) /* USB PHY 1 */ +#define IMXRT_USBHSDCD1_BASE (0x42ca0800ul) /* USB HS charger detect 1 */ +#define IMXRT_USBPHY2_BASE (0x42cb0000ul) +#define IMXRT_USBHSDCD2_BASE (0x42cb0800ul) + +#define IMXRT_LPIT3_BASE (0x42cc0000ul) +#define IMXRT_LPTMR3_BASE (0x42cd0000ul) + +#define IMXRT_LPI2C5_BASE (0x42d30000ul) +#define IMXRT_LPI2C6_BASE (0x42d40000ul) +#define IMXRT_LPSPI5_BASE (0x42d50000ul) +#define IMXRT_LPSPI6_BASE (0x42d60000ul) +#define IMXRT_LPUART9_BASE (0x42d70000ul) +#define IMXRT_LPUART10_BASE (0x42d80000ul) +#define IMXRT_LPUART11_BASE (0x42d90000ul) +#define IMXRT_LPUART8_BASE (0x42da0000ul) /* Note: LPUART8 base > 9..11 */ +#define IMXRT_CMP1_BASE (0x42dc0000ul) /* Analog Comparator 1 */ +#define IMXRT_CMP2_BASE (0x42dd0000ul) +#define IMXRT_CMP3_BASE (0x42de0000ul) + +/* WAKEUPMIX GPIO ports (RGPIO2..RGPIO6) */ + +#define IMXRT_GPIO2_BASE (0x43810000ul) +#define IMXRT_GPIO3_BASE (0x43820000ul) +#define IMXRT_GPIO4_BASE (0x43830000ul) +#define IMXRT_GPIO5_BASE (0x43840000ul) +#define IMXRT_GPIO6_BASE (0x43850000ul) + +/* AONMIX Peripheral Domain (0x4420_0000 - 0x447F_FFFF) *********************/ + +#define IMXRT_DMA3_BASE (0x44000000ul) /* eDMA3 (AON) */ + +#define IMXRT_BLK_CTRL_NS_AON_BASE (0x44210000ul) /* AON non-secure block control */ + +#define IMXRT_LPUART1_BASE (0x44380000ul) +#define IMXRT_LPUART2_BASE (0x44390000ul) + +#define IMXRT_IOMUXC_AON_BASE (0x443c0000ul) /* IOMUX (AON pads) */ + +#define IMXRT_CCM_BASE (0x44450000ul) /* Clock Controller Module */ +#define IMXRT_SRC_BASE (0x44460000ul) /* System Reset Controller */ + +/* SRC power-slice sub-blocks (per mix, non-secure aliases). IMXRT1180RM + * Ch. 27. Each slice is 0x400 bytes. + */ + +#define IMXRT_AON_MIX_SLICE_BASE (0x44460800ul) +#define IMXRT_WAKEUP_MIX_SLICE_BASE (0x44460c00ul) +#define IMXRT_MEGA_MIX_SLICE_BASE (0x44461000ul) +#define IMXRT_NETC_MIX_SLICE_BASE (0x44461400ul) +#define IMXRT_CM33PLATFORM_MIX_SLICE (0x44461800ul) +#define IMXRT_CM7PLATFORM_MIX_SLICE (0x44461c00ul) + +#define IMXRT_GPC_CPU_CTRL_BASE (0x44470000ul) /* GPC CPU control */ +#define IMXRT_GPC_SM_BASE (0x44471000ul) /* GPC state machine */ + +/* AONMIX ANADIG (analog / PLL / OSC). See imxrt118x_anadig.h for the + * per-register offsets and bit fields. + */ + +#define IMXRT_ANADIG_PLL_BASE (0x44480000ul) /* Analog PLL registers */ +#define IMXRT_ANADIG_OSC_BASE (0x44481000ul) /* Analog OSC registers */ +#define IMXRT_ANADIG_TEMPSENSOR_BASE (0x44482000ul) +#define IMXRT_ANADIG_MISC_BASE (0x44483000ul) +#define IMXRT_ANADIG_LDO_BASE (0x44484000ul) /* Analog PMU LDOs incl. PHY_LDO */ +#define IMXRT_DCDC_BASE (0x44520000ul) /* On-chip DCDC */ + +/* AONMIX BLK_CTRL (block-control fabric) - secure alias. See + * IMXRT_BLK_CTRL_NS_AON_BASE above for the non-secure alias. + */ + +#define IMXRT_BLK_CTRL_S_AONMIX_BASE (0x444f0000ul) /* AON secure block control */ + +/* AONMIX common serial + timers */ + +#define IMXRT_TSTMR1_BASE (0x442c0000ul) /* Time Stamp Timer 1 */ +#define IMXRT_RTWDOG1_BASE (0x442d0000ul) /* WDog 1 */ +#define IMXRT_RTWDOG2_BASE (0x442e0000ul) +#define IMXRT_LPIT1_BASE (0x442f0000ul) +#define IMXRT_LPTMR1_BASE (0x44300000ul) +#define IMXRT_TPM1_BASE (0x44310000ul) +#define IMXRT_TPM2_BASE (0x44320000ul) +#define IMXRT_I3C1_BASE (0x44330000ul) +#define IMXRT_LPI2C1_BASE (0x44340000ul) +#define IMXRT_LPI2C2_BASE (0x44350000ul) +#define IMXRT_LPSPI1_BASE (0x44360000ul) +#define IMXRT_LPSPI2_BASE (0x44370000ul) +#define IMXRT_CAN1_BASE (0x443a0000ul) +#define IMXRT_LPUART7_BASE (0x44570000ul) +#define IMXRT_LPUART12_BASE (0x44580000ul) +#define IMXRT_CAN3_BASE (0x445b0000ul) +#define IMXRT_FLEXSPI2C_BASE (0x445e0000ul) /* FlexSPI2 controller */ +#define IMXRT_OTFAD2_BASE (0x445e0000ul) /* On-The-Fly AES Decrypt 2 */ + +/* AONMIX secure services (S3MU, ELE, OTP, RGPIO1) */ + +#define IMXRT_GPIO1_BASE (0x47400000ul) /* RGPIO1 (AON) */ +#define IMXRT_MU_APPS_S3MUA_BASE (0x47520000ul) /* Applications MU to ELE (NS alias) */ +#define IMXRT_S3MUA_BASE (0x57540000ul) /* System 3 MU (ELE), secure alias */ +#define IMXRT_S3MUA_NS_BASE (0x47540000ul) /* System 3 MU (ELE), non-secure alias */ + +/* TRDC1 (AON) instance */ + +#define IMXRT_TRDC1_BASE (0x44270000ul) /* TRDC1 (AON) */ + +/* NETCMIX Domain (0x6000_0000 - 0x60FF_FFFF) *******************************/ + +#define IMXRT_ENETC0_SI0_BASE (0x60b00000ul) /* ENETC0 station interface 0 */ +#define IMXRT_ENETC0_BASE (0x60b10000ul) /* ENETC0 common regs */ +#define IMXRT_ENETC0_PORT_BASE (0x60b14000ul) /* ENETC0 port regs */ +#define IMXRT_ENETC0_ETH_MAC_BASE (0x60b15000ul) /* ENETC0 MAC regs */ +#define IMXRT_ENETC0_GLOBAL_BASE (0x60b20000ul) +#define IMXRT_ENETC1_SI0_BASE (0x60b40000ul) +#define IMXRT_ENETC1_BASE (0x60b50000ul) +#define IMXRT_ENETC1_PORT_BASE (0x60b54000ul) +#define IMXRT_ENETC1_PSEUDO_MAC_BASE (0x60b55000ul) +#define IMXRT_ENETC1_GLOBAL_BASE (0x60b60000ul) +#define IMXRT_ENETC1_SI1_BASE (0x60c10000ul) +#define IMXRT_EMDIO_BASE (0x60ba0000ul) /* External MDIO */ +#define IMXRT_TMR0_BASE (0x60b80000ul) /* NETC 1588 Timer */ +#define IMXRT_SW0_GLOBAL_BASE (0x60a80000ul) /* Switch 0 global */ + +/* CM7 Private Peripheral Bus (0xE000_0000 - 0xE00F_FFFF) *******************/ + +#define IMXRT_M7_MCM_BASE (0xe0080000ul) /* CM7 memory control module */ + +#endif /* __ARCH_ARM_SRC_IMXRT_HARDWARE_RT118X_IMXRT118X_MEMORYMAP_H */ diff --git a/arch/arm/src/imxrt/hardware/rt118x/imxrt118x_ocotp.h b/arch/arm/src/imxrt/hardware/rt118x/imxrt118x_ocotp.h new file mode 100644 index 0000000000000..8ddd178799c72 --- /dev/null +++ b/arch/arm/src/imxrt/hardware/rt118x/imxrt118x_ocotp.h @@ -0,0 +1,47 @@ +/**************************************************************************** + * arch/arm/src/imxrt/hardware/rt118x/imxrt118x_ocotp.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_IMXRT_HARDWARE_RT118X_IMXRT118X_OCOTP_H +#define __ARCH_ARM_SRC_IMXRT_HARDWARE_RT118X_IMXRT118X_OCOTP_H + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* On i.MX RT chips fronted by the EdgeLock Enclave (RT1180 and later), + * the OCOTP fuse controller is owned by the ELE (IMXRT1180RM Ch. 7.1.2). + * The SoC exposes a read-only window of the non-security-related OCOTP + * shadow registers at: + * + * IMXRT_OCOTP_SHADOW_BASE + 0x4 * + * + * (IMXRT1180RM Ch. 26.1 "Fusemap"). + * + * Write and reload paths must go through the ELE messaging protocol. + * That is not implemented in this port; imxrt_ocotp_write() and + * imxrt_ocotp_reload() therefore return -ENOSYS on chips with + * CONFIG_IMXRT_ELE=y. + */ + +#define IMXRT_OCOTP_SHADOW_BASE (0x47518000ul) + +#endif /* __ARCH_ARM_SRC_IMXRT_HARDWARE_RT118X_IMXRT118X_OCOTP_H */ diff --git a/arch/arm/src/imxrt/hardware/rt118x/imxrt118x_pinmux.h b/arch/arm/src/imxrt/hardware/rt118x/imxrt118x_pinmux.h new file mode 100644 index 0000000000000..ff9e826f0523b --- /dev/null +++ b/arch/arm/src/imxrt/hardware/rt118x/imxrt118x_pinmux.h @@ -0,0 +1,1842 @@ +/**************************************************************************** + * arch/arm/src/imxrt/hardware/rt118x/imxrt118x_pinmux.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_IMXRT_HARDWARE_RT118X_IMXRT118X_PINMUX_H +#define __ARCH_ARM_SRC_IMXRT_HARDWARE_RT118X_IMXRT118X_PINMUX_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include "hardware/rt118x/imxrt118x_iomuxc.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Each IOMUXC_PAD__ constant is a packed uint32_t suitable for + * use as the padcfg argument of IOMUX_PIN(padcfg, pad_ctl, sion) or + * IOMUX_GPIO(padcfg, pad_ctl, gpio). The layout and packing is defined + * in imxrt118x_iomuxc.h. + */ + +#define IOMUXC_PAD_GPIO_EMC_B1_00_SEMC_DATA00 IMXRT_PADCFG(0, 0, 0x0, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_EMC_B1_00_XBAR1_XBAR_INOUT04 IMXRT_PADCFG(0, 0, 0x1, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_EMC_B1_00_SINC3_MOD_CLK0 IMXRT_PADCFG(0, 0, 0x2, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_EMC_B1_00_LPUART3_CTS_B IMXRT_PADCFG(0, 0, 0x3, 0, 119, 0x0) +#define IOMUXC_PAD_GPIO_EMC_B1_00_NETC_PINMUX_ETH3_TXD03 IMXRT_PADCFG(0, 0, 0x4, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_EMC_B1_00_GPIO2_IO00 IMXRT_PADCFG(0, 0, 0x5, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_EMC_B1_00_KPP_ROW03 IMXRT_PADCFG(0, 0, 0x6, 0, 77, 0x0) +#define IOMUXC_PAD_GPIO_EMC_B1_00_FLEXIO1_FLEXIO00 IMXRT_PADCFG(0, 0, 0x8, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_EMC_B1_00_NETC_PINMUX_ETH4_TXD03 IMXRT_PADCFG(0, 0, 0x9, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_EMC_B1_00_ECAT_TX_DATA3_0 IMXRT_PADCFG(0, 0, 0xa, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_EMC_B1_00_AHB_SRAMC_DATA00 IMXRT_PADCFG(0, 0, 0xc, 0, IMXRT_PADCFG_NO_DSYIDX, 0) + +#define IOMUXC_PAD_GPIO_EMC_B1_01_SEMC_DATA01 IMXRT_PADCFG(0, 1, 0x0, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_EMC_B1_01_XBAR1_XBAR_INOUT05 IMXRT_PADCFG(0, 1, 0x1, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_EMC_B1_01_SINC3_MOD_CLK1 IMXRT_PADCFG(0, 1, 0x2, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_EMC_B1_01_LPUART3_RTS_B IMXRT_PADCFG(0, 1, 0x3, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_EMC_B1_01_NETC_PINMUX_ETH3_TXD02 IMXRT_PADCFG(0, 1, 0x4, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_EMC_B1_01_GPIO2_IO01 IMXRT_PADCFG(0, 1, 0x5, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_EMC_B1_01_KPP_COL03 IMXRT_PADCFG(0, 1, 0x6, 0, 69, 0x0) +#define IOMUXC_PAD_GPIO_EMC_B1_01_FLEXIO1_FLEXIO01 IMXRT_PADCFG(0, 1, 0x8, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_EMC_B1_01_NETC_PINMUX_ETH4_TXD02 IMXRT_PADCFG(0, 1, 0x9, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_EMC_B1_01_ECAT_TX_DATA2_0 IMXRT_PADCFG(0, 1, 0xa, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_EMC_B1_01_AHB_SRAMC_DATA01 IMXRT_PADCFG(0, 1, 0xc, 0, IMXRT_PADCFG_NO_DSYIDX, 0) + +#define IOMUXC_PAD_GPIO_EMC_B1_02_SEMC_DATA02 IMXRT_PADCFG(0, 2, 0x0, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_EMC_B1_02_XBAR1_XBAR_INOUT06 IMXRT_PADCFG(0, 2, 0x1, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_EMC_B1_02_SINC3_MOD_CLK2 IMXRT_PADCFG(0, 2, 0x2, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_EMC_B1_02_LPUART3_RX IMXRT_PADCFG(0, 2, 0x3, 0, 120, 0x0) +#define IOMUXC_PAD_GPIO_EMC_B1_02_NETC_PINMUX_ETH3_RX_CLK IMXRT_PADCFG(0, 2, 0x4, 0, 222, 0x0) +#define IOMUXC_PAD_GPIO_EMC_B1_02_GPIO2_IO02 IMXRT_PADCFG(0, 2, 0x5, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_EMC_B1_02_KPP_ROW02 IMXRT_PADCFG(0, 2, 0x6, 0, 76, 0x0) +#define IOMUXC_PAD_GPIO_EMC_B1_02_FLEXIO1_FLEXIO02 IMXRT_PADCFG(0, 2, 0x8, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_EMC_B1_02_NETC_PINMUX_ETH4_RX_CLK IMXRT_PADCFG(0, 2, 0x9, 0, 230, 0x0) +#define IOMUXC_PAD_GPIO_EMC_B1_02_ECAT_RX_CLK_0 IMXRT_PADCFG(0, 2, 0xa, 0, 3, 0x0) +#define IOMUXC_PAD_GPIO_EMC_B1_02_AHB_SRAMC_DATA02 IMXRT_PADCFG(0, 2, 0xc, 0, IMXRT_PADCFG_NO_DSYIDX, 0) + +#define IOMUXC_PAD_GPIO_EMC_B1_03_SEMC_DATA03 IMXRT_PADCFG(0, 3, 0x0, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_EMC_B1_03_XBAR1_XBAR_INOUT07 IMXRT_PADCFG(0, 3, 0x1, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_EMC_B1_03_SINC3_EMCLK00 IMXRT_PADCFG(0, 3, 0x2, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_EMC_B1_03_LPUART3_TX IMXRT_PADCFG(0, 3, 0x3, 0, 121, 0x0) +#define IOMUXC_PAD_GPIO_EMC_B1_03_NETC_PINMUX_ETH3_RXD03 IMXRT_PADCFG(0, 3, 0x4, 0, 228, 0x0) +#define IOMUXC_PAD_GPIO_EMC_B1_03_GPIO2_IO03 IMXRT_PADCFG(0, 3, 0x5, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_EMC_B1_03_KPP_COL02 IMXRT_PADCFG(0, 3, 0x6, 0, 68, 0x0) +#define IOMUXC_PAD_GPIO_EMC_B1_03_FLEXIO1_FLEXIO03 IMXRT_PADCFG(0, 3, 0x8, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_EMC_B1_03_NETC_PINMUX_ETH4_RXD03 IMXRT_PADCFG(0, 3, 0x9, 0, 236, 0x0) +#define IOMUXC_PAD_GPIO_EMC_B1_03_ECAT_RX_DATA3_0 IMXRT_PADCFG(0, 3, 0xa, 0, 11, 0x0) +#define IOMUXC_PAD_GPIO_EMC_B1_03_AHB_SRAMC_DATA03 IMXRT_PADCFG(0, 3, 0xc, 0, IMXRT_PADCFG_NO_DSYIDX, 0) + +#define IOMUXC_PAD_GPIO_EMC_B1_04_SEMC_DATA04 IMXRT_PADCFG(0, 4, 0x0, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_EMC_B1_04_XBAR1_XBAR_INOUT08 IMXRT_PADCFG(0, 4, 0x1, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_EMC_B1_04_SINC3_EMBIT00 IMXRT_PADCFG(0, 4, 0x2, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_EMC_B1_04_LPUART3_DSR_B IMXRT_PADCFG(0, 4, 0x3, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_EMC_B1_04_NETC_PINMUX_ETH3_RXD02 IMXRT_PADCFG(0, 4, 0x4, 0, 227, 0x0) +#define IOMUXC_PAD_GPIO_EMC_B1_04_GPIO2_IO04 IMXRT_PADCFG(0, 4, 0x5, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_EMC_B1_04_KPP_ROW01 IMXRT_PADCFG(0, 4, 0x6, 0, 75, 0x0) +#define IOMUXC_PAD_GPIO_EMC_B1_04_FLEXIO1_FLEXIO04 IMXRT_PADCFG(0, 4, 0x8, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_EMC_B1_04_NETC_PINMUX_ETH4_RXD02 IMXRT_PADCFG(0, 4, 0x9, 0, 235, 0x0) +#define IOMUXC_PAD_GPIO_EMC_B1_04_ECAT_RX_DATA2_0 IMXRT_PADCFG(0, 4, 0xa, 0, 9, 0x0) +#define IOMUXC_PAD_GPIO_EMC_B1_04_AHB_SRAMC_DATA04 IMXRT_PADCFG(0, 4, 0xc, 0, IMXRT_PADCFG_NO_DSYIDX, 0) + +#define IOMUXC_PAD_GPIO_EMC_B1_05_SEMC_DATA05 IMXRT_PADCFG(0, 5, 0x0, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_EMC_B1_05_XBAR1_XBAR_INOUT09 IMXRT_PADCFG(0, 5, 0x1, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_EMC_B1_05_SINC3_EMCLK01 IMXRT_PADCFG(0, 5, 0x2, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_EMC_B1_05_LPUART3_DCD_B IMXRT_PADCFG(0, 5, 0x3, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_EMC_B1_05_NETC_PINMUX_ETH3_TXD00 IMXRT_PADCFG(0, 5, 0x4, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_EMC_B1_05_GPIO2_IO05 IMXRT_PADCFG(0, 5, 0x5, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_EMC_B1_05_KPP_ROW07 IMXRT_PADCFG(0, 5, 0x6, 0, 81, 0x0) +#define IOMUXC_PAD_GPIO_EMC_B1_05_FLEXIO1_FLEXIO05 IMXRT_PADCFG(0, 5, 0x8, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_EMC_B1_05_NETC_PINMUX_ETH4_TXD00 IMXRT_PADCFG(0, 5, 0x9, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_EMC_B1_05_ECAT_TX_DATA0_0 IMXRT_PADCFG(0, 5, 0xa, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_EMC_B1_05_AHB_SRAMC_DATA05 IMXRT_PADCFG(0, 5, 0xc, 0, IMXRT_PADCFG_NO_DSYIDX, 0) + +#define IOMUXC_PAD_GPIO_EMC_B1_06_SEMC_DATA06 IMXRT_PADCFG(0, 6, 0x0, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_EMC_B1_06_FLEXPWM4_PWMB03 IMXRT_PADCFG(0, 6, 0x1, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_EMC_B1_06_SINC3_EMBIT01 IMXRT_PADCFG(0, 6, 0x2, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_EMC_B1_06_LPUART3_RI_B IMXRT_PADCFG(0, 6, 0x3, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_EMC_B1_06_NETC_PINMUX_ETH3_TXD01 IMXRT_PADCFG(0, 6, 0x4, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_EMC_B1_06_GPIO2_IO06 IMXRT_PADCFG(0, 6, 0x5, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_EMC_B1_06_KPP_COL07 IMXRT_PADCFG(0, 6, 0x6, 0, 73, 0x0) +#define IOMUXC_PAD_GPIO_EMC_B1_06_FLEXIO1_FLEXIO06 IMXRT_PADCFG(0, 6, 0x8, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_EMC_B1_06_NETC_PINMUX_ETH4_TXD01 IMXRT_PADCFG(0, 6, 0x9, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_EMC_B1_06_ECAT_TX_DATA1_0 IMXRT_PADCFG(0, 6, 0xa, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_EMC_B1_06_AHB_SRAMC_DATA06 IMXRT_PADCFG(0, 6, 0xc, 0, IMXRT_PADCFG_NO_DSYIDX, 0) + +#define IOMUXC_PAD_GPIO_EMC_B1_07_SEMC_DATA07 IMXRT_PADCFG(0, 7, 0x0, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_EMC_B1_07_FLEXPWM4_PWMA03 IMXRT_PADCFG(0, 7, 0x1, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_EMC_B1_07_SINC3_EMCLK02 IMXRT_PADCFG(0, 7, 0x2, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_EMC_B1_07_LPUART3_DTR_B IMXRT_PADCFG(0, 7, 0x3, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_EMC_B1_07_NETC_PINMUX_ETH3_TX_EN IMXRT_PADCFG(0, 7, 0x4, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_EMC_B1_07_GPIO2_IO07 IMXRT_PADCFG(0, 7, 0x5, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_EMC_B1_07_KPP_ROW06 IMXRT_PADCFG(0, 7, 0x6, 0, 80, 0x0) +#define IOMUXC_PAD_GPIO_EMC_B1_07_FLEXIO1_FLEXIO07 IMXRT_PADCFG(0, 7, 0x8, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_EMC_B1_07_NETC_PINMUX_ETH4_TX_EN IMXRT_PADCFG(0, 7, 0x9, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_EMC_B1_07_ECAT_TX_EN_0 IMXRT_PADCFG(0, 7, 0xa, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_EMC_B1_07_AHB_SRAMC_DATA07 IMXRT_PADCFG(0, 7, 0xc, 0, IMXRT_PADCFG_NO_DSYIDX, 0) + +#define IOMUXC_PAD_GPIO_EMC_B1_08_SEMC_DM00 IMXRT_PADCFG(0, 8, 0x0, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_EMC_B1_08_FLEXPWM2_PWMB03 IMXRT_PADCFG(0, 8, 0x1, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_EMC_B1_08_SINC3_EMBIT02 IMXRT_PADCFG(0, 8, 0x2, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_EMC_B1_08_LPUART4_DSR_B IMXRT_PADCFG(0, 8, 0x3, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_EMC_B1_08_NETC_PINMUX_ETH3_TX_CLK IMXRT_PADCFG(0, 8, 0x4, 0, 229, 0x0) +#define IOMUXC_PAD_GPIO_EMC_B1_08_GPIO2_IO08 IMXRT_PADCFG(0, 8, 0x5, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_EMC_B1_08_KPP_COL06 IMXRT_PADCFG(0, 8, 0x6, 0, 72, 0x0) +#define IOMUXC_PAD_GPIO_EMC_B1_08_FLEXIO1_FLEXIO08 IMXRT_PADCFG(0, 8, 0x8, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_EMC_B1_08_NETC_PINMUX_ETH4_TX_CLK IMXRT_PADCFG(0, 8, 0x9, 0, 237, 0x0) +#define IOMUXC_PAD_GPIO_EMC_B1_08_ECAT_TX_CLK_0 IMXRT_PADCFG(0, 8, 0xa, 0, 17, 0x0) +#define IOMUXC_PAD_GPIO_EMC_B1_08_AHB_SRAMC_LBB IMXRT_PADCFG(0, 8, 0xc, 0, IMXRT_PADCFG_NO_DSYIDX, 0) + +#define IOMUXC_PAD_GPIO_EMC_B1_09_SEMC_ADDR00 IMXRT_PADCFG(0, 9, 0x0, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_EMC_B1_09_FLEXPWM2_PWMA03 IMXRT_PADCFG(0, 9, 0x1, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_EMC_B1_09_SINC3_EMCLK03 IMXRT_PADCFG(0, 9, 0x2, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_EMC_B1_09_LPUART4_DCD_B IMXRT_PADCFG(0, 9, 0x3, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_EMC_B1_09_NETC_PINMUX_ETH3_RXD00 IMXRT_PADCFG(0, 9, 0x4, 0, 225, 0x0) +#define IOMUXC_PAD_GPIO_EMC_B1_09_GPIO2_IO09 IMXRT_PADCFG(0, 9, 0x5, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_EMC_B1_09_KPP_ROW05 IMXRT_PADCFG(0, 9, 0x6, 0, 79, 0x0) +#define IOMUXC_PAD_GPIO_EMC_B1_09_FLEXIO1_FLEXIO09 IMXRT_PADCFG(0, 9, 0x8, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_EMC_B1_09_NETC_PINMUX_ETH4_RXD00 IMXRT_PADCFG(0, 9, 0x9, 0, 233, 0x0) +#define IOMUXC_PAD_GPIO_EMC_B1_09_ECAT_RX_DATA0_0 IMXRT_PADCFG(0, 9, 0xa, 0, 5, 0x0) +#define IOMUXC_PAD_GPIO_EMC_B1_09_AHB_SRAMC_ADDR00 IMXRT_PADCFG(0, 9, 0xc, 0, IMXRT_PADCFG_NO_DSYIDX, 0) + +#define IOMUXC_PAD_GPIO_EMC_B1_10_SEMC_ADDR01 IMXRT_PADCFG(0, 10, 0x0, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_EMC_B1_10_FLEXPWM3_PWMB03 IMXRT_PADCFG(0, 10, 0x1, 0, 40, 0x0) +#define IOMUXC_PAD_GPIO_EMC_B1_10_SINC3_EMBIT03 IMXRT_PADCFG(0, 10, 0x2, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_EMC_B1_10_LPUART4_RI_B IMXRT_PADCFG(0, 10, 0x3, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_EMC_B1_10_NETC_PINMUX_ETH3_RXD01 IMXRT_PADCFG(0, 10, 0x4, 0, 226, 0x0) +#define IOMUXC_PAD_GPIO_EMC_B1_10_GPIO2_IO10 IMXRT_PADCFG(0, 10, 0x5, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_EMC_B1_10_KPP_COL05 IMXRT_PADCFG(0, 10, 0x6, 0, 71, 0x0) +#define IOMUXC_PAD_GPIO_EMC_B1_10_FLEXIO1_FLEXIO10 IMXRT_PADCFG(0, 10, 0x8, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_EMC_B1_10_NETC_PINMUX_ETH4_RXD01 IMXRT_PADCFG(0, 10, 0x9, 0, 234, 0x0) +#define IOMUXC_PAD_GPIO_EMC_B1_10_ECAT_RX_DATA1_0 IMXRT_PADCFG(0, 10, 0xa, 0, 7, 0x0) +#define IOMUXC_PAD_GPIO_EMC_B1_10_AHB_SRAMC_ADDR01 IMXRT_PADCFG(0, 10, 0xc, 0, IMXRT_PADCFG_NO_DSYIDX, 0) + +#define IOMUXC_PAD_GPIO_EMC_B1_11_SEMC_ADDR02 IMXRT_PADCFG(0, 11, 0x0, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_EMC_B1_11_FLEXPWM3_PWMA03 IMXRT_PADCFG(0, 11, 0x1, 0, 36, 0x0) +#define IOMUXC_PAD_GPIO_EMC_B1_11_SINC_FILTER_GLUE3_BREAK IMXRT_PADCFG(0, 11, 0x2, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_EMC_B1_11_LPUART4_DTR_B IMXRT_PADCFG(0, 11, 0x3, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_EMC_B1_11_NETC_PINMUX_ETH3_RX_DV IMXRT_PADCFG(0, 11, 0x4, 0, 223, 0x0) +#define IOMUXC_PAD_GPIO_EMC_B1_11_GPIO2_IO11 IMXRT_PADCFG(0, 11, 0x5, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_EMC_B1_11_KPP_ROW04 IMXRT_PADCFG(0, 11, 0x6, 0, 78, 0x0) +#define IOMUXC_PAD_GPIO_EMC_B1_11_FLEXIO1_FLEXIO11 IMXRT_PADCFG(0, 11, 0x8, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_EMC_B1_11_NETC_PINMUX_ETH4_RX_DV IMXRT_PADCFG(0, 11, 0x9, 0, 231, 0x0) +#define IOMUXC_PAD_GPIO_EMC_B1_11_ECAT_RX_DV_0 IMXRT_PADCFG(0, 11, 0xa, 0, 13, 0x0) +#define IOMUXC_PAD_GPIO_EMC_B1_11_AHB_SRAMC_ADDR02 IMXRT_PADCFG(0, 11, 0xc, 0, IMXRT_PADCFG_NO_DSYIDX, 0) + +#define IOMUXC_PAD_GPIO_EMC_B1_12_SEMC_ADDR03 IMXRT_PADCFG(0, 12, 0x0, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_EMC_B1_12_FLEXPWM4_PWMA00 IMXRT_PADCFG(0, 12, 0x1, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_EMC_B1_12_LPUART4_TX IMXRT_PADCFG(0, 12, 0x2, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_EMC_B1_12_NETC_PINMUX_ETH3_RX_ER IMXRT_PADCFG(0, 12, 0x4, 0, 224, 0x0) +#define IOMUXC_PAD_GPIO_EMC_B1_12_GPIO2_IO12 IMXRT_PADCFG(0, 12, 0x5, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_EMC_B1_12_KPP_COL04 IMXRT_PADCFG(0, 12, 0x6, 0, 70, 0x0) +#define IOMUXC_PAD_GPIO_EMC_B1_12_FLEXIO1_FLEXIO12 IMXRT_PADCFG(0, 12, 0x8, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_EMC_B1_12_NETC_PINMUX_ETH4_RX_ER IMXRT_PADCFG(0, 12, 0x9, 0, 232, 0x0) +#define IOMUXC_PAD_GPIO_EMC_B1_12_ECAT_PT0_RX_ER IMXRT_PADCFG(0, 12, 0xa, 0, 15, 0x0) +#define IOMUXC_PAD_GPIO_EMC_B1_12_AHB_SRAMC_ADDR03 IMXRT_PADCFG(0, 12, 0xc, 0, IMXRT_PADCFG_NO_DSYIDX, 0) + +#define IOMUXC_PAD_GPIO_EMC_B1_13_SEMC_ADDR04 IMXRT_PADCFG(0, 13, 0x0, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_EMC_B1_13_FLEXPWM4_PWMB00 IMXRT_PADCFG(0, 13, 0x1, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_EMC_B1_13_LPUART4_RX IMXRT_PADCFG(0, 13, 0x2, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_EMC_B1_13_NETC_PINMUX_ETH2_RX_DV IMXRT_PADCFG(0, 13, 0x3, 0, 215, 0x0) +#define IOMUXC_PAD_GPIO_EMC_B1_13_NETC_PINMUX_ETH3_TX_ER IMXRT_PADCFG(0, 13, 0x4, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_EMC_B1_13_GPIO2_IO13 IMXRT_PADCFG(0, 13, 0x5, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_EMC_B1_13_KPP_COL01 IMXRT_PADCFG(0, 13, 0x6, 0, 67, 0x0) +#define IOMUXC_PAD_GPIO_EMC_B1_13_FLEXIO1_FLEXIO13 IMXRT_PADCFG(0, 13, 0x8, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_EMC_B1_13_NETC_PINMUX_ETH4_TX_ER IMXRT_PADCFG(0, 13, 0x9, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_EMC_B1_13_QTIMER1_TIMER1 IMXRT_PADCFG(0, 13, 0xa, 0, 239, 0x0) +#define IOMUXC_PAD_GPIO_EMC_B1_13_AHB_SRAMC_ADDR04 IMXRT_PADCFG(0, 13, 0xc, 0, IMXRT_PADCFG_NO_DSYIDX, 0) + +#define IOMUXC_PAD_GPIO_EMC_B1_14_SEMC_ADDR05 IMXRT_PADCFG(0, 14, 0x0, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_EMC_B1_14_FLEXPWM4_PWMA01 IMXRT_PADCFG(0, 14, 0x1, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_EMC_B1_14_LPUART5_TX IMXRT_PADCFG(0, 14, 0x2, 0, 128, 0x0) +#define IOMUXC_PAD_GPIO_EMC_B1_14_NETC_PINMUX_ETH2_TX_EN IMXRT_PADCFG(0, 14, 0x3, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_EMC_B1_14_NETC_ETH3_CRS IMXRT_PADCFG(0, 14, 0x4, 0, 196, 0x0) +#define IOMUXC_PAD_GPIO_EMC_B1_14_GPIO2_IO14 IMXRT_PADCFG(0, 14, 0x5, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_EMC_B1_14_KPP_ROW00 IMXRT_PADCFG(0, 14, 0x6, 0, 74, 0x0) +#define IOMUXC_PAD_GPIO_EMC_B1_14_FLEXIO1_FLEXIO14 IMXRT_PADCFG(0, 14, 0x8, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_EMC_B1_14_NETC_ETH4_CRS IMXRT_PADCFG(0, 14, 0x9, 0, 200, 0x0) +#define IOMUXC_PAD_GPIO_EMC_B1_14_LPUART4_CTS_B IMXRT_PADCFG(0, 14, 0xa, 0, 122, 0x0) +#define IOMUXC_PAD_GPIO_EMC_B1_14_AHB_SRAMC_ADDR05 IMXRT_PADCFG(0, 14, 0xc, 0, IMXRT_PADCFG_NO_DSYIDX, 0) + +#define IOMUXC_PAD_GPIO_EMC_B1_15_SEMC_ADDR06 IMXRT_PADCFG(0, 15, 0x0, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_EMC_B1_15_FLEXPWM4_PWMB01 IMXRT_PADCFG(0, 15, 0x1, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_EMC_B1_15_LPUART5_RX IMXRT_PADCFG(0, 15, 0x2, 0, 127, 0x0) +#define IOMUXC_PAD_GPIO_EMC_B1_15_NETC_PINMUX_ETH2_TX_CLK IMXRT_PADCFG(0, 15, 0x3, 0, 221, 0x0) +#define IOMUXC_PAD_GPIO_EMC_B1_15_NETC_ETH3_COL IMXRT_PADCFG(0, 15, 0x4, 0, 195, 0x0) +#define IOMUXC_PAD_GPIO_EMC_B1_15_GPIO2_IO15 IMXRT_PADCFG(0, 15, 0x5, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_EMC_B1_15_KPP_COL00 IMXRT_PADCFG(0, 15, 0x6, 0, 66, 0x0) +#define IOMUXC_PAD_GPIO_EMC_B1_15_FLEXIO1_FLEXIO15 IMXRT_PADCFG(0, 15, 0x8, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_EMC_B1_15_NETC_ETH4_COL IMXRT_PADCFG(0, 15, 0x9, 0, 199, 0x0) +#define IOMUXC_PAD_GPIO_EMC_B1_15_LPUART4_RTS_B IMXRT_PADCFG(0, 15, 0xa, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_EMC_B1_15_AHB_SRAMC_ADDR06 IMXRT_PADCFG(0, 15, 0xc, 0, IMXRT_PADCFG_NO_DSYIDX, 0) + +#define IOMUXC_PAD_GPIO_EMC_B1_16_SEMC_ADDR07 IMXRT_PADCFG(0, 16, 0x0, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_EMC_B1_16_FLEXPWM4_PWMB02 IMXRT_PADCFG(0, 16, 0x1, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_EMC_B1_16_LPUART9_TX IMXRT_PADCFG(0, 16, 0x2, 0, 139, 0x0) +#define IOMUXC_PAD_GPIO_EMC_B1_16_NETC_PINMUX_ETH2_RXD00 IMXRT_PADCFG(0, 16, 0x3, 0, 217, 0x0) +#define IOMUXC_PAD_GPIO_EMC_B1_16_NETC_ETH3_SLV_MDC IMXRT_PADCFG(0, 16, 0x4, 0, 197, 0x0) +#define IOMUXC_PAD_GPIO_EMC_B1_16_GPIO2_IO16 IMXRT_PADCFG(0, 16, 0x5, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_EMC_B1_16_NETC_ETH4_SLV_MDC IMXRT_PADCFG(0, 16, 0x6, 0, 201, 0x0) +#define IOMUXC_PAD_GPIO_EMC_B1_16_FLEXIO1_FLEXIO16 IMXRT_PADCFG(0, 16, 0x8, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_EMC_B1_16_NETC_ETH2_SLV_MDC IMXRT_PADCFG(0, 16, 0x9, 0, 193, 0x0) +#define IOMUXC_PAD_GPIO_EMC_B1_16_LPSPI6_PCS2 IMXRT_PADCFG(0, 16, 0xa, 0, 110, 0x0) +#define IOMUXC_PAD_GPIO_EMC_B1_16_AHB_SRAMC_ADDR07 IMXRT_PADCFG(0, 16, 0xc, 0, IMXRT_PADCFG_NO_DSYIDX, 0) + +#define IOMUXC_PAD_GPIO_EMC_B1_17_SEMC_ADDR08 IMXRT_PADCFG(0, 17, 0x0, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_EMC_B1_17_FLEXPWM4_PWMA02 IMXRT_PADCFG(0, 17, 0x1, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_EMC_B1_17_LPUART9_RX IMXRT_PADCFG(0, 17, 0x2, 0, 138, 0x0) +#define IOMUXC_PAD_GPIO_EMC_B1_17_NETC_PINMUX_ETH2_RXD01 IMXRT_PADCFG(0, 17, 0x3, 0, 218, 0x0) +#define IOMUXC_PAD_GPIO_EMC_B1_17_NETC_ETH3_SLV_MDIO IMXRT_PADCFG(0, 17, 0x4, 0, 198, 0x0) +#define IOMUXC_PAD_GPIO_EMC_B1_17_GPIO2_IO17 IMXRT_PADCFG(0, 17, 0x5, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_EMC_B1_17_NETC_ETH4_SLV_MDIO IMXRT_PADCFG(0, 17, 0x6, 0, 202, 0x0) +#define IOMUXC_PAD_GPIO_EMC_B1_17_FLEXIO1_FLEXIO17 IMXRT_PADCFG(0, 17, 0x8, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_EMC_B1_17_NETC_ETH2_SLV_MDIO IMXRT_PADCFG(0, 17, 0x9, 0, 194, 0x0) +#define IOMUXC_PAD_GPIO_EMC_B1_17_LPSPI6_PCS1 IMXRT_PADCFG(0, 17, 0xa, 0, 109, 0x0) +#define IOMUXC_PAD_GPIO_EMC_B1_17_AHB_SRAMC_ADDR08 IMXRT_PADCFG(0, 17, 0xc, 0, IMXRT_PADCFG_NO_DSYIDX, 0) + +#define IOMUXC_PAD_GPIO_EMC_B1_18_SEMC_ADDR09 IMXRT_PADCFG(0, 18, 0x0, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_EMC_B1_18_FLEXPWM2_PWMA00 IMXRT_PADCFG(0, 18, 0x1, 0, 27, 0x0) +#define IOMUXC_PAD_GPIO_EMC_B1_18_QTIMER1_TIMER0 IMXRT_PADCFG(0, 18, 0x2, 0, 238, 0x0) +#define IOMUXC_PAD_GPIO_EMC_B1_18_LPSPI6_SCK IMXRT_PADCFG(0, 18, 0x3, 0, 112, 0x0) +#define IOMUXC_PAD_GPIO_EMC_B1_18_NETC_ETH2_CRS IMXRT_PADCFG(0, 18, 0x4, 0, 192, 0x0) +#define IOMUXC_PAD_GPIO_EMC_B1_18_GPIO2_IO18 IMXRT_PADCFG(0, 18, 0x5, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_EMC_B1_18_FLEXIO1_FLEXIO18 IMXRT_PADCFG(0, 18, 0x8, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_EMC_B1_18_NETC_EMDC IMXRT_PADCFG(0, 18, 0xa, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_EMC_B1_18_AHB_SRAMC_ADDR09 IMXRT_PADCFG(0, 18, 0xc, 0, IMXRT_PADCFG_NO_DSYIDX, 0) + +#define IOMUXC_PAD_GPIO_EMC_B1_19_SEMC_ADDR11 IMXRT_PADCFG(0, 19, 0x0, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_EMC_B1_19_FLEXPWM2_PWMB00 IMXRT_PADCFG(0, 19, 0x1, 0, 30, 0x0) +#define IOMUXC_PAD_GPIO_EMC_B1_19_QTIMER2_TIMER0 IMXRT_PADCFG(0, 19, 0x2, 0, 241, 0x0) +#define IOMUXC_PAD_GPIO_EMC_B1_19_LPSPI6_SDI IMXRT_PADCFG(0, 19, 0x3, 0, 113, 0x0) +#define IOMUXC_PAD_GPIO_EMC_B1_19_NETC_ETH2_COL IMXRT_PADCFG(0, 19, 0x4, 0, 191, 0x0) +#define IOMUXC_PAD_GPIO_EMC_B1_19_GPIO2_IO19 IMXRT_PADCFG(0, 19, 0x5, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_EMC_B1_19_FLEXIO1_FLEXIO19 IMXRT_PADCFG(0, 19, 0x8, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_EMC_B1_19_NETC_EMDIO IMXRT_PADCFG(0, 19, 0xa, 0, 190, 0x0) +#define IOMUXC_PAD_GPIO_EMC_B1_19_AHB_SRAMC_ADDR11 IMXRT_PADCFG(0, 19, 0xc, 0, IMXRT_PADCFG_NO_DSYIDX, 0) + +#define IOMUXC_PAD_GPIO_EMC_B1_20_SEMC_ADDR12 IMXRT_PADCFG(0, 20, 0x0, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_EMC_B1_20_FLEXPWM2_PWMA01 IMXRT_PADCFG(0, 20, 0x1, 0, 28, 0x0) +#define IOMUXC_PAD_GPIO_EMC_B1_20_QTIMER3_TIMER0 IMXRT_PADCFG(0, 20, 0x2, 0, 244, 0x0) +#define IOMUXC_PAD_GPIO_EMC_B1_20_LPSPI6_SDO IMXRT_PADCFG(0, 20, 0x3, 0, 114, 0x0) +#define IOMUXC_PAD_GPIO_EMC_B1_20_NETC_PINMUX_ETH2_TX_ER IMXRT_PADCFG(0, 20, 0x4, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_EMC_B1_20_GPIO2_IO20 IMXRT_PADCFG(0, 20, 0x5, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_EMC_B1_20_FLEXIO1_FLEXIO20 IMXRT_PADCFG(0, 20, 0x8, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_EMC_B1_20_AHB_SRAMC_ADDR12 IMXRT_PADCFG(0, 20, 0xc, 0, IMXRT_PADCFG_NO_DSYIDX, 0) + +#define IOMUXC_PAD_GPIO_EMC_B1_21_SEMC_BA0 IMXRT_PADCFG(0, 21, 0x0, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_EMC_B1_21_FLEXPWM2_PWMB01 IMXRT_PADCFG(0, 21, 0x1, 0, 31, 0x0) +#define IOMUXC_PAD_GPIO_EMC_B1_21_QTIMER4_TIMER0 IMXRT_PADCFG(0, 21, 0x2, 0, 247, 0x0) +#define IOMUXC_PAD_GPIO_EMC_B1_21_LPSPI6_PCS0 IMXRT_PADCFG(0, 21, 0x3, 0, 108, 0x0) +#define IOMUXC_PAD_GPIO_EMC_B1_21_NETC_PINMUX_ETH2_RX_CLK IMXRT_PADCFG(0, 21, 0x4, 0, 214, 0x0) +#define IOMUXC_PAD_GPIO_EMC_B1_21_GPIO2_IO21 IMXRT_PADCFG(0, 21, 0x5, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_EMC_B1_21_FLEXIO1_FLEXIO21 IMXRT_PADCFG(0, 21, 0x8, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_EMC_B1_21_LPUART4_CTS_B IMXRT_PADCFG(0, 21, 0x9, 0, 122, 0x1) +#define IOMUXC_PAD_GPIO_EMC_B1_21_FLEXSPI2_BUS2BIT_B_DQS IMXRT_PADCFG(0, 21, 0xa, 0, 53, 0x0) +#define IOMUXC_PAD_GPIO_EMC_B1_21_AHB_SRAMC_ADDR13 IMXRT_PADCFG(0, 21, 0xc, 0, IMXRT_PADCFG_NO_DSYIDX, 0) + +#define IOMUXC_PAD_GPIO_EMC_B1_22_SEMC_BA1 IMXRT_PADCFG(0, 22, 0x0, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_EMC_B1_22_FLEXPWM2_PWMB02 IMXRT_PADCFG(0, 22, 0x1, 0, 32, 0x0) +#define IOMUXC_PAD_GPIO_EMC_B1_22_QTIMER5_TIMER0 IMXRT_PADCFG(0, 22, 0x2, 0, 250, 0x0) +#define IOMUXC_PAD_GPIO_EMC_B1_22_LPSPI4_SCK IMXRT_PADCFG(0, 22, 0x3, 0, 98, 0x0) +#define IOMUXC_PAD_GPIO_EMC_B1_22_NETC_PINMUX_ETH2_RXD02 IMXRT_PADCFG(0, 22, 0x4, 0, 219, 0x0) +#define IOMUXC_PAD_GPIO_EMC_B1_22_GPIO2_IO22 IMXRT_PADCFG(0, 22, 0x5, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_EMC_B1_22_FLEXIO1_FLEXIO22 IMXRT_PADCFG(0, 22, 0x8, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_EMC_B1_22_LPUART4_RTS_B IMXRT_PADCFG(0, 22, 0x9, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_EMC_B1_22_FLEXSPI2_BUS2BIT_B_DATA03 IMXRT_PADCFG(0, 22, 0xa, 0, 61, 0x0) +#define IOMUXC_PAD_GPIO_EMC_B1_22_AHB_SRAMC_ADDR14 IMXRT_PADCFG(0, 22, 0xc, 0, IMXRT_PADCFG_NO_DSYIDX, 0) + +#define IOMUXC_PAD_GPIO_EMC_B1_23_SEMC_ADDR10 IMXRT_PADCFG(0, 23, 0x0, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_EMC_B1_23_FLEXPWM2_PWMA02 IMXRT_PADCFG(0, 23, 0x1, 0, 29, 0x0) +#define IOMUXC_PAD_GPIO_EMC_B1_23_QTIMER6_TIMER0 IMXRT_PADCFG(0, 23, 0x2, 0, 253, 0x0) +#define IOMUXC_PAD_GPIO_EMC_B1_23_LPSPI4_SDI IMXRT_PADCFG(0, 23, 0x3, 0, 99, 0x0) +#define IOMUXC_PAD_GPIO_EMC_B1_23_NETC_PINMUX_ETH2_RXD03 IMXRT_PADCFG(0, 23, 0x4, 0, 220, 0x0) +#define IOMUXC_PAD_GPIO_EMC_B1_23_GPIO2_IO23 IMXRT_PADCFG(0, 23, 0x5, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_EMC_B1_23_FLEXIO1_FLEXIO23 IMXRT_PADCFG(0, 23, 0x8, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_EMC_B1_23_FLEXSPI2_BUS2BIT_B_DATA02 IMXRT_PADCFG(0, 23, 0xa, 0, 60, 0x0) +#define IOMUXC_PAD_GPIO_EMC_B1_23_AHB_SRAMC_ADDR10 IMXRT_PADCFG(0, 23, 0xc, 0, IMXRT_PADCFG_NO_DSYIDX, 0) + +#define IOMUXC_PAD_GPIO_EMC_B1_24_SEMC_CAS IMXRT_PADCFG(0, 24, 0x0, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_EMC_B1_24_FLEXPWM1_PWMA00 IMXRT_PADCFG(0, 24, 0x1, 0, 21, 0x0) +#define IOMUXC_PAD_GPIO_EMC_B1_24_QTIMER7_TIMER0 IMXRT_PADCFG(0, 24, 0x2, 0, 256, 0x0) +#define IOMUXC_PAD_GPIO_EMC_B1_24_LPSPI4_SDO IMXRT_PADCFG(0, 24, 0x3, 0, 100, 0x0) +#define IOMUXC_PAD_GPIO_EMC_B1_24_NETC_PINMUX_ETH2_TXD03 IMXRT_PADCFG(0, 24, 0x4, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_EMC_B1_24_GPIO2_IO24 IMXRT_PADCFG(0, 24, 0x5, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_EMC_B1_24_FLEXIO1_FLEXIO24 IMXRT_PADCFG(0, 24, 0x8, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_EMC_B1_24_NETC_ETH3_SLV_MDC IMXRT_PADCFG(0, 24, 0x9, 0, 197, 0x1) +#define IOMUXC_PAD_GPIO_EMC_B1_24_FLEXSPI2_BUS2BIT_B_DATA01 IMXRT_PADCFG(0, 24, 0xa, 0, 59, 0x0) +#define IOMUXC_PAD_GPIO_EMC_B1_24_AHB_SRAMC_ADDR15 IMXRT_PADCFG(0, 24, 0xc, 0, IMXRT_PADCFG_NO_DSYIDX, 0) + +#define IOMUXC_PAD_GPIO_EMC_B1_25_SEMC_RAS IMXRT_PADCFG(0, 25, 0x0, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_EMC_B1_25_FLEXPWM1_PWMB00 IMXRT_PADCFG(0, 25, 0x1, 0, 24, 0x0) +#define IOMUXC_PAD_GPIO_EMC_B1_25_QTIMER8_TIMER0 IMXRT_PADCFG(0, 25, 0x2, 0, 258, 0x0) +#define IOMUXC_PAD_GPIO_EMC_B1_25_LPSPI4_PCS0 IMXRT_PADCFG(0, 25, 0x3, 0, 97, 0x0) +#define IOMUXC_PAD_GPIO_EMC_B1_25_NETC_PINMUX_ETH2_TXD02 IMXRT_PADCFG(0, 25, 0x4, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_EMC_B1_25_GPIO2_IO25 IMXRT_PADCFG(0, 25, 0x5, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_EMC_B1_25_FLEXIO1_FLEXIO25 IMXRT_PADCFG(0, 25, 0x8, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_EMC_B1_25_NETC_ETH3_SLV_MDIO IMXRT_PADCFG(0, 25, 0x9, 0, 198, 0x1) +#define IOMUXC_PAD_GPIO_EMC_B1_25_FLEXSPI2_BUS2BIT_B_DATA00 IMXRT_PADCFG(0, 25, 0xa, 0, 58, 0x0) +#define IOMUXC_PAD_GPIO_EMC_B1_25_AHB_SRAMC_ADDR16 IMXRT_PADCFG(0, 25, 0xc, 0, IMXRT_PADCFG_NO_DSYIDX, 0) + +#define IOMUXC_PAD_GPIO_EMC_B1_26_SEMC_CLK IMXRT_PADCFG(0, 26, 0x0, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_EMC_B1_26_FLEXPWM1_PWMA01 IMXRT_PADCFG(0, 26, 0x1, 0, 22, 0x0) +#define IOMUXC_PAD_GPIO_EMC_B1_26_XBAR1_XBAR_INOUT10 IMXRT_PADCFG(0, 26, 0x2, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_EMC_B1_26_FLEXSPI2_BUS2BIT_A_SS1_B IMXRT_PADCFG(0, 26, 0x3, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_EMC_B1_26_NETC_PINMUX_ETH2_TXD01 IMXRT_PADCFG(0, 26, 0x4, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_EMC_B1_26_GPIO2_IO26 IMXRT_PADCFG(0, 26, 0x5, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_EMC_B1_26_ECAT_TX_DATA1_1 IMXRT_PADCFG(0, 26, 0x6, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_EMC_B1_26_LPSPI6_SCK IMXRT_PADCFG(0, 26, 0xa, 0, 112, 0x1) +#define IOMUXC_PAD_GPIO_EMC_B1_26_AHB_SRAMC_WE IMXRT_PADCFG(0, 26, 0xc, 0, IMXRT_PADCFG_NO_DSYIDX, 0) + +#define IOMUXC_PAD_GPIO_EMC_B1_27_SEMC_CKE IMXRT_PADCFG(0, 27, 0x0, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_EMC_B1_27_FLEXPWM1_PWMB01 IMXRT_PADCFG(0, 27, 0x1, 0, 25, 0x0) +#define IOMUXC_PAD_GPIO_EMC_B1_27_XBAR1_XBAR_INOUT11 IMXRT_PADCFG(0, 27, 0x2, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_EMC_B1_27_FLEXSPI2_BUS2BIT_B_SS1_B IMXRT_PADCFG(0, 27, 0x3, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_EMC_B1_27_NETC_PINMUX_ETH2_TXD00 IMXRT_PADCFG(0, 27, 0x4, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_EMC_B1_27_GPIO2_IO27 IMXRT_PADCFG(0, 27, 0x5, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_EMC_B1_27_ECAT_TX_DATA0_1 IMXRT_PADCFG(0, 27, 0x6, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_EMC_B1_27_LPUART6_RI_B IMXRT_PADCFG(0, 27, 0x9, 0, 132, 0x0) +#define IOMUXC_PAD_GPIO_EMC_B1_27_LPSPI6_SDI IMXRT_PADCFG(0, 27, 0xa, 0, 113, 0x1) +#define IOMUXC_PAD_GPIO_EMC_B1_27_AHB_SRAMC_OEB IMXRT_PADCFG(0, 27, 0xc, 0, IMXRT_PADCFG_NO_DSYIDX, 0) + +#define IOMUXC_PAD_GPIO_EMC_B1_28_SEMC_WE IMXRT_PADCFG(0, 28, 0x0, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_EMC_B1_28_FLEXPWM1_PWMB02 IMXRT_PADCFG(0, 28, 0x1, 0, 26, 0x0) +#define IOMUXC_PAD_GPIO_EMC_B1_28_XBAR1_XBAR_INOUT12 IMXRT_PADCFG(0, 28, 0x2, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_EMC_B1_28_FLEXSPI2_BUS2BIT_B_SS0_B IMXRT_PADCFG(0, 28, 0x3, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_EMC_B1_28_NETC_PINMUX_ETH2_TX_EN IMXRT_PADCFG(0, 28, 0x4, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_EMC_B1_28_GPIO2_IO28 IMXRT_PADCFG(0, 28, 0x5, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_EMC_B1_28_ECAT_TX_EN_1 IMXRT_PADCFG(0, 28, 0x6, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_EMC_B1_28_LPUART6_DTR_B IMXRT_PADCFG(0, 28, 0x9, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_EMC_B1_28_LPSPI6_SDO IMXRT_PADCFG(0, 28, 0xa, 0, 114, 0x1) +#define IOMUXC_PAD_GPIO_EMC_B1_28_AHB_SRAMC_ADV IMXRT_PADCFG(0, 28, 0xc, 0, IMXRT_PADCFG_NO_DSYIDX, 0) + +#define IOMUXC_PAD_GPIO_EMC_B1_29_SEMC_CS0 IMXRT_PADCFG(0, 29, 0x0, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_EMC_B1_29_FLEXPWM1_PWMA02 IMXRT_PADCFG(0, 29, 0x1, 0, 23, 0x0) +#define IOMUXC_PAD_GPIO_EMC_B1_29_XBAR1_XBAR_INOUT13 IMXRT_PADCFG(0, 29, 0x2, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_EMC_B1_29_FLEXSPI2_BUS2BIT_B_DQS IMXRT_PADCFG(0, 29, 0x3, 0, 53, 0x1) +#define IOMUXC_PAD_GPIO_EMC_B1_29_NETC_PINMUX_ETH2_TX_CLK IMXRT_PADCFG(0, 29, 0x4, 0, 221, 0x1) +#define IOMUXC_PAD_GPIO_EMC_B1_29_GPIO2_IO29 IMXRT_PADCFG(0, 29, 0x5, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_EMC_B1_29_ECAT_TX_CLK_1 IMXRT_PADCFG(0, 29, 0x6, 0, 18, 0x0) +#define IOMUXC_PAD_GPIO_EMC_B1_29_LPUART6_DCD_B IMXRT_PADCFG(0, 29, 0x9, 0, 130, 0x0) +#define IOMUXC_PAD_GPIO_EMC_B1_29_LPSPI6_PCS0 IMXRT_PADCFG(0, 29, 0xa, 0, 108, 0x1) +#define IOMUXC_PAD_GPIO_EMC_B1_29_AHB_SRAMC_CS0 IMXRT_PADCFG(0, 29, 0xc, 0, IMXRT_PADCFG_NO_DSYIDX, 0) + +#define IOMUXC_PAD_GPIO_EMC_B1_30_SEMC_DATA08 IMXRT_PADCFG(0, 30, 0x0, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_EMC_B1_30_FLEXPWM3_PWMA00 IMXRT_PADCFG(0, 30, 0x1, 0, 33, 0x0) +#define IOMUXC_PAD_GPIO_EMC_B1_30_XBAR1_XBAR_INOUT14 IMXRT_PADCFG(0, 30, 0x2, 0, 293, 0x0) +#define IOMUXC_PAD_GPIO_EMC_B1_30_FLEXSPI2_BUS2BIT_B_DATA03 IMXRT_PADCFG(0, 30, 0x3, 0, 61, 0x1) +#define IOMUXC_PAD_GPIO_EMC_B1_30_NETC_PINMUX_ETH2_RXD00 IMXRT_PADCFG(0, 30, 0x4, 0, 217, 0x1) +#define IOMUXC_PAD_GPIO_EMC_B1_30_GPIO2_IO30 IMXRT_PADCFG(0, 30, 0x5, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_EMC_B1_30_ECAT_RX_DATA0_1 IMXRT_PADCFG(0, 30, 0x6, 0, 6, 0x0) +#define IOMUXC_PAD_GPIO_EMC_B1_30_LPUART6_DSR_B IMXRT_PADCFG(0, 30, 0x9, 0, 131, 0x0) +#define IOMUXC_PAD_GPIO_EMC_B1_30_LPSPI6_PCS1 IMXRT_PADCFG(0, 30, 0xa, 0, 109, 0x1) +#define IOMUXC_PAD_GPIO_EMC_B1_30_AHB_SRAMC_DATA08 IMXRT_PADCFG(0, 30, 0xc, 0, IMXRT_PADCFG_NO_DSYIDX, 0) + +#define IOMUXC_PAD_GPIO_EMC_B1_31_SEMC_DATA09 IMXRT_PADCFG(0, 31, 0x0, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_EMC_B1_31_FLEXPWM3_PWMB00 IMXRT_PADCFG(0, 31, 0x1, 0, 37, 0x0) +#define IOMUXC_PAD_GPIO_EMC_B1_31_LPUART6_TX IMXRT_PADCFG(0, 31, 0x2, 0, 134, 0x0) +#define IOMUXC_PAD_GPIO_EMC_B1_31_FLEXSPI2_BUS2BIT_B_DATA02 IMXRT_PADCFG(0, 31, 0x3, 0, 60, 0x1) +#define IOMUXC_PAD_GPIO_EMC_B1_31_NETC_PINMUX_ETH2_RXD01 IMXRT_PADCFG(0, 31, 0x4, 0, 218, 0x1) +#define IOMUXC_PAD_GPIO_EMC_B1_31_GPIO2_IO31 IMXRT_PADCFG(0, 31, 0x5, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_EMC_B1_31_ECAT_RX_DATA1_1 IMXRT_PADCFG(0, 31, 0x6, 0, 8, 0x0) +#define IOMUXC_PAD_GPIO_EMC_B1_31_LPSPI5_SCK IMXRT_PADCFG(0, 31, 0x9, 0, 105, 0x0) +#define IOMUXC_PAD_GPIO_EMC_B1_31_LPSPI6_PCS2 IMXRT_PADCFG(0, 31, 0xa, 0, 110, 0x1) +#define IOMUXC_PAD_GPIO_EMC_B1_31_AHB_SRAMC_DATA09 IMXRT_PADCFG(0, 31, 0xc, 0, IMXRT_PADCFG_NO_DSYIDX, 0) + +#define IOMUXC_PAD_GPIO_EMC_B1_32_SEMC_DATA10 IMXRT_PADCFG(0, 32, 0x0, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_EMC_B1_32_FLEXPWM3_PWMA01 IMXRT_PADCFG(0, 32, 0x1, 0, 34, 0x0) +#define IOMUXC_PAD_GPIO_EMC_B1_32_LPUART6_RX IMXRT_PADCFG(0, 32, 0x2, 0, 133, 0x0) +#define IOMUXC_PAD_GPIO_EMC_B1_32_FLEXSPI2_BUS2BIT_B_DATA01 IMXRT_PADCFG(0, 32, 0x3, 0, 59, 0x1) +#define IOMUXC_PAD_GPIO_EMC_B1_32_NETC_PINMUX_ETH2_RX_DV IMXRT_PADCFG(0, 32, 0x4, 0, 215, 0x1) +#define IOMUXC_PAD_GPIO_EMC_B1_32_GPIO3_IO00 IMXRT_PADCFG(0, 32, 0x5, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_EMC_B1_32_ECAT_RX_DV_1 IMXRT_PADCFG(0, 32, 0x6, 0, 14, 0x0) +#define IOMUXC_PAD_GPIO_EMC_B1_32_LPSPI5_SDO IMXRT_PADCFG(0, 32, 0x9, 0, 107, 0x0) +#define IOMUXC_PAD_GPIO_EMC_B1_32_LPSPI6_PCS3 IMXRT_PADCFG(0, 32, 0xa, 0, 111, 0x0) +#define IOMUXC_PAD_GPIO_EMC_B1_32_AHB_SRAMC_DATA10 IMXRT_PADCFG(0, 32, 0xc, 0, IMXRT_PADCFG_NO_DSYIDX, 0) + +#define IOMUXC_PAD_GPIO_EMC_B1_33_SEMC_DATA11 IMXRT_PADCFG(0, 33, 0x0, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_EMC_B1_33_FLEXPWM3_PWMB01 IMXRT_PADCFG(0, 33, 0x1, 0, 38, 0x0) +#define IOMUXC_PAD_GPIO_EMC_B1_33_LPUART6_CTS_B IMXRT_PADCFG(0, 33, 0x2, 0, 129, 0x0) +#define IOMUXC_PAD_GPIO_EMC_B1_33_FLEXSPI2_BUS2BIT_B_DATA00 IMXRT_PADCFG(0, 33, 0x3, 0, 58, 0x1) +#define IOMUXC_PAD_GPIO_EMC_B1_33_NETC_PINMUX_ETH2_RX_ER IMXRT_PADCFG(0, 33, 0x4, 0, 216, 0x0) +#define IOMUXC_PAD_GPIO_EMC_B1_33_GPIO3_IO01 IMXRT_PADCFG(0, 33, 0x5, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_EMC_B1_33_ECAT_RX_ER_1 IMXRT_PADCFG(0, 33, 0x6, 0, 16, 0x0) +#define IOMUXC_PAD_GPIO_EMC_B1_33_LPSPI5_SDI IMXRT_PADCFG(0, 33, 0x9, 0, 106, 0x0) +#define IOMUXC_PAD_GPIO_EMC_B1_33_NETC_PINMUX_ETH2_RX_CLK IMXRT_PADCFG(0, 33, 0xa, 0, 214, 0x1) +#define IOMUXC_PAD_GPIO_EMC_B1_33_AHB_SRAMC_DATA11 IMXRT_PADCFG(0, 33, 0xc, 0, IMXRT_PADCFG_NO_DSYIDX, 0) + +#define IOMUXC_PAD_GPIO_EMC_B1_34_SEMC_DATA12 IMXRT_PADCFG(0, 34, 0x0, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_EMC_B1_34_FLEXPWM3_PWMB02 IMXRT_PADCFG(0, 34, 0x1, 0, 39, 0x0) +#define IOMUXC_PAD_GPIO_EMC_B1_34_LPUART6_RTS_B IMXRT_PADCFG(0, 34, 0x2, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_EMC_B1_34_FLEXSPI2_BUS2BIT_B_SCLK IMXRT_PADCFG(0, 34, 0x3, 0, 63, 0x0) +#define IOMUXC_PAD_GPIO_EMC_B1_34_NETC_PINMUX_ETH2_RXD02 IMXRT_PADCFG(0, 34, 0x4, 0, 219, 0x1) +#define IOMUXC_PAD_GPIO_EMC_B1_34_GPIO3_IO02 IMXRT_PADCFG(0, 34, 0x5, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_EMC_B1_34_ECAT_RX_DATA2_1 IMXRT_PADCFG(0, 34, 0x6, 0, 10, 0x0) +#define IOMUXC_PAD_GPIO_EMC_B1_34_NETC_PINMUX_ETH0_TXD00 IMXRT_PADCFG(0, 34, 0x9, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_EMC_B1_34_LPSPI5_PCS0 IMXRT_PADCFG(0, 34, 0xa, 0, 101, 0x0) +#define IOMUXC_PAD_GPIO_EMC_B1_34_AHB_SRAMC_DATA12 IMXRT_PADCFG(0, 34, 0xc, 0, IMXRT_PADCFG_NO_DSYIDX, 0) + +#define IOMUXC_PAD_GPIO_EMC_B1_35_SEMC_DATA13 IMXRT_PADCFG(0, 35, 0x0, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_EMC_B1_35_FLEXPWM3_PWMA02 IMXRT_PADCFG(0, 35, 0x1, 0, 35, 0x0) +#define IOMUXC_PAD_GPIO_EMC_B1_35_LPUART5_TX IMXRT_PADCFG(0, 35, 0x2, 0, 128, 0x1) +#define IOMUXC_PAD_GPIO_EMC_B1_35_FLEXSPI2_BUS2BIT_A_DATA00 IMXRT_PADCFG(0, 35, 0x3, 0, 54, 0x0) +#define IOMUXC_PAD_GPIO_EMC_B1_35_NETC_PINMUX_ETH2_RXD03 IMXRT_PADCFG(0, 35, 0x4, 0, 220, 0x1) +#define IOMUXC_PAD_GPIO_EMC_B1_35_GPIO3_IO03 IMXRT_PADCFG(0, 35, 0x5, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_EMC_B1_35_ECAT_RX_DATA3_1 IMXRT_PADCFG(0, 35, 0x6, 0, 12, 0x0) +#define IOMUXC_PAD_GPIO_EMC_B1_35_NETC_PINMUX_ETH0_TXD01 IMXRT_PADCFG(0, 35, 0x9, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_EMC_B1_35_LPSPI5_PCS1 IMXRT_PADCFG(0, 35, 0xa, 0, 102, 0x0) +#define IOMUXC_PAD_GPIO_EMC_B1_35_AHB_SRAMC_DATA13 IMXRT_PADCFG(0, 35, 0xc, 0, IMXRT_PADCFG_NO_DSYIDX, 0) + +#define IOMUXC_PAD_GPIO_EMC_B1_36_SEMC_DATA14 IMXRT_PADCFG(0, 36, 0x0, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_EMC_B1_36_FLEXPWM1_PWMA00 IMXRT_PADCFG(0, 36, 0x1, 0, 21, 0x1) +#define IOMUXC_PAD_GPIO_EMC_B1_36_LPUART5_RX IMXRT_PADCFG(0, 36, 0x2, 0, 127, 0x1) +#define IOMUXC_PAD_GPIO_EMC_B1_36_FLEXSPI2_BUS2BIT_A_DATA01 IMXRT_PADCFG(0, 36, 0x3, 0, 55, 0x0) +#define IOMUXC_PAD_GPIO_EMC_B1_36_NETC_PINMUX_ETH2_TXD03 IMXRT_PADCFG(0, 36, 0x4, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_EMC_B1_36_GPIO3_IO04 IMXRT_PADCFG(0, 36, 0x5, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_EMC_B1_36_ECAT_TX_DATA3_1 IMXRT_PADCFG(0, 36, 0x6, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_EMC_B1_36_NETC_PINMUX_ETH0_TX_EN IMXRT_PADCFG(0, 36, 0x9, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_EMC_B1_36_AHB_SRAMC_DATA14 IMXRT_PADCFG(0, 36, 0xc, 0, IMXRT_PADCFG_NO_DSYIDX, 0) + +#define IOMUXC_PAD_GPIO_EMC_B1_37_SEMC_DATA15 IMXRT_PADCFG(0, 37, 0x0, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_EMC_B1_37_FLEXPWM1_PWMB00 IMXRT_PADCFG(0, 37, 0x1, 0, 24, 0x1) +#define IOMUXC_PAD_GPIO_EMC_B1_37_LPUART5_CTS_B IMXRT_PADCFG(0, 37, 0x2, 0, 123, 0x0) +#define IOMUXC_PAD_GPIO_EMC_B1_37_FLEXSPI2_BUS2BIT_A_DATA02 IMXRT_PADCFG(0, 37, 0x3, 0, 56, 0x0) +#define IOMUXC_PAD_GPIO_EMC_B1_37_NETC_PINMUX_ETH2_TXD02 IMXRT_PADCFG(0, 37, 0x4, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_EMC_B1_37_GPIO3_IO05 IMXRT_PADCFG(0, 37, 0x5, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_EMC_B1_37_ECAT_TX_DATA2_1 IMXRT_PADCFG(0, 37, 0x6, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_EMC_B1_37_NETC_PINMUX_ETH0_TX_CLK IMXRT_PADCFG(0, 37, 0x9, 0, 213, 0x0) +#define IOMUXC_PAD_GPIO_EMC_B1_37_AHB_SRAMC_DATA15 IMXRT_PADCFG(0, 37, 0xc, 0, IMXRT_PADCFG_NO_DSYIDX, 0) + +#define IOMUXC_PAD_GPIO_EMC_B1_38_SEMC_DM01 IMXRT_PADCFG(0, 38, 0x0, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_EMC_B1_38_FLEXPWM1_PWMB03 IMXRT_PADCFG(0, 38, 0x1, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_EMC_B1_38_LPUART5_RTS_B IMXRT_PADCFG(0, 38, 0x2, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_EMC_B1_38_FLEXSPI2_BUS2BIT_A_DATA03 IMXRT_PADCFG(0, 38, 0x3, 0, 57, 0x0) +#define IOMUXC_PAD_GPIO_EMC_B1_38_NETC_PINMUX_ETH2_RX_CLK IMXRT_PADCFG(0, 38, 0x4, 0, 214, 0x2) +#define IOMUXC_PAD_GPIO_EMC_B1_38_GPIO3_IO06 IMXRT_PADCFG(0, 38, 0x5, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_EMC_B1_38_ECAT_RX_CLK_1 IMXRT_PADCFG(0, 38, 0x6, 0, 4, 0x0) +#define IOMUXC_PAD_GPIO_EMC_B1_38_NETC_PINMUX_ETH0_RXD00 IMXRT_PADCFG(0, 38, 0x9, 0, 209, 0x0) +#define IOMUXC_PAD_GPIO_EMC_B1_38_AHB_SRAMC_UBB IMXRT_PADCFG(0, 38, 0xc, 0, IMXRT_PADCFG_NO_DSYIDX, 0) + +#define IOMUXC_PAD_GPIO_EMC_B1_39_SEMC_DQS IMXRT_PADCFG(0, 39, 0x0, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_EMC_B1_39_FLEXPWM1_PWMA03 IMXRT_PADCFG(0, 39, 0x1, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_EMC_B1_39_XBAR1_XBAR_INOUT15 IMXRT_PADCFG(0, 39, 0x2, 0, 294, 0x0) +#define IOMUXC_PAD_GPIO_EMC_B1_39_FLEXSPI2_BUS2BIT_A_SS0_B IMXRT_PADCFG(0, 39, 0x3, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_EMC_B1_39_NETC_PINMUX_ETH2_TX_ER IMXRT_PADCFG(0, 39, 0x4, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_EMC_B1_39_GPIO3_IO07 IMXRT_PADCFG(0, 39, 0x5, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_EMC_B1_39_QTIMER2_TIMER1 IMXRT_PADCFG(0, 39, 0x6, 0, 242, 0x0) +#define IOMUXC_PAD_GPIO_EMC_B1_39_NETC_PINMUX_ETH0_RXD01 IMXRT_PADCFG(0, 39, 0x9, 0, 210, 0x0) +#define IOMUXC_PAD_GPIO_EMC_B1_39_AHB_SRAMC_CS1 IMXRT_PADCFG(0, 39, 0xc, 0, IMXRT_PADCFG_NO_DSYIDX, 0) + +#define IOMUXC_PAD_GPIO_EMC_B1_40_SEMC_RDY IMXRT_PADCFG(0, 40, 0x0, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_EMC_B1_40_NETC_EMDC IMXRT_PADCFG(0, 40, 0x1, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_EMC_B1_40_NETC_ETH2_SLV_MDC IMXRT_PADCFG(0, 40, 0x2, 0, 193, 0x1) +#define IOMUXC_PAD_GPIO_EMC_B1_40_FLEXSPI2_BUS2BIT_A_DQS IMXRT_PADCFG(0, 40, 0x3, 0, 52, 0x0) +#define IOMUXC_PAD_GPIO_EMC_B1_40_NETC_ETH2_CRS IMXRT_PADCFG(0, 40, 0x4, 0, 192, 0x1) +#define IOMUXC_PAD_GPIO_EMC_B1_40_GPIO3_IO08 IMXRT_PADCFG(0, 40, 0x5, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_EMC_B1_40_QTIMER3_TIMER1 IMXRT_PADCFG(0, 40, 0x6, 0, 245, 0x0) +#define IOMUXC_PAD_GPIO_EMC_B1_40_NETC_PINMUX_ETH0_RX_DV IMXRT_PADCFG(0, 40, 0x9, 0, 207, 0x0) +#define IOMUXC_PAD_GPIO_EMC_B1_40_AHB_SRAMC_CS2 IMXRT_PADCFG(0, 40, 0xc, 0, IMXRT_PADCFG_NO_DSYIDX, 0) + +#define IOMUXC_PAD_GPIO_EMC_B1_41_SEMC_CSX00 IMXRT_PADCFG(0, 41, 0x0, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_EMC_B1_41_NETC_EMDIO IMXRT_PADCFG(0, 41, 0x1, 0, 190, 0x1) +#define IOMUXC_PAD_GPIO_EMC_B1_41_NETC_ETH2_SLV_MDIO IMXRT_PADCFG(0, 41, 0x2, 0, 194, 0x1) +#define IOMUXC_PAD_GPIO_EMC_B1_41_FLEXSPI2_BUS2BIT_A_SCLK IMXRT_PADCFG(0, 41, 0x3, 0, 62, 0x0) +#define IOMUXC_PAD_GPIO_EMC_B1_41_NETC_ETH2_COL IMXRT_PADCFG(0, 41, 0x4, 0, 191, 0x1) +#define IOMUXC_PAD_GPIO_EMC_B1_41_GPIO3_IO09 IMXRT_PADCFG(0, 41, 0x5, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_EMC_B1_41_QTIMER4_TIMER1 IMXRT_PADCFG(0, 41, 0x6, 0, 248, 0x0) +#define IOMUXC_PAD_GPIO_EMC_B1_41_NETC_PINMUX_ETH0_RX_ER IMXRT_PADCFG(0, 41, 0x9, 0, 208, 0x0) +#define IOMUXC_PAD_GPIO_EMC_B1_41_AHB_SRAMC_CS3 IMXRT_PADCFG(0, 41, 0xc, 0, IMXRT_PADCFG_NO_DSYIDX, 0) + +#define IOMUXC_PAD_GPIO_EMC_B2_00_SEMC_DATA16 IMXRT_PADCFG(0, 42, 0x0, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_EMC_B2_00_CCM_ENET_REF_CLK_25M IMXRT_PADCFG(0, 42, 0x1, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_EMC_B2_00_QTIMER5_TIMER1 IMXRT_PADCFG(0, 42, 0x2, 0, 251, 0x0) +#define IOMUXC_PAD_GPIO_EMC_B2_00_NETC_EMDC IMXRT_PADCFG(0, 42, 0x3, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_EMC_B2_00_NETC_PINMUX_ETH0_RX_CLK IMXRT_PADCFG(0, 42, 0x4, 0, 206, 0x0) +#define IOMUXC_PAD_GPIO_EMC_B2_00_GPIO3_IO10 IMXRT_PADCFG(0, 42, 0x5, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_EMC_B2_00_XBAR1_XBAR_INOUT20 IMXRT_PADCFG(0, 42, 0x6, 0, 298, 0x0) +#define IOMUXC_PAD_GPIO_EMC_B2_00_LPSPI5_SCK IMXRT_PADCFG(0, 42, 0x8, 0, 105, 0x1) +#define IOMUXC_PAD_GPIO_EMC_B2_00_LPI2C3_SCL IMXRT_PADCFG(0, 42, 0x9, 0, 82, 0x0) +#define IOMUXC_PAD_GPIO_EMC_B2_00_FLEXPWM3_PWMA00 IMXRT_PADCFG(0, 42, 0xa, 0, 33, 0x1) +#define IOMUXC_PAD_GPIO_EMC_B2_00_ECAT_RX_CLK_0 IMXRT_PADCFG(0, 42, 0xc, 0, 3, 0x1) + +#define IOMUXC_PAD_GPIO_EMC_B2_01_SEMC_DATA17 IMXRT_PADCFG(0, 43, 0x0, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_EMC_B2_01_USDHC2_CD_B IMXRT_PADCFG(0, 43, 0x1, 0, 291, 0x0) +#define IOMUXC_PAD_GPIO_EMC_B2_01_QTIMER6_TIMER1 IMXRT_PADCFG(0, 43, 0x2, 0, 254, 0x0) +#define IOMUXC_PAD_GPIO_EMC_B2_01_NETC_EMDIO IMXRT_PADCFG(0, 43, 0x3, 0, 190, 0x2) +#define IOMUXC_PAD_GPIO_EMC_B2_01_NETC_PINMUX_ETH0_RXD02 IMXRT_PADCFG(0, 43, 0x4, 0, 211, 0x0) +#define IOMUXC_PAD_GPIO_EMC_B2_01_GPIO3_IO11 IMXRT_PADCFG(0, 43, 0x5, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_EMC_B2_01_XBAR1_XBAR_INOUT21 IMXRT_PADCFG(0, 43, 0x6, 0, 299, 0x0) +#define IOMUXC_PAD_GPIO_EMC_B2_01_LPSPI5_PCS0 IMXRT_PADCFG(0, 43, 0x8, 0, 101, 0x1) +#define IOMUXC_PAD_GPIO_EMC_B2_01_LPI2C3_SDA IMXRT_PADCFG(0, 43, 0x9, 0, 83, 0x0) +#define IOMUXC_PAD_GPIO_EMC_B2_01_FLEXPWM3_PWMB00 IMXRT_PADCFG(0, 43, 0xa, 0, 37, 0x1) +#define IOMUXC_PAD_GPIO_EMC_B2_01_ECAT_RX_DATA2_0 IMXRT_PADCFG(0, 43, 0xc, 0, 9, 0x1) + +#define IOMUXC_PAD_GPIO_EMC_B2_02_SEMC_DATA18 IMXRT_PADCFG(0, 44, 0x0, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_EMC_B2_02_USDHC2_WP IMXRT_PADCFG(0, 44, 0x1, 0, 292, 0x0) +#define IOMUXC_PAD_GPIO_EMC_B2_02_QTIMER7_TIMER1 IMXRT_PADCFG(0, 44, 0x2, 0, 257, 0x0) +#define IOMUXC_PAD_GPIO_EMC_B2_02_NETC_PINMUX_ETH0_RXD03 IMXRT_PADCFG(0, 44, 0x4, 0, 212, 0x0) +#define IOMUXC_PAD_GPIO_EMC_B2_02_GPIO3_IO12 IMXRT_PADCFG(0, 44, 0x5, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_EMC_B2_02_XBAR1_XBAR_INOUT22 IMXRT_PADCFG(0, 44, 0x6, 0, 300, 0x0) +#define IOMUXC_PAD_GPIO_EMC_B2_02_LPSPI5_SDO IMXRT_PADCFG(0, 44, 0x8, 0, 107, 0x1) +#define IOMUXC_PAD_GPIO_EMC_B2_02_CCM_CLKO1 IMXRT_PADCFG(0, 44, 0x9, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_EMC_B2_02_FLEXPWM3_PWMA01 IMXRT_PADCFG(0, 44, 0xa, 0, 34, 0x1) +#define IOMUXC_PAD_GPIO_EMC_B2_02_ECAT_RX_DATA3_0 IMXRT_PADCFG(0, 44, 0xc, 0, 11, 0x1) + +#define IOMUXC_PAD_GPIO_EMC_B2_03_SEMC_DATA19 IMXRT_PADCFG(0, 45, 0x0, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_EMC_B2_03_USDHC2_VSELECT IMXRT_PADCFG(0, 45, 0x1, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_EMC_B2_03_QTIMER8_TIMER1 IMXRT_PADCFG(0, 45, 0x2, 0, 259, 0x0) +#define IOMUXC_PAD_GPIO_EMC_B2_03_NETC_PINMUX_ETH0_TXD02 IMXRT_PADCFG(0, 45, 0x4, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_EMC_B2_03_GPIO3_IO13 IMXRT_PADCFG(0, 45, 0x5, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_EMC_B2_03_XBAR1_XBAR_INOUT23 IMXRT_PADCFG(0, 45, 0x6, 0, 301, 0x0) +#define IOMUXC_PAD_GPIO_EMC_B2_03_LPSPI5_SDI IMXRT_PADCFG(0, 45, 0x8, 0, 106, 0x1) +#define IOMUXC_PAD_GPIO_EMC_B2_03_NETC_ETH3_CRS IMXRT_PADCFG(0, 45, 0x9, 0, 196, 0x1) +#define IOMUXC_PAD_GPIO_EMC_B2_03_FLEXPWM3_PWMB01 IMXRT_PADCFG(0, 45, 0xa, 0, 38, 0x1) +#define IOMUXC_PAD_GPIO_EMC_B2_03_ECAT_TX_DATA2_0 IMXRT_PADCFG(0, 45, 0xc, 0, IMXRT_PADCFG_NO_DSYIDX, 0) + +#define IOMUXC_PAD_GPIO_EMC_B2_04_SEMC_DATA20 IMXRT_PADCFG(0, 46, 0x0, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_EMC_B2_04_USDHC2_RESET_B IMXRT_PADCFG(0, 46, 0x1, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_EMC_B2_04_SAI2_MCLK IMXRT_PADCFG(0, 46, 0x2, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_EMC_B2_04_NETC_PINMUX_ETH0_TXD03 IMXRT_PADCFG(0, 46, 0x4, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_EMC_B2_04_GPIO3_IO14 IMXRT_PADCFG(0, 46, 0x5, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_EMC_B2_04_XBAR1_XBAR_INOUT24 IMXRT_PADCFG(0, 46, 0x6, 0, 302, 0x0) +#define IOMUXC_PAD_GPIO_EMC_B2_04_LPSPI3_SCK IMXRT_PADCFG(0, 46, 0x8, 0, 94, 0x0) +#define IOMUXC_PAD_GPIO_EMC_B2_04_NETC_ETH3_COL IMXRT_PADCFG(0, 46, 0x9, 0, 195, 0x1) +#define IOMUXC_PAD_GPIO_EMC_B2_04_FLEXPWM3_PWMB02 IMXRT_PADCFG(0, 46, 0xa, 0, 39, 0x1) +#define IOMUXC_PAD_GPIO_EMC_B2_04_ECAT_TX_DATA3_0 IMXRT_PADCFG(0, 46, 0xc, 0, IMXRT_PADCFG_NO_DSYIDX, 0) + +#define IOMUXC_PAD_GPIO_EMC_B2_05_SEMC_DATA21 IMXRT_PADCFG(0, 47, 0x0, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_EMC_B2_05_NETC_ETH4_SLV_MDC IMXRT_PADCFG(0, 47, 0x1, 0, 201, 0x1) +#define IOMUXC_PAD_GPIO_EMC_B2_05_SAI2_RX_SYNC IMXRT_PADCFG(0, 47, 0x2, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_EMC_B2_05_NETC_PINMUX_ETH0_TXD00 IMXRT_PADCFG(0, 47, 0x3, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_EMC_B2_05_NETC_ETH4_CRS IMXRT_PADCFG(0, 47, 0x4, 0, 200, 0x1) +#define IOMUXC_PAD_GPIO_EMC_B2_05_GPIO3_IO15 IMXRT_PADCFG(0, 47, 0x5, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_EMC_B2_05_XBAR1_XBAR_INOUT25 IMXRT_PADCFG(0, 47, 0x6, 0, 303, 0x0) +#define IOMUXC_PAD_GPIO_EMC_B2_05_LPSPI3_PCS0 IMXRT_PADCFG(0, 47, 0x8, 0, 90, 0x0) +#define IOMUXC_PAD_GPIO_EMC_B2_05_NETC_PINMUX_ETH3_TXD00 IMXRT_PADCFG(0, 47, 0x9, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_EMC_B2_05_FLEXPWM3_PWMA02 IMXRT_PADCFG(0, 47, 0xa, 0, 35, 0x1) +#define IOMUXC_PAD_GPIO_EMC_B2_05_ECAT_TX_DATA0_0 IMXRT_PADCFG(0, 47, 0xc, 0, IMXRT_PADCFG_NO_DSYIDX, 0) + +#define IOMUXC_PAD_GPIO_EMC_B2_06_SEMC_DATA22 IMXRT_PADCFG(0, 48, 0x0, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_EMC_B2_06_NETC_ETH4_SLV_MDIO IMXRT_PADCFG(0, 48, 0x1, 0, 202, 0x1) +#define IOMUXC_PAD_GPIO_EMC_B2_06_SAI2_RX_BCLK IMXRT_PADCFG(0, 48, 0x2, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_EMC_B2_06_NETC_PINMUX_ETH0_TXD01 IMXRT_PADCFG(0, 48, 0x3, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_EMC_B2_06_NETC_ETH4_COL IMXRT_PADCFG(0, 48, 0x4, 0, 199, 0x1) +#define IOMUXC_PAD_GPIO_EMC_B2_06_GPIO3_IO16 IMXRT_PADCFG(0, 48, 0x5, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_EMC_B2_06_XBAR1_XBAR_INOUT26 IMXRT_PADCFG(0, 48, 0x6, 0, 304, 0x0) +#define IOMUXC_PAD_GPIO_EMC_B2_06_LPSPI3_SDO IMXRT_PADCFG(0, 48, 0x8, 0, 96, 0x0) +#define IOMUXC_PAD_GPIO_EMC_B2_06_NETC_PINMUX_ETH3_TXD01 IMXRT_PADCFG(0, 48, 0x9, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_EMC_B2_06_FLEXPWM3_PWMB03 IMXRT_PADCFG(0, 48, 0xa, 0, 40, 0x1) +#define IOMUXC_PAD_GPIO_EMC_B2_06_ECAT_TX_DATA1_0 IMXRT_PADCFG(0, 48, 0xc, 0, IMXRT_PADCFG_NO_DSYIDX, 0) + +#define IOMUXC_PAD_GPIO_EMC_B2_07_SEMC_DATA23 IMXRT_PADCFG(0, 49, 0x0, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_EMC_B2_07_NETC_PINMUX_ETH4_TX_ER IMXRT_PADCFG(0, 49, 0x1, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_EMC_B2_07_SAI2_RX_DATA IMXRT_PADCFG(0, 49, 0x2, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_EMC_B2_07_NETC_PINMUX_ETH0_TX_EN IMXRT_PADCFG(0, 49, 0x3, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_EMC_B2_07_GPIO3_IO17 IMXRT_PADCFG(0, 49, 0x5, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_EMC_B2_07_XBAR1_XBAR_INOUT27 IMXRT_PADCFG(0, 49, 0x6, 0, 305, 0x0) +#define IOMUXC_PAD_GPIO_EMC_B2_07_LPSPI3_SDI IMXRT_PADCFG(0, 49, 0x8, 0, 95, 0x0) +#define IOMUXC_PAD_GPIO_EMC_B2_07_NETC_PINMUX_ETH3_TX_EN IMXRT_PADCFG(0, 49, 0x9, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_EMC_B2_07_FLEXPWM3_PWMA03 IMXRT_PADCFG(0, 49, 0xa, 0, 36, 0x1) +#define IOMUXC_PAD_GPIO_EMC_B2_07_ECAT_TX_EN_0 IMXRT_PADCFG(0, 49, 0xc, 0, IMXRT_PADCFG_NO_DSYIDX, 0) + +#define IOMUXC_PAD_GPIO_EMC_B2_08_SEMC_DM02 IMXRT_PADCFG(0, 50, 0x0, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_EMC_B2_08_NETC_PINMUX_ETH4_RX_CLK IMXRT_PADCFG(0, 50, 0x1, 0, 230, 0x1) +#define IOMUXC_PAD_GPIO_EMC_B2_08_SAI2_TX_DATA IMXRT_PADCFG(0, 50, 0x2, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_EMC_B2_08_NETC_PINMUX_ETH0_TX_CLK IMXRT_PADCFG(0, 50, 0x3, 0, 213, 0x1) +#define IOMUXC_PAD_GPIO_EMC_B2_08_GPIO3_IO18 IMXRT_PADCFG(0, 50, 0x5, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_EMC_B2_08_XBAR1_XBAR_INOUT28 IMXRT_PADCFG(0, 50, 0x6, 0, 306, 0x0) +#define IOMUXC_PAD_GPIO_EMC_B2_08_LPSPI3_PCS3 IMXRT_PADCFG(0, 50, 0x8, 0, 93, 0x0) +#define IOMUXC_PAD_GPIO_EMC_B2_08_NETC_PINMUX_ETH3_TX_CLK IMXRT_PADCFG(0, 50, 0x9, 0, 229, 0x1) +#define IOMUXC_PAD_GPIO_EMC_B2_08_CCM_CLKO2 IMXRT_PADCFG(0, 50, 0xa, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_EMC_B2_08_ECAT_TX_CLK_0 IMXRT_PADCFG(0, 50, 0xc, 0, 17, 0x1) + +#define IOMUXC_PAD_GPIO_EMC_B2_09_SEMC_DATA24 IMXRT_PADCFG(0, 51, 0x0, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_EMC_B2_09_NETC_PINMUX_ETH4_RXD03 IMXRT_PADCFG(0, 51, 0x1, 0, 236, 0x1) +#define IOMUXC_PAD_GPIO_EMC_B2_09_SAI2_TX_BCLK IMXRT_PADCFG(0, 51, 0x2, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_EMC_B2_09_NETC_PINMUX_ETH0_RXD00 IMXRT_PADCFG(0, 51, 0x3, 0, 209, 0x1) +#define IOMUXC_PAD_GPIO_EMC_B2_09_GPIO3_IO19 IMXRT_PADCFG(0, 51, 0x5, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_EMC_B2_09_XBAR1_XBAR_INOUT29 IMXRT_PADCFG(0, 51, 0x6, 0, 307, 0x0) +#define IOMUXC_PAD_GPIO_EMC_B2_09_LPSPI3_PCS2 IMXRT_PADCFG(0, 51, 0x8, 0, 92, 0x0) +#define IOMUXC_PAD_GPIO_EMC_B2_09_NETC_PINMUX_ETH3_RXD00 IMXRT_PADCFG(0, 51, 0x9, 0, 225, 0x1) +#define IOMUXC_PAD_GPIO_EMC_B2_09_QTIMER1_TIMER0 IMXRT_PADCFG(0, 51, 0xa, 0, 238, 0x1) +#define IOMUXC_PAD_GPIO_EMC_B2_09_ECAT_RX_DATA0_0 IMXRT_PADCFG(0, 51, 0xc, 0, 5, 0x1) + +#define IOMUXC_PAD_GPIO_EMC_B2_10_SEMC_DATA25 IMXRT_PADCFG(0, 52, 0x0, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_EMC_B2_10_NETC_PINMUX_ETH4_RXD02 IMXRT_PADCFG(0, 52, 0x1, 0, 235, 0x1) +#define IOMUXC_PAD_GPIO_EMC_B2_10_SAI2_TX_SYNC IMXRT_PADCFG(0, 52, 0x2, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_EMC_B2_10_NETC_PINMUX_ETH0_RXD01 IMXRT_PADCFG(0, 52, 0x3, 0, 210, 0x1) +#define IOMUXC_PAD_GPIO_EMC_B2_10_GPIO3_IO20 IMXRT_PADCFG(0, 52, 0x5, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_EMC_B2_10_XBAR1_XBAR_INOUT30 IMXRT_PADCFG(0, 52, 0x6, 0, 308, 0x0) +#define IOMUXC_PAD_GPIO_EMC_B2_10_LPSPI3_PCS1 IMXRT_PADCFG(0, 52, 0x8, 0, 91, 0x0) +#define IOMUXC_PAD_GPIO_EMC_B2_10_NETC_PINMUX_ETH3_RXD01 IMXRT_PADCFG(0, 52, 0x9, 0, 226, 0x1) +#define IOMUXC_PAD_GPIO_EMC_B2_10_QTIMER1_TIMER1 IMXRT_PADCFG(0, 52, 0xa, 0, 239, 0x1) +#define IOMUXC_PAD_GPIO_EMC_B2_10_ECAT_RX_DATA1_0 IMXRT_PADCFG(0, 52, 0xc, 0, 7, 0x1) + +#define IOMUXC_PAD_GPIO_EMC_B2_11_SEMC_DATA26 IMXRT_PADCFG(0, 53, 0x0, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_EMC_B2_11_NETC_PINMUX_ETH4_TXD03 IMXRT_PADCFG(0, 53, 0x1, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_EMC_B2_11_SPDIF_OUT IMXRT_PADCFG(0, 53, 0x2, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_EMC_B2_11_NETC_PINMUX_ETH0_RX_DV IMXRT_PADCFG(0, 53, 0x3, 0, 207, 0x1) +#define IOMUXC_PAD_GPIO_EMC_B2_11_LPSPI5_PCS3 IMXRT_PADCFG(0, 53, 0x4, 0, 104, 0x0) +#define IOMUXC_PAD_GPIO_EMC_B2_11_GPIO3_IO21 IMXRT_PADCFG(0, 53, 0x5, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_EMC_B2_11_XBAR1_XBAR_INOUT31 IMXRT_PADCFG(0, 53, 0x6, 0, 309, 0x0) +#define IOMUXC_PAD_GPIO_EMC_B2_11_SAI3_RX_SYNC IMXRT_PADCFG(0, 53, 0x8, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_EMC_B2_11_NETC_PINMUX_ETH3_RX_DV IMXRT_PADCFG(0, 53, 0x9, 0, 223, 0x1) +#define IOMUXC_PAD_GPIO_EMC_B2_11_QTIMER1_TIMER2 IMXRT_PADCFG(0, 53, 0xa, 0, 240, 0x0) +#define IOMUXC_PAD_GPIO_EMC_B2_11_ECAT_RX_DV_0 IMXRT_PADCFG(0, 53, 0xc, 0, 13, 0x1) + +#define IOMUXC_PAD_GPIO_EMC_B2_12_SEMC_DATA27 IMXRT_PADCFG(0, 54, 0x0, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_EMC_B2_12_NETC_PINMUX_ETH4_TXD02 IMXRT_PADCFG(0, 54, 0x1, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_EMC_B2_12_SPDIF_IN IMXRT_PADCFG(0, 54, 0x2, 0, 282, 0x0) +#define IOMUXC_PAD_GPIO_EMC_B2_12_NETC_PINMUX_ETH0_RX_ER IMXRT_PADCFG(0, 54, 0x3, 0, 208, 0x1) +#define IOMUXC_PAD_GPIO_EMC_B2_12_LPSPI5_PCS2 IMXRT_PADCFG(0, 54, 0x4, 0, 103, 0x0) +#define IOMUXC_PAD_GPIO_EMC_B2_12_GPIO3_IO22 IMXRT_PADCFG(0, 54, 0x5, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_EMC_B2_12_XBAR1_XBAR_INOUT32 IMXRT_PADCFG(0, 54, 0x6, 0, 310, 0x0) +#define IOMUXC_PAD_GPIO_EMC_B2_12_SAI3_RX_BCLK IMXRT_PADCFG(0, 54, 0x8, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_EMC_B2_12_NETC_PINMUX_ETH3_RX_ER IMXRT_PADCFG(0, 54, 0x9, 0, 224, 0x1) +#define IOMUXC_PAD_GPIO_EMC_B2_12_QTIMER1_TIMER3 IMXRT_PADCFG(0, 54, 0xa, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_EMC_B2_12_ECAT_PT0_RX_ER IMXRT_PADCFG(0, 54, 0xc, 0, 15, 0x1) + +#define IOMUXC_PAD_GPIO_EMC_B2_13_SEMC_DATA28 IMXRT_PADCFG(0, 55, 0x0, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_EMC_B2_13_NETC_PINMUX_ETH4_TXD00 IMXRT_PADCFG(0, 55, 0x1, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_EMC_B2_13_LPUART11_TX IMXRT_PADCFG(0, 55, 0x2, 0, 118, 0x0) +#define IOMUXC_PAD_GPIO_EMC_B2_13_NETC_PINMUX_ETH0_TXD03 IMXRT_PADCFG(0, 55, 0x3, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_EMC_B2_13_LPSPI5_PCS1 IMXRT_PADCFG(0, 55, 0x4, 0, 102, 0x1) +#define IOMUXC_PAD_GPIO_EMC_B2_13_GPIO3_IO23 IMXRT_PADCFG(0, 55, 0x5, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_EMC_B2_13_XBAR1_XBAR_INOUT33 IMXRT_PADCFG(0, 55, 0x6, 0, 311, 0x0) +#define IOMUXC_PAD_GPIO_EMC_B2_13_SAI3_RX_DATA IMXRT_PADCFG(0, 55, 0x8, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_EMC_B2_13_NETC_PINMUX_ETH3_TXD03 IMXRT_PADCFG(0, 55, 0x9, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_EMC_B2_13_QTIMER2_TIMER0 IMXRT_PADCFG(0, 55, 0xa, 0, 241, 0x1) +#define IOMUXC_PAD_GPIO_EMC_B2_13_ECAT_TX_DATA0_1 IMXRT_PADCFG(0, 55, 0xc, 0, IMXRT_PADCFG_NO_DSYIDX, 0) + +#define IOMUXC_PAD_GPIO_EMC_B2_14_SEMC_DATA29 IMXRT_PADCFG(0, 56, 0x0, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_EMC_B2_14_NETC_PINMUX_ETH4_TXD01 IMXRT_PADCFG(0, 56, 0x1, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_EMC_B2_14_LPUART11_RX IMXRT_PADCFG(0, 56, 0x2, 0, 117, 0x0) +#define IOMUXC_PAD_GPIO_EMC_B2_14_NETC_PINMUX_ETH0_TXD02 IMXRT_PADCFG(0, 56, 0x3, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_EMC_B2_14_LPUART5_DSR_B IMXRT_PADCFG(0, 56, 0x4, 0, 125, 0x0) +#define IOMUXC_PAD_GPIO_EMC_B2_14_GPIO3_IO24 IMXRT_PADCFG(0, 56, 0x5, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_EMC_B2_14_XBAR1_XBAR_INOUT34 IMXRT_PADCFG(0, 56, 0x6, 0, 312, 0x0) +#define IOMUXC_PAD_GPIO_EMC_B2_14_SAI3_TX_DATA IMXRT_PADCFG(0, 56, 0x8, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_EMC_B2_14_NETC_PINMUX_ETH3_TXD02 IMXRT_PADCFG(0, 56, 0x9, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_EMC_B2_14_QTIMER2_TIMER1 IMXRT_PADCFG(0, 56, 0xa, 0, 242, 0x1) +#define IOMUXC_PAD_GPIO_EMC_B2_14_ECAT_TX_DATA1_1 IMXRT_PADCFG(0, 56, 0xc, 0, IMXRT_PADCFG_NO_DSYIDX, 0) + +#define IOMUXC_PAD_GPIO_EMC_B2_15_SEMC_DATA30 IMXRT_PADCFG(0, 57, 0x0, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_EMC_B2_15_NETC_PINMUX_ETH4_TX_EN IMXRT_PADCFG(0, 57, 0x1, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_EMC_B2_15_LPUART11_CTS_B IMXRT_PADCFG(0, 57, 0x2, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_EMC_B2_15_NETC_PINMUX_ETH0_RX_CLK IMXRT_PADCFG(0, 57, 0x3, 0, 206, 0x1) +#define IOMUXC_PAD_GPIO_EMC_B2_15_LPUART5_DCD_B IMXRT_PADCFG(0, 57, 0x4, 0, 124, 0x0) +#define IOMUXC_PAD_GPIO_EMC_B2_15_GPIO3_IO25 IMXRT_PADCFG(0, 57, 0x5, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_EMC_B2_15_XBAR1_XBAR_INOUT35 IMXRT_PADCFG(0, 57, 0x6, 0, 313, 0x0) +#define IOMUXC_PAD_GPIO_EMC_B2_15_SAI3_TX_BCLK IMXRT_PADCFG(0, 57, 0x8, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_EMC_B2_15_NETC_PINMUX_ETH3_RX_CLK IMXRT_PADCFG(0, 57, 0x9, 0, 222, 0x1) +#define IOMUXC_PAD_GPIO_EMC_B2_15_QTIMER2_TIMER2 IMXRT_PADCFG(0, 57, 0xa, 0, 243, 0x0) +#define IOMUXC_PAD_GPIO_EMC_B2_15_ECAT_TX_EN_1 IMXRT_PADCFG(0, 57, 0xc, 0, IMXRT_PADCFG_NO_DSYIDX, 0) + +#define IOMUXC_PAD_GPIO_EMC_B2_16_SEMC_DATA31 IMXRT_PADCFG(0, 58, 0x0, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_EMC_B2_16_NETC_PINMUX_ETH4_TX_CLK IMXRT_PADCFG(0, 58, 0x1, 0, 237, 0x1) +#define IOMUXC_PAD_GPIO_EMC_B2_16_LPUART11_RTS_B IMXRT_PADCFG(0, 58, 0x2, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_EMC_B2_16_NETC_PINMUX_ETH0_RXD02 IMXRT_PADCFG(0, 58, 0x3, 0, 211, 0x1) +#define IOMUXC_PAD_GPIO_EMC_B2_16_LPUART5_DTR_B IMXRT_PADCFG(0, 58, 0x4, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_EMC_B2_16_GPIO3_IO26 IMXRT_PADCFG(0, 58, 0x5, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_EMC_B2_16_XBAR1_XBAR_INOUT14 IMXRT_PADCFG(0, 58, 0x6, 0, 293, 0x1) +#define IOMUXC_PAD_GPIO_EMC_B2_16_SAI3_TX_SYNC IMXRT_PADCFG(0, 58, 0x8, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_EMC_B2_16_NETC_PINMUX_ETH3_RXD02 IMXRT_PADCFG(0, 58, 0x9, 0, 227, 0x1) +#define IOMUXC_PAD_GPIO_EMC_B2_16_QTIMER2_TIMER3 IMXRT_PADCFG(0, 58, 0xa, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_EMC_B2_16_ECAT_TX_CLK_1 IMXRT_PADCFG(0, 58, 0xc, 0, 18, 0x1) + +#define IOMUXC_PAD_GPIO_EMC_B2_17_SEMC_DM03 IMXRT_PADCFG(0, 59, 0x0, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_EMC_B2_17_NETC_PINMUX_ETH4_RXD00 IMXRT_PADCFG(0, 59, 0x1, 0, 233, 0x1) +#define IOMUXC_PAD_GPIO_EMC_B2_17_LPUART5_TX IMXRT_PADCFG(0, 59, 0x2, 0, 128, 0x2) +#define IOMUXC_PAD_GPIO_EMC_B2_17_NETC_PINMUX_ETH0_RXD03 IMXRT_PADCFG(0, 59, 0x3, 0, 212, 0x1) +#define IOMUXC_PAD_GPIO_EMC_B2_17_GPIO3_IO27 IMXRT_PADCFG(0, 59, 0x5, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_EMC_B2_17_XBAR1_XBAR_INOUT15 IMXRT_PADCFG(0, 59, 0x6, 0, 294, 0x1) +#define IOMUXC_PAD_GPIO_EMC_B2_17_SAI3_MCLK IMXRT_PADCFG(0, 59, 0x8, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_EMC_B2_17_NETC_PINMUX_ETH3_RXD03 IMXRT_PADCFG(0, 59, 0x9, 0, 228, 0x1) +#define IOMUXC_PAD_GPIO_EMC_B2_17_QTIMER3_TIMER0 IMXRT_PADCFG(0, 59, 0xa, 0, 244, 0x1) +#define IOMUXC_PAD_GPIO_EMC_B2_17_ECAT_RX_DATA0_1 IMXRT_PADCFG(0, 59, 0xc, 0, 6, 0x1) + +#define IOMUXC_PAD_GPIO_EMC_B2_18_SEMC_DQS4 IMXRT_PADCFG(0, 60, 0x0, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_EMC_B2_18_NETC_PINMUX_ETH4_RXD01 IMXRT_PADCFG(0, 60, 0x1, 0, 234, 0x1) +#define IOMUXC_PAD_GPIO_EMC_B2_18_LPUART5_RX IMXRT_PADCFG(0, 60, 0x2, 0, 127, 0x2) +#define IOMUXC_PAD_GPIO_EMC_B2_18_NETC_PINMUX_ETH0_TX_ER IMXRT_PADCFG(0, 60, 0x3, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_EMC_B2_18_GPIO3_IO28 IMXRT_PADCFG(0, 60, 0x5, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_EMC_B2_18_XBAR1_XBAR_INOUT16 IMXRT_PADCFG(0, 60, 0x6, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_EMC_B2_18_EWM_EWM_OUT_B IMXRT_PADCFG(0, 60, 0x8, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_EMC_B2_18_NETC_PINMUX_ETH3_TX_ER IMXRT_PADCFG(0, 60, 0x9, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_EMC_B2_18_QTIMER3_TIMER1 IMXRT_PADCFG(0, 60, 0xa, 0, 245, 0x1) +#define IOMUXC_PAD_GPIO_EMC_B2_18_ECAT_RX_DATA1_1 IMXRT_PADCFG(0, 60, 0xc, 0, 8, 0x1) + +#define IOMUXC_PAD_GPIO_EMC_B2_19_SEMC_CLKX00 IMXRT_PADCFG(0, 61, 0x0, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_EMC_B2_19_NETC_PINMUX_ETH4_RX_DV IMXRT_PADCFG(0, 61, 0x1, 0, 231, 0x1) +#define IOMUXC_PAD_GPIO_EMC_B2_19_LPUART5_CTS_B IMXRT_PADCFG(0, 61, 0x2, 0, 123, 0x1) +#define IOMUXC_PAD_GPIO_EMC_B2_19_NETC_ETH0_CRS IMXRT_PADCFG(0, 61, 0x3, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_EMC_B2_19_NETC_EMDC IMXRT_PADCFG(0, 61, 0x4, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_EMC_B2_19_GPIO3_IO29 IMXRT_PADCFG(0, 61, 0x5, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_EMC_B2_19_XBAR1_XBAR_INOUT36 IMXRT_PADCFG(0, 61, 0x6, 0, 314, 0x0) +#define IOMUXC_PAD_GPIO_EMC_B2_19_LPI2C3_SCL IMXRT_PADCFG(0, 61, 0x8, 0, 82, 0x1) +#define IOMUXC_PAD_GPIO_EMC_B2_19_NETC_ETH3_SLV_MDC IMXRT_PADCFG(0, 61, 0x9, 0, 197, 0x2) +#define IOMUXC_PAD_GPIO_EMC_B2_19_QTIMER3_TIMER2 IMXRT_PADCFG(0, 61, 0xa, 0, 246, 0x0) +#define IOMUXC_PAD_GPIO_EMC_B2_19_ECAT_RX_DV_1 IMXRT_PADCFG(0, 61, 0xc, 0, 14, 0x1) + +#define IOMUXC_PAD_GPIO_EMC_B2_20_SEMC_CLKX01 IMXRT_PADCFG(0, 62, 0x0, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_EMC_B2_20_NETC_PINMUX_ETH4_RX_ER IMXRT_PADCFG(0, 62, 0x1, 0, 232, 0x1) +#define IOMUXC_PAD_GPIO_EMC_B2_20_LPUART5_RTS_B IMXRT_PADCFG(0, 62, 0x2, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_EMC_B2_20_NETC_ETH0_COL IMXRT_PADCFG(0, 62, 0x3, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_EMC_B2_20_NETC_EMDIO IMXRT_PADCFG(0, 62, 0x4, 0, 190, 0x3) +#define IOMUXC_PAD_GPIO_EMC_B2_20_GPIO3_IO30 IMXRT_PADCFG(0, 62, 0x5, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_EMC_B2_20_XBAR1_XBAR_INOUT37 IMXRT_PADCFG(0, 62, 0x6, 0, 315, 0x0) +#define IOMUXC_PAD_GPIO_EMC_B2_20_LPI2C3_SDA IMXRT_PADCFG(0, 62, 0x8, 0, 83, 0x1) +#define IOMUXC_PAD_GPIO_EMC_B2_20_NETC_ETH3_SLV_MDIO IMXRT_PADCFG(0, 62, 0x9, 0, 198, 0x2) +#define IOMUXC_PAD_GPIO_EMC_B2_20_QTIMER3_TIMER3 IMXRT_PADCFG(0, 62, 0xa, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_EMC_B2_20_ECAT_RX_ER_1 IMXRT_PADCFG(0, 62, 0xc, 0, 16, 0x1) + +#define IOMUXC_PAD_GPIO_AD_00_CAN2_TX IMXRT_PADCFG(0, 63, 0x1, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_AD_00_MIC_CLK IMXRT_PADCFG(0, 63, 0x2, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_AD_00_GPT2_CAPTURE1 IMXRT_PADCFG(0, 63, 0x3, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_AD_00_FLEXPWM1_PWMA00 IMXRT_PADCFG(0, 63, 0x4, 0, 21, 0x2) +#define IOMUXC_PAD_GPIO_AD_00_GPIO4_IO00 IMXRT_PADCFG(0, 63, 0x5, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_AD_00_SINC1_MOD_CLK0 IMXRT_PADCFG(0, 63, 0x6, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_AD_00_FLEXIO2_FLEXIO00 IMXRT_PADCFG(0, 63, 0x8, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_AD_00_QTIMER4_TIMER0 IMXRT_PADCFG(0, 63, 0x9, 0, 247, 0x1) + +#define IOMUXC_PAD_GPIO_AD_01_CAN2_RX IMXRT_PADCFG(0, 64, 0x1, 0, 1, 0x0) +#define IOMUXC_PAD_GPIO_AD_01_MIC_BITSTREAM00 IMXRT_PADCFG(0, 64, 0x2, 0, 140, 0x0) +#define IOMUXC_PAD_GPIO_AD_01_GPT2_CAPTURE2 IMXRT_PADCFG(0, 64, 0x3, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_AD_01_FLEXPWM1_PWMB00 IMXRT_PADCFG(0, 64, 0x4, 0, 24, 0x2) +#define IOMUXC_PAD_GPIO_AD_01_GPIO4_IO01 IMXRT_PADCFG(0, 64, 0x5, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_AD_01_SINC1_MOD_CLK1 IMXRT_PADCFG(0, 64, 0x6, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_AD_01_FLEXIO2_FLEXIO01 IMXRT_PADCFG(0, 64, 0x8, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_AD_01_QTIMER4_TIMER1 IMXRT_PADCFG(0, 64, 0x9, 0, 248, 0x1) + +#define IOMUXC_PAD_GPIO_AD_02_MIC_BITSTREAM01 IMXRT_PADCFG(0, 65, 0x2, 0, 141, 0x0) +#define IOMUXC_PAD_GPIO_AD_02_GPT2_COMPARE1 IMXRT_PADCFG(0, 65, 0x3, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_AD_02_FLEXPWM1_PWMA01 IMXRT_PADCFG(0, 65, 0x4, 0, 22, 0x1) +#define IOMUXC_PAD_GPIO_AD_02_GPIO4_IO02 IMXRT_PADCFG(0, 65, 0x5, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_AD_02_SINC1_MOD_CLK2 IMXRT_PADCFG(0, 65, 0x6, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_AD_02_FLEXIO2_FLEXIO02 IMXRT_PADCFG(0, 65, 0x8, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_AD_02_QTIMER4_TIMER2 IMXRT_PADCFG(0, 65, 0x9, 0, 249, 0x0) + +#define IOMUXC_PAD_GPIO_AD_03_MIC_BITSTREAM02 IMXRT_PADCFG(0, 66, 0x2, 0, 142, 0x0) +#define IOMUXC_PAD_GPIO_AD_03_GPT2_COMPARE2 IMXRT_PADCFG(0, 66, 0x3, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_AD_03_FLEXPWM1_PWMB01 IMXRT_PADCFG(0, 66, 0x4, 0, 25, 0x1) +#define IOMUXC_PAD_GPIO_AD_03_GPIO4_IO03 IMXRT_PADCFG(0, 66, 0x5, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_AD_03_SINC1_EMCLK00 IMXRT_PADCFG(0, 66, 0x6, 0, 273, 0x0) +#define IOMUXC_PAD_GPIO_AD_03_FLEXIO2_FLEXIO03 IMXRT_PADCFG(0, 66, 0x8, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_AD_03_QTIMER4_TIMER3 IMXRT_PADCFG(0, 66, 0x9, 0, IMXRT_PADCFG_NO_DSYIDX, 0) + +#define IOMUXC_PAD_GPIO_AD_04_MIC_BITSTREAM03 IMXRT_PADCFG(0, 67, 0x2, 0, 143, 0x0) +#define IOMUXC_PAD_GPIO_AD_04_GPT2_COMPARE3 IMXRT_PADCFG(0, 67, 0x3, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_AD_04_FLEXPWM1_PWMB02 IMXRT_PADCFG(0, 67, 0x4, 0, 26, 0x1) +#define IOMUXC_PAD_GPIO_AD_04_GPIO4_IO04 IMXRT_PADCFG(0, 67, 0x5, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_AD_04_SINC1_EMBIT00 IMXRT_PADCFG(0, 67, 0x6, 0, 269, 0x0) +#define IOMUXC_PAD_GPIO_AD_04_FLEXIO2_FLEXIO04 IMXRT_PADCFG(0, 67, 0x8, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_AD_04_QTIMER5_TIMER0 IMXRT_PADCFG(0, 67, 0x9, 0, 250, 0x1) + +#define IOMUXC_PAD_GPIO_AD_05_GPT2_CLK IMXRT_PADCFG(0, 68, 0x3, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_AD_05_FLEXPWM1_PWMA02 IMXRT_PADCFG(0, 68, 0x4, 0, 23, 0x1) +#define IOMUXC_PAD_GPIO_AD_05_GPIO4_IO05 IMXRT_PADCFG(0, 68, 0x5, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_AD_05_SINC1_EMCLK01 IMXRT_PADCFG(0, 68, 0x6, 0, 274, 0x0) +#define IOMUXC_PAD_GPIO_AD_05_CCM_ENET_REF_CLK_25M IMXRT_PADCFG(0, 68, 0x7, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_AD_05_FLEXIO2_FLEXIO05 IMXRT_PADCFG(0, 68, 0x8, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_AD_05_QTIMER5_TIMER1 IMXRT_PADCFG(0, 68, 0x9, 0, 251, 0x1) + +#define IOMUXC_PAD_GPIO_AD_06_USB_OTG2_OC IMXRT_PADCFG(0, 69, 0x0, 0, 285, 0x0) +#define IOMUXC_PAD_GPIO_AD_06_CAN3_TX IMXRT_PADCFG(0, 69, 0x1, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_AD_06_FLEXPWM1_PWMX00 IMXRT_PADCFG(0, 69, 0x4, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_AD_06_GPIO4_IO06 IMXRT_PADCFG(0, 69, 0x5, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_AD_06_SINC1_EMBIT01 IMXRT_PADCFG(0, 69, 0x6, 0, 270, 0x0) +#define IOMUXC_PAD_GPIO_AD_06_FLEXIO2_FLEXIO06 IMXRT_PADCFG(0, 69, 0x8, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_AD_06_QTIMER5_TIMER2 IMXRT_PADCFG(0, 69, 0x9, 0, 252, 0x0) + +#define IOMUXC_PAD_GPIO_AD_07_USB_OTG2_PWR IMXRT_PADCFG(0, 70, 0x0, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_AD_07_CAN3_RX IMXRT_PADCFG(0, 70, 0x1, 0, 2, 0x0) +#define IOMUXC_PAD_GPIO_AD_07_FLEXPWM1_PWMX01 IMXRT_PADCFG(0, 70, 0x4, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_AD_07_GPIO4_IO07 IMXRT_PADCFG(0, 70, 0x5, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_AD_07_SINC1_EMCLK02 IMXRT_PADCFG(0, 70, 0x6, 0, 275, 0x0) +#define IOMUXC_PAD_GPIO_AD_07_FLEXIO2_FLEXIO07 IMXRT_PADCFG(0, 70, 0x8, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_AD_07_QTIMER5_TIMER3 IMXRT_PADCFG(0, 70, 0x9, 0, IMXRT_PADCFG_NO_DSYIDX, 0) + +#define IOMUXC_PAD_GPIO_AD_08_USBPHY2_OTG_ID IMXRT_PADCFG(0, 71, 0x0, 0, 288, 0x0) +#define IOMUXC_PAD_GPIO_AD_08_LPI2C5_SCL IMXRT_PADCFG(0, 71, 0x1, 0, 86, 0x0) +#define IOMUXC_PAD_GPIO_AD_08_FLEXPWM1_PWMX02 IMXRT_PADCFG(0, 71, 0x4, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_AD_08_GPIO4_IO08 IMXRT_PADCFG(0, 71, 0x5, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_AD_08_SINC1_EMBIT02 IMXRT_PADCFG(0, 71, 0x6, 0, 271, 0x0) +#define IOMUXC_PAD_GPIO_AD_08_FLEXIO2_FLEXIO08 IMXRT_PADCFG(0, 71, 0x8, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_AD_08_QTIMER6_TIMER0 IMXRT_PADCFG(0, 71, 0x9, 0, 253, 0x1) + +#define IOMUXC_PAD_GPIO_AD_09_USBPHY1_OTG_ID IMXRT_PADCFG(0, 72, 0x0, 0, 287, 0x0) +#define IOMUXC_PAD_GPIO_AD_09_LPI2C5_SDA IMXRT_PADCFG(0, 72, 0x1, 0, 87, 0x0) +#define IOMUXC_PAD_GPIO_AD_09_FLEXPWM1_PWMX03 IMXRT_PADCFG(0, 72, 0x4, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_AD_09_GPIO4_IO09 IMXRT_PADCFG(0, 72, 0x5, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_AD_09_SINC1_EMCLK03 IMXRT_PADCFG(0, 72, 0x6, 0, 276, 0x0) +#define IOMUXC_PAD_GPIO_AD_09_FLEXIO2_FLEXIO09 IMXRT_PADCFG(0, 72, 0x8, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_AD_09_QTIMER6_TIMER1 IMXRT_PADCFG(0, 72, 0x9, 0, 254, 0x1) + +#define IOMUXC_PAD_GPIO_AD_10_USB_OTG1_PWR IMXRT_PADCFG(0, 73, 0x0, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_AD_10_FLEXPWM2_PWMX00 IMXRT_PADCFG(0, 73, 0x4, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_AD_10_GPIO4_IO10 IMXRT_PADCFG(0, 73, 0x5, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_AD_10_SINC1_EMBIT03 IMXRT_PADCFG(0, 73, 0x6, 0, 272, 0x0) +#define IOMUXC_PAD_GPIO_AD_10_FLEXIO2_FLEXIO10 IMXRT_PADCFG(0, 73, 0x8, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_AD_10_QTIMER6_TIMER2 IMXRT_PADCFG(0, 73, 0x9, 0, 255, 0x0) + +#define IOMUXC_PAD_GPIO_AD_11_USB_OTG1_OC IMXRT_PADCFG(0, 74, 0x0, 0, 286, 0x0) +#define IOMUXC_PAD_GPIO_AD_11_FLEXPWM2_PWMX01 IMXRT_PADCFG(0, 74, 0x4, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_AD_11_GPIO4_IO11 IMXRT_PADCFG(0, 74, 0x5, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_AD_11_SINC_FILTER_GLUE1_BREAK IMXRT_PADCFG(0, 74, 0x6, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_AD_11_FLEXIO2_FLEXIO11 IMXRT_PADCFG(0, 74, 0x8, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_AD_11_QTIMER6_TIMER3 IMXRT_PADCFG(0, 74, 0x9, 0, IMXRT_PADCFG_NO_DSYIDX, 0) + +#define IOMUXC_PAD_GPIO_AD_12_SPDIF_LOCK IMXRT_PADCFG(0, 75, 0x0, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_AD_12_LPI2C5_SCLS IMXRT_PADCFG(0, 75, 0x1, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_AD_12_GPT1_CAPTURE1 IMXRT_PADCFG(0, 75, 0x2, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_AD_12_KPP_ROW07 IMXRT_PADCFG(0, 75, 0x3, 0, 81, 0x1) +#define IOMUXC_PAD_GPIO_AD_12_FLEXPWM2_PWMX02 IMXRT_PADCFG(0, 75, 0x4, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_AD_12_GPIO4_IO12 IMXRT_PADCFG(0, 75, 0x5, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_AD_12_XBAR1_XBAR_INOUT18 IMXRT_PADCFG(0, 75, 0x6, 0, 296, 0x0) +#define IOMUXC_PAD_GPIO_AD_12_EWM_EWM_OUT_B IMXRT_PADCFG(0, 75, 0x7, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_AD_12_FLEXIO2_FLEXIO12 IMXRT_PADCFG(0, 75, 0x8, 0, IMXRT_PADCFG_NO_DSYIDX, 0) + +#define IOMUXC_PAD_GPIO_AD_13_SPDIF_SR_CLK IMXRT_PADCFG(0, 76, 0x0, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_AD_13_LPI2C5_SDAS IMXRT_PADCFG(0, 76, 0x1, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_AD_13_GPT1_CAPTURE2 IMXRT_PADCFG(0, 76, 0x2, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_AD_13_KPP_COL07 IMXRT_PADCFG(0, 76, 0x3, 0, 73, 0x1) +#define IOMUXC_PAD_GPIO_AD_13_FLEXPWM2_PWMX03 IMXRT_PADCFG(0, 76, 0x4, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_AD_13_GPIO4_IO13 IMXRT_PADCFG(0, 76, 0x5, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_AD_13_LPUART3_TX IMXRT_PADCFG(0, 76, 0x6, 0, 121, 0x1) +#define IOMUXC_PAD_GPIO_AD_13_USDHC2_CD_B IMXRT_PADCFG(0, 76, 0x7, 0, 291, 0x1) +#define IOMUXC_PAD_GPIO_AD_13_FLEXIO2_FLEXIO13 IMXRT_PADCFG(0, 76, 0x8, 0, IMXRT_PADCFG_NO_DSYIDX, 0) + +#define IOMUXC_PAD_GPIO_AD_14_SPDIF_EXT_CLK IMXRT_PADCFG(0, 77, 0x0, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_AD_14_LPI2C5_HREQ IMXRT_PADCFG(0, 77, 0x1, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_AD_14_GPT1_COMPARE1 IMXRT_PADCFG(0, 77, 0x2, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_AD_14_KPP_ROW06 IMXRT_PADCFG(0, 77, 0x3, 0, 80, 0x1) +#define IOMUXC_PAD_GPIO_AD_14_FLEXPWM3_PWMX00 IMXRT_PADCFG(0, 77, 0x4, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_AD_14_GPIO4_IO14 IMXRT_PADCFG(0, 77, 0x5, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_AD_14_LPUART3_RX IMXRT_PADCFG(0, 77, 0x6, 0, 120, 0x1) +#define IOMUXC_PAD_GPIO_AD_14_USDHC2_WP IMXRT_PADCFG(0, 77, 0x7, 0, 292, 0x1) +#define IOMUXC_PAD_GPIO_AD_14_FLEXIO2_FLEXIO14 IMXRT_PADCFG(0, 77, 0x8, 0, IMXRT_PADCFG_NO_DSYIDX, 0) + +#define IOMUXC_PAD_GPIO_AD_15_SPDIF_IN IMXRT_PADCFG(0, 78, 0x0, 0, 282, 0x1) +#define IOMUXC_PAD_GPIO_AD_15_LPUART10_TX IMXRT_PADCFG(0, 78, 0x1, 0, 116, 0x0) +#define IOMUXC_PAD_GPIO_AD_15_GPT1_COMPARE2 IMXRT_PADCFG(0, 78, 0x2, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_AD_15_KPP_COL06 IMXRT_PADCFG(0, 78, 0x3, 0, 72, 0x1) +#define IOMUXC_PAD_GPIO_AD_15_FLEXPWM3_PWMX01 IMXRT_PADCFG(0, 78, 0x4, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_AD_15_GPIO4_IO15 IMXRT_PADCFG(0, 78, 0x5, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_AD_15_LPUART3_CTS_B IMXRT_PADCFG(0, 78, 0x6, 0, 119, 0x1) +#define IOMUXC_PAD_GPIO_AD_15_LPSPI3_PCS1 IMXRT_PADCFG(0, 78, 0x7, 0, 91, 0x1) +#define IOMUXC_PAD_GPIO_AD_15_FLEXIO2_FLEXIO15 IMXRT_PADCFG(0, 78, 0x8, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_AD_15_CAN1_TX IMXRT_PADCFG(0, 78, 0x9, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_AD_15_ECAT_CLK_ECAT_CLK25 IMXRT_PADCFG(0, 78, 0xc, 0, IMXRT_PADCFG_NO_DSYIDX, 0) + +#define IOMUXC_PAD_GPIO_AD_16_SPDIF_OUT IMXRT_PADCFG(0, 79, 0x0, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_AD_16_LPUART10_RX IMXRT_PADCFG(0, 79, 0x1, 0, 115, 0x0) +#define IOMUXC_PAD_GPIO_AD_16_GPT1_COMPARE3 IMXRT_PADCFG(0, 79, 0x2, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_AD_16_KPP_ROW05 IMXRT_PADCFG(0, 79, 0x3, 0, 79, 0x1) +#define IOMUXC_PAD_GPIO_AD_16_FLEXPWM3_PWMX02 IMXRT_PADCFG(0, 79, 0x4, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_AD_16_GPIO4_IO16 IMXRT_PADCFG(0, 79, 0x5, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_AD_16_LPUART3_RTS_B IMXRT_PADCFG(0, 79, 0x6, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_AD_16_LPSPI3_SCK IMXRT_PADCFG(0, 79, 0x7, 0, 94, 0x1) +#define IOMUXC_PAD_GPIO_AD_16_FLEXIO2_FLEXIO16 IMXRT_PADCFG(0, 79, 0x8, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_AD_16_CAN1_RX IMXRT_PADCFG(0, 79, 0x9, 0, 0, 0x0) +#define IOMUXC_PAD_GPIO_AD_16_ECAT_LINK_0 IMXRT_PADCFG(0, 79, 0xc, 0, IMXRT_PADCFG_NO_DSYIDX, 0) + +#define IOMUXC_PAD_GPIO_AD_17_SAI4_MCLK IMXRT_PADCFG(0, 80, 0x0, 0, 260, 0x0) +#define IOMUXC_PAD_GPIO_AD_17_ACMP1_CMPO IMXRT_PADCFG(0, 80, 0x1, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_AD_17_GPT1_CLK IMXRT_PADCFG(0, 80, 0x2, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_AD_17_KPP_COL05 IMXRT_PADCFG(0, 80, 0x3, 0, 71, 0x1) +#define IOMUXC_PAD_GPIO_AD_17_FLEXPWM3_PWMX03 IMXRT_PADCFG(0, 80, 0x4, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_AD_17_GPIO4_IO17 IMXRT_PADCFG(0, 80, 0x5, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_AD_17_I3C2_PUR IMXRT_PADCFG(0, 80, 0x6, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_AD_17_LPSPI3_PCS0 IMXRT_PADCFG(0, 80, 0x7, 0, 90, 0x1) +#define IOMUXC_PAD_GPIO_AD_17_FLEXIO2_FLEXIO17 IMXRT_PADCFG(0, 80, 0x8, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_AD_17_LPI2C3_HREQ IMXRT_PADCFG(0, 80, 0x9, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_AD_17_ECAT_LINK_1 IMXRT_PADCFG(0, 80, 0xc, 0, IMXRT_PADCFG_NO_DSYIDX, 0) + +#define IOMUXC_PAD_GPIO_AD_18_SAI4_RX_SYNC IMXRT_PADCFG(0, 81, 0x0, 0, 264, 0x0) +#define IOMUXC_PAD_GPIO_AD_18_ACMP2_CMPO IMXRT_PADCFG(0, 81, 0x1, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_AD_18_LPUART5_RI_B IMXRT_PADCFG(0, 81, 0x2, 0, 126, 0x0) +#define IOMUXC_PAD_GPIO_AD_18_KPP_ROW04 IMXRT_PADCFG(0, 81, 0x3, 0, 78, 0x1) +#define IOMUXC_PAD_GPIO_AD_18_FLEXPWM4_PWMX00 IMXRT_PADCFG(0, 81, 0x4, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_AD_18_GPIO4_IO18 IMXRT_PADCFG(0, 81, 0x5, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_AD_18_I3C2_SCL IMXRT_PADCFG(0, 81, 0x6, 0, 64, 0x0) +#define IOMUXC_PAD_GPIO_AD_18_LPSPI3_SDO IMXRT_PADCFG(0, 81, 0x7, 0, 96, 0x1) +#define IOMUXC_PAD_GPIO_AD_18_FLEXIO2_FLEXIO18 IMXRT_PADCFG(0, 81, 0x8, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_AD_18_LPI2C3_SCL IMXRT_PADCFG(0, 81, 0x9, 0, 82, 0x2) +#define IOMUXC_PAD_GPIO_AD_18_ECAT_PROM_CLK IMXRT_PADCFG(0, 81, 0xc, 0, IMXRT_PADCFG_NO_DSYIDX, 0) + +#define IOMUXC_PAD_GPIO_AD_19_SAI4_RX_BCLK IMXRT_PADCFG(0, 82, 0x0, 0, 261, 0x0) +#define IOMUXC_PAD_GPIO_AD_19_ACMP3_CMPO IMXRT_PADCFG(0, 82, 0x1, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_AD_19_XBAR1_XBAR_INOUT19 IMXRT_PADCFG(0, 82, 0x2, 0, 297, 0x0) +#define IOMUXC_PAD_GPIO_AD_19_KPP_COL04 IMXRT_PADCFG(0, 82, 0x3, 0, 70, 0x1) +#define IOMUXC_PAD_GPIO_AD_19_FLEXPWM4_PWMX01 IMXRT_PADCFG(0, 82, 0x4, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_AD_19_GPIO4_IO19 IMXRT_PADCFG(0, 82, 0x5, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_AD_19_I3C2_SDA IMXRT_PADCFG(0, 82, 0x6, 0, 65, 0x0) +#define IOMUXC_PAD_GPIO_AD_19_LPSPI3_SDI IMXRT_PADCFG(0, 82, 0x7, 0, 95, 0x1) +#define IOMUXC_PAD_GPIO_AD_19_FLEXIO2_FLEXIO19 IMXRT_PADCFG(0, 82, 0x8, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_AD_19_LPI2C3_SDA IMXRT_PADCFG(0, 82, 0x9, 0, 83, 0x2) +#define IOMUXC_PAD_GPIO_AD_19_ECAT_PROM_DATA IMXRT_PADCFG(0, 82, 0xc, 0, 20, 0x0) + +#define IOMUXC_PAD_GPIO_AD_20_SAI4_RX_DATA00 IMXRT_PADCFG(0, 83, 0x0, 0, 262, 0x0) +#define IOMUXC_PAD_GPIO_AD_20_ACMP4_CMPO IMXRT_PADCFG(0, 83, 0x1, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_AD_20_LPIT2_TRIGGER00 IMXRT_PADCFG(0, 83, 0x2, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_AD_20_SINC1_EMCLK00 IMXRT_PADCFG(0, 83, 0x3, 0, 273, 0x1) +#define IOMUXC_PAD_GPIO_AD_20_FLEXPWM4_PWMX02 IMXRT_PADCFG(0, 83, 0x4, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_AD_20_GPIO4_IO20 IMXRT_PADCFG(0, 83, 0x5, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_AD_20_NETC_TMR_TRIG1 IMXRT_PADCFG(0, 83, 0x6, 0, 203, 0x0) +#define IOMUXC_PAD_GPIO_AD_20_NETC_1588_CLK IMXRT_PADCFG(0, 83, 0x7, 0, 205, 0x0) +#define IOMUXC_PAD_GPIO_AD_20_FLEXIO2_FLEXIO20 IMXRT_PADCFG(0, 83, 0x8, 0, IMXRT_PADCFG_NO_DSYIDX, 0) + +#define IOMUXC_PAD_GPIO_AD_21_SAI4_TX_DATA00 IMXRT_PADCFG(0, 84, 0x0, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_AD_21_LPIT2_TRIGGER01 IMXRT_PADCFG(0, 84, 0x2, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_AD_21_SINC1_EMBIT00 IMXRT_PADCFG(0, 84, 0x3, 0, 269, 0x1) +#define IOMUXC_PAD_GPIO_AD_21_FLEXPWM4_PWMX03 IMXRT_PADCFG(0, 84, 0x4, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_AD_21_GPIO4_IO21 IMXRT_PADCFG(0, 84, 0x5, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_AD_21_NETC_TMR_TRIG2 IMXRT_PADCFG(0, 84, 0x6, 0, 204, 0x0) +#define IOMUXC_PAD_GPIO_AD_21_NETC_TMR_GCLK IMXRT_PADCFG(0, 84, 0x7, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_AD_21_FLEXIO2_FLEXIO21 IMXRT_PADCFG(0, 84, 0x8, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_AD_21_ECAT_LED_RUN IMXRT_PADCFG(0, 84, 0xc, 0, IMXRT_PADCFG_NO_DSYIDX, 0) + +#define IOMUXC_PAD_GPIO_AD_22_SAI4_TX_BCLK IMXRT_PADCFG(0, 85, 0x0, 0, 265, 0x0) +#define IOMUXC_PAD_GPIO_AD_22_LPIT2_TRIGGER02 IMXRT_PADCFG(0, 85, 0x2, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_AD_22_SINC1_EMCLK01 IMXRT_PADCFG(0, 85, 0x3, 0, 274, 0x1) +#define IOMUXC_PAD_GPIO_AD_22_GPIO4_IO22 IMXRT_PADCFG(0, 85, 0x5, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_AD_22_NETC_TMR_ALARM1 IMXRT_PADCFG(0, 85, 0x7, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_AD_22_FLEXIO2_FLEXIO22 IMXRT_PADCFG(0, 85, 0x8, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_AD_22_ECAT_LED_ERR IMXRT_PADCFG(0, 85, 0xc, 0, IMXRT_PADCFG_NO_DSYIDX, 0) + +#define IOMUXC_PAD_GPIO_AD_23_SAI4_TX_SYNC IMXRT_PADCFG(0, 86, 0x0, 0, 266, 0x0) +#define IOMUXC_PAD_GPIO_AD_23_LPIT2_TRIGGER03 IMXRT_PADCFG(0, 86, 0x2, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_AD_23_SINC1_EMBIT01 IMXRT_PADCFG(0, 86, 0x3, 0, 270, 0x1) +#define IOMUXC_PAD_GPIO_AD_23_GPIO4_IO23 IMXRT_PADCFG(0, 86, 0x5, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_AD_23_NETC_TMR_ALARM2 IMXRT_PADCFG(0, 86, 0x7, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_AD_23_FLEXIO2_FLEXIO23 IMXRT_PADCFG(0, 86, 0x8, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_AD_23_ECAT_LED_STATE_RUN IMXRT_PADCFG(0, 86, 0xc, 0, IMXRT_PADCFG_NO_DSYIDX, 0) + +#define IOMUXC_PAD_GPIO_AD_24_LPUART6_TX IMXRT_PADCFG(0, 87, 0x0, 0, 134, 0x1) +#define IOMUXC_PAD_GPIO_AD_24_LPI2C4_SCL IMXRT_PADCFG(0, 87, 0x1, 0, 84, 0x0) +#define IOMUXC_PAD_GPIO_AD_24_SINC2_MOD_CLK1 IMXRT_PADCFG(0, 87, 0x3, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_AD_24_FLEXPWM2_PWMA00 IMXRT_PADCFG(0, 87, 0x4, 0, 27, 0x1) +#define IOMUXC_PAD_GPIO_AD_24_GPIO4_IO24 IMXRT_PADCFG(0, 87, 0x5, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_AD_24_NETC_TMR_TRIG1 IMXRT_PADCFG(0, 87, 0x7, 0, 203, 0x1) +#define IOMUXC_PAD_GPIO_AD_24_FLEXIO2_FLEXIO24 IMXRT_PADCFG(0, 87, 0x8, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_AD_24_ECAT_LINK_ACT00 IMXRT_PADCFG(0, 87, 0xc, 0, IMXRT_PADCFG_NO_DSYIDX, 0) + +#define IOMUXC_PAD_GPIO_AD_25_LPUART6_RX IMXRT_PADCFG(0, 88, 0x0, 0, 133, 0x1) +#define IOMUXC_PAD_GPIO_AD_25_LPI2C4_SDA IMXRT_PADCFG(0, 88, 0x1, 0, 85, 0x0) +#define IOMUXC_PAD_GPIO_AD_25_LPSPI5_PCS3 IMXRT_PADCFG(0, 88, 0x2, 0, 104, 0x1) +#define IOMUXC_PAD_GPIO_AD_25_SINC2_MOD_CLK2 IMXRT_PADCFG(0, 88, 0x3, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_AD_25_FLEXPWM2_PWMB00 IMXRT_PADCFG(0, 88, 0x4, 0, 30, 0x1) +#define IOMUXC_PAD_GPIO_AD_25_GPIO4_IO25 IMXRT_PADCFG(0, 88, 0x5, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_AD_25_NETC_TMR_TRIG2 IMXRT_PADCFG(0, 88, 0x7, 0, 204, 0x1) +#define IOMUXC_PAD_GPIO_AD_25_FLEXIO2_FLEXIO25 IMXRT_PADCFG(0, 88, 0x8, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_AD_25_ECAT_LINK_ACT01 IMXRT_PADCFG(0, 88, 0xc, 0, IMXRT_PADCFG_NO_DSYIDX, 0) + +#define IOMUXC_PAD_GPIO_AD_26_LPUART6_CTS_B IMXRT_PADCFG(0, 89, 0x0, 0, 129, 0x1) +#define IOMUXC_PAD_GPIO_AD_26_LPUART5_TX IMXRT_PADCFG(0, 89, 0x1, 0, 128, 0x3) +#define IOMUXC_PAD_GPIO_AD_26_LPSPI5_PCS2 IMXRT_PADCFG(0, 89, 0x2, 0, 103, 0x1) +#define IOMUXC_PAD_GPIO_AD_26_SINC2_EMCLK00 IMXRT_PADCFG(0, 89, 0x3, 0, 279, 0x0) +#define IOMUXC_PAD_GPIO_AD_26_FLEXPWM2_PWMA01 IMXRT_PADCFG(0, 89, 0x4, 0, 28, 0x1) +#define IOMUXC_PAD_GPIO_AD_26_GPIO4_IO26 IMXRT_PADCFG(0, 89, 0x5, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_AD_26_KPP_ROW00 IMXRT_PADCFG(0, 89, 0x6, 0, 74, 0x1) +#define IOMUXC_PAD_GPIO_AD_26_NETC_TMR_PP1 IMXRT_PADCFG(0, 89, 0x7, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_AD_26_FLEXIO2_FLEXIO26 IMXRT_PADCFG(0, 89, 0x8, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_AD_26_USDHC2_CD_B IMXRT_PADCFG(0, 89, 0x9, 0, 291, 0x2) +#define IOMUXC_PAD_GPIO_AD_26_MIC_BITSTREAM02 IMXRT_PADCFG(0, 89, 0xc, 0, 142, 0x1) + +#define IOMUXC_PAD_GPIO_AD_27_LPUART6_RTS_B IMXRT_PADCFG(0, 90, 0x0, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_AD_27_LPUART5_RX IMXRT_PADCFG(0, 90, 0x1, 0, 127, 0x3) +#define IOMUXC_PAD_GPIO_AD_27_LPSPI5_PCS1 IMXRT_PADCFG(0, 90, 0x2, 0, 102, 0x2) +#define IOMUXC_PAD_GPIO_AD_27_SINC2_EMBIT00 IMXRT_PADCFG(0, 90, 0x3, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_AD_27_FLEXPWM2_PWMB01 IMXRT_PADCFG(0, 90, 0x4, 0, 31, 0x1) +#define IOMUXC_PAD_GPIO_AD_27_GPIO4_IO27 IMXRT_PADCFG(0, 90, 0x5, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_AD_27_KPP_COL00 IMXRT_PADCFG(0, 90, 0x6, 0, 66, 0x1) +#define IOMUXC_PAD_GPIO_AD_27_NETC_TMR_PP2 IMXRT_PADCFG(0, 90, 0x7, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_AD_27_FLEXIO2_FLEXIO27 IMXRT_PADCFG(0, 90, 0x8, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_AD_27_USDHC2_WP IMXRT_PADCFG(0, 90, 0x9, 0, 292, 0x2) +#define IOMUXC_PAD_GPIO_AD_27_MIC_CLK IMXRT_PADCFG(0, 90, 0xc, 0, IMXRT_PADCFG_NO_DSYIDX, 0) + +#define IOMUXC_PAD_GPIO_AD_28_LPSPI5_SCK IMXRT_PADCFG(0, 91, 0x0, 0, 105, 0x2) +#define IOMUXC_PAD_GPIO_AD_28_I3C1_PUR IMXRT_PADCFG(0, 91, 0x2, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_AD_28_SINC2_EMCLK01 IMXRT_PADCFG(0, 91, 0x3, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_AD_28_FLEXPWM2_PWMB02 IMXRT_PADCFG(0, 91, 0x4, 0, 32, 0x1) +#define IOMUXC_PAD_GPIO_AD_28_GPIO4_IO28 IMXRT_PADCFG(0, 91, 0x5, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_AD_28_KPP_ROW03 IMXRT_PADCFG(0, 91, 0x6, 0, 77, 0x1) +#define IOMUXC_PAD_GPIO_AD_28_NETC_TMR_PP3 IMXRT_PADCFG(0, 91, 0x7, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_AD_28_FLEXIO2_FLEXIO28 IMXRT_PADCFG(0, 91, 0x8, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_AD_28_USDHC2_RESET_B IMXRT_PADCFG(0, 91, 0x9, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_AD_28_MIC_BITSTREAM00 IMXRT_PADCFG(0, 91, 0xc, 0, 140, 0x1) + +#define IOMUXC_PAD_GPIO_AD_29_LPSPI5_PCS0 IMXRT_PADCFG(0, 92, 0x0, 0, 101, 0x2) +#define IOMUXC_PAD_GPIO_AD_29_USDHC2_CD_B IMXRT_PADCFG(0, 92, 0x2, 0, 291, 0x3) +#define IOMUXC_PAD_GPIO_AD_29_SINC2_EMBIT01 IMXRT_PADCFG(0, 92, 0x3, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_AD_29_FLEXPWM2_PWMA02 IMXRT_PADCFG(0, 92, 0x4, 0, 29, 0x1) +#define IOMUXC_PAD_GPIO_AD_29_GPIO4_IO29 IMXRT_PADCFG(0, 92, 0x5, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_AD_29_KPP_COL03 IMXRT_PADCFG(0, 92, 0x6, 0, 69, 0x1) +#define IOMUXC_PAD_GPIO_AD_29_EWM_EWM_OUT_B IMXRT_PADCFG(0, 92, 0x7, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_AD_29_FLEXIO2_FLEXIO29 IMXRT_PADCFG(0, 92, 0x8, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_AD_29_USDHC2_VSELECT IMXRT_PADCFG(0, 92, 0x9, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_AD_29_MIC_BITSTREAM01 IMXRT_PADCFG(0, 92, 0xc, 0, 141, 0x1) + +#define IOMUXC_PAD_GPIO_AD_30_LPSPI5_SDO IMXRT_PADCFG(0, 93, 0x0, 0, 107, 0x2) +#define IOMUXC_PAD_GPIO_AD_30_USB_OTG2_OC IMXRT_PADCFG(0, 93, 0x1, 0, 285, 0x1) +#define IOMUXC_PAD_GPIO_AD_30_CAN2_TX IMXRT_PADCFG(0, 93, 0x2, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_AD_30_SINC2_EMCLK02 IMXRT_PADCFG(0, 93, 0x3, 0, 280, 0x0) +#define IOMUXC_PAD_GPIO_AD_30_LPUART8_TX IMXRT_PADCFG(0, 93, 0x4, 0, 137, 0x0) +#define IOMUXC_PAD_GPIO_AD_30_GPIO4_IO30 IMXRT_PADCFG(0, 93, 0x5, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_AD_30_KPP_ROW02 IMXRT_PADCFG(0, 93, 0x6, 0, 76, 0x1) +#define IOMUXC_PAD_GPIO_AD_30_NETC_EMDC IMXRT_PADCFG(0, 93, 0x7, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_AD_30_FLEXIO2_FLEXIO30 IMXRT_PADCFG(0, 93, 0x8, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_AD_30_XBAR1_XBAR_INOUT24 IMXRT_PADCFG(0, 93, 0x9, 0, 302, 0x1) +#define IOMUXC_PAD_GPIO_AD_30_ECAT_MCLK IMXRT_PADCFG(0, 93, 0xc, 0, IMXRT_PADCFG_NO_DSYIDX, 0) + +#define IOMUXC_PAD_GPIO_AD_31_LPSPI5_SDI IMXRT_PADCFG(0, 94, 0x0, 0, 106, 0x2) +#define IOMUXC_PAD_GPIO_AD_31_USB_OTG2_PWR IMXRT_PADCFG(0, 94, 0x1, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_AD_31_CAN2_RX IMXRT_PADCFG(0, 94, 0x2, 0, 1, 0x1) +#define IOMUXC_PAD_GPIO_AD_31_SINC2_EMBIT02 IMXRT_PADCFG(0, 94, 0x3, 0, 277, 0x0) +#define IOMUXC_PAD_GPIO_AD_31_LPUART8_RX IMXRT_PADCFG(0, 94, 0x4, 0, 136, 0x0) +#define IOMUXC_PAD_GPIO_AD_31_GPIO4_IO31 IMXRT_PADCFG(0, 94, 0x5, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_AD_31_KPP_COL02 IMXRT_PADCFG(0, 94, 0x6, 0, 68, 0x1) +#define IOMUXC_PAD_GPIO_AD_31_NETC_EMDIO IMXRT_PADCFG(0, 94, 0x7, 0, 190, 0x4) +#define IOMUXC_PAD_GPIO_AD_31_FLEXIO2_FLEXIO31 IMXRT_PADCFG(0, 94, 0x8, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_AD_31_XBAR1_XBAR_INOUT25 IMXRT_PADCFG(0, 94, 0x9, 0, 303, 0x1) +#define IOMUXC_PAD_GPIO_AD_31_ECAT_MDIO IMXRT_PADCFG(0, 94, 0xc, 0, 19, 0x0) + +#define IOMUXC_PAD_GPIO_AD_32_LPI2C5_SCL IMXRT_PADCFG(0, 95, 0x0, 0, 86, 0x1) +#define IOMUXC_PAD_GPIO_AD_32_USBPHY2_OTG_ID IMXRT_PADCFG(0, 95, 0x1, 0, 288, 0x1) +#define IOMUXC_PAD_GPIO_AD_32_GPC_PMIC_RDY IMXRT_PADCFG(0, 95, 0x2, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_AD_32_SINC2_EMCLK03 IMXRT_PADCFG(0, 95, 0x3, 0, 281, 0x0) +#define IOMUXC_PAD_GPIO_AD_32_USDHC1_CD_B IMXRT_PADCFG(0, 95, 0x4, 0, 289, 0x0) +#define IOMUXC_PAD_GPIO_AD_32_GPIO5_IO00 IMXRT_PADCFG(0, 95, 0x5, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_AD_32_KPP_ROW01 IMXRT_PADCFG(0, 95, 0x6, 0, 75, 0x1) +#define IOMUXC_PAD_GPIO_AD_32_NETC_TMR_TRIG1 IMXRT_PADCFG(0, 95, 0x7, 0, 203, 0x2) +#define IOMUXC_PAD_GPIO_AD_32_LPUART10_TX IMXRT_PADCFG(0, 95, 0x8, 0, 116, 0x1) +#define IOMUXC_PAD_GPIO_AD_32_MIC_BITSTREAM03 IMXRT_PADCFG(0, 95, 0xc, 0, 143, 0x1) + +#define IOMUXC_PAD_GPIO_AD_33_LPI2C5_SDA IMXRT_PADCFG(0, 96, 0x0, 0, 87, 0x1) +#define IOMUXC_PAD_GPIO_AD_33_USBPHY1_OTG_ID IMXRT_PADCFG(0, 96, 0x1, 0, 287, 0x1) +#define IOMUXC_PAD_GPIO_AD_33_XBAR1_XBAR_INOUT17 IMXRT_PADCFG(0, 96, 0x2, 0, 295, 0x0) +#define IOMUXC_PAD_GPIO_AD_33_SINC2_EMBIT03 IMXRT_PADCFG(0, 96, 0x3, 0, 278, 0x0) +#define IOMUXC_PAD_GPIO_AD_33_USDHC1_WP IMXRT_PADCFG(0, 96, 0x4, 0, 290, 0x0) +#define IOMUXC_PAD_GPIO_AD_33_GPIO5_IO01 IMXRT_PADCFG(0, 96, 0x5, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_AD_33_KPP_COL01 IMXRT_PADCFG(0, 96, 0x6, 0, 67, 0x1) +#define IOMUXC_PAD_GPIO_AD_33_NETC_TMR_TRIG2 IMXRT_PADCFG(0, 96, 0x7, 0, 204, 0x2) +#define IOMUXC_PAD_GPIO_AD_33_LPUART10_RX IMXRT_PADCFG(0, 96, 0x8, 0, 115, 0x1) + +#define IOMUXC_PAD_GPIO_AD_34_I3C2_SCL IMXRT_PADCFG(0, 97, 0x0, 0, 64, 0x1) +#define IOMUXC_PAD_GPIO_AD_34_USB_OTG1_PWR IMXRT_PADCFG(0, 97, 0x1, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_AD_34_XBAR1_XBAR_INOUT18 IMXRT_PADCFG(0, 97, 0x2, 0, 296, 0x1) +#define IOMUXC_PAD_GPIO_AD_34_SINC_FILTER_GLUE2_BREAK IMXRT_PADCFG(0, 97, 0x3, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_AD_34_USDHC1_VSELECT IMXRT_PADCFG(0, 97, 0x4, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_AD_34_GPIO5_IO02 IMXRT_PADCFG(0, 97, 0x5, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_AD_34_NETC_TMR_ALARM1 IMXRT_PADCFG(0, 97, 0x7, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_AD_34_LPUART10_CTS_B IMXRT_PADCFG(0, 97, 0x8, 0, IMXRT_PADCFG_NO_DSYIDX, 0) + +#define IOMUXC_PAD_GPIO_AD_35_I3C2_SDA IMXRT_PADCFG(0, 98, 0x0, 0, 65, 0x1) +#define IOMUXC_PAD_GPIO_AD_35_USB_OTG1_OC IMXRT_PADCFG(0, 98, 0x1, 0, 286, 0x1) +#define IOMUXC_PAD_GPIO_AD_35_XBAR1_XBAR_INOUT19 IMXRT_PADCFG(0, 98, 0x2, 0, 297, 0x1) +#define IOMUXC_PAD_GPIO_AD_35_SINC2_MOD_CLK0 IMXRT_PADCFG(0, 98, 0x3, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_AD_35_USDHC1_RESET_B IMXRT_PADCFG(0, 98, 0x4, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_AD_35_GPIO5_IO03 IMXRT_PADCFG(0, 98, 0x5, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_AD_35_NETC_TMR_ALARM2 IMXRT_PADCFG(0, 98, 0x7, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_AD_35_LPUART10_RTS_B IMXRT_PADCFG(0, 98, 0x8, 0, IMXRT_PADCFG_NO_DSYIDX, 0) + +#define IOMUXC_PAD_GPIO_SD_B1_00_USDHC1_CMD IMXRT_PADCFG(0, 99, 0x0, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_SD_B1_00_SINC1_EMCLK02 IMXRT_PADCFG(0, 99, 0x1, 0, 275, 0x1) +#define IOMUXC_PAD_GPIO_SD_B1_00_XBAR1_XBAR_INOUT20 IMXRT_PADCFG(0, 99, 0x2, 0, 298, 0x1) +#define IOMUXC_PAD_GPIO_SD_B1_00_LPTMR2_ALT1 IMXRT_PADCFG(0, 99, 0x3, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_SD_B1_00_XSPI_SLV_CS IMXRT_PADCFG(0, 99, 0x4, 0, 344, 0x0) +#define IOMUXC_PAD_GPIO_SD_B1_00_GPIO5_IO04 IMXRT_PADCFG(0, 99, 0x5, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_SD_B1_00_LPSPI3_PCS0 IMXRT_PADCFG(0, 99, 0x6, 0, 90, 0x2) +#define IOMUXC_PAD_GPIO_SD_B1_00_KPP_ROW07 IMXRT_PADCFG(0, 99, 0x8, 0, 81, 0x2) +#define IOMUXC_PAD_GPIO_SD_B1_00_CCM_CLKO1 IMXRT_PADCFG(0, 99, 0xc, 0, IMXRT_PADCFG_NO_DSYIDX, 0) + +#define IOMUXC_PAD_GPIO_SD_B1_01_USDHC1_CLK IMXRT_PADCFG(0, 100, 0x0, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_SD_B1_01_SINC1_EMBIT02 IMXRT_PADCFG(0, 100, 0x1, 0, 271, 0x1) +#define IOMUXC_PAD_GPIO_SD_B1_01_XBAR1_XBAR_INOUT21 IMXRT_PADCFG(0, 100, 0x2, 0, 299, 0x1) +#define IOMUXC_PAD_GPIO_SD_B1_01_LPTMR2_ALT2 IMXRT_PADCFG(0, 100, 0x3, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_SD_B1_01_XSPI_SLV_CLK IMXRT_PADCFG(0, 100, 0x4, 0, 354, 0x0) +#define IOMUXC_PAD_GPIO_SD_B1_01_GPIO5_IO05 IMXRT_PADCFG(0, 100, 0x5, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_SD_B1_01_LPSPI3_SCK IMXRT_PADCFG(0, 100, 0x6, 0, 94, 0x2) +#define IOMUXC_PAD_GPIO_SD_B1_01_KPP_COL07 IMXRT_PADCFG(0, 100, 0x8, 0, 73, 0x2) +#define IOMUXC_PAD_GPIO_SD_B1_01_CCM_CLKO2 IMXRT_PADCFG(0, 100, 0xc, 0, IMXRT_PADCFG_NO_DSYIDX, 0) + +#define IOMUXC_PAD_GPIO_SD_B1_02_USDHC1_DATA0 IMXRT_PADCFG(0, 101, 0x0, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_SD_B1_02_SINC1_EMCLK03 IMXRT_PADCFG(0, 101, 0x1, 0, 276, 0x1) +#define IOMUXC_PAD_GPIO_SD_B1_02_XBAR1_XBAR_INOUT22 IMXRT_PADCFG(0, 101, 0x2, 0, 300, 0x1) +#define IOMUXC_PAD_GPIO_SD_B1_02_LPTMR2_ALT3 IMXRT_PADCFG(0, 101, 0x3, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_SD_B1_02_XSPI_SLV_DATA04 IMXRT_PADCFG(0, 101, 0x4, 0, 350, 0x0) +#define IOMUXC_PAD_GPIO_SD_B1_02_GPIO5_IO06 IMXRT_PADCFG(0, 101, 0x5, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_SD_B1_02_LPSPI3_SDO IMXRT_PADCFG(0, 101, 0x6, 0, 96, 0x2) +#define IOMUXC_PAD_GPIO_SD_B1_02_KPP_ROW06 IMXRT_PADCFG(0, 101, 0x8, 0, 80, 0x2) +#define IOMUXC_PAD_GPIO_SD_B1_02_FLEXSPI1_BUS2BIT_A_SS1_B IMXRT_PADCFG(0, 101, 0x9, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_SD_B1_02_ECAT_RESET_OUT IMXRT_PADCFG(0, 101, 0xc, 0, IMXRT_PADCFG_NO_DSYIDX, 0) + +#define IOMUXC_PAD_GPIO_SD_B1_03_USDHC1_DATA1 IMXRT_PADCFG(0, 102, 0x0, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_SD_B1_03_SINC1_EMBIT03 IMXRT_PADCFG(0, 102, 0x1, 0, 272, 0x1) +#define IOMUXC_PAD_GPIO_SD_B1_03_XBAR1_XBAR_INOUT23 IMXRT_PADCFG(0, 102, 0x2, 0, 301, 0x1) +#define IOMUXC_PAD_GPIO_SD_B1_03_LPTMR3_ALT1 IMXRT_PADCFG(0, 102, 0x3, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_SD_B1_03_XSPI_SLV_DATA05 IMXRT_PADCFG(0, 102, 0x4, 0, 351, 0x0) +#define IOMUXC_PAD_GPIO_SD_B1_03_GPIO5_IO07 IMXRT_PADCFG(0, 102, 0x5, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_SD_B1_03_LPSPI3_SDI IMXRT_PADCFG(0, 102, 0x6, 0, 95, 0x2) +#define IOMUXC_PAD_GPIO_SD_B1_03_KPP_COL06 IMXRT_PADCFG(0, 102, 0x8, 0, 72, 0x2) +#define IOMUXC_PAD_GPIO_SD_B1_03_FLEXSPI1_BUS2BIT_B_SS1_B IMXRT_PADCFG(0, 102, 0x9, 0, IMXRT_PADCFG_NO_DSYIDX, 0) + +#define IOMUXC_PAD_GPIO_SD_B1_04_USDHC1_DATA2 IMXRT_PADCFG(0, 103, 0x0, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_SD_B1_04_SINC_FILTER_GLUE1_BREAK IMXRT_PADCFG(0, 103, 0x1, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_SD_B1_04_SINC2_EMCLK02 IMXRT_PADCFG(0, 103, 0x2, 0, 280, 0x1) +#define IOMUXC_PAD_GPIO_SD_B1_04_LPTMR3_ALT2 IMXRT_PADCFG(0, 103, 0x3, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_SD_B1_04_XSPI_SLV_DATA06 IMXRT_PADCFG(0, 103, 0x4, 0, 352, 0x0) +#define IOMUXC_PAD_GPIO_SD_B1_04_GPIO5_IO08 IMXRT_PADCFG(0, 103, 0x5, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_SD_B1_04_LPSPI3_PCS1 IMXRT_PADCFG(0, 103, 0x6, 0, 91, 0x2) +#define IOMUXC_PAD_GPIO_SD_B1_04_FLEXSPI1_BUS2BIT_B_SS0_B IMXRT_PADCFG(0, 103, 0x8, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_SD_B1_04_FLEXSPI1_BUS2BIT_A_SS1_B IMXRT_PADCFG(0, 103, 0x9, 0, IMXRT_PADCFG_NO_DSYIDX, 0) + +#define IOMUXC_PAD_GPIO_SD_B1_05_USDHC1_DATA3 IMXRT_PADCFG(0, 104, 0x0, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_SD_B1_05_SINC2_EMBIT02 IMXRT_PADCFG(0, 104, 0x2, 0, 277, 0x1) +#define IOMUXC_PAD_GPIO_SD_B1_05_LPTMR3_ALT3 IMXRT_PADCFG(0, 104, 0x3, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_SD_B1_05_XSPI_SLV_DATA07 IMXRT_PADCFG(0, 104, 0x4, 0, 353, 0x0) +#define IOMUXC_PAD_GPIO_SD_B1_05_GPIO5_IO09 IMXRT_PADCFG(0, 104, 0x5, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_SD_B1_05_LPSPI3_PCS2 IMXRT_PADCFG(0, 104, 0x6, 0, 92, 0x1) +#define IOMUXC_PAD_GPIO_SD_B1_05_FLEXSPI1_BUS2BIT_B_SS0_B IMXRT_PADCFG(0, 104, 0x9, 0, IMXRT_PADCFG_NO_DSYIDX, 0) + +#define IOMUXC_PAD_GPIO_SD_B2_00_USDHC2_DATA3 IMXRT_PADCFG(0, 105, 0x0, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_SD_B2_00_FLEXSPI1_BUS2BIT_B_DATA04 IMXRT_PADCFG(0, 105, 0x1, 0, 47, 0x0) +#define IOMUXC_PAD_GPIO_SD_B2_00_XSPI_SLV_DATA04 IMXRT_PADCFG(0, 105, 0x2, 0, 350, 0x1) +#define IOMUXC_PAD_GPIO_SD_B2_00_XBAR1_XBAR_INOUT17 IMXRT_PADCFG(0, 105, 0x3, 0, 295, 0x1) +#define IOMUXC_PAD_GPIO_SD_B2_00_KPP_ROW01 IMXRT_PADCFG(0, 105, 0x4, 0, 75, 0x2) +#define IOMUXC_PAD_GPIO_SD_B2_00_GPIO5_IO10 IMXRT_PADCFG(0, 105, 0x5, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_SD_B2_00_LPSPI3_PCS3 IMXRT_PADCFG(0, 105, 0x6, 0, 93, 0x1) +#define IOMUXC_PAD_GPIO_SD_B2_00_NETC_1588_CLK IMXRT_PADCFG(0, 105, 0x8, 0, 205, 0x1) +#define IOMUXC_PAD_GPIO_SD_B2_00_LPUART8_TX IMXRT_PADCFG(0, 105, 0x9, 0, 137, 0x1) +#define IOMUXC_PAD_GPIO_SD_B2_00_MIC_BITSTREAM00 IMXRT_PADCFG(0, 105, 0xc, 0, 140, 0x2) + +#define IOMUXC_PAD_GPIO_SD_B2_01_USDHC2_DATA2 IMXRT_PADCFG(0, 106, 0x0, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_SD_B2_01_FLEXSPI1_BUS2BIT_B_DATA05 IMXRT_PADCFG(0, 106, 0x1, 0, 48, 0x0) +#define IOMUXC_PAD_GPIO_SD_B2_01_XSPI_SLV_DATA05 IMXRT_PADCFG(0, 106, 0x2, 0, 351, 0x1) +#define IOMUXC_PAD_GPIO_SD_B2_01_QTIMER6_TIMER0 IMXRT_PADCFG(0, 106, 0x3, 0, 253, 0x2) +#define IOMUXC_PAD_GPIO_SD_B2_01_KPP_COL01 IMXRT_PADCFG(0, 106, 0x4, 0, 67, 0x2) +#define IOMUXC_PAD_GPIO_SD_B2_01_GPIO5_IO11 IMXRT_PADCFG(0, 106, 0x5, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_SD_B2_01_NETC_TMR_GCLK IMXRT_PADCFG(0, 106, 0x8, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_SD_B2_01_LPUART8_RX IMXRT_PADCFG(0, 106, 0x9, 0, 136, 0x1) +#define IOMUXC_PAD_GPIO_SD_B2_01_MIC_BITSTREAM01 IMXRT_PADCFG(0, 106, 0xc, 0, 141, 0x2) + +#define IOMUXC_PAD_GPIO_SD_B2_02_USDHC2_DATA1 IMXRT_PADCFG(0, 107, 0x0, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_SD_B2_02_FLEXSPI1_BUS2BIT_B_DATA06 IMXRT_PADCFG(0, 107, 0x1, 0, 49, 0x0) +#define IOMUXC_PAD_GPIO_SD_B2_02_XSPI_SLV_DATA06 IMXRT_PADCFG(0, 107, 0x2, 0, 352, 0x1) +#define IOMUXC_PAD_GPIO_SD_B2_02_QTIMER6_TIMER1 IMXRT_PADCFG(0, 107, 0x3, 0, 254, 0x2) +#define IOMUXC_PAD_GPIO_SD_B2_02_KPP_ROW00 IMXRT_PADCFG(0, 107, 0x4, 0, 74, 0x2) +#define IOMUXC_PAD_GPIO_SD_B2_02_GPIO5_IO12 IMXRT_PADCFG(0, 107, 0x5, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_SD_B2_02_NETC_TMR_ALARM1 IMXRT_PADCFG(0, 107, 0x8, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_SD_B2_02_LPUART8_CTS_B IMXRT_PADCFG(0, 107, 0x9, 0, 135, 0x0) +#define IOMUXC_PAD_GPIO_SD_B2_02_MIC_BITSTREAM02 IMXRT_PADCFG(0, 107, 0xc, 0, 142, 0x2) + +#define IOMUXC_PAD_GPIO_SD_B2_03_USDHC2_DATA0 IMXRT_PADCFG(0, 108, 0x0, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_SD_B2_03_FLEXSPI1_BUS2BIT_B_DATA07 IMXRT_PADCFG(0, 108, 0x1, 0, 50, 0x0) +#define IOMUXC_PAD_GPIO_SD_B2_03_XSPI_SLV_DATA07 IMXRT_PADCFG(0, 108, 0x2, 0, 353, 0x1) +#define IOMUXC_PAD_GPIO_SD_B2_03_QTIMER6_TIMER2 IMXRT_PADCFG(0, 108, 0x3, 0, 255, 0x1) +#define IOMUXC_PAD_GPIO_SD_B2_03_KPP_COL00 IMXRT_PADCFG(0, 108, 0x4, 0, 66, 0x2) +#define IOMUXC_PAD_GPIO_SD_B2_03_GPIO5_IO13 IMXRT_PADCFG(0, 108, 0x5, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_SD_B2_03_NETC_TMR_ALARM2 IMXRT_PADCFG(0, 108, 0x8, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_SD_B2_03_LPUART8_RTS_B IMXRT_PADCFG(0, 108, 0x9, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_SD_B2_03_MIC_BITSTREAM03 IMXRT_PADCFG(0, 108, 0xc, 0, 143, 0x2) + +#define IOMUXC_PAD_GPIO_SD_B2_04_USDHC2_CLK IMXRT_PADCFG(0, 109, 0x0, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_SD_B2_04_FLEXSPI1_BUS2BIT_B_SS1_B IMXRT_PADCFG(0, 109, 0x1, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_SD_B2_04_QTIMER7_TIMER0 IMXRT_PADCFG(0, 109, 0x3, 0, 256, 0x1) +#define IOMUXC_PAD_GPIO_SD_B2_04_KPP_ROW03 IMXRT_PADCFG(0, 109, 0x4, 0, 77, 0x2) +#define IOMUXC_PAD_GPIO_SD_B2_04_GPIO5_IO14 IMXRT_PADCFG(0, 109, 0x5, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_SD_B2_04_LPUART5_RI_B IMXRT_PADCFG(0, 109, 0x6, 0, 126, 0x1) +#define IOMUXC_PAD_GPIO_SD_B2_04_NETC_TMR_PP1 IMXRT_PADCFG(0, 109, 0x8, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_SD_B2_04_MIC_CLK IMXRT_PADCFG(0, 109, 0xc, 0, IMXRT_PADCFG_NO_DSYIDX, 0) + +#define IOMUXC_PAD_GPIO_SD_B2_05_USDHC2_CMD IMXRT_PADCFG(0, 110, 0x0, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_SD_B2_05_FLEXSPI1_BUS2BIT_B_DQS IMXRT_PADCFG(0, 110, 0x1, 0, 42, 0x0) +#define IOMUXC_PAD_GPIO_SD_B2_05_XSPI_SLV_DQS IMXRT_PADCFG(0, 110, 0x2, 0, 345, 0x0) +#define IOMUXC_PAD_GPIO_SD_B2_05_QTIMER7_TIMER1 IMXRT_PADCFG(0, 110, 0x3, 0, 257, 0x1) +#define IOMUXC_PAD_GPIO_SD_B2_05_LPSPI4_PCS3 IMXRT_PADCFG(0, 110, 0x4, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_SD_B2_05_GPIO5_IO15 IMXRT_PADCFG(0, 110, 0x5, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_SD_B2_05_LPUART5_DTR_B IMXRT_PADCFG(0, 110, 0x6, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_SD_B2_05_NETC_TMR_PP2 IMXRT_PADCFG(0, 110, 0x8, 0, IMXRT_PADCFG_NO_DSYIDX, 0) + +#define IOMUXC_PAD_GPIO_SD_B2_06_USDHC2_RESET_B IMXRT_PADCFG(0, 111, 0x0, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_SD_B2_06_FLEXSPI1_BUS2BIT_B_SS0_B IMXRT_PADCFG(0, 111, 0x1, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_SD_B2_06_XSPI_SLV_CS IMXRT_PADCFG(0, 111, 0x2, 0, 344, 0x1) +#define IOMUXC_PAD_GPIO_SD_B2_06_QTIMER7_TIMER2 IMXRT_PADCFG(0, 111, 0x3, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_SD_B2_06_LPSPI4_PCS2 IMXRT_PADCFG(0, 111, 0x4, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_SD_B2_06_GPIO5_IO16 IMXRT_PADCFG(0, 111, 0x5, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_SD_B2_06_LPUART5_CTS_B IMXRT_PADCFG(0, 111, 0x6, 0, 123, 0x2) +#define IOMUXC_PAD_GPIO_SD_B2_06_NETC_TMR_PP3 IMXRT_PADCFG(0, 111, 0x8, 0, IMXRT_PADCFG_NO_DSYIDX, 0) + +#define IOMUXC_PAD_GPIO_SD_B2_07_USDHC2_STROBE IMXRT_PADCFG(0, 112, 0x0, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_SD_B2_07_FLEXSPI1_BUS2BIT_B_SCLK IMXRT_PADCFG(0, 112, 0x1, 0, 51, 0x0) +#define IOMUXC_PAD_GPIO_SD_B2_07_XSPI_SLV_CLK IMXRT_PADCFG(0, 112, 0x2, 0, 354, 0x1) +#define IOMUXC_PAD_GPIO_SD_B2_07_QTIMER7_TIMER3 IMXRT_PADCFG(0, 112, 0x3, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_SD_B2_07_LPSPI4_PCS1 IMXRT_PADCFG(0, 112, 0x4, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_SD_B2_07_GPIO5_IO17 IMXRT_PADCFG(0, 112, 0x5, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_SD_B2_07_LPUART5_RTS_B IMXRT_PADCFG(0, 112, 0x6, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_SD_B2_07_NETC_TMR_ALARM1 IMXRT_PADCFG(0, 112, 0x8, 0, IMXRT_PADCFG_NO_DSYIDX, 0) + +#define IOMUXC_PAD_GPIO_SD_B2_08_USDHC2_DATA4 IMXRT_PADCFG(0, 113, 0x0, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_SD_B2_08_FLEXSPI1_BUS2BIT_B_DATA00 IMXRT_PADCFG(0, 113, 0x1, 0, 43, 0x0) +#define IOMUXC_PAD_GPIO_SD_B2_08_XSPI_SLV_DATA00 IMXRT_PADCFG(0, 113, 0x2, 0, 346, 0x0) +#define IOMUXC_PAD_GPIO_SD_B2_08_QTIMER8_TIMER0 IMXRT_PADCFG(0, 113, 0x3, 0, 258, 0x1) +#define IOMUXC_PAD_GPIO_SD_B2_08_LPSPI4_SCK IMXRT_PADCFG(0, 113, 0x4, 0, 98, 0x1) +#define IOMUXC_PAD_GPIO_SD_B2_08_GPIO5_IO18 IMXRT_PADCFG(0, 113, 0x5, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_SD_B2_08_LPUART5_TX IMXRT_PADCFG(0, 113, 0x6, 0, 128, 0x4) +#define IOMUXC_PAD_GPIO_SD_B2_08_NETC_TMR_ALARM2 IMXRT_PADCFG(0, 113, 0x8, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_SD_B2_08_NETC_TMR_PP2 IMXRT_PADCFG(0, 113, 0x9, 0, IMXRT_PADCFG_NO_DSYIDX, 0) + +#define IOMUXC_PAD_GPIO_SD_B2_09_USDHC2_DATA5 IMXRT_PADCFG(0, 114, 0x0, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_SD_B2_09_FLEXSPI1_BUS2BIT_B_DATA01 IMXRT_PADCFG(0, 114, 0x1, 0, 44, 0x0) +#define IOMUXC_PAD_GPIO_SD_B2_09_XSPI_SLV_DATA01 IMXRT_PADCFG(0, 114, 0x2, 0, 347, 0x0) +#define IOMUXC_PAD_GPIO_SD_B2_09_QTIMER8_TIMER1 IMXRT_PADCFG(0, 114, 0x3, 0, 259, 0x1) +#define IOMUXC_PAD_GPIO_SD_B2_09_LPSPI4_PCS0 IMXRT_PADCFG(0, 114, 0x4, 0, 97, 0x1) +#define IOMUXC_PAD_GPIO_SD_B2_09_GPIO5_IO19 IMXRT_PADCFG(0, 114, 0x5, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_SD_B2_09_LPUART5_RX IMXRT_PADCFG(0, 114, 0x6, 0, 127, 0x4) +#define IOMUXC_PAD_GPIO_SD_B2_09_NETC_TMR_PP1 IMXRT_PADCFG(0, 114, 0x9, 0, IMXRT_PADCFG_NO_DSYIDX, 0) + +#define IOMUXC_PAD_GPIO_SD_B2_10_USDHC2_DATA6 IMXRT_PADCFG(0, 115, 0x0, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_SD_B2_10_FLEXSPI1_BUS2BIT_B_DATA02 IMXRT_PADCFG(0, 115, 0x1, 0, 45, 0x0) +#define IOMUXC_PAD_GPIO_SD_B2_10_XSPI_SLV_DATA02 IMXRT_PADCFG(0, 115, 0x2, 0, 348, 0x0) +#define IOMUXC_PAD_GPIO_SD_B2_10_QTIMER8_TIMER2 IMXRT_PADCFG(0, 115, 0x3, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_SD_B2_10_LPSPI4_SDO IMXRT_PADCFG(0, 115, 0x4, 0, 100, 0x1) +#define IOMUXC_PAD_GPIO_SD_B2_10_GPIO5_IO20 IMXRT_PADCFG(0, 115, 0x5, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_SD_B2_10_LPUART5_DCD_B IMXRT_PADCFG(0, 115, 0x6, 0, 124, 0x1) +#define IOMUXC_PAD_GPIO_SD_B2_10_NETC_TMR_TRIG2 IMXRT_PADCFG(0, 115, 0x8, 0, 204, 0x3) +#define IOMUXC_PAD_GPIO_SD_B2_10_NETC_TMR_PP3 IMXRT_PADCFG(0, 115, 0x9, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_SD_B2_10_NETC_EMDIO IMXRT_PADCFG(0, 115, 0xa, 0, 190, 0x5) +#define IOMUXC_PAD_GPIO_SD_B2_10_ECAT_MDIO IMXRT_PADCFG(0, 115, 0xc, 0, 19, 0x1) + +#define IOMUXC_PAD_GPIO_SD_B2_11_USDHC2_DATA7 IMXRT_PADCFG(0, 116, 0x0, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_SD_B2_11_FLEXSPI1_BUS2BIT_B_DATA03 IMXRT_PADCFG(0, 116, 0x1, 0, 46, 0x0) +#define IOMUXC_PAD_GPIO_SD_B2_11_XSPI_SLV_DATA03 IMXRT_PADCFG(0, 116, 0x2, 0, 349, 0x0) +#define IOMUXC_PAD_GPIO_SD_B2_11_QTIMER8_TIMER3 IMXRT_PADCFG(0, 116, 0x3, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_SD_B2_11_LPSPI4_SDI IMXRT_PADCFG(0, 116, 0x4, 0, 99, 0x1) +#define IOMUXC_PAD_GPIO_SD_B2_11_GPIO5_IO21 IMXRT_PADCFG(0, 116, 0x5, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_SD_B2_11_LPUART5_DSR_B IMXRT_PADCFG(0, 116, 0x6, 0, 125, 0x1) +#define IOMUXC_PAD_GPIO_SD_B2_11_SFA_ATX_CLK_OUT IMXRT_PADCFG(0, 116, 0x7, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_SD_B2_11_NETC_TMR_TRIG1 IMXRT_PADCFG(0, 116, 0x8, 0, 203, 0x3) +#define IOMUXC_PAD_GPIO_SD_B2_11_NETC_EMDC IMXRT_PADCFG(0, 116, 0xa, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_SD_B2_11_ECAT_MCLK IMXRT_PADCFG(0, 116, 0xc, 0, IMXRT_PADCFG_NO_DSYIDX, 0) + +#define IOMUXC_PAD_GPIO_SD_B2_12_DUMMY_FLEXSPI1_BUS2BIT_A_DQS IMXRT_PADCFG(0, 117, 0x0, 0, 41, 0x0) +#define IOMUXC_PAD_GPIO_SD_B2_12_DUMMY_FLEXSPI1_BUS2BIT_B_DQS IMXRT_PADCFG(0, 117, 0x1, 0, 42, 0x1) +#define IOMUXC_PAD_GPIO_SD_B2_12_DUMMY_GPIO5_IO22 IMXRT_PADCFG(0, 117, 0x5, 0, IMXRT_PADCFG_NO_DSYIDX, 0) + +#define IOMUXC_PAD_GPIO_B1_00_NETC_PINMUX_ETH1_TXD00 IMXRT_PADCFG(0, 118, 0x0, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_B1_00_ADC2_CONV_D00 IMXRT_PADCFG(0, 118, 0x1, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_B1_00_SEMC_CSX01 IMXRT_PADCFG(0, 118, 0x2, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_B1_00_QTIMER1_TIMER0 IMXRT_PADCFG(0, 118, 0x3, 0, 238, 0x2) +#define IOMUXC_PAD_GPIO_B1_00_XBAR1_XBAR_INOUT26 IMXRT_PADCFG(0, 118, 0x4, 0, 304, 0x1) +#define IOMUXC_PAD_GPIO_B1_00_GPIO6_IO00 IMXRT_PADCFG(0, 118, 0x5, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_B1_00_TPM5_CH00 IMXRT_PADCFG(0, 118, 0x6, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_B1_00_NETC_PINMUX_ETH4_TXD00 IMXRT_PADCFG(0, 118, 0x8, 0, IMXRT_PADCFG_NO_DSYIDX, 0) + +#define IOMUXC_PAD_GPIO_B1_01_NETC_PINMUX_ETH1_TXD01 IMXRT_PADCFG(0, 119, 0x0, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_B1_01_ADC2_CONV_D01 IMXRT_PADCFG(0, 119, 0x1, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_B1_01_SEMC_CSX02 IMXRT_PADCFG(0, 119, 0x2, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_B1_01_QTIMER1_TIMER1 IMXRT_PADCFG(0, 119, 0x3, 0, 239, 0x2) +#define IOMUXC_PAD_GPIO_B1_01_XBAR1_XBAR_INOUT27 IMXRT_PADCFG(0, 119, 0x4, 0, 305, 0x1) +#define IOMUXC_PAD_GPIO_B1_01_GPIO6_IO01 IMXRT_PADCFG(0, 119, 0x5, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_B1_01_TPM5_CH01 IMXRT_PADCFG(0, 119, 0x6, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_B1_01_NETC_PINMUX_ETH4_TXD01 IMXRT_PADCFG(0, 119, 0x8, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_B1_01_SAI4_RX_DATA00 IMXRT_PADCFG(0, 119, 0xc, 0, 262, 0x1) + +#define IOMUXC_PAD_GPIO_B1_02_NETC_PINMUX_ETH1_TX_EN IMXRT_PADCFG(0, 120, 0x0, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_B1_02_ADC2_CONV_D02 IMXRT_PADCFG(0, 120, 0x1, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_B1_02_LPI2C6_SCL IMXRT_PADCFG(0, 120, 0x2, 0, 88, 0x0) +#define IOMUXC_PAD_GPIO_B1_02_QTIMER1_TIMER2 IMXRT_PADCFG(0, 120, 0x3, 0, 240, 0x1) +#define IOMUXC_PAD_GPIO_B1_02_XBAR1_XBAR_INOUT28 IMXRT_PADCFG(0, 120, 0x4, 0, 306, 0x1) +#define IOMUXC_PAD_GPIO_B1_02_GPIO6_IO02 IMXRT_PADCFG(0, 120, 0x5, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_B1_02_TPM5_CH02 IMXRT_PADCFG(0, 120, 0x6, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_B1_02_FLEXSPI1_BUS2BIT_B_SS1_B IMXRT_PADCFG(0, 120, 0x7, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_B1_02_NETC_PINMUX_ETH4_TX_EN IMXRT_PADCFG(0, 120, 0x8, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_B1_02_LPUART11_TX IMXRT_PADCFG(0, 120, 0x9, 0, 118, 0x1) +#define IOMUXC_PAD_GPIO_B1_02_SAI4_RX_DATA01 IMXRT_PADCFG(0, 120, 0xc, 0, 263, 0x0) + +#define IOMUXC_PAD_GPIO_B1_03_NETC_PINMUX_ETH1_TX_CLK IMXRT_PADCFG(0, 121, 0x0, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_B1_03_ADC2_CONV_D03 IMXRT_PADCFG(0, 121, 0x1, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_B1_03_LPI2C6_SDA IMXRT_PADCFG(0, 121, 0x2, 0, 89, 0x0) +#define IOMUXC_PAD_GPIO_B1_03_QTIMER2_TIMER0 IMXRT_PADCFG(0, 121, 0x3, 0, 241, 0x2) +#define IOMUXC_PAD_GPIO_B1_03_XBAR1_XBAR_INOUT29 IMXRT_PADCFG(0, 121, 0x4, 0, 307, 0x1) +#define IOMUXC_PAD_GPIO_B1_03_GPIO6_IO03 IMXRT_PADCFG(0, 121, 0x5, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_B1_03_TPM5_CH03 IMXRT_PADCFG(0, 121, 0x6, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_B1_03_FLEXSPI1_BUS2BIT_B_DQS IMXRT_PADCFG(0, 121, 0x7, 0, 42, 0x2) +#define IOMUXC_PAD_GPIO_B1_03_NETC_PINMUX_ETH4_TX_CLK IMXRT_PADCFG(0, 121, 0x8, 0, 237, 0x2) +#define IOMUXC_PAD_GPIO_B1_03_LPUART11_RX IMXRT_PADCFG(0, 121, 0x9, 0, 117, 0x1) +#define IOMUXC_PAD_GPIO_B1_03_SAI4_RX_DATA02 IMXRT_PADCFG(0, 121, 0xc, 0, IMXRT_PADCFG_NO_DSYIDX, 0) + +#define IOMUXC_PAD_GPIO_B1_04_NETC_PINMUX_ETH1_RXD00 IMXRT_PADCFG(0, 122, 0x0, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_B1_04_ADC2_CONV_D04 IMXRT_PADCFG(0, 122, 0x1, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_B1_04_LPUART9_RX IMXRT_PADCFG(0, 122, 0x2, 0, 138, 0x1) +#define IOMUXC_PAD_GPIO_B1_04_QTIMER2_TIMER1 IMXRT_PADCFG(0, 122, 0x3, 0, 242, 0x2) +#define IOMUXC_PAD_GPIO_B1_04_XBAR1_XBAR_INOUT30 IMXRT_PADCFG(0, 122, 0x4, 0, 308, 0x1) +#define IOMUXC_PAD_GPIO_B1_04_GPIO6_IO04 IMXRT_PADCFG(0, 122, 0x5, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_B1_04_TPM5_EXTCLK IMXRT_PADCFG(0, 122, 0x6, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_B1_04_FLEXSPI1_BUS2BIT_B_SS0_B IMXRT_PADCFG(0, 122, 0x7, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_B1_04_NETC_PINMUX_ETH4_RXD00 IMXRT_PADCFG(0, 122, 0x8, 0, 233, 0x2) +#define IOMUXC_PAD_GPIO_B1_04_SAI4_RX_DATA03 IMXRT_PADCFG(0, 122, 0xc, 0, IMXRT_PADCFG_NO_DSYIDX, 0) + +#define IOMUXC_PAD_GPIO_B1_05_NETC_PINMUX_ETH1_RXD01 IMXRT_PADCFG(0, 123, 0x0, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_B1_05_ADC2_CONV_D05 IMXRT_PADCFG(0, 123, 0x1, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_B1_05_LPUART9_CTS_B IMXRT_PADCFG(0, 123, 0x2, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_B1_05_QTIMER2_TIMER2 IMXRT_PADCFG(0, 123, 0x3, 0, 243, 0x1) +#define IOMUXC_PAD_GPIO_B1_05_XBAR1_XBAR_INOUT31 IMXRT_PADCFG(0, 123, 0x4, 0, 309, 0x1) +#define IOMUXC_PAD_GPIO_B1_05_GPIO6_IO05 IMXRT_PADCFG(0, 123, 0x5, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_B1_05_TPM6_EXTCLK IMXRT_PADCFG(0, 123, 0x6, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_B1_05_FLEXSPI1_BUS2BIT_B_SCLK IMXRT_PADCFG(0, 123, 0x7, 0, 51, 0x1) +#define IOMUXC_PAD_GPIO_B1_05_NETC_PINMUX_ETH4_RXD01 IMXRT_PADCFG(0, 123, 0x8, 0, 234, 0x2) +#define IOMUXC_PAD_GPIO_B1_05_SAI4_MCLK IMXRT_PADCFG(0, 123, 0xc, 0, 260, 0x1) + +#define IOMUXC_PAD_GPIO_B1_06_NETC_PINMUX_ETH1_RX_DV IMXRT_PADCFG(0, 124, 0x0, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_B1_06_ADC2_CONV_D06 IMXRT_PADCFG(0, 124, 0x1, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_B1_06_LPUART9_TX IMXRT_PADCFG(0, 124, 0x2, 0, 139, 0x1) +#define IOMUXC_PAD_GPIO_B1_06_QTIMER3_TIMER0 IMXRT_PADCFG(0, 124, 0x3, 0, 244, 0x2) +#define IOMUXC_PAD_GPIO_B1_06_XBAR1_XBAR_INOUT32 IMXRT_PADCFG(0, 124, 0x4, 0, 310, 0x1) +#define IOMUXC_PAD_GPIO_B1_06_GPIO6_IO06 IMXRT_PADCFG(0, 124, 0x5, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_B1_06_TPM6_CH00 IMXRT_PADCFG(0, 124, 0x6, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_B1_06_FLEXSPI1_BUS2BIT_B_DATA07 IMXRT_PADCFG(0, 124, 0x7, 0, 50, 0x1) +#define IOMUXC_PAD_GPIO_B1_06_NETC_PINMUX_ETH4_RX_DV IMXRT_PADCFG(0, 124, 0x8, 0, 231, 0x2) +#define IOMUXC_PAD_GPIO_B1_06_SAI4_RX_BCLK IMXRT_PADCFG(0, 124, 0xc, 0, 261, 0x1) + +#define IOMUXC_PAD_GPIO_B1_07_NETC_PINMUX_ETH1_TXD02 IMXRT_PADCFG(0, 125, 0x0, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_B1_07_ADC2_CONV_D07 IMXRT_PADCFG(0, 125, 0x1, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_B1_07_LPUART9_RTS_B IMXRT_PADCFG(0, 125, 0x2, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_B1_07_QTIMER3_TIMER1 IMXRT_PADCFG(0, 125, 0x3, 0, 245, 0x2) +#define IOMUXC_PAD_GPIO_B1_07_XBAR1_XBAR_INOUT33 IMXRT_PADCFG(0, 125, 0x4, 0, 311, 0x1) +#define IOMUXC_PAD_GPIO_B1_07_GPIO6_IO07 IMXRT_PADCFG(0, 125, 0x5, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_B1_07_TPM6_CH01 IMXRT_PADCFG(0, 125, 0x6, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_B1_07_FLEXSPI1_BUS2BIT_B_DATA06 IMXRT_PADCFG(0, 125, 0x7, 0, 49, 0x1) +#define IOMUXC_PAD_GPIO_B1_07_NETC_PINMUX_ETH4_TXD02 IMXRT_PADCFG(0, 125, 0x8, 0, 232, 0x2) +#define IOMUXC_PAD_GPIO_B1_07_LPSPI6_SDI IMXRT_PADCFG(0, 125, 0x9, 0, 113, 0x2) +#define IOMUXC_PAD_GPIO_B1_07_SAI4_RX_SYNC IMXRT_PADCFG(0, 125, 0xc, 0, 264, 0x1) + +#define IOMUXC_PAD_GPIO_B1_08_NETC_PINMUX_ETH1_TXD03 IMXRT_PADCFG(0, 126, 0x0, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_B1_08_ADC2_CONV_RDY_CLK IMXRT_PADCFG(0, 126, 0x1, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_B1_08_USDHC1_CD_B IMXRT_PADCFG(0, 126, 0x2, 0, 289, 0x1) +#define IOMUXC_PAD_GPIO_B1_08_QTIMER3_TIMER2 IMXRT_PADCFG(0, 126, 0x3, 0, 246, 0x1) +#define IOMUXC_PAD_GPIO_B1_08_XBAR1_XBAR_INOUT36 IMXRT_PADCFG(0, 126, 0x4, 0, 314, 0x1) +#define IOMUXC_PAD_GPIO_B1_08_GPIO6_IO08 IMXRT_PADCFG(0, 126, 0x5, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_B1_08_TPM6_CH02 IMXRT_PADCFG(0, 126, 0x6, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_B1_08_FLEXSPI1_BUS2BIT_B_DATA05 IMXRT_PADCFG(0, 126, 0x7, 0, 48, 0x1) +#define IOMUXC_PAD_GPIO_B1_08_NETC_PINMUX_ETH4_TXD03 IMXRT_PADCFG(0, 126, 0x8, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_B1_08_LPSPI6_SDO IMXRT_PADCFG(0, 126, 0x9, 0, 114, 0x2) +#define IOMUXC_PAD_GPIO_B1_08_SAI4_TX_BCLK IMXRT_PADCFG(0, 126, 0xc, 0, 265, 0x1) + +#define IOMUXC_PAD_GPIO_B1_09_NETC_PINMUX_ETH1_RXD02 IMXRT_PADCFG(0, 127, 0x0, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_B1_09_USDHC1_WP IMXRT_PADCFG(0, 127, 0x2, 0, 290, 0x1) +#define IOMUXC_PAD_GPIO_B1_09_QTIMER4_TIMER0 IMXRT_PADCFG(0, 127, 0x3, 0, 247, 0x2) +#define IOMUXC_PAD_GPIO_B1_09_XBAR1_XBAR_INOUT37 IMXRT_PADCFG(0, 127, 0x4, 0, 315, 0x1) +#define IOMUXC_PAD_GPIO_B1_09_GPIO6_IO09 IMXRT_PADCFG(0, 127, 0x5, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_B1_09_TPM6_CH03 IMXRT_PADCFG(0, 127, 0x6, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_B1_09_FLEXSPI1_BUS2BIT_B_DATA04 IMXRT_PADCFG(0, 127, 0x7, 0, 47, 0x1) +#define IOMUXC_PAD_GPIO_B1_09_NETC_PINMUX_ETH4_RXD02 IMXRT_PADCFG(0, 127, 0x8, 0, 235, 0x2) +#define IOMUXC_PAD_GPIO_B1_09_LPSPI6_PCS1 IMXRT_PADCFG(0, 127, 0x9, 0, 109, 0x2) +#define IOMUXC_PAD_GPIO_B1_09_SAI4_TX_SYNC IMXRT_PADCFG(0, 127, 0xc, 0, 266, 0x1) + +#define IOMUXC_PAD_GPIO_B1_10_NETC_PINMUX_ETH1_RXD03 IMXRT_PADCFG(0, 128, 0x0, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_B1_10_USDHC1_RESET_B IMXRT_PADCFG(0, 128, 0x2, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_B1_10_QTIMER4_TIMER1 IMXRT_PADCFG(0, 128, 0x3, 0, 248, 0x2) +#define IOMUXC_PAD_GPIO_B1_10_XBAR1_XBAR_INOUT34 IMXRT_PADCFG(0, 128, 0x4, 0, 312, 0x1) +#define IOMUXC_PAD_GPIO_B1_10_GPIO6_IO10 IMXRT_PADCFG(0, 128, 0x5, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_B1_10_FLEXSPI1_BUS2BIT_B_DATA03 IMXRT_PADCFG(0, 128, 0x7, 0, 46, 0x1) +#define IOMUXC_PAD_GPIO_B1_10_NETC_PINMUX_ETH4_RXD03 IMXRT_PADCFG(0, 128, 0x8, 0, 236, 0x2) +#define IOMUXC_PAD_GPIO_B1_10_LPSPI6_PCS2 IMXRT_PADCFG(0, 128, 0x9, 0, 110, 0x2) +#define IOMUXC_PAD_GPIO_B1_10_SAI4_TX_DATA00 IMXRT_PADCFG(0, 128, 0xc, 0, IMXRT_PADCFG_NO_DSYIDX, 0) + +#define IOMUXC_PAD_GPIO_B1_11_NETC_PINMUX_ETH1_RX_CLK IMXRT_PADCFG(0, 129, 0x0, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_B1_11_QTIMER4_TIMER2 IMXRT_PADCFG(0, 129, 0x3, 0, 249, 0x1) +#define IOMUXC_PAD_GPIO_B1_11_XBAR1_XBAR_INOUT35 IMXRT_PADCFG(0, 129, 0x4, 0, 313, 0x1) +#define IOMUXC_PAD_GPIO_B1_11_GPIO6_IO11 IMXRT_PADCFG(0, 129, 0x5, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_B1_11_FLEXSPI1_BUS2BIT_B_DATA02 IMXRT_PADCFG(0, 129, 0x7, 0, 45, 0x1) +#define IOMUXC_PAD_GPIO_B1_11_NETC_PINMUX_ETH4_RX_CLK IMXRT_PADCFG(0, 129, 0x8, 0, 230, 0x2) +#define IOMUXC_PAD_GPIO_B1_11_LPSPI6_PCS3 IMXRT_PADCFG(0, 129, 0x9, 0, 111, 0x1) +#define IOMUXC_PAD_GPIO_B1_11_SAI4_TX_DATA01 IMXRT_PADCFG(0, 129, 0xc, 0, IMXRT_PADCFG_NO_DSYIDX, 0) + +#define IOMUXC_PAD_GPIO_B1_12_NETC_PINMUX_ETH1_RX_ER IMXRT_PADCFG(0, 130, 0x0, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_B1_12_NETC_EMDIO IMXRT_PADCFG(0, 130, 0x1, 0, 190, 0x6) +#define IOMUXC_PAD_GPIO_B1_12_GPIO6_IO12 IMXRT_PADCFG(0, 130, 0x5, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_B1_12_FLEXSPI1_BUS2BIT_B_DATA01 IMXRT_PADCFG(0, 130, 0x7, 0, 44, 0x1) +#define IOMUXC_PAD_GPIO_B1_12_NETC_PINMUX_ETH4_RX_ER IMXRT_PADCFG(0, 130, 0x8, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_B1_12_LPSPI6_PCS0 IMXRT_PADCFG(0, 130, 0x9, 0, 108, 0x2) +#define IOMUXC_PAD_GPIO_B1_12_SAI4_TX_DATA02 IMXRT_PADCFG(0, 130, 0xc, 0, IMXRT_PADCFG_NO_DSYIDX, 0) + +#define IOMUXC_PAD_GPIO_B1_13_NETC_PINMUX_ETH1_TX_ER IMXRT_PADCFG(0, 131, 0x0, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_B1_13_NETC_EMDC IMXRT_PADCFG(0, 131, 0x1, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_B1_13_USDHC1_VSELECT IMXRT_PADCFG(0, 131, 0x2, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_B1_13_CCM_ENET_REF_CLK_25M IMXRT_PADCFG(0, 131, 0x3, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_B1_13_GPIO6_IO13 IMXRT_PADCFG(0, 131, 0x5, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_B1_13_FLEXSPI1_BUS2BIT_B_DATA00 IMXRT_PADCFG(0, 131, 0x7, 0, 43, 0x1) +#define IOMUXC_PAD_GPIO_B1_13_NETC_PINMUX_ETH4_TX_ER IMXRT_PADCFG(0, 131, 0x8, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_B1_13_LPSPI6_SCK IMXRT_PADCFG(0, 131, 0x9, 0, 112, 0x2) +#define IOMUXC_PAD_GPIO_B1_13_SAI4_TX_DATA03 IMXRT_PADCFG(0, 131, 0xc, 0, IMXRT_PADCFG_NO_DSYIDX, 0) + +#define IOMUXC_PAD_GPIO_B2_00_NETC_ETH1_CRS IMXRT_PADCFG(0, 132, 0x0, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_B2_00_SEMC_CSX03 IMXRT_PADCFG(0, 132, 0x1, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_B2_00_LPIT3_TRIGGER00 IMXRT_PADCFG(0, 132, 0x2, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_B2_00_SAI4_MCLK IMXRT_PADCFG(0, 132, 0x4, 0, 260, 0x2) +#define IOMUXC_PAD_GPIO_B2_00_GPIO6_IO14 IMXRT_PADCFG(0, 132, 0x5, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_B2_00_NETC_ETH4_CRS IMXRT_PADCFG(0, 132, 0x8, 0, 200, 0x2) +#define IOMUXC_PAD_GPIO_B2_00_LPSPI6_SDI IMXRT_PADCFG(0, 132, 0x9, 0, 113, 0x3) +#define IOMUXC_PAD_GPIO_B2_00_NETC_ETH2_SLV_MDIO IMXRT_PADCFG(0, 132, 0xa, 0, 194, 0x2) +#define IOMUXC_PAD_GPIO_B2_00_ECAT_CLK_ECAT_CLK25 IMXRT_PADCFG(0, 132, 0xc, 0, IMXRT_PADCFG_NO_DSYIDX, 0) + +#define IOMUXC_PAD_GPIO_B2_01_NETC_ETH1_COL IMXRT_PADCFG(0, 133, 0x0, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_B2_01_LPIT3_TRIGGER01 IMXRT_PADCFG(0, 133, 0x2, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_B2_01_SAI4_TX_BCLK IMXRT_PADCFG(0, 133, 0x4, 0, 265, 0x2) +#define IOMUXC_PAD_GPIO_B2_01_GPIO6_IO15 IMXRT_PADCFG(0, 133, 0x5, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_B2_01_FLEXSPI1_BUS2BIT_A_SS1_B IMXRT_PADCFG(0, 133, 0x6, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_B2_01_NETC_ETH4_COL IMXRT_PADCFG(0, 133, 0x8, 0, 199, 0x2) +#define IOMUXC_PAD_GPIO_B2_01_LPSPI6_SDO IMXRT_PADCFG(0, 133, 0x9, 0, 114, 0x3) +#define IOMUXC_PAD_GPIO_B2_01_NETC_ETH2_SLV_MDC IMXRT_PADCFG(0, 133, 0xa, 0, 193, 0x2) +#define IOMUXC_PAD_GPIO_B2_01_NETC_PINMUX_ETH2_RX_ER IMXRT_PADCFG(0, 133, 0xb, 0, 216, 0x1) +#define IOMUXC_PAD_GPIO_B2_01_ECAT_RX_ER_1 IMXRT_PADCFG(0, 133, 0xc, 0, 16, 0x2) + +#define IOMUXC_PAD_GPIO_B2_02_LPIT3_TRIGGER02 IMXRT_PADCFG(0, 134, 0x2, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_B2_02_NETC_EMDIO IMXRT_PADCFG(0, 134, 0x3, 0, 190, 0x7) +#define IOMUXC_PAD_GPIO_B2_02_SAI4_TX_SYNC IMXRT_PADCFG(0, 134, 0x4, 0, 266, 0x2) +#define IOMUXC_PAD_GPIO_B2_02_GPIO6_IO16 IMXRT_PADCFG(0, 134, 0x5, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_B2_02_FLEXSPI1_BUS2BIT_B_SCLK IMXRT_PADCFG(0, 134, 0x6, 0, 51, 0x2) +#define IOMUXC_PAD_GPIO_B2_02_CCM_ENET_REF_CLK_25M IMXRT_PADCFG(0, 134, 0x9, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_B2_02_EWM_EWM_OUT_B IMXRT_PADCFG(0, 134, 0xa, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_B2_02_NETC_PINMUX_ETH2_RXD02 IMXRT_PADCFG(0, 134, 0xb, 0, 219, 0x2) +#define IOMUXC_PAD_GPIO_B2_02_ECAT_RX_DATA2_1 IMXRT_PADCFG(0, 134, 0xc, 0, 10, 0x1) + +#define IOMUXC_PAD_GPIO_B2_03_LPIT3_TRIGGER03 IMXRT_PADCFG(0, 135, 0x2, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_B2_03_NETC_EMDC IMXRT_PADCFG(0, 135, 0x3, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_B2_03_SAI4_TX_DATA00 IMXRT_PADCFG(0, 135, 0x4, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_B2_03_GPIO6_IO17 IMXRT_PADCFG(0, 135, 0x5, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_B2_03_FLEXSPI1_BUS2BIT_A_DATA04 IMXRT_PADCFG(0, 135, 0x7, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_B2_03_XSPI_SLV_DATA04 IMXRT_PADCFG(0, 135, 0xa, 0, 350, 0x2) +#define IOMUXC_PAD_GPIO_B2_03_NETC_PINMUX_ETH2_RXD03 IMXRT_PADCFG(0, 135, 0xb, 0, 220, 0x2) +#define IOMUXC_PAD_GPIO_B2_03_ECAT_RX_DATA3_1 IMXRT_PADCFG(0, 135, 0xc, 0, 12, 0x1) + +#define IOMUXC_PAD_GPIO_B2_04_SINC1_MOD_CLK0 IMXRT_PADCFG(0, 136, 0x0, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_B2_04_SINC2_MOD_CLK0 IMXRT_PADCFG(0, 136, 0x1, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_B2_04_SINC3_MOD_CLK0 IMXRT_PADCFG(0, 136, 0x2, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_B2_04_SAI4_RX_SYNC IMXRT_PADCFG(0, 136, 0x4, 0, 264, 0x2) +#define IOMUXC_PAD_GPIO_B2_04_GPIO6_IO18 IMXRT_PADCFG(0, 136, 0x5, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_B2_04_FLEXSPI1_BUS2BIT_A_DATA05 IMXRT_PADCFG(0, 136, 0x7, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_B2_04_TPM3_EXTCLK IMXRT_PADCFG(0, 136, 0x8, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_B2_04_XSPI_SLV_DATA05 IMXRT_PADCFG(0, 136, 0xa, 0, 351, 0x2) +#define IOMUXC_PAD_GPIO_B2_04_NETC_PINMUX_ETH2_TXD02 IMXRT_PADCFG(0, 136, 0xb, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_B2_04_ECAT_TX_DATA2_1 IMXRT_PADCFG(0, 136, 0xc, 0, IMXRT_PADCFG_NO_DSYIDX, 0) + +#define IOMUXC_PAD_GPIO_B2_05_SINC1_MOD_CLK1 IMXRT_PADCFG(0, 137, 0x0, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_B2_05_SINC2_MOD_CLK1 IMXRT_PADCFG(0, 137, 0x1, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_B2_05_SINC3_MOD_CLK1 IMXRT_PADCFG(0, 137, 0x2, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_B2_05_SAI4_RX_BCLK IMXRT_PADCFG(0, 137, 0x4, 0, 261, 0x2) +#define IOMUXC_PAD_GPIO_B2_05_GPIO6_IO19 IMXRT_PADCFG(0, 137, 0x5, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_B2_05_MIC_CLK IMXRT_PADCFG(0, 137, 0x6, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_B2_05_FLEXSPI1_BUS2BIT_A_DATA06 IMXRT_PADCFG(0, 137, 0x7, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_B2_05_TPM3_CH00 IMXRT_PADCFG(0, 137, 0x8, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_B2_05_XSPI_SLV_DATA06 IMXRT_PADCFG(0, 137, 0xa, 0, 352, 0x2) +#define IOMUXC_PAD_GPIO_B2_05_NETC_PINMUX_ETH2_TXD03 IMXRT_PADCFG(0, 137, 0xb, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_B2_05_ECAT_TX_DATA3_1 IMXRT_PADCFG(0, 137, 0xc, 0, IMXRT_PADCFG_NO_DSYIDX, 0) + +#define IOMUXC_PAD_GPIO_B2_06_SINC1_MOD_CLK2 IMXRT_PADCFG(0, 138, 0x0, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_B2_06_SINC2_MOD_CLK2 IMXRT_PADCFG(0, 138, 0x1, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_B2_06_SINC3_MOD_CLK2 IMXRT_PADCFG(0, 138, 0x2, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_B2_06_LPUART6_DSR_B IMXRT_PADCFG(0, 138, 0x3, 0, 131, 0x1) +#define IOMUXC_PAD_GPIO_B2_06_SAI4_RX_DATA00 IMXRT_PADCFG(0, 138, 0x4, 0, 262, 0x2) +#define IOMUXC_PAD_GPIO_B2_06_GPIO6_IO20 IMXRT_PADCFG(0, 138, 0x5, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_B2_06_FLEXSPI1_BUS2BIT_A_DATA07 IMXRT_PADCFG(0, 138, 0x7, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_B2_06_TPM3_CH01 IMXRT_PADCFG(0, 138, 0x8, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_B2_06_LPUART11_TX IMXRT_PADCFG(0, 138, 0x9, 0, 118, 0x2) +#define IOMUXC_PAD_GPIO_B2_06_XSPI_SLV_DATA07 IMXRT_PADCFG(0, 138, 0xa, 0, 353, 0x2) +#define IOMUXC_PAD_GPIO_B2_06_NETC_PINMUX_ETH2_TXD00 IMXRT_PADCFG(0, 138, 0xb, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_B2_06_ECAT_TX_DATA0_1 IMXRT_PADCFG(0, 138, 0xc, 0, IMXRT_PADCFG_NO_DSYIDX, 0) + +#define IOMUXC_PAD_GPIO_B2_07_QTIMER5_TIMER0 IMXRT_PADCFG(0, 139, 0x0, 0, 250, 0x2) +#define IOMUXC_PAD_GPIO_B2_07_LPUART6_DCD_B IMXRT_PADCFG(0, 139, 0x3, 0, 130, 0x1) +#define IOMUXC_PAD_GPIO_B2_07_SAI4_TX_DATA01 IMXRT_PADCFG(0, 139, 0x4, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_B2_07_GPIO6_IO21 IMXRT_PADCFG(0, 139, 0x5, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_B2_07_SAI4_RX_DATA01 IMXRT_PADCFG(0, 139, 0x6, 0, 263, 0x1) +#define IOMUXC_PAD_GPIO_B2_07_FLEXSPI1_BUS2BIT_A_DQS IMXRT_PADCFG(0, 139, 0x7, 0, 41, 0x1) +#define IOMUXC_PAD_GPIO_B2_07_TPM3_CH02 IMXRT_PADCFG(0, 139, 0x8, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_B2_07_LPUART11_RX IMXRT_PADCFG(0, 139, 0x9, 0, 117, 0x2) +#define IOMUXC_PAD_GPIO_B2_07_XSPI_SLV_DQS IMXRT_PADCFG(0, 139, 0xa, 0, 345, 0x1) +#define IOMUXC_PAD_GPIO_B2_07_NETC_PINMUX_ETH2_TXD01 IMXRT_PADCFG(0, 139, 0xb, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_B2_07_ECAT_TX_DATA1_1 IMXRT_PADCFG(0, 139, 0xc, 0, IMXRT_PADCFG_NO_DSYIDX, 0) + +#define IOMUXC_PAD_GPIO_B2_08_QTIMER5_TIMER1 IMXRT_PADCFG(0, 140, 0x0, 0, 251, 0x2) +#define IOMUXC_PAD_GPIO_B2_08_SINC2_EMCLK02 IMXRT_PADCFG(0, 140, 0x1, 0, 280, 0x2) +#define IOMUXC_PAD_GPIO_B2_08_LPUART6_RI_B IMXRT_PADCFG(0, 140, 0x4, 0, 132, 0x1) +#define IOMUXC_PAD_GPIO_B2_08_GPIO6_IO22 IMXRT_PADCFG(0, 140, 0x5, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_B2_08_LPI2C6_SCL IMXRT_PADCFG(0, 140, 0x6, 0, 88, 0x1) +#define IOMUXC_PAD_GPIO_B2_08_FLEXSPI1_BUS2BIT_A_SCLK IMXRT_PADCFG(0, 140, 0x7, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_B2_08_TPM3_CH03 IMXRT_PADCFG(0, 140, 0x8, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_B2_08_SPDIF_IN IMXRT_PADCFG(0, 140, 0x9, 0, 282, 0x2) +#define IOMUXC_PAD_GPIO_B2_08_XSPI_SLV_CLK IMXRT_PADCFG(0, 140, 0xa, 0, 354, 0x2) +#define IOMUXC_PAD_GPIO_B2_08_NETC_PINMUX_ETH2_TX_EN IMXRT_PADCFG(0, 140, 0xb, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_B2_08_ECAT_TX_EN_1 IMXRT_PADCFG(0, 140, 0xc, 0, IMXRT_PADCFG_NO_DSYIDX, 0) + +#define IOMUXC_PAD_GPIO_B2_09_QTIMER5_TIMER2 IMXRT_PADCFG(0, 141, 0x0, 0, 252, 0x1) +#define IOMUXC_PAD_GPIO_B2_09_SINC2_EMBIT02 IMXRT_PADCFG(0, 141, 0x1, 0, 277, 0x2) +#define IOMUXC_PAD_GPIO_B2_09_LPUART6_DTR_B IMXRT_PADCFG(0, 141, 0x4, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_B2_09_GPIO6_IO23 IMXRT_PADCFG(0, 141, 0x5, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_B2_09_LPI2C6_SDA IMXRT_PADCFG(0, 141, 0x6, 0, 89, 0x1) +#define IOMUXC_PAD_GPIO_B2_09_FLEXSPI1_BUS2BIT_A_SS0_B IMXRT_PADCFG(0, 141, 0x7, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_B2_09_TPM4_EXTCLK IMXRT_PADCFG(0, 141, 0x8, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_B2_09_SPDIF_OUT IMXRT_PADCFG(0, 141, 0x9, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_B2_09_XSPI_SLV_CS IMXRT_PADCFG(0, 141, 0xa, 0, 344, 0x2) +#define IOMUXC_PAD_GPIO_B2_09_NETC_PINMUX_ETH2_TX_CLK IMXRT_PADCFG(0, 141, 0xb, 0, 221, 0x2) +#define IOMUXC_PAD_GPIO_B2_09_ECAT_TX_CLK_1 IMXRT_PADCFG(0, 141, 0xc, 0, 18, 0x2) + +#define IOMUXC_PAD_GPIO_B2_10_MIC_BITSTREAM00 IMXRT_PADCFG(0, 142, 0x0, 0, 140, 0x3) +#define IOMUXC_PAD_GPIO_B2_10_SINC2_EMCLK03 IMXRT_PADCFG(0, 142, 0x1, 0, 281, 0x1) +#define IOMUXC_PAD_GPIO_B2_10_CAN3_TX IMXRT_PADCFG(0, 142, 0x2, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_B2_10_LPUART8_CTS_B IMXRT_PADCFG(0, 142, 0x3, 0, 135, 0x1) +#define IOMUXC_PAD_GPIO_B2_10_LPUART6_TX IMXRT_PADCFG(0, 142, 0x4, 0, 134, 0x2) +#define IOMUXC_PAD_GPIO_B2_10_GPIO6_IO24 IMXRT_PADCFG(0, 142, 0x5, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_B2_10_LPI2C4_SCL IMXRT_PADCFG(0, 142, 0x6, 0, 84, 0x1) +#define IOMUXC_PAD_GPIO_B2_10_FLEXSPI1_BUS2BIT_A_DATA00 IMXRT_PADCFG(0, 142, 0x7, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_B2_10_TPM4_CH00 IMXRT_PADCFG(0, 142, 0x8, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_B2_10_LPSPI4_SCK IMXRT_PADCFG(0, 142, 0x9, 0, 98, 0x2) +#define IOMUXC_PAD_GPIO_B2_10_XSPI_SLV_DATA00 IMXRT_PADCFG(0, 142, 0xa, 0, 346, 0x1) +#define IOMUXC_PAD_GPIO_B2_10_NETC_PINMUX_ETH2_RXD00 IMXRT_PADCFG(0, 142, 0xb, 0, 217, 0x2) +#define IOMUXC_PAD_GPIO_B2_10_ECAT_RX_DATA0_1 IMXRT_PADCFG(0, 142, 0xc, 0, 6, 0x2) + +#define IOMUXC_PAD_GPIO_B2_11_MIC_BITSTREAM01 IMXRT_PADCFG(0, 143, 0x0, 0, 141, 0x3) +#define IOMUXC_PAD_GPIO_B2_11_SINC2_EMBIT03 IMXRT_PADCFG(0, 143, 0x1, 0, 278, 0x1) +#define IOMUXC_PAD_GPIO_B2_11_CAN3_RX IMXRT_PADCFG(0, 143, 0x2, 0, 2, 0x1) +#define IOMUXC_PAD_GPIO_B2_11_LPUART8_RTS_B IMXRT_PADCFG(0, 143, 0x3, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_B2_11_LPUART6_RX IMXRT_PADCFG(0, 143, 0x4, 0, 133, 0x2) +#define IOMUXC_PAD_GPIO_B2_11_GPIO6_IO25 IMXRT_PADCFG(0, 143, 0x5, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_B2_11_LPI2C4_SDA IMXRT_PADCFG(0, 143, 0x6, 0, 85, 0x1) +#define IOMUXC_PAD_GPIO_B2_11_FLEXSPI1_BUS2BIT_A_DATA01 IMXRT_PADCFG(0, 143, 0x7, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_B2_11_TPM4_CH01 IMXRT_PADCFG(0, 143, 0x8, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_B2_11_LPSPI4_SDI IMXRT_PADCFG(0, 143, 0x9, 0, 99, 0x2) +#define IOMUXC_PAD_GPIO_B2_11_XSPI_SLV_DATA01 IMXRT_PADCFG(0, 143, 0xa, 0, 347, 0x1) +#define IOMUXC_PAD_GPIO_B2_11_NETC_PINMUX_ETH2_RXD01 IMXRT_PADCFG(0, 143, 0xb, 0, 218, 0x2) +#define IOMUXC_PAD_GPIO_B2_11_ECAT_RX_DATA1_1 IMXRT_PADCFG(0, 143, 0xc, 0, 8, 0x2) + +#define IOMUXC_PAD_GPIO_B2_12_MIC_BITSTREAM02 IMXRT_PADCFG(0, 144, 0x0, 0, 142, 0x3) +#define IOMUXC_PAD_GPIO_B2_12_SINC_FILTER_GLUE2_BREAK IMXRT_PADCFG(0, 144, 0x1, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_B2_12_LPUART8_TX IMXRT_PADCFG(0, 144, 0x2, 0, 137, 0x2) +#define IOMUXC_PAD_GPIO_B2_12_LPUART6_CTS_B IMXRT_PADCFG(0, 144, 0x4, 0, 129, 0x2) +#define IOMUXC_PAD_GPIO_B2_12_GPIO6_IO26 IMXRT_PADCFG(0, 144, 0x5, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_B2_12_CAN3_TX IMXRT_PADCFG(0, 144, 0x6, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_B2_12_FLEXSPI1_BUS2BIT_A_DATA02 IMXRT_PADCFG(0, 144, 0x7, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_B2_12_TPM4_CH02 IMXRT_PADCFG(0, 144, 0x8, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_B2_12_LPSPI4_SDO IMXRT_PADCFG(0, 144, 0x9, 0, 100, 0x2) +#define IOMUXC_PAD_GPIO_B2_12_XSPI_SLV_DATA02 IMXRT_PADCFG(0, 144, 0xa, 0, 348, 0x1) +#define IOMUXC_PAD_GPIO_B2_12_NETC_PINMUX_ETH2_RX_DV IMXRT_PADCFG(0, 144, 0xb, 0, 215, 0x2) +#define IOMUXC_PAD_GPIO_B2_12_ECAT_RX_DV_1 IMXRT_PADCFG(0, 144, 0xc, 0, 14, 0x2) + +#define IOMUXC_PAD_GPIO_B2_13_MIC_BITSTREAM03 IMXRT_PADCFG(0, 145, 0x0, 0, 143, 0x3) +#define IOMUXC_PAD_GPIO_B2_13_SINC2_EMCLK00 IMXRT_PADCFG(0, 145, 0x1, 0, 279, 0x1) +#define IOMUXC_PAD_GPIO_B2_13_LPUART8_RX IMXRT_PADCFG(0, 145, 0x2, 0, 136, 0x2) +#define IOMUXC_PAD_GPIO_B2_13_LPUART6_RTS_B IMXRT_PADCFG(0, 145, 0x4, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_B2_13_GPIO6_IO27 IMXRT_PADCFG(0, 145, 0x5, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_B2_13_CAN3_RX IMXRT_PADCFG(0, 145, 0x6, 0, 2, 0x2) +#define IOMUXC_PAD_GPIO_B2_13_FLEXSPI1_BUS2BIT_A_DATA03 IMXRT_PADCFG(0, 145, 0x7, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_B2_13_TPM4_CH03 IMXRT_PADCFG(0, 145, 0x8, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_B2_13_LPSPI4_PCS0 IMXRT_PADCFG(0, 145, 0x9, 0, 97, 0x2) +#define IOMUXC_PAD_GPIO_B2_13_XSPI_SLV_DATA03 IMXRT_PADCFG(0, 145, 0xa, 0, 349, 0x1) +#define IOMUXC_PAD_GPIO_B2_13_NETC_PINMUX_ETH2_RX_CLK IMXRT_PADCFG(0, 145, 0xb, 0, 214, 0x3) +#define IOMUXC_PAD_GPIO_B2_13_ECAT_RX_CLK_1 IMXRT_PADCFG(0, 145, 0xc, 0, 4, 0x1) + +#define IOMUXC_PAD_GPIO_AON_00_SRC_BOOT_MODE00 IMXRT_PADCFG(1, 0, 0x0, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_AON_00_CAN1_TX IMXRT_PADCFG(1, 0, 0x1, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_AON_00_LPTMR1_ALT1 IMXRT_PADCFG(1, 0, 0x4, 1, 17, 0x0) +#define IOMUXC_PAD_GPIO_AON_00_GPIO1_IO00 IMXRT_PADCFG(1, 0, 0x5, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_AON_00_LPUART2_TX IMXRT_PADCFG(1, 0, 0x6, 1, 28, 0x0) +#define IOMUXC_PAD_GPIO_AON_00_TPM1_EXTCLK IMXRT_PADCFG(1, 0, 0x8, 0, IMXRT_PADCFG_NO_DSYIDX, 0) + +#define IOMUXC_PAD_GPIO_AON_01_SRC_BOOT_MODE01 IMXRT_PADCFG(1, 1, 0x0, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_AON_01_CAN1_RX IMXRT_PADCFG(1, 1, 0x1, 0, 0, 0x1) +#define IOMUXC_PAD_GPIO_AON_01_LPTMR1_ALT2 IMXRT_PADCFG(1, 1, 0x4, 1, 18, 0x0) +#define IOMUXC_PAD_GPIO_AON_01_GPIO1_IO01 IMXRT_PADCFG(1, 1, 0x5, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_AON_01_LPUART2_RX IMXRT_PADCFG(1, 1, 0x6, 1, 27, 0x0) +#define IOMUXC_PAD_GPIO_AON_01_TPM1_CH00 IMXRT_PADCFG(1, 1, 0x8, 0, IMXRT_PADCFG_NO_DSYIDX, 0) + +#define IOMUXC_PAD_GPIO_AON_02_SRC_BOOT_MODE02 IMXRT_PADCFG(1, 2, 0x0, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_AON_02_CAN3_TX IMXRT_PADCFG(1, 2, 0x1, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_AON_02_LPSPI2_PCS3 IMXRT_PADCFG(1, 2, 0x2, 1, 13, 0x0) +#define IOMUXC_PAD_GPIO_AON_02_LPSPI2_SDO IMXRT_PADCFG(1, 2, 0x3, 1, 16, 0x0) +#define IOMUXC_PAD_GPIO_AON_02_LPTMR1_ALT3 IMXRT_PADCFG(1, 2, 0x4, 1, 19, 0x0) +#define IOMUXC_PAD_GPIO_AON_02_GPIO1_IO02 IMXRT_PADCFG(1, 2, 0x5, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_AON_02_LPUART2_RTS_B IMXRT_PADCFG(1, 2, 0x6, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_AON_02_TPM1_CH01 IMXRT_PADCFG(1, 2, 0x8, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_AON_02_ECAT_CLK_ECAT_CLK25 IMXRT_PADCFG(1, 2, 0xc, 0, IMXRT_PADCFG_NO_DSYIDX, 0) + +#define IOMUXC_PAD_GPIO_AON_03_CAN3_RX IMXRT_PADCFG(1, 3, 0x1, 0, 2, 0x3) +#define IOMUXC_PAD_GPIO_AON_03_LPSPI1_PCS1 IMXRT_PADCFG(1, 3, 0x2, 1, 7, 0x0) +#define IOMUXC_PAD_GPIO_AON_03_LPSPI2_SDI IMXRT_PADCFG(1, 3, 0x3, 1, 15, 0x0) +#define IOMUXC_PAD_GPIO_AON_03_LPSPI1_PCS3 IMXRT_PADCFG(1, 3, 0x4, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_AON_03_GPIO1_IO03 IMXRT_PADCFG(1, 3, 0x5, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_AON_03_LPUART2_CTS_B IMXRT_PADCFG(1, 3, 0x6, 1, 26, 0x0) +#define IOMUXC_PAD_GPIO_AON_03_TPM1_CH02 IMXRT_PADCFG(1, 3, 0x8, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_AON_03_ECAT_LED_STATE_RUN IMXRT_PADCFG(1, 3, 0xc, 0, IMXRT_PADCFG_NO_DSYIDX, 0) + +#define IOMUXC_PAD_GPIO_AON_04_LPSPI1_SCK IMXRT_PADCFG(1, 4, 0x0, 1, 8, 0x0) +#define IOMUXC_PAD_GPIO_AON_04_SAI1_TX_DATA00 IMXRT_PADCFG(1, 4, 0x2, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_AON_04_SAI1_RX_DATA01 IMXRT_PADCFG(1, 4, 0x3, 1, 35, 0x0) +#define IOMUXC_PAD_GPIO_AON_04_GPIO1_IO04 IMXRT_PADCFG(1, 4, 0x5, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_AON_04_LPUART7_CTS_B IMXRT_PADCFG(1, 4, 0x6, 1, 29, 0x0) +#define IOMUXC_PAD_GPIO_AON_04_TPM1_CH03 IMXRT_PADCFG(1, 4, 0x8, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_AON_04_ECAT_LED_RUN IMXRT_PADCFG(1, 4, 0xc, 0, IMXRT_PADCFG_NO_DSYIDX, 0) + +#define IOMUXC_PAD_GPIO_AON_05_LPSPI1_PCS0 IMXRT_PADCFG(1, 5, 0x0, 1, 6, 0x0) +#define IOMUXC_PAD_GPIO_AON_05_SAI1_TX_SYNC IMXRT_PADCFG(1, 5, 0x2, 1, 38, 0x0) +#define IOMUXC_PAD_GPIO_AON_05_GPIO1_IO05 IMXRT_PADCFG(1, 5, 0x5, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_AON_05_LPUART7_RTS_B IMXRT_PADCFG(1, 5, 0x6, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_AON_05_NMI_GLUE_NMI IMXRT_PADCFG(1, 5, 0x7, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_AON_05_ECAT_LED_ERR IMXRT_PADCFG(1, 5, 0xc, 0, IMXRT_PADCFG_NO_DSYIDX, 0) + +#define IOMUXC_PAD_GPIO_AON_06_LPSPI1_SDO IMXRT_PADCFG(1, 6, 0x0, 1, 10, 0x0) +#define IOMUXC_PAD_GPIO_AON_06_I3C1_PUR IMXRT_PADCFG(1, 6, 0x1, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_AON_06_SAI1_TX_BCLK IMXRT_PADCFG(1, 6, 0x2, 1, 37, 0x0) +#define IOMUXC_PAD_GPIO_AON_06_LPI2C1_SDA IMXRT_PADCFG(1, 6, 0x3, 1, 3, 0x0) +#define IOMUXC_PAD_GPIO_AON_06_GPIO1_IO06 IMXRT_PADCFG(1, 6, 0x5, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_AON_06_CAN1_TX IMXRT_PADCFG(1, 6, 0x6, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_AON_06_ECAT_SDA IMXRT_PADCFG(1, 6, 0xc, 0, 20, 0x1) + +#define IOMUXC_PAD_GPIO_AON_07_LPSPI1_SDI IMXRT_PADCFG(1, 7, 0x0, 1, 9, 0x0) +#define IOMUXC_PAD_GPIO_AON_07_SAI1_MCLK IMXRT_PADCFG(1, 7, 0x2, 1, 32, 0x0) +#define IOMUXC_PAD_GPIO_AON_07_LPI2C1_SCL IMXRT_PADCFG(1, 7, 0x3, 1, 2, 0x0) +#define IOMUXC_PAD_GPIO_AON_07_GPIO1_IO07 IMXRT_PADCFG(1, 7, 0x5, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_AON_07_CAN1_RX IMXRT_PADCFG(1, 7, 0x6, 0, 0, 0x2) +#define IOMUXC_PAD_GPIO_AON_07_ECAT_SCL IMXRT_PADCFG(1, 7, 0xc, 0, IMXRT_PADCFG_NO_DSYIDX, 0) + +#define IOMUXC_PAD_GPIO_AON_08_LPUART1_TX IMXRT_PADCFG(1, 8, 0x0, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_AON_08_S400_TX IMXRT_PADCFG(1, 8, 0x1, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_AON_08_SAI1_RX_DATA00 IMXRT_PADCFG(1, 8, 0x2, 1, 34, 0x0) +#define IOMUXC_PAD_GPIO_AON_08_SAI1_TX_DATA01 IMXRT_PADCFG(1, 8, 0x3, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_AON_08_GPIO1_IO08 IMXRT_PADCFG(1, 8, 0x5, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_AON_08_LPI2C1_SDA IMXRT_PADCFG(1, 8, 0x6, 1, 3, 0x1) +#define IOMUXC_PAD_GPIO_AON_08_LPSPI1_PCS1 IMXRT_PADCFG(1, 8, 0x8, 1, 7, 0x1) +#define IOMUXC_PAD_GPIO_AON_08_ECAT_LINK_ACT00 IMXRT_PADCFG(1, 8, 0xc, 0, IMXRT_PADCFG_NO_DSYIDX, 0) + +#define IOMUXC_PAD_GPIO_AON_09_LPUART1_RX IMXRT_PADCFG(1, 9, 0x0, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_AON_09_S400_RX IMXRT_PADCFG(1, 9, 0x1, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_AON_09_SAI1_RX_BCLK IMXRT_PADCFG(1, 9, 0x2, 1, 33, 0x0) +#define IOMUXC_PAD_GPIO_AON_09_LPIT1_TRIGGER00 IMXRT_PADCFG(1, 9, 0x3, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_AON_09_GPIO1_IO09 IMXRT_PADCFG(1, 9, 0x5, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_AON_09_LPI2C1_SCL IMXRT_PADCFG(1, 9, 0x6, 1, 2, 0x1) +#define IOMUXC_PAD_GPIO_AON_09_LPSPI1_PCS2 IMXRT_PADCFG(1, 9, 0x8, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_AON_09_ECAT_LINK_ACT01 IMXRT_PADCFG(1, 9, 0xc, 0, IMXRT_PADCFG_NO_DSYIDX, 0) + +#define IOMUXC_PAD_GPIO_AON_10_JTAG_MUX_TRSTB IMXRT_PADCFG(1, 10, 0x0, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_AON_10_LPSPI2_PCS0 IMXRT_PADCFG(1, 10, 0x1, 1, 11, 0x0) +#define IOMUXC_PAD_GPIO_AON_10_SAI1_RX_SYNC IMXRT_PADCFG(1, 10, 0x2, 1, 36, 0x0) +#define IOMUXC_PAD_GPIO_AON_10_LPIT1_TRIGGER01 IMXRT_PADCFG(1, 10, 0x3, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_AON_10_TPM2_EXTCLK IMXRT_PADCFG(1, 10, 0x4, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_AON_10_GPIO1_IO10 IMXRT_PADCFG(1, 10, 0x5, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_AON_10_LPI2C1_SCLS IMXRT_PADCFG(1, 10, 0x6, 0, IMXRT_PADCFG_NO_DSYIDX, 0) + +#define IOMUXC_PAD_GPIO_AON_11_JTAG_MUX_TDO IMXRT_PADCFG(1, 11, 0x0, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_AON_11_LPUART1_CTS_B IMXRT_PADCFG(1, 11, 0x2, 1, 20, 0x0) +#define IOMUXC_PAD_GPIO_AON_11_LPIT1_TRIGGER02 IMXRT_PADCFG(1, 11, 0x3, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_AON_11_TPM2_CH00 IMXRT_PADCFG(1, 11, 0x4, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_AON_11_GPIO1_IO11 IMXRT_PADCFG(1, 11, 0x5, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_AON_11_LPI2C1_SDAS IMXRT_PADCFG(1, 11, 0x6, 0, IMXRT_PADCFG_NO_DSYIDX, 0) + +#define IOMUXC_PAD_GPIO_AON_12_JTAG_MUX_TDI IMXRT_PADCFG(1, 12, 0x0, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_AON_12_LPUART1_RTS_B IMXRT_PADCFG(1, 12, 0x2, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_AON_12_LPIT1_TRIGGER03 IMXRT_PADCFG(1, 12, 0x3, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_AON_12_TPM2_CH01 IMXRT_PADCFG(1, 12, 0x4, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_AON_12_GPIO1_IO12 IMXRT_PADCFG(1, 12, 0x5, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_AON_12_LPI2C1_HREQ IMXRT_PADCFG(1, 12, 0x6, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_AON_12_LPSPI1_SCK IMXRT_PADCFG(1, 12, 0x8, 1, 8, 0x1) + +#define IOMUXC_PAD_GPIO_AON_13_JTAG_MUX_TCK IMXRT_PADCFG(1, 13, 0x0, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_AON_13_LPUART12_CTS_B IMXRT_PADCFG(1, 13, 0x2, 1, 23, 0x0) +#define IOMUXC_PAD_GPIO_AON_13_LPUART1_DSR_B IMXRT_PADCFG(1, 13, 0x3, 1, 22, 0x0) +#define IOMUXC_PAD_GPIO_AON_13_TPM2_CH02 IMXRT_PADCFG(1, 13, 0x4, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_AON_13_GPIO1_IO13 IMXRT_PADCFG(1, 13, 0x5, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_AON_13_LPTMR1_ALT1 IMXRT_PADCFG(1, 13, 0x6, 1, 17, 0x1) +#define IOMUXC_PAD_GPIO_AON_13_LPSPI1_PCS0 IMXRT_PADCFG(1, 13, 0x8, 1, 6, 0x1) + +#define IOMUXC_PAD_GPIO_AON_14_JTAG_MUX_TMS IMXRT_PADCFG(1, 14, 0x0, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_AON_14_LPUART12_RTS_B IMXRT_PADCFG(1, 14, 0x2, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_AON_14_LPUART1_DCD_B IMXRT_PADCFG(1, 14, 0x3, 1, 21, 0x0) +#define IOMUXC_PAD_GPIO_AON_14_TPM2_CH03 IMXRT_PADCFG(1, 14, 0x4, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_AON_14_GPIO1_IO14 IMXRT_PADCFG(1, 14, 0x5, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_AON_14_LPTMR1_ALT2 IMXRT_PADCFG(1, 14, 0x6, 1, 18, 0x1) +#define IOMUXC_PAD_GPIO_AON_14_LPSPI1_SDO IMXRT_PADCFG(1, 14, 0x8, 1, 10, 0x1) + +#define IOMUXC_PAD_GPIO_AON_15_FLEXSPI2_BUS2BIT_B_DATA03 IMXRT_PADCFG(1, 15, 0x0, 0, 61, 0x2) +#define IOMUXC_PAD_GPIO_AON_15_LPSPI2_PCS1 IMXRT_PADCFG(1, 15, 0x1, 1, 12, 0x0) +#define IOMUXC_PAD_GPIO_AON_15_LPUART12_TX IMXRT_PADCFG(1, 15, 0x2, 1, 25, 0x0) +#define IOMUXC_PAD_GPIO_AON_15_LPUART1_RI_B IMXRT_PADCFG(1, 15, 0x3, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_AON_15_LPI2C2_SDA IMXRT_PADCFG(1, 15, 0x4, 1, 5, 0x0) +#define IOMUXC_PAD_GPIO_AON_15_GPIO1_IO15 IMXRT_PADCFG(1, 15, 0x5, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_AON_15_LPTMR1_ALT3 IMXRT_PADCFG(1, 15, 0x6, 1, 19, 0x1) +#define IOMUXC_PAD_GPIO_AON_15_LPSPI1_SDI IMXRT_PADCFG(1, 15, 0x8, 1, 9, 0x1) +#define IOMUXC_PAD_GPIO_AON_15_I3C1_SDA IMXRT_PADCFG(1, 15, 0x9, 1, 1, 0x0) + +#define IOMUXC_PAD_GPIO_AON_16_FLEXSPI2_BUS2BIT_B_DATA02 IMXRT_PADCFG(1, 16, 0x0, 0, 60, 0x2) +#define IOMUXC_PAD_GPIO_AON_16_LPSPI2_PCS0 IMXRT_PADCFG(1, 16, 0x1, 1, 11, 0x1) +#define IOMUXC_PAD_GPIO_AON_16_LPUART12_RX IMXRT_PADCFG(1, 16, 0x2, 1, 24, 0x0) +#define IOMUXC_PAD_GPIO_AON_16_LPUART1_DTR_B IMXRT_PADCFG(1, 16, 0x3, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_AON_16_LPI2C2_SCL IMXRT_PADCFG(1, 16, 0x4, 1, 4, 0x0) +#define IOMUXC_PAD_GPIO_AON_16_GPIO1_IO16 IMXRT_PADCFG(1, 16, 0x5, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_AON_16_CAN1_TX IMXRT_PADCFG(1, 16, 0x6, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_AON_16_LPUART7_CTS_B IMXRT_PADCFG(1, 16, 0x8, 1, 29, 0x1) +#define IOMUXC_PAD_GPIO_AON_16_I3C1_SCL IMXRT_PADCFG(1, 16, 0x9, 1, 0, 0x0) + +#define IOMUXC_PAD_GPIO_AON_17_FLEXSPI2_BUS2BIT_B_DATA01 IMXRT_PADCFG(1, 17, 0x0, 0, 59, 0x2) +#define IOMUXC_PAD_GPIO_AON_17_LPSPI2_SDI IMXRT_PADCFG(1, 17, 0x1, 1, 15, 0x1) +#define IOMUXC_PAD_GPIO_AON_17_LPUART7_TX IMXRT_PADCFG(1, 17, 0x2, 1, 31, 0x0) +#define IOMUXC_PAD_GPIO_AON_17_LPI2C2_SDA IMXRT_PADCFG(1, 17, 0x3, 1, 5, 0x1) +#define IOMUXC_PAD_GPIO_AON_17_LPUART1_DSR_B IMXRT_PADCFG(1, 17, 0x4, 1, 22, 0x1) +#define IOMUXC_PAD_GPIO_AON_17_GPIO1_IO17 IMXRT_PADCFG(1, 17, 0x5, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_AON_17_CAN1_RX IMXRT_PADCFG(1, 17, 0x6, 0, 0, 0x3) + +#define IOMUXC_PAD_GPIO_AON_18_FLEXSPI2_BUS2BIT_B_DATA00 IMXRT_PADCFG(1, 18, 0x0, 0, 58, 0x2) +#define IOMUXC_PAD_GPIO_AON_18_LPSPI2_SDO IMXRT_PADCFG(1, 18, 0x1, 1, 16, 0x1) +#define IOMUXC_PAD_GPIO_AON_18_LPUART7_RX IMXRT_PADCFG(1, 18, 0x2, 1, 30, 0x0) +#define IOMUXC_PAD_GPIO_AON_18_LPI2C2_SCL IMXRT_PADCFG(1, 18, 0x3, 1, 4, 0x1) +#define IOMUXC_PAD_GPIO_AON_18_LPUART1_DCD_B IMXRT_PADCFG(1, 18, 0x4, 1, 21, 0x1) +#define IOMUXC_PAD_GPIO_AON_18_GPIO1_IO18 IMXRT_PADCFG(1, 18, 0x5, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_AON_18_CAN3_TX IMXRT_PADCFG(1, 18, 0x6, 0, IMXRT_PADCFG_NO_DSYIDX, 0) + +#define IOMUXC_PAD_GPIO_AON_19_FLEXSPI2_BUS2BIT_B_SCLK IMXRT_PADCFG(1, 19, 0x0, 0, 63, 0x1) +#define IOMUXC_PAD_GPIO_AON_19_LPSPI2_SCK IMXRT_PADCFG(1, 19, 0x1, 1, 14, 0x0) +#define IOMUXC_PAD_GPIO_AON_19_FLEXSPI2_BUS2BIT_A_SS1_B IMXRT_PADCFG(1, 19, 0x3, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_AON_19_LPUART1_CTS_B IMXRT_PADCFG(1, 19, 0x4, 1, 20, 0x1) +#define IOMUXC_PAD_GPIO_AON_19_GPIO1_IO19 IMXRT_PADCFG(1, 19, 0x5, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_AON_19_CAN3_RX IMXRT_PADCFG(1, 19, 0x6, 0, 2, 0x4) +#define IOMUXC_PAD_GPIO_AON_19_LPUART7_RTS_B IMXRT_PADCFG(1, 19, 0x8, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_AON_19_LPUART12_TX IMXRT_PADCFG(1, 19, 0x9, 1, 25, 0x1) +#define IOMUXC_PAD_GPIO_AON_19_ADC1_CONV_D00 IMXRT_PADCFG(1, 19, 0xc, 0, IMXRT_PADCFG_NO_DSYIDX, 0) + +#define IOMUXC_PAD_GPIO_AON_20_FLEXSPI2_BUS2BIT_B_DQS IMXRT_PADCFG(1, 20, 0x0, 0, 53, 0x2) +#define IOMUXC_PAD_GPIO_AON_20_FLEXSPI2_BUS2BIT_A_SS1_B IMXRT_PADCFG(1, 20, 0x1, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_AON_20_LPI2C1_SDA IMXRT_PADCFG(1, 20, 0x2, 1, 3, 0x2) +#define IOMUXC_PAD_GPIO_AON_20_I3C1_SDA IMXRT_PADCFG(1, 20, 0x3, 1, 1, 0x1) +#define IOMUXC_PAD_GPIO_AON_20_LPUART1_RTS_B IMXRT_PADCFG(1, 20, 0x4, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_AON_20_GPIO1_IO20 IMXRT_PADCFG(1, 20, 0x5, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_AON_20_LPUART12_RX IMXRT_PADCFG(1, 20, 0x9, 1, 24, 0x1) +#define IOMUXC_PAD_GPIO_AON_20_ADC1_CONV_D01 IMXRT_PADCFG(1, 20, 0xc, 0, IMXRT_PADCFG_NO_DSYIDX, 0) + +#define IOMUXC_PAD_GPIO_AON_21_FLEXSPI2_BUS2BIT_B_SS0_B IMXRT_PADCFG(1, 21, 0x0, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_AON_21_LPSPI2_PCS1 IMXRT_PADCFG(1, 21, 0x1, 1, 12, 0x1) +#define IOMUXC_PAD_GPIO_AON_21_LPI2C1_SCL IMXRT_PADCFG(1, 21, 0x2, 1, 2, 0x2) +#define IOMUXC_PAD_GPIO_AON_21_I3C1_SCL IMXRT_PADCFG(1, 21, 0x3, 1, 0, 0x1) +#define IOMUXC_PAD_GPIO_AON_21_SAI1_TX_DATA00 IMXRT_PADCFG(1, 21, 0x4, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_AON_21_GPIO1_IO21 IMXRT_PADCFG(1, 21, 0x5, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_AON_21_FLEXSPI2_BUS2BIT_A_DQS IMXRT_PADCFG(1, 21, 0x8, 0, 52, 0x1) +#define IOMUXC_PAD_GPIO_AON_21_SAI1_RX_DATA01 IMXRT_PADCFG(1, 21, 0x9, 1, 35, 0x1) +#define IOMUXC_PAD_GPIO_AON_21_ADC1_CONV_D02 IMXRT_PADCFG(1, 21, 0xc, 0, IMXRT_PADCFG_NO_DSYIDX, 0) + +#define IOMUXC_PAD_GPIO_AON_22_FLEXSPI2_BUS2BIT_A_SS0_B IMXRT_PADCFG(1, 22, 0x0, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_AON_22_LPI2C2_SDA IMXRT_PADCFG(1, 22, 0x1, 1, 5, 0x2) +#define IOMUXC_PAD_GPIO_AON_22_LPUART7_TX IMXRT_PADCFG(1, 22, 0x2, 1, 31, 0x1) +#define IOMUXC_PAD_GPIO_AON_22_LPUART12_CTS_B IMXRT_PADCFG(1, 22, 0x3, 1, 23, 0x1) +#define IOMUXC_PAD_GPIO_AON_22_SAI1_TX_SYNC IMXRT_PADCFG(1, 22, 0x4, 1, 38, 0x1) +#define IOMUXC_PAD_GPIO_AON_22_GPIO1_IO22 IMXRT_PADCFG(1, 22, 0x5, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_AON_22_LPSPI2_SCK IMXRT_PADCFG(1, 22, 0x6, 1, 14, 0x1) +#define IOMUXC_PAD_GPIO_AON_22_CCMSRCGPC_CCMOBS1 IMXRT_PADCFG(1, 22, 0xa, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_AON_22_ADC1_CONV_D03 IMXRT_PADCFG(1, 22, 0xc, 0, IMXRT_PADCFG_NO_DSYIDX, 0) + +#define IOMUXC_PAD_GPIO_AON_23_FLEXSPI2_BUS2BIT_A_SCLK IMXRT_PADCFG(1, 23, 0x0, 0, 62, 0x1) +#define IOMUXC_PAD_GPIO_AON_23_LPI2C2_SCL IMXRT_PADCFG(1, 23, 0x1, 1, 4, 0x2) +#define IOMUXC_PAD_GPIO_AON_23_LPUART7_RX IMXRT_PADCFG(1, 23, 0x2, 1, 30, 0x1) +#define IOMUXC_PAD_GPIO_AON_23_LPUART12_RTS_B IMXRT_PADCFG(1, 23, 0x3, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_AON_23_SAI1_TX_BCLK IMXRT_PADCFG(1, 23, 0x4, 1, 37, 0x1) +#define IOMUXC_PAD_GPIO_AON_23_GPIO1_IO23 IMXRT_PADCFG(1, 23, 0x5, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_AON_23_LPSPI2_SDO IMXRT_PADCFG(1, 23, 0x6, 1, 16, 0x2) +#define IOMUXC_PAD_GPIO_AON_23_CCMSRCGPC_CCMOBS2 IMXRT_PADCFG(1, 23, 0xa, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_AON_23_ADC1_CONV_D04 IMXRT_PADCFG(1, 23, 0xc, 0, IMXRT_PADCFG_NO_DSYIDX, 0) + +#define IOMUXC_PAD_GPIO_AON_24_FLEXSPI2_BUS2BIT_A_DATA00 IMXRT_PADCFG(1, 24, 0x0, 0, 54, 0x1) +#define IOMUXC_PAD_GPIO_AON_24_LPI2C1_SDA IMXRT_PADCFG(1, 24, 0x1, 1, 3, 0x3) +#define IOMUXC_PAD_GPIO_AON_24_LPUART2_RTS_B IMXRT_PADCFG(1, 24, 0x2, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_AON_24_LPUART7_CTS_B IMXRT_PADCFG(1, 24, 0x3, 1, 29, 0x2) +#define IOMUXC_PAD_GPIO_AON_24_SAI1_MCLK IMXRT_PADCFG(1, 24, 0x4, 1, 32, 0x1) +#define IOMUXC_PAD_GPIO_AON_24_GPIO1_IO24 IMXRT_PADCFG(1, 24, 0x5, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_AON_24_LPSPI2_SDI IMXRT_PADCFG(1, 24, 0x6, 1, 15, 0x2) +#define IOMUXC_PAD_GPIO_AON_24_ADC1_CONV_D05 IMXRT_PADCFG(1, 24, 0xc, 0, IMXRT_PADCFG_NO_DSYIDX, 0) + +#define IOMUXC_PAD_GPIO_AON_25_FLEXSPI2_BUS2BIT_A_DATA01 IMXRT_PADCFG(1, 25, 0x0, 0, 55, 0x1) +#define IOMUXC_PAD_GPIO_AON_25_LPI2C1_SCL IMXRT_PADCFG(1, 25, 0x1, 1, 2, 0x3) +#define IOMUXC_PAD_GPIO_AON_25_LPUART2_CTS_B IMXRT_PADCFG(1, 25, 0x2, 1, 26, 0x1) +#define IOMUXC_PAD_GPIO_AON_25_LPUART7_RTS_B IMXRT_PADCFG(1, 25, 0x3, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_AON_25_SAI1_RX_DATA00 IMXRT_PADCFG(1, 25, 0x4, 1, 34, 0x1) +#define IOMUXC_PAD_GPIO_AON_25_GPIO1_IO25 IMXRT_PADCFG(1, 25, 0x5, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_AON_25_LPSPI2_PCS0 IMXRT_PADCFG(1, 25, 0x6, 1, 11, 0x2) +#define IOMUXC_PAD_GPIO_AON_25_SAI1_TX_DATA01 IMXRT_PADCFG(1, 25, 0x7, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_AON_25_ADC1_CONV_D06 IMXRT_PADCFG(1, 25, 0xc, 0, IMXRT_PADCFG_NO_DSYIDX, 0) + +#define IOMUXC_PAD_GPIO_AON_26_FLEXSPI2_BUS2BIT_A_DATA02 IMXRT_PADCFG(1, 26, 0x0, 0, 56, 0x1) +#define IOMUXC_PAD_GPIO_AON_26_LPSPI2_PCS2 IMXRT_PADCFG(1, 26, 0x1, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_AON_26_LPUART2_TX IMXRT_PADCFG(1, 26, 0x2, 1, 28, 0x1) +#define IOMUXC_PAD_GPIO_AON_26_SAI1_RX_BCLK IMXRT_PADCFG(1, 26, 0x4, 1, 33, 0x1) +#define IOMUXC_PAD_GPIO_AON_26_GPIO1_IO26 IMXRT_PADCFG(1, 26, 0x5, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_AON_26_ADC1_CONV_D07 IMXRT_PADCFG(1, 26, 0xc, 0, IMXRT_PADCFG_NO_DSYIDX, 0) + +#define IOMUXC_PAD_GPIO_AON_27_FLEXSPI2_BUS2BIT_A_DATA03 IMXRT_PADCFG(1, 27, 0x0, 0, 57, 0x1) +#define IOMUXC_PAD_GPIO_AON_27_LPSPI2_PCS3 IMXRT_PADCFG(1, 27, 0x1, 1, 13, 0x1) +#define IOMUXC_PAD_GPIO_AON_27_LPUART2_RX IMXRT_PADCFG(1, 27, 0x2, 1, 27, 0x1) +#define IOMUXC_PAD_GPIO_AON_27_SAI1_RX_SYNC IMXRT_PADCFG(1, 27, 0x4, 1, 36, 0x1) +#define IOMUXC_PAD_GPIO_AON_27_GPIO1_IO27 IMXRT_PADCFG(1, 27, 0x5, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_AON_27_EWM_EWM_OUT_B IMXRT_PADCFG(1, 27, 0x7, 0, IMXRT_PADCFG_NO_DSYIDX, 0) +#define IOMUXC_PAD_GPIO_AON_27_ADC1_CONV_RDY_CLK IMXRT_PADCFG(1, 27, 0xc, 0, IMXRT_PADCFG_NO_DSYIDX, 0) + +#define IOMUXC_PAD_GPIO_AON_28_DUMMY_FLEXSPI2_BUS2BIT_A_DQS IMXRT_PADCFG(1, 28, 0x0, 0, 52, 0x2) +#define IOMUXC_PAD_GPIO_AON_28_DUMMY_FLEXSPI2_BUS2BIT_B_DQS IMXRT_PADCFG(1, 28, 0x1, 0, 53, 0x3) +#define IOMUXC_PAD_GPIO_AON_28_DUMMY_GPIO1_IO28 IMXRT_PADCFG(1, 28, 0x5, 0, IMXRT_PADCFG_NO_DSYIDX, 0) + +#endif /* __ARCH_ARM_SRC_IMXRT_HARDWARE_RT118X_IMXRT118X_PINMUX_H */ \ No newline at end of file diff --git a/arch/arm/src/imxrt/hardware/rt118x/imxrt118x_trdc.h b/arch/arm/src/imxrt/hardware/rt118x/imxrt118x_trdc.h new file mode 100644 index 0000000000000..7eed42efa677f --- /dev/null +++ b/arch/arm/src/imxrt/hardware/rt118x/imxrt118x_trdc.h @@ -0,0 +1,73 @@ +/**************************************************************************** + * arch/arm/src/imxrt/hardware/rt118x/imxrt118x_trdc.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_IMXRT_HARDWARE_RT118X_IMXRT118X_TRDC_H +#define __ARCH_ARM_SRC_IMXRT_HARDWARE_RT118X_IMXRT118X_TRDC_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* RT1180 has three TRDC instances; the bases live in + * imxrt118x_memorymap.h. + * + * TRDC1 -> AONMIX (0x44270000) + * TRDC2 -> WAKEUPMIX / MEGAMIX (0x42460000) + * TRDC3 -> NETC / media (0x42810000) + * + * The HWCFG0 offset and the MBC/MRC register offsets below are from the + * RT1180 TRDC register layout. + */ + +#define IMXRT_TRDC_HWCFG0_OFFSET 0xf0 + +#define IMXRT_MBC0_MEM_GLBAC(n) (0x20 + (n << 2)) +#define IMXRT_MBC_MEM_BLK_CFG_0(m, n) (0x200 * m + 0x40 + (n << 2)) +#define IMXRT_MBC_MEM_BLK_CFG_I(m, n, i) \ + (0x200 * m + 0x40 + (80 << 2) + (i - 1) * 0x28 + (n << 2)) +#define IMXRT_MRC0_DOM_RGD_W(m, n) (0x100 * m + 0x40 + (n << 3)) + +/* Fused-off peripheral filtering is not ported: RT1180 exposes no equivalent + * FSB shadow at a known-good offset here, and nothing in this port depends + * on it. The fuse-handling code is therefore omitted rather than left + * half-wired. + */ + +#define DID_NUM 16 +#define MBC_MAX_NUM 4 +#define MRC_MAX_NUM 2 +#define MBC_NUM(HWCFG) ((HWCFG >> 16) & 0xF) +#define MRC_NUM(HWCFG) ((HWCFG >> 24) & 0x1F) + +#define MBC_BLK_NUM(GLBCFG) (GLBCFG & 0x3FF) +#define MRC_RGN_NUM(GLBCFG) (GLBCFG & 0x1F) + +#define GLBAC_SETTING_MASK (0x7777) +#define GLBAC_LOCK_MASK BIT(31) + +#endif /* __ARCH_ARM_SRC_IMXRT_HARDWARE_RT118X_IMXRT118X_TRDC_H */ diff --git a/arch/arm/src/imxrt/hardware/rt118x/imxrt118x_xbar.h b/arch/arm/src/imxrt/hardware/rt118x/imxrt118x_xbar.h new file mode 100644 index 0000000000000..ba1267fe74e6c --- /dev/null +++ b/arch/arm/src/imxrt/hardware/rt118x/imxrt118x_xbar.h @@ -0,0 +1,917 @@ +/**************************************************************************** + * arch/arm/src/imxrt/hardware/rt118x/imxrt118x_xbar.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_IMXRT_HARDWARE_RT118X_IMXRT118X_XBAR_H +#define __ARCH_ARM_SRC_IMXRT_HARDWARE_RT118X_IMXRT118X_XBAR_H + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Inter-Peripheral Crossbar Switch (XBAR) for i.MX RT1180 (IMXRT1180RM + * Ch. 78). Three instances are present: + * + * XBAR1 base 0x4275_0000 216 inputs, 221 outputs (SEL0..SEL110) + * XBAR2 base 0x4276_0000 178 inputs, 32 outputs (SEL0..SEL15) + * XBAR3 base 0x4277_0000 178 inputs, 32 outputs (SEL0..SEL15) + * + * All three instances use full 8-bit select fields. + */ + +#define IMXRT_XBAR_SEL_MASKS {0xff, 0xff, 0xff} + +/* IMXRT_XBARn_BASE constants live in the RT1180 memory map + * (hardware/rt118x/imxrt118x_memorymap.h). + */ + +/**************************************************************************** + * XBAR Input Assignments (IMXRT1180RM Table 14) + ****************************************************************************/ + +#define IMXRT_XBAR1_IN_GND IMXRT_XBAR1(XBAR_INPUT, 0) /* XBAR1_IN0 <- - GND */ +#define IMXRT_XBAR1_IN_1B1 IMXRT_XBAR1(XBAR_INPUT, 1) /* XBAR1_IN1 <- - 1'B1 */ +#define IMXRT_XBAR1_IN_GND_2 IMXRT_XBAR1(XBAR_INPUT, 2) /* XBAR1_IN2 <- - GND */ +#define IMXRT_XBAR1_IN_1B1_2 IMXRT_XBAR1(XBAR_INPUT, 3) /* XBAR1_IN3 <- - 1'B1 */ +#define IMXRT_XBAR1_IN_IOMUX_XBAR_INOUT04 IMXRT_XBAR1(XBAR_INPUT, 4) /* XBAR1_IN4 <- - SW_MUX_CTL_PAD_GPIO_EMC_B1_ 00[MUX_MODE] = 0x1 */ +#define IMXRT_XBAR1_IN_IOMUX_XBAR_INOUT05 IMXRT_XBAR1(XBAR_INPUT, 5) /* XBAR1_IN5 <- - SW_MUX_CTL_PAD_GPIO_EMC_B1_ 01[MUX_MODE] = 0x1 */ +#define IMXRT_XBAR1_IN_IOMUX_XBAR_INOUT06 IMXRT_XBAR1(XBAR_INPUT, 6) /* XBAR1_IN6 <- - SW_MUX_CTL_PAD_GPIO_EMC_B1_ 02[MUX_MODE] = 0x1 */ +#define IMXRT_XBAR1_IN_IOMUX_XBAR_INOUT07 IMXRT_XBAR1(XBAR_INPUT, 7) /* XBAR1_IN7 <- - SW_MUX_CTL_PAD_GPIO_EMC_B1_ 03[MUX_MODE] = 0x1 */ +#define IMXRT_XBAR1_IN_IOMUX_XBAR_INOUT08 IMXRT_XBAR1(XBAR_INPUT, 8) /* XBAR1_IN8 <- - SW_MUX_CTL_PAD_GPIO_EMC_B1_ 04[MUX_MODE] = 0x1 */ +#define IMXRT_XBAR1_IN_IOMUX_XBAR_INOUT09 IMXRT_XBAR1(XBAR_INPUT, 9) /* XBAR1_IN9 <- - SW_MUX_CTL_PAD_GPIO_EMC_B1_ 05[MUX_MODE] = 0x1 */ +#define IMXRT_XBAR1_IN_IOMUX_XBAR_INOUT10 IMXRT_XBAR1(XBAR_INPUT, 10) /* XBAR1_IN10 <- - SW_MUX_CTL_PAD_GPIO_EMC_B1_ 26[MUX_MODE] = 0x2 */ +#define IMXRT_XBAR1_IN_IOMUX_XBAR_INOUT11 IMXRT_XBAR1(XBAR_INPUT, 11) /* XBAR1_IN11 <- - SW_MUX_CTL_PAD_GPIO_EMC_B1_ 27[MUX_MODE] = 0x2 */ +#define IMXRT_XBAR1_IN_IOMUX_XBAR_INOUT12 IMXRT_XBAR1(XBAR_INPUT, 12) /* XBAR1_IN12 <- - SW_MUX_CTL_PAD_GPIO_EMC_B1_ 28[MUX_MODE] = 0x2 */ +#define IMXRT_XBAR1_IN_IOMUX_XBAR_INOUT13 IMXRT_XBAR1(XBAR_INPUT, 13) /* XBAR1_IN13 <- - SW_MUX_CTL_PAD_GPIO_EMC_B1_ 29[MUX_MODE] = 0x2 */ +#define IMXRT_XBAR1_IN_IOMUX_XBAR_INOUT14 IMXRT_XBAR1(XBAR_INPUT, 14) /* XBAR1_IN14 <- - SW_MUX_CTL_PAD_GPIO_EMC_B2_ 16[MUX_MODE] = 0x6 */ +#define IMXRT_XBAR1_IN_IOMUX_XBAR_INOUT15 IMXRT_XBAR1(XBAR_INPUT, 15) /* XBAR1_IN15 <- - SW_MUX_CTL_PAD_GPIO_EMC_B2_ 17[MUX_MODE] = 0x6 */ +#define IMXRT_XBAR1_IN_IOMUX_XBAR_INOUT16 IMXRT_XBAR1(XBAR_INPUT, 16) /* XBAR1_IN16 <- - SW_MUX_CTL_PAD_GPIO_EMC_B2_ 18[MUX_MODE] = 0x6 */ +#define IMXRT_XBAR1_IN_IOMUX_XBAR_INOUT17 IMXRT_XBAR1(XBAR_INPUT, 17) /* XBAR1_IN17 <- - SW_MUX_CTL_PAD_GPIO_AD_33[MU See IOMUX Controller X_MODE] = */ +#define IMXRT_XBAR1_IN_IOMUX_XBAR_INOUT18 IMXRT_XBAR1(XBAR_INPUT, 18) /* XBAR1_IN18 <- - SW_MUX_CTL_PAD_GPIO_AD_12[MU See IOMUX Controller X_MODE] = */ +#define IMXRT_XBAR1_IN_IOMUX_XBAR_INOUT19 IMXRT_XBAR1(XBAR_INPUT, 19) /* XBAR1_IN19 <- - SW_MUX_CTL_PAD_GPIO_AD_19[MU See IOMUX Controller X_MODE] = */ +#define IMXRT_XBAR1_IN_IOMUX_XBAR_INOUT20 IMXRT_XBAR1(XBAR_INPUT, 20) /* XBAR1_IN20 <- - SW_MUX_CTL_PAD_GPIO_EMC_B2_ 00[MUX_MODE] = 0x6 */ +#define IMXRT_XBAR1_IN_IOMUX_XBAR_INOUT21 IMXRT_XBAR1(XBAR_INPUT, 21) /* XBAR1_IN21 <- - SW_MUX_CTL_PAD_GPIO_EMC_B2_ 01[MUX_MODE] = 0x6 */ +#define IMXRT_XBAR1_IN_IOMUX_XBAR_INOUT22 IMXRT_XBAR1(XBAR_INPUT, 22) /* XBAR1_IN22 <- - SW_MUX_CTL_PAD_GPIO_EMC_B2_ 02[MUX_MODE] = 0x6 */ +#define IMXRT_XBAR1_IN_IOMUX_XBAR_INOUT23 IMXRT_XBAR1(XBAR_INPUT, 23) /* XBAR1_IN23 <- - SW_MUX_CTL_PAD_GPIO_EMC_B2_ 03[MUX_MODE] = 0x6 */ +#define IMXRT_XBAR1_IN_IOMUX_XBAR_INOUT24 IMXRT_XBAR1(XBAR_INPUT, 24) /* XBAR1_IN24 <- - SW_MUX_CTL_PAD_GPIO_EMC_B2_ 04[MUX_MODE] = 0x6 */ +#define IMXRT_XBAR1_IN_IOMUX_XBAR_INOUT25 IMXRT_XBAR1(XBAR_INPUT, 25) /* XBAR1_IN25 <- - SW_MUX_CTL_PAD_GPIO_EMC_B2_ 05[MUX_MODE] = 0x6 */ +#define IMXRT_XBAR1_IN_IOMUX_XBAR_INOUT26 IMXRT_XBAR1(XBAR_INPUT, 26) /* XBAR1_IN26 <- - SW_MUX_CTL_PAD_GPIO_EMC_B2_ 06[MUX_MODE] = 0x6 */ +#define IMXRT_XBAR1_IN_IOMUX_XBAR_INOUT27 IMXRT_XBAR1(XBAR_INPUT, 27) /* XBAR1_IN27 <- - SW_MUX_CTL_PAD_GPIO_EMC_B2_ 07[MUX_MODE] = 0x6 */ +#define IMXRT_XBAR1_IN_IOMUX_XBAR_INOUT28 IMXRT_XBAR1(XBAR_INPUT, 28) /* XBAR1_IN28 <- - SW_MUX_CTL_PAD_GPIO_EMC_B2_ 08[MUX_MODE] = 0x6 */ +#define IMXRT_XBAR1_IN_IOMUX_XBAR_INOUT29 IMXRT_XBAR1(XBAR_INPUT, 29) /* XBAR1_IN29 <- - SW_MUX_CTL_PAD_GPIO_EMC_B2_ 09[MUX_MODE] = 0x6 */ +#define IMXRT_XBAR1_IN_IOMUX_XBAR_INOUT30 IMXRT_XBAR1(XBAR_INPUT, 30) /* XBAR1_IN30 <- - SW_MUX_CTL_PAD_GPIO_EMC_B2_ 10[MUX_MODE] = 0x6 */ +#define IMXRT_XBAR1_IN_IOMUX_XBAR_INOUT31 IMXRT_XBAR1(XBAR_INPUT, 31) /* XBAR1_IN31 <- - SW_MUX_CTL_PAD_GPIO_EMC_B2_ 11[MUX_MODE] = 0x6 */ +#define IMXRT_XBAR1_IN_IOMUX_XBAR_INOUT32 IMXRT_XBAR1(XBAR_INPUT, 32) /* XBAR1_IN32 <- - SW_MUX_CTL_PAD_GPIO_EMC_B2_ 12[MUX_MODE] = 0x6 */ +#define IMXRT_XBAR1_IN_IOMUX_XBAR_INOUT33 IMXRT_XBAR1(XBAR_INPUT, 33) /* XBAR1_IN33 <- - SW_MUX_CTL_PAD_GPIO_EMC_B2_ 13[MUX_MODE] = 0x6 */ +#define IMXRT_XBAR1_IN_IOMUX_XBAR_INOUT34 IMXRT_XBAR1(XBAR_INPUT, 34) /* XBAR1_IN34 <- - SW_MUX_CTL_PAD_GPIO_EMC_B2_ 14[MUX_MODE] = 0x6 */ +#define IMXRT_XBAR1_IN_IOMUX_XBAR_INOUT35 IMXRT_XBAR1(XBAR_INPUT, 35) /* XBAR1_IN35 <- - SW_MUX_CTL_PAD_GPIO_EMC_B2_ 15[MUX_MODE] = 0x6 */ +#define IMXRT_XBAR1_IN_IOMUX_XBAR_INOUT36 IMXRT_XBAR1(XBAR_INPUT, 36) /* XBAR1_IN36 <- - SW_MUX_CTL_PAD_GPIO_EMC_B2_ 19[MUX_MODE] = 0x6 */ +#define IMXRT_XBAR1_IN_IOMUX_XBAR_INOUT37 IMXRT_XBAR1(XBAR_INPUT, 37) /* XBAR1_IN37 <- - SW_MUX_CTL_PAD_GPIO_EMC_B2_ 20[MUX_MODE] = 0x6 */ +#define IMXRT_XBAR1_IN_CMP1_COUT IMXRT_XBAR1(XBAR_INPUT, 38) /* XBAR1_IN38 <- CMP1 COUT */ +#define IMXRT_XBAR1_IN_CMP2_COUT IMXRT_XBAR1(XBAR_INPUT, 39) /* XBAR1_IN39 <- CMP2 COUT */ +#define IMXRT_XBAR1_IN_CMP3_COUT IMXRT_XBAR1(XBAR_INPUT, 40) /* XBAR1_IN40 <- CMP3 COUT */ +#define IMXRT_XBAR1_IN_CMP4_COUT IMXRT_XBAR1(XBAR_INPUT, 41) /* XBAR1_IN41 <- CMP4 COUT */ +#define IMXRT_XBAR1_IN_TMR1_TMR0_OUTPUT IMXRT_XBAR1(XBAR_INPUT, 42) /* XBAR1_IN42 <- TMR1 TMR0_OUTPUT */ +#define IMXRT_XBAR1_IN_TMR1_TMR1_OUTPUT IMXRT_XBAR1(XBAR_INPUT, 43) /* XBAR1_IN43 <- TMR1 TMR1_OUTPUT */ +#define IMXRT_XBAR1_IN_TMR1_TMR2_OUTPUT IMXRT_XBAR1(XBAR_INPUT, 44) /* XBAR1_IN44 <- TMR1 TMR2_OUTPUT */ +#define IMXRT_XBAR1_IN_TMR1_TMR3_OUTPUT IMXRT_XBAR1(XBAR_INPUT, 45) /* XBAR1_IN45 <- TMR1 TMR3_OUTPUT */ +#define IMXRT_XBAR1_IN_TMR2_TMR0_OUTPUT IMXRT_XBAR1(XBAR_INPUT, 46) /* XBAR1_IN46 <- TMR2 TMR0_OUTPUT */ +#define IMXRT_XBAR1_IN_TMR2_TMR1_OUTPUT IMXRT_XBAR1(XBAR_INPUT, 47) /* XBAR1_IN47 <- TMR2 TMR1_OUTPUT */ +#define IMXRT_XBAR1_IN_TMR2_TMR2_OUTPUT IMXRT_XBAR1(XBAR_INPUT, 48) /* XBAR1_IN48 <- TMR2 TMR2_OUTPUT */ +#define IMXRT_XBAR1_IN_TMR2_TMR3_OUTPUT IMXRT_XBAR1(XBAR_INPUT, 49) /* XBAR1_IN49 <- TMR2 TMR3_OUTPUT */ +#define IMXRT_XBAR1_IN_TMR3_TMR0_OUTPUT IMXRT_XBAR1(XBAR_INPUT, 50) /* XBAR1_IN50 <- TMR3 TMR0_OUTPUT */ +#define IMXRT_XBAR1_IN_TMR3_TMR1_OUTPUT IMXRT_XBAR1(XBAR_INPUT, 51) /* XBAR1_IN51 <- TMR3 TMR1_OUTPUT */ +#define IMXRT_XBAR1_IN_TMR3_TMR2_OUTPUT IMXRT_XBAR1(XBAR_INPUT, 52) /* XBAR1_IN52 <- TMR3 TMR2_OUTPUT */ +#define IMXRT_XBAR1_IN_TMR3_TMR3_OUTPUT IMXRT_XBAR1(XBAR_INPUT, 53) /* XBAR1_IN53 <- TMR3 TMR3_OUTPUT */ +#define IMXRT_XBAR1_IN_TMR4_TMR0_OUTPUT IMXRT_XBAR1(XBAR_INPUT, 54) /* XBAR1_IN54 <- TMR4 TMR0_OUTPUT */ +#define IMXRT_XBAR1_IN_TMR4_TMR1_OUTPUT IMXRT_XBAR1(XBAR_INPUT, 55) /* XBAR1_IN55 <- TMR4 TMR1_OUTPUT */ +#define IMXRT_XBAR1_IN_TMR4_TMR2_OUTPUT IMXRT_XBAR1(XBAR_INPUT, 56) /* XBAR1_IN56 <- TMR4 TMR2_OUTPUT */ +#define IMXRT_XBAR1_IN_TMR4_TMR3_OUTPUT IMXRT_XBAR1(XBAR_INPUT, 57) /* XBAR1_IN57 <- TMR4 TMR3_OUTPUT */ +#define IMXRT_XBAR1_IN_TMR5_TMR0_OUTPUT IMXRT_XBAR1(XBAR_INPUT, 58) /* XBAR1_IN58 <- TMR5 TMR0_OUTPUT */ +#define IMXRT_XBAR1_IN_TMR5_TMR1_OUTPUT IMXRT_XBAR1(XBAR_INPUT, 59) /* XBAR1_IN59 <- TMR5 TMR1_OUTPUT */ +#define IMXRT_XBAR1_IN_TMR5_TMR2_OUTPUT IMXRT_XBAR1(XBAR_INPUT, 60) /* XBAR1_IN60 <- TMR5 TMR2_OUTPUT */ +#define IMXRT_XBAR1_IN_TMR5_TMR3_OUTPUT IMXRT_XBAR1(XBAR_INPUT, 61) /* XBAR1_IN61 <- TMR5 TMR3_OUTPUT */ +#define IMXRT_XBAR1_IN_TMR6_TMR0_OUTPUT IMXRT_XBAR1(XBAR_INPUT, 62) /* XBAR1_IN62 <- TMR6 TMR0_OUTPUT */ +#define IMXRT_XBAR1_IN_TMR6_TMR1_OUTPUT IMXRT_XBAR1(XBAR_INPUT, 63) /* XBAR1_IN63 <- TMR6 TMR1_OUTPUT */ +#define IMXRT_XBAR1_IN_TMR6_TMR2_OUTPUT IMXRT_XBAR1(XBAR_INPUT, 64) /* XBAR1_IN64 <- TMR6 TMR2_OUTPUT */ +#define IMXRT_XBAR1_IN_TMR6_TMR3_OUTPUT IMXRT_XBAR1(XBAR_INPUT, 65) /* XBAR1_IN65 <- TMR6 TMR3_OUTPUT */ +#define IMXRT_XBAR1_IN_TMR7_TMR0_OUTPUT IMXRT_XBAR1(XBAR_INPUT, 66) /* XBAR1_IN66 <- TMR7 TMR0_OUTPUT */ +#define IMXRT_XBAR1_IN_TMR7_TMR1_OUTPUT IMXRT_XBAR1(XBAR_INPUT, 67) /* XBAR1_IN67 <- TMR7 TMR1_OUTPUT */ +#define IMXRT_XBAR1_IN_TMR7_TMR2_OUTPUT IMXRT_XBAR1(XBAR_INPUT, 68) /* XBAR1_IN68 <- TMR7 TMR2_OUTPUT */ +#define IMXRT_XBAR1_IN_TMR7_TMR3_OUTPUT IMXRT_XBAR1(XBAR_INPUT, 69) /* XBAR1_IN69 <- TMR7 TMR3_OUTPUT */ +#define IMXRT_XBAR1_IN_TMR8_TMR0_OUTPUT IMXRT_XBAR1(XBAR_INPUT, 70) /* XBAR1_IN70 <- TMR8 TMR0_OUTPUT */ +#define IMXRT_XBAR1_IN_TMR8_TMR1_OUTPUT IMXRT_XBAR1(XBAR_INPUT, 71) /* XBAR1_IN71 <- TMR8 TMR1_OUTPUT */ +#define IMXRT_XBAR1_IN_TMR8_TMR2_OUTPUT IMXRT_XBAR1(XBAR_INPUT, 72) /* XBAR1_IN72 <- TMR8 TMR2_OUTPUT */ +#define IMXRT_XBAR1_IN_TMR8_TMR3_OUTPUT IMXRT_XBAR1(XBAR_INPUT, 73) /* XBAR1_IN73 <- TMR8 TMR3_OUTPUT */ +#define IMXRT_XBAR1_IN_FLEXPWM1_PWM0_MUX_TRIGGER0 IMXRT_XBAR1(XBAR_INPUT, 74) /* XBAR1_IN74 <- FLEXPWM1 PWM0_MUX_TRIGGER0 */ +#define IMXRT_XBAR1_IN_FLEXPWM1_PWM0_MUX_TRIGGER1 IMXRT_XBAR1(XBAR_INPUT, 75) /* XBAR1_IN75 <- FLEXPWM1 PWM0_MUX_TRIGGER1 */ +#define IMXRT_XBAR1_IN_FLEXPWM1_PWM1_MUX_TRIGGER0 IMXRT_XBAR1(XBAR_INPUT, 76) /* XBAR1_IN76 <- FLEXPWM1 PWM1_MUX_TRIGGER0 */ +#define IMXRT_XBAR1_IN_FLEXPWM1_PWM1_MUX_TRIGGER1 IMXRT_XBAR1(XBAR_INPUT, 77) /* XBAR1_IN77 <- FLEXPWM1 PWM1_MUX_TRIGGER1 */ +#define IMXRT_XBAR1_IN_FLEXPWM1_PWM2_MUX_TRIGGER0 IMXRT_XBAR1(XBAR_INPUT, 78) /* XBAR1_IN78 <- FLEXPWM1 PWM2_MUX_TRIGGER0 */ +#define IMXRT_XBAR1_IN_FLEXPWM1_PWM2_MUX_TRIGGER1 IMXRT_XBAR1(XBAR_INPUT, 79) /* XBAR1_IN79 <- FLEXPWM1 PWM2_MUX_TRIGGER1 */ +#define IMXRT_XBAR1_IN_FLEXPWM1_PWM3_MUX_TRIGGER0 IMXRT_XBAR1(XBAR_INPUT, 80) /* XBAR1_IN80 <- FLEXPWM1 PWM3_MUX_TRIGGER0 */ +#define IMXRT_XBAR1_IN_FLEXPWM1_PWM3_MUX_TRIGGER1 IMXRT_XBAR1(XBAR_INPUT, 81) /* XBAR1_IN81 <- FLEXPWM1 PWM3_MUX_TRIGGER1 */ +#define IMXRT_XBAR1_IN_FLEXPWM2_PWM0_MUX_TRIGGER0 IMXRT_XBAR1(XBAR_INPUT, 82) /* XBAR1_IN82 <- FLEXPWM2 PWM0_MUX_TRIGGER0 */ +#define IMXRT_XBAR1_IN_FLEXPWM2_PWM1_MUX_TRIGGER0 IMXRT_XBAR1(XBAR_INPUT, 83) /* XBAR1_IN83 <- FLEXPWM2 PWM1_MUX_TRIGGER0 */ +#define IMXRT_XBAR1_IN_FLEXPWM2_PWM2_MUX_TRIGGER0 IMXRT_XBAR1(XBAR_INPUT, 84) /* XBAR1_IN84 <- FLEXPWM2 PWM2_MUX_TRIGGER0 */ +#define IMXRT_XBAR1_IN_FLEXPWM2_PWM3_MUX_TRIGGER0 IMXRT_XBAR1(XBAR_INPUT, 85) /* XBAR1_IN85 <- FLEXPWM2 PWM3_MUX_TRIGGER0 */ +#define IMXRT_XBAR1_IN_FLEXPWM3_PWM0_MUX_TRIGGER0 IMXRT_XBAR1(XBAR_INPUT, 86) /* XBAR1_IN86 <- FLEXPWM3 PWM0_MUX_TRIGGER0 */ +#define IMXRT_XBAR1_IN_FLEXPWM3_PWM1_MUX_TRIGGER0 IMXRT_XBAR1(XBAR_INPUT, 87) /* XBAR1_IN87 <- FLEXPWM3 PWM1_MUX_TRIGGER0 */ +#define IMXRT_XBAR1_IN_FLEXPWM3_PWM2_MUX_TRIGGER0 IMXRT_XBAR1(XBAR_INPUT, 88) /* XBAR1_IN88 <- FLEXPWM3 PWM2_MUX_TRIGGER0 */ +#define IMXRT_XBAR1_IN_FLEXPWM3_PWM3_MUX_TRIGGER0 IMXRT_XBAR1(XBAR_INPUT, 89) /* XBAR1_IN89 <- FLEXPWM3 PWM3_MUX_TRIGGER0 */ +#define IMXRT_XBAR1_IN_FLEXPWM4_PWM0_MUX_TRIGGER0 IMXRT_XBAR1(XBAR_INPUT, 90) /* XBAR1_IN90 <- FLEXPWM4 PWM0_MUX_TRIGGER0 */ +#define IMXRT_XBAR1_IN_FLEXPWM4_PWM1_MUX_TRIGGER0 IMXRT_XBAR1(XBAR_INPUT, 91) /* XBAR1_IN91 <- FLEXPWM4 PWM1_MUX_TRIGGER0 */ +#define IMXRT_XBAR1_IN_FLEXPWM4_PWM2_MUX_TRIGGER0 IMXRT_XBAR1(XBAR_INPUT, 92) /* XBAR1_IN92 <- FLEXPWM4 PWM2_MUX_TRIGGER0 */ +#define IMXRT_XBAR1_IN_FLEXPWM4_PWM3_MUX_TRIGGER0 IMXRT_XBAR1(XBAR_INPUT, 93) /* XBAR1_IN93 <- FLEXPWM4 PWM3_MUX_TRIGGER0 */ +#define IMXRT_XBAR1_IN_LPIT1_LPIT_TRIG_OUT0 IMXRT_XBAR1(XBAR_INPUT, 94) /* XBAR1_IN94 <- LPIT1 LPIT_TRIG_OUT0 */ +#define IMXRT_XBAR1_IN_LPIT1_LPIT_TRIG_OUT1 IMXRT_XBAR1(XBAR_INPUT, 95) /* XBAR1_IN95 <- LPIT1 LPIT_TRIG_OUT1 */ +#define IMXRT_XBAR1_IN_LPIT1_LPIT_TRIG_OUT2 IMXRT_XBAR1(XBAR_INPUT, 96) /* XBAR1_IN96 <- LPIT1 LPIT_TRIG_OUT2 */ +#define IMXRT_XBAR1_IN_LPIT1_LPIT_TRIG_OUT3 IMXRT_XBAR1(XBAR_INPUT, 97) /* XBAR1_IN97 <- LPIT1 LPIT_TRIG_OUT3 */ +#define IMXRT_XBAR1_IN_LPIT2_LPIT_TRIG_OUT0 IMXRT_XBAR1(XBAR_INPUT, 98) /* XBAR1_IN98 <- LPIT2 LPIT_TRIG_OUT0 */ +#define IMXRT_XBAR1_IN_LPIT2_LPIT_TRIG_OUT1 IMXRT_XBAR1(XBAR_INPUT, 99) /* XBAR1_IN99 <- LPIT2 LPIT_TRIG_OUT1 */ +#define IMXRT_XBAR1_IN_LPIT2_LPIT_TRIG_OUT2 IMXRT_XBAR1(XBAR_INPUT, 100) /* XBAR1_IN100 <- LPIT2 LPIT_TRIG_OUT2 */ +#define IMXRT_XBAR1_IN_LPIT2_LPIT_TRIG_OUT3 IMXRT_XBAR1(XBAR_INPUT, 101) /* XBAR1_IN101 <- LPIT2 LPIT_TRIG_OUT3 */ +#define IMXRT_XBAR1_IN_LPIT3_LPIT_TRIG_OUT0 IMXRT_XBAR1(XBAR_INPUT, 102) /* XBAR1_IN102 <- LPIT3 LPIT_TRIG_OUT0 */ +#define IMXRT_XBAR1_IN_LPIT3_LPIT_TRIG_OUT1 IMXRT_XBAR1(XBAR_INPUT, 103) /* XBAR1_IN103 <- LPIT3 LPIT_TRIG_OUT1 */ +#define IMXRT_XBAR1_IN_LPIT3_LPIT_TRIG_OUT2 IMXRT_XBAR1(XBAR_INPUT, 104) /* XBAR1_IN104 <- LPIT3 LPIT_TRIG_OUT2 */ +#define IMXRT_XBAR1_IN_LPIT3_LPIT_TRIG_OUT3 IMXRT_XBAR1(XBAR_INPUT, 105) /* XBAR1_IN105 <- LPIT3 LPIT_TRIG_OUT3 */ +#define IMXRT_XBAR1_IN_TRIGGER_SY_TRIGGER_SYNC_OUT0_NC IMXRT_XBAR1(XBAR_INPUT, 106) /* XBAR1_IN106 <- TRIGGER_SY TRIGGER_SYNC_OUT0 - NC */ +#define IMXRT_XBAR1_IN_TRIGGER_SY_TRIGGER_SYNC_OUT1_NC IMXRT_XBAR1(XBAR_INPUT, 107) /* XBAR1_IN107 <- TRIGGER_SY TRIGGER_SYNC_OUT1 - NC */ +#define IMXRT_XBAR1_IN_TRIGGER_SY_TRIGGER_SYNC_OUT2_NC IMXRT_XBAR1(XBAR_INPUT, 108) /* XBAR1_IN108 <- TRIGGER_SY TRIGGER_SYNC_OUT2 - NC */ +#define IMXRT_XBAR1_IN_TRIGGER_SY_TRIGGER_SYNC_OUT3_NC IMXRT_XBAR1(XBAR_INPUT, 109) /* XBAR1_IN109 <- TRIGGER_SY TRIGGER_SYNC_OUT3 - NC */ +#define IMXRT_XBAR1_IN_EDMA4_DMA_TRIGGER_OUT0 IMXRT_XBAR1(XBAR_INPUT, 110) /* XBAR1_IN110 <- eDMA4 DMA_TRIGGER_OUT0 */ +#define IMXRT_XBAR1_IN_EDMA4_DMA_TRIGGER_OUT1 IMXRT_XBAR1(XBAR_INPUT, 111) /* XBAR1_IN111 <- eDMA4 DMA_TRIGGER_OUT1 */ +#define IMXRT_XBAR1_IN_EDMA4_DMA_TRIGGER_OUT2 IMXRT_XBAR1(XBAR_INPUT, 112) /* XBAR1_IN112 <- eDMA4 DMA_TRIGGER_OUT2 */ +#define IMXRT_XBAR1_IN_EDMA4_DMA_TRIGGER_OUT3 IMXRT_XBAR1(XBAR_INPUT, 113) /* XBAR1_IN113 <- eDMA4 DMA_TRIGGER_OUT3 */ +#define IMXRT_XBAR1_IN_EDMA4_DMA_TRIGGER_OUT4 IMXRT_XBAR1(XBAR_INPUT, 114) /* XBAR1_IN114 <- eDMA4 DMA_TRIGGER_OUT4 */ +#define IMXRT_XBAR1_IN_EDMA4_DMA_TRIGGER_OUT5 IMXRT_XBAR1(XBAR_INPUT, 115) /* XBAR1_IN115 <- eDMA4 DMA_TRIGGER_OUT5 */ +#define IMXRT_XBAR1_IN_EDMA4_DMA_TRIGGER_OUT6 IMXRT_XBAR1(XBAR_INPUT, 116) /* XBAR1_IN116 <- eDMA4 DMA_TRIGGER_OUT6 */ +#define IMXRT_XBAR1_IN_EDMA4_DMA_TRIGGER_OUT7 IMXRT_XBAR1(XBAR_INPUT, 117) /* XBAR1_IN117 <- eDMA4 DMA_TRIGGER_OUT7 */ +#define IMXRT_XBAR1_IN_EDMA3_DMA_TRIGGER_OUT0 IMXRT_XBAR1(XBAR_INPUT, 118) /* XBAR1_IN118 <- eDMA3 DMA_TRIGGER_OUT0 */ +#define IMXRT_XBAR1_IN_EDMA3_DMA_TRIGGER_OUT1 IMXRT_XBAR1(XBAR_INPUT, 119) /* XBAR1_IN119 <- eDMA3 DMA_TRIGGER_OUT1 */ +#define IMXRT_XBAR1_IN_EDMA3_DMA_TRIGGER_OUT2 IMXRT_XBAR1(XBAR_INPUT, 120) /* XBAR1_IN120 <- eDMA3 DMA_TRIGGER_OUT2 */ +#define IMXRT_XBAR1_IN_EDMA3_DMA_TRIGGER_OUT3 IMXRT_XBAR1(XBAR_INPUT, 121) /* XBAR1_IN121 <- eDMA3 DMA_TRIGGER_OUT3 */ +#define IMXRT_XBAR1_IN_EDMA3_DMA_TRIGGER_OUT4 IMXRT_XBAR1(XBAR_INPUT, 122) /* XBAR1_IN122 <- eDMA3 DMA_TRIGGER_OUT4 */ +#define IMXRT_XBAR1_IN_EDMA3_DMA_TRIGGER_OUT5 IMXRT_XBAR1(XBAR_INPUT, 123) /* XBAR1_IN123 <- eDMA3 DMA_TRIGGER_OUT5 */ +#define IMXRT_XBAR1_IN_EDMA3_DMA_TRIGGER_OUT6 IMXRT_XBAR1(XBAR_INPUT, 124) /* XBAR1_IN124 <- eDMA3 DMA_TRIGGER_OUT6 */ +#define IMXRT_XBAR1_IN_EDMA3_DMA_TRIGGER_OUT7 IMXRT_XBAR1(XBAR_INPUT, 125) /* XBAR1_IN125 <- eDMA3 DMA_TRIGGER_OUT7 */ +#define IMXRT_XBAR1_IN_ADC1_ADC_TCOMP_PULSE0 IMXRT_XBAR1(XBAR_INPUT, 126) /* XBAR1_IN126 <- ADC1 ADC_TCOMP_PULSE0 */ +#define IMXRT_XBAR1_IN_ADC1_ADC_TCOMP_PULSE1 IMXRT_XBAR1(XBAR_INPUT, 127) /* XBAR1_IN127 <- ADC1 ADC_TCOMP_PULSE1 */ +#define IMXRT_XBAR1_IN_ADC1_ADC_TCOMP_PULSE2 IMXRT_XBAR1(XBAR_INPUT, 128) /* XBAR1_IN128 <- ADC1 ADC_TCOMP_PULSE2 */ +#define IMXRT_XBAR1_IN_ADC1_ADC_TCOMP_PULSE3 IMXRT_XBAR1(XBAR_INPUT, 129) /* XBAR1_IN129 <- ADC1 ADC_TCOMP_PULSE3 */ +#define IMXRT_XBAR1_IN_ADC1_ADC_TCOMP_PULSE4 IMXRT_XBAR1(XBAR_INPUT, 130) /* XBAR1_IN130 <- ADC1 ADC_TCOMP_PULSE4 */ +#define IMXRT_XBAR1_IN_ADC1_ADC_TCOMP_PULSE5 IMXRT_XBAR1(XBAR_INPUT, 131) /* XBAR1_IN131 <- ADC1 ADC_TCOMP_PULSE5 */ +#define IMXRT_XBAR1_IN_ADC1_ADC_TCOMP_PULSE6 IMXRT_XBAR1(XBAR_INPUT, 132) /* XBAR1_IN132 <- ADC1 ADC_TCOMP_PULSE6 */ +#define IMXRT_XBAR1_IN_ADC1_ADC_TCOMP_PULSE7 IMXRT_XBAR1(XBAR_INPUT, 133) /* XBAR1_IN133 <- ADC1 ADC_TCOMP_PULSE7 */ +#define IMXRT_XBAR1_IN_ADC2_ADC_TCOMP_PULSE0 IMXRT_XBAR1(XBAR_INPUT, 134) /* XBAR1_IN134 <- ADC2 ADC_TCOMP_PULSE0 */ +#define IMXRT_XBAR1_IN_ADC2_ADC_TCOMP_PULSE1 IMXRT_XBAR1(XBAR_INPUT, 135) /* XBAR1_IN135 <- ADC2 ADC_TCOMP_PULSE1 */ +#define IMXRT_XBAR1_IN_ADC2_ADC_TCOMP_PULSE2 IMXRT_XBAR1(XBAR_INPUT, 136) /* XBAR1_IN136 <- ADC2 ADC_TCOMP_PULSE2 */ +#define IMXRT_XBAR1_IN_ADC2_ADC_TCOMP_PULSE3 IMXRT_XBAR1(XBAR_INPUT, 137) /* XBAR1_IN137 <- ADC2 ADC_TCOMP_PULSE3 */ +#define IMXRT_XBAR1_IN_ADC2_ADC_TCOMP_PULSE4 IMXRT_XBAR1(XBAR_INPUT, 138) /* XBAR1_IN138 <- ADC2 ADC_TCOMP_PULSE4 */ +#define IMXRT_XBAR1_IN_ADC2_ADC_TCOMP_PULSE5 IMXRT_XBAR1(XBAR_INPUT, 139) /* XBAR1_IN139 <- ADC2 ADC_TCOMP_PULSE5 */ +#define IMXRT_XBAR1_IN_ADC2_ADC_TCOMP_PULSE6 IMXRT_XBAR1(XBAR_INPUT, 140) /* XBAR1_IN140 <- ADC2 ADC_TCOMP_PULSE6 */ +#define IMXRT_XBAR1_IN_ADC2_ADC_TCOMP_PULSE7 IMXRT_XBAR1(XBAR_INPUT, 141) /* XBAR1_IN141 <- ADC2 ADC_TCOMP_PULSE7 */ +#define IMXRT_XBAR1_IN_TPM1_TPM_CH_TRIGGER0 IMXRT_XBAR1(XBAR_INPUT, 142) /* XBAR1_IN142 <- TPM1 TPM_CH_TRIGGER0 */ +#define IMXRT_XBAR1_IN_TPM1_TPM_CH_TRIGGER1 IMXRT_XBAR1(XBAR_INPUT, 143) /* XBAR1_IN143 <- TPM1 TPM_CH_TRIGGER1 */ +#define IMXRT_XBAR1_IN_TPM1_TPM_CH_TRIGGER2 IMXRT_XBAR1(XBAR_INPUT, 144) /* XBAR1_IN144 <- TPM1 TPM_CH_TRIGGER2 */ +#define IMXRT_XBAR1_IN_TPM1_TPM_CH_TRIGGER3 IMXRT_XBAR1(XBAR_INPUT, 145) /* XBAR1_IN145 <- TPM1 TPM_CH_TRIGGER3 */ +#define IMXRT_XBAR1_IN_TPM1_TPM_TRIGGER IMXRT_XBAR1(XBAR_INPUT, 146) /* XBAR1_IN146 <- TPM1 TPM_TRIGGER */ +#define IMXRT_XBAR1_IN_TPM2_TPM_CH_TRIGGER0 IMXRT_XBAR1(XBAR_INPUT, 147) /* XBAR1_IN147 <- TPM2 TPM_CH_TRIGGER0 */ +#define IMXRT_XBAR1_IN_TPM2_TPM_CH_TRIGGER1 IMXRT_XBAR1(XBAR_INPUT, 148) /* XBAR1_IN148 <- TPM2 TPM_CH_TRIGGER1 */ +#define IMXRT_XBAR1_IN_TPM2_TPM_CH_TRIGGER2 IMXRT_XBAR1(XBAR_INPUT, 149) /* XBAR1_IN149 <- TPM2 TPM_CH_TRIGGER2 */ +#define IMXRT_XBAR1_IN_TPM2_TPM_CH_TRIGGER3 IMXRT_XBAR1(XBAR_INPUT, 150) /* XBAR1_IN150 <- TPM2 TPM_CH_TRIGGER3 */ +#define IMXRT_XBAR1_IN_TPM2_TPM_TRIGGER IMXRT_XBAR1(XBAR_INPUT, 151) /* XBAR1_IN151 <- TPM2 TPM_TRIGGER */ +#define IMXRT_XBAR1_IN_TPM3_TPM_CH_TRIGGER0 IMXRT_XBAR1(XBAR_INPUT, 152) /* XBAR1_IN152 <- TPM3 TPM_CH_TRIGGER0 */ +#define IMXRT_XBAR1_IN_TPM3_TPM_CH_TRIGGER1 IMXRT_XBAR1(XBAR_INPUT, 153) /* XBAR1_IN153 <- TPM3 TPM_CH_TRIGGER1 */ +#define IMXRT_XBAR1_IN_TPM3_TPM_CH_TRIGGER2 IMXRT_XBAR1(XBAR_INPUT, 154) /* XBAR1_IN154 <- TPM3 TPM_CH_TRIGGER2 */ +#define IMXRT_XBAR1_IN_TPM3_TPM_CH_TRIGGER3 IMXRT_XBAR1(XBAR_INPUT, 155) /* XBAR1_IN155 <- TPM3 TPM_CH_TRIGGER3 */ +#define IMXRT_XBAR1_IN_TPM3_TPM_TRIGGER IMXRT_XBAR1(XBAR_INPUT, 156) /* XBAR1_IN156 <- TPM3 TPM_TRIGGER */ +#define IMXRT_XBAR1_IN_TPM4_TPM_CH_TRIGGER0 IMXRT_XBAR1(XBAR_INPUT, 157) /* XBAR1_IN157 <- TPM4 TPM_CH_TRIGGER0 */ +#define IMXRT_XBAR1_IN_TPM4_TPM_CH_TRIGGER1 IMXRT_XBAR1(XBAR_INPUT, 158) /* XBAR1_IN158 <- TPM4 TPM_CH_TRIGGER1 */ +#define IMXRT_XBAR1_IN_TPM4_TPM_CH_TRIGGER2 IMXRT_XBAR1(XBAR_INPUT, 159) /* XBAR1_IN159 <- TPM4 TPM_CH_TRIGGER2 */ +#define IMXRT_XBAR1_IN_TPM4_TPM_CH_TRIGGER3 IMXRT_XBAR1(XBAR_INPUT, 160) /* XBAR1_IN160 <- TPM4 TPM_CH_TRIGGER3 */ +#define IMXRT_XBAR1_IN_TPM4_TPM_TRIGGER IMXRT_XBAR1(XBAR_INPUT, 161) /* XBAR1_IN161 <- TPM4 TPM_TRIGGER */ +#define IMXRT_XBAR1_IN_TPM5_TPM_CH_TRIGGER0 IMXRT_XBAR1(XBAR_INPUT, 162) /* XBAR1_IN162 <- TPM5 TPM_CH_TRIGGER0 */ +#define IMXRT_XBAR1_IN_TPM5_TPM_CH_TRIGGER1 IMXRT_XBAR1(XBAR_INPUT, 163) /* XBAR1_IN163 <- TPM5 TPM_CH_TRIGGER1 */ +#define IMXRT_XBAR1_IN_TPM5_TPM_CH_TRIGGER2 IMXRT_XBAR1(XBAR_INPUT, 164) /* XBAR1_IN164 <- TPM5 TPM_CH_TRIGGER2 */ +#define IMXRT_XBAR1_IN_TPM5_TPM_CH_TRIGGER3 IMXRT_XBAR1(XBAR_INPUT, 165) /* XBAR1_IN165 <- TPM5 TPM_CH_TRIGGER3 */ +#define IMXRT_XBAR1_IN_TPM5_TPM_TRIGGER IMXRT_XBAR1(XBAR_INPUT, 166) /* XBAR1_IN166 <- TPM5 TPM_TRIGGER */ +#define IMXRT_XBAR1_IN_TPM6_TPM_CH_TRIGGER0 IMXRT_XBAR1(XBAR_INPUT, 167) /* XBAR1_IN167 <- TPM6 TPM_CH_TRIGGER0 */ +#define IMXRT_XBAR1_IN_TPM6_TPM_CH_TRIGGER1 IMXRT_XBAR1(XBAR_INPUT, 168) /* XBAR1_IN168 <- TPM6 TPM_CH_TRIGGER1 */ +#define IMXRT_XBAR1_IN_TPM6_TPM_CH_TRIGGER2 IMXRT_XBAR1(XBAR_INPUT, 169) /* XBAR1_IN169 <- TPM6 TPM_CH_TRIGGER2 */ +#define IMXRT_XBAR1_IN_TPM6_TPM_CH_TRIGGER3 IMXRT_XBAR1(XBAR_INPUT, 170) /* XBAR1_IN170 <- TPM6 TPM_CH_TRIGGER3 */ +#define IMXRT_XBAR1_IN_TPM6_TPM_TRIGGER IMXRT_XBAR1(XBAR_INPUT, 171) /* XBAR1_IN171 <- TPM6 TPM_TRIGGER */ +#define IMXRT_XBAR1_IN_LPTMR1_LPTIMER_TRIGGER_DELAY IMXRT_XBAR1(XBAR_INPUT, 172) /* XBAR1_IN172 <- LPTMR1 LPTIMER_TRIGGER_DELAY */ +#define IMXRT_XBAR1_IN_LPTMR2_LPTIMER_TRIGGER_DELAY IMXRT_XBAR1(XBAR_INPUT, 173) /* XBAR1_IN173 <- LPTMR2 LPTIMER_TRIGGER_DELAY */ +#define IMXRT_XBAR1_IN_LPTMR3_LPTIMER_TRIGGER_DELAY IMXRT_XBAR1(XBAR_INPUT, 174) /* XBAR1_IN174 <- LPTMR3 LPTIMER_TRIGGER_DELAY */ +#define IMXRT_XBAR1_IN_NETC_TMR_1588_PP1 IMXRT_XBAR1(XBAR_INPUT, 175) /* XBAR1_IN175 <- NETC TMR_1588_PP1 */ +#define IMXRT_XBAR1_IN_NETC_TMR_1588_PP2 IMXRT_XBAR1(XBAR_INPUT, 176) /* XBAR1_IN176 <- NETC TMR_1588_PP2 */ +#define IMXRT_XBAR1_IN_NETC_TMR_1588_PP3 IMXRT_XBAR1(XBAR_INPUT, 177) /* XBAR1_IN177 <- NETC TMR_1588_PP3 */ +#define IMXRT_XBAR1_IN_SINC1_CHANNEL_0_BREAK_DUE_TO_CLOCK_ABSENCE_DETECTED IMXRT_XBAR1(XBAR_INPUT, 178) /* XBAR1_IN178 <- SINC1 Channel 0 break due to clock absence detected */ +#define IMXRT_XBAR1_IN_SINC1_CHANNEL_1_BREAK_DUE_TO_CLOCK_ABSENCE_DETECTED IMXRT_XBAR1(XBAR_INPUT, 179) /* XBAR1_IN179 <- SINC1 Channel 1 break due to clock absence detected */ +#define IMXRT_XBAR1_IN_SINC1_CHANNEL_2_BREAK_DUE_TO_CLOCK_ABSENCE_DETECTED IMXRT_XBAR1(XBAR_INPUT, 180) /* XBAR1_IN180 <- SINC1 Channel 2 break due to clock absence detected */ +#define IMXRT_XBAR1_IN_SINC1_CHANNEL_3_BREAK_DUE_TO_CLOCK_ABSENCE_DETECTED IMXRT_XBAR1(XBAR_INPUT, 181) /* XBAR1_IN181 <- SINC1 Channel 3 break due to clock absence detected */ +#define IMXRT_XBAR1_IN_SINC2_CHANNEL_0_BREAK_DUE_TO_CLOCK_ABSENCE_DETECTED IMXRT_XBAR1(XBAR_INPUT, 182) /* XBAR1_IN182 <- SINC2 Channel 0 break due to clock absence detected */ +#define IMXRT_XBAR1_IN_SINC2_CHANNEL_1_BREAK_DUE_TO_CLOCK_ABSENCE_DETECTED IMXRT_XBAR1(XBAR_INPUT, 183) /* XBAR1_IN183 <- SINC2 Channel 1 break due to clock absence detected */ +#define IMXRT_XBAR1_IN_SINC2_CHANNEL_2_BREAK_DUE_TO_CLOCK_ABSENCE_DETECTED IMXRT_XBAR1(XBAR_INPUT, 184) /* XBAR1_IN184 <- SINC2 Channel 2 break due to clock absence detected */ +#define IMXRT_XBAR1_IN_SINC2_CHANNEL_3_BREAK_DUE_TO_CLOCK_ABSENCE_DETECTED IMXRT_XBAR1(XBAR_INPUT, 185) /* XBAR1_IN185 <- SINC2 Channel 3 break due to clock absence detected */ +#define IMXRT_XBAR1_IN_SINC3_CHANNEL_0_BREAK_DUE_TO_CLOCK_ABSENCE_DETECTED IMXRT_XBAR1(XBAR_INPUT, 186) /* XBAR1_IN186 <- SINC3 Channel 0 break due to clock absence detected */ +#define IMXRT_XBAR1_IN_SINC3_CHANNEL_1_BREAK_DUE_TO_CLOCK_ABSENCE_DETECTED IMXRT_XBAR1(XBAR_INPUT, 187) /* XBAR1_IN187 <- SINC3 Channel 1 break due to clock absence detected */ +#define IMXRT_XBAR1_IN_SINC3_CHANNEL_2_BREAK_DUE_TO_CLOCK_ABSENCE_DETECTED IMXRT_XBAR1(XBAR_INPUT, 188) /* XBAR1_IN188 <- SINC3 Channel 2 break due to clock absence detected */ +#define IMXRT_XBAR1_IN_SINC3_CHANNEL_3_BREAK_DUE_TO_CLOCK_ABSENCE_DETECTED IMXRT_XBAR1(XBAR_INPUT, 189) /* XBAR1_IN189 <- SINC3 Channel 3 break due to clock absence detected */ +#define IMXRT_XBAR1_IN_AOI1_AOI_OUT0 IMXRT_XBAR1(XBAR_INPUT, 190) /* XBAR1_IN190 <- AOI1 AOI_OUT0 */ +#define IMXRT_XBAR1_IN_AOI1_AOI_OUT1 IMXRT_XBAR1(XBAR_INPUT, 191) /* XBAR1_IN191 <- AOI1 AOI_OUT1 */ +#define IMXRT_XBAR1_IN_AOI1_AOI_OUT2 IMXRT_XBAR1(XBAR_INPUT, 192) /* XBAR1_IN192 <- AOI1 AOI_OUT2 */ +#define IMXRT_XBAR1_IN_AOI1_AOI_OUT3 IMXRT_XBAR1(XBAR_INPUT, 193) /* XBAR1_IN193 <- AOI1 AOI_OUT3 */ +#define IMXRT_XBAR1_IN_AOI2_AOI_OUT0 IMXRT_XBAR1(XBAR_INPUT, 194) /* XBAR1_IN194 <- AOI2 AOI_OUT0 */ +#define IMXRT_XBAR1_IN_AOI2_AOI_OUT1 IMXRT_XBAR1(XBAR_INPUT, 195) /* XBAR1_IN195 <- AOI2 AOI_OUT1 */ +#define IMXRT_XBAR1_IN_AOI2_AOI_OUT2 IMXRT_XBAR1(XBAR_INPUT, 196) /* XBAR1_IN196 <- AOI2 AOI_OUT2 */ +#define IMXRT_XBAR1_IN_AOI2_AOI_OUT3 IMXRT_XBAR1(XBAR_INPUT, 197) /* XBAR1_IN197 <- AOI2 AOI_OUT3 */ +#define IMXRT_XBAR1_IN_TRIGGER_SY_TRIGGER_SYNC_OUT4_NC IMXRT_XBAR1(XBAR_INPUT, 198) /* XBAR1_IN198 <- TRIGGER_SY TRIGGER_SYNC_OUT4 - NC */ +#define IMXRT_XBAR1_IN_TRIGGER_SY_TRIGGER_SYNC_OUT5_NC IMXRT_XBAR1(XBAR_INPUT, 199) /* XBAR1_IN199 <- TRIGGER_SY TRIGGER_SYNC_OUT5 - NC */ +#define IMXRT_XBAR1_IN_TRIGGER_SY_TRIGGER_SYNC_OUT6_NC IMXRT_XBAR1(XBAR_INPUT, 200) /* XBAR1_IN200 <- TRIGGER_SY TRIGGER_SYNC_OUT6 - NC */ +#define IMXRT_XBAR1_IN_TRIGGER_SY_TRIGGER_SYNC_OUT7_NC IMXRT_XBAR1(XBAR_INPUT, 201) /* XBAR1_IN201 <- TRIGGER_SY TRIGGER_SYNC_OUT7 - NC */ +#define IMXRT_XBAR1_IN_RESERVED IMXRT_XBAR1(XBAR_INPUT, 202) /* XBAR1_IN202 <- - Reserved */ +#define IMXRT_XBAR1_IN_RESERVED_2 IMXRT_XBAR1(XBAR_INPUT, 203) /* XBAR1_IN203 <- - Reserved */ +#define IMXRT_XBAR1_IN_RESERVED_3 IMXRT_XBAR1(XBAR_INPUT, 204) /* XBAR1_IN204 <- - Reserved */ +#define IMXRT_XBAR1_IN_RESERVED_4 IMXRT_XBAR1(XBAR_INPUT, 205) /* XBAR1_IN205 <- - Reserved */ +#define IMXRT_XBAR1_IN_AOI3_AOI_OUT0 IMXRT_XBAR1(XBAR_INPUT, 206) /* XBAR1_IN206 <- AOI3 AOI_OUT0 */ +#define IMXRT_XBAR1_IN_AOI3_AOI_OUT1 IMXRT_XBAR1(XBAR_INPUT, 207) /* XBAR1_IN207 <- AOI3 AOI_OUT1 */ +#define IMXRT_XBAR1_IN_AOI3_AOI_OUT2 IMXRT_XBAR1(XBAR_INPUT, 208) /* XBAR1_IN208 <- AOI3 AOI_OUT2 */ +#define IMXRT_XBAR1_IN_AOI3_AOI_OUT3 IMXRT_XBAR1(XBAR_INPUT, 209) /* XBAR1_IN209 <- AOI3 AOI_OUT3 */ +#define IMXRT_XBAR1_IN_AOI4_AOI_OUT0 IMXRT_XBAR1(XBAR_INPUT, 210) /* XBAR1_IN210 <- AOI4 AOI_OUT0 */ +#define IMXRT_XBAR1_IN_AOI4_AOI_OUT1 IMXRT_XBAR1(XBAR_INPUT, 211) /* XBAR1_IN211 <- AOI4 AOI_OUT1 */ +#define IMXRT_XBAR1_IN_AOI4_AOI_OUT2 IMXRT_XBAR1(XBAR_INPUT, 212) /* XBAR1_IN212 <- AOI4 AOI_OUT2 */ +#define IMXRT_XBAR1_IN_AOI4_AOI_OUT3 IMXRT_XBAR1(XBAR_INPUT, 213) /* XBAR1_IN213 <- AOI4 AOI_OUT3 */ +#define IMXRT_XBAR1_IN_ECAT_SYNC_OUT0 IMXRT_XBAR1(XBAR_INPUT, 214) /* XBAR1_IN214 <- ECAT SYNC_OUT0 */ +#define IMXRT_XBAR1_IN_ECAT_SYNC_OUT1 IMXRT_XBAR1(XBAR_INPUT, 215) /* XBAR1_IN215 <- ECAT SYNC_OUT1 */ + +#define IMXRT_XBAR2_IN_GND IMXRT_XBAR2(XBAR_INPUT, 0) /* XBAR2_IN0 <- - GND */ +#define IMXRT_XBAR2_IN_1B1 IMXRT_XBAR2(XBAR_INPUT, 1) /* XBAR2_IN1 <- - 1'B1 */ +#define IMXRT_XBAR2_IN_GND_2 IMXRT_XBAR2(XBAR_INPUT, 2) /* XBAR2_IN2 <- - GND */ +#define IMXRT_XBAR2_IN_1B1_2 IMXRT_XBAR2(XBAR_INPUT, 3) /* XBAR2_IN3 <- - 1'B1 */ +#define IMXRT_XBAR2_IN_CMP1_COUT IMXRT_XBAR2(XBAR_INPUT, 4) /* XBAR2_IN4 <- CMP1 COUT */ +#define IMXRT_XBAR2_IN_CMP2_COUT IMXRT_XBAR2(XBAR_INPUT, 5) /* XBAR2_IN5 <- CMP2 COUT */ +#define IMXRT_XBAR2_IN_CMP3_COUT IMXRT_XBAR2(XBAR_INPUT, 6) /* XBAR2_IN6 <- CMP3 COUT */ +#define IMXRT_XBAR2_IN_CMP4_COUT IMXRT_XBAR2(XBAR_INPUT, 7) /* XBAR2_IN7 <- CMP4 COUT */ +#define IMXRT_XBAR2_IN_TMR1_TMR0_OUTPUT IMXRT_XBAR2(XBAR_INPUT, 8) /* XBAR2_IN8 <- TMR1 TMR0_OUTPUT */ +#define IMXRT_XBAR2_IN_TMR1_TMR1_OUTPUT IMXRT_XBAR2(XBAR_INPUT, 9) /* XBAR2_IN9 <- TMR1 TMR1_OUTPUT */ +#define IMXRT_XBAR2_IN_TMR1_TMR2_OUTPUT IMXRT_XBAR2(XBAR_INPUT, 10) /* XBAR2_IN10 <- TMR1 TMR2_OUTPUT */ +#define IMXRT_XBAR2_IN_TMR1_TMR3_OUTPUT IMXRT_XBAR2(XBAR_INPUT, 11) /* XBAR2_IN11 <- TMR1 TMR3_OUTPUT */ +#define IMXRT_XBAR2_IN_TMR2_TMR0_OUTPUT IMXRT_XBAR2(XBAR_INPUT, 12) /* XBAR2_IN12 <- TMR2 TMR0_OUTPUT */ +#define IMXRT_XBAR2_IN_TMR2_TMR1_OUTPUT IMXRT_XBAR2(XBAR_INPUT, 13) /* XBAR2_IN13 <- TMR2 TMR1_OUTPUT */ +#define IMXRT_XBAR2_IN_TMR2_TMR2_OUTPUT IMXRT_XBAR2(XBAR_INPUT, 14) /* XBAR2_IN14 <- TMR2 TMR2_OUTPUT */ +#define IMXRT_XBAR2_IN_TMR2_TMR3_OUTPUT IMXRT_XBAR2(XBAR_INPUT, 15) /* XBAR2_IN15 <- TMR2 TMR3_OUTPUT */ +#define IMXRT_XBAR2_IN_TMR3_TMR0_OUTPUT IMXRT_XBAR2(XBAR_INPUT, 16) /* XBAR2_IN16 <- TMR3 TMR0_OUTPUT */ +#define IMXRT_XBAR2_IN_TMR3_TMR1_OUTPUT IMXRT_XBAR2(XBAR_INPUT, 17) /* XBAR2_IN17 <- TMR3 TMR1_OUTPUT */ +#define IMXRT_XBAR2_IN_TMR3_TMR2_OUTPUT IMXRT_XBAR2(XBAR_INPUT, 18) /* XBAR2_IN18 <- TMR3 TMR2_OUTPUT */ +#define IMXRT_XBAR2_IN_TMR3_TMR3_OUTPUT IMXRT_XBAR2(XBAR_INPUT, 19) /* XBAR2_IN19 <- TMR3 TMR3_OUTPUT */ +#define IMXRT_XBAR2_IN_TMR4_TMR0_OUTPUT IMXRT_XBAR2(XBAR_INPUT, 20) /* XBAR2_IN20 <- TMR4 TMR0_OUTPUT */ +#define IMXRT_XBAR2_IN_TMR4_TMR1_OUTPUT IMXRT_XBAR2(XBAR_INPUT, 21) /* XBAR2_IN21 <- TMR4 TMR1_OUTPUT */ +#define IMXRT_XBAR2_IN_TMR4_TMR2_OUTPUT IMXRT_XBAR2(XBAR_INPUT, 22) /* XBAR2_IN22 <- TMR4 TMR2_OUTPUT */ +#define IMXRT_XBAR2_IN_TMR4_TMR3_OUTPUT IMXRT_XBAR2(XBAR_INPUT, 23) /* XBAR2_IN23 <- TMR4 TMR3_OUTPUT */ +#define IMXRT_XBAR2_IN_TMR5_TMR0_OUTPUT IMXRT_XBAR2(XBAR_INPUT, 24) /* XBAR2_IN24 <- TMR5 TMR0_OUTPUT */ +#define IMXRT_XBAR2_IN_TMR5_TMR1_OUTPUT IMXRT_XBAR2(XBAR_INPUT, 25) /* XBAR2_IN25 <- TMR5 TMR1_OUTPUT */ +#define IMXRT_XBAR2_IN_TMR5_TMR2_OUTPUT IMXRT_XBAR2(XBAR_INPUT, 26) /* XBAR2_IN26 <- TMR5 TMR2_OUTPUT */ +#define IMXRT_XBAR2_IN_TMR5_TMR3_OUTPUT IMXRT_XBAR2(XBAR_INPUT, 27) /* XBAR2_IN27 <- TMR5 TMR3_OUTPUT */ +#define IMXRT_XBAR2_IN_TMR6_TMR0_OUTPUT IMXRT_XBAR2(XBAR_INPUT, 28) /* XBAR2_IN28 <- TMR6 TMR0_OUTPUT */ +#define IMXRT_XBAR2_IN_TMR6_TMR1_OUTPUT IMXRT_XBAR2(XBAR_INPUT, 29) /* XBAR2_IN29 <- TMR6 TMR1_OUTPUT */ +#define IMXRT_XBAR2_IN_TMR6_TMR2_OUTPUT IMXRT_XBAR2(XBAR_INPUT, 30) /* XBAR2_IN30 <- TMR6 TMR2_OUTPUT */ +#define IMXRT_XBAR2_IN_TMR6_TMR3_OUTPUT IMXRT_XBAR2(XBAR_INPUT, 31) /* XBAR2_IN31 <- TMR6 TMR3_OUTPUT */ +#define IMXRT_XBAR2_IN_TMR7_TMR0_OUTPUT IMXRT_XBAR2(XBAR_INPUT, 32) /* XBAR2_IN32 <- TMR7 TMR0_OUTPUT */ +#define IMXRT_XBAR2_IN_TMR7_TMR1_OUTPUT IMXRT_XBAR2(XBAR_INPUT, 33) /* XBAR2_IN33 <- TMR7 TMR1_OUTPUT */ +#define IMXRT_XBAR2_IN_TMR7_TMR2_OUTPUT IMXRT_XBAR2(XBAR_INPUT, 34) /* XBAR2_IN34 <- TMR7 TMR2_OUTPUT */ +#define IMXRT_XBAR2_IN_TMR7_TMR3_OUTPUT IMXRT_XBAR2(XBAR_INPUT, 35) /* XBAR2_IN35 <- TMR7 TMR3_OUTPUT */ +#define IMXRT_XBAR2_IN_TMR8_TMR0_OUTPUT IMXRT_XBAR2(XBAR_INPUT, 36) /* XBAR2_IN36 <- TMR8 TMR0_OUTPUT */ +#define IMXRT_XBAR2_IN_TMR8_TMR1_OUTPUT IMXRT_XBAR2(XBAR_INPUT, 37) /* XBAR2_IN37 <- TMR8 TMR1_OUTPUT */ +#define IMXRT_XBAR2_IN_TMR8_TMR2_OUTPUT IMXRT_XBAR2(XBAR_INPUT, 38) /* XBAR2_IN38 <- TMR8 TMR2_OUTPUT */ +#define IMXRT_XBAR2_IN_TMR8_TMR3_OUTPUT IMXRT_XBAR2(XBAR_INPUT, 39) /* XBAR2_IN39 <- TMR8 TMR3_OUTPUT */ +#define IMXRT_XBAR2_IN_FLEXPWM1_PWM0_MUX_TRIGGER0 IMXRT_XBAR2(XBAR_INPUT, 40) /* XBAR2_IN40 <- FLEXPWM1 PWM0_MUX_TRIGGER0 */ +#define IMXRT_XBAR2_IN_FLEXPWM1_PWM1_MUX_TRIGGER0 IMXRT_XBAR2(XBAR_INPUT, 41) /* XBAR2_IN41 <- FLEXPWM1 PWM1_MUX_TRIGGER0 */ +#define IMXRT_XBAR2_IN_FLEXPWM1_PWM2_MUX_TRIGGER0 IMXRT_XBAR2(XBAR_INPUT, 42) /* XBAR2_IN42 <- FLEXPWM1 PWM2_MUX_TRIGGER0 */ +#define IMXRT_XBAR2_IN_FLEXPWM1_PWM3_MUX_TRIGGER0 IMXRT_XBAR2(XBAR_INPUT, 43) /* XBAR2_IN43 <- FLEXPWM1 PWM3_MUX_TRIGGER0 */ +#define IMXRT_XBAR2_IN_FLEXPWM2_PWM0_MUX_TRIGGER0 IMXRT_XBAR2(XBAR_INPUT, 44) /* XBAR2_IN44 <- FLEXPWM2 PWM0_MUX_TRIGGER0 */ +#define IMXRT_XBAR2_IN_FLEXPWM2_PWM1_MUX_TRIGGER0 IMXRT_XBAR2(XBAR_INPUT, 45) /* XBAR2_IN45 <- FLEXPWM2 PWM1_MUX_TRIGGER0 */ +#define IMXRT_XBAR2_IN_FLEXPWM2_PWM2_MUX_TRIGGER0 IMXRT_XBAR2(XBAR_INPUT, 46) /* XBAR2_IN46 <- FLEXPWM2 PWM2_MUX_TRIGGER0 */ +#define IMXRT_XBAR2_IN_FLEXPWM2_PWM3_MUX_TRIGGER0 IMXRT_XBAR2(XBAR_INPUT, 47) /* XBAR2_IN47 <- FLEXPWM2 PWM3_MUX_TRIGGER0 */ +#define IMXRT_XBAR2_IN_FLEXPWM3_PWM0_MUX_TRIGGER0 IMXRT_XBAR2(XBAR_INPUT, 48) /* XBAR2_IN48 <- FLEXPWM3 PWM0_MUX_TRIGGER0 */ +#define IMXRT_XBAR2_IN_FLEXPWM3_PWM1_MUX_TRIGGER0 IMXRT_XBAR2(XBAR_INPUT, 49) /* XBAR2_IN49 <- FLEXPWM3 PWM1_MUX_TRIGGER0 */ +#define IMXRT_XBAR2_IN_FLEXPWM3_PWM2_MUX_TRIGGER0 IMXRT_XBAR2(XBAR_INPUT, 50) /* XBAR2_IN50 <- FLEXPWM3 PWM2_MUX_TRIGGER0 */ +#define IMXRT_XBAR2_IN_FLEXPWM3_PWM3_MUX_TRIGGER0 IMXRT_XBAR2(XBAR_INPUT, 51) /* XBAR2_IN51 <- FLEXPWM3 PWM3_MUX_TRIGGER0 */ +#define IMXRT_XBAR2_IN_FLEXPWM4_PWM0_MUX_TRIGGER0 IMXRT_XBAR2(XBAR_INPUT, 52) /* XBAR2_IN52 <- FLEXPWM4 PWM0_MUX_TRIGGER0 */ +#define IMXRT_XBAR2_IN_FLEXPWM4_PWM1_MUX_TRIGGER0 IMXRT_XBAR2(XBAR_INPUT, 53) /* XBAR2_IN53 <- FLEXPWM4 PWM1_MUX_TRIGGER0 */ +#define IMXRT_XBAR2_IN_FLEXPWM4_PWM2_MUX_TRIGGER0 IMXRT_XBAR2(XBAR_INPUT, 54) /* XBAR2_IN54 <- FLEXPWM4 PWM2_MUX_TRIGGER0 */ +#define IMXRT_XBAR2_IN_FLEXPWM4_PWM3_MUX_TRIGGER0 IMXRT_XBAR2(XBAR_INPUT, 55) /* XBAR2_IN55 <- FLEXPWM4 PWM3_MUX_TRIGGER0 */ +#define IMXRT_XBAR2_IN_LPIT1_LPIT_TRIG_OUT0 IMXRT_XBAR2(XBAR_INPUT, 56) /* XBAR2_IN56 <- LPIT1 LPIT_TRIG_OUT0 */ +#define IMXRT_XBAR2_IN_LPIT1_LPIT_TRIG_OUT1 IMXRT_XBAR2(XBAR_INPUT, 57) /* XBAR2_IN57 <- LPIT1 LPIT_TRIG_OUT1 */ +#define IMXRT_XBAR2_IN_LPIT1_LPIT_TRIG_OUT2 IMXRT_XBAR2(XBAR_INPUT, 58) /* XBAR2_IN58 <- LPIT1 LPIT_TRIG_OUT2 */ +#define IMXRT_XBAR2_IN_LPIT1_LPIT_TRIG_OUT3 IMXRT_XBAR2(XBAR_INPUT, 59) /* XBAR2_IN59 <- LPIT1 LPIT_TRIG_OUT3 */ +#define IMXRT_XBAR2_IN_LPIT2_LPIT_TRIG_OUT0 IMXRT_XBAR2(XBAR_INPUT, 60) /* XBAR2_IN60 <- LPIT2 LPIT_TRIG_OUT0 */ +#define IMXRT_XBAR2_IN_LPIT2_LPIT_TRIG_OUT1 IMXRT_XBAR2(XBAR_INPUT, 61) /* XBAR2_IN61 <- LPIT2 LPIT_TRIG_OUT1 */ +#define IMXRT_XBAR2_IN_LPIT2_LPIT_TRIG_OUT2 IMXRT_XBAR2(XBAR_INPUT, 62) /* XBAR2_IN62 <- LPIT2 LPIT_TRIG_OUT2 */ +#define IMXRT_XBAR2_IN_LPIT2_LPIT_TRIG_OUT3 IMXRT_XBAR2(XBAR_INPUT, 63) /* XBAR2_IN63 <- LPIT2 LPIT_TRIG_OUT3 */ +#define IMXRT_XBAR2_IN_LPIT3_LPIT_TRIG_OUT0 IMXRT_XBAR2(XBAR_INPUT, 64) /* XBAR2_IN64 <- LPIT3 LPIT_TRIG_OUT0 */ +#define IMXRT_XBAR2_IN_LPIT3_LPIT_TRIG_OUT1 IMXRT_XBAR2(XBAR_INPUT, 65) /* XBAR2_IN65 <- LPIT3 LPIT_TRIG_OUT1 */ +#define IMXRT_XBAR2_IN_LPIT3_LPIT_TRIG_OUT2 IMXRT_XBAR2(XBAR_INPUT, 66) /* XBAR2_IN66 <- LPIT3 LPIT_TRIG_OUT2 */ +#define IMXRT_XBAR2_IN_LPIT3_LPIT_TRIG_OUT3 IMXRT_XBAR2(XBAR_INPUT, 67) /* XBAR2_IN67 <- LPIT3 LPIT_TRIG_OUT3 */ +#define IMXRT_XBAR2_IN_SINC1_PULSE_TRG0 IMXRT_XBAR2(XBAR_INPUT, 68) /* XBAR2_IN68 <- SINC1 PULSE_TRG0 */ +#define IMXRT_XBAR2_IN_SINC1_PULSE_TRG1 IMXRT_XBAR2(XBAR_INPUT, 69) /* XBAR2_IN69 <- SINC1 PULSE_TRG1 */ +#define IMXRT_XBAR2_IN_SINC1_PULSE_TRG2 IMXRT_XBAR2(XBAR_INPUT, 70) /* XBAR2_IN70 <- SINC1 PULSE_TRG2 */ +#define IMXRT_XBAR2_IN_SINC1_PULSE_TRG3 IMXRT_XBAR2(XBAR_INPUT, 71) /* XBAR2_IN71 <- SINC1 PULSE_TRG3 */ +#define IMXRT_XBAR2_IN_EDMA4_DMA_TRIGGER_OUT0 IMXRT_XBAR2(XBAR_INPUT, 72) /* XBAR2_IN72 <- eDMA4 DMA_TRIGGER_OUT0 */ +#define IMXRT_XBAR2_IN_EDMA4_DMA_TRIGGER_OUT1 IMXRT_XBAR2(XBAR_INPUT, 73) /* XBAR2_IN73 <- eDMA4 DMA_TRIGGER_OUT1 */ +#define IMXRT_XBAR2_IN_EDMA4_DMA_TRIGGER_OUT2 IMXRT_XBAR2(XBAR_INPUT, 74) /* XBAR2_IN74 <- eDMA4 DMA_TRIGGER_OUT2 */ +#define IMXRT_XBAR2_IN_EDMA4_DMA_TRIGGER_OUT3 IMXRT_XBAR2(XBAR_INPUT, 75) /* XBAR2_IN75 <- eDMA4 DMA_TRIGGER_OUT3 */ +#define IMXRT_XBAR2_IN_EDMA4_DMA_TRIGGER_OUT4 IMXRT_XBAR2(XBAR_INPUT, 76) /* XBAR2_IN76 <- eDMA4 DMA_TRIGGER_OUT4 */ +#define IMXRT_XBAR2_IN_EDMA4_DMA_TRIGGER_OUT5 IMXRT_XBAR2(XBAR_INPUT, 77) /* XBAR2_IN77 <- eDMA4 DMA_TRIGGER_OUT5 */ +#define IMXRT_XBAR2_IN_EDMA4_DMA_TRIGGER_OUT6 IMXRT_XBAR2(XBAR_INPUT, 78) /* XBAR2_IN78 <- eDMA4 DMA_TRIGGER_OUT6 */ +#define IMXRT_XBAR2_IN_EDMA4_DMA_TRIGGER_OUT7 IMXRT_XBAR2(XBAR_INPUT, 79) /* XBAR2_IN79 <- eDMA4 DMA_TRIGGER_OUT7 */ +#define IMXRT_XBAR2_IN_EDMA3_DMA_TRIGGER_OUT0 IMXRT_XBAR2(XBAR_INPUT, 80) /* XBAR2_IN80 <- eDMA3 DMA_TRIGGER_OUT0 */ +#define IMXRT_XBAR2_IN_EDMA3_DMA_TRIGGER_OUT1 IMXRT_XBAR2(XBAR_INPUT, 81) /* XBAR2_IN81 <- eDMA3 DMA_TRIGGER_OUT1 */ +#define IMXRT_XBAR2_IN_EDMA3_DMA_TRIGGER_OUT2 IMXRT_XBAR2(XBAR_INPUT, 82) /* XBAR2_IN82 <- eDMA3 DMA_TRIGGER_OUT2 */ +#define IMXRT_XBAR2_IN_EDMA3_DMA_TRIGGER_OUT3 IMXRT_XBAR2(XBAR_INPUT, 83) /* XBAR2_IN83 <- eDMA3 DMA_TRIGGER_OUT3 */ +#define IMXRT_XBAR2_IN_EDMA3_DMA_TRIGGER_OUT4 IMXRT_XBAR2(XBAR_INPUT, 84) /* XBAR2_IN84 <- eDMA3 DMA_TRIGGER_OUT4 */ +#define IMXRT_XBAR2_IN_EDMA3_DMA_TRIGGER_OUT5 IMXRT_XBAR2(XBAR_INPUT, 85) /* XBAR2_IN85 <- eDMA3 DMA_TRIGGER_OUT5 */ +#define IMXRT_XBAR2_IN_EDMA3_DMA_TRIGGER_OUT6 IMXRT_XBAR2(XBAR_INPUT, 86) /* XBAR2_IN86 <- eDMA3 DMA_TRIGGER_OUT6 */ +#define IMXRT_XBAR2_IN_EDMA3_DMA_TRIGGER_OUT7 IMXRT_XBAR2(XBAR_INPUT, 87) /* XBAR2_IN87 <- eDMA3 DMA_TRIGGER_OUT7 */ +#define IMXRT_XBAR2_IN_ADC1_ADC_TCOMP_PULSE0 IMXRT_XBAR2(XBAR_INPUT, 88) /* XBAR2_IN88 <- ADC1 ADC_TCOMP_PULSE0 */ +#define IMXRT_XBAR2_IN_ADC1_ADC_TCOMP_PULSE1 IMXRT_XBAR2(XBAR_INPUT, 89) /* XBAR2_IN89 <- ADC1 ADC_TCOMP_PULSE1 */ +#define IMXRT_XBAR2_IN_ADC1_ADC_TCOMP_PULSE2 IMXRT_XBAR2(XBAR_INPUT, 90) /* XBAR2_IN90 <- ADC1 ADC_TCOMP_PULSE2 */ +#define IMXRT_XBAR2_IN_ADC1_ADC_TCOMP_PULSE3 IMXRT_XBAR2(XBAR_INPUT, 91) /* XBAR2_IN91 <- ADC1 ADC_TCOMP_PULSE3 */ +#define IMXRT_XBAR2_IN_ADC1_ADC_TCOMP_PULSE4 IMXRT_XBAR2(XBAR_INPUT, 92) /* XBAR2_IN92 <- ADC1 ADC_TCOMP_PULSE4 */ +#define IMXRT_XBAR2_IN_ADC1_ADC_TCOMP_PULSE5 IMXRT_XBAR2(XBAR_INPUT, 93) /* XBAR2_IN93 <- ADC1 ADC_TCOMP_PULSE5 */ +#define IMXRT_XBAR2_IN_ADC1_ADC_TCOMP_PULSE6 IMXRT_XBAR2(XBAR_INPUT, 94) /* XBAR2_IN94 <- ADC1 ADC_TCOMP_PULSE6 */ +#define IMXRT_XBAR2_IN_ADC1_ADC_TCOMP_PULSE7 IMXRT_XBAR2(XBAR_INPUT, 95) /* XBAR2_IN95 <- ADC1 ADC_TCOMP_PULSE7 */ +#define IMXRT_XBAR2_IN_ADC2_ADC_TCOMP_PULSE0 IMXRT_XBAR2(XBAR_INPUT, 96) /* XBAR2_IN96 <- ADC2 ADC_TCOMP_PULSE0 */ +#define IMXRT_XBAR2_IN_ADC2_ADC_TCOMP_PULSE1 IMXRT_XBAR2(XBAR_INPUT, 97) /* XBAR2_IN97 <- ADC2 ADC_TCOMP_PULSE1 */ +#define IMXRT_XBAR2_IN_ADC2_ADC_TCOMP_PULSE2 IMXRT_XBAR2(XBAR_INPUT, 98) /* XBAR2_IN98 <- ADC2 ADC_TCOMP_PULSE2 */ +#define IMXRT_XBAR2_IN_ADC2_ADC_TCOMP_PULSE3 IMXRT_XBAR2(XBAR_INPUT, 99) /* XBAR2_IN99 <- ADC2 ADC_TCOMP_PULSE3 */ +#define IMXRT_XBAR2_IN_ADC2_ADC_TCOMP_PULSE4 IMXRT_XBAR2(XBAR_INPUT, 100) /* XBAR2_IN100 <- ADC2 ADC_TCOMP_PULSE4 */ +#define IMXRT_XBAR2_IN_ADC2_ADC_TCOMP_PULSE5 IMXRT_XBAR2(XBAR_INPUT, 101) /* XBAR2_IN101 <- ADC2 ADC_TCOMP_PULSE5 */ +#define IMXRT_XBAR2_IN_ADC2_ADC_TCOMP_PULSE6 IMXRT_XBAR2(XBAR_INPUT, 102) /* XBAR2_IN102 <- ADC2 ADC_TCOMP_PULSE6 */ +#define IMXRT_XBAR2_IN_ADC2_ADC_TCOMP_PULSE7 IMXRT_XBAR2(XBAR_INPUT, 103) /* XBAR2_IN103 <- ADC2 ADC_TCOMP_PULSE7 */ +#define IMXRT_XBAR2_IN_TPM1_TPM_CH_TRIGGER0 IMXRT_XBAR2(XBAR_INPUT, 104) /* XBAR2_IN104 <- TPM1 TPM_CH_TRIGGER0 */ +#define IMXRT_XBAR2_IN_TPM1_TPM_CH_TRIGGER1 IMXRT_XBAR2(XBAR_INPUT, 105) /* XBAR2_IN105 <- TPM1 TPM_CH_TRIGGER1 */ +#define IMXRT_XBAR2_IN_TPM1_TPM_CH_TRIGGER2 IMXRT_XBAR2(XBAR_INPUT, 106) /* XBAR2_IN106 <- TPM1 TPM_CH_TRIGGER2 */ +#define IMXRT_XBAR2_IN_TPM1_TPM_CH_TRIGGER3 IMXRT_XBAR2(XBAR_INPUT, 107) /* XBAR2_IN107 <- TPM1 TPM_CH_TRIGGER3 */ +#define IMXRT_XBAR2_IN_TPM1_TPM_TRIGGER IMXRT_XBAR2(XBAR_INPUT, 108) /* XBAR2_IN108 <- TPM1 TPM_TRIGGER */ +#define IMXRT_XBAR2_IN_TPM2_TPM_CH_TRIGGER0 IMXRT_XBAR2(XBAR_INPUT, 109) /* XBAR2_IN109 <- TPM2 TPM_CH_TRIGGER0 */ +#define IMXRT_XBAR2_IN_TPM2_TPM_CH_TRIGGER1 IMXRT_XBAR2(XBAR_INPUT, 110) /* XBAR2_IN110 <- TPM2 TPM_CH_TRIGGER1 */ +#define IMXRT_XBAR2_IN_TPM2_TPM_CH_TRIGGER2 IMXRT_XBAR2(XBAR_INPUT, 111) /* XBAR2_IN111 <- TPM2 TPM_CH_TRIGGER2 */ +#define IMXRT_XBAR2_IN_TPM2_TPM_CH_TRIGGER3 IMXRT_XBAR2(XBAR_INPUT, 112) /* XBAR2_IN112 <- TPM2 TPM_CH_TRIGGER3 */ +#define IMXRT_XBAR2_IN_TPM2_TPM_TRIGGER IMXRT_XBAR2(XBAR_INPUT, 113) /* XBAR2_IN113 <- TPM2 TPM_TRIGGER */ +#define IMXRT_XBAR2_IN_TPM3_TPM_CH_TRIGGER0 IMXRT_XBAR2(XBAR_INPUT, 114) /* XBAR2_IN114 <- TPM3 TPM_CH_TRIGGER0 */ +#define IMXRT_XBAR2_IN_TPM3_TPM_CH_TRIGGER1 IMXRT_XBAR2(XBAR_INPUT, 115) /* XBAR2_IN115 <- TPM3 TPM_CH_TRIGGER1 */ +#define IMXRT_XBAR2_IN_TPM3_TPM_CH_TRIGGER2 IMXRT_XBAR2(XBAR_INPUT, 116) /* XBAR2_IN116 <- TPM3 TPM_CH_TRIGGER2 */ +#define IMXRT_XBAR2_IN_TPM3_TPM_CH_TRIGGER3 IMXRT_XBAR2(XBAR_INPUT, 117) /* XBAR2_IN117 <- TPM3 TPM_CH_TRIGGER3 */ +#define IMXRT_XBAR2_IN_TPM3_TPM_TRIGGER IMXRT_XBAR2(XBAR_INPUT, 118) /* XBAR2_IN118 <- TPM3 TPM_TRIGGER */ +#define IMXRT_XBAR2_IN_TPM4_TPM_CH_TRIGGER0 IMXRT_XBAR2(XBAR_INPUT, 119) /* XBAR2_IN119 <- TPM4 TPM_CH_TRIGGER0 */ +#define IMXRT_XBAR2_IN_TPM4_TPM_CH_TRIGGER1 IMXRT_XBAR2(XBAR_INPUT, 120) /* XBAR2_IN120 <- TPM4 TPM_CH_TRIGGER1 */ +#define IMXRT_XBAR2_IN_TPM4_TPM_CH_TRIGGER2 IMXRT_XBAR2(XBAR_INPUT, 121) /* XBAR2_IN121 <- TPM4 TPM_CH_TRIGGER2 */ +#define IMXRT_XBAR2_IN_TPM4_TPM_CH_TRIGGER3 IMXRT_XBAR2(XBAR_INPUT, 122) /* XBAR2_IN122 <- TPM4 TPM_CH_TRIGGER3 */ +#define IMXRT_XBAR2_IN_TPM4_TPM_TRIGGER IMXRT_XBAR2(XBAR_INPUT, 123) /* XBAR2_IN123 <- TPM4 TPM_TRIGGER */ +#define IMXRT_XBAR2_IN_TPM5_TPM_CH_TRIGGER0 IMXRT_XBAR2(XBAR_INPUT, 124) /* XBAR2_IN124 <- TPM5 TPM_CH_TRIGGER0 */ +#define IMXRT_XBAR2_IN_TPM5_TPM_CH_TRIGGER1 IMXRT_XBAR2(XBAR_INPUT, 125) /* XBAR2_IN125 <- TPM5 TPM_CH_TRIGGER1 */ +#define IMXRT_XBAR2_IN_TPM5_TPM_CH_TRIGGER2 IMXRT_XBAR2(XBAR_INPUT, 126) /* XBAR2_IN126 <- TPM5 TPM_CH_TRIGGER2 */ +#define IMXRT_XBAR2_IN_TPM5_TPM_CH_TRIGGER3 IMXRT_XBAR2(XBAR_INPUT, 127) /* XBAR2_IN127 <- TPM5 TPM_CH_TRIGGER3 */ +#define IMXRT_XBAR2_IN_TPM5_TPM_TRIGGER IMXRT_XBAR2(XBAR_INPUT, 128) /* XBAR2_IN128 <- TPM5 TPM_TRIGGER */ +#define IMXRT_XBAR2_IN_TPM6_TPM_CH_TRIGGER0 IMXRT_XBAR2(XBAR_INPUT, 129) /* XBAR2_IN129 <- TPM6 TPM_CH_TRIGGER0 */ +#define IMXRT_XBAR2_IN_TPM6_TPM_CH_TRIGGER1 IMXRT_XBAR2(XBAR_INPUT, 130) /* XBAR2_IN130 <- TPM6 TPM_CH_TRIGGER1 */ +#define IMXRT_XBAR2_IN_TPM6_TPM_CH_TRIGGER2 IMXRT_XBAR2(XBAR_INPUT, 131) /* XBAR2_IN131 <- TPM6 TPM_CH_TRIGGER2 */ +#define IMXRT_XBAR2_IN_TPM6_TPM_CH_TRIGGER3 IMXRT_XBAR2(XBAR_INPUT, 132) /* XBAR2_IN132 <- TPM6 TPM_CH_TRIGGER3 */ +#define IMXRT_XBAR2_IN_TPM6_TPM_TRIGGER IMXRT_XBAR2(XBAR_INPUT, 133) /* XBAR2_IN133 <- TPM6 TPM_TRIGGER */ +#define IMXRT_XBAR2_IN_LPTMR1_LPTIMER_TRIGGER_DELAY IMXRT_XBAR2(XBAR_INPUT, 134) /* XBAR2_IN134 <- LPTMR1 LPTIMER_TRIGGER_DELAY */ +#define IMXRT_XBAR2_IN_LPTMR2_LPTIMER_TRIGGER_DELAY IMXRT_XBAR2(XBAR_INPUT, 135) /* XBAR2_IN135 <- LPTMR2 LPTIMER_TRIGGER_DELAY */ +#define IMXRT_XBAR2_IN_LPTMR3_LPTIMER_TRIGGER_DELAY IMXRT_XBAR2(XBAR_INPUT, 136) /* XBAR2_IN136 <- LPTMR3 LPTIMER_TRIGGER_DELAY */ +#define IMXRT_XBAR2_IN_NETC_TMR_1588_PP1 IMXRT_XBAR2(XBAR_INPUT, 137) /* XBAR2_IN137 <- NETC TMR_1588_PP1 */ +#define IMXRT_XBAR2_IN_NETC_TMR_1588_PP2 IMXRT_XBAR2(XBAR_INPUT, 138) /* XBAR2_IN138 <- NETC TMR_1588_PP2 */ +#define IMXRT_XBAR2_IN_NETC_TMR_1588_PP3 IMXRT_XBAR2(XBAR_INPUT, 139) /* XBAR2_IN139 <- NETC TMR_1588_PP3 */ +#define IMXRT_XBAR2_IN_SINC1_CHANNEL_0_BREAK_DUE_TO_CLOCK_ABSENCE_DETECTED IMXRT_XBAR2(XBAR_INPUT, 140) /* XBAR2_IN140 <- SINC1 Channel 0 break due to clock absence detected */ +#define IMXRT_XBAR2_IN_SINC1_CHANNEL_1_BREAK_DUE_TO_CLOCK_ABSENCE_DETECTED IMXRT_XBAR2(XBAR_INPUT, 141) /* XBAR2_IN141 <- SINC1 Channel 1 break due to clock absence detected */ +#define IMXRT_XBAR2_IN_SINC1_CHANNEL_2_BREAK_DUE_TO_CLOCK_ABSENCE_DETECTED IMXRT_XBAR2(XBAR_INPUT, 142) /* XBAR2_IN142 <- SINC1 Channel 2 break due to clock absence detected */ +#define IMXRT_XBAR2_IN_SINC1_CHANNEL_3_BREAK_DUE_TO_CLOCK_ABSENCE_DETECTED IMXRT_XBAR2(XBAR_INPUT, 143) /* XBAR2_IN143 <- SINC1 Channel 3 break due to clock absence detected */ +#define IMXRT_XBAR2_IN_SINC2_CHANNEL_0_BREAK_DUE_TO_CLOCK_ABSENCE_DETECTED IMXRT_XBAR2(XBAR_INPUT, 144) /* XBAR2_IN144 <- SINC2 Channel 0 break due to clock absence detected */ +#define IMXRT_XBAR2_IN_SINC2_CHANNEL_1_BREAK_DUE_TO_CLOCK_ABSENCE_DETECTED IMXRT_XBAR2(XBAR_INPUT, 145) /* XBAR2_IN145 <- SINC2 Channel 1 break due to clock absence detected */ +#define IMXRT_XBAR2_IN_SINC2_CHANNEL_2_BREAK_DUE_TO_CLOCK_ABSENCE_DETECTED IMXRT_XBAR2(XBAR_INPUT, 146) /* XBAR2_IN146 <- SINC2 Channel 2 break due to clock absence detected */ +#define IMXRT_XBAR2_IN_SINC2_CHANNEL_3_BREAK_DUE_TO_CLOCK_ABSENCE_DETECTED IMXRT_XBAR2(XBAR_INPUT, 147) /* XBAR2_IN147 <- SINC2 Channel 3 break due to clock absence detected */ +#define IMXRT_XBAR2_IN_SINC3_CHANNEL_0_BREAK_DUE_TO_CLOCK_ABSENCE_DETECTED IMXRT_XBAR2(XBAR_INPUT, 148) /* XBAR2_IN148 <- SINC3 Channel 0 break due to clock absence detected */ +#define IMXRT_XBAR2_IN_SINC3_CHANNEL_1_BREAK_DUE_TO_CLOCK_ABSENCE_DETECTED IMXRT_XBAR2(XBAR_INPUT, 149) /* XBAR2_IN149 <- SINC3 Channel 1 break due to clock absence detected */ +#define IMXRT_XBAR2_IN_SINC3_CHANNEL_2_BREAK_DUE_TO_CLOCK_ABSENCE_DETECTED IMXRT_XBAR2(XBAR_INPUT, 150) /* XBAR2_IN150 <- SINC3 Channel 2 break due to clock absence detected */ +#define IMXRT_XBAR2_IN_SINC3_CHANNEL_3_BREAK_DUE_TO_CLOCK_ABSENCE_DETECTED IMXRT_XBAR2(XBAR_INPUT, 151) /* XBAR2_IN151 <- SINC3 Channel 3 break due to clock absence detected */ +#define IMXRT_XBAR2_IN_RESERVED IMXRT_XBAR2(XBAR_INPUT, 152) /* XBAR2_IN152 <- - Reserved */ +#define IMXRT_XBAR2_IN_RESERVED_2 IMXRT_XBAR2(XBAR_INPUT, 153) /* XBAR2_IN153 <- - Reserved */ +#define IMXRT_XBAR2_IN_RESERVED_3 IMXRT_XBAR2(XBAR_INPUT, 154) /* XBAR2_IN154 <- - Reserved */ +#define IMXRT_XBAR2_IN_RESERVED_4 IMXRT_XBAR2(XBAR_INPUT, 155) /* XBAR2_IN155 <- - Reserved */ +#define IMXRT_XBAR2_IN_EQDC1_POS_MATCH0 IMXRT_XBAR2(XBAR_INPUT, 156) /* XBAR2_IN156 <- eQDC1 POS_MATCH0 */ +#define IMXRT_XBAR2_IN_EQDC1_POS_MATCH1 IMXRT_XBAR2(XBAR_INPUT, 157) /* XBAR2_IN157 <- eQDC1 POS_MATCH1 */ +#define IMXRT_XBAR2_IN_EQDC1_POS_MATCH2 IMXRT_XBAR2(XBAR_INPUT, 158) /* XBAR2_IN158 <- eQDC1 POS_MATCH2 */ +#define IMXRT_XBAR2_IN_EQDC1_POS_MATCH3 IMXRT_XBAR2(XBAR_INPUT, 159) /* XBAR2_IN159 <- eQDC1 POS_MATCH3 */ +#define IMXRT_XBAR2_IN_EQDC1_COMP_FLG0 IMXRT_XBAR2(XBAR_INPUT, 160) /* XBAR2_IN160 <- eQDC1 COMP_FLG0 */ +#define IMXRT_XBAR2_IN_EQDC1_COMP_FLG1 IMXRT_XBAR2(XBAR_INPUT, 161) /* XBAR2_IN161 <- eQDC1 COMP_FLG1 */ +#define IMXRT_XBAR2_IN_EQDC1_COMP_FLG2 IMXRT_XBAR2(XBAR_INPUT, 162) /* XBAR2_IN162 <- eQDC1 COMP_FLG2 */ +#define IMXRT_XBAR2_IN_EQDC1_COMP_FLG3 IMXRT_XBAR2(XBAR_INPUT, 163) /* XBAR2_IN163 <- eQDC1 COMP_FLG3 */ +#define IMXRT_XBAR2_IN_EQDC1_CNT_DN IMXRT_XBAR2(XBAR_INPUT, 164) /* XBAR2_IN164 <- eQDC1 CNT_DN */ +#define IMXRT_XBAR2_IN_EQDC1_CNT_UP IMXRT_XBAR2(XBAR_INPUT, 165) /* XBAR2_IN165 <- eQDC1 CNT_UP */ +#define IMXRT_XBAR2_IN_EQDC1_DIR IMXRT_XBAR2(XBAR_INPUT, 166) /* XBAR2_IN166 <- eQDC1 DIR */ +#define IMXRT_XBAR2_IN_EQDC3_POS_MATCH0 IMXRT_XBAR2(XBAR_INPUT, 167) /* XBAR2_IN167 <- eQDC3 POS_MATCH0 */ +#define IMXRT_XBAR2_IN_EQDC3_POS_MATCH1 IMXRT_XBAR2(XBAR_INPUT, 168) /* XBAR2_IN168 <- eQDC3 POS_MATCH1 */ +#define IMXRT_XBAR2_IN_EQDC3_POS_MATCH2 IMXRT_XBAR2(XBAR_INPUT, 169) /* XBAR2_IN169 <- eQDC3 POS_MATCH2 */ +#define IMXRT_XBAR2_IN_EQDC3_POS_MATCH3 IMXRT_XBAR2(XBAR_INPUT, 170) /* XBAR2_IN170 <- eQDC3 POS_MATCH3 */ +#define IMXRT_XBAR2_IN_EQDC3_COMP_FLG0 IMXRT_XBAR2(XBAR_INPUT, 171) /* XBAR2_IN171 <- eQDC3 COMP_FLG0 */ +#define IMXRT_XBAR2_IN_EQDC3_COMP_FLG1 IMXRT_XBAR2(XBAR_INPUT, 172) /* XBAR2_IN172 <- eQDC3 COMP_FLG1 */ +#define IMXRT_XBAR2_IN_EQDC3_COMP_FLG2 IMXRT_XBAR2(XBAR_INPUT, 173) /* XBAR2_IN173 <- eQDC3 COMP_FLG2 */ +#define IMXRT_XBAR2_IN_EQDC3_COMP_FLG3 IMXRT_XBAR2(XBAR_INPUT, 174) /* XBAR2_IN174 <- eQDC3 COMP_FLG3 */ +#define IMXRT_XBAR2_IN_EQDC3_CNT_DN IMXRT_XBAR2(XBAR_INPUT, 175) /* XBAR2_IN175 <- eQDC3 CNT_DN */ +#define IMXRT_XBAR2_IN_EQDC3_CNT_UP IMXRT_XBAR2(XBAR_INPUT, 176) /* XBAR2_IN176 <- eQDC3 CNT_UP */ +#define IMXRT_XBAR2_IN_EQDC3_DIR IMXRT_XBAR2(XBAR_INPUT, 177) /* XBAR2_IN177 <- eQDC3 DIR */ + +#define IMXRT_XBAR3_IN_GND IMXRT_XBAR3(XBAR_INPUT, 0) /* XBAR3_IN0 <- - GND */ +#define IMXRT_XBAR3_IN_1B1 IMXRT_XBAR3(XBAR_INPUT, 1) /* XBAR3_IN1 <- - 1'B1 */ +#define IMXRT_XBAR3_IN_GND_2 IMXRT_XBAR3(XBAR_INPUT, 2) /* XBAR3_IN2 <- - GND */ +#define IMXRT_XBAR3_IN_1B1_2 IMXRT_XBAR3(XBAR_INPUT, 3) /* XBAR3_IN3 <- - 1'B1 */ +#define IMXRT_XBAR3_IN_CMP1_COUT IMXRT_XBAR3(XBAR_INPUT, 4) /* XBAR3_IN4 <- CMP1 COUT */ +#define IMXRT_XBAR3_IN_CMP2_COUT IMXRT_XBAR3(XBAR_INPUT, 5) /* XBAR3_IN5 <- CMP2 COUT */ +#define IMXRT_XBAR3_IN_CMP3_COUT IMXRT_XBAR3(XBAR_INPUT, 6) /* XBAR3_IN6 <- CMP3 COUT */ +#define IMXRT_XBAR3_IN_CMP4_COUT IMXRT_XBAR3(XBAR_INPUT, 7) /* XBAR3_IN7 <- CMP4 COUT */ +#define IMXRT_XBAR3_IN_TMR1_TMR0_OUTPUT IMXRT_XBAR3(XBAR_INPUT, 8) /* XBAR3_IN8 <- TMR1 TMR0_OUTPUT */ +#define IMXRT_XBAR3_IN_TMR1_TMR1_OUTPUT IMXRT_XBAR3(XBAR_INPUT, 9) /* XBAR3_IN9 <- TMR1 TMR1_OUTPUT */ +#define IMXRT_XBAR3_IN_TMR1_TMR2_OUTPUT IMXRT_XBAR3(XBAR_INPUT, 10) /* XBAR3_IN10 <- TMR1 TMR2_OUTPUT */ +#define IMXRT_XBAR3_IN_TMR1_TMR3_OUTPUT IMXRT_XBAR3(XBAR_INPUT, 11) /* XBAR3_IN11 <- TMR1 TMR3_OUTPUT */ +#define IMXRT_XBAR3_IN_TMR2_TMR0_OUTPUT IMXRT_XBAR3(XBAR_INPUT, 12) /* XBAR3_IN12 <- TMR2 TMR0_OUTPUT */ +#define IMXRT_XBAR3_IN_TMR2_TMR1_OUTPUT IMXRT_XBAR3(XBAR_INPUT, 13) /* XBAR3_IN13 <- TMR2 TMR1_OUTPUT */ +#define IMXRT_XBAR3_IN_TMR2_TMR2_OUTPUT IMXRT_XBAR3(XBAR_INPUT, 14) /* XBAR3_IN14 <- TMR2 TMR2_OUTPUT */ +#define IMXRT_XBAR3_IN_TMR2_TMR3_OUTPUT IMXRT_XBAR3(XBAR_INPUT, 15) /* XBAR3_IN15 <- TMR2 TMR3_OUTPUT */ +#define IMXRT_XBAR3_IN_TMR3_TMR0_OUTPUT IMXRT_XBAR3(XBAR_INPUT, 16) /* XBAR3_IN16 <- TMR3 TMR0_OUTPUT */ +#define IMXRT_XBAR3_IN_TMR3_TMR1_OUTPUT IMXRT_XBAR3(XBAR_INPUT, 17) /* XBAR3_IN17 <- TMR3 TMR1_OUTPUT */ +#define IMXRT_XBAR3_IN_TMR3_TMR2_OUTPUT IMXRT_XBAR3(XBAR_INPUT, 18) /* XBAR3_IN18 <- TMR3 TMR2_OUTPUT */ +#define IMXRT_XBAR3_IN_TMR3_TMR3_OUTPUT IMXRT_XBAR3(XBAR_INPUT, 19) /* XBAR3_IN19 <- TMR3 TMR3_OUTPUT */ +#define IMXRT_XBAR3_IN_TMR4_TMR0_OUTPUT IMXRT_XBAR3(XBAR_INPUT, 20) /* XBAR3_IN20 <- TMR4 TMR0_OUTPUT */ +#define IMXRT_XBAR3_IN_TMR4_TMR1_OUTPUT IMXRT_XBAR3(XBAR_INPUT, 21) /* XBAR3_IN21 <- TMR4 TMR1_OUTPUT */ +#define IMXRT_XBAR3_IN_TMR4_TMR2_OUTPUT IMXRT_XBAR3(XBAR_INPUT, 22) /* XBAR3_IN22 <- TMR4 TMR2_OUTPUT */ +#define IMXRT_XBAR3_IN_TMR4_TMR3_OUTPUT IMXRT_XBAR3(XBAR_INPUT, 23) /* XBAR3_IN23 <- TMR4 TMR3_OUTPUT */ +#define IMXRT_XBAR3_IN_TMR5_TMR0_OUTPUT IMXRT_XBAR3(XBAR_INPUT, 24) /* XBAR3_IN24 <- TMR5 TMR0_OUTPUT */ +#define IMXRT_XBAR3_IN_TMR5_TMR1_OUTPUT IMXRT_XBAR3(XBAR_INPUT, 25) /* XBAR3_IN25 <- TMR5 TMR1_OUTPUT */ +#define IMXRT_XBAR3_IN_TMR5_TMR2_OUTPUT IMXRT_XBAR3(XBAR_INPUT, 26) /* XBAR3_IN26 <- TMR5 TMR2_OUTPUT */ +#define IMXRT_XBAR3_IN_TMR5_TMR3_OUTPUT IMXRT_XBAR3(XBAR_INPUT, 27) /* XBAR3_IN27 <- TMR5 TMR3_OUTPUT */ +#define IMXRT_XBAR3_IN_TMR6_TMR0_OUTPUT IMXRT_XBAR3(XBAR_INPUT, 28) /* XBAR3_IN28 <- TMR6 TMR0_OUTPUT */ +#define IMXRT_XBAR3_IN_TMR6_TMR1_OUTPUT IMXRT_XBAR3(XBAR_INPUT, 29) /* XBAR3_IN29 <- TMR6 TMR1_OUTPUT */ +#define IMXRT_XBAR3_IN_TMR6_TMR2_OUTPUT IMXRT_XBAR3(XBAR_INPUT, 30) /* XBAR3_IN30 <- TMR6 TMR2_OUTPUT */ +#define IMXRT_XBAR3_IN_TMR6_TMR3_OUTPUT IMXRT_XBAR3(XBAR_INPUT, 31) /* XBAR3_IN31 <- TMR6 TMR3_OUTPUT */ +#define IMXRT_XBAR3_IN_TMR7_TMR0_OUTPUT IMXRT_XBAR3(XBAR_INPUT, 32) /* XBAR3_IN32 <- TMR7 TMR0_OUTPUT */ +#define IMXRT_XBAR3_IN_TMR7_TMR1_OUTPUT IMXRT_XBAR3(XBAR_INPUT, 33) /* XBAR3_IN33 <- TMR7 TMR1_OUTPUT */ +#define IMXRT_XBAR3_IN_TMR7_TMR2_OUTPUT IMXRT_XBAR3(XBAR_INPUT, 34) /* XBAR3_IN34 <- TMR7 TMR2_OUTPUT */ +#define IMXRT_XBAR3_IN_TMR7_TMR3_OUTPUT IMXRT_XBAR3(XBAR_INPUT, 35) /* XBAR3_IN35 <- TMR7 TMR3_OUTPUT */ +#define IMXRT_XBAR3_IN_TMR8_TMR0_OUTPUT IMXRT_XBAR3(XBAR_INPUT, 36) /* XBAR3_IN36 <- TMR8 TMR0_OUTPUT */ +#define IMXRT_XBAR3_IN_TMR8_TMR1_OUTPUT IMXRT_XBAR3(XBAR_INPUT, 37) /* XBAR3_IN37 <- TMR8 TMR1_OUTPUT */ +#define IMXRT_XBAR3_IN_TMR8_TMR2_OUTPUT IMXRT_XBAR3(XBAR_INPUT, 38) /* XBAR3_IN38 <- TMR8 TMR2_OUTPUT */ +#define IMXRT_XBAR3_IN_TMR8_TMR3_OUTPUT IMXRT_XBAR3(XBAR_INPUT, 39) /* XBAR3_IN39 <- TMR8 TMR3_OUTPUT */ +#define IMXRT_XBAR3_IN_FLEXPWM1_PWM0_MUX_TRIGGER0 IMXRT_XBAR3(XBAR_INPUT, 40) /* XBAR3_IN40 <- FLEXPWM1 PWM0_MUX_TRIGGER0 */ +#define IMXRT_XBAR3_IN_FLEXPWM1_PWM1_MUX_TRIGGER0 IMXRT_XBAR3(XBAR_INPUT, 41) /* XBAR3_IN41 <- FLEXPWM1 PWM1_MUX_TRIGGER0 */ +#define IMXRT_XBAR3_IN_FLEXPWM1_PWM2_MUX_TRIGGER0 IMXRT_XBAR3(XBAR_INPUT, 42) /* XBAR3_IN42 <- FLEXPWM1 PWM2_MUX_TRIGGER0 */ +#define IMXRT_XBAR3_IN_FLEXPWM1_PWM3_MUX_TRIGGER0 IMXRT_XBAR3(XBAR_INPUT, 43) /* XBAR3_IN43 <- FLEXPWM1 PWM3_MUX_TRIGGER0 */ +#define IMXRT_XBAR3_IN_FLEXPWM2_PWM0_MUX_TRIGGER0 IMXRT_XBAR3(XBAR_INPUT, 44) /* XBAR3_IN44 <- FLEXPWM2 PWM0_MUX_TRIGGER0 */ +#define IMXRT_XBAR3_IN_FLEXPWM2_PWM1_MUX_TRIGGER0 IMXRT_XBAR3(XBAR_INPUT, 45) /* XBAR3_IN45 <- FLEXPWM2 PWM1_MUX_TRIGGER0 */ +#define IMXRT_XBAR3_IN_FLEXPWM2_PWM2_MUX_TRIGGER0 IMXRT_XBAR3(XBAR_INPUT, 46) /* XBAR3_IN46 <- FLEXPWM2 PWM2_MUX_TRIGGER0 */ +#define IMXRT_XBAR3_IN_FLEXPWM2_PWM3_MUX_TRIGGER0 IMXRT_XBAR3(XBAR_INPUT, 47) /* XBAR3_IN47 <- FLEXPWM2 PWM3_MUX_TRIGGER0 */ +#define IMXRT_XBAR3_IN_FLEXPWM3_PWM0_MUX_TRIGGER0 IMXRT_XBAR3(XBAR_INPUT, 48) /* XBAR3_IN48 <- FLEXPWM3 PWM0_MUX_TRIGGER0 */ +#define IMXRT_XBAR3_IN_FLEXPWM3_PWM1_MUX_TRIGGER0 IMXRT_XBAR3(XBAR_INPUT, 49) /* XBAR3_IN49 <- FLEXPWM3 PWM1_MUX_TRIGGER0 */ +#define IMXRT_XBAR3_IN_FLEXPWM3_PWM2_MUX_TRIGGER0 IMXRT_XBAR3(XBAR_INPUT, 50) /* XBAR3_IN50 <- FLEXPWM3 PWM2_MUX_TRIGGER0 */ +#define IMXRT_XBAR3_IN_FLEXPWM3_PWM3_MUX_TRIGGER0 IMXRT_XBAR3(XBAR_INPUT, 51) /* XBAR3_IN51 <- FLEXPWM3 PWM3_MUX_TRIGGER0 */ +#define IMXRT_XBAR3_IN_FLEXPWM4_PWM0_MUX_TRIGGER0 IMXRT_XBAR3(XBAR_INPUT, 52) /* XBAR3_IN52 <- FLEXPWM4 PWM0_MUX_TRIGGER0 */ +#define IMXRT_XBAR3_IN_FLEXPWM4_PWM1_MUX_TRIGGER0 IMXRT_XBAR3(XBAR_INPUT, 53) /* XBAR3_IN53 <- FLEXPWM4 PWM1_MUX_TRIGGER0 */ +#define IMXRT_XBAR3_IN_FLEXPWM4_PWM2_MUX_TRIGGER0 IMXRT_XBAR3(XBAR_INPUT, 54) /* XBAR3_IN54 <- FLEXPWM4 PWM2_MUX_TRIGGER0 */ +#define IMXRT_XBAR3_IN_FLEXPWM4_PWM3_MUX_TRIGGER0 IMXRT_XBAR3(XBAR_INPUT, 55) /* XBAR3_IN55 <- FLEXPWM4 PWM3_MUX_TRIGGER0 */ +#define IMXRT_XBAR3_IN_LPIT1_LPIT_TRIG_OUT0 IMXRT_XBAR3(XBAR_INPUT, 56) /* XBAR3_IN56 <- LPIT1 LPIT_TRIG_OUT0 */ +#define IMXRT_XBAR3_IN_LPIT1_LPIT_TRIG_OUT1 IMXRT_XBAR3(XBAR_INPUT, 57) /* XBAR3_IN57 <- LPIT1 LPIT_TRIG_OUT1 */ +#define IMXRT_XBAR3_IN_LPIT1_LPIT_TRIG_OUT2 IMXRT_XBAR3(XBAR_INPUT, 58) /* XBAR3_IN58 <- LPIT1 LPIT_TRIG_OUT2 */ +#define IMXRT_XBAR3_IN_LPIT1_LPIT_TRIG_OUT3 IMXRT_XBAR3(XBAR_INPUT, 59) /* XBAR3_IN59 <- LPIT1 LPIT_TRIG_OUT3 */ +#define IMXRT_XBAR3_IN_LPIT2_LPIT_TRIG_OUT0 IMXRT_XBAR3(XBAR_INPUT, 60) /* XBAR3_IN60 <- LPIT2 LPIT_TRIG_OUT0 */ +#define IMXRT_XBAR3_IN_LPIT2_LPIT_TRIG_OUT1 IMXRT_XBAR3(XBAR_INPUT, 61) /* XBAR3_IN61 <- LPIT2 LPIT_TRIG_OUT1 */ +#define IMXRT_XBAR3_IN_LPIT2_LPIT_TRIG_OUT2 IMXRT_XBAR3(XBAR_INPUT, 62) /* XBAR3_IN62 <- LPIT2 LPIT_TRIG_OUT2 */ +#define IMXRT_XBAR3_IN_LPIT2_LPIT_TRIG_OUT3 IMXRT_XBAR3(XBAR_INPUT, 63) /* XBAR3_IN63 <- LPIT2 LPIT_TRIG_OUT3 */ +#define IMXRT_XBAR3_IN_LPIT3_LPIT_TRIG_OUT0 IMXRT_XBAR3(XBAR_INPUT, 64) /* XBAR3_IN64 <- LPIT3 LPIT_TRIG_OUT0 */ +#define IMXRT_XBAR3_IN_LPIT3_LPIT_TRIG_OUT1 IMXRT_XBAR3(XBAR_INPUT, 65) /* XBAR3_IN65 <- LPIT3 LPIT_TRIG_OUT1 */ +#define IMXRT_XBAR3_IN_LPIT3_LPIT_TRIG_OUT2 IMXRT_XBAR3(XBAR_INPUT, 66) /* XBAR3_IN66 <- LPIT3 LPIT_TRIG_OUT2 */ +#define IMXRT_XBAR3_IN_LPIT3_LPIT_TRIG_OUT3 IMXRT_XBAR3(XBAR_INPUT, 67) /* XBAR3_IN67 <- LPIT3 LPIT_TRIG_OUT3 */ +#define IMXRT_XBAR3_IN_SINC2_PULSE_TRG0 IMXRT_XBAR3(XBAR_INPUT, 68) /* XBAR3_IN68 <- SINC2 PULSE_TRG0 */ +#define IMXRT_XBAR3_IN_SINC2_PULSE_TRG1 IMXRT_XBAR3(XBAR_INPUT, 69) /* XBAR3_IN69 <- SINC2 PULSE_TRG1 */ +#define IMXRT_XBAR3_IN_SINC2_PULSE_TRG2 IMXRT_XBAR3(XBAR_INPUT, 70) /* XBAR3_IN70 <- SINC2 PULSE_TRG2 */ +#define IMXRT_XBAR3_IN_SINC2_PULSE_TRG3 IMXRT_XBAR3(XBAR_INPUT, 71) /* XBAR3_IN71 <- SINC2 PULSE_TRG3 */ +#define IMXRT_XBAR3_IN_EDMA4_DMA_TRIGGER_OUT0 IMXRT_XBAR3(XBAR_INPUT, 72) /* XBAR3_IN72 <- eDMA4 DMA_TRIGGER_OUT0 */ +#define IMXRT_XBAR3_IN_EDMA4_DMA_TRIGGER_OUT1 IMXRT_XBAR3(XBAR_INPUT, 73) /* XBAR3_IN73 <- eDMA4 DMA_TRIGGER_OUT1 */ +#define IMXRT_XBAR3_IN_EDMA4_DMA_TRIGGER_OUT2 IMXRT_XBAR3(XBAR_INPUT, 74) /* XBAR3_IN74 <- eDMA4 DMA_TRIGGER_OUT2 */ +#define IMXRT_XBAR3_IN_EDMA4_DMA_TRIGGER_OUT3 IMXRT_XBAR3(XBAR_INPUT, 75) /* XBAR3_IN75 <- eDMA4 DMA_TRIGGER_OUT3 */ +#define IMXRT_XBAR3_IN_EDMA4_DMA_TRIGGER_OUT4 IMXRT_XBAR3(XBAR_INPUT, 76) /* XBAR3_IN76 <- eDMA4 DMA_TRIGGER_OUT4 */ +#define IMXRT_XBAR3_IN_EDMA4_DMA_TRIGGER_OUT5 IMXRT_XBAR3(XBAR_INPUT, 77) /* XBAR3_IN77 <- eDMA4 DMA_TRIGGER_OUT5 */ +#define IMXRT_XBAR3_IN_EDMA4_DMA_TRIGGER_OUT6 IMXRT_XBAR3(XBAR_INPUT, 78) /* XBAR3_IN78 <- eDMA4 DMA_TRIGGER_OUT6 */ +#define IMXRT_XBAR3_IN_EDMA4_DMA_TRIGGER_OUT7 IMXRT_XBAR3(XBAR_INPUT, 79) /* XBAR3_IN79 <- eDMA4 DMA_TRIGGER_OUT7 */ +#define IMXRT_XBAR3_IN_EDMA3_DMA_TRIGGER_OUT0 IMXRT_XBAR3(XBAR_INPUT, 80) /* XBAR3_IN80 <- eDMA3 DMA_TRIGGER_OUT0 */ +#define IMXRT_XBAR3_IN_EDMA3_DMA_TRIGGER_OUT1 IMXRT_XBAR3(XBAR_INPUT, 81) /* XBAR3_IN81 <- eDMA3 DMA_TRIGGER_OUT1 */ +#define IMXRT_XBAR3_IN_EDMA3_DMA_TRIGGER_OUT2 IMXRT_XBAR3(XBAR_INPUT, 82) /* XBAR3_IN82 <- eDMA3 DMA_TRIGGER_OUT2 */ +#define IMXRT_XBAR3_IN_EDMA3_DMA_TRIGGER_OUT3 IMXRT_XBAR3(XBAR_INPUT, 83) /* XBAR3_IN83 <- eDMA3 DMA_TRIGGER_OUT3 */ +#define IMXRT_XBAR3_IN_EDMA3_DMA_TRIGGER_OUT4 IMXRT_XBAR3(XBAR_INPUT, 84) /* XBAR3_IN84 <- eDMA3 DMA_TRIGGER_OUT4 */ +#define IMXRT_XBAR3_IN_EDMA3_DMA_TRIGGER_OUT5 IMXRT_XBAR3(XBAR_INPUT, 85) /* XBAR3_IN85 <- eDMA3 DMA_TRIGGER_OUT5 */ +#define IMXRT_XBAR3_IN_EDMA3_DMA_TRIGGER_OUT6 IMXRT_XBAR3(XBAR_INPUT, 86) /* XBAR3_IN86 <- eDMA3 DMA_TRIGGER_OUT6 */ +#define IMXRT_XBAR3_IN_EDMA3_DMA_TRIGGER_OUT7 IMXRT_XBAR3(XBAR_INPUT, 87) /* XBAR3_IN87 <- eDMA3 DMA_TRIGGER_OUT7 */ +#define IMXRT_XBAR3_IN_ADC1_ADC_TCOMP_PULSE0 IMXRT_XBAR3(XBAR_INPUT, 88) /* XBAR3_IN88 <- ADC1 ADC_TCOMP_PULSE0 */ +#define IMXRT_XBAR3_IN_ADC1_ADC_TCOMP_PULSE1 IMXRT_XBAR3(XBAR_INPUT, 89) /* XBAR3_IN89 <- ADC1 ADC_TCOMP_PULSE1 */ +#define IMXRT_XBAR3_IN_ADC1_ADC_TCOMP_PULSE2 IMXRT_XBAR3(XBAR_INPUT, 90) /* XBAR3_IN90 <- ADC1 ADC_TCOMP_PULSE2 */ +#define IMXRT_XBAR3_IN_ADC1_ADC_TCOMP_PULSE3 IMXRT_XBAR3(XBAR_INPUT, 91) /* XBAR3_IN91 <- ADC1 ADC_TCOMP_PULSE3 */ +#define IMXRT_XBAR3_IN_ADC1_ADC_TCOMP_PULSE4 IMXRT_XBAR3(XBAR_INPUT, 92) /* XBAR3_IN92 <- ADC1 ADC_TCOMP_PULSE4 */ +#define IMXRT_XBAR3_IN_ADC1_ADC_TCOMP_PULSE5 IMXRT_XBAR3(XBAR_INPUT, 93) /* XBAR3_IN93 <- ADC1 ADC_TCOMP_PULSE5 */ +#define IMXRT_XBAR3_IN_ADC1_ADC_TCOMP_PULSE6 IMXRT_XBAR3(XBAR_INPUT, 94) /* XBAR3_IN94 <- ADC1 ADC_TCOMP_PULSE6 */ +#define IMXRT_XBAR3_IN_ADC1_ADC_TCOMP_PULSE7 IMXRT_XBAR3(XBAR_INPUT, 95) /* XBAR3_IN95 <- ADC1 ADC_TCOMP_PULSE7 */ +#define IMXRT_XBAR3_IN_ADC2_ADC_TCOMP_PULSE0 IMXRT_XBAR3(XBAR_INPUT, 96) /* XBAR3_IN96 <- ADC2 ADC_TCOMP_PULSE0 */ +#define IMXRT_XBAR3_IN_ADC2_ADC_TCOMP_PULSE1 IMXRT_XBAR3(XBAR_INPUT, 97) /* XBAR3_IN97 <- ADC2 ADC_TCOMP_PULSE1 */ +#define IMXRT_XBAR3_IN_ADC2_ADC_TCOMP_PULSE2 IMXRT_XBAR3(XBAR_INPUT, 98) /* XBAR3_IN98 <- ADC2 ADC_TCOMP_PULSE2 */ +#define IMXRT_XBAR3_IN_ADC2_ADC_TCOMP_PULSE3 IMXRT_XBAR3(XBAR_INPUT, 99) /* XBAR3_IN99 <- ADC2 ADC_TCOMP_PULSE3 */ +#define IMXRT_XBAR3_IN_ADC2_ADC_TCOMP_PULSE4 IMXRT_XBAR3(XBAR_INPUT, 100) /* XBAR3_IN100 <- ADC2 ADC_TCOMP_PULSE4 */ +#define IMXRT_XBAR3_IN_ADC2_ADC_TCOMP_PULSE5 IMXRT_XBAR3(XBAR_INPUT, 101) /* XBAR3_IN101 <- ADC2 ADC_TCOMP_PULSE5 */ +#define IMXRT_XBAR3_IN_ADC2_ADC_TCOMP_PULSE6 IMXRT_XBAR3(XBAR_INPUT, 102) /* XBAR3_IN102 <- ADC2 ADC_TCOMP_PULSE6 */ +#define IMXRT_XBAR3_IN_ADC2_ADC_TCOMP_PULSE7 IMXRT_XBAR3(XBAR_INPUT, 103) /* XBAR3_IN103 <- ADC2 ADC_TCOMP_PULSE7 */ +#define IMXRT_XBAR3_IN_TPM1_TPM_CH_TRIGGER0 IMXRT_XBAR3(XBAR_INPUT, 104) /* XBAR3_IN104 <- TPM1 TPM_CH_TRIGGER0 */ +#define IMXRT_XBAR3_IN_TPM1_TPM_CH_TRIGGER1 IMXRT_XBAR3(XBAR_INPUT, 105) /* XBAR3_IN105 <- TPM1 TPM_CH_TRIGGER1 */ +#define IMXRT_XBAR3_IN_TPM1_TPM_CH_TRIGGER2 IMXRT_XBAR3(XBAR_INPUT, 106) /* XBAR3_IN106 <- TPM1 TPM_CH_TRIGGER2 */ +#define IMXRT_XBAR3_IN_TPM1_TPM_CH_TRIGGER3 IMXRT_XBAR3(XBAR_INPUT, 107) /* XBAR3_IN107 <- TPM1 TPM_CH_TRIGGER3 */ +#define IMXRT_XBAR3_IN_TPM1_TPM_TRIGGER IMXRT_XBAR3(XBAR_INPUT, 108) /* XBAR3_IN108 <- TPM1 TPM_TRIGGER */ +#define IMXRT_XBAR3_IN_TPM2_TPM_CH_TRIGGER0 IMXRT_XBAR3(XBAR_INPUT, 109) /* XBAR3_IN109 <- TPM2 TPM_CH_TRIGGER0 */ +#define IMXRT_XBAR3_IN_TPM2_TPM_CH_TRIGGER1 IMXRT_XBAR3(XBAR_INPUT, 110) /* XBAR3_IN110 <- TPM2 TPM_CH_TRIGGER1 */ +#define IMXRT_XBAR3_IN_TPM2_TPM_CH_TRIGGER2 IMXRT_XBAR3(XBAR_INPUT, 111) /* XBAR3_IN111 <- TPM2 TPM_CH_TRIGGER2 */ +#define IMXRT_XBAR3_IN_TPM2_TPM_CH_TRIGGER3 IMXRT_XBAR3(XBAR_INPUT, 112) /* XBAR3_IN112 <- TPM2 TPM_CH_TRIGGER3 */ +#define IMXRT_XBAR3_IN_TPM2_TPM_TRIGGER IMXRT_XBAR3(XBAR_INPUT, 113) /* XBAR3_IN113 <- TPM2 TPM_TRIGGER */ +#define IMXRT_XBAR3_IN_TPM3_TPM_CH_TRIGGER0 IMXRT_XBAR3(XBAR_INPUT, 114) /* XBAR3_IN114 <- TPM3 TPM_CH_TRIGGER0 */ +#define IMXRT_XBAR3_IN_TPM3_TPM_CH_TRIGGER1 IMXRT_XBAR3(XBAR_INPUT, 115) /* XBAR3_IN115 <- TPM3 TPM_CH_TRIGGER1 */ +#define IMXRT_XBAR3_IN_TPM3_TPM_CH_TRIGGER2 IMXRT_XBAR3(XBAR_INPUT, 116) /* XBAR3_IN116 <- TPM3 TPM_CH_TRIGGER2 */ +#define IMXRT_XBAR3_IN_TPM3_TPM_CH_TRIGGER3 IMXRT_XBAR3(XBAR_INPUT, 117) /* XBAR3_IN117 <- TPM3 TPM_CH_TRIGGER3 */ +#define IMXRT_XBAR3_IN_TPM3_TPM_TRIGGER IMXRT_XBAR3(XBAR_INPUT, 118) /* XBAR3_IN118 <- TPM3 TPM_TRIGGER */ +#define IMXRT_XBAR3_IN_TPM4_TPM_CH_TRIGGER0 IMXRT_XBAR3(XBAR_INPUT, 119) /* XBAR3_IN119 <- TPM4 TPM_CH_TRIGGER0 */ +#define IMXRT_XBAR3_IN_TPM4_TPM_CH_TRIGGER1 IMXRT_XBAR3(XBAR_INPUT, 120) /* XBAR3_IN120 <- TPM4 TPM_CH_TRIGGER1 */ +#define IMXRT_XBAR3_IN_TPM4_TPM_CH_TRIGGER2 IMXRT_XBAR3(XBAR_INPUT, 121) /* XBAR3_IN121 <- TPM4 TPM_CH_TRIGGER2 */ +#define IMXRT_XBAR3_IN_TPM4_TPM_CH_TRIGGER3 IMXRT_XBAR3(XBAR_INPUT, 122) /* XBAR3_IN122 <- TPM4 TPM_CH_TRIGGER3 */ +#define IMXRT_XBAR3_IN_TPM4_TPM_TRIGGER IMXRT_XBAR3(XBAR_INPUT, 123) /* XBAR3_IN123 <- TPM4 TPM_TRIGGER */ +#define IMXRT_XBAR3_IN_TPM5_TPM_CH_TRIGGER0 IMXRT_XBAR3(XBAR_INPUT, 124) /* XBAR3_IN124 <- TPM5 TPM_CH_TRIGGER0 */ +#define IMXRT_XBAR3_IN_TPM5_TPM_CH_TRIGGER1 IMXRT_XBAR3(XBAR_INPUT, 125) /* XBAR3_IN125 <- TPM5 TPM_CH_TRIGGER1 */ +#define IMXRT_XBAR3_IN_TPM5_TPM_CH_TRIGGER2 IMXRT_XBAR3(XBAR_INPUT, 126) /* XBAR3_IN126 <- TPM5 TPM_CH_TRIGGER2 */ +#define IMXRT_XBAR3_IN_TPM5_TPM_CH_TRIGGER3 IMXRT_XBAR3(XBAR_INPUT, 127) /* XBAR3_IN127 <- TPM5 TPM_CH_TRIGGER3 */ +#define IMXRT_XBAR3_IN_TPM5_TPM_TRIGGER IMXRT_XBAR3(XBAR_INPUT, 128) /* XBAR3_IN128 <- TPM5 TPM_TRIGGER */ +#define IMXRT_XBAR3_IN_TPM6_TPM_CH_TRIGGER0 IMXRT_XBAR3(XBAR_INPUT, 129) /* XBAR3_IN129 <- TPM6 TPM_CH_TRIGGER0 */ +#define IMXRT_XBAR3_IN_TPM6_TPM_CH_TRIGGER1 IMXRT_XBAR3(XBAR_INPUT, 130) /* XBAR3_IN130 <- TPM6 TPM_CH_TRIGGER1 */ +#define IMXRT_XBAR3_IN_TPM6_TPM_CH_TRIGGER2 IMXRT_XBAR3(XBAR_INPUT, 131) /* XBAR3_IN131 <- TPM6 TPM_CH_TRIGGER2 */ +#define IMXRT_XBAR3_IN_TPM6_TPM_CH_TRIGGER3 IMXRT_XBAR3(XBAR_INPUT, 132) /* XBAR3_IN132 <- TPM6 TPM_CH_TRIGGER3 */ +#define IMXRT_XBAR3_IN_TPM6_TPM_TRIGGER IMXRT_XBAR3(XBAR_INPUT, 133) /* XBAR3_IN133 <- TPM6 TPM_TRIGGER */ +#define IMXRT_XBAR3_IN_LPTMR1_LPTIMER_TRIGGER_DELAY IMXRT_XBAR3(XBAR_INPUT, 134) /* XBAR3_IN134 <- LPTMR1 LPTIMER_TRIGGER_DELAY */ +#define IMXRT_XBAR3_IN_LPTMR2_LPTIMER_TRIGGER_DELAY IMXRT_XBAR3(XBAR_INPUT, 135) /* XBAR3_IN135 <- LPTMR2 LPTIMER_TRIGGER_DELAY */ +#define IMXRT_XBAR3_IN_LPTMR3_LPTIMER_TRIGGER_DELAY IMXRT_XBAR3(XBAR_INPUT, 136) /* XBAR3_IN136 <- LPTMR3 LPTIMER_TRIGGER_DELAY */ +#define IMXRT_XBAR3_IN_NETC_TMR_1588_PP1 IMXRT_XBAR3(XBAR_INPUT, 137) /* XBAR3_IN137 <- NETC TMR_1588_PP1 */ +#define IMXRT_XBAR3_IN_NETC_TMR_1588_PP2 IMXRT_XBAR3(XBAR_INPUT, 138) /* XBAR3_IN138 <- NETC TMR_1588_PP2 */ +#define IMXRT_XBAR3_IN_NETC_TMR_1588_PP3 IMXRT_XBAR3(XBAR_INPUT, 139) /* XBAR3_IN139 <- NETC TMR_1588_PP3 */ +#define IMXRT_XBAR3_IN_SINC1_CHANNEL_0_BREAK_DUE_TO_CLOCK_ABSENCE_DETECTED IMXRT_XBAR3(XBAR_INPUT, 140) /* XBAR3_IN140 <- SINC1 Channel 0 break due to clock absence detected */ +#define IMXRT_XBAR3_IN_SINC1_CHANNEL_1_BREAK_DUE_TO_CLOCK_ABSENCE_DETECTED IMXRT_XBAR3(XBAR_INPUT, 141) /* XBAR3_IN141 <- SINC1 Channel 1 break due to clock absence detected */ +#define IMXRT_XBAR3_IN_SINC1_CHANNEL_2_BREAK_DUE_TO_CLOCK_ABSENCE_DETECTED IMXRT_XBAR3(XBAR_INPUT, 142) /* XBAR3_IN142 <- SINC1 Channel 2 break due to clock absence detected */ +#define IMXRT_XBAR3_IN_SINC1_CHANNEL_3_BREAK_DUE_TO_CLOCK_ABSENCE_DETECTED IMXRT_XBAR3(XBAR_INPUT, 143) /* XBAR3_IN143 <- SINC1 Channel 3 break due to clock absence detected */ +#define IMXRT_XBAR3_IN_SINC2_CHANNEL_0_BREAK_DUE_TO_CLOCK_ABSENCE_DETECTED IMXRT_XBAR3(XBAR_INPUT, 144) /* XBAR3_IN144 <- SINC2 Channel 0 break due to clock absence detected */ +#define IMXRT_XBAR3_IN_SINC2_CHANNEL_1_BREAK_DUE_TO_CLOCK_ABSENCE_DETECTED IMXRT_XBAR3(XBAR_INPUT, 145) /* XBAR3_IN145 <- SINC2 Channel 1 break due to clock absence detected */ +#define IMXRT_XBAR3_IN_SINC2_CHANNEL_2_BREAK_DUE_TO_CLOCK_ABSENCE_DETECTED IMXRT_XBAR3(XBAR_INPUT, 146) /* XBAR3_IN146 <- SINC2 Channel 2 break due to clock absence detected */ +#define IMXRT_XBAR3_IN_SINC2_CHANNEL_3_BREAK_DUE_TO_CLOCK_ABSENCE_DETECTED IMXRT_XBAR3(XBAR_INPUT, 147) /* XBAR3_IN147 <- SINC2 Channel 3 break due to clock absence detected */ +#define IMXRT_XBAR3_IN_SINC3_CHANNEL_0_BREAK_DUE_TO_CLOCK_ABSENCE_DETECTED IMXRT_XBAR3(XBAR_INPUT, 148) /* XBAR3_IN148 <- SINC3 Channel 0 break due to clock absence detected */ +#define IMXRT_XBAR3_IN_SINC3_CHANNEL_1_BREAK_DUE_TO_CLOCK_ABSENCE_DETECTED IMXRT_XBAR3(XBAR_INPUT, 149) /* XBAR3_IN149 <- SINC3 Channel 1 break due to clock absence detected */ +#define IMXRT_XBAR3_IN_SINC3_CHANNEL_2_BREAK_DUE_TO_CLOCK_ABSENCE_DETECTED IMXRT_XBAR3(XBAR_INPUT, 150) /* XBAR3_IN150 <- SINC3 Channel 2 break due to clock absence detected */ +#define IMXRT_XBAR3_IN_SINC3_CHANNEL_3_BREAK_DUE_TO_CLOCK_ABSENCE_DETECTED IMXRT_XBAR3(XBAR_INPUT, 151) /* XBAR3_IN151 <- SINC3 Channel 3 break due to clock absence detected */ +#define IMXRT_XBAR3_IN_RESERVED IMXRT_XBAR3(XBAR_INPUT, 152) /* XBAR3_IN152 <- - Reserved */ +#define IMXRT_XBAR3_IN_RESERVED_2 IMXRT_XBAR3(XBAR_INPUT, 153) /* XBAR3_IN153 <- - Reserved */ +#define IMXRT_XBAR3_IN_RESERVED_3 IMXRT_XBAR3(XBAR_INPUT, 154) /* XBAR3_IN154 <- - Reserved */ +#define IMXRT_XBAR3_IN_RESERVED_4 IMXRT_XBAR3(XBAR_INPUT, 155) /* XBAR3_IN155 <- - Reserved */ +#define IMXRT_XBAR3_IN_EQDC2_POS_MATCH0 IMXRT_XBAR3(XBAR_INPUT, 156) /* XBAR3_IN156 <- eQDC2 POS_MATCH0 */ +#define IMXRT_XBAR3_IN_EQDC2_POS_MATCH1 IMXRT_XBAR3(XBAR_INPUT, 157) /* XBAR3_IN157 <- eQDC2 POS_MATCH1 */ +#define IMXRT_XBAR3_IN_EQDC2_POS_MATCH2 IMXRT_XBAR3(XBAR_INPUT, 158) /* XBAR3_IN158 <- eQDC2 POS_MATCH2 */ +#define IMXRT_XBAR3_IN_EQDC2_POS_MATCH3 IMXRT_XBAR3(XBAR_INPUT, 159) /* XBAR3_IN159 <- eQDC2 POS_MATCH3 */ +#define IMXRT_XBAR3_IN_EQDC2_COMP_FLG0 IMXRT_XBAR3(XBAR_INPUT, 160) /* XBAR3_IN160 <- eQDC2 COMP_FLG0 */ +#define IMXRT_XBAR3_IN_EQDC2_COMP_FLG1 IMXRT_XBAR3(XBAR_INPUT, 161) /* XBAR3_IN161 <- eQDC2 COMP_FLG1 */ +#define IMXRT_XBAR3_IN_EQDC2_COMP_FLG2 IMXRT_XBAR3(XBAR_INPUT, 162) /* XBAR3_IN162 <- eQDC2 COMP_FLG2 */ +#define IMXRT_XBAR3_IN_EQDC2_COMP_FLG3 IMXRT_XBAR3(XBAR_INPUT, 163) /* XBAR3_IN163 <- eQDC2 COMP_FLG3 */ +#define IMXRT_XBAR3_IN_EQDC2_CNT_DN IMXRT_XBAR3(XBAR_INPUT, 164) /* XBAR3_IN164 <- eQDC2 CNT_DN */ +#define IMXRT_XBAR3_IN_EQDC2_CNT_UP IMXRT_XBAR3(XBAR_INPUT, 165) /* XBAR3_IN165 <- eQDC2 CNT_UP */ +#define IMXRT_XBAR3_IN_EQDC2_DIR IMXRT_XBAR3(XBAR_INPUT, 166) /* XBAR3_IN166 <- eQDC2 DIR */ +#define IMXRT_XBAR3_IN_EQDC4_POS_MATCH0 IMXRT_XBAR3(XBAR_INPUT, 167) /* XBAR3_IN167 <- eQDC4 POS_MATCH0 */ +#define IMXRT_XBAR3_IN_EQDC4_POS_MATCH1 IMXRT_XBAR3(XBAR_INPUT, 168) /* XBAR3_IN168 <- eQDC4 POS_MATCH1 */ +#define IMXRT_XBAR3_IN_EQDC4_POS_MATCH2 IMXRT_XBAR3(XBAR_INPUT, 169) /* XBAR3_IN169 <- eQDC4 POS_MATCH2 */ +#define IMXRT_XBAR3_IN_EQDC4_POS_MATCH3 IMXRT_XBAR3(XBAR_INPUT, 170) /* XBAR3_IN170 <- eQDC4 POS_MATCH3 */ +#define IMXRT_XBAR3_IN_EQDC4_COMP_FLG0 IMXRT_XBAR3(XBAR_INPUT, 171) /* XBAR3_IN171 <- eQDC4 COMP_FLG0 */ +#define IMXRT_XBAR3_IN_EQDC4_COMP_FLG1 IMXRT_XBAR3(XBAR_INPUT, 172) /* XBAR3_IN172 <- eQDC4 COMP_FLG1 */ +#define IMXRT_XBAR3_IN_EQDC4_COMP_FLG2 IMXRT_XBAR3(XBAR_INPUT, 173) /* XBAR3_IN173 <- eQDC4 COMP_FLG2 */ +#define IMXRT_XBAR3_IN_EQDC4_COMP_FLG3 IMXRT_XBAR3(XBAR_INPUT, 174) /* XBAR3_IN174 <- eQDC4 COMP_FLG3 */ +#define IMXRT_XBAR3_IN_EQDC4_CNT_DN IMXRT_XBAR3(XBAR_INPUT, 175) /* XBAR3_IN175 <- eQDC4 CNT_DN */ +#define IMXRT_XBAR3_IN_EQDC4_CNT_UP IMXRT_XBAR3(XBAR_INPUT, 176) /* XBAR3_IN176 <- eQDC4 CNT_UP */ +#define IMXRT_XBAR3_IN_EQDC4_DIR IMXRT_XBAR3(XBAR_INPUT, 177) /* XBAR3_IN177 <- eQDC4 DIR */ + +/**************************************************************************** + * XBAR Output Assignments (IMXRT1180RM Table 15) + ****************************************************************************/ + +#define IMXRT_XBAR1_OUT_EDMA4_DMA_MUX_REQ154 IMXRT_XBAR1(XBAR_OUTPUT, 0) /* XBAR1_OUT0 -> eDMA4 DMA_MUX_REQ154 */ +#define IMXRT_XBAR1_OUT_EDMA4_DMA_MUX_REQ155 IMXRT_XBAR1(XBAR_OUTPUT, 1) /* XBAR1_OUT1 -> eDMA4 DMA_MUX_REQ155 */ +#define IMXRT_XBAR1_OUT_EDMA4_DMA_MUX_REQ156 IMXRT_XBAR1(XBAR_OUTPUT, 2) /* XBAR1_OUT2 -> eDMA4 DMA_MUX_REQ156 */ +#define IMXRT_XBAR1_OUT_EDMA4_DMA_MUX_REQ157 IMXRT_XBAR1(XBAR_OUTPUT, 3) /* XBAR1_OUT3 -> eDMA4 DMA_MUX_REQ157 */ +#define IMXRT_XBAR1_OUT_IOMUX_XBAR_INOUT04 IMXRT_XBAR1(XBAR_OUTPUT, 4) /* XBAR1_OUT4 -> - SW_MUX_CTL_PAD_GPIO_EMC_B1_ 00[MUX_MODE] = 0x1 */ +#define IMXRT_XBAR1_OUT_IOMUX_XBAR_INOUT05 IMXRT_XBAR1(XBAR_OUTPUT, 5) /* XBAR1_OUT5 -> - SW_MUX_CTL_PAD_GPIO_EMC_B1_ 01[MUX_MODE] = 0x1 */ +#define IMXRT_XBAR1_OUT_IOMUX_XBAR_INOUT06 IMXRT_XBAR1(XBAR_OUTPUT, 6) /* XBAR1_OUT6 -> - SW_MUX_CTL_PAD_GPIO_EMC_B1_ 02[MUX_MODE] = 0x1 */ +#define IMXRT_XBAR1_OUT_IOMUX_XBAR_INOUT07 IMXRT_XBAR1(XBAR_OUTPUT, 7) /* XBAR1_OUT7 -> - SW_MUX_CTL_PAD_GPIO_EMC_B1_ 03[MUX_MODE] = 0x1 */ +#define IMXRT_XBAR1_OUT_IOMUX_XBAR_INOUT08 IMXRT_XBAR1(XBAR_OUTPUT, 8) /* XBAR1_OUT8 -> - SW_MUX_CTL_PAD_GPIO_EMC_B1_ 04[MUX_MODE] = 0x1 */ +#define IMXRT_XBAR1_OUT_IOMUX_XBAR_INOUT09 IMXRT_XBAR1(XBAR_OUTPUT, 9) /* XBAR1_OUT9 -> - SW_MUX_CTL_PAD_GPIO_EMC_B1_ 05[MUX_MODE] = 0x1 */ +#define IMXRT_XBAR1_OUT_IOMUX_XBAR_INOUT10 IMXRT_XBAR1(XBAR_OUTPUT, 10) /* XBAR1_OUT10 -> - SW_MUX_CTL_PAD_GPIO_EMC_B1_ 26[MUX_MODE] = 0x2 */ +#define IMXRT_XBAR1_OUT_IOMUX_XBAR_INOUT11 IMXRT_XBAR1(XBAR_OUTPUT, 11) /* XBAR1_OUT11 -> - SW_MUX_CTL_PAD_GPIO_EMC_B1_ 27[MUX_MODE] = 0x2 */ +#define IMXRT_XBAR1_OUT_IOMUX_XBAR_INOUT12 IMXRT_XBAR1(XBAR_OUTPUT, 12) /* XBAR1_OUT12 -> - SW_MUX_CTL_PAD_GPIO_EMC_B1_ 28[MUX_MODE] = 0x2 */ +#define IMXRT_XBAR1_OUT_IOMUX_XBAR_INOUT13 IMXRT_XBAR1(XBAR_OUTPUT, 13) /* XBAR1_OUT13 -> - SW_MUX_CTL_PAD_GPIO_EMC_B1_ 29[MUX_MODE] = 0x2 */ +#define IMXRT_XBAR1_OUT_IOMUX_XBAR_INOUT14 IMXRT_XBAR1(XBAR_OUTPUT, 14) /* XBAR1_OUT14 -> - SW_MUX_CTL_PAD_GPIO_EMC_B1_ 30[MUX_MODE] = 0x2 */ +#define IMXRT_XBAR1_OUT_IOMUX_XBAR_INOUT15 IMXRT_XBAR1(XBAR_OUTPUT, 15) /* XBAR1_OUT15 -> - SW_MUX_CTL_PAD_GPIO_EMC_B1_ 39[MUX_MODE] = 0x2 */ +#define IMXRT_XBAR1_OUT_IOMUX_XBAR_INOUT16 IMXRT_XBAR1(XBAR_OUTPUT, 16) /* XBAR1_OUT16 -> - SW_MUX_CTL_PAD_GPIO_EMC_B2_ 18[MUX_MODE] = 0x6 */ +#define IMXRT_XBAR1_OUT_IOMUX_XBAR_INOUT17 IMXRT_XBAR1(XBAR_OUTPUT, 17) /* XBAR1_OUT17 -> - SW_MUX_CTL_PAD_GPIO_AD_33[MU See IOMUX Controller X_MODE] = */ +#define IMXRT_XBAR1_OUT_IOMUX_XBAR_INOUT18 IMXRT_XBAR1(XBAR_OUTPUT, 18) /* XBAR1_OUT18 -> - SW_MUX_CTL_PAD_GPIO_AD_12[MU See IOMUX Controller X_MODE] = */ +#define IMXRT_XBAR1_OUT_IOMUX_XBAR_INOUT19 IMXRT_XBAR1(XBAR_OUTPUT, 19) /* XBAR1_OUT19 -> - SW_MUX_CTL_PAD_GPIO_AD_19[MU See IOMUX Controller X_MODE] = */ +#define IMXRT_XBAR1_OUT_IOMUX_XBAR_INOUT20 IMXRT_XBAR1(XBAR_OUTPUT, 20) /* XBAR1_OUT20 -> - SW_MUX_CTL_PAD_GPIO_EMC_B2_ 00[MUX_MODE] = 0x6 */ +#define IMXRT_XBAR1_OUT_IOMUX_XBAR_INOUT21 IMXRT_XBAR1(XBAR_OUTPUT, 21) /* XBAR1_OUT21 -> - SW_MUX_CTL_PAD_GPIO_EMC_B2_ 01[MUX_MODE] = 0x6 */ +#define IMXRT_XBAR1_OUT_IOMUX_XBAR_INOUT22 IMXRT_XBAR1(XBAR_OUTPUT, 22) /* XBAR1_OUT22 -> - SW_MUX_CTL_PAD_GPIO_EMC_B2_ 02[MUX_MODE] = 0x6 */ +#define IMXRT_XBAR1_OUT_IOMUX_XBAR_INOUT23 IMXRT_XBAR1(XBAR_OUTPUT, 23) /* XBAR1_OUT23 -> - SW_MUX_CTL_PAD_GPIO_EMC_B2_ 03[MUX_MODE] = 0x6 */ +#define IMXRT_XBAR1_OUT_IOMUX_XBAR_INOUT24 IMXRT_XBAR1(XBAR_OUTPUT, 24) /* XBAR1_OUT24 -> - SW_MUX_CTL_PAD_GPIO_EMC_B2_ 04[MUX_MODE] = 0x6 */ +#define IMXRT_XBAR1_OUT_IOMUX_XBAR_INOUT25 IMXRT_XBAR1(XBAR_OUTPUT, 25) /* XBAR1_OUT25 -> - SW_MUX_CTL_PAD_GPIO_EMC_B2_ 05[MUX_MODE] = 0x6 */ +#define IMXRT_XBAR1_OUT_IOMUX_XBAR_INOUT26 IMXRT_XBAR1(XBAR_OUTPUT, 26) /* XBAR1_OUT26 -> - SW_MUX_CTL_PAD_GPIO_EMC_B2_ 06[MUX_MODE] = 0x6 */ +#define IMXRT_XBAR1_OUT_IOMUX_XBAR_INOUT27 IMXRT_XBAR1(XBAR_OUTPUT, 27) /* XBAR1_OUT27 -> - SW_MUX_CTL_PAD_GPIO_EMC_B2_ 07[MUX_MODE] = 0x6 */ +#define IMXRT_XBAR1_OUT_IOMUX_XBAR_INOUT28 IMXRT_XBAR1(XBAR_OUTPUT, 28) /* XBAR1_OUT28 -> - SW_MUX_CTL_PAD_GPIO_EMC_B2_ 08[MUX_MODE] = 0x6 */ +#define IMXRT_XBAR1_OUT_IOMUX_XBAR_INOUT29 IMXRT_XBAR1(XBAR_OUTPUT, 29) /* XBAR1_OUT29 -> - SW_MUX_CTL_PAD_GPIO_EMC_B2_ 09[MUX_MODE] = 0x6 */ +#define IMXRT_XBAR1_OUT_IOMUX_XBAR_INOUT30 IMXRT_XBAR1(XBAR_OUTPUT, 30) /* XBAR1_OUT30 -> - SW_MUX_CTL_PAD_GPIO_EMC_B2_ 10[MUX_MODE] = 0x6 */ +#define IMXRT_XBAR1_OUT_IOMUX_XBAR_INOUT31 IMXRT_XBAR1(XBAR_OUTPUT, 31) /* XBAR1_OUT31 -> - SW_MUX_CTL_PAD_GPIO_EMC_B2_ 11[MUX_MODE] = 0x6 */ +#define IMXRT_XBAR1_OUT_IOMUX_XBAR_INOUT32 IMXRT_XBAR1(XBAR_OUTPUT, 32) /* XBAR1_OUT32 -> - SW_MUX_CTL_PAD_GPIO_EMC_B2_ 12[MUX_MODE] = 0x6 */ +#define IMXRT_XBAR1_OUT_IOMUX_XBAR_INOUT33 IMXRT_XBAR1(XBAR_OUTPUT, 33) /* XBAR1_OUT33 -> - SW_MUX_CTL_PAD_GPIO_EMC_B2_ 13[MUX_MODE] = 0x6 */ +#define IMXRT_XBAR1_OUT_IOMUX_XBAR_INOUT34 IMXRT_XBAR1(XBAR_OUTPUT, 34) /* XBAR1_OUT34 -> - SW_MUX_CTL_PAD_GPIO_EMC_B2_ 14[MUX_MODE] = 0x6 */ +#define IMXRT_XBAR1_OUT_IOMUX_XBAR_INOUT35 IMXRT_XBAR1(XBAR_OUTPUT, 35) /* XBAR1_OUT35 -> - SW_MUX_CTL_PAD_GPIO_EMC_B2_ 15[MUX_MODE] = 0x6 */ +#define IMXRT_XBAR1_OUT_IOMUX_XBAR_INOUT36 IMXRT_XBAR1(XBAR_OUTPUT, 36) /* XBAR1_OUT36 -> - SW_MUX_CTL_PAD_GPIO_EMC_B2_ 19[MUX_MODE] = 0x6 */ +#define IMXRT_XBAR1_OUT_IOMUX_XBAR_INOUT37 IMXRT_XBAR1(XBAR_OUTPUT, 37) /* XBAR1_OUT37 -> - SW_MUX_CTL_PAD_GPIO_EMC_B2_ 20[MUX_MODE] = 0x6 */ +#define IMXRT_XBAR1_OUT_CMP1_SAMPLE IMXRT_XBAR1(XBAR_OUTPUT, 38) /* XBAR1_OUT38 -> CMP1 SAMPLE */ +#define IMXRT_XBAR1_OUT_CMP2_SAMPLE IMXRT_XBAR1(XBAR_OUTPUT, 39) /* XBAR1_OUT39 -> CMP2 SAMPLE */ +#define IMXRT_XBAR1_OUT_CMP3_SAMPLE IMXRT_XBAR1(XBAR_OUTPUT, 40) /* XBAR1_OUT40 -> CMP3 SAMPLE */ +#define IMXRT_XBAR1_OUT_CMP4_SAMPLE IMXRT_XBAR1(XBAR_OUTPUT, 41) /* XBAR1_OUT41 -> CMP4 SAMPLE */ +#define IMXRT_XBAR1_OUT_FLEXPWM1_EXTA0 IMXRT_XBAR1(XBAR_OUTPUT, 42) /* XBAR1_OUT42 -> FLEXPWM1 EXTA0 */ +#define IMXRT_XBAR1_OUT_FLEXPWM1_EXTA1 IMXRT_XBAR1(XBAR_OUTPUT, 43) /* XBAR1_OUT43 -> FLEXPWM1 EXTA1 */ +#define IMXRT_XBAR1_OUT_FLEXPWM1_EXTA2 IMXRT_XBAR1(XBAR_OUTPUT, 44) /* XBAR1_OUT44 -> FLEXPWM1 EXTA2 */ +#define IMXRT_XBAR1_OUT_FLEXPWM1_EXTA3 IMXRT_XBAR1(XBAR_OUTPUT, 45) /* XBAR1_OUT45 -> FLEXPWM1 EXTA3 */ +#define IMXRT_XBAR1_OUT_FLEXPWM1_EXT_SYNC0 IMXRT_XBAR1(XBAR_OUTPUT, 46) /* XBAR1_OUT46 -> FLEXPWM1 EXT_SYNC0 */ +#define IMXRT_XBAR1_OUT_FLEXPWM1_EXT_SYNC1 IMXRT_XBAR1(XBAR_OUTPUT, 47) /* XBAR1_OUT47 -> FLEXPWM1 EXT_SYNC1 */ +#define IMXRT_XBAR1_OUT_FLEXPWM1_EXT_SYNC2 IMXRT_XBAR1(XBAR_OUTPUT, 48) /* XBAR1_OUT48 -> FLEXPWM1 EXT_SYNC2 */ +#define IMXRT_XBAR1_OUT_FLEXPWM1_EXT_SYNC3 IMXRT_XBAR1(XBAR_OUTPUT, 49) /* XBAR1_OUT49 -> FLEXPWM1 EXT_SYNC3 */ +#define IMXRT_XBAR1_OUT_FLEXPWM1_EXT_CLK IMXRT_XBAR1(XBAR_OUTPUT, 50) /* XBAR1_OUT50 -> FLEXPWM1 EXT_CLK */ +#define IMXRT_XBAR1_OUT_FLEXPWM1_FAULT0 IMXRT_XBAR1(XBAR_OUTPUT, 51) /* XBAR1_OUT51 -> FLEXPWM1 FAULT0 */ +#define IMXRT_XBAR1_OUT_FLEXPWM1_FAULT1 IMXRT_XBAR1(XBAR_OUTPUT, 52) /* XBAR1_OUT52 -> FLEXPWM1 FAULT1 */ +#define IMXRT_XBAR1_OUT_FLEXPWM1_FAULT2 IMXRT_XBAR1(XBAR_OUTPUT, 53) /* XBAR1_OUT53 -> FLEXPWM1 FAULT2 */ +#define IMXRT_XBAR1_OUT_FLEXPWM1_FAULT3 IMXRT_XBAR1(XBAR_OUTPUT, 54) /* XBAR1_OUT54 -> FLEXPWM1 FAULT3 */ +#define IMXRT_XBAR1_OUT_FLEXPWM1_EXT_FORCE IMXRT_XBAR1(XBAR_OUTPUT, 55) /* XBAR1_OUT55 -> FLEXPWM1 EXT_FORCE */ +#define IMXRT_XBAR1_OUT_FLEXPWM2_EXTA0 IMXRT_XBAR1(XBAR_OUTPUT, 56) /* XBAR1_OUT56 -> FLEXPWM2 EXTA0 */ +#define IMXRT_XBAR1_OUT_FLEXPWM2_EXTA1 IMXRT_XBAR1(XBAR_OUTPUT, 57) /* XBAR1_OUT57 -> FLEXPWM2 EXTA1 */ +#define IMXRT_XBAR1_OUT_FLEXPWM2_EXTA2 IMXRT_XBAR1(XBAR_OUTPUT, 58) /* XBAR1_OUT58 -> FLEXPWM2 EXTA2 */ +#define IMXRT_XBAR1_OUT_FLEXPWM2_EXTA3 IMXRT_XBAR1(XBAR_OUTPUT, 59) /* XBAR1_OUT59 -> FLEXPWM2 EXTA3 */ +#define IMXRT_XBAR1_OUT_FLEXPWM2_EXT_SYNC0 IMXRT_XBAR1(XBAR_OUTPUT, 60) /* XBAR1_OUT60 -> FLEXPWM2 EXT_SYNC0 */ +#define IMXRT_XBAR1_OUT_FLEXPWM2_EXT_SYNC1 IMXRT_XBAR1(XBAR_OUTPUT, 61) /* XBAR1_OUT61 -> FLEXPWM2 EXT_SYNC1 */ +#define IMXRT_XBAR1_OUT_FLEXPWM2_EXT_SYNC2 IMXRT_XBAR1(XBAR_OUTPUT, 62) /* XBAR1_OUT62 -> FLEXPWM2 EXT_SYNC2 */ +#define IMXRT_XBAR1_OUT_FLEXPWM2_EXT_SYNC3 IMXRT_XBAR1(XBAR_OUTPUT, 63) /* XBAR1_OUT63 -> FLEXPWM2 EXT_SYNC3 */ +#define IMXRT_XBAR1_OUT_FLEXPWM2_EXT_CLK IMXRT_XBAR1(XBAR_OUTPUT, 64) /* XBAR1_OUT64 -> FLEXPWM2 EXT_CLK */ +#define IMXRT_XBAR1_OUT_FLEXPWM2_FAULT0 IMXRT_XBAR1(XBAR_OUTPUT, 65) /* XBAR1_OUT65 -> FLEXPWM2 FAULT0 */ +#define IMXRT_XBAR1_OUT_FLEXPWM2_FAULT1 IMXRT_XBAR1(XBAR_OUTPUT, 66) /* XBAR1_OUT66 -> FLEXPWM2 FAULT1 */ +#define IMXRT_XBAR1_OUT_FLEXPWM2_EXT_FORCE IMXRT_XBAR1(XBAR_OUTPUT, 67) /* XBAR1_OUT67 -> FLEXPWM2 EXT_FORCE */ +#define IMXRT_XBAR1_OUT_FLEXPWM3_EXTA0 IMXRT_XBAR1(XBAR_OUTPUT, 68) /* XBAR1_OUT68 -> FLEXPWM3 EXTA0 */ +#define IMXRT_XBAR1_OUT_FLEXPWM3_EXTA1 IMXRT_XBAR1(XBAR_OUTPUT, 69) /* XBAR1_OUT69 -> FLEXPWM3 EXTA1 */ +#define IMXRT_XBAR1_OUT_FLEXPWM3_EXTA2 IMXRT_XBAR1(XBAR_OUTPUT, 70) /* XBAR1_OUT70 -> FLEXPWM3 EXTA2 */ +#define IMXRT_XBAR1_OUT_FLEXPWM3_EXTA3 IMXRT_XBAR1(XBAR_OUTPUT, 71) /* XBAR1_OUT71 -> FLEXPWM3 EXTA3 */ +#define IMXRT_XBAR1_OUT_FLEXPWM3_EXT_CLK IMXRT_XBAR1(XBAR_OUTPUT, 72) /* XBAR1_OUT72 -> FLEXPWM3 EXT_CLK */ +#define IMXRT_XBAR1_OUT_FLEXPWM3_EXT_SYNC0 IMXRT_XBAR1(XBAR_OUTPUT, 73) /* XBAR1_OUT73 -> FLEXPWM3 EXT_SYNC0 */ +#define IMXRT_XBAR1_OUT_FLEXPWM3_EXT_SYNC1 IMXRT_XBAR1(XBAR_OUTPUT, 74) /* XBAR1_OUT74 -> FLEXPWM3 EXT_SYNC1 */ +#define IMXRT_XBAR1_OUT_FLEXPWM3_EXT_SYNC2 IMXRT_XBAR1(XBAR_OUTPUT, 75) /* XBAR1_OUT75 -> FLEXPWM3 EXT_SYNC2 */ +#define IMXRT_XBAR1_OUT_FLEXPWM3_EXT_SYNC3 IMXRT_XBAR1(XBAR_OUTPUT, 76) /* XBAR1_OUT76 -> FLEXPWM3 EXT_SYNC3 */ +#define IMXRT_XBAR1_OUT_FLEXPWM3_FAULT0 IMXRT_XBAR1(XBAR_OUTPUT, 77) /* XBAR1_OUT77 -> FLEXPWM3 FAULT0 */ +#define IMXRT_XBAR1_OUT_FLEXPWM3_FAULT1 IMXRT_XBAR1(XBAR_OUTPUT, 78) /* XBAR1_OUT78 -> FLEXPWM3 FAULT1 */ +#define IMXRT_XBAR1_OUT_FLEXPWM3_EXT_FORCE IMXRT_XBAR1(XBAR_OUTPUT, 79) /* XBAR1_OUT79 -> FLEXPWM3 EXT_FORCE */ +#define IMXRT_XBAR1_OUT_FLEXPWM4_EXT_SYNC0 IMXRT_XBAR1(XBAR_OUTPUT, 80) /* XBAR1_OUT80 -> FLEXPWM4 EXT_SYNC0 */ +#define IMXRT_XBAR1_OUT_FLEXPWM4_EXT_SYNC1 IMXRT_XBAR1(XBAR_OUTPUT, 81) /* XBAR1_OUT81 -> FLEXPWM4 EXT_SYNC1 */ +#define IMXRT_XBAR1_OUT_FLEXPWM4_EXT_SYNC2 IMXRT_XBAR1(XBAR_OUTPUT, 82) /* XBAR1_OUT82 -> FLEXPWM4 EXT_SYNC2 */ +#define IMXRT_XBAR1_OUT_FLEXPWM4_EXT_SYNC3 IMXRT_XBAR1(XBAR_OUTPUT, 83) /* XBAR1_OUT83 -> FLEXPWM4 EXT_SYNC3 */ +#define IMXRT_XBAR1_OUT_FLEXPWM4_FAULT0 IMXRT_XBAR1(XBAR_OUTPUT, 84) /* XBAR1_OUT84 -> FLEXPWM4 FAULT0 */ +#define IMXRT_XBAR1_OUT_FLEXPWM4_FAULT1 IMXRT_XBAR1(XBAR_OUTPUT, 85) /* XBAR1_OUT85 -> FLEXPWM4 FAULT1 */ +#define IMXRT_XBAR1_OUT_FLEXPWM4_EXT_FORCE IMXRT_XBAR1(XBAR_OUTPUT, 86) /* XBAR1_OUT86 -> FLEXPWM4 EXT_FORCE */ +#define IMXRT_XBAR1_OUT_EQDC1_PHASE_A_INPUT IMXRT_XBAR1(XBAR_OUTPUT, 87) /* XBAR1_OUT87 -> eQDC1 PHASE_A_INPUT */ +#define IMXRT_XBAR1_OUT_EQDC1_PHASE_B_INPUT IMXRT_XBAR1(XBAR_OUTPUT, 88) /* XBAR1_OUT88 -> eQDC1 PHASE_B_INPUT */ +#define IMXRT_XBAR1_OUT_EQDC1_INDEX IMXRT_XBAR1(XBAR_OUTPUT, 89) /* XBAR1_OUT89 -> eQDC1 INDEX */ +#define IMXRT_XBAR1_OUT_EQDC1_HOME IMXRT_XBAR1(XBAR_OUTPUT, 90) /* XBAR1_OUT90 -> eQDC1 HOME */ +#define IMXRT_XBAR1_OUT_EQDC1_TRIGGER IMXRT_XBAR1(XBAR_OUTPUT, 91) /* XBAR1_OUT91 -> eQDC1 TRIGGER */ +#define IMXRT_XBAR1_OUT_EQDC2_PHASE_A_INPUT IMXRT_XBAR1(XBAR_OUTPUT, 92) /* XBAR1_OUT92 -> eQDC2 PHASE_A_INPUT */ +#define IMXRT_XBAR1_OUT_EQDC2_PHASE_B_INPUT IMXRT_XBAR1(XBAR_OUTPUT, 93) /* XBAR1_OUT93 -> eQDC2 PHASE_B_INPUT */ +#define IMXRT_XBAR1_OUT_EQDC2_INDEX IMXRT_XBAR1(XBAR_OUTPUT, 94) /* XBAR1_OUT94 -> eQDC2 INDEX */ +#define IMXRT_XBAR1_OUT_EQDC2_HOME IMXRT_XBAR1(XBAR_OUTPUT, 95) /* XBAR1_OUT95 -> eQDC2 HOME */ +#define IMXRT_XBAR1_OUT_EQDC2_TRIGGER IMXRT_XBAR1(XBAR_OUTPUT, 96) /* XBAR1_OUT96 -> eQDC2 TRIGGER */ +#define IMXRT_XBAR1_OUT_EQDC3_PHASE_A_INPUT IMXRT_XBAR1(XBAR_OUTPUT, 97) /* XBAR1_OUT97 -> eQDC3 PHASE_A_INPUT */ +#define IMXRT_XBAR1_OUT_EQDC3_PHASE_B_INPUT IMXRT_XBAR1(XBAR_OUTPUT, 98) /* XBAR1_OUT98 -> eQDC3 PHASE_B_INPUT */ +#define IMXRT_XBAR1_OUT_EQDC3_INDEX IMXRT_XBAR1(XBAR_OUTPUT, 99) /* XBAR1_OUT99 -> eQDC3 INDEX */ +#define IMXRT_XBAR1_OUT_EQDC3_HOME IMXRT_XBAR1(XBAR_OUTPUT, 100) /* XBAR1_OUT100 -> eQDC3 HOME */ +#define IMXRT_XBAR1_OUT_EQDC3_TRIGGER IMXRT_XBAR1(XBAR_OUTPUT, 101) /* XBAR1_OUT101 -> eQDC3 TRIGGER */ +#define IMXRT_XBAR1_OUT_EQDC4_PHASE_A_INPUT IMXRT_XBAR1(XBAR_OUTPUT, 102) /* XBAR1_OUT102 -> eQDC4 PHASE_A_INPUT */ +#define IMXRT_XBAR1_OUT_EQDC4_PHASE_B_INPUT IMXRT_XBAR1(XBAR_OUTPUT, 103) /* XBAR1_OUT103 -> eQDC4 PHASE_B_INPUT */ +#define IMXRT_XBAR1_OUT_EQDC4_INDEX IMXRT_XBAR1(XBAR_OUTPUT, 104) /* XBAR1_OUT104 -> eQDC4 INDEX */ +#define IMXRT_XBAR1_OUT_EQDC4_HOME IMXRT_XBAR1(XBAR_OUTPUT, 105) /* XBAR1_OUT105 -> eQDC4 HOME */ +#define IMXRT_XBAR1_OUT_EQDC4_TRIGGER IMXRT_XBAR1(XBAR_OUTPUT, 106) /* XBAR1_OUT106 -> eQDC4 TRIGGER */ +#define IMXRT_XBAR1_OUT_TMR1_TMR0_INPUT_QTIMER_CTRL1 IMXRT_XBAR1(XBAR_OUTPUT, 107) /* XBAR1_OUT107 -> TMR1 TMR0_INPUT QTIMER_CTRL1[QTIMER1_TM R0_INPUT_SEL] = 1 */ +#define IMXRT_XBAR1_OUT_TMR1_TMR1_INPUT_QTIMER_CTRL1 IMXRT_XBAR1(XBAR_OUTPUT, 108) /* XBAR1_OUT108 -> TMR1 TMR1_INPUT QTIMER_CTRL1[QTIMER1_TM R1_INPUT_SEL] = 1 */ +#define IMXRT_XBAR1_OUT_TMR1_TMR2_INPUT_QTIMER_CTRL1 IMXRT_XBAR1(XBAR_OUTPUT, 109) /* XBAR1_OUT109 -> TMR1 TMR2_INPUT QTIMER_CTRL1[QTIMER1_TM R2_INPUT_SEL] = 1 */ +#define IMXRT_XBAR1_OUT_TMR1_TMR3_INPUT_QTIMER_CTRL1 IMXRT_XBAR1(XBAR_OUTPUT, 110) /* XBAR1_OUT110 -> TMR1 TMR3_INPUT QTIMER_CTRL1[QTIMER1_TM R3_INPUT_SEL] = 1 */ +#define IMXRT_XBAR1_OUT_TMR2_TMR0_INPUT_QTIMER_CTRL1 IMXRT_XBAR1(XBAR_OUTPUT, 111) /* XBAR1_OUT111 -> TMR2 TMR0_INPUT QTIMER_CTRL1[QTIMER2_TM R0_INPUT_SEL] = 1 */ +#define IMXRT_XBAR1_OUT_TMR2_TMR1_INPUT_QTIMER_CTRL1 IMXRT_XBAR1(XBAR_OUTPUT, 112) /* XBAR1_OUT112 -> TMR2 TMR1_INPUT QTIMER_CTRL1[QTIMER2_TM R1_INPUT_SEL] = 1 */ +#define IMXRT_XBAR1_OUT_TMR2_TMR2_INPUT_QTIMER_CTRL1 IMXRT_XBAR1(XBAR_OUTPUT, 113) /* XBAR1_OUT113 -> TMR2 TMR2_INPUT QTIMER_CTRL1[QTIMER2_TM R2_INPUT_SEL] = 1 */ +#define IMXRT_XBAR1_OUT_TMR2_TMR3_INPUT_QTIMER_CTRL1 IMXRT_XBAR1(XBAR_OUTPUT, 114) /* XBAR1_OUT114 -> TMR2 TMR3_INPUT QTIMER_CTRL1[QTIMER2_TM R3_INPUT_SEL] = 1 */ +#define IMXRT_XBAR1_OUT_TMR3_TMR0_INPUT_QTIMER_CTRL1 IMXRT_XBAR1(XBAR_OUTPUT, 115) /* XBAR1_OUT115 -> TMR3 TMR0_INPUT QTIMER_CTRL1[QTIMER3_TM R0_INPUT_SEL] = 1 */ +#define IMXRT_XBAR1_OUT_TMR3_TMR1_INPUT_QTIMER_CTRL1 IMXRT_XBAR1(XBAR_OUTPUT, 116) /* XBAR1_OUT116 -> TMR3 TMR1_INPUT QTIMER_CTRL1[QTIMER3_TM R1_INPUT_SEL] = 1 */ +#define IMXRT_XBAR1_OUT_TMR3_TMR2_INPUT_QTIMER_CTRL1 IMXRT_XBAR1(XBAR_OUTPUT, 117) /* XBAR1_OUT117 -> TMR3 TMR2_INPUT QTIMER_CTRL1[QTIMER3_TM R2_INPUT_SEL] = 1 */ +#define IMXRT_XBAR1_OUT_TMR3_TMR3_INPUT_QTIMER_CTRL1 IMXRT_XBAR1(XBAR_OUTPUT, 118) /* XBAR1_OUT118 -> TMR3 TMR3_INPUT QTIMER_CTRL1[QTIMER3_TM R3_INPUT_SEL] = 1 */ +#define IMXRT_XBAR1_OUT_TMR4_TMR0_INPUT_QTIMER_CTRL1 IMXRT_XBAR1(XBAR_OUTPUT, 119) /* XBAR1_OUT119 -> TMR4 TMR0_INPUT QTIMER_CTRL1[QTIMER4_TM R0_INPUT_SEL] = 1 */ +#define IMXRT_XBAR1_OUT_TMR4_TMR1_INPUT_QTIMER_CTRL1 IMXRT_XBAR1(XBAR_OUTPUT, 120) /* XBAR1_OUT120 -> TMR4 TMR1_INPUT QTIMER_CTRL1[QTIMER4_TM R1_INPUT_SEL] = 1 */ +#define IMXRT_XBAR1_OUT_TMR4_TMR2_INPUT_QTIMER_CTRL1 IMXRT_XBAR1(XBAR_OUTPUT, 121) /* XBAR1_OUT121 -> TMR4 TMR2_INPUT QTIMER_CTRL1[QTIMER4_TM R2_INPUT_SEL] = 1 */ +#define IMXRT_XBAR1_OUT_TMR4_TMR3_INPUT_QTIMER_CTRL1 IMXRT_XBAR1(XBAR_OUTPUT, 122) /* XBAR1_OUT122 -> TMR4 TMR3_INPUT QTIMER_CTRL1[QTIMER4_TM R3_INPUT_SEL] = 1 */ +#define IMXRT_XBAR1_OUT_TMR5_TMR0_INPUT_QTIMER_CTRL2 IMXRT_XBAR1(XBAR_OUTPUT, 123) /* XBAR1_OUT123 -> TMR5 TMR0_INPUT QTIMER_CTRL2[QTIMER5_TM R0_INPUT_SEL] = 1 */ +#define IMXRT_XBAR1_OUT_TMR5_TMR1_INPUT_QTIMER_CTRL2 IMXRT_XBAR1(XBAR_OUTPUT, 124) /* XBAR1_OUT124 -> TMR5 TMR1_INPUT QTIMER_CTRL2[QTIMER5_TM R1_INPUT_SEL] = 1 */ +#define IMXRT_XBAR1_OUT_TMR5_TMR2_INPUT_QTIMER_CTRL2 IMXRT_XBAR1(XBAR_OUTPUT, 125) /* XBAR1_OUT125 -> TMR5 TMR2_INPUT QTIMER_CTRL2[QTIMER5_TM R2_INPUT_SEL] = 1 */ +#define IMXRT_XBAR1_OUT_TMR5_TMR3_INPUT_QTIMER_CTRL2 IMXRT_XBAR1(XBAR_OUTPUT, 126) /* XBAR1_OUT126 -> TMR5 TMR3_INPUT QTIMER_CTRL2[QTIMER5_TM R3_INPUT_SEL] = 1 */ +#define IMXRT_XBAR1_OUT_TMR6_TMR0_INPUT_QTIMER_CTRL2 IMXRT_XBAR1(XBAR_OUTPUT, 127) /* XBAR1_OUT127 -> TMR6 TMR0_INPUT QTIMER_CTRL2[QTIMER6_TM R0_INPUT_SEL] = 1 */ +#define IMXRT_XBAR1_OUT_TMR6_TMR1_INPUT_QTIMER_CTRL2 IMXRT_XBAR1(XBAR_OUTPUT, 128) /* XBAR1_OUT128 -> TMR6 TMR1_INPUT QTIMER_CTRL2[QTIMER6_TM R1_INPUT_SEL] = 1 */ +#define IMXRT_XBAR1_OUT_TMR6_TMR2_INPUT_QTIMER_CTRL2 IMXRT_XBAR1(XBAR_OUTPUT, 129) /* XBAR1_OUT129 -> TMR6 TMR2_INPUT QTIMER_CTRL2[QTIMER6_TM R2_INPUT_SEL] = 1 */ +#define IMXRT_XBAR1_OUT_TMR6_TMR3_INPUT_QTIMER_CTRL2 IMXRT_XBAR1(XBAR_OUTPUT, 130) /* XBAR1_OUT130 -> TMR6 TMR3_INPUT QTIMER_CTRL2[QTIMER6_TM R3_INPUT_SEL] = 1 */ +#define IMXRT_XBAR1_OUT_TMR7_TMR0_INPUT_QTIMER_CTRL2 IMXRT_XBAR1(XBAR_OUTPUT, 131) /* XBAR1_OUT131 -> TMR7 TMR0_INPUT QTIMER_CTRL2[QTIMER7_TM R0_INPUT_SEL] = 1 */ +#define IMXRT_XBAR1_OUT_TMR7_TMR1_INPUT_QTIMER_CTRL2 IMXRT_XBAR1(XBAR_OUTPUT, 132) /* XBAR1_OUT132 -> TMR7 TMR1_INPUT QTIMER_CTRL2[QTIMER7_TM R1_INPUT_SEL] = 1 */ +#define IMXRT_XBAR1_OUT_TMR7_TMR2_INPUT_QTIMER_CTRL2 IMXRT_XBAR1(XBAR_OUTPUT, 133) /* XBAR1_OUT133 -> TMR7 TMR2_INPUT QTIMER_CTRL2[QTIMER7_TM R2_INPUT_SEL] = 1 */ +#define IMXRT_XBAR1_OUT_TMR7_TMR3_INPUT_QTIMER_CTRL2 IMXRT_XBAR1(XBAR_OUTPUT, 134) /* XBAR1_OUT134 -> TMR7 TMR3_INPUT QTIMER_CTRL2[QTIMER7_TM R3_INPUT_SEL] = 1 */ +#define IMXRT_XBAR1_OUT_TMR8_TMR0_INPUT_QTIMER_CTRL2 IMXRT_XBAR1(XBAR_OUTPUT, 135) /* XBAR1_OUT135 -> TMR8 TMR0_INPUT QTIMER_CTRL2[QTIMER8_TM R0_INPUT_SEL] = 1 */ +#define IMXRT_XBAR1_OUT_TMR8_TMR1_INPUT_QTIMER_CTRL2 IMXRT_XBAR1(XBAR_OUTPUT, 136) /* XBAR1_OUT136 -> TMR8 TMR1_INPUT QTIMER_CTRL2[QTIMER8_TM R1_INPUT_SEL] = 1 */ +#define IMXRT_XBAR1_OUT_TMR8_TMR2_INPUT_QTIMER_CTRL2 IMXRT_XBAR1(XBAR_OUTPUT, 137) /* XBAR1_OUT137 -> TMR8 TMR2_INPUT QTIMER_CTRL2[QTIMER8_TM R2_INPUT_SEL] = 1 */ +#define IMXRT_XBAR1_OUT_TMR8_TMR3_INPUT_QTIMER_CTRL2 IMXRT_XBAR1(XBAR_OUTPUT, 138) /* XBAR1_OUT138 -> TMR8 TMR3_INPUT QTIMER_CTRL2[QTIMER8_TM R3_INPUT_SEL] = 1 */ +#define IMXRT_XBAR1_OUT_EWM_EWM_IN IMXRT_XBAR1(XBAR_OUTPUT, 139) /* XBAR1_OUT139 -> EWM EWM_IN */ +#define IMXRT_XBAR1_OUT_ADC1_HW_TRG0 IMXRT_XBAR1(XBAR_OUTPUT, 140) /* XBAR1_OUT140 -> ADC1 HW_TRG0 */ +#define IMXRT_XBAR1_OUT_ADC1_HW_TRG1 IMXRT_XBAR1(XBAR_OUTPUT, 141) /* XBAR1_OUT141 -> ADC1 HW_TRG1 */ +#define IMXRT_XBAR1_OUT_ADC1_HW_TRG2 IMXRT_XBAR1(XBAR_OUTPUT, 142) /* XBAR1_OUT142 -> ADC1 HW_TRG2 */ +#define IMXRT_XBAR1_OUT_ADC1_HW_TRG3 IMXRT_XBAR1(XBAR_OUTPUT, 143) /* XBAR1_OUT143 -> ADC1 HW_TRG3 */ +#define IMXRT_XBAR1_OUT_ADC1_HW_TRG4 IMXRT_XBAR1(XBAR_OUTPUT, 144) /* XBAR1_OUT144 -> ADC1 HW_TRG4 */ +#define IMXRT_XBAR1_OUT_ADC1_HW_TRG5 IMXRT_XBAR1(XBAR_OUTPUT, 145) /* XBAR1_OUT145 -> ADC1 HW_TRG5 */ +#define IMXRT_XBAR1_OUT_ADC1_HW_TRG6 IMXRT_XBAR1(XBAR_OUTPUT, 146) /* XBAR1_OUT146 -> ADC1 HW_TRG6 */ +#define IMXRT_XBAR1_OUT_ADC1_HW_TRG7 IMXRT_XBAR1(XBAR_OUTPUT, 147) /* XBAR1_OUT147 -> ADC1 HW_TRG7 */ +#define IMXRT_XBAR1_OUT_SINC1_EXT_TRIGGER0 IMXRT_XBAR1(XBAR_OUTPUT, 148) /* XBAR1_OUT148 -> SINC1 EXT_TRIGGER0 */ +#define IMXRT_XBAR1_OUT_SINC1_EXT_TRIGGER1 IMXRT_XBAR1(XBAR_OUTPUT, 149) /* XBAR1_OUT149 -> SINC1 EXT_TRIGGER1 */ +#define IMXRT_XBAR1_OUT_SINC1_EXT_TRIGGER2 IMXRT_XBAR1(XBAR_OUTPUT, 150) /* XBAR1_OUT150 -> SINC1 EXT_TRIGGER2 */ +#define IMXRT_XBAR1_OUT_SINC1_EXT_TRIGGER3 IMXRT_XBAR1(XBAR_OUTPUT, 151) /* XBAR1_OUT151 -> SINC1 EXT_TRIGGER3 */ +#define IMXRT_XBAR1_OUT_FLEXIO1_FLEXIO_TRIGGER_IN0 IMXRT_XBAR1(XBAR_OUTPUT, 152) /* XBAR1_OUT152 -> FLEXIO1 FLEXIO_TRIGGER_IN0 */ +#define IMXRT_XBAR1_OUT_FLEXIO1_FLEXIO_TRIGGER_IN1 IMXRT_XBAR1(XBAR_OUTPUT, 153) /* XBAR1_OUT153 -> FLEXIO1 FLEXIO_TRIGGER_IN1 */ +#define IMXRT_XBAR1_OUT_FLEXIO2_FLEXIO_TRIGGER_IN0 IMXRT_XBAR1(XBAR_OUTPUT, 154) /* XBAR1_OUT154 -> FLEXIO2 FLEXIO_TRIGGER_IN0 */ +#define IMXRT_XBAR1_OUT_FLEXIO2_FLEXIO_TRIGGER_IN1 IMXRT_XBAR1(XBAR_OUTPUT, 155) /* XBAR1_OUT155 -> FLEXIO2 FLEXIO_TRIGGER_IN1 */ +#define IMXRT_XBAR1_OUT_LPI2C1_LPI2C_TRG_INPUT IMXRT_XBAR1(XBAR_OUTPUT, 156) /* XBAR1_OUT156 -> LPI2C1 LPI2C_TRG_INPUT */ +#define IMXRT_XBAR1_OUT_LPI2C2_LPI2C_TRG_INPUT IMXRT_XBAR1(XBAR_OUTPUT, 157) /* XBAR1_OUT157 -> LPI2C2 LPI2C_TRG_INPUT */ +#define IMXRT_XBAR1_OUT_LPI2C3_LPI2C_TRG_INPUT IMXRT_XBAR1(XBAR_OUTPUT, 158) /* XBAR1_OUT158 -> LPI2C3 LPI2C_TRG_INPUT */ +#define IMXRT_XBAR1_OUT_LPI2C4_LPI2C_TRG_INPUT IMXRT_XBAR1(XBAR_OUTPUT, 159) /* XBAR1_OUT159 -> LPI2C4 LPI2C_TRG_INPUT */ +#define IMXRT_XBAR1_OUT_LPI2C5_LPI2C_TRG_INPUT IMXRT_XBAR1(XBAR_OUTPUT, 160) /* XBAR1_OUT160 -> LPI2C5 LPI2C_TRG_INPUT */ +#define IMXRT_XBAR1_OUT_LPI2C6_LPI2C_TRG_INPUT IMXRT_XBAR1(XBAR_OUTPUT, 161) /* XBAR1_OUT161 -> LPI2C6 LPI2C_TRG_INPUT */ +#define IMXRT_XBAR1_OUT_LPSPI1_LPSPI_TRG_INPUT IMXRT_XBAR1(XBAR_OUTPUT, 162) /* XBAR1_OUT162 -> LPSPI1 LPSPI_TRG_INPUT */ +#define IMXRT_XBAR1_OUT_LPSPI2_LPSPI_TRG_INPUT IMXRT_XBAR1(XBAR_OUTPUT, 163) /* XBAR1_OUT163 -> LPSPI2 LPSPI_TRG_INPUT */ +#define IMXRT_XBAR1_OUT_LPSPI3_LPSPI_TRG_INPUT IMXRT_XBAR1(XBAR_OUTPUT, 164) /* XBAR1_OUT164 -> LPSPI3 LPSPI_TRG_INPUT */ +#define IMXRT_XBAR1_OUT_LPSPI4_LPSPI_TRG_INPUT IMXRT_XBAR1(XBAR_OUTPUT, 165) /* XBAR1_OUT165 -> LPSPI4 LPSPI_TRG_INPUT */ +#define IMXRT_XBAR1_OUT_LPSPI5_LPSPI_TRG_INPUT IMXRT_XBAR1(XBAR_OUTPUT, 166) /* XBAR1_OUT166 -> LPSPI5 LPSPI_TRG_INPUT */ +#define IMXRT_XBAR1_OUT_LPSPI6_LPSPI_TRG_INPUT IMXRT_XBAR1(XBAR_OUTPUT, 167) /* XBAR1_OUT167 -> LPSPI6 LPSPI_TRG_INPUT */ +#define IMXRT_XBAR1_OUT_LPUART1_LPUART_TRG_INPUT IMXRT_XBAR1(XBAR_OUTPUT, 168) /* XBAR1_OUT168 -> LPUART1 LPUART_TRG_INPUT */ +#define IMXRT_XBAR1_OUT_LPUART2_LPUART_TRG_INPUT IMXRT_XBAR1(XBAR_OUTPUT, 169) /* XBAR1_OUT169 -> LPUART2 LPUART_TRG_INPUT */ +#define IMXRT_XBAR1_OUT_LPUART3_LPUART_TRG_INPUT IMXRT_XBAR1(XBAR_OUTPUT, 170) /* XBAR1_OUT170 -> LPUART3 LPUART_TRG_INPUT */ +#define IMXRT_XBAR1_OUT_LPUART4_LPUART_TRG_INPUT IMXRT_XBAR1(XBAR_OUTPUT, 171) /* XBAR1_OUT171 -> LPUART4 LPUART_TRG_INPUT */ +#define IMXRT_XBAR1_OUT_LPUART5_LPUART_TRG_INPUT IMXRT_XBAR1(XBAR_OUTPUT, 172) /* XBAR1_OUT172 -> LPUART5 LPUART_TRG_INPUT */ +#define IMXRT_XBAR1_OUT_LPUART6_LPUART_TRG_INPUT IMXRT_XBAR1(XBAR_OUTPUT, 173) /* XBAR1_OUT173 -> LPUART6 LPUART_TRG_INPUT */ +#define IMXRT_XBAR1_OUT_LPUART7_LPUART_TRG_INPUT IMXRT_XBAR1(XBAR_OUTPUT, 174) /* XBAR1_OUT174 -> LPUART7 LPUART_TRG_INPUT */ +#define IMXRT_XBAR1_OUT_LPUART8_LPUART_TRG_INPUT IMXRT_XBAR1(XBAR_OUTPUT, 175) /* XBAR1_OUT175 -> LPUART8 LPUART_TRG_INPUT */ +#define IMXRT_XBAR1_OUT_LPUART9_LPUART_TRG_INPUT IMXRT_XBAR1(XBAR_OUTPUT, 176) /* XBAR1_OUT176 -> LPUART9 LPUART_TRG_INPUT */ +#define IMXRT_XBAR1_OUT_LPUART10_LPUART_TRG_INPUT IMXRT_XBAR1(XBAR_OUTPUT, 177) /* XBAR1_OUT177 -> LPUART10 LPUART_TRG_INPUT */ +#define IMXRT_XBAR1_OUT_LPUART11_LPUART_TRG_INPUT IMXRT_XBAR1(XBAR_OUTPUT, 178) /* XBAR1_OUT178 -> LPUART11 LPUART_TRG_INPUT */ +#define IMXRT_XBAR1_OUT_LPUART12_LPUART_TRG_INPUT IMXRT_XBAR1(XBAR_OUTPUT, 179) /* XBAR1_OUT179 -> LPUART12 LPUART_TRG_INPUT */ +#define IMXRT_XBAR1_OUT_LPIT1_LPIT_EXT_TRIG_IN0 IMXRT_XBAR1(XBAR_OUTPUT, 180) /* XBAR1_OUT180 -> LPIT1 LPIT_EXT_TRIG_IN0 */ +#define IMXRT_XBAR1_OUT_LPIT1_LPIT_EXT_TRIG_IN1 IMXRT_XBAR1(XBAR_OUTPUT, 181) /* XBAR1_OUT181 -> LPIT1 LPIT_EXT_TRIG_IN1 */ +#define IMXRT_XBAR1_OUT_LPIT1_LPIT_EXT_TRIG_IN2 IMXRT_XBAR1(XBAR_OUTPUT, 182) /* XBAR1_OUT182 -> LPIT1 LPIT_EXT_TRIG_IN2 */ +#define IMXRT_XBAR1_OUT_LPIT1_LPIT_EXT_TRIG_IN3 IMXRT_XBAR1(XBAR_OUTPUT, 183) /* XBAR1_OUT183 -> LPIT1 LPIT_EXT_TRIG_IN3 */ +#define IMXRT_XBAR1_OUT_TPM1_TPM_TRIGGER_IN0 IMXRT_XBAR1(XBAR_OUTPUT, 184) /* XBAR1_OUT184 -> TPM1 TPM_TRIGGER_IN0 */ +#define IMXRT_XBAR1_OUT_TPM1_TPM_TRIGGER_IN1 IMXRT_XBAR1(XBAR_OUTPUT, 185) /* XBAR1_OUT185 -> TPM1 TPM_TRIGGER_IN1 */ +#define IMXRT_XBAR1_OUT_TPM2_TPM_TRIGGER_IN1 IMXRT_XBAR1(XBAR_OUTPUT, 186) /* XBAR1_OUT186 -> TPM2 TPM_TRIGGER_IN1 */ +#define IMXRT_XBAR1_OUT_TPM3_TPM_TRIGGER_IN1 IMXRT_XBAR1(XBAR_OUTPUT, 187) /* XBAR1_OUT187 -> TPM3 TPM_TRIGGER_IN1 */ +#define IMXRT_XBAR1_OUT_TPM1_TPM_TRIGGER_IN2 IMXRT_XBAR1(XBAR_OUTPUT, 188) /* XBAR1_OUT188 -> TPM1 TPM_TRIGGER_IN2 */ +#define IMXRT_XBAR1_OUT_TPM1_TPM_TRIGGER_IN3 IMXRT_XBAR1(XBAR_OUTPUT, 189) /* XBAR1_OUT189 -> TPM1 TPM_TRIGGER_IN3 */ +#define IMXRT_XBAR1_OUT_TPM2_TPM_TRIGGER_IN3 IMXRT_XBAR1(XBAR_OUTPUT, 190) /* XBAR1_OUT190 -> TPM2 TPM_TRIGGER_IN3 */ +#define IMXRT_XBAR1_OUT_TPM3_TPM_TRIGGER_IN3 IMXRT_XBAR1(XBAR_OUTPUT, 191) /* XBAR1_OUT191 -> TPM3 TPM_TRIGGER_IN3 */ +#define IMXRT_XBAR1_OUT_TPM4_TPM_TRIGGER_IN0 IMXRT_XBAR1(XBAR_OUTPUT, 192) /* XBAR1_OUT192 -> TPM4 TPM_TRIGGER_IN0 */ +#define IMXRT_XBAR1_OUT_TPM4_TPM_TRIGGER_IN1 IMXRT_XBAR1(XBAR_OUTPUT, 193) /* XBAR1_OUT193 -> TPM4 TPM_TRIGGER_IN1 */ +#define IMXRT_XBAR1_OUT_TPM5_TPM_TRIGGER_IN1 IMXRT_XBAR1(XBAR_OUTPUT, 194) /* XBAR1_OUT194 -> TPM5 TPM_TRIGGER_IN1 */ +#define IMXRT_XBAR1_OUT_TPM6_TPM_TRIGGER_IN1 IMXRT_XBAR1(XBAR_OUTPUT, 195) /* XBAR1_OUT195 -> TPM6 TPM_TRIGGER_IN1 */ +#define IMXRT_XBAR1_OUT_TPM4_TPM_TRIGGER_IN2 IMXRT_XBAR1(XBAR_OUTPUT, 196) /* XBAR1_OUT196 -> TPM4 TPM_TRIGGER_IN2 */ +#define IMXRT_XBAR1_OUT_TPM4_TPM_TRIGGER_IN3 IMXRT_XBAR1(XBAR_OUTPUT, 197) /* XBAR1_OUT197 -> TPM4 TPM_TRIGGER_IN3 */ +#define IMXRT_XBAR1_OUT_TPM5_TPM_TRIGGER_IN3 IMXRT_XBAR1(XBAR_OUTPUT, 198) /* XBAR1_OUT198 -> TPM5 TPM_TRIGGER_IN3 */ +#define IMXRT_XBAR1_OUT_TPM6_TPM_TRIGGER_IN3 IMXRT_XBAR1(XBAR_OUTPUT, 199) /* XBAR1_OUT199 -> TPM6 TPM_TRIGGER_IN3 */ +#define IMXRT_XBAR1_OUT_NETC_TMR_1588_TRIG1 IMXRT_XBAR1(XBAR_OUTPUT, 200) /* XBAR1_OUT200 -> NETC TMR_1588_TRIG1 */ +#define IMXRT_XBAR1_OUT_NETC_TMR_1588_TRIG2 IMXRT_XBAR1(XBAR_OUTPUT, 201) /* XBAR1_OUT201 -> NETC TMR_1588_TRIG2 */ +#define IMXRT_XBAR1_OUT_RESERVED IMXRT_XBAR1(XBAR_OUTPUT, 202) /* XBAR1_OUT202 -> - Reserved */ +#define IMXRT_XBAR1_OUT_RESERVED_2 IMXRT_XBAR1(XBAR_OUTPUT, 203) /* XBAR1_OUT203 -> - Reserved */ +#define IMXRT_XBAR1_OUT_RESERVED_3 IMXRT_XBAR1(XBAR_OUTPUT, 204) /* XBAR1_OUT204 -> - Reserved */ +#define IMXRT_XBAR1_OUT_RESERVED_4 IMXRT_XBAR1(XBAR_OUTPUT, 205) /* XBAR1_OUT205 -> - Reserved */ +#define IMXRT_XBAR1_OUT_EQDC1_ICAP1 IMXRT_XBAR1(XBAR_OUTPUT, 206) /* XBAR1_OUT206 -> eQDC1 ICAP1 */ +#define IMXRT_XBAR1_OUT_EQDC1_ICAP2 IMXRT_XBAR1(XBAR_OUTPUT, 207) /* XBAR1_OUT207 -> eQDC1 ICAP2 */ +#define IMXRT_XBAR1_OUT_EQDC1_ICAP3 IMXRT_XBAR1(XBAR_OUTPUT, 208) /* XBAR1_OUT208 -> eQDC1 ICAP3 */ +#define IMXRT_XBAR1_OUT_EQDC2_ICAP1 IMXRT_XBAR1(XBAR_OUTPUT, 209) /* XBAR1_OUT209 -> eQDC2 ICAP1 */ +#define IMXRT_XBAR1_OUT_EQDC2_ICAP2 IMXRT_XBAR1(XBAR_OUTPUT, 210) /* XBAR1_OUT210 -> eQDC2 ICAP2 */ +#define IMXRT_XBAR1_OUT_EQDC2_ICAP3 IMXRT_XBAR1(XBAR_OUTPUT, 211) /* XBAR1_OUT211 -> eQDC2 ICAP3 */ +#define IMXRT_XBAR1_OUT_EQDC3_ICAP1 IMXRT_XBAR1(XBAR_OUTPUT, 212) /* XBAR1_OUT212 -> eQDC3 ICAP1 */ +#define IMXRT_XBAR1_OUT_EQDC3_ICAP2 IMXRT_XBAR1(XBAR_OUTPUT, 213) /* XBAR1_OUT213 -> eQDC3 ICAP2 */ +#define IMXRT_XBAR1_OUT_EQDC3_ICAP3 IMXRT_XBAR1(XBAR_OUTPUT, 214) /* XBAR1_OUT214 -> eQDC3 ICAP3 */ +#define IMXRT_XBAR1_OUT_EQDC4_ICAP1 IMXRT_XBAR1(XBAR_OUTPUT, 215) /* XBAR1_OUT215 -> eQDC4 ICAP1 */ +#define IMXRT_XBAR1_OUT_EQDC4_ICAP2 IMXRT_XBAR1(XBAR_OUTPUT, 216) /* XBAR1_OUT216 -> eQDC4 ICAP2 */ +#define IMXRT_XBAR1_OUT_EQDC4_ICAP3 IMXRT_XBAR1(XBAR_OUTPUT, 217) /* XBAR1_OUT217 -> eQDC4 ICAP3 */ +#define IMXRT_XBAR1_OUT_ECAT_LATCH_IN0 IMXRT_XBAR1(XBAR_OUTPUT, 218) /* XBAR1_OUT218 -> ECAT LATCH_IN0 */ +#define IMXRT_XBAR1_OUT_ECAT_LATCH_IN1 IMXRT_XBAR1(XBAR_OUTPUT, 219) /* XBAR1_OUT219 -> ECAT LATCH_IN1 */ +#define IMXRT_XBAR1_OUT_SAFETY_CLK_DUT_CLK_MON IMXRT_XBAR1(XBAR_OUTPUT, 220) /* XBAR1_OUT220 -> SAFETY_CLK DUT_CLK - _MON */ + +#define IMXRT_XBAR2_OUT_AOI1_AOI_IN0 IMXRT_XBAR2(XBAR_OUTPUT, 0) /* XBAR2_OUT0 -> AOI1 AOI_IN0 */ +#define IMXRT_XBAR2_OUT_AOI1_AOI_IN1 IMXRT_XBAR2(XBAR_OUTPUT, 1) /* XBAR2_OUT1 -> AOI1 AOI_IN1 */ +#define IMXRT_XBAR2_OUT_AOI1_AOI_IN2 IMXRT_XBAR2(XBAR_OUTPUT, 2) /* XBAR2_OUT2 -> AOI1 AOI_IN2 */ +#define IMXRT_XBAR2_OUT_AOI1_AOI_IN3 IMXRT_XBAR2(XBAR_OUTPUT, 3) /* XBAR2_OUT3 -> AOI1 AOI_IN3 */ +#define IMXRT_XBAR2_OUT_AOI1_AOI_IN4 IMXRT_XBAR2(XBAR_OUTPUT, 4) /* XBAR2_OUT4 -> AOI1 AOI_IN4 */ +#define IMXRT_XBAR2_OUT_AOI1_AOI_IN5 IMXRT_XBAR2(XBAR_OUTPUT, 5) /* XBAR2_OUT5 -> AOI1 AOI_IN5 */ +#define IMXRT_XBAR2_OUT_AOI1_AOI_IN6 IMXRT_XBAR2(XBAR_OUTPUT, 6) /* XBAR2_OUT6 -> AOI1 AOI_IN6 */ +#define IMXRT_XBAR2_OUT_AOI1_AOI_IN7 IMXRT_XBAR2(XBAR_OUTPUT, 7) /* XBAR2_OUT7 -> AOI1 AOI_IN7 */ +#define IMXRT_XBAR2_OUT_AOI1_AOI_IN8 IMXRT_XBAR2(XBAR_OUTPUT, 8) /* XBAR2_OUT8 -> AOI1 AOI_IN8 */ +#define IMXRT_XBAR2_OUT_AOI1_AOI_IN9 IMXRT_XBAR2(XBAR_OUTPUT, 9) /* XBAR2_OUT9 -> AOI1 AOI_IN9 */ +#define IMXRT_XBAR2_OUT_AOI1_AOI_IN10 IMXRT_XBAR2(XBAR_OUTPUT, 10) /* XBAR2_OUT10 -> AOI1 AOI_IN10 */ +#define IMXRT_XBAR2_OUT_AOI1_AOI_IN11 IMXRT_XBAR2(XBAR_OUTPUT, 11) /* XBAR2_OUT11 -> AOI1 AOI_IN11 */ +#define IMXRT_XBAR2_OUT_AOI1_AOI_IN12 IMXRT_XBAR2(XBAR_OUTPUT, 12) /* XBAR2_OUT12 -> AOI1 AOI_IN12 */ +#define IMXRT_XBAR2_OUT_AOI1_AOI_IN13 IMXRT_XBAR2(XBAR_OUTPUT, 13) /* XBAR2_OUT13 -> AOI1 AOI_IN13 */ +#define IMXRT_XBAR2_OUT_AOI1_AOI_IN14 IMXRT_XBAR2(XBAR_OUTPUT, 14) /* XBAR2_OUT14 -> AOI1 AOI_IN14 */ +#define IMXRT_XBAR2_OUT_AOI1_AOI_IN15 IMXRT_XBAR2(XBAR_OUTPUT, 15) /* XBAR2_OUT15 -> AOI1 AOI_IN15 */ +#define IMXRT_XBAR2_OUT_AOI3_AOI_IN0 IMXRT_XBAR2(XBAR_OUTPUT, 16) /* XBAR2_OUT16 -> AOI3 AOI_IN0 */ +#define IMXRT_XBAR2_OUT_AOI3_AOI_IN1 IMXRT_XBAR2(XBAR_OUTPUT, 17) /* XBAR2_OUT17 -> AOI3 AOI_IN1 */ +#define IMXRT_XBAR2_OUT_AOI3_AOI_IN2 IMXRT_XBAR2(XBAR_OUTPUT, 18) /* XBAR2_OUT18 -> AOI3 AOI_IN2 */ +#define IMXRT_XBAR2_OUT_AOI3_AOI_IN3 IMXRT_XBAR2(XBAR_OUTPUT, 19) /* XBAR2_OUT19 -> AOI3 AOI_IN3 */ +#define IMXRT_XBAR2_OUT_AOI3_AOI_IN4 IMXRT_XBAR2(XBAR_OUTPUT, 20) /* XBAR2_OUT20 -> AOI3 AOI_IN4 */ +#define IMXRT_XBAR2_OUT_AOI3_AOI_IN5 IMXRT_XBAR2(XBAR_OUTPUT, 21) /* XBAR2_OUT21 -> AOI3 AOI_IN5 */ +#define IMXRT_XBAR2_OUT_AOI3_AOI_IN6 IMXRT_XBAR2(XBAR_OUTPUT, 22) /* XBAR2_OUT22 -> AOI3 AOI_IN6 */ +#define IMXRT_XBAR2_OUT_AOI3_AOI_IN7 IMXRT_XBAR2(XBAR_OUTPUT, 23) /* XBAR2_OUT23 -> AOI3 AOI_IN7 */ +#define IMXRT_XBAR2_OUT_AOI3_AOI_IN8 IMXRT_XBAR2(XBAR_OUTPUT, 24) /* XBAR2_OUT24 -> AOI3 AOI_IN8 */ +#define IMXRT_XBAR2_OUT_AOI3_AOI_IN9 IMXRT_XBAR2(XBAR_OUTPUT, 25) /* XBAR2_OUT25 -> AOI3 AOI_IN9 */ +#define IMXRT_XBAR2_OUT_AOI3_AOI_IN10 IMXRT_XBAR2(XBAR_OUTPUT, 26) /* XBAR2_OUT26 -> AOI3 AOI_IN10 */ +#define IMXRT_XBAR2_OUT_AOI3_AOI_IN11 IMXRT_XBAR2(XBAR_OUTPUT, 27) /* XBAR2_OUT27 -> AOI3 AOI_IN11 */ +#define IMXRT_XBAR2_OUT_AOI3_AOI_IN12 IMXRT_XBAR2(XBAR_OUTPUT, 28) /* XBAR2_OUT28 -> AOI3 AOI_IN12 */ +#define IMXRT_XBAR2_OUT_AOI3_AOI_IN13 IMXRT_XBAR2(XBAR_OUTPUT, 29) /* XBAR2_OUT29 -> AOI3 AOI_IN13 */ +#define IMXRT_XBAR2_OUT_AOI3_AOI_IN14 IMXRT_XBAR2(XBAR_OUTPUT, 30) /* XBAR2_OUT30 -> AOI3 AOI_IN14 */ +#define IMXRT_XBAR2_OUT_AOI3_AOI_IN15 IMXRT_XBAR2(XBAR_OUTPUT, 31) /* XBAR2_OUT31 -> AOI3 AOI_IN15 */ + +#define IMXRT_XBAR3_OUT_AOI2_AOI_IN0 IMXRT_XBAR3(XBAR_OUTPUT, 0) /* XBAR3_OUT0 -> AOI2 AOI_IN0 */ +#define IMXRT_XBAR3_OUT_AOI2_AOI_IN1 IMXRT_XBAR3(XBAR_OUTPUT, 1) /* XBAR3_OUT1 -> AOI2 AOI_IN1 */ +#define IMXRT_XBAR3_OUT_AOI2_AOI_IN2 IMXRT_XBAR3(XBAR_OUTPUT, 2) /* XBAR3_OUT2 -> AOI2 AOI_IN2 */ +#define IMXRT_XBAR3_OUT_AOI2_AOI_IN3 IMXRT_XBAR3(XBAR_OUTPUT, 3) /* XBAR3_OUT3 -> AOI2 AOI_IN3 */ +#define IMXRT_XBAR3_OUT_AOI2_AOI_IN4 IMXRT_XBAR3(XBAR_OUTPUT, 4) /* XBAR3_OUT4 -> AOI2 AOI_IN4 */ +#define IMXRT_XBAR3_OUT_AOI2_AOI_IN5 IMXRT_XBAR3(XBAR_OUTPUT, 5) /* XBAR3_OUT5 -> AOI2 AOI_IN5 */ +#define IMXRT_XBAR3_OUT_AOI2_AOI_IN6 IMXRT_XBAR3(XBAR_OUTPUT, 6) /* XBAR3_OUT6 -> AOI2 AOI_IN6 */ +#define IMXRT_XBAR3_OUT_AOI2_AOI_IN7 IMXRT_XBAR3(XBAR_OUTPUT, 7) /* XBAR3_OUT7 -> AOI2 AOI_IN7 */ +#define IMXRT_XBAR3_OUT_AOI2_AOI_IN8 IMXRT_XBAR3(XBAR_OUTPUT, 8) /* XBAR3_OUT8 -> AOI2 AOI_IN8 */ +#define IMXRT_XBAR3_OUT_AOI2_AOI_IN9 IMXRT_XBAR3(XBAR_OUTPUT, 9) /* XBAR3_OUT9 -> AOI2 AOI_IN9 */ +#define IMXRT_XBAR3_OUT_AOI2_AOI_IN10 IMXRT_XBAR3(XBAR_OUTPUT, 10) /* XBAR3_OUT10 -> AOI2 AOI_IN10 */ +#define IMXRT_XBAR3_OUT_AOI2_AOI_IN11 IMXRT_XBAR3(XBAR_OUTPUT, 11) /* XBAR3_OUT11 -> AOI2 AOI_IN11 */ +#define IMXRT_XBAR3_OUT_AOI2_AOI_IN12 IMXRT_XBAR3(XBAR_OUTPUT, 12) /* XBAR3_OUT12 -> AOI2 AOI_IN12 */ +#define IMXRT_XBAR3_OUT_AOI2_AOI_IN13 IMXRT_XBAR3(XBAR_OUTPUT, 13) /* XBAR3_OUT13 -> AOI2 AOI_IN13 */ +#define IMXRT_XBAR3_OUT_AOI2_AOI_IN14 IMXRT_XBAR3(XBAR_OUTPUT, 14) /* XBAR3_OUT14 -> AOI2 AOI_IN14 */ +#define IMXRT_XBAR3_OUT_AOI2_AOI_IN15 IMXRT_XBAR3(XBAR_OUTPUT, 15) /* XBAR3_OUT15 -> AOI2 AOI_IN15 */ +#define IMXRT_XBAR3_OUT_AOI4_AOI_IN0 IMXRT_XBAR3(XBAR_OUTPUT, 16) /* XBAR3_OUT16 -> AOI4 AOI_IN0 */ +#define IMXRT_XBAR3_OUT_AOI4_AOI_IN1 IMXRT_XBAR3(XBAR_OUTPUT, 17) /* XBAR3_OUT17 -> AOI4 AOI_IN1 */ +#define IMXRT_XBAR3_OUT_AOI4_AOI_IN2 IMXRT_XBAR3(XBAR_OUTPUT, 18) /* XBAR3_OUT18 -> AOI4 AOI_IN2 */ +#define IMXRT_XBAR3_OUT_AOI4_AOI_IN3 IMXRT_XBAR3(XBAR_OUTPUT, 19) /* XBAR3_OUT19 -> AOI4 AOI_IN3 */ +#define IMXRT_XBAR3_OUT_AOI4_AOI_IN4 IMXRT_XBAR3(XBAR_OUTPUT, 20) /* XBAR3_OUT20 -> AOI4 AOI_IN4 */ +#define IMXRT_XBAR3_OUT_AOI4_AOI_IN5 IMXRT_XBAR3(XBAR_OUTPUT, 21) /* XBAR3_OUT21 -> AOI4 AOI_IN5 */ +#define IMXRT_XBAR3_OUT_AOI4_AOI_IN6 IMXRT_XBAR3(XBAR_OUTPUT, 22) /* XBAR3_OUT22 -> AOI4 AOI_IN6 */ +#define IMXRT_XBAR3_OUT_AOI4_AOI_IN7 IMXRT_XBAR3(XBAR_OUTPUT, 23) /* XBAR3_OUT23 -> AOI4 AOI_IN7 */ +#define IMXRT_XBAR3_OUT_AOI4_AOI_IN8 IMXRT_XBAR3(XBAR_OUTPUT, 24) /* XBAR3_OUT24 -> AOI4 AOI_IN8 */ +#define IMXRT_XBAR3_OUT_AOI4_AOI_IN9 IMXRT_XBAR3(XBAR_OUTPUT, 25) /* XBAR3_OUT25 -> AOI4 AOI_IN9 */ +#define IMXRT_XBAR3_OUT_AOI4_AOI_IN10 IMXRT_XBAR3(XBAR_OUTPUT, 26) /* XBAR3_OUT26 -> AOI4 AOI_IN10 */ +#define IMXRT_XBAR3_OUT_AOI4_AOI_IN11 IMXRT_XBAR3(XBAR_OUTPUT, 27) /* XBAR3_OUT27 -> AOI4 AOI_IN11 */ +#define IMXRT_XBAR3_OUT_AOI4_AOI_IN12 IMXRT_XBAR3(XBAR_OUTPUT, 28) /* XBAR3_OUT28 -> AOI4 AOI_IN12 */ +#define IMXRT_XBAR3_OUT_AOI4_AOI_IN13 IMXRT_XBAR3(XBAR_OUTPUT, 29) /* XBAR3_OUT29 -> AOI4 AOI_IN13 */ +#define IMXRT_XBAR3_OUT_AOI4_AOI_IN14 IMXRT_XBAR3(XBAR_OUTPUT, 30) /* XBAR3_OUT30 -> AOI4 AOI_IN14 */ +#define IMXRT_XBAR3_OUT_AOI4_AOI_IN15 IMXRT_XBAR3(XBAR_OUTPUT, 31) /* XBAR3_OUT31 -> AOI4 AOI_IN15 */ + +#endif /* __ARCH_ARM_SRC_IMXRT_HARDWARE_RT118X_IMXRT118X_XBAR_H */ diff --git a/arch/arm/src/imxrt/imxrt118x_ele.c b/arch/arm/src/imxrt/imxrt118x_ele.c new file mode 100644 index 0000000000000..0c7f8ffb322b2 --- /dev/null +++ b/arch/arm/src/imxrt/imxrt118x_ele.c @@ -0,0 +1,694 @@ +/**************************************************************************** + * arch/arm/src/imxrt/imxrt118x_ele.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include + +#include +#include +#include +#include +#include +#include + +#include "arm_internal.h" +#include "hardware/rt118x/imxrt118x_memorymap.h" +#include "imxrt118x_ele.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#ifdef CONFIG_IMXRT_ELE_LOAD_FW +# ifndef IMXRT_ELE_FW_ABS_PATH +# error "IMXRT_ELE_FW_ABS_PATH must be set via CFLAGS (see arch/arm/src/imxrt/Make.defs)" +# endif + +# define STR2(m) #m +# define STR(m) STR2(m) +#endif + +/* The M7 core is Armv7-M and the M33 core is Armv8-M; pick whichever + * D-Cache line size macro chip.h provided for the core we're building + * for. + */ + +#if defined(ARMV8M_DCACHE_LINESIZE) +# define DCACHE_LINESIZE ARMV8M_DCACHE_LINESIZE +#else +# define DCACHE_LINESIZE ARMV7M_DCACHE_LINESIZE +#endif + +#define upper_32_bits(n) ((uint32_t)(((n) >> 16) >> 16)) +#define lower_32_bits(n) ((uint32_t)(n)) + +#define ELE_RNG_TIMEOUT_US 5000 +#define ELE_RNG_SLEEP_US 100 +#define ELE_TRNG_STATUS_READY 0x3 +#define ELE_CSAL_STATUS_READY 0x2 + +/**************************************************************************** + * Private Types + ****************************************************************************/ + +struct ele_trng_state +{ + uint8_t trng_state; + uint8_t csal_state; + uint16_t reserved; +}; + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +static struct ele_msg g_msg; + +#ifdef CONFIG_IMXRT_ELE_LOAD_FW +/* Embeds the NXP EdgeLock Enclave firmware AHAB container (path from + * CONFIG_IMXRT_ELE_FW_PATH) directly into the driver image so that + * imxrt118x_ele_init() can hand its address to the ELE via LOAD_FW at + * boot time, without depending on where the container sits in the outer + * AHAB flash layout. + * + * The container is proprietary NXP object code; see + * tools/imxrt1180/Config.mk for the license note. + * + * This is legacy/fallback support: the RT118x ROM can also load the ELE + * FW automatically from a properly packed AHAB container, in which case + * CONFIG_IMXRT_ELE_LOAD_FW should be left disabled (the default). + */ + +__asm__ ( + ".section .rodata.imxrt118x_ele_fw, \"a\"\n" + ".balign 8\n" + ".globl imxrt118x_ele_fw\n" +"imxrt118x_ele_fw:\n" + ".incbin " STR(IMXRT_ELE_FW_ABS_PATH) "\n" + ".balign 8\n" + ".globl imxrt118x_ele_fw_end\n" +"imxrt118x_ele_fw_end:\n" +); +#endif + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: imxrt118x_ele_sendmsg + * + * Description: + * Send a message to the EdgeLock Enclave over the System 3 Message Unit A. + * + ****************************************************************************/ + +static void imxrt118x_ele_sendmsg(struct ele_msg *msg_ptr) +{ + /* Check that ele is ready to receive */ + + while (!((1) & getreg32(ELE_MU_TSR))); + + /* write header to slot 0 */ + + putreg32(msg_ptr->header.data, ELE_MU_TR(0)); + + /* write data */ + + for (int i = 1; i < msg_ptr->header.size; i++) + { + int tx_channel; + + tx_channel = i % ELE_TR_NUM; + while (!((1 << tx_channel) & getreg32(ELE_MU_TSR))); + + /* Write data */ + + putreg32(msg_ptr->data[i - 1], ELE_MU_TR(tx_channel)); + } +} + +/**************************************************************************** + * Name: imxrt118x_ele_receivemsg + * + * Description: + * Receive a response message from the EdgeLock Enclave. + * + ****************************************************************************/ + +static void imxrt118x_ele_receivemsg(struct ele_msg *msg_ptr) +{ + /* Check if data ready */ + + while (!((1) & getreg32(ELE_MU_RSR))); + + /* Read Header from slot 0 */ + + msg_ptr->header.data = getreg32(ELE_MU_RR(0)); + + for (int i = 1; i < msg_ptr->header.size; i++) + { + /* Check if empty */ + + int rx_channel = (i) % ELE_RR_NUM; + + while (!((1 << rx_channel) & getreg32(ELE_MU_RSR))); + + /* Read data */ + + msg_ptr->data[i - 1] = getreg32(ELE_MU_RR(rx_channel)); + } +} + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +void imxrt118x_ele_init(void) +{ + putreg32(0, ELE_MU_TCR); + putreg32(0, ELE_MU_RCR); + +#ifdef CONFIG_IMXRT_ELE_LOAD_FW + /* Load the ELE firmware ourselves. The RT118x ROM only ships a minimal + * ELE stub that understands LOAD_FW, so every other ELE command - + * RELEASE_RDC, ENABLE_APC - depends on this. The blob is embedded in + * this file (from CONFIG_IMXRT_ELE_FW_PATH). + * + * This is disabled by default: the RT118x ROM can instead load a + * properly packed AHAB container containing the ELE FW automatically, + * before this code ever runs (see tools/imxrt1180/build_flash_image.sh). + */ + + imxrt118x_ele_load_fw((uint32_t)(uintptr_t)imxrt118x_ele_fw); +#endif + + /* Verify that some ELE firmware - whichever way it got there - is + * actually running, by reading back its version. + */ + + imxrt118x_ele_check_fw_version(); +} + +int imxrt118x_ele_load_fw(uint32_t fw_addr) +{ + g_msg.header.version = ELE_VERSION; + g_msg.header.tag = ELE_CMD_TAG; + g_msg.header.size = 4; + g_msg.header.command = ELE_LOAD_FW_REQ; + g_msg.data[0] = fw_addr; + g_msg.data[1] = 0; + g_msg.data[2] = fw_addr; + + imxrt118x_ele_sendmsg(&g_msg); + imxrt118x_ele_receivemsg(&g_msg); + + if ((g_msg.data[0] & 0xff) == ELE_OK) + { + return 0; + } + + return -EIO; +} + +int imxrt118x_ele_release_rdc(uint32_t rdc_id) +{ + g_msg.header.version = ELE_VERSION; + g_msg.header.tag = ELE_CMD_TAG; + g_msg.header.size = 2; + g_msg.header.command = ELE_RELEASE_RDC_REQ; + g_msg.data[0] = rdc_id; + + imxrt118x_ele_sendmsg(&g_msg); + imxrt118x_ele_receivemsg(&g_msg); + + if ((g_msg.data[0] & 0xff) == ELE_OK) + { + return 0; + } + + return -EIO; +} + +uint32_t imxrt118x_ele_read_common_fuse(uint32_t fuse_id) +{ + uint32_t value = 0; + + g_msg.header.version = ELE_VERSION; + g_msg.header.tag = ELE_CMD_TAG; + g_msg.header.size = 2; + g_msg.header.command = ELE_READ_FUSE_REQ; + g_msg.data[0] = fuse_id; + + imxrt118x_ele_sendmsg(&g_msg); + imxrt118x_ele_receivemsg(&g_msg); + + if ((g_msg.data[0] & 0xff) == ELE_OK) + { + value = g_msg.data[1]; + } + + return value; +} + +int imxrt118x_ele_get_key(uint8_t *key, size_t key_size, + uint8_t *ctx, size_t ctx_size) +{ + if (!key) + { + _err("Invalid key parameter\n"); + return -EINVAL; + } + + if (!ctx) + { + _err("Invalid context parameter\n"); + return -EINVAL; + } + + if ((key_size != 16) && (key_size != 32)) + { + _err("Invalid key size\n"); + return -EINVAL; + } + + if (!IS_ALIGNED((uintptr_t)key, DCACHE_LINESIZE)) + { + _err("Invalid key alignment\n"); + return -EINVAL; + } + + if (!IS_ALIGNED((uintptr_t)ctx, DCACHE_LINESIZE)) + { + _err("Invalid context alignment\n"); + return -EINVAL; + } + + g_msg.header.version = ELE_VERSION; + g_msg.header.tag = ELE_CMD_TAG; + g_msg.header.size = 7; + g_msg.header.command = ELE_DERIVE_KEY_REQ; + g_msg.data[0] = upper_32_bits((uintptr_t)key); + g_msg.data[1] = lower_32_bits((uintptr_t)key); + g_msg.data[2] = upper_32_bits((uintptr_t)ctx); + g_msg.data[3] = lower_32_bits((uintptr_t)ctx); + g_msg.data[4] = ((ctx_size << 16) | key_size); + + uint32_t crc = g_msg.header.data; + + for (uint32_t i = 0; i < g_msg.header.size - 2; i++) + { + crc ^= g_msg.data[i]; + } + + g_msg.data[5] = crc; + + up_flush_dcache((uintptr_t)ctx, (uintptr_t)(ctx + ctx_size)); + up_invalidate_dcache((uintptr_t)key, (uintptr_t)(key + key_size)); + + imxrt118x_ele_sendmsg(&g_msg); + imxrt118x_ele_receivemsg(&g_msg); + + up_invalidate_dcache((uintptr_t)key, (uintptr_t)(key + key_size)); + + if ((g_msg.data[0] & 0xff) == ELE_OK) + { + return 0; + } + + return -EIO; +} + +int imxrt118x_ele_get_events(uint32_t *buffer, size_t buffer_size) +{ + size_t events_num; + size_t i; + + g_msg.header.version = ELE_VERSION; + g_msg.header.tag = ELE_CMD_TAG; + g_msg.header.size = 1; + g_msg.header.command = ELE_GET_EVENTS_REQ; + + imxrt118x_ele_sendmsg(&g_msg); + imxrt118x_ele_receivemsg(&g_msg); + + if ((g_msg.data[0] & 0xff) == ELE_OK) + { + events_num = g_msg.data[1] & 0xffff; + if (buffer) + { + for (i = 0; (i < buffer_size) && (i < events_num); i++) + { + buffer[i] = g_msg.data[i + 2]; + } + + return (int)i; + } + else + { + return (int)events_num; + } + } + + return -EIO; +} + +int imxrt118x_ele_close_device(void) +{ + g_msg.header.version = ELE_VERSION; + g_msg.header.tag = ELE_CMD_TAG; + g_msg.header.size = 2; + g_msg.header.command = ELE_FWD_LIFECYCLE_UP_REQ; + g_msg.data[0] = 0x08; + + imxrt118x_ele_sendmsg(&g_msg); + imxrt118x_ele_receivemsg(&g_msg); + + if ((g_msg.data[0] & 0xff) == ELE_OK) + { + return 0; + } + + return -EIO; +} + +uint32_t imxrt118x_ele_get_lifecycle(void) +{ + static uint8_t info[ELE_GET_INFO_BYTES] + aligned_data(DCACHE_LINESIZE); + + uint32_t addr = (uint32_t)(uintptr_t)info; + + g_msg.header.version = ELE_VERSION; + g_msg.header.tag = ELE_CMD_TAG; + g_msg.header.size = 4; + g_msg.header.command = ELE_GET_INFO_REQ; + g_msg.data[0] = upper_32_bits(addr); + g_msg.data[1] = lower_32_bits(addr); + g_msg.data[2] = sizeof(info); + + up_invalidate_dcache(addr, addr + sizeof(info)); + + imxrt118x_ele_sendmsg(&g_msg); + imxrt118x_ele_receivemsg(&g_msg); + + if ((g_msg.data[0] & 0xff) != ELE_OK) + { + return 0; + } + + up_invalidate_dcache(addr, addr + sizeof(info)); + + return ((uint32_t *)info)[ELE_GET_INFO_LC_WORD] & ELE_GET_INFO_LC_MASK; +} + +int imxrt118x_ele_auth_oem_ctnr(unsigned long ctnr_addr, uint32_t *response) +{ + g_msg.header.version = ELE_VERSION; + g_msg.header.tag = ELE_CMD_TAG; + g_msg.header.size = 3; + g_msg.header.command = ELE_OEM_CNTN_AUTH_REQ; + g_msg.data[0] = upper_32_bits(ctnr_addr); + g_msg.data[1] = lower_32_bits(ctnr_addr); + + imxrt118x_ele_sendmsg(&g_msg); + imxrt118x_ele_receivemsg(&g_msg); + if (response) + { + *response = g_msg.data[0]; + } + + if ((g_msg.data[0] & 0xff) == ELE_OK) + { + return 0; + } + + return -EIO; +} + +int imxrt118x_ele_release_container(uint32_t *response) +{ + g_msg.header.version = ELE_VERSION; + g_msg.header.tag = ELE_CMD_TAG; + g_msg.header.size = 1; + g_msg.header.command = ELE_RELEASE_CONTAINER_REQ; + + imxrt118x_ele_sendmsg(&g_msg); + imxrt118x_ele_receivemsg(&g_msg); + + if (response) + { + *response = g_msg.data[0]; + } + + if ((g_msg.data[0] & 0xff) == ELE_OK) + { + return 0; + } + + return -EIO; +} + +int imxrt118x_ele_verify_image(uint32_t img_id, uint32_t *response) +{ + g_msg.header.version = ELE_VERSION; + g_msg.header.tag = ELE_CMD_TAG; + g_msg.header.size = 2; + g_msg.header.command = ELE_VERIFY_IMAGE_REQ; + g_msg.data[0] = 1 << img_id; + + imxrt118x_ele_sendmsg(&g_msg); + imxrt118x_ele_receivemsg(&g_msg); + + if (response) + { + *response = g_msg.data[0]; + } + + if ((g_msg.data[0] & 0xff) == ELE_OK) + { + return 0; + } + + return -EIO; +} + +int imxrt118x_ele_start_rng(void) +{ + g_msg.header.version = ELE_VERSION; + g_msg.header.tag = ELE_CMD_TAG; + g_msg.header.size = 1; + g_msg.header.command = ELE_START_RNG_REQ; + + imxrt118x_ele_sendmsg(&g_msg); + imxrt118x_ele_receivemsg(&g_msg); + + if ((g_msg.data[0] & 0xff) == ELE_OK) + { + return 0; + } + + return -EIO; +} + +int imxrt118x_ele_get_trng_state(void) +{ + g_msg.header.version = ELE_VERSION; + g_msg.header.tag = ELE_CMD_TAG; + g_msg.header.size = 1; + g_msg.header.command = ELE_GET_TRNG_STATE_REQ; + + imxrt118x_ele_sendmsg(&g_msg); + imxrt118x_ele_receivemsg(&g_msg); + + if ((g_msg.data[0] & 0xff) == ELE_OK) + { + struct ele_trng_state *ele_trng = + (struct ele_trng_state *)(g_msg.data + 1); + + if (ele_trng->trng_state != ELE_TRNG_STATUS_READY || + ele_trng->csal_state != ELE_CSAL_STATUS_READY) + { + /* Ensure imxrt118x_ele_start_rng() was called earlier or we + * will end up here. + */ + + return -EBUSY; + } + else + { + return 0; + } + } + + return -EIO; +} + +int imxrt118x_ele_get_random(uint32_t paddr, size_t len) +{ + uint16_t counter = 0; + uint16_t max_tries = ELE_RNG_TIMEOUT_US / ELE_RNG_SLEEP_US; + + if (paddr == 0 || len == 0) + { + _err("Wrong input parameters!\n"); + return -EINVAL; + } + + while ((imxrt118x_ele_get_trng_state() != 0)) + { + if (counter > max_tries) + { + _err("Timed out after %hu iterations!\n", counter); + return -EBUSY; + } + + usleep(ELE_RNG_SLEEP_US); + counter++; + } + + /* Flush the cache before sending the request to ELE. */ + + up_flush_dcache((uintptr_t)paddr, (uintptr_t)(paddr + len)); + + g_msg.header.version = ELE_VERSION_FW; + g_msg.header.tag = ELE_CMD_TAG; + g_msg.header.size = 4; + g_msg.header.command = ELE_GET_RNG_REQ; + g_msg.data[0] = 0; + g_msg.data[1] = paddr; + g_msg.data[2] = len; + + imxrt118x_ele_sendmsg(&g_msg); + imxrt118x_ele_receivemsg(&g_msg); + + if ((g_msg.data[0] & 0xff) == ELE_OK) + { + /* Invalidate the cache so we can read the result from RAM. */ + + up_invalidate_dcache((uintptr_t)paddr, + (uintptr_t)(paddr + len)); + return 0; + } + + return -EIO; +} + +int imxrt118x_ele_commit(uint32_t info, uint32_t *response) +{ + g_msg.header.version = ELE_VERSION; + g_msg.header.tag = ELE_CMD_TAG; + g_msg.header.size = 2; + g_msg.header.command = ELE_COMMIT_REQ; + g_msg.data[0] = info; + + imxrt118x_ele_sendmsg(&g_msg); + imxrt118x_ele_receivemsg(&g_msg); + + if (response) + { + *response = g_msg.data[0]; + } + + if ((g_msg.data[0] & 0xff) == ELE_OK) + { + return 0; + } + + return -EIO; +} + +int imxrt118x_ele_enable_apc(void) +{ + g_msg.header.version = ELE_VERSION; + g_msg.header.tag = ELE_CMD_TAG; + g_msg.header.size = 1; + g_msg.header.command = ELE_ENABLE_APC_REQ; + + imxrt118x_ele_sendmsg(&g_msg); + imxrt118x_ele_receivemsg(&g_msg); + + if ((g_msg.data[0] & 0xff) == ELE_OK) + { + return 0; + } + + return -EIO; +} + +int imxrt118x_ele_voltage_change_start(void) +{ + g_msg.header.version = ELE_VERSION; + g_msg.header.tag = ELE_CMD_TAG; + g_msg.header.size = 1; + g_msg.header.command = ELE_VOLTAGE_CHANGE_START_REQ; + + imxrt118x_ele_sendmsg(&g_msg); + imxrt118x_ele_receivemsg(&g_msg); + + if ((g_msg.data[0] & 0xff) == ELE_OK) + { + return 0; + } + + return -EIO; +} + +int imxrt118x_ele_voltage_change_finish(void) +{ + g_msg.header.version = ELE_VERSION; + g_msg.header.tag = ELE_CMD_TAG; + g_msg.header.size = 1; + g_msg.header.command = ELE_VOLTAGE_CHANGE_FINISH_REQ; + + imxrt118x_ele_sendmsg(&g_msg); + imxrt118x_ele_receivemsg(&g_msg); + + if ((g_msg.data[0] & 0xff) == ELE_OK) + { + return 0; + } + + return -EIO; +} + +int imxrt118x_ele_check_fw_version(void) +{ + g_msg.header.version = ELE_VERSION; + g_msg.header.tag = ELE_CMD_TAG; + g_msg.header.size = 1; + g_msg.header.command = ELE_GET_FW_VERSION_REQ; + + imxrt118x_ele_sendmsg(&g_msg); + imxrt118x_ele_receivemsg(&g_msg); + + if ((g_msg.data[0] & 0xff) != ELE_OK) + { + return -EIO; + } + + return 0; +} diff --git a/arch/arm/src/imxrt/imxrt118x_ele.h b/arch/arm/src/imxrt/imxrt118x_ele.h new file mode 100644 index 0000000000000..1d9b3836db275 --- /dev/null +++ b/arch/arm/src/imxrt/imxrt118x_ele.h @@ -0,0 +1,381 @@ +/**************************************************************************** + * arch/arm/src/imxrt/imxrt118x_ele.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_IMXRT_IMXRT118X_ELE_H +#define __ARCH_ARM_SRC_IMXRT_IMXRT118X_ELE_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include + +#include "hardware/rt118x/imxrt118x_ele.h" + +/**************************************************************************** + * Public Function Prototypes + ****************************************************************************/ + +#ifdef CONFIG_IMXRT_ELE_LOAD_FW +/* Embedded ELE firmware container, incbin'd directly from + * CONFIG_IMXRT_ELE_FW_PATH (see imxrt118x_ele.c). Only needed when the + * driver is responsible for handing the FW to the ELE at runtime; when + * the FW is instead packed into the boot AHAB container for the ROM to + * load automatically, this blob is not built into the image at all. + */ + +extern const uint8_t imxrt118x_ele_fw[]; +extern const uint8_t imxrt118x_ele_fw_end[]; +#endif + +/**************************************************************************** + * Name: imxrt118x_ele_init + * + * Description: + * Bring the EdgeLock Enclave up. + * + * Input Parameters: + * None + * + * Returned Value: + * None + * + ****************************************************************************/ + +void imxrt118x_ele_init(void); + +/**************************************************************************** + * Name: imxrt118x_ele_load_fw + * + * Description: + * Load the EdgeLock Enclave firmware. + * + * Input Parameters: + * fw_addr - Address of the ELE firmware container. + * + * Returned Value: + * OK on success, a negated errno value otherwise. + * + ****************************************************************************/ + +int imxrt118x_ele_load_fw(uint32_t fw_addr); + +/**************************************************************************** + * Name: imxrt118x_ele_release_rdc + * + * Description: + * Request ownership of one TRDC. + * + * Input Parameters: + * rdc_id - Packed TRDC and core identifier. + * + * Returned Value: + * OK on success, a negated errno value otherwise. + * + ****************************************************************************/ + +int imxrt118x_ele_release_rdc(uint32_t rdc_id); + +/**************************************************************************** + * Name: imxrt118x_ele_read_common_fuse + * + * Description: + * Read a common fuse value. + * + * Input Parameters: + * fuse_id - Fuse ID + * + * Returned Value: + * Fuse value. Returns zero if read failed. + * + ****************************************************************************/ + +uint32_t imxrt118x_ele_read_common_fuse(uint32_t fuse_id); + +/**************************************************************************** + * Name: imxrt118x_ele_get_key + * + * Description: + * Return HW unique key value. + * + * Input Parameters: + * key - Key buffer, must be cache line aligned + * key_size - Key size in bytes, must be 16 or 32 + * ctx - Context buffer, must be cache line aligned + * ctx_size - Context buffer size + * + * Returned Value: + * OK on success, a negated errno value otherwise. + * + ****************************************************************************/ + +int imxrt118x_ele_get_key(uint8_t *key, size_t key_size, + uint8_t *ctx, size_t ctx_size); + +/**************************************************************************** + * Name: imxrt118x_ele_get_events + * + * Description: + * Return ELE events. + * + * Input Parameters: + * buffer - Event buffer + * buffer_size - Event buffer size + * + * Returned Value: + * Zero (OK) is returned if no events. A negated errno value is returned + * on failure. Positive value is number of events read. + * + ****************************************************************************/ + +int imxrt118x_ele_get_events(uint32_t *buffer, size_t buffer_size); + +/**************************************************************************** + * Name: imxrt118x_ele_close_device + * + * Description: + * Set device to OEM close state. This operation is irreversible. + * + * Returned Value: + * OK on success, a negated errno value otherwise. + * + ****************************************************************************/ + +int imxrt118x_ele_close_device(void); + +/**************************************************************************** + * Name: imxrt118x_ele_get_lifecycle + * + * Description: + * Return the device's lifecycle value, queried from the ELE via + * GET_INFO (RT118x has no i.MX9-style FSB lifecycle register). + * + * Returned Value: + * Lifecycle value. + * + ****************************************************************************/ + +uint32_t imxrt118x_ele_get_lifecycle(void); + +/**************************************************************************** + * Name: imxrt118x_ele_auth_oem_ctnr + * + * Description: + * Authenticate container header. + * + * Input Parameters: + * ctnr_addr - Address of the container header. + * + * Output Parameters: + * response - ELE response, can be used for debugging. + * + * Returned Value: + * OK on success, a negated errno value otherwise. + * + ****************************************************************************/ + +int imxrt118x_ele_auth_oem_ctnr(unsigned long ctnr_addr, uint32_t *response); + +/**************************************************************************** + * Name: imxrt118x_ele_release_container + * + * Description: + * Release the container from the ELE, used after + * imxrt118x_ele_auth_oem_ctnr(). + * + * Output Parameters: + * response - ELE response, can be used for debugging. + * + * Returned Value: + * OK on success, a negated errno value otherwise. + * + ****************************************************************************/ + +int imxrt118x_ele_release_container(uint32_t *response); + +/**************************************************************************** + * Name: imxrt118x_ele_verify_image + * + * Description: + * Verify the specified image, for the current container. + * + * Input Parameters: + * img_id - The id of the image in the context of the current container. + * + * Output Parameters: + * response - ELE response, can be used for debugging. + * + * Returned Value: + * OK on success, a negated errno value otherwise. + * + ****************************************************************************/ + +int imxrt118x_ele_verify_image(uint32_t img_id, uint32_t *response); + +/**************************************************************************** + * Name: imxrt118x_ele_start_rng + * + * Description: + * Sends command to initialize the ELE RNG context. + * + * Returned Value: + * OK on success, a negated errno value otherwise. + * + ****************************************************************************/ + +int imxrt118x_ele_start_rng(void); + +/**************************************************************************** + * Name: imxrt118x_ele_get_trng_state + * + * Description: + * Query the state of the True Random Number Generator. + * + * Returned Value: + * Zero is returned if the Random Number Generator (RNG) is ready for + * use. A negated errno value (-EBUSY) or another is returned on + * failure. + * + ****************************************************************************/ + +int imxrt118x_ele_get_trng_state(void); + +/**************************************************************************** + * Name: imxrt118x_ele_get_random + * + * Description: + * Request from the ELE the generation of a random number of specified + * length. + * + * Input Parameters: + * paddr - 32bit physical address to store the random number. + * len - Length in bytes of the random number. + * + * Returned Value: + * Zero is returned if ELE successfully generated the random number. + * A negated errno value (-EBUSY) or another is returned on failure. + * + ****************************************************************************/ + +int imxrt118x_ele_get_random(uint32_t paddr, size_t len); + +/**************************************************************************** + * Name: imxrt118x_ele_commit + * + * Description: + * Sends commit command to the ELE. + * + * Input Parameters: + * info - Information type to be committed + * + * Output Parameters: + * response - ELE response, can be used for debugging. + * + * Returned Value: + * OK on success, a negated errno value otherwise. + * + ****************************************************************************/ + +int imxrt118x_ele_commit(uint32_t info, uint32_t *response); + +/**************************************************************************** + * Name: imxrt118x_ele_enable_apc + * + * Description: + * Enable Access Permission Control for the M7. + * + * Input Parameters: + * None + * + * Returned Value: + * OK on success, a negated errno value otherwise. + * + ****************************************************************************/ + +int imxrt118x_ele_enable_apc(void); + +/**************************************************************************** + * Name: imxrt118x_ele_voltage_change_start + * + * Description: + * Begin an ELE-guarded VDD1P0 voltage change (VOLTAGE_CHANGE_START, + * 0x12). When the digital glitch detector (GDET) is enabled, the DCDC + * target must only be reprogrammed between this command and + * imxrt118x_ele_voltage_change_finish(); otherwise the glitch detector + * can trip on the transition and put the SoC into an unpredictable + * (lockup/reset) state. While the change is in progress the ELE accepts + * no other command and aborts if FINISH is not issued within 50 ms. + * + * Input Parameters: + * None + * + * Returned Value: + * OK on success, a negated errno value otherwise. ELE firmware that + * does not implement the command simply rejects it, in which case the + * caller may proceed with the (unguarded) voltage change. + * + ****************************************************************************/ + +int imxrt118x_ele_voltage_change_start(void); + +/**************************************************************************** + * Name: imxrt118x_ele_voltage_change_finish + * + * Description: + * Complete an ELE-guarded VDD1P0 voltage change (VOLTAGE_CHANGE_FINISH, + * 0x13), removing the GDET isolation started by + * imxrt118x_ele_voltage_change_start(). Must be issued within 50 ms of + * the START command. + * + * Input Parameters: + * None + * + * Returned Value: + * OK on success, a negated errno value otherwise. + * + ****************************************************************************/ + +int imxrt118x_ele_voltage_change_finish(void); + +/**************************************************************************** + * Name: imxrt118x_ele_check_fw_version + * + * Description: + * Query the EdgeLock Enclave firmware version (GET_FW_VERSION) and log + * it, so it can be verified that the intended ELE firmware is active - + * whether it was loaded by NuttX (CONFIG_IMXRT_ELE_LOAD_FW) or by the + * ROM itself from a properly packed AHAB container. + * + * Input Parameters: + * None + * + * Returned Value: + * OK on success, a negated errno value otherwise. + * + ****************************************************************************/ + +int imxrt118x_ele_check_fw_version(void); + +#endif /* __ARCH_ARM_SRC_IMXRT_IMXRT118X_ELE_H */ diff --git a/arch/arm/src/imxrt/imxrt118x_start_cm7.c b/arch/arm/src/imxrt/imxrt118x_start_cm7.c new file mode 100644 index 0000000000000..fcb8e969326af --- /dev/null +++ b/arch/arm/src/imxrt/imxrt118x_start_cm7.c @@ -0,0 +1,236 @@ +/**************************************************************************** + * arch/arm/src/imxrt/imxrt118x_start_cm7.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include + +#include + +#include "arm_internal.h" +#include "imxrt118x_ele.h" +#include "imxrt118x_start_cm7.h" +#include "hardware/imxrt_ccm.h" +#include "hardware/rt117x/imxrt117x_dcdc.h" +#include "hardware/rt118x/imxrt118x_anadig.h" +#include "hardware/rt118x/imxrt118x_blkctrl.h" +#include "hardware/rt118x/imxrt118x_gpc.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#define CCM_M7_ROOT_CONFIG (CCM_CR_CTRL_MUX_SRCSEL(2) | \ + CCM_CR_CTRL_DIV(1)) + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: imxrt118x_pmu_enable_body_bias_fbb_cm7 + * + * Description: + * Enable forward body bias (FBB) on the LVT core logic. FBB is required + * for the M7 to reach its 800 MHz HSRUN (OverDrive) frequency + * (IMXRT1180RM Rev. 10 sec. 2.1.3). + * + * Follows the "PMU Well Bias Enable Sequence" of RM sec. 24.3.2.3.3.2. + * FBB is implemented in the Cortex-M7 platform only (RM sec. 19.3.3), + * and the second step turns on the CM7 well-bias power switch, so this + * belongs to the M7 release path rather than to generic clock setup. + * The RM requires VDD_SOC_IN and VDD_AON_ANA to be settled beforehand; + * imxrt_clockconfig() has already raised VDD1P0 to 1.125 V by this + * point. + * + ****************************************************************************/ + +static int imxrt118x_pmu_enable_body_bias_fbb_cm7(void) +{ + int timeout; + uint32_t regval; + + /* Step 1/2: configure the well bias. */ + + regval = getreg32(IMXRT_ANADIG_PMU_BIAS_CTRL); + regval &= ~(ANADIG_PMU_BIAS_CTRL_WB_NW_LVL_1P8_MASK | + ANADIG_PMU_BIAS_CTRL_WB_PW_LVL_1P8_MASK | + ANADIG_PMU_BIAS_CTRL_WB_CFG_1P8_MASK); + regval |= ANADIG_PMU_BIAS_CTRL_WB_CFG_1P8(ANADIG_PMU_WB_CFG_NWELL_FBB | + ANADIG_PMU_WB_CFG_PULLDOWN_EN | + ANADIG_PMU_WB_CFG_AREA( + ANADIG_PMU_WB_AREA_90UA) | + ANADIG_PMU_WB_CFG_ADAPTIVE_DIS | + ANADIG_PMU_WB_CFG_OSC( + ANADIG_PMU_WB_OSC_FULL)) | + ANADIG_PMU_BIAS_CTRL_WB_NW_LVL_1P8(1) | + ANADIG_PMU_BIAS_CTRL_WB_PW_LVL_1P8(1); + putreg32(regval, IMXRT_ANADIG_PMU_BIAS_CTRL); + + /* Step 3: turn on the CM7 FBB switch and the well-bias regulator. */ + + regval = getreg32(IMXRT_ANADIG_PMU_BIAS_CTRL2); + regval |= ANADIG_PMU_BIAS_CTRL2_WB_EN | + ANADIG_PMU_BIAS_CTRL2_WB_PWR_SW_EN_1P8; + putreg32(regval, IMXRT_ANADIG_PMU_BIAS_CTRL2); + + /* Step 4: wait for the well bias to stabilise. */ + + for (timeout = 10000; timeout != 0; timeout--) + { + if ((getreg32(IMXRT_ANADIG_PMU_BIAS_CTRL2) & + ANADIG_PMU_BIAS_CTRL2_WB_OK) != 0) + { + return 0; + } + + up_udelay(1); + } + + syslog(LOG_ERR, "bootloader: FBB not stable (BIAS_CTRL2=0x%08" PRIx32 + ")\n", getreg32(IMXRT_ANADIG_PMU_BIAS_CTRL2)); + return -ETIMEDOUT; +} + +/**************************************************************************** + * Name: prepare_m7_power + ****************************************************************************/ + +static int prepare_m7_power(void) +{ + uint32_t rootctrl; + + /* Forward body bias is required for HSRUN (IMXRT1180RM Rev. 10 + * Table 128). + */ + + if (imxrt118x_pmu_enable_body_bias_fbb_cm7() < 0) + { + return -ETIMEDOUT; + } + + /* Stop root0 before selecting ARM_PLL / 1. Keep it stopped until the + * status register reflects the requested mux and divider, then restart + * it and wait for the transition to complete. + */ + + putreg32(CCM_CR_CTRL_OFF, IMXRT_CCM_CR_CTRL_SET(CCM_CR_M7)); + + while ((getreg32(IMXRT_CCM_CR_STAT0(CCM_CR_M7)) & + (CCM_CR_STAT0_OFF | CCM_CR_STAT0_CHANGING)) != CCM_CR_STAT0_OFF); + + rootctrl = getreg32(IMXRT_CCM_CR_CTRL(CCM_CR_M7)); + rootctrl &= ~(CCM_CR_CTRL_MUX_MASK | CCM_CR_CTRL_DIV_MASK); + rootctrl |= CCM_M7_ROOT_CONFIG; + putreg32(rootctrl, IMXRT_CCM_CR_CTRL(CCM_CR_M7)); + + while ((getreg32(IMXRT_CCM_CR_STAT0(CCM_CR_M7)) & + (CCM_CR_STAT0_MUX_MASK | CCM_CR_STAT0_DIV_MASK | + CCM_CR_STAT0_OFF | CCM_CR_STAT0_CHANGING)) != + (CCM_M7_ROOT_CONFIG | CCM_CR_STAT0_OFF)); + + putreg32(CCM_CR_CTRL_OFF, IMXRT_CCM_CR_CTRL_CLR(CCM_CR_M7)); + + while (getreg32(IMXRT_CCM_CR_STAT0(CCM_CR_M7)) & + (CCM_CR_STAT0_OFF | CCM_CR_STAT0_CHANGING)); + + putreg32(DCDC_REG3_REG_FBK_SEL(2) | + DCDC_REG3_DISABLE_IDLE_SKIP | + DCDC_REG3_DISABLE_PULSE_SKIP, + IMXRT_DCDC_REG3); + + return 0; +} + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: imxrt118x_release_cm7 + ****************************************************************************/ + +int imxrt118x_release_cm7(uintptr_t vtor) +{ + uint32_t cfg; + int ret; + + /* Prepare the M7 power domain and core clock root. ARM_PLL is configured + * by the M33's imxrt_clockconfig(). + */ + + if (prepare_m7_power() < 0) + { + return -ETIMEDOUT; + } + + /* Keep the M7 platform in RUN during WFI so core exceptions such as + * SysTick can wake it without requiring a GPC wakeup source. This is + * done before reset release because the bootloader owns the M7 power + * setup. + */ + + modifyreg32(IMXRT_GPC_CM7_MODE_CTRL, + GPC_CM_MODE_CTRL_TARGET_MASK, + GPC_CM_MODE_CTRL_TARGET(GPC_CM_MODE_TARGET_RUN)); + modifyreg32(IMXRT_GPC_CM_MISC(1), + GPC_CM_MISC_SLEEP_HOLD_EN, 0); + + /* Program the M7 initial VTOR and force its clocks on. */ + + cfg = getreg32(IMXRT_AON_M7_CFG); + cfg = (cfg & ~AON_M7_CFG_INITVTOR_MASK) | + AON_M7_CFG_INITVTOR(vtor >> AON_M7_CFG_INITVTOR_SHIFT) | + AON_M7_CFG_HCLK_FORCE_ON | + AON_M7_CFG_CORECLK_FORCE_ON; + putreg32(cfg, IMXRT_AON_M7_CFG); + + /* Release the M7 from reset (write-once). */ + + putreg32(getreg32(IMXRT_SRC_SCR) | SRC_SCR_BT_RELEASE_M7, IMXRT_SRC_SCR); + + /* Ask ELE to release the M7. */ + + ret = imxrt118x_ele_enable_apc(); + if (ret < 0) + { + return ret; + } + + /* Kick the M7 by toggling its clock around WAIT deassertion. + */ + + putreg32(0, IMXRT_CCM_LPCG_DIR(0)); + + putreg32(getreg32(IMXRT_AON_M7_CFG) & ~AON_M7_CFG_WAIT, IMXRT_AON_M7_CFG); + + putreg32(CCM_LPCG_DIR_ON, IMXRT_CCM_LPCG_DIR(0)); + + return 0; +} diff --git a/arch/arm/src/imxrt/imxrt118x_start_cm7.h b/arch/arm/src/imxrt/imxrt118x_start_cm7.h new file mode 100644 index 0000000000000..c5edc4ae369ae --- /dev/null +++ b/arch/arm/src/imxrt/imxrt118x_start_cm7.h @@ -0,0 +1,40 @@ +/**************************************************************************** + * arch/arm/src/imxrt/imxrt118x_start_cm7.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_IMXRT_IMXRT118X_START_CM7_H +#define __ARCH_ARM_SRC_IMXRT_IMXRT118X_START_CM7_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include + +/**************************************************************************** + * Public Function Prototypes + ****************************************************************************/ + +int imxrt118x_release_cm7(uintptr_t vtor); + +#endif /* __ARCH_ARM_SRC_IMXRT_IMXRT118X_START_CM7_H */ diff --git a/arch/arm/src/imxrt/imxrt118x_trdc.c b/arch/arm/src/imxrt/imxrt118x_trdc.c new file mode 100644 index 0000000000000..d19589544311c --- /dev/null +++ b/arch/arm/src/imxrt/imxrt118x_trdc.c @@ -0,0 +1,696 @@ +/**************************************************************************** + * arch/arm/src/imxrt/imxrt118x_trdc.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include +#include +#include +#include +#include + +#include + +#include "chip.h" +#include "arm_internal.h" +#include "imxrt118x_ele.h" +#include "imxrt118x_trdc.h" +#include + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#define mmio_read_32(c) getreg32(c) +#define mmio_write_32(c, v) putreg32(v, c) +#define mmio_clrbits_32(addr, clear) modifyreg32(addr, clear, 0) +#define mmio_setbits_32(addr, set) modifyreg32(addr, 0, set) +#define mmio_clrsetbits_32(addr, clear, set) modifyreg32(addr, clear, set) + +/* Packed ELE TRDC release IDs. The ELE RELEASE_RDC payload is + * (RdcID << 8) | CoreID, so parameterize by target core ID + * (ELE_CORE_CM33_ID or ELE_CORE_CM7_ID). + */ + +#define TRDC_AON(core) ((ELE_TRDC_AON_ID << 8) | ((core) & 0xff)) +#define TRDC_WAKEUP(core) ((ELE_TRDC_WAKEUP_ID << 8) | ((core) & 0xff)) +#define TRDC_MEDIA(core) ((ELE_TRDC_MEGA_ID << 8) | ((core) & 0xff)) + +#define VERBOSE _none + +/**************************************************************************** + * Private Types + ****************************************************************************/ + +struct mbc_mem_dom +{ + uint32_t mem_glbcfg[4]; + uint32_t nse_blk_index; + uint32_t nse_blk_set; + uint32_t nse_blk_clr; + uint32_t nsr_blk_clr_all; + uint32_t memn_glbac[8]; + + /* The upper only existed in the beginning of each MBC */ + + uint32_t mem0_blk_cfg_w[64]; + uint32_t mem0_blk_nse_w[16]; + uint32_t mem1_blk_cfg_w[8]; + uint32_t mem1_blk_nse_w[2]; + uint32_t mem2_blk_cfg_w[8]; + uint32_t mem2_blk_nse_w[2]; + uint32_t mem3_blk_cfg_w[8]; + uint32_t mem3_blk_nse_w[2]; /* 0x1F0, 0x1F4 */ + uint32_t reserved[2]; +}; + +struct mrc_rgn_dom +{ + uint32_t mrc_glbcfg[4]; + uint32_t nse_rgn_indirect; + uint32_t nse_rgn_set; + uint32_t nse_rgn_clr; + uint32_t nse_rgn_clr_all; + uint32_t memn_glbac[8]; + + /* The upper only existed in the beginning of each MRC */ + + uint32_t rgn_desc_words[16][2]; /* 16 regions at max, 2 words per region */ + uint32_t rgn_nse; + uint32_t reserved2[15]; +}; + +struct mda_inst +{ + uint32_t mda_w[8]; +}; + +struct trdc_mgr +{ + uint32_t trdc_cr; + uint32_t res0[59]; + uint32_t trdc_hwcfg0; + uint32_t trdc_hwcfg1; + uint32_t res1[450]; + struct mda_inst mda[8]; + uint32_t res2[15808]; +}; + +struct trdc_mbc +{ + struct mbc_mem_dom mem_dom[DID_NUM]; +}; + +struct trdc_mrc +{ + struct mrc_rgn_dom mrc_dom[DID_NUM]; +}; + +struct trdc_mgr_info +{ + unsigned long trdc_base; + uint8_t mbc_id; + uint8_t mbc_mem_id; + uint8_t blk_mgr; + uint8_t blk_mc; +}; + +struct trdc_config_info +{ + unsigned long trdc_base; + struct trdc_glbac_config *mbc_glbac; + uint32_t num_mbc_glbac; + struct trdc_mbc_config *mbc_cfg; + uint32_t num_mbc_cfg; + struct trdc_glbac_config *mrc_glbac; + uint32_t num_mrc_glbac; + struct trdc_mrc_config *mrc_cfg; + uint32_t num_mrc_cfg; +}; + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/* Protect each TRDC's own manager/controller register blocks. */ + +static const struct trdc_mgr_info g_trdc_mgr_blks[] = +{ + { IMXRT_TRDC1_BASE, 0, 0, 39, 40 }, /* TRDC1 (AON) */ + { IMXRT_TRDC2_BASE, 0, 0, 70, 71 }, /* TRDC2 (WAKEUP) */ + { IMXRT_TRDC2_BASE, 1, 0, 1, 2 }, /* TRDC3 via TRDC2 MBC1 */ +}; + +static const struct trdc_config_info g_trdc_cfg_info[] = +{ + { + IMXRT_TRDC1_BASE, + trdc_a_mbc_glbac, nitems(trdc_a_mbc_glbac), + trdc_a_mbc, nitems(trdc_a_mbc), + trdc_a_mrc_glbac, nitems(trdc_a_mrc_glbac), + trdc_a_mrc, nitems(trdc_a_mrc) + }, /* TRDC1 (AON) */ + { + IMXRT_TRDC2_BASE, + trdc_w_mbc_glbac, nitems(trdc_w_mbc_glbac), + trdc_w_mbc, nitems(trdc_w_mbc), + trdc_w_mrc_glbac, nitems(trdc_w_mrc_glbac), + trdc_w_mrc, nitems(trdc_w_mrc) + }, /* TRDC2 (WAKEUP / MEGA) */ +}; + +/**************************************************************************** + * Private Function Prototypes + ****************************************************************************/ + +static int trdc_mda_set_noncpu(unsigned long trdc_reg, uint32_t mda_inst, + uint32_t mda_reg, bool did_bypass, uint8_t sa, + uint8_t pa, uint8_t did, bool lock) +{ + struct trdc_mgr *trdc_base = (struct trdc_mgr *)trdc_reg; + uint32_t *mda_w = &trdc_base->mda[mda_inst].mda_w[mda_reg]; + uint32_t val = mmio_read_32((uintptr_t)mda_w); + + if (!(val & BIT(29))) /* cpu */ + return -EINVAL; + + val = BIT(31) | ((sa & 0x3) << 6) | ((pa & 0x3) << 4) | (did & 0xf); + if (did_bypass) + val |= BIT(8); + + mmio_write_32((uintptr_t)mda_w, val); + + if (lock) + mmio_write_32((uintptr_t)mda_w, val | BIT(30)); + + return 0; +} + +static int trdc_mda_set_cpu(unsigned long trdc_reg, uint32_t mda_inst, + uint32_t mda_reg, uint8_t did_sel, uint8_t sa, uint8_t did, bool lock) +{ + struct trdc_mgr *trdc_base = (struct trdc_mgr *)trdc_reg; + uint32_t *mda_w = &trdc_base->mda[mda_inst].mda_w[mda_reg]; + uint32_t val = mmio_read_32((uintptr_t)mda_w); + + if (val & BIT(29)) /* non-cpu */ + return -EINVAL; + + val = BIT(31) | ((sa & 0x3) << 14) | ((did_sel & 0x3) << 4) | + (did & 0xf); + + mmio_write_32((uintptr_t)mda_w, val); + + if (lock) + mmio_write_32((uintptr_t)mda_w, val | BIT(30)); + + return 0; +} + +static unsigned long trdc_get_mbc_base(unsigned long trdc_reg, + uint32_t mbc_x) +{ + struct trdc_mgr *trdc_base = (struct trdc_mgr *)trdc_reg; + uint32_t mbc_num = MBC_NUM(trdc_base->trdc_hwcfg0); + + if (mbc_x >= mbc_num) + return 0; + + return trdc_reg + 0x10000 + 0x2000 * mbc_x; +} + +static unsigned long trdc_get_mrc_base(unsigned long trdc_reg, + uint32_t mrc_x) +{ + struct trdc_mgr *trdc_base = (struct trdc_mgr *)trdc_reg; + uint32_t mbc_num = MBC_NUM(trdc_base->trdc_hwcfg0); + uint32_t mrc_num = MRC_NUM(trdc_base->trdc_hwcfg0); + + if (mrc_x >= mrc_num) + return 0; + + return trdc_reg + 0x10000 + 0x2000 * mbc_num + 0x1000 * mrc_x; +} + +static uint32_t trdc_mbc_blk_num(unsigned long trdc_reg, uint32_t mbc_x, + uint32_t mem_x) +{ + struct trdc_mbc *mbc_base = + (struct trdc_mbc *)trdc_get_mbc_base(trdc_reg, mbc_x); + struct mbc_mem_dom *mbc_dom; + uint32_t glbcfg; + + if (mbc_base == 0) + return 0; + + /* only first dom has the glbcfg */ + + mbc_dom = &mbc_base->mem_dom[0]; + glbcfg = mmio_read_32((uintptr_t)&mbc_dom->mem_glbcfg[mem_x]); + + return MBC_BLK_NUM(glbcfg); +} + +static int trdc_mbc_set_control(unsigned long trdc_reg, uint32_t mbc_x, + uint32_t glbac_id, uint32_t glbac_val) +{ + struct trdc_mbc *mbc_base = + (struct trdc_mbc *)trdc_get_mbc_base(trdc_reg, mbc_x); + struct mbc_mem_dom *mbc_dom; + uint32_t i; + + if (mbc_base == 0 || glbac_id >= 8) + return -EINVAL; + + /* Skip glbac7 used for TRDC MGR protection */ + + if (glbac_id == 7 && glbac_val != 0x6000) + { + for (i = 0; i < nitems(g_trdc_mgr_blks); i++) + { + if (trdc_reg == g_trdc_mgr_blks[i].trdc_base + && mbc_x == g_trdc_mgr_blks[i].mbc_id) + { + return -EPERM; + } + } + } + + /* Skip glbac6 used for fused module */ + + if (glbac_id == 6 && glbac_val != 0) + return -EPERM; + + /* only first dom has the glbac */ + + mbc_dom = &mbc_base->mem_dom[0]; + + mmio_write_32((uintptr_t)&mbc_dom->memn_glbac[glbac_id], glbac_val); + + return 0; +} + +static int trdc_mbc_blk_config(unsigned long trdc_reg, uint32_t mbc_x, + uint32_t dom_x, uint32_t mem_x, uint32_t blk_x, + bool sec_access, uint32_t glbac_id) +{ + struct trdc_mbc *mbc_base = + (struct trdc_mbc *)trdc_get_mbc_base(trdc_reg, mbc_x); + struct mbc_mem_dom *mbc_dom; + uint32_t *cfg_w; + uint32_t index; + uint32_t offset; + uint32_t val; + + if (mbc_base == 0 || glbac_id >= 8) + return -EINVAL; + + mbc_dom = &mbc_base->mem_dom[dom_x]; + + switch (mem_x) + { + case 0: + cfg_w = &mbc_dom->mem0_blk_cfg_w[blk_x / 8]; + break; + case 1: + cfg_w = &mbc_dom->mem1_blk_cfg_w[blk_x / 8]; + break; + case 2: + cfg_w = &mbc_dom->mem2_blk_cfg_w[blk_x / 8]; + break; + case 3: + cfg_w = &mbc_dom->mem3_blk_cfg_w[blk_x / 8]; + break; + default: + return -1; + }; + + index = blk_x % 8; + offset = index * 4; + + val = mmio_read_32((uintptr_t)cfg_w); + val &= ~(0xfu << offset); + + if (sec_access) + { + val |= ((0x0 | (glbac_id & 0x7)) << offset); + mmio_write_32((uintptr_t)cfg_w, val); + } + else + { + val |= ((0x8 | (glbac_id & 0x7)) << offset); /* nse bit set */ + mmio_write_32((uintptr_t)cfg_w, val); + } + + return 0; +} + +static int trdc_mrc_set_control(unsigned long trdc_reg, uint32_t mrc_x, + uint32_t glbac_id, uint32_t glbac_val) +{ + struct trdc_mrc *mrc_base = + (struct trdc_mrc *)trdc_get_mrc_base(trdc_reg, mrc_x); + struct mrc_rgn_dom *mrc_dom; + + if (mrc_base == 0 || glbac_id >= 8) + return -EINVAL; + + /* only first dom has the glbac */ + + mrc_dom = &mrc_base->mrc_dom[0]; + + mmio_write_32((uintptr_t)&mrc_dom->memn_glbac[glbac_id], glbac_val); + + return 0; +} + +static int trdc_mrc_rgn_config(unsigned long trdc_reg, + uint32_t mrc_x, uint32_t dom_x, uint32_t rgn_id, + uint32_t addr_start, uint32_t addr_size, + bool sec_access, uint32_t glbac_id) +{ + struct trdc_mrc *mrc_base = + (struct trdc_mrc *)trdc_get_mrc_base(trdc_reg, mrc_x); + struct mrc_rgn_dom *mrc_dom; + uint32_t *desc_w; + uint32_t addr_end; + + if (mrc_base == 0 || glbac_id >= 8 || rgn_id >= 16) + return -EINVAL; + + mrc_dom = &mrc_base->mrc_dom[dom_x]; + + addr_end = addr_start + addr_size - 1; + addr_start &= ~0x3fff; + addr_end &= ~0x3fff; + + desc_w = &mrc_dom->rgn_desc_words[rgn_id][0]; + + if (sec_access) + { + mmio_write_32((uintptr_t)desc_w, addr_start | (glbac_id & 0x7)); + mmio_write_32((uintptr_t)(desc_w + 1), addr_end | 0x1); + } + else + { + mmio_write_32((uintptr_t)desc_w, addr_start | (glbac_id & 0x7)); + mmio_write_32((uintptr_t)(desc_w + 1), (addr_end | 0x1 | 0x10)); + } + return 0; +} + +static bool trdc_mrc_enabled(unsigned long trdc_base) +{ + return (!!(mmio_read_32(trdc_base) & 0x8000)); +} + +static bool trdc_mbc_enabled(unsigned long trdc_base) +{ + return (!!(mmio_read_32(trdc_base) & 0x4000)); +} + +static bool is_trdc_mgr_slot(unsigned long trdc_base, + uint8_t mbc_id, uint8_t mem_id, uint16_t blk_id) +{ + uint32_t i; + + for (i = 0; i < nitems(g_trdc_mgr_blks); i++) + { + if (g_trdc_mgr_blks[i].trdc_base == trdc_base) + { + if (mbc_id == g_trdc_mgr_blks[i].mbc_id + && mem_id == g_trdc_mgr_blks[i].mbc_mem_id + && (blk_id == g_trdc_mgr_blks[i].blk_mgr + || blk_id == g_trdc_mgr_blks[i].blk_mc)) + return true; + } + } + return false; +} + +static void trdc_mgr_mbc_setup(const struct trdc_mgr_info *mgr) +{ + uint32_t i; + + if (trdc_mbc_enabled(mgr->trdc_base)) + { + trdc_mbc_set_control(mgr->trdc_base, mgr->mbc_id, 7, 0x6000); /* ONLY secure privilege can access */ + for (i = 0; i < 16; i++) + { + trdc_mbc_blk_config(mgr->trdc_base, mgr->mbc_id, + i, mgr->mbc_mem_id, mgr->blk_mgr, true, 7); + trdc_mbc_blk_config(mgr->trdc_base, mgr->mbc_id, + i, mgr->mbc_mem_id, mgr->blk_mc, true, 7); + } + + /* Lock the TRDC manager policy. */ + + trdc_mbc_set_control(mgr->trdc_base, mgr->mbc_id, + 7, GLBAC_LOCK_MASK | 0x6000); + } +} + +static void trdc_setup(const struct trdc_config_info *cfg) +{ + int i; + int j; + uint32_t num; + bool is_mgr; + + if (trdc_mrc_enabled(cfg->trdc_base)) + { + for (i = 0; i < cfg->num_mrc_glbac; i++) + { + trdc_mrc_set_control(cfg->trdc_base, cfg->mrc_glbac[i].mbc_mrc_id, + cfg->mrc_glbac[i].glbac_id, + cfg->mrc_glbac[i].glbac_val & GLBAC_SETTING_MASK); + } + + for (i = 0; i < cfg->num_mrc_cfg; i++) + { + trdc_mrc_rgn_config(cfg->trdc_base, + cfg->mrc_cfg[i].mrc_id, cfg->mrc_cfg[i].dom_id, + cfg->mrc_cfg[i].region_id, cfg->mrc_cfg[i].region_start, + cfg->mrc_cfg[i].region_size, cfg->mrc_cfg[i].secure, + cfg->mrc_cfg[i].glbac_id); + } + } + + if (trdc_mbc_enabled(cfg->trdc_base)) + { + for (i = 0; i < cfg->num_mbc_glbac; i++) + { + trdc_mbc_set_control(cfg->trdc_base, cfg->mbc_glbac[i].mbc_mrc_id, + cfg->mbc_glbac[i].glbac_id, + cfg->mbc_glbac[i].glbac_val & GLBAC_SETTING_MASK); + } + + for (i = 0; i < cfg->num_mbc_cfg; i++) + { + if (cfg->mbc_cfg[i].blk_id == MBC_BLK_ALL) + { + num = trdc_mbc_blk_num(cfg->trdc_base, cfg->mbc_cfg[i].mbc_id, + cfg->mbc_cfg[i].mem_id); + + for (j = 0; j < num; j++) + { + /* Skip the protected TRDC blocks. */ + + is_mgr = is_trdc_mgr_slot(cfg->trdc_base, + cfg->mbc_cfg[i].mbc_id, cfg->mbc_cfg[i].mem_id, j); + if (is_mgr) + continue; + + trdc_mbc_blk_config(cfg->trdc_base, cfg->mbc_cfg[i].mbc_id, + cfg->mbc_cfg[i].dom_id, + cfg->mbc_cfg[i].mem_id, j, cfg->mbc_cfg[i].secure, + cfg->mbc_cfg[i].glbac_id); + } + } + else + { + trdc_mbc_blk_config(cfg->trdc_base, cfg->mbc_cfg[i].mbc_id, + cfg->mbc_cfg[i].dom_id, cfg->mbc_cfg[i].mem_id, + cfg->mbc_cfg[i].blk_id, cfg->mbc_cfg[i].secure, + cfg->mbc_cfg[i].glbac_id); + } + } + } +} + +static void trdc_try_lockup(const struct trdc_config_info *cfg) +{ + uint32_t i; + + if (trdc_mrc_enabled(cfg->trdc_base)) + { + for (i = 0; i < cfg->num_mrc_glbac; i++) + { + trdc_mrc_set_control(cfg->trdc_base, + cfg->mrc_glbac[i].mbc_mrc_id, + cfg->mrc_glbac[i].glbac_id, + cfg->mrc_glbac[i].glbac_val + & (GLBAC_SETTING_MASK | GLBAC_LOCK_MASK)); + } + } + + if (trdc_mbc_enabled(cfg->trdc_base)) + { + for (i = 0; i < cfg->num_mbc_glbac; i++) + { + trdc_mbc_set_control(cfg->trdc_base, cfg->mbc_glbac[i].mbc_mrc_id, + cfg->mbc_glbac[i].glbac_id, + cfg->mbc_glbac[i].glbac_val + & (GLBAC_SETTING_MASK | GLBAC_LOCK_MASK)); + } + } +} + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +void imxrt118x_trdc_config(void) +{ + int i; + + /* Assign GPIO2..GPIO6 to non-secure access. */ + + mmio_write_32(IMXRT_GPIO2_BASE + 0x10, 0xffffffff); + mmio_write_32(IMXRT_GPIO2_BASE + 0x14, 0x3); + mmio_write_32(IMXRT_GPIO2_BASE + 0x18, 0xffffffff); + mmio_write_32(IMXRT_GPIO2_BASE + 0x1c, 0x3); + + mmio_write_32(IMXRT_GPIO3_BASE + 0x10, 0xffffffff); + mmio_write_32(IMXRT_GPIO3_BASE + 0x14, 0x3); + mmio_write_32(IMXRT_GPIO3_BASE + 0x18, 0xffffffff); + mmio_write_32(IMXRT_GPIO3_BASE + 0x1c, 0x3); + + mmio_write_32(IMXRT_GPIO4_BASE + 0x10, 0xffffffff); + mmio_write_32(IMXRT_GPIO4_BASE + 0x14, 0x3); + mmio_write_32(IMXRT_GPIO4_BASE + 0x18, 0xffffffff); + mmio_write_32(IMXRT_GPIO4_BASE + 0x1c, 0x3); + + mmio_write_32(IMXRT_GPIO5_BASE + 0x10, 0xffffffff); + mmio_write_32(IMXRT_GPIO5_BASE + 0x14, 0x3); + mmio_write_32(IMXRT_GPIO5_BASE + 0x18, 0xffffffff); + mmio_write_32(IMXRT_GPIO5_BASE + 0x1c, 0x3); + + mmio_write_32(IMXRT_GPIO6_BASE + 0x10, 0xffffffff); + mmio_write_32(IMXRT_GPIO6_BASE + 0x14, 0x3); + mmio_write_32(IMXRT_GPIO6_BASE + 0x18, 0xffffffff); + mmio_write_32(IMXRT_GPIO6_BASE + 0x1c, 0x3); + + /* Apply common DAC setup. */ + + trdc_mda_set_cpu(IMXRT_TRDC1_BASE, 1, 0, TRDC_MDA_DID_FROM_INPUT, + TRDC_MDA_FORCE_SECURE, DID_CM33, false); /* MDAC_A1 CM33 */ + trdc_mda_set_noncpu(IMXRT_TRDC1_BASE, 2, 0, true, + TRDC_MDA_FORCE_SECURE, TRDC_MDA_FORCE_PRIVILEGE, DID_EDMA3, false); + + trdc_mda_set_cpu(IMXRT_TRDC2_BASE, 0, 0, TRDC_MDA_DID_FROM_INPUT, + TRDC_MDA_FORCE_SECURE, DID_CM7, false); /* MDAC_W0 CM7 AHBP */ + trdc_mda_set_cpu(IMXRT_TRDC2_BASE, 1, 0, TRDC_MDA_DID_FROM_INPUT, + TRDC_MDA_FORCE_SECURE, DID_CM7, false); /* MDAC_W1 CM7 AXI */ + trdc_mda_set_noncpu(IMXRT_TRDC2_BASE, 2, 0, true, + TRDC_MDA_FORCE_SECURE, TRDC_MDA_FORCE_PRIVILEGE, DID_DAP, false); + trdc_mda_set_noncpu(IMXRT_TRDC2_BASE, 3, 0, true, + TRDC_MDA_FORCE_SECURE, TRDC_MDA_FORCE_PRIVILEGE, DID_CORESIGHT, false); + trdc_mda_set_noncpu(IMXRT_TRDC2_BASE, 4, 0, true, + TRDC_MDA_FORCE_SECURE, TRDC_MDA_FORCE_PRIVILEGE, DID_EDMA4, false); + trdc_mda_set_cpu(IMXRT_TRDC2_BASE, 5, 0, TRDC_MDA_DID_FROM_INPUT, + TRDC_MDA_FORCE_SECURE, DID_NETC, false); /* MDAC_W5 NETC */ + + trdc_mda_set_noncpu(IMXRT_TRDC3_BASE, 0, 0, true, + TRDC_MDA_FORCE_SECURE, TRDC_MDA_FORCE_PRIVILEGE, DID_USDHC1, false); + trdc_mda_set_noncpu(IMXRT_TRDC3_BASE, 1, 0, true, + TRDC_MDA_FORCE_SECURE, TRDC_MDA_FORCE_PRIVILEGE, DID_USDHC2, false); + trdc_mda_set_noncpu(IMXRT_TRDC3_BASE, 3, 0, true, + TRDC_MDA_FORCE_SECURE, TRDC_MDA_FORCE_PRIVILEGE, DID_USB, false); + trdc_mda_set_noncpu(IMXRT_TRDC3_BASE, 4, 0, true, + TRDC_MDA_FORCE_SECURE, TRDC_MDA_FORCE_PRIVILEGE, DID_FLEXSPI_FLR, false); + + /* Protect TRDC manager slots. */ + + for (i = 0; i < nitems(g_trdc_mgr_blks); i++) + { + trdc_mgr_mbc_setup(&g_trdc_mgr_blks[i]); + } + + /* Apply board TRDC settings. */ + + for (i = 0; i < nitems(g_trdc_cfg_info); i++) + { + trdc_setup(&g_trdc_cfg_info[i]); + } + + /* Lock board TRDC settings where requested. */ + + for (i = 0; i < nitems(g_trdc_cfg_info); i++) + { + trdc_try_lockup(&g_trdc_cfg_info[i]); + } +} + +/**************************************************************************** + * Name: imxrt118x_trdc_init + * + * Description: + * Request ownership of the TRDCs. + * + * Input Parameters: + * None + * + * Returned Value: + * Zero (OK) on success, a negated error value otherwise + * + ****************************************************************************/ + +int imxrt118x_trdc_init(void) +{ + int ret; + + /* TRDC ordering constraint (see the TRDC_*() macros above): all cores' + * AON and MEGA must be released before any core's WAKEUP. + */ + + ret = imxrt118x_ele_release_rdc(TRDC_AON(ELE_CORE_CM33_ID)); + ret |= imxrt118x_ele_release_rdc(TRDC_AON(ELE_CORE_CM7_ID)); + ret |= imxrt118x_ele_release_rdc(TRDC_MEDIA(ELE_CORE_CM33_ID)); + ret |= imxrt118x_ele_release_rdc(TRDC_MEDIA(ELE_CORE_CM7_ID)); + ret |= imxrt118x_ele_release_rdc(TRDC_WAKEUP(ELE_CORE_CM33_ID)); + ret |= imxrt118x_ele_release_rdc(TRDC_WAKEUP(ELE_CORE_CM7_ID)); + + if (ret != 0) + { + return ret; + } + + return 0; +} diff --git a/arch/arm/src/imxrt/imxrt118x_trdc.h b/arch/arm/src/imxrt/imxrt118x_trdc.h new file mode 100644 index 0000000000000..7edc7e47edb9b --- /dev/null +++ b/arch/arm/src/imxrt/imxrt118x_trdc.h @@ -0,0 +1,108 @@ +/**************************************************************************** + * arch/arm/src/imxrt/imxrt118x_trdc.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ +#ifndef __ARCH_ARM_SRC_IMXRT_IMXRT118X_TRDC_H +#define __ARCH_ARM_SRC_IMXRT_IMXRT118X_TRDC_H +/**************************************************************************** + * Included Files + ****************************************************************************/ +#include +#include +#include "hardware/rt118x/imxrt118x_trdc.h" + +/**************************************************************************** + * Public Function Prototypes + ****************************************************************************/ +#define MBC_BLK_ALL 255 +#define MRC_REG_ALL 16 + +/* TRDC MDA attribute encodings. */ + +#define TRDC_MDA_DID_FROM_MDA 0 +#define TRDC_MDA_DID_FROM_INPUT 1 +#define TRDC_MDA_FORCE_SECURE 0 +#define TRDC_MDA_FORCE_NONSECURE 1 +#define TRDC_MDA_USE_MASTER_SECURE 2 +#define TRDC_MDA_FORCE_USER 0 +#define TRDC_MDA_FORCE_PRIVILEGE 1 +#define TRDC_MDA_USE_MASTER_PRIV 2 + +struct trdc_glbac_config +{ + uint8_t mbc_mrc_id; + uint8_t glbac_id; + uint32_t glbac_val; +}; + +struct trdc_mbc_config +{ + uint8_t mbc_id; + uint8_t dom_id; + uint8_t mem_id; + uint8_t blk_id; + uint8_t glbac_id; + bool secure; +}; + +struct trdc_mrc_config +{ + uint8_t mrc_id; + uint8_t dom_id; + uint8_t region_id; + uint32_t region_start; + uint32_t region_size; + uint8_t glbac_id; + bool secure; +}; + +/**************************************************************************** + * Name: imxrt118x_trdc_config + * + * Description: + * Configure TRDC resource access. + * + * Input Parameters: + * None + * + * Returned Value: + * None + * + ****************************************************************************/ + +void imxrt118x_trdc_config(void); + +/**************************************************************************** + * Name: imxrt118x_trdc_init + * + * Description: + * Take ownership of the TRDCs. + * + * Input Parameters: + * None + * + * Returned Value: + * OK on success, a negated error value otherwise + * + ****************************************************************************/ + +int imxrt118x_trdc_init(void); + +#endif /* __ARCH_ARM_SRC_IMXRT_IMXRT118X_TRDC_H */ \ No newline at end of file diff --git a/arch/arm/src/imxrt/imxrt_allocateheap.c b/arch/arm/src/imxrt/imxrt_allocateheap.c index 8ad9ed5a4b945..b6a040cfaf513 100644 --- a/arch/arm/src/imxrt/imxrt_allocateheap.c +++ b/arch/arm/src/imxrt/imxrt_allocateheap.c @@ -159,16 +159,23 @@ # define IMXRT_DTCM 0 #endif -#ifndef IMXRT_OCRAM_SIZE - -extern const uint32_t _ram_size[]; /* See linker script */ +extern const uint32_t _ram_size[]; /* See linker script */ +#ifndef IMXRT_OCRAM_SIZE # define IMXRT_OCRAM_SIZE ((uint32_t)_ram_size) #endif #define FLEXRAM_REMAINING_K ((IMXRT_OCRAM_SIZE / 1024) - (CONFIG_IMXRT_DTCM + CONFIG_IMXRT_DTCM)) -#if defined(CONFIG_IMXRT_OCRAM_PRIMARY) +#if defined(CONFIG_IMXRT_TCM_PRIMARY) +/* Place the primary heap in the core-local TCM. Both cores alias their + * TCM at IMXRT_DTCM_BASE (M7 DTCM in the M7 view, M33 SysTCM in the M33 + * view); the size is picked up from the linker script's _ram_size. + */ + +# define PRIMARY_RAM_START IMXRT_DTCM_BASE +# define PRIMARY_RAM_SIZE ((uint32_t)_ram_size) +#elif defined(CONFIG_IMXRT_OCRAM_PRIMARY) # define PRIMARY_RAM_START _IMXRT_OCRAM_BASE # define PRIMARY_RAM_SIZE IMXRT_OCRAM_SIZE - (CONFIG_ITCM_USED + CONFIG_DTCM_USED) # define IMXRT_OCRAM_ASSIGNED 1 diff --git a/arch/arm/src/imxrt/imxrt_clockconfig.h b/arch/arm/src/imxrt/imxrt_clockconfig.h index 1e5bb74885456..47b76bce7d1f5 100644 --- a/arch/arm/src/imxrt/imxrt_clockconfig.h +++ b/arch/arm/src/imxrt/imxrt_clockconfig.h @@ -33,7 +33,9 @@ * hence we use a VER2 driver for clockconfig */ -#ifdef CONFIG_IMXRT_CLOCKCONFIG_VER2 +#ifdef CONFIG_IMXRT_CLOCKCONFIG_VER3 +#include "imxrt_clockconfig_ver3.h" +#elif defined(CONFIG_IMXRT_CLOCKCONFIG_VER2) #include "imxrt_clockconfig_ver2.h" #else #include "imxrt_clockconfig_ver1.h" diff --git a/arch/arm/src/imxrt/imxrt_clockconfig_ver3.c b/arch/arm/src/imxrt/imxrt_clockconfig_ver3.c new file mode 100644 index 0000000000000..fdcc3de608786 --- /dev/null +++ b/arch/arm/src/imxrt/imxrt_clockconfig_ver3.c @@ -0,0 +1,566 @@ +/**************************************************************************** + * arch/arm/src/imxrt/imxrt_clockconfig_ver3.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +#include +#include + +#include "arm_internal.h" +#include "hardware/imxrt_memorymap.h" +#include "hardware/imxrt_dcdc.h" +#include "hardware/rt118x/imxrt118x_anadig.h" +#include "hardware/rt118x/imxrt118x_ccm.h" +#include "hardware/rt118x/imxrt118x_gpc.h" +#include "imxrt_clockconfig_ver3.h" +#ifdef CONFIG_IMXRT_ELE +# include "imxrt118x_ele.h" +#endif + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Fixed clock source frequencies programmed by the Cortex-M33 boot ROM + * before the M7 is released. NuttX does not reprogram these PLLs, so + * their frequencies are treated as static constants; if a future use + * case needs to reconfigure the PLLs, extend imxrt_get_clock() to read + * the ANADIG registers instead. + */ + +#define IMXRT_OSC_24M_HZ (24000000u) +#define IMXRT_OSC_RC_24M_HZ (24000000u) +#define IMXRT_OSC_RC_400M_HZ (400000000u) +#define IMXRT_ARM_PLL_HZ (798000000u) +#define IMXRT_SYS_PLL1_HZ (1000000000u) +#define IMXRT_SYS_PLL2_HZ (528000000u) +#define IMXRT_SYS_PLL3_HZ (480000000u) + +/* Standard PFD fractions used by the boot ROM (IMXRT1180RM Ch. 20.5 default + * configuration). Output = (PLL * 18) / frac. + */ + +#define IMXRT_SYS_PLL2_PFD0_HZ (352000000u) /* frac = 27 */ +#define IMXRT_SYS_PLL2_PFD1_HZ (594000000u) /* frac = 16 */ +#define IMXRT_SYS_PLL2_PFD2_HZ (396000000u) /* frac = 24 */ +#define IMXRT_SYS_PLL2_PFD3_HZ (297000000u) /* frac = 32 */ +#define IMXRT_SYS_PLL3_PFD0_HZ (664615384u) /* frac = 13 */ +#define IMXRT_SYS_PLL3_PFD1_HZ (508235294u) /* frac = 17 */ +#define IMXRT_SYS_PLL3_PFD2_HZ (392727272u) /* frac = 22 */ +#define IMXRT_SYS_PLL3_PFD3_HZ (392727272u) /* frac = 22 */ + +/* ARM_PLL loop divider for 798 MHz with post_div = 2: + * + * Fout = 24 MHz * 133 / (2 * 2) = 798 MHz + */ + +#define ARM_PLL_DIV_SELECT (133) + +/* Analog settling delays, expressed as NOP spins because no timer exists + * this early. The M33 still runs from OSC_RC_400M/2 (200 MHz), so one + * iteration is roughly 5 ns; both values are generously rounded up. + */ + +#define PLL_LDO_SETTLE_SPINS (1000) /* SDK uses 1 us */ +#define ARM_PLL_SETTLE_SPINS (25000) /* SDK uses 30 us */ +#define DCDC_SETTLE_SPINS (100000) /* ~123 us of 32 kHz clock */ + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +#ifdef CONFIG_ARCH_CHIP_MIMXRT1189CVM8C_CM33 + +/**************************************************************************** + * Name: imxrt_spin + * + * Description: + * Crude busy delay for the analog settling times required during clock + * bring-up. The OS timer is not running this early and the core clock + * is still OSC_RC_400M/2, so this is expressed in loop iterations rather + * than microseconds. + * + ****************************************************************************/ + +static void imxrt_spin(int spins) +{ + int i; + + for (i = 0; i < spins; i++) + { + __asm__ __volatile__("nop"); + } +} + +/**************************************************************************** + * Name: imxrt_set_core_voltage + * + * Description: + * Program the VDD1P0 run-mode target of the on-chip DCDC. + * + * Both cores share a single VDD1P0 rail. The DCDC arbitrates TRG_SW_0 + * and TRG_SW_1 and applies the higher of the two targets + * (IMXRT1180RM Rev. 10 sec. 22.7.1.8), so both must be programmed for + * the new target to take effect. + * + * Input Parameters: + * target - VDD1P0CTRL_TRG encoding, 25 mV per step from 0.6 V. + * + ****************************************************************************/ + +static void imxrt_set_core_voltage(uint32_t target) +{ + uint32_t regval; + +#ifdef CONFIG_IMXRT_ELE + /* Guard the DCDC target change with the EdgeLock Enclave voltage-change + * handshake. + */ + + imxrt118x_ele_voltage_change_start(); +#endif + + regval = getreg32(IMXRT_DCDC_TRG_SW_0); + regval &= ~DCDC_TRG_SW_VDD1P0CTRL_TRG_MASK; + regval |= DCDC_TRG_SW_VDD1P0CTRL_TRG(target); + putreg32(regval, IMXRT_DCDC_TRG_SW_0); + + regval = getreg32(IMXRT_DCDC_TRG_SW_1); + regval &= ~DCDC_TRG_SW_VDD1P0CTRL_TRG_MASK; + regval |= DCDC_TRG_SW_VDD1P0CTRL_TRG(target); + putreg32(regval, IMXRT_DCDC_TRG_SW_1); + +#ifdef CONFIG_IMXRT_ELE + /* Remove the GDET isolation. Must be issued within 50 ms of START and + * with no other ELE command in between (only DCDC register writes above). + */ + + imxrt118x_ele_voltage_change_finish(); +#endif + + /* Wait for the regulator to reach the new target. CURRENT_TRG + * [DCDC_UPDATING] must not be used for this: RM sec. 22.7.1.5 states it + * can stay asserted for seconds and is intended for debug only. The + * supply status is REG0[STS_DC_OK], which is synchronised to the 32 kHz + * clock and settles within ~4 of its cycles (~123 us), so allow the + * request to reach the analog before sampling it. + */ + + imxrt_spin(DCDC_SETTLE_SPINS); + + while ((getreg32(IMXRT_DCDC_REG0) & DCDC_REG0_STS_DC_OK) == 0); +} + +/**************************************************************************** + * Name: imxrt_enable_pll_ldo + * + * Description: + * Enable the PHY LDO that supplies the PLLs. It must be up and stable + * before ARM_PLL is powered on. + * + ****************************************************************************/ + +static void imxrt_enable_pll_ldo(void) +{ + uint32_t regval; + + regval = PHY_LDO_CTRL0_LINREG_OUTPUT_TRG(0x10) | PHY_LDO_CTRL0_LINREG_EN; + + if (getreg32(IMXRT_PHY_LDO_CTRL0_RW) != regval) + { + /* Bring the regulator up with its current limiter armed ... */ + + putreg32(regval | PHY_LDO_CTRL0_LINREG_ILIMIT_EN, + IMXRT_PHY_LDO_CTRL0_RW); + imxrt_spin(PLL_LDO_SETTLE_SPINS); + + /* ... then drop the limiter once stable, which lowers ARM PLL jitter + * at cold temperature. + */ + + putreg32(regval, IMXRT_PHY_LDO_CTRL0_RW); + } +} + +/**************************************************************************** + * Name: imxrt_init_arm_pll + * + * Description: + * Bring up ARM_PLL at 798 MHz. + * + * Fout = 24 MHz * DIV_SELECT / (2 * post_div) + * = 24 MHz * 133 / (2 * 2) + * = 798 MHz + * + * This is the maximum supported ARM_PLL output. It clocks the M7 + * directly and gives the M33 266 MHz through its integer divider. + * + * The RM's ARM_PLL_CTRL description refers to a "PLL Enable Sequence" + * topic for the HOLD_RING_OFF handling, but no such section exists in + * Rev. 10 and no hold time is given. NXP's own CLOCK_InitArmPll() does + * not use HOLD_RING_OFF on this PLL at all, so follow that: configure + * the dividers while gated, power up, allow the analog to settle, then + * wait for lock. + * + ****************************************************************************/ + +static void imxrt_init_arm_pll(void) +{ + uint32_t regval; + + imxrt_enable_pll_ldo(); + + regval = ANADIG_PLL_ARM_DIV_SELECT(ARM_PLL_DIV_SELECT) | + ANADIG_PLL_ARM_POST_DIV_SEL(ANADIG_PLL_ARM_POST_DIV_2); + + /* Power the PLL down before touching the dividers, keeping the output + * gated so that nothing sees an intermediate frequency. + */ + + putreg32(regval | ANADIG_PLL_ARM_GATE, IMXRT_ANADIG_PLL_ARM_CTRL); + + /* Apply the configuration and power up, still gated. */ + + putreg32(regval | ANADIG_PLL_ARM_GATE | ANADIG_PLL_ARM_POWERUP, + IMXRT_ANADIG_PLL_ARM_CTRL); + + UP_DSB(); + UP_ISB(); + + imxrt_spin(ARM_PLL_SETTLE_SPINS); + + while ((getreg32(IMXRT_ANADIG_PLL_ARM_CTRL) & + ANADIG_PLL_ARM_STABLE) == 0); + + /* Locked: enable the clock and ungate the output. */ + + putreg32(regval | ANADIG_PLL_ARM_POWERUP | ANADIG_PLL_ARM_ENABLE_CLK, + IMXRT_ANADIG_PLL_ARM_CTRL); +} + +#endif /* CONFIG_ARCH_CHIP_MIMXRT1189CVM8C_CM33 */ + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: imxrt_ccm_configure_root_clock + ****************************************************************************/ + +int imxrt_ccm_configure_root_clock(int root, int src, uint32_t div) +{ + uint32_t auth; + uint32_t regval; + uint32_t newval; + int i; + + if (root >= CCM_CR_COUNT || div == 0 || div > 256) + { + return -EINVAL; + } + + auth = getreg32(IMXRT_CCM_CR_AUTH(root)); + + if ((auth & CCM_CR_AUTH_DOMAIN(BOARD_CCM_DOMAIN_ID)) == 0) + { + return -EINVAL; + } + + /* Find the mux index that selects the requested source. */ + + for (i = 0; i < ROOT_MUX_MAX; i++) + { + if (g_ccm_root_mux[root][i] == src) + { + break; + } + } + + if (i == ROOT_MUX_MAX) + { + return -EINVAL; + } + + regval = getreg32(IMXRT_CCM_CR_CTRL(root)); + newval = regval & ~(CCM_CR_CTRL_MUX_MASK | CCM_CR_CTRL_DIV_MASK); + newval |= CCM_CR_CTRL_MUX_SRCSEL(i) | CCM_CR_CTRL_DIV(div); + + /* Do not reconfigure a root that already has the requested settings. */ + + if (newval == regval) + { + return OK; + } + + putreg32(newval, IMXRT_CCM_CR_CTRL(root)); + + while (getreg32(IMXRT_CCM_CR_STAT0(root)) & CCM_CR_STAT0_CHANGING); + + return OK; +} + +/**************************************************************************** + * Name: imxrt_ccm_gate_on + ****************************************************************************/ + +int imxrt_ccm_gate_on(int gate, bool enabled) +{ + uint32_t value; + + if (gate >= CCM_LPCG_COUNT) + { + return -EINVAL; + } + + value = enabled ? CCM_LPCG_DIR_ON : 0u; + putreg32(value, IMXRT_CCM_LPCG_DIR(gate)); + + while ((getreg32(IMXRT_CCM_LPCG_STAT0(gate)) & CCM_LPCG_STAT0_ON) != + value); + + return OK; +} + +/**************************************************************************** + * Name: imxrt_periphclk_configure + * + * Description: + * Thin wrapper that lets legacy callers pass CCM_LPCG_DIR_ON / + * CCM_LPCG_DIR_OFF as the second argument. + * + ****************************************************************************/ + +void imxrt_periphclk_configure(unsigned int index, unsigned int value) +{ + imxrt_ccm_gate_on((int)index, (value & CCM_LPCG_DIR_ON) != 0); +} + +/**************************************************************************** + * Name: imxrt_get_clock + ****************************************************************************/ + +int imxrt_get_clock(int clkname, uint32_t *frequency) +{ + switch (clkname) + { + case OSC_RC_24M: + *frequency = IMXRT_OSC_RC_24M_HZ; + break; + + case OSC_RC_400M: + *frequency = IMXRT_OSC_RC_400M_HZ; + break; + + case OSC_24M: + *frequency = IMXRT_OSC_24M_HZ; + break; + + case ARM_PLL_OUT: + *frequency = IMXRT_ARM_PLL_HZ; + break; + + case SYS_PLL1_OUT: + *frequency = IMXRT_SYS_PLL1_HZ; + break; + + case SYS_PLL1_DIV2: + *frequency = IMXRT_SYS_PLL1_HZ / 2; + break; + + case SYS_PLL1_DIV5: + *frequency = IMXRT_SYS_PLL1_HZ / 5; + break; + + case SYS_PLL2_OUT: + *frequency = IMXRT_SYS_PLL2_HZ; + break; + + case SYS_PLL2_PFD0: + *frequency = IMXRT_SYS_PLL2_PFD0_HZ; + break; + + case SYS_PLL2_PFD1: + *frequency = IMXRT_SYS_PLL2_PFD1_HZ; + break; + + case SYS_PLL2_PFD2: + *frequency = IMXRT_SYS_PLL2_PFD2_HZ; + break; + + case SYS_PLL2_PFD3: + *frequency = IMXRT_SYS_PLL2_PFD3_HZ; + break; + + case SYS_PLL3_OUT: + *frequency = IMXRT_SYS_PLL3_HZ; + break; + + case SYS_PLL3_DIV2: + *frequency = IMXRT_SYS_PLL3_HZ / 2; + break; + + case SYS_PLL3_PFD0: + *frequency = IMXRT_SYS_PLL3_PFD0_HZ; + break; + + case SYS_PLL3_PFD1: + *frequency = IMXRT_SYS_PLL3_PFD1_HZ; + break; + + case SYS_PLL3_PFD2: + *frequency = IMXRT_SYS_PLL3_PFD2_HZ; + break; + + case SYS_PLL3_PFD3: + *frequency = IMXRT_SYS_PLL3_PFD3_HZ; + break; + + case AUDIO_PLL_OUT: + *frequency = 0; + break; + + default: + return -ENODEV; + } + + return OK; +} + +/**************************************************************************** + * Name: imxrt_get_rootclock + ****************************************************************************/ + +int imxrt_get_rootclock(uint32_t clkroot, uint32_t *frequency) +{ + uint32_t reg; + uint32_t mux; + uint32_t div; + int clkname; + + if (clkroot >= CCM_CR_COUNT) + { + return -ENODEV; + } + + reg = getreg32(IMXRT_CCM_CR_CTRL(clkroot)); + + if ((reg & CCM_CR_CTRL_OFF) != 0) + { + *frequency = 0; + return OK; + } + + mux = (reg & CCM_CR_CTRL_MUX_MASK) >> CCM_CR_CTRL_MUX_SHIFT; + clkname = g_ccm_root_mux[clkroot][mux]; + imxrt_get_clock(clkname, frequency); + div = ((reg & CCM_CR_CTRL_DIV_MASK) >> CCM_CR_CTRL_DIV_SHIFT) + 1; + *frequency = *frequency / div; + + return OK; +} + +/**************************************************************************** + * Name: imxrt_clockconfig + * + * Description: + * Called to initialize the i.MX RT. This does whatever setup is needed to + * put the SoC in a usable state. The Cortex-M33 boot ROM has already + * started essential PLLs and set the FlexSPI1 clock, so only the roots + * required by NuttX are configured here. CCM_CR_FLEXSPI1 and its LPCG + * MUST NOT be touched while executing XIP from FlexSPI1. + * + ****************************************************************************/ + +void imxrt_clockconfig(void) +{ +#ifdef CONFIG_ARCH_CHIP_MIMXRT1189CVM8C_CM33 + /* Raise VDD1P0 to the HSRUN (OverDrive) level. Both cores share this + * rail and the M33 is the boot core, so it does this on behalf of both. + * + * Forward body bias is deliberately not enabled here. Per RM sec. + * 19.3.3 and 24.3.2.3.3.2 FBB is implemented in the Cortex-M7 platform + * only; the well-bias power switch it turns on belongs to the M7 domain. + * It is enabled by the bootloader as part of releasing the M7. + */ + + imxrt_set_core_voltage(DCDC_1P0_TARGET_1P125V); + + /* Configure ARM_PLL and the M33 root here. The M7 root and M7-specific + * power setup are owned by the bootloader. The M7 must not touch + * ARM_PLL or the M33 root when it later executes this function. + */ + + imxrt_init_arm_pll(); + + /* M33 core clock: ARM_PLL (798 MHz) / 3 = 266 MHz. */ + + imxrt_ccm_configure_root_clock(CCM_CR_M33, ARM_PLL_OUT, 3); + + /* Root1 belongs exclusively to the M33 domain. LOCK_LIST makes this + * ownership immutable until the next system reset. + */ + + putreg32(CCM_CR_AUTH_DOMAIN(BOARD_CCM_DOMAIN_ID) | + CCM_CR_AUTH_LOCK_LIST, + IMXRT_CCM_CR_AUTH(CCM_CR_M33)); + +#endif + +#ifdef CONFIG_ARCH_CHIP_MIMXRT1189CVM8C_CM33 + /* Keep both CPU cores in RUN during WFI so core exceptions such as + * SysTick can wake them without requiring a GPC wakeup source. + */ + + modifyreg32(IMXRT_GPC_CM33_MODE_CTRL, + GPC_CM_MODE_CTRL_TARGET_MASK, + GPC_CM_MODE_CTRL_TARGET(GPC_CM_MODE_TARGET_RUN)); + modifyreg32(IMXRT_GPC_CM_MISC(0), + GPC_CM_MISC_SLEEP_HOLD_EN, 0); +#endif + + /* AON bus (LPUART1/2 pclk): SYS_PLL2 (528 MHz) / 4 = 132 MHz */ + + imxrt_ccm_configure_root_clock(CCM_CR_BUS_AON, SYS_PLL2_OUT, 4); + + /* M7 SysTick reference: 24 MHz / 240 = 100 kHz */ + + imxrt_ccm_configure_root_clock(CCM_CR_M7_SYSTICK, OSC_24M, 240); + + /* LPUART1/2 functional clock: SYS_PLL3_DIV2 (240 MHz) / 10 = 24 MHz */ + + imxrt_ccm_configure_root_clock(CCM_CR_LPUART0102, SYS_PLL3_DIV2, 10); + + /* Turn on the LPCGs used by the minimal port */ + + imxrt_ccm_gate_on(CCM_LPCG_IOMUXC1, true); + imxrt_ccm_gate_on(CCM_LPCG_IOMUXC2, true); + imxrt_ccm_gate_on(CCM_LPCG_LPUART1, true); +} diff --git a/arch/arm/src/imxrt/imxrt_clockconfig_ver3.h b/arch/arm/src/imxrt/imxrt_clockconfig_ver3.h new file mode 100644 index 0000000000000..3bff311d4ddb9 --- /dev/null +++ b/arch/arm/src/imxrt/imxrt_clockconfig_ver3.h @@ -0,0 +1,113 @@ +/**************************************************************************** + * arch/arm/src/imxrt/imxrt_clockconfig_ver3.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_IMXRT_IMXRT_CLOCKCONFIG_VER3_H +#define __ARCH_ARM_SRC_IMXRT_IMXRT_CLOCKCONFIG_VER3_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include + +#include "hardware/rt118x/imxrt118x_ccm.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* LPCG helpers so the shared code can enable/disable peripheral clock gates + * with the same names as on other i.MX RT families. + */ + +#define imxrt_clockall_lpuart1() imxrt_ccm_gate_on(CCM_LPCG_LPUART1, true) +#define imxrt_clockall_lpuart2() imxrt_ccm_gate_on(CCM_LPCG_LPUART2, true) +#define imxrt_clockall_lpuart3() imxrt_ccm_gate_on(CCM_LPCG_LPUART3, true) +#define imxrt_clockall_lpuart4() imxrt_ccm_gate_on(CCM_LPCG_LPUART4, true) +#define imxrt_clockall_lpuart5() imxrt_ccm_gate_on(CCM_LPCG_LPUART5, true) +#define imxrt_clockall_lpuart6() imxrt_ccm_gate_on(CCM_LPCG_LPUART6, true) +#define imxrt_clockall_lpuart7() imxrt_ccm_gate_on(CCM_LPCG_LPUART7, true) +#define imxrt_clockall_lpuart8() imxrt_ccm_gate_on(CCM_LPCG_LPUART8, true) +#define imxrt_clockall_lpuart9() imxrt_ccm_gate_on(CCM_LPCG_LPUART9, true) +#define imxrt_clockall_lpuart10() imxrt_ccm_gate_on(CCM_LPCG_LPUART10, true) +#define imxrt_clockall_lpuart11() imxrt_ccm_gate_on(CCM_LPCG_LPUART11, true) +#define imxrt_clockall_lpuart12() imxrt_ccm_gate_on(CCM_LPCG_LPUART12, true) + +#define imxrt_clockall_xbar1() imxrt_ccm_gate_on(CCM_LPCG_XBAR1, true) +#define imxrt_clockall_xbar2() imxrt_ccm_gate_on(CCM_LPCG_XBAR2, true) +#define imxrt_clockall_xbar3() imxrt_ccm_gate_on(CCM_LPCG_XBAR3, true) + +#define imxrt_clockall_gpio1() imxrt_ccm_gate_on(CCM_LPCG_GPIO1, true) +#define imxrt_clockall_gpio2() imxrt_ccm_gate_on(CCM_LPCG_GPIO2, true) +#define imxrt_clockall_gpio3() imxrt_ccm_gate_on(CCM_LPCG_GPIO3, true) +#define imxrt_clockall_gpio4() imxrt_ccm_gate_on(CCM_LPCG_GPIO4, true) +#define imxrt_clockall_gpio5() imxrt_ccm_gate_on(CCM_LPCG_GPIO5, true) +#define imxrt_clockall_gpio6() imxrt_ccm_gate_on(CCM_LPCG_GPIO6, true) + +#define imxrt_clockall_ocotp_ctrl() imxrt_ccm_gate_on(CCM_LPCG_OCOTP, true) + +#define imxrt_clockall_usboh3() imxrt_ccm_gate_on(CCM_LPCG_USB, true) +#define imxrt_clockoff_usboh3() imxrt_ccm_gate_on(CCM_LPCG_USB, false) +#define imxrt_clockrun_usboh3() imxrt_ccm_gate_on(CCM_LPCG_USB, true) + +/**************************************************************************** + * Public Function Prototypes + ****************************************************************************/ + +/* Initialise the RT1180 clock tree. */ + +void imxrt_clockconfig(void); + +/* Program a clock root's MUX + DIV using a clock source name from + * ccm_clock_name_e. Returns OK, or -EINVAL if the (root, src) pair is + * not valid. + */ + +int imxrt_ccm_configure_root_clock(int root, int src, uint32_t div); + +/* Enable or disable a low-power clock gate (LPCG). */ + +int imxrt_ccm_gate_on(int gate, bool enabled); + +/* Compatibility shim for existing callers that use CCM_LPCG_DIR_ON / + * CCM_LPCG_DIR_OFF as the value argument. + */ + +void imxrt_periphclk_configure(unsigned int index, unsigned int value); + +/* Return the frequency in Hz of the named clock source (OSC / PLL / PFD) + * or zero if unknown. + */ + +int imxrt_get_clock(int clkname, uint32_t *frequency); + +/* Return the frequency in Hz of the selected clock root (after MUX and + * DIV are applied). Signature matches RT117x's imxrt_get_rootclock() so + * that shared drivers do not need to distinguish between families. + */ + +int imxrt_get_rootclock(uint32_t clkroot, uint32_t *frequency); + +#endif /* __ARCH_ARM_SRC_IMXRT_IMXRT_CLOCKCONFIG_VER3_H */ diff --git a/arch/arm/src/imxrt/imxrt_clrpend.c b/arch/arm/src/imxrt/imxrt_clrpend.c index fb874717c4e74..b759b1e3d6dce 100644 --- a/arch/arm/src/imxrt/imxrt_clrpend.c +++ b/arch/arm/src/imxrt/imxrt_clrpend.c @@ -89,6 +89,27 @@ void imxrt_clrpend(int irq) putreg32(1 << (irq - IMXRT_IRQ_EXTINT - 128), NVIC_IRQ128_159_CLRPEND); } +#endif +#if IMXRT_IRQ_NEXTINT >= 192 + else if (irq < (IMXRT_IRQ_EXTINT + 192)) + { + putreg32(1 << (irq - IMXRT_IRQ_EXTINT - 160), + NVIC_IRQ160_191_CLRPEND); + } +#endif +#if IMXRT_IRQ_NEXTINT >= 224 + else if (irq < (IMXRT_IRQ_EXTINT + 224)) + { + putreg32(1 << (irq - IMXRT_IRQ_EXTINT - 192), + NVIC_IRQ192_223_CLRPEND); + } +#endif +#if IMXRT_IRQ_NEXTINT >= 240 + else if (irq < (IMXRT_IRQ_EXTINT + 240)) + { + putreg32(1 << (irq - IMXRT_IRQ_EXTINT - 224), + NVIC_IRQ224_239_CLRPEND); + } #endif else { diff --git a/arch/arm/src/imxrt/imxrt_config.h b/arch/arm/src/imxrt/imxrt_config.h index 98b772aac6e5d..a96670f1c991a 100644 --- a/arch/arm/src/imxrt/imxrt_config.h +++ b/arch/arm/src/imxrt/imxrt_config.h @@ -71,6 +71,18 @@ #ifdef CONFIG_IMXRT_LPUART8 # define HAVE_LPUART8 1 #endif +#ifdef CONFIG_IMXRT_LPUART9 +# define HAVE_LPUART9 1 +#endif +#ifdef CONFIG_IMXRT_LPUART10 +# define HAVE_LPUART10 1 +#endif +#ifdef CONFIG_IMXRT_LPUART11 +# define HAVE_LPUART11 1 +#endif +#ifdef CONFIG_IMXRT_LPUART12 +# define HAVE_LPUART12 1 +#endif /* Check if we have a LPUART device */ @@ -79,7 +91,8 @@ #if defined(HAVE_LPUART1) || defined(HAVE_LPUART2) || defined(HAVE_LPUART3) || \ defined(HAVE_LPUART4) || defined(HAVE_LPUART5) || defined(HAVE_LPUART6) || \ - defined(HAVE_LPUART7) || defined(HAVE_LPUART8) + defined(HAVE_LPUART7) || defined(HAVE_LPUART8) || defined(HAVE_LPUART9) || \ + defined(HAVE_LPUART10) || defined(HAVE_LPUART11) || defined(HAVE_LPUART12) # define HAVE_LPUART_DEVICE 1 #endif diff --git a/arch/arm/src/imxrt/imxrt_edma.h b/arch/arm/src/imxrt/imxrt_edma.h index 8bca05b09bc4a..a24c5429207ef 100644 --- a/arch/arm/src/imxrt/imxrt_edma.h +++ b/arch/arm/src/imxrt/imxrt_edma.h @@ -99,7 +99,12 @@ #include #include -#include "hardware/imxrt_edma.h" + +#ifdef CONFIG_IMXRT_EDMA_VER2 +# include "hardware/rt118x/imxrt118x_edma.h" +#else +# include "hardware/imxrt_edma.h" +#endif /**************************************************************************** * Pre-processor Definitions @@ -138,13 +143,26 @@ typedef void *DMACH_HANDLE; typedef void (*edma_callback_t)(DMACH_HANDLE handle, void *arg, bool done, int result); -/* eDMA transfer sizes */ +/* eDMA transfer type */ + +enum imxrt_edma_xfrtype_e +{ + EDMA_MEM2MEM = 0, /* Transfer from memory to memory */ + EDMA_PERIPH2MEM, /* Transfer from peripheral to memory */ + EDMA_MEM2PERIPH, /* Transfer from memory to peripheral */ +}; -enum kinetis_edma_sizes_e +/* eDMA transfer sises */ + +enum imxrt_edma_sizes_e { EDMA_8BIT = 0, /* Transfer data size 8 */ EDMA_16BIT = 1, /* Transfer data size 16 */ EDMA_32BIT = 2, /* Transfer data size 32 */ + EDMA_64BIT = 3, /* Transfer data size 64 */ + EDMA_16BYTE = 4, /* Transfer data size 16-byte */ + EDMA_32BYTE = 5, /* Transfer data size 32-byte */ + EDMA_64BYTE = 6, /* Transfer data size 64-byte */ }; /* This structure holds the source/destination transfer attribute @@ -166,6 +184,11 @@ struct imxrt_edma_xfrconfig_s #else uint32_t nbytes; /* Bytes to transfer in a minor loop */ #endif +#ifdef CONFIG_IMXRT_EDMA_VER2 + uint8_t smod; + uint8_t dmod; + uint8_t bwc; +#endif #ifdef CONFIG_IMXRT_EDMA_ELINK DMACH_HANDLE linkch; /* Link channel (With EDMA_CONFIG_LINKTYPE_* flags) */ #endif diff --git a/arch/arm/src/imxrt/imxrt_edma_ver2.c b/arch/arm/src/imxrt/imxrt_edma_ver2.c new file mode 100644 index 0000000000000..1be42a936ec6f --- /dev/null +++ b/arch/arm/src/imxrt/imxrt_edma_ver2.c @@ -0,0 +1,1529 @@ +/**************************************************************************** + * arch/arm/src/imxrt/imxrt_edma_ver2.c + * + * SPDX-License-Identifier: BSD-3-Clause + * SPDX-FileCopyrightText: 2019, 2021, 2023 Gregory Nutt. + * SPDX-FileCopyrightText: 2022 NXP + * SPDX-FileCopyrightText: 2016-2017 NXP + * SPDX-FileCopyrightText: 2015, Freescale Semiconductor, Inc. + * SPDX-FileContributor: Gregory Nutt + * SPDX-FileContributor: David Sidrane + * SPDX-FileContributor: Peter van der Perk + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include + +#include "arm_internal.h" +#include "sched/sched.h" + +#include "chip.h" +#include "imxrt_edma.h" +#include "imxrt_clockconfig.h" + +#include "hardware/imxrt_ccm.h" +#include "hardware/rt118x/imxrt118x_edma.h" +#include "hardware/imxrt_dmamux.h" + +#ifdef CONFIG_IMXRT_EDMA + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* TCD Alignment. + * + * eDMA TCDs must be aligned with the D-Cache line boundaries to facilitate + * cache operations on the TCDs when the D-Cache is enabled. + * + * NOTE: The TCDs are 32-bytes in length. We implicitly assume that the + * D-Cache line size is also 32-bits. Otherwise, padding would be required + * at the ends of the TCDS and buffers to protect data after the end of from + * invalidation. + */ + +#define EDMA_ALIGN ARMV7M_DCACHE_LINESIZE +#define EDMA_ALIGN_MASK (EDMA_ALIGN - 1) +#define EDMA_ALIGN_UP(n) (((n) + EDMA_ALIGN_MASK) & ~EDMA_ALIGN_MASK) + +/**************************************************************************** + * Private Types + ****************************************************************************/ + +/* State of a DMA channel */ + +enum imxrt_dmastate_e +{ + IMXRT_DMA_IDLE = 0, /* No DMA in progress */ + IMXRT_DMA_CONFIGURED, /* DMA configured, but not yet started */ + IMXRT_DMA_ACTIVE /* DMA has been started and is in progress */ +}; + +/* This structure describes one DMA channel */ + +struct imxrt_dmach_s +{ + uintptr_t base; /* DMA engine base address */ + uint32_t flags; /* DMA channel flags */ + bool inuse; /* true: The DMA channel is in use */ + uint8_t dmamux; /* DMAMUX channel number */ + uint8_t chan; /* DMA channel number (either eDMA3 or eDMA4) */ + uint8_t state; /* Channel state. See enum imxrt_dmastate_e */ + edma_callback_t callback; /* Callback invoked when the DMA completes */ + void *arg; /* Argument passed to callback function */ +#if CONFIG_IMXRT_EDMA_NTCD > 0 + /* That TCD list is linked through the DLAST SGA field. The first transfer + * to be performed is at the head of the list. Subsequent TCDs are added + * at the tail of the list. + */ + + struct imxrt_edmatcd_s *head; /* First TCD in the list */ + struct imxrt_edmatcd_s *tail; /* Last TCD in the list */ +#endif +}; + +/* This structure describes the state of the eDMA controller */ + +struct imxrt_edma_s +{ + /* These mutex protect the DMA channel and descriptor tables */ + + mutex_t chlock; /* Protects channel table */ +#if CONFIG_IMXRT_EDMA_NTCD > 0 + sem_t dsem; /* Supports wait for free descriptors */ +#endif + + /* This array describes each DMA channel */ + + struct imxrt_dmach_s dmach[IMXRT_EDMA_NCHANNELS]; + spinlock_t lock; +}; + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/* The state of the eDMA */ + +static struct imxrt_edma_s g_edma = +{ + .chlock = NXMUTEX_INITIALIZER, +#if CONFIG_IMXRT_EDMA_NTCD > 0 + .dsem = SEM_INITIALIZER(CONFIG_IMXRT_EDMA_NTCD), +#endif + .lock = SP_UNLOCKED +}; + +#if CONFIG_IMXRT_EDMA_NTCD > 0 +/* This is a singly-linked list of free TCDs */ + +static sq_queue_t g_tcd_free; + +/* This is a pool of pre-allocated TCDs */ + +static struct imxrt_edmatcd_s g_tcd_pool[CONFIG_IMXRT_EDMA_NTCD] + aligned_data(EDMA_ALIGN); +#endif + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: imxrt_tcd_alloc + * + * Description: + * Allocate an in-memory, TCD + * + ****************************************************************************/ + +#if CONFIG_IMXRT_EDMA_NTCD > 0 +static struct imxrt_edmatcd_s *imxrt_tcd_alloc(void) +{ + struct imxrt_edmatcd_s *tcd; + irqstate_t flags; + + /* Take the 'dsem'. When we hold the the 'dsem', then we know that one + * TCD is reserved for us in the free list. + * + * NOTE: We use a critical section here because we may block waiting for + * the 'dsem'. The critical section will be suspended while we are + * waiting. + */ + + nxsem_wait_uninterruptible(&g_edma.dsem); + + /* Now there should be a TCD in the free list reserved just for us */ + + flags = spin_lock_irqsave(&g_edma.lock); + tcd = (struct imxrt_edmatcd_s *)sq_remfirst(&g_tcd_free); + DEBUGASSERT(tcd != NULL); + + spin_unlock_irqrestore(&g_edma.lock, flags); + return tcd; +} +#endif + +/**************************************************************************** + * Name: imxrt_tcd_free + * + * Description: + * Free an in-memory, TCD + * + ****************************************************************************/ + +#if CONFIG_IMXRT_EDMA_NTCD > 0 +static void imxrt_tcd_free_nolock(struct imxrt_edmatcd_s *tcd) +{ + /* Add the the TCD to the end of the free list and post the 'dsem', + * possibly waking up another thread that might be waiting for + * a TCD. + */ + + sq_addlast((sq_entry_t *)tcd, &g_tcd_free); + nxsem_post(&g_edma.dsem); +} + +static void imxrt_tcd_free(struct imxrt_edmatcd_s *tcd) +{ + irqstate_t flags; + + /* Add the TCD to the end of the free list and post the 'dsem', + * possibly waking up another thread that might be waiting for + * a TCD. + */ + + flags = spin_lock_irqsave_nopreempt(&g_edma.lock); + imxrt_tcd_free_nolock(tcd); + spin_unlock_irqrestore_nopreempt(&g_edma.lock, flags); +} +#endif + +/**************************************************************************** + * Name: imxrt_tcd_initialize() + * + * Description: + * Initialize the TCD free list from the pool of pre-allocated TCDs. + * + * Assumptions: + * Called early in the initialization sequence so no special protection is + * necessary. + * + ****************************************************************************/ + +#if CONFIG_IMXRT_EDMA_NTCD > 0 +static inline void imxrt_tcd_initialize(void) +{ + sq_entry_t *tcd; + int i; + + /* Add each pre-allocated TCD to the tail of the TCD free list */ + + sq_init(&g_tcd_free); + for (i = 0; i < CONFIG_IMXRT_EDMA_NTCD; i++) + { + tcd = (sq_entry_t *)&g_tcd_pool[i]; + sq_addlast(tcd, &g_tcd_free); + } +} +#endif + +/**************************************************************************** + * Name: imxrt_tcd_chanlink + * + * Description: + * This function configures either a minor link or a major link. The minor + * link means the channel link is triggered every time CITER decreases by 1 + * The major link means that the channel link is triggered when the CITER + * is exhausted. + * + * NOTE: Users should ensure that DONE flag is cleared before calling this + * interface, or the configuration is invalid. + * + * Input Parameters: + * tcd - Point to the TCD structure. + * type - Channel link type. + * chan - The linked channel number. + * + * Returned Value: + * None + * + ****************************************************************************/ + +#ifdef CONFIG_IMXRT_EDMA_ELINK +static inline void imxrt_tcd_chanlink(uint8_t flags, + struct imxrt_dmach_s *linkch, + struct imxrt_edmatcd_s *tcd) +{ + uint16_t regval16; + + flags &= EDMA_CONFIG_LINKTYPE_MASK; + + if (linkch == NULL || flags == EDMA_CONFIG_LINKTYPE_LINKNONE) + { + /* No link or no link channel provided */ + + /* Disable minor links */ + + /* Disable major link */ + + tcd->csr &= ~EDMA_TCD_CSR_MAJORELINK; + } + else if (flags == EDMA_CONFIG_LINKTYPE_MINORLINK) /* Minor link config */ + { + /* Enable minor link */ + + tcd->citer |= EDMA_TCD_CITER_ELINK; + tcd->biter |= EDMA_TCD_BITER_ELINK; + + /* Set linked channel */ + + regval16 = tcd->citer; + regval16 &= ~EDMA_TCD_CITER_LINKCH_MASK; + regval16 |= EDMA_TCD_CITER_LINKCH(linkch->chan); + tcd->citer = regval16; + + regval16 = tcd->biter; + regval16 &= ~EDMA_TCD_BITER_LINKCH_MASK; + regval16 |= EDMA_TCD_BITER_LINKCH(linkch->chan); + tcd->biter = regval16; + } + else /* if (flags == EDMA_CONFIG_LINKTYPE_MAJORLINK) Major link config */ + { + /* Enable major link */ + + regval16 = tcd->csr; + regval16 |= EDMA_TCD_CSR_MAJORELINK; + tcd->csr = regval16; + + /* Set major linked channel */ + + regval16 &= ~EDMA_TCD_CSR_MAJORLINKCH_MASK; + regval16 |= EDMA_TCD_CSR_MAJORLINKCH(linkch->chan); + tcd->csr = regval16; + } +} +#endif + +/**************************************************************************** + * Name: imxrt_tcd_configure + * + * Description: + * Configure all TCD registers to the specified values. 'tcd' is an + * 'overlay' that may refer either to either the TCD register set or to an + * in-memory TCD structure. + * + ****************************************************************************/ + +static inline void imxrt_tcd_configure(struct imxrt_edmatcd_s *tcd, + const struct imxrt_edma_xfrconfig_s *config) +{ + tcd->saddr = config->saddr; + tcd->soff = config->soff; + tcd->attr = EDMA_TCD_ATTR_SSIZE(config->ssize) | /* Transfer Attributes */ + EDMA_TCD_ATTR_DSIZE(config->dsize); +#ifdef CONFIG_IMXRT_EDMA_MOD + tcd->attr |= EDMA_TCD_ATTR_SMOD(config->smod) | /* Transfer Attributes */ + EDMA_TCD_ATTR_DMOD(config->dmod); +#endif + tcd->nbytes = config->nbytes; + tcd->slast = config->flags & EDMA_CONFIG_LOOPSRC ? + -(config->iter * config->nbytes) : 0; + + tcd->daddr = config->daddr; + tcd->doff = config->doff; + tcd->citer = config->iter & EDMA_TCD_CITER_MASK; + tcd->biter = config->iter & EDMA_TCD_BITER_MASK; + tcd->csr = config->flags & EDMA_CONFIG_LOOP_MASK ? + 0 : EDMA_TCD_CSR_DREQ; + tcd->csr |= config->flags & EDMA_CONFIG_INTHALF ? + EDMA_TCD_CSR_INTHALF : 0; + tcd->dlastsga = config->flags & EDMA_CONFIG_LOOPDEST ? + -(config->iter * config->nbytes) : 0; + + /* And special case flags */ + +#ifdef CONFIG_IMXRT_EDMA_ELINK + /* Configure major/minor link mapping */ + + imxrt_tcd_chanlink(config->flags, (struct imxrt_dmach_s *)config->linkch, + tcd); +#endif +} + +/**************************************************************************** + * Name: imxrt_tcd_instantiate + * + * Description: + * Copy an in-memory TCD into eDMA channel TCD registers + * + ****************************************************************************/ + +#if CONFIG_IMXRT_EDMA_NTCD > 0 +static void imxrt_tcd_instantiate(struct imxrt_dmach_s *dmach, + const struct imxrt_edmatcd_s *tcd) +{ + uintptr_t base = IMXRT_EDMA_TCD(dmach->base, dmach->chan); + + /* Push tcd into hardware TCD register */ + + /* Clear DONE bit first, otherwise ESG cannot be set */ + + putreg16(0, base + IMXRT_EDMA_TCD_CSR_OFFSET); + + putreg32(tcd->saddr, base + IMXRT_EDMA_TCD_SADDR_OFFSET); + putreg16(tcd->soff, base + IMXRT_EDMA_TCD_SOFF_OFFSET); + putreg16(tcd->attr, base + IMXRT_EDMA_TCD_ATTR_OFFSET); + putreg32(tcd->nbytes, base + IMXRT_EDMA_TCD_NBYTES_OFFSET); + putreg32(tcd->slast, base + IMXRT_EDMA_TCD_SLAST_SDA_OFFSET); + putreg32(tcd->daddr, base + IMXRT_EDMA_TCD_DADDR_OFFSET); + putreg16(tcd->doff, base + IMXRT_EDMA_TCD_DOFF_OFFSET); + putreg16(tcd->citer, base + IMXRT_EDMA_TCD_CITER_OFFSET); + putreg32(tcd->dlastsga, base + IMXRT_EDMA_TCD_DLAST_SGA_OFFSET); + + putreg16(tcd->csr, base + IMXRT_EDMA_TCD_CSR_OFFSET); + + putreg16(tcd->biter, base + IMXRT_EDMA_TCD_BITER_OFFSET); +} +#endif + +/**************************************************************************** + * Name: imxrt_dmaterminate + * + * Description: + * Terminate the DMA transfer and disable the DMA channel + * + ****************************************************************************/ + +static void imxrt_dmaterminate(struct imxrt_dmach_s *dmach, int result) +{ + uintptr_t base = IMXRT_EDMA_TCD(dmach->base, dmach->chan); +#if CONFIG_IMXRT_EDMA_NTCD > 0 + struct imxrt_edmatcd_s *tcd; + struct imxrt_edmatcd_s *next; +#endif + edma_callback_t callback; + void *arg; + + irqstate_t flags; + + flags = spin_lock_irqsave_nopreempt(&g_edma.lock); + + /* Disable channel IRQ requests */ + + putreg32(EDMA_CH_INT, base + IMXRT_EDMA_CH_INT_OFFSET); + + /* Clear CSR to disable channel. Because if the given channel started, + * transfer CSR will be not zero. Because if it is the last transfer, DREQ + * will be set. If not, ESG will be set. + */ + + putreg32(0, base + IMXRT_EDMA_CH_CSR_OFFSET); + + putreg16(0, base + IMXRT_EDMA_TCD_CSR_OFFSET); + + /* Cancel next TCD transfer. */ + + putreg32(0, base + IMXRT_EDMA_TCD_DLAST_SGA_OFFSET); + +#if CONFIG_IMXRT_EDMA_NTCD > 0 + /* Return all allocated TCDs to the free list */ + + for (tcd = dmach->head; tcd != NULL; tcd = next) + { + /* If channel looped to itself we are done + * if not continue to free tcds in chain + */ + + next = dmach->flags & EDMA_CONFIG_LOOPDEST ? + NULL : (struct imxrt_edmatcd_s *)((uintptr_t)tcd->dlastsga); + + imxrt_tcd_free_nolock(tcd); + } + + dmach->head = NULL; + dmach->tail = NULL; +#endif + + /* Perform the DMA complete callback */ + + callback = dmach->callback; + arg = dmach->arg; + + dmach->callback = NULL; + dmach->arg = NULL; + dmach->state = IMXRT_DMA_IDLE; + + spin_unlock_irqrestore_nopreempt(&g_edma.lock, flags); + + if (callback) + { + callback((DMACH_HANDLE)dmach, arg, true, result); + } +} + +/**************************************************************************** + * Name: imxrt_edma_intstatus + * + * Description: + * DMA interrupt status per eDMA engine and channel. + * + ****************************************************************************/ + +static inline uint32_t imxrt_edma_intstatus(uintptr_t base, uint8_t chan) +{ + /* The status register varies depending on eDMA instance and channel */ + +#ifdef IMXRT_DMA3_BASE + /* eDMA3 uses the normal INT register */ + + if (base == IMXRT_DMA3_BASE) + { + return getreg32(IMXRT_EDMA_INT); + } +#endif + +#ifdef IMXRT_DMA4_BASE + /* eDMA4 has two INT status registers, holding 32 statuses each */ + + if (chan > 31) + { + return getreg32(IMXRT_EDMA_INT_HIGH); + } + + return getreg32(IMXRT_EDMA_INT_LOW); +#endif +} + +/**************************************************************************** + * Name: imxrt_edma_isr + * + * Description: + * DMA interrupt service routine. The vector handler calls this with the + * appropriate parameters. + * + ****************************************************************************/ + +static int imxrt_edma_isr(int irq, void *context, void *arg) +{ + struct imxrt_dmach_s *dmach; + uintptr_t base; + uint32_t regval32; + uint32_t errval32; + uint8_t chan; + int result; + + /* 'arg' should the DMA channel instance. */ + + dmach = (struct imxrt_dmach_s *)arg; + DEBUGASSERT(dmach != NULL); + + chan = dmach->chan; + base = IMXRT_EDMA_TCD(dmach->base, dmach->chan); + + /* Get the eDMA Error Status register value. */ + + errval32 = getreg32(base + IMXRT_EDMA_CH_ES_OFFSET); + + if (errval32 & EDMA_CH_ES_ERR) + { + DEBUGASSERT(dmach->state == IMXRT_DMA_ACTIVE); + + /* Clear the error */ + + putreg32(EDMA_CH_ES_ERR, base + IMXRT_EDMA_CH_ES_OFFSET); + + /* Clear the pending eDMA channel interrupt */ + + putreg32(EDMA_CH_INT, base + IMXRT_EDMA_CH_INT_OFFSET); + + imxrt_dmaterminate(dmach, -EIO); + return OK; + } + + /* Check for an eDMA pending interrupt on this channel */ + + regval32 = imxrt_edma_intstatus(dmach->base, dmach->chan); + if ((regval32 & EDMA_INT(chan & 31)) != 0) + { + /* An interrupt is pending. + * This should only happen if the channel is active. + */ + + DEBUGASSERT(dmach->state == IMXRT_DMA_ACTIVE); + + /* Clear the pending eDMA channel interrupt */ + + putreg32(EDMA_CH_INT, base + IMXRT_EDMA_CH_INT_OFFSET); + + /* Get the eDMA TCD Control and Status register value. */ + + regval32 = getreg32(base + IMXRT_EDMA_CH_CSR_OFFSET); + + /* Check if transfer has finished. */ + + if ((regval32 & EDMA_CH_CSR_DONE) != 0) + { + /* Clear the pending DONE interrupt status. */ + + regval32 |= EDMA_CH_CSR_DONE; + putreg32(regval32, base + IMXRT_EDMA_CH_CSR_OFFSET); + result = OK; + } + else + { + /* Perform the half or end-of-major-cycle DMA callback */ + + if (dmach->callback != NULL) + { + dmach->callback((DMACH_HANDLE)dmach, dmach->arg, false, OK); + } + + return OK; + } + + /* Terminate the transfer when it is done. */ + + if ((dmach->flags & EDMA_CONFIG_LOOP_MASK) == 0) + { + imxrt_dmaterminate(dmach, result); + } + else if (dmach->callback != NULL) + { + dmach->callback((DMACH_HANDLE)dmach, dmach->arg, true, result); + } + } + + return OK; +} + +/**************************************************************************** + * Name: imxrt_edma_interrupt + * + * Description: + * DMA interrupt handler. This function clears the channel major + * interrupt flag and calls the callback function if it is not NULL. + * + * NOTE: For the case using TCD queue, when the major iteration count is + * exhausted, additional operations are performed. These include the + * final address adjustments and reloading of the BITER field into the + * CITER. Assertion of an optional interrupt request also occurs at this + * time, as does a possible fetch of a new TCD from memory using the + * scatter/gather address pointer included in the descriptor (if scatter/ + * gather is enabled). + * + ****************************************************************************/ + +static int imxrt_edma_interrupt(int irq, void *context, void *arg) +{ + struct imxrt_dmach_s *dmach = (struct imxrt_dmach_s *)arg; + +#ifdef IMXRT_DMA3_BASE + if ((irq >= IMXRT_IRQ_DMA3_CH0) && (irq <= IMXRT_IRQ_DMA3_CH31)) + { + /* eDMA3 interrupt has a single source */ + + imxrt_edma_isr(irq, context, dmach); + } +#endif + +#ifdef IMXRT_DMA4_BASE + if ((irq >= IMXRT_IRQ_DMA4_CH0_CH1_CH32_CH33) && + (irq <= IMXRT_IRQ_DMA4_CH30_CH31_CH62_CH63)) + { + /* eDMA4 interrupt has four sources on iMXRT8x */ + + imxrt_edma_isr(irq, context, dmach); + imxrt_edma_isr(irq, context, dmach + 1); + imxrt_edma_isr(irq, context, dmach + 32); + imxrt_edma_isr(irq, context, dmach + 33); + } +#endif + + return OK; +} + +/**************************************************************************** + * Name: imxrt_edma_configure + * + * Description: + * Configure eDMA instance. + * + ****************************************************************************/ + +static void imxrt_edma_configure(uintptr_t base) +{ + uint32_t regval; + + /* Configure the eDMA controllers */ + + regval = getreg32(IMXRT_EDMA_CSR(base)); + regval &= ~(EDMA_CSR_EDBG | EDMA_CSR_ERCA | EDMA_CSR_HAE | EDMA_CSR_GCLC | + EDMA_CSR_GMRC); + +#ifdef CONFIG_IMXRT_EDMA_EDBG + regval |= EDMA_CSR_EDBG; /* Enable Debug */ +#endif +#ifdef CONFIG_IMXRT_EDMA_ERCA + regval |= EDMA_CSR_ERCA; /* Enable Round Robin Channel Arbitration */ +#endif +#ifdef CONFIG_IMXRT_EDMA_ERGA + regval |= EDMA_CSR_ERGA; /* Enable Round Robin Group Arbitration */ +#endif +#ifdef CONFIG_IMXRT_EDMA_HOE + regval |= EDMA_CSR_HAE; /* Halt On Error */ +#endif +#ifdef CONFIG_IMXRT_EDMA_CLM + regval |= EDMA_CSR_GCLC; /* Continuous Link Mode */ +#endif + + putreg32(regval, IMXRT_EDMA_CSR(base)); +} + +/**************************************************************************** + * Name: imxrt_find_free_ch + * + * Description: + * Configure eDMA instance. + * + ****************************************************************************/ + +static struct imxrt_dmach_s * imxrt_find_free_ch(uint16_t dmamux) +{ + struct imxrt_dmach_s *candidate; + uintptr_t base; + unsigned int chndx; + unsigned int offset; + unsigned int max; + + /* eDMA base for MUX */ + + base = imxrt_dmamux_get_dmabase(dmamux); + + /* On RT118x both eDMA3 and eDMA4 have per-channel CH_MUX registers so + * any free channel of the correct engine can be used. + */ + + offset = imxrt_edma_choffset(base); + max = imxrt_edma_chmax(base); + + for (chndx = offset; chndx < max; chndx++) + { + candidate = &g_edma.dmach[chndx]; + if (!candidate->inuse) + { + return candidate; + } + } + + return NULL; +} + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: arm_dma_initialize + * + * Description: + * Initialize the DMA subsystem + * + * Returned Value: + * None + * + ****************************************************************************/ + +void weak_function arm_dma_initialize(void) +{ + struct imxrt_dmach_s *dmach; + uintptr_t base; + int chan; + int i; + + dmainfo("Initialize eDMA\n"); + + /* Configure the instances. */ + + dmach = &g_edma.dmach[0]; + +#ifdef IMXRT_DMA3_BASE + /* Configure eDMA3's LPCG29 (m33_clk_root). That root is already configured + * by the M33 boot ROM so we only need to enable the LPCG. + */ + + imxrt_ccm_gate_on(CCM_LPCG_EDMA3, true); + + imxrt_edma_configure(IMXRT_DMA3_BASE); + + /* Initialize the channel */ + + for (i = 0; i < DMA3_CHANNEL_COUNT; i++, dmach++) + { + dmach->base = IMXRT_DMA3_BASE; + dmach->chan = i; + + irq_attach(IMXRT_IRQ_DMA3_CH0 + i, imxrt_edma_interrupt, dmach); + } +#endif + +#ifdef IMXRT_DMA4_BASE + /* Configure eDMA4's clock root and enable its LPCG. + * + * wakeup_axi_clk_root = SYS_PLL3_OUT (480 MHz) / 2 = 240 MHz. + */ + + imxrt_ccm_configure_root_clock(CCM_CR_WAKEUP_AXI, SYS_PLL3_OUT, 2); + + /* Enable peripheral clock (eDMA4: wakeup_axi_clk_root, LPCG30) */ + + imxrt_ccm_gate_on(CCM_LPCG_EDMA4, true); + + imxrt_edma_configure(IMXRT_DMA4_BASE); + + /* Initialize the channel */ + + for (i = 0; i < DMA4_CHANNEL_COUNT; i++, dmach++) + { + dmach->base = IMXRT_DMA4_BASE; + dmach->chan = i; + + /* Each eDMA4 interrupt is shared by four channels: n, n+1, n+32 and + * n+33. So IRQ (DMA4_CH0_CH1_CH32_CH33 + k) serves the channels + * 2k, 2k+1, 2k+32 and 2k+33, and the 64 channels are covered by the + * 32 lowest channel handles only. Attach every second channel of + * the lower half and pass that channel's handle as the argument. + */ + + if (i < (DMA4_CHANNEL_COUNT / 2) && (i & 0x01) == 0) + { + irq_attach(IMXRT_IRQ_DMA4_CH0_CH1_CH32_CH33 + (i >> 1), + imxrt_edma_interrupt, dmach); + } + } +#endif + +#if CONFIG_IMXRT_EDMA_NTCD > 0 + /* Initialize the list of free TCDs from the pool of pre-allocated TCDs. */ + + imxrt_tcd_initialize(); +#endif + + /* Disable all DMA channel interrupts at the eDMA controller */ + + for (i = 0; i < IMXRT_EDMA_NCHANNELS; i++) + { + /* DMA engine base and TCD channel */ + + base = g_edma.dmach[i].base; + chan = g_edma.dmach[i].chan; + + /* Disable all DMA channels and DMA channel interrupts */ + + putreg32(0, IMXRT_EDMA_TCD(base, chan) + IMXRT_EDMA_CH_CSR_OFFSET); + + /* Clear interrupt if any */ + + putreg32(1, IMXRT_EDMA_TCD(base, chan) + IMXRT_EDMA_CH_INT_OFFSET); + + /* Set all TCD CSR, biter and citer entries to 0 so that + * will be 0 when DONE is not set so that imxrt_dmach_getcount + * reports 0. + */ + + putreg16(0, IMXRT_EDMA_TCD(base, chan) + IMXRT_EDMA_TCD_CSR_OFFSET); + putreg16(0, IMXRT_EDMA_TCD(base, chan) + IMXRT_EDMA_TCD_CITER_OFFSET); + putreg16(0, IMXRT_EDMA_TCD(base, chan) + IMXRT_EDMA_TCD_BITER_OFFSET); + } + +#ifdef IMXRT_DMA3_BASE + /* Clear all pending DMA channel interrupts */ + + putreg32(0xffffffff, IMXRT_EDMA_INT); + + /* Enable the channel interrupts at the NVIC (still disabled at the eDMA + * controller). + */ + + for (i = 0; i < DMA3_IRQ_COUNT; i++) + { + up_enable_irq(IMXRT_IRQ_DMA3_CH0 + i); + } +#endif + +#ifdef IMXRT_DMA4_BASE + /* Clear all pending DMA channel interrupts */ + + putreg32(0xffffffff, IMXRT_EDMA_INT_LOW); + putreg32(0xffffffff, IMXRT_EDMA_INT_HIGH); + + /* Enable the channel interrupts at the NVIC (still disabled at the eDMA + * controller). + */ + + for (i = 0; i < DMA4_IRQ_COUNT; i++) + { + up_enable_irq(IMXRT_IRQ_DMA4_CH0_CH1_CH32_CH33 + i); + } +#endif +} + +/**************************************************************************** + * Name: imxrt_dmach_alloc + * + * Allocate a DMA channel. This function sets aside a DMA channel, + * initializes the DMAMUX for the channel, then gives the caller exclusive + * access to the DMA channel. + * + * Input Parameters: + * + * dmamux - DMAMUX configuration see DMAMUX channel configuration register + * bit-field definitions in hardware/imxrt_dmamux.h. + * Settings include: + * + * DMAMUX_CHCFG_SOURCE Chip-specific DMA source (required) + * DMAMUX_CHCFG_TRIG DMA Channel Trigger Enable (optional) + * DMAMUX_CHCFG_ENBL DMA Mux Channel Enable (required) + * + * A value of zero will disable the DMAMUX channel. + * dchpri - DCHPRI channel priority configuration. See DCHPRI channel + * configuration register bit-field definitions in + * hardware/imxrt_edma.h. Meaningful settings include: + * + * EDMA_DCHPRI_CHPRI Channel Arbitration Priority + * DCHPRI_DPA Disable Preempt Ability + * DCHPRI_ECP Enable Channel Preemption + * + * The power-on default, 0x05, is a reasonable choice. + * + * Returned Value: + * If a DMA channel is available, this function returns a non-NULL, void* + * DMA channel handle. NULL is returned on any failure. + * + ****************************************************************************/ + +DMACH_HANDLE imxrt_dmach_alloc(uint32_t dmamux, uint8_t dchpri) +{ + struct imxrt_dmach_s *dmach; + uintptr_t base; + uint32_t regval; + int ret; + + /* Search for an available DMA channel */ + + dmach = NULL; + ret = nxmutex_lock(&g_edma.chlock); + if (ret < 0) + { + return NULL; + } + + /* Find channel for this DMA MUX */ + + dmach = imxrt_find_free_ch(dmamux); + if (dmach) + { + dmach->inuse = true; + dmach->state = IMXRT_DMA_IDLE; + dmach->dmamux = dmamux & EDMA_MUX_MASK; + + /* TCD register base */ + + base = IMXRT_EDMA_TCD(dmach->base, dmach->chan); + + /* Clear any pending interrupts on the channel */ + + putreg32(0, base + IMXRT_EDMA_CH_CSR_OFFSET); + + /* Make sure that the channel is disabled. */ + + putreg32(EDMA_CH_INT, base + IMXRT_EDMA_CH_INT_OFFSET); + + regval = getreg32(base + IMXRT_EDMA_CH_SBR_OFFSET); + regval |= EDMA_CH_SBR_EMI | EDMA_CH_SBR_SEC | EDMA_CH_SBR_PAL; + putreg32(regval, base + IMXRT_EDMA_CH_SBR_OFFSET); + + /* Set the DMAMUX source */ + + if (imxrt_edma_tcdhasmux(dmach->base)) + { + /* Set reset value first to CH MUX */ + + putreg8(0, base + IMXRT_EDMA_CH_MUX_OFFSET); + dmainfo("CH%d: MUX:%u->%p\n", dmach->chan, dmach->dmamux, + (void *)(base + IMXRT_EDMA_CH_MUX_OFFSET)); + putreg8(dmach->dmamux, base + IMXRT_EDMA_CH_MUX_OFFSET); + } + } + + nxmutex_unlock(&g_edma.chlock); + + /* Show the result of the allocation */ + + if (dmach != NULL) + { + dmainfo("CH%d: returning dmach: %p\n", dmach->chan, dmach); + } + else + { + dmaerr("ERROR: Failed allocate eDMA channel\n"); + } + + return (DMACH_HANDLE)dmach; +} + +/**************************************************************************** + * Name: imxrt_dmach_free + * + * Description: + * Release a DMA channel. NOTE: The 'handle' used in this argument must + * NEVER be used again until imxrt_dmach_alloc() is called again to + * re-gain a valid handle. + * + * Returned Value: + * None + * + ****************************************************************************/ + +void imxrt_dmach_free(DMACH_HANDLE handle) +{ + struct imxrt_dmach_s *dmach = (struct imxrt_dmach_s *)handle; + uintptr_t base = IMXRT_EDMA_TCD(dmach->base, dmach->chan); + + dmainfo("dmach: %p\n", dmach); + DEBUGASSERT(dmach != NULL && dmach->inuse && + dmach->state != IMXRT_DMA_ACTIVE); + + /* Mark the channel no longer in use. Clearing the inuse flag is an atomic + * operation and so should be safe. + */ + + dmach->flags = 0; + dmach->inuse = false; /* No longer in use */ + dmach->state = IMXRT_DMA_IDLE; /* Better not be active! */ + + /* Make sure that the channel is disabled. */ + + putreg32(EDMA_CH_INT, base + IMXRT_EDMA_CH_INT_OFFSET); + + /* Disable the associated DMAMUX */ + + if (imxrt_edma_tcdhasmux(dmach->base)) + { + putreg8(0, base + IMXRT_EDMA_CH_MUX_OFFSET); + } +} + +/**************************************************************************** + * Name: imxrt_dmach_xfrsetup + * + * Description: + * This function adds the eDMA transfer to the DMA sequence. The request + * is setup according to the content of the transfer configuration + * structure. For "normal" DMA, imxrt_dmach_xfrsetup is called only once. + * Scatter/gather DMA is accomplished by calling this function repeatedly, + * once for each transfer in the sequence. Scatter/gather DMA processing + * is enabled automatically when the second transfer configuration is + * received. + * + * This function may be called multiple times to handle multiple, + * discontinuous transfers (scatter-gather) + * + * Input Parameters: + * handle - DMA channel handle created by imxrt_dmach_alloc() + * config - A DMA transfer configuration instance, populated by the + * The content of 'config' describes the transfer + * + * Returned Value + * Zero (OK) is returned on success; a negated errno value is returned on + * any failure. + * + ****************************************************************************/ + +int imxrt_dmach_xfrsetup(DMACH_HANDLE handle, + const struct imxrt_edma_xfrconfig_s *config) +{ + struct imxrt_dmach_s *dmach = (struct imxrt_dmach_s *)handle; + uintptr_t base = IMXRT_EDMA_TCD(dmach->base, dmach->chan); +#if CONFIG_IMXRT_EDMA_NTCD > 0 + struct imxrt_edmatcd_s *tcd; + struct imxrt_edmatcd_s *prev; + uint16_t mask = config->flags & EDMA_CONFIG_INTMAJOR ? 0 : + EDMA_TCD_CSR_INTMAJOR; + uint16_t regval16; +#else + uint32_t regval32; +#endif + + DEBUGASSERT(dmach != NULL); + dmainfo("dmach%u: %p config: %p\n", dmach->chan, dmach, config); + + dmach->flags = config->flags; + +#if CONFIG_IMXRT_EDMA_NTCD > 0 + /* Scatter/gather DMA is supported */ + + /* Allocate a TCD, waiting if necessary */ + + tcd = imxrt_tcd_alloc(); + + /* Configure current TCD block transfer. */ + + imxrt_tcd_configure(tcd, config); + + /* Enable the interrupt when the major iteration count completes for this + * TCD. For "normal" DMAs, this will correspond to the DMA DONE + * interrupt; for scatter gather DMAs, multiple interrupts will be + * generated with the final being the DONE interrupt. + */ + + tcd->csr |= EDMA_TCD_CSR_INTMAJOR; + + /* Is this the first descriptor in the list? */ + + if (dmach->head == NULL) + { + /* Yes.. add it to the list */ + + dmach->head = tcd; + dmach->tail = tcd; + + /* And instantiate the first TCD in the DMA channel TCD registers. */ + + imxrt_tcd_instantiate(dmach, tcd); + } + else + { + /* Cannot mix transfer types */ + + if (dmach->flags & EDMA_CONFIG_LOOP_MASK) + { + imxrt_tcd_free(tcd); + return -EINVAL; + } + + /* Chain from previous descriptor in the list. */ + + /* Enable scatter/gather feature in the previous TCD. */ + + prev = dmach->tail; + regval16 = prev->csr; + regval16 &= ~(EDMA_TCD_CSR_DREQ | mask); + regval16 |= EDMA_TCD_CSR_ESG; + prev->csr = regval16; + + prev->dlastsga = (uint32_t)((uintptr_t)tcd); + dmach->tail = tcd; + + /* Clean cache associated with the previous TCD memory */ + + up_clean_dcache((uintptr_t)prev, + (uintptr_t)prev + sizeof(struct imxrt_edmatcd_s)); + + /* Check if the TCD block in the DMA channel registers is the same as + * the previous previous TCD. This can happen if the previous TCD was + * the first TCD and has already be loaded into the TCD registers. + */ + + if (dmach->head == prev) + { + /* Enable scatter/gather also in the TCD registers. */ + + regval16 = getreg16(base + IMXRT_EDMA_TCD_CSR_OFFSET); + regval16 &= ~(EDMA_TCD_CSR_DREQ | mask); + regval16 |= EDMA_TCD_CSR_ESG; + putreg16(regval16, base + IMXRT_EDMA_TCD_CSR_OFFSET); + + putreg32((uint32_t)((uintptr_t)tcd), + base + IMXRT_EDMA_TCD_DLAST_SGA_OFFSET); + } + } + + /* Clean cache associated with the TCD memory */ + + up_clean_dcache((uintptr_t)tcd, + (uintptr_t)tcd + sizeof(struct imxrt_edmatcd_s)); +#else + + /* Scatter/gather DMA is NOT supported */ + + /* Check if eDMA is busy: if the channel has started transfer, CSR will be + * non-zero. + */ + + regval32 = getreg32(base + IMXRT_EDMA_CH_CSR_OFFSET); + + if (regval32 != 0 && (regval32 & EDMA_CH_CSR_DONE) == 0) + { + return -EBUSY; + } + + /* Configure channel TCD registers to the values specified in config. */ + + imxrt_tcd_configure((struct imxrt_edmatcd_s *) + (base + IMXRT_EDMA_TCD_SADDR_OFFSET), config); + + /* Enable the DONE interrupt when the major iteration count completes. */ + + modifyreg16(base + IMXRT_EDMA_TCD_CSR_OFFSET, 0, EDMA_TCD_CSR_INTMAJOR); +#endif + + dmach->state = IMXRT_DMA_CONFIGURED; + return OK; +} + +/**************************************************************************** + * Name: imxrt_dmach_start + * + * Description: + * Start the DMA transfer. This function should be called after the final + * call to imxrt_dmach_xfrsetup() in order to avoid race conditions. + * + * At the conclusion of each major DMA loop, a callback to the user + * provided function is made: |For "normal" DMAs, this will correspond to + * the DMA DONE interrupt; for scatter gather DMAs, + * this will be generated with the final TCD. + * + * At the conclusion of the DMA, the DMA channel is reset, all TCDs are + * freed, and the callback function is called with the the success/fail + * result of the DMA. + * + * NOTE: On Rx DMAs (peripheral-to-memory or memory-to-memory), it is + * necessary to invalidate the destination memory. That is not done + * automatically by the DMA module. Invalidation of the destination memory + * regions is the responsibility of the caller. + * + * Input Parameters: + * handle - DMA channel handle created by imxrt_dmach_alloc() + * callback - The callback to be invoked when the DMA is completes or is + * aborted. + * arg - An argument that accompanies the callback + * + * Returned Value: + * Zero (OK) is returned on success; a negated errno value is returned on + * any failure. + * + ****************************************************************************/ + +int imxrt_dmach_start(DMACH_HANDLE handle, edma_callback_t callback, + void *arg) +{ + struct imxrt_dmach_s *dmach = (struct imxrt_dmach_s *)handle; + uintptr_t base = IMXRT_EDMA_TCD(dmach->base, dmach->chan); + irqstate_t flags; + uint32_t regval; + uint8_t chan; + + DEBUGASSERT(dmach != NULL && dmach->state == IMXRT_DMA_CONFIGURED); + chan = dmach->chan; + dmainfo("dmach%u: %p callback: %p arg: %p\n", chan, dmach, callback, arg); + + /* Save the callback info. This will be invoked when the DMA completes */ + + flags = spin_lock_irqsave(&g_edma.lock); + dmach->callback = callback; + dmach->arg = arg; + +#if CONFIG_IMXRT_EDMA_NTCD > 0 + /* Although it is not recommended, it might be possible to call this + * function multiple times while adding TCDs on the fly. + */ + + if (dmach->state != IMXRT_DMA_ACTIVE) +#endif + { + dmach->state = IMXRT_DMA_ACTIVE; + + regval = getreg32(base + IMXRT_EDMA_CH_CSR_OFFSET); + regval |= EDMA_CH_CSR_ERQ | EDMA_CH_CSR_EEI; + putreg32(regval, base + IMXRT_EDMA_CH_CSR_OFFSET); + + if ((dmach->flags & EDMA_CONFIG_SWSTART) != 0) + { + putreg16(getreg16(base + IMXRT_EDMA_TCD_CSR_OFFSET) | + EDMA_TCD_CSR_START, + base + IMXRT_EDMA_TCD_CSR_OFFSET); + } + } + + spin_unlock_irqrestore(&g_edma.lock, flags); + return OK; +} + +/**************************************************************************** + * Name: imxrt_dmach_stop + * + * Description: + * Cancel the DMA. After imxrt_dmach_stop() is called, the DMA channel + * is reset, all TCDs are freed, and imxrt_dmarx/txsetup() must be called + * before imxrt_dmach_start() can be called again. + * + * Input Parameters: + * handle - DMA channel handle created by imxrt_dmach_alloc() + * + * Returned Value: + * None. + * + ****************************************************************************/ + +void imxrt_dmach_stop(DMACH_HANDLE handle) +{ + struct imxrt_dmach_s *dmach = (struct imxrt_dmach_s *)handle; + + dmainfo("dmach: %p\n", dmach); + DEBUGASSERT(dmach != NULL); + + imxrt_dmaterminate(dmach, -EINTR); +} + +/**************************************************************************** + * Name: imxrt_dmach_getcount + * + * Description: + * This function checks the TCD (Task Control Descriptor) status for a + * specified eDMA channel and returns the the number of major loop counts + * that have not finished. + * + * NOTES: + * 1. This function can only be used to get unfinished major loop count of + * transfer without the next TCD, or it might be inaccuracy. + * 2. The unfinished/remaining transfer bytes cannot be obtained directly + * from registers while the channel is running. + * + * Because to calculate the remaining bytes, the initial NBYTES configured + * in DMA_TCDn_NBYTES_MLNO register is needed while the eDMA IP does not + * support getting it while a channel is active. In another words, the + * NBYTES value reading is always the actual (decrementing) NBYTES value + * the dma_engine is working with while a channel is running. + * Consequently, to get the remaining transfer bytes, a software-saved + * initial value of NBYTES (for example copied before enabling the channel) + * is needed. The formula to calculate it is shown below: + * + * RemainingBytes = RemainingMajorLoopCount * + * NBYTES(initially configured) + * + * Input Parameters: + * handle - DMA channel handle created by imxrt_dmach_alloc() + * + * Returned Value: + * Major loop count which has not been transferred yet for the current TCD. + * + ****************************************************************************/ + +unsigned int imxrt_dmach_getcount(DMACH_HANDLE handle) +{ + struct imxrt_dmach_s *dmach = (struct imxrt_dmach_s *)handle; + uintptr_t base = IMXRT_EDMA_TCD(dmach->base, dmach->chan); + unsigned int remaining = 0; + uintptr_t regval32; + uint16_t regval16; + + DEBUGASSERT(dmach != NULL); + + /* If the DMA is done, then the remaining count is zero */ + + regval32 = getreg32(base + IMXRT_EDMA_CH_CSR_OFFSET); + + if ((regval32 & EDMA_CH_CSR_DONE) == 0) + { + /* Calculate the unfinished bytes */ + + regval16 = getreg16(base + IMXRT_EDMA_TCD_CITER_OFFSET); + + if ((regval16 & EDMA_TCD_CITER_ELINK) != 0) + { + remaining = (regval16 & EDMA_TCD_CITER_MASK_ELINK) >> + EDMA_TCD_CITER_SHIFT; + } + else + { + remaining = (regval16 & EDMA_TCD_CITER_MASK) >> + EDMA_TCD_CITER_SHIFT; + } + } + + return remaining; +} + +/**************************************************************************** + * Name: imxrt_dmach_idle + * + * Description: + * This function checks if the dma is idle + * + * Returned Value: + * 0 - if idle + * !0 - not + * + ****************************************************************************/ + +unsigned int imxrt_dmach_idle(DMACH_HANDLE handle) +{ + struct imxrt_dmach_s *dmach = (struct imxrt_dmach_s *)handle; + + return dmach->state == IMXRT_DMA_IDLE ? 0 : -1; +} + +/**************************************************************************** + * Name: imxrt_dmasample + * + * Description: + * Sample DMA register contents + * + * Assumptions: + * - DMA handle allocated by imxrt_dmach_alloc() + * + ****************************************************************************/ + +#ifdef CONFIG_DEBUG_DMA +void imxrt_dmasample(DMACH_HANDLE handle, struct imxrt_dmaregs_s *regs) +{ + struct imxrt_dmach_s *dmach = (struct imxrt_dmach_s *)handle; + unsigned int chan; + irqstate_t flags; + uintptr_t base = IMXRT_EDMA_TCD(dmach->base, dmach->chan); + + DEBUGASSERT(dmach != NULL && regs != NULL); + chan = dmach->chan; + regs->chan = chan; + + /* eDMA Global Registers */ + + flags = spin_lock_irqsave(&g_edma.lock); + + /* REVISIT: eDMA4 does not show INT_HIGH / HRS_HIGH values correctly */ + + regs->cr = getreg32(IMXRT_EDMA_CSR(base)); /* Control */ + regs->es = getreg32(IMXRT_EDMA_ES(base)); /* Error Status */ + regs->req = getreg32(IMXRT_EDMA_INT); /* Interrupt Request */ + regs->hrs = getreg32(IMXRT_EDMA_HRS); /* Hardware Request Status */ + + /* eDMA TCD */ + + regs->saddr = getreg32(base + IMXRT_EDMA_TCD_SADDR_OFFSET); + regs->soff = getreg16(base + IMXRT_EDMA_TCD_SOFF_OFFSET); + regs->attr = getreg16(base + IMXRT_EDMA_TCD_ATTR_OFFSET); + regs->nbml = getreg32(base + IMXRT_EDMA_TCD_NBYTES_OFFSET); + regs->slast = getreg32(base + IMXRT_EDMA_TCD_SLAST_SDA_OFFSET); + regs->daddr = getreg32(base + IMXRT_EDMA_TCD_DADDR_OFFSET); + regs->doff = getreg16(base + IMXRT_EDMA_TCD_DOFF_OFFSET); + regs->citer = getreg16(base + IMXRT_EDMA_TCD_CITER_OFFSET); + regs->dlastsga = getreg32(base + IMXRT_EDMA_TCD_DLAST_SGA_OFFSET); + regs->csr = getreg16(base + IMXRT_EDMA_TCD_CSR_OFFSET); + regs->biter = getreg16(base + IMXRT_EDMA_TCD_BITER_OFFSET); + + /* DMAMUX registers */ + + if (imxrt_edma_tcdhasmux(dmach->base)) + { + regs->dmamux = getreg32(base + IMXRT_EDMA_CH_MUX_OFFSET); + } + else + { + regs->dmamux = 0; + } + + spin_unlock_irqrestore(&g_edma.lock, flags); +} +#endif /* CONFIG_DEBUG_DMA */ + +/**************************************************************************** + * Name: imxrt_dmadump + * + * Description: + * Dump previously sampled DMA register contents + * + * Assumptions: + * - DMA handle allocated by imxrt_dmach_alloc() + * + ****************************************************************************/ + +#ifdef CONFIG_DEBUG_DMA +void imxrt_dmadump(const struct imxrt_dmaregs_s *regs, const char *msg) +{ + unsigned int chan; + + DEBUGASSERT(regs != NULL && msg != NULL); + + chan = regs->chan; + DEBUGASSERT(chan < IMXRT_EDMA_NCHANNELS); + + dmainfo("%s\n", msg); + dmainfo(" eDMA Global Registers:\n"); + dmainfo(" CR: %08x\n", (unsigned int)regs->cr); + dmainfo(" ES: %08x\n", (unsigned int)regs->es); + dmainfo(" INT: %08x\n", (unsigned int)regs->req); + dmainfo(" EARS: %08x\n", (unsigned int)regs->hrs); + + /* eDMA Channel registers */ + + dmainfo(" eDMA Channel %u Registers:\n", chan); + dmainfo(" DCHPRI: %02x\n", regs->dchpri); + + /* eDMA TCD */ + + dmainfo(" eDMA Channel %u TCD Registers:\n", chan); + dmainfo(" SADDR: %08x\n", (unsigned int)regs->saddr); + dmainfo(" SOFF: %04x\n", (unsigned int)regs->soff); + dmainfo(" ATTR: %04x\n", (unsigned int)regs->attr); + dmainfo(" NBML: %05x\n", (unsigned int)regs->nbml); + dmainfo(" SLAST: %05x\n", (unsigned int)regs->slast); + dmainfo(" DADDR: %05x\n", (unsigned int)regs->daddr); + dmainfo(" DOFF: %04x\n", (unsigned int)regs->doff); + dmainfo(" CITER: %04x\n", (unsigned int)regs->citer); + dmainfo(" DLASTSGA: %08x\n", (unsigned int)regs->dlastsga); + dmainfo(" CSR: %04x\n", (unsigned int)regs->csr); + dmainfo(" BITER: %04x\n", (unsigned int)regs->biter); + + /* DMAMUX registers */ + + dmainfo(" DMAMUX Channel %u Registers:\n", chan); + dmainfo(" DMAMUX: %08x\n", (unsigned int)regs->dmamux); +} +#endif /* CONFIG_DEBUG_DMA */ +#endif /* CONFIG_IMXRT_EDMA */ diff --git a/arch/arm/src/imxrt/imxrt_gpio.h b/arch/arm/src/imxrt/imxrt_gpio.h index 049e43d850e15..5523cdbbc567a 100644 --- a/arch/arm/src/imxrt/imxrt_gpio.h +++ b/arch/arm/src/imxrt/imxrt_gpio.h @@ -33,6 +33,17 @@ #include #include "chip.h" + +#ifdef CONFIG_IMXRT_RGPIO + +/* The RGPIO IP block (used by RT118x) has its public interface in a + * separate header and driver source. + */ + +# include "imxrt_rgpio.h" + +#else + #include "hardware/imxrt_gpio.h" /**************************************************************************** @@ -380,4 +391,6 @@ int imxrt_dump_gpio(uint32_t pinset, const char *msg); #if defined(__cplusplus) } #endif + +#endif /* CONFIG_IMXRT_RGPIO */ #endif /* __ARCH_ARM_SRC_IMXRT_IMXRT_GPIO_H */ diff --git a/arch/arm/src/imxrt/imxrt_iomuxc.h b/arch/arm/src/imxrt/imxrt_iomuxc.h index 2d32f56f653bd..d6973891de767 100644 --- a/arch/arm/src/imxrt/imxrt_iomuxc.h +++ b/arch/arm/src/imxrt/imxrt_iomuxc.h @@ -30,10 +30,13 @@ #include /* IMXRT117X IOMUX Differs too much from IMXRT10XX - * hence we use a VER2 driver + * hence we use a VER2 driver. IMXRT118x uses another (generation 3) + * IOMUXC IP; that is IMXRT_IOMUX_VER3. */ -#ifdef CONFIG_IMXRT_IOMUX_VER2 +#ifdef CONFIG_IMXRT_IOMUX_VER3 +#include "imxrt_iomuxc_ver3.h" +#elif defined(CONFIG_IMXRT_IOMUX_VER2) #include "imxrt_iomuxc_ver2.h" #else #include "imxrt_iomuxc_ver1.h" diff --git a/arch/arm/src/imxrt/imxrt_iomuxc_ver3.c b/arch/arm/src/imxrt/imxrt_iomuxc_ver3.c new file mode 100644 index 0000000000000..995328d2e1f0f --- /dev/null +++ b/arch/arm/src/imxrt/imxrt_iomuxc_ver3.c @@ -0,0 +1,194 @@ +/**************************************************************************** + * arch/arm/src/imxrt/imxrt_iomuxc_ver3.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +#include "arm_internal.h" +#include "hardware/imxrt_memorymap.h" +#include "imxrt_iomuxc_ver3.h" + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/* Descriptors for the two IOMUXC instances on RT1180. These four numbers + * per bank are all we need to derive MUX_CTL, PAD_CTL and DAISY register + * addresses from a packed IMXRT_PADCFG value using pure arithmetic. + * + * ctl_first : offset of MUX_CTL[0] within the bank + * pad_delta : PAD_CTL[i] = MUX_CTL[i] + pad_delta (constant per bank) + * dsy_first : offset of DAISY[0] within the bank + */ + +static const struct imxrt_iomux_bank_s g_bank[IMXRT_PADCFG_NBANKS] = +{ + [IMXRT_PADCFG_BANK_MAIN] = + { + .base = IMXRT_IOMUXC_WKUP_BASE, /* 0x42a1_0000 */ + .ctl_first = 0x010u, + .pad_delta = 0x248u, + .dsy_first = 0x4a0u, + }, + [IMXRT_PADCFG_BANK_AON] = + { + .base = IMXRT_IOMUXC_AON_BASE, /* 0x443c_0000 */ + .ctl_first = 0x000u, + .pad_delta = 0x074u, + .dsy_first = 0x0e8u, + }, +}; + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: imxrt_iomux_ctlreg + * + * Description: + * Compute the SW_MUX_CTL register address for a packed padcfg value. + * + ****************************************************************************/ + +static inline uintptr_t imxrt_iomux_ctlreg(uint32_t padcfg) +{ + const struct imxrt_iomux_bank_s *b = &g_bank[IMXRT_PADCFG_PADBANK(padcfg)]; + + return (uintptr_t)b->base + b->ctl_first + + IMXRT_PADCFG_PADIDX(padcfg) * 4u; +} + +/**************************************************************************** + * Name: imxrt_iomux_padreg + * + * Description: + * Compute the SW_PAD_CTL register address for a packed padcfg value. + * + ****************************************************************************/ + +static inline uintptr_t imxrt_iomux_padreg(uint32_t padcfg) +{ + const struct imxrt_iomux_bank_s *b = &g_bank[IMXRT_PADCFG_PADBANK(padcfg)]; + + return imxrt_iomux_ctlreg(padcfg) + b->pad_delta; +} + +/**************************************************************************** + * Name: imxrt_iomux_dsyreg + * + * Description: + * Compute the DAISY (input) register address for a packed padcfg value, + * or 0 if the pad/alt has no input daisy. Note that the daisy bank + * may differ from the pad bank (a pin on one IOMUXC can route to a + * peripheral whose input mux lives on the other IOMUXC). + * + ****************************************************************************/ + +static inline uintptr_t imxrt_iomux_dsyreg(uint32_t padcfg) +{ + uint32_t dsy_idx = IMXRT_PADCFG_DSYIDX(padcfg); + const struct imxrt_iomux_bank_s *b; + + if (dsy_idx == IMXRT_PADCFG_NO_DSYIDX) + { + return 0; + } + + b = &g_bank[IMXRT_PADCFG_DSYBANK(padcfg)]; + return (uintptr_t)b->base + b->dsy_first + dsy_idx * 4u; +} + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: imxrt_iomux_configure + ****************************************************************************/ + +int imxrt_iomux_configure(imxrt_pinset_t pinset) +{ + uint32_t padcfg = IMXRT_PINSET_PADCFG(pinset); + uintptr_t ctlreg = imxrt_iomux_ctlreg(padcfg); + uintptr_t padreg = imxrt_iomux_padreg(padcfg); + uintptr_t dsyreg = imxrt_iomux_dsyreg(padcfg); + uint32_t mux = IMXRT_PADCFG_MUX(padcfg); + uint32_t mux_side = IMXRT_PINSET_MUXSIDE(pinset); + + /* Write MUX_CTL: ALT | mux side-band bits (currently only SION) */ + + putreg32(IOMUXC_MUX_MODE_ALT(mux) | mux_side, ctlreg); + + /* Write PAD_CTL */ + + putreg32(IMXRT_PINSET_PADCTL(pinset), padreg); + + /* Route the peripheral input mux (daisy) if this alt uses one */ + + if (dsyreg != 0) + { + putreg32(IMXRT_PADCFG_DSY(padcfg), dsyreg); + } + + return OK; +} + +/**************************************************************************** + * Name: imxrt_iomux_gpio + * + * Description: + * Force a pad to GPIO mode. On RT1180 dedicated GPIO_IOxx pads on the + * main IOMUXC take ALT0 for GPIO; all other pads (including AON pads) + * use ALT5. + * + ****************************************************************************/ + +int imxrt_iomux_gpio(imxrt_pinset_t pinset, bool sion) +{ + uint32_t padcfg = IMXRT_PINSET_PADCFG(pinset); + uintptr_t ctlreg = imxrt_iomux_ctlreg(padcfg); + uintptr_t padreg = imxrt_iomux_padreg(padcfg); + uint32_t reg_sion = sion ? IOMUXC_MUX_SION_ON : 0; + uint32_t alt; + + /* On the main IOMUXC, the dedicated GPIO_IO pads (there is no other + * function on ALT0) select GPIO via ALT0. Every other pad selects GPIO + * via ALT5. The IOMUXC_PAD_..._GPIOx_IOn macros generated from the SDK + * already carry the correct ALT (0 or 5) in the padcfg field, so we + * simply write the pre-encoded ALT and SION. + */ + + alt = IMXRT_PADCFG_MUX(padcfg); + + putreg32(IOMUXC_MUX_MODE_ALT(alt) | reg_sion, ctlreg); + putreg32(IMXRT_PINSET_PADCTL(pinset), padreg); + + return OK; +} diff --git a/arch/arm/src/imxrt/imxrt_iomuxc_ver3.h b/arch/arm/src/imxrt/imxrt_iomuxc_ver3.h new file mode 100644 index 0000000000000..7df1c027acda3 --- /dev/null +++ b/arch/arm/src/imxrt/imxrt_iomuxc_ver3.h @@ -0,0 +1,159 @@ +/**************************************************************************** + * arch/arm/src/imxrt/imxrt_iomuxc_ver3.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_IMXRT_IMXRT_IOMUXC_VER3_H +#define __ARCH_ARM_SRC_IMXRT_IMXRT_IOMUXC_VER3_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include + +#include "hardware/rt118x/imxrt118x_iomuxc.h" +#include "hardware/rt118x/imxrt118x_pinmux.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* imxrt_pinset_t is a 64-bit descriptor packing all four sub-fields + * needed to fully program a physical pad: + * + * bits 0..31 : padcfg IMXRT_PADCFG(...) constant (pad_bank, + * pad_idx, ALT, dsy_bank, dsy_idx, dsy_val). + * bits 32..39 : pad_ctl SW_PAD_CTL byte. + * bits 40..47 : mux_side SW_MUX_CTL side-band bits in register order + * (currently only SION at bit 4). + * bits 48..63 : gpio 16-bit gpio pinset (port | pin | mode | + * output value | int cfg | int both). + */ + +#define IMXRT_PINSET_PADCFG_SHIFT (0) +#define IMXRT_PINSET_PADCTL_SHIFT (32) +#define IMXRT_PINSET_MUXSIDE_SHIFT (40) +#define IMXRT_PINSET_GPIO_SHIFT (48) + +#define IMXRT_PINSET_PADCFG(_p) ((uint32_t)(_p)) +#define IMXRT_PINSET_PADCTL(_p) ((uint8_t)((_p) >> IMXRT_PINSET_PADCTL_SHIFT)) +#define IMXRT_PINSET_MUXSIDE(_p) ((uint8_t)((_p) >> IMXRT_PINSET_MUXSIDE_SHIFT)) +#define IMXRT_PINSET_GPIO(_p) ((uint16_t)((_p) >> IMXRT_PINSET_GPIO_SHIFT)) + +/* Compose a full 64-bit pinset from its four sub-fields. See + * IOMUX_PIN and IOMUX_GPIO below for the convenient wrappers. + */ + +#define IOMUX_CFG(_padcfg, _pad_ctl, _mux_side, _gpio) \ + (((uint64_t)(uint32_t)(_padcfg)) | \ + (((uint64_t)(uint8_t)(_pad_ctl)) << IMXRT_PINSET_PADCTL_SHIFT) | \ + (((uint64_t)(uint8_t)(_mux_side)) << IMXRT_PINSET_MUXSIDE_SHIFT) | \ + (((uint64_t)(uint16_t)(_gpio)) << IMXRT_PINSET_GPIO_SHIFT)) + +/* Peripheral pin: no GPIO fields. `mux_side' is OR'd into SW_MUX_CTL + * verbatim; the only defined bit is IOMUXC_MUX_SION_ON. + */ + +#define IOMUX_PIN(_padcfg, _pad_ctl, _mux_side) \ + IOMUX_CFG(_padcfg, _pad_ctl, _mux_side, 0xc000u) + +/* GPIO pin: caller supplies pad_ctl and a 16-bit gpio pinset built from + * GPIO_INPUT / GPIO_OUTPUT / GPIO_PORTn / GPIO_PINn / etc. SION is 0 + * because a GPIO output only needs to sample the pad when the ALT is + * routed elsewhere. + */ + +#define IOMUX_GPIO(_padcfg, _pad_ctl, _gpio) \ + IOMUX_CFG(_padcfg, _pad_ctl, 0, _gpio) + +/**************************************************************************** + * Public Types + ****************************************************************************/ + +/* Packed 64-bit pad + GPIO descriptor. See IOMUX_CFG above for the + * bit layout. Peripheral drivers and board files should treat this + * type as opaque and use the IOMUX_PIN / IOMUX_GPIO macros to build + * values and the IMXRT_PINSET_* macros (or the driver entry points) to + * consume them. + */ + +typedef uint64_t imxrt_pinset_t; + +/**************************************************************************** + * Public Function Prototypes + ****************************************************************************/ + +#undef EXTERN +#if defined(__cplusplus) +#define EXTERN extern "C" +extern "C" +{ +#else +#define EXTERN extern +#endif + +/**************************************************************************** + * Name: imxrt_iomux_configure + * + * Description: + * Program a pad's SW_MUX_CTL, SW_PAD_CTL and (if applicable) input + * DAISY select register from a packed pinset. + * + * Input Parameters: + * pinset - the pad configuration built with IOMUX_PIN() or IOMUX_GPIO() + * + * Returned Value: + * Zero (OK) on success; a negated errno value on failure. + * + ****************************************************************************/ + +int imxrt_iomux_configure(imxrt_pinset_t pinset); + +/**************************************************************************** + * Name: imxrt_iomux_gpio + * + * Description: + * Forcibly set a pad to GPIO mode. This overrides and disconnects any + * peripheral that was previously routed through the pad. The GPIO ALT + * is selected automatically based on the pad (ALT5 for most pads, ALT0 + * for dedicated GPIO_IO pads on the main IOMUXC). + * + * Input Parameters: + * pinset - the pad configuration. Only the padcfg and pad_ctl fields + * are used to identify the pad and program SW_PAD_CTL. + * sion - if true; sets SION, otherwise clears it. + * + * Returned Value: + * Zero (OK) on success; a negated errno value on failure. + * + ****************************************************************************/ + +int imxrt_iomux_gpio(imxrt_pinset_t pinset, bool sion); + +#undef EXTERN +#if defined(__cplusplus) +} +#endif + +#endif /* __ARCH_ARM_SRC_IMXRT_IMXRT_IOMUXC_VER3_H */ diff --git a/arch/arm/src/imxrt/imxrt_irq.c b/arch/arm/src/imxrt/imxrt_irq.c index 3a8a87059db3d..b311685cd71fe 100644 --- a/arch/arm/src/imxrt/imxrt_irq.c +++ b/arch/arm/src/imxrt/imxrt_irq.c @@ -200,12 +200,20 @@ static void imxrt_dumpnvic(const char *msg, int irq) getreg32(NVIC_IRQ204_207_PRIORITY)); #endif #if IMXRT_IRQ_NEXTINT > 208 - irqinfo(" %08x %08x %08x\n", + irqinfo(" %08x %08x %08x %08x\n", getreg32(NVIC_IRQ208_211_PRIORITY), getreg32(NVIC_IRQ212_215_PRIORITY), - getreg32(NVIC_IRQ216_219_PRIORITY)); + getreg32(NVIC_IRQ216_219_PRIORITY), + getreg32(NVIC_IRQ220_223_PRIORITY)); +#endif +#if IMXRT_IRQ_NEXTINT > 224 + irqinfo(" %08x %08x %08x %08x\n", + getreg32(NVIC_IRQ224_227_PRIORITY), + getreg32(NVIC_IRQ228_231_PRIORITY), + getreg32(NVIC_IRQ232_235_PRIORITY), + getreg32(NVIC_IRQ236_239_PRIORITY)); #endif -#if IMXRT_IRQ_NEXTINT > 218 +#if IMXRT_IRQ_NEXTINT > 240 # warning Missing logic #endif @@ -339,14 +347,22 @@ static int imxrt_irqinfo(int irq, uintptr_t *regaddr, uint32_t *bit, else #endif #if IMXRT_IRQ_NEXTINT > 192 - if (extint < 219) + if (extint < 224) { *regaddr = (NVIC_IRQ192_223_ENABLE + offset); *bit = 1 << (extint - 192); } else #endif -#if IMXRT_IRQ_NEXTINT > 218 +#if IMXRT_IRQ_NEXTINT > 224 + if (extint < 240) + { + *regaddr = (NVIC_IRQ224_239_ENABLE + offset); + *bit = 1 << (extint - 224); + } + else +#endif +#if IMXRT_IRQ_NEXTINT > 240 # error Missing logic #endif { diff --git a/arch/arm/src/imxrt/imxrt_lowputc.c b/arch/arm/src/imxrt/imxrt_lowputc.c index b071f4b332844..9e8ad70be0d1d 100644 --- a/arch/arm/src/imxrt/imxrt_lowputc.c +++ b/arch/arm/src/imxrt/imxrt_lowputc.c @@ -483,7 +483,8 @@ void imxrt_lowsetup(void) int imxrt_lpuart_configure(uint32_t base, const struct uart_config_s *config) { -#ifndef CONFIG_ARCH_FAMILY_IMXRT117x +#if !defined(CONFIG_ARCH_FAMILY_IMXRT117x) && \ + !defined(CONFIG_ARCH_FAMILY_IMXRT118x) uint32_t src_freq = 0; uint32_t pll3_div = 0; uint32_t uart_div = 0; @@ -499,7 +500,8 @@ int imxrt_lpuart_configure(uint32_t base, uint32_t regval; uint32_t regval2; -#ifdef CONFIG_ARCH_FAMILY_IMXRT117x +#if defined(CONFIG_ARCH_FAMILY_IMXRT117x) || \ + defined(CONFIG_ARCH_FAMILY_IMXRT118x) if (base == IMXRT_LPUART1_BASE) { if (imxrt_get_rootclock(CCM_CR_LPUART1, &lpuart_freq) != OK) diff --git a/arch/arm/src/imxrt/imxrt_lpi2c.c b/arch/arm/src/imxrt/imxrt_lpi2c.c index 561ae36564c34..98fe39c0b01bc 100644 --- a/arch/arm/src/imxrt/imxrt_lpi2c.c +++ b/arch/arm/src/imxrt/imxrt_lpi2c.c @@ -1072,7 +1072,8 @@ static void imxrt_lpi2c_tracedump(struct imxrt_lpi2c_priv_s *priv) static void imxrt_lpi2c_setclock(struct imxrt_lpi2c_priv_s *priv, uint32_t frequency) { -#ifndef CONFIG_ARCH_FAMILY_IMXRT117x +#if !defined(CONFIG_ARCH_FAMILY_IMXRT117x) && \ + !defined(CONFIG_ARCH_FAMILY_IMXRT118x) uint32_t pll3_div = 0; uint32_t lpi2c_clk_div; #endif @@ -1108,7 +1109,8 @@ static void imxrt_lpi2c_setclock(struct imxrt_lpi2c_priv_s *priv, /* Get the LPI2C clock source frequency */ -#ifdef CONFIG_ARCH_FAMILY_IMXRT117x +#if defined(CONFIG_ARCH_FAMILY_IMXRT117x) || \ + defined(CONFIG_ARCH_FAMILY_IMXRT118x) if (priv->config->base == IMXRT_LPI2C1_BASE) { imxrt_get_rootclock(CCM_CR_LPI2C1, &src_freq); @@ -1682,7 +1684,8 @@ void imxrt_lpi2c_clock_enable (uint32_t base) } else if (base == IMXRT_LPI2C4_BASE) { -#ifndef CONFIG_ARCH_FAMILY_IMXRT117x +#if !defined(CONFIG_ARCH_FAMILY_IMXRT117x) && \ + !defined(CONFIG_ARCH_FAMILY_IMXRT118x) imxrt_clockall_lpi2c4_serial(); #else imxrt_clockall_lpi2c4(); @@ -1722,7 +1725,8 @@ void imxrt_lpi2c_clock_disable (uint32_t base) } else if (base == IMXRT_LPI2C4_BASE) { -#ifndef CONFIG_ARCH_FAMILY_IMXRT117x +#if !defined(CONFIG_ARCH_FAMILY_IMXRT117x) && \ + !defined(CONFIG_ARCH_FAMILY_IMXRT118x) imxrt_clockoff_lpi2c4_serial(); #else imxrt_clockoff_lpi2c4(); diff --git a/arch/arm/src/imxrt/imxrt_lpspi.c b/arch/arm/src/imxrt/imxrt_lpspi.c index af34bdbde02d4..7e60ac7b6c588 100644 --- a/arch/arm/src/imxrt/imxrt_lpspi.c +++ b/arch/arm/src/imxrt/imxrt_lpspi.c @@ -731,7 +731,8 @@ static inline void imxrt_lpspi_master_set_delays( uint32_t delay_ns, enum imxrt_delay_e type) { -#ifndef CONFIG_ARCH_FAMILY_IMXRT117x +#if !defined(CONFIG_ARCH_FAMILY_IMXRT117x) && \ + !defined(CONFIG_ARCH_FAMILY_IMXRT118x) uint32_t pll3_div; uint32_t pll_freq; #endif @@ -745,7 +746,8 @@ static inline void imxrt_lpspi_master_set_delays( uint32_t clock_div_prescaler; uint32_t additional_scaler; -#ifdef CONFIG_ARCH_FAMILY_IMXRT117x +#if defined(CONFIG_ARCH_FAMILY_IMXRT117x) || \ + defined(CONFIG_ARCH_FAMILY_IMXRT118x) if (priv->spibase == IMXRT_LPSPI1_BASE) { imxrt_get_rootclock(CCM_CR_LPSPI1, &src_freq); @@ -942,7 +944,8 @@ static uint32_t imxrt_lpspi_setfrequency(struct spi_dev_s *dev, { struct imxrt_lpspidev_s *priv = (struct imxrt_lpspidev_s *)dev; -#ifndef CONFIG_ARCH_FAMILY_IMXRT117x +#if !defined(CONFIG_ARCH_FAMILY_IMXRT117x) && \ + !defined(CONFIG_ARCH_FAMILY_IMXRT118x) uint32_t pll_freq; uint32_t pll3_div; #endif @@ -970,7 +973,8 @@ static uint32_t imxrt_lpspi_setfrequency(struct spi_dev_s *dev, LPSPI_CR_MEN, 0); } -#ifdef CONFIG_ARCH_FAMILY_IMXRT117x +#if defined(CONFIG_ARCH_FAMILY_IMXRT117x) || \ + defined(CONFIG_ARCH_FAMILY_IMXRT118x) if (priv->spibase == IMXRT_LPSPI1_BASE) { imxrt_get_rootclock(CCM_CR_LPSPI1, &src_freq); diff --git a/arch/arm/src/imxrt/imxrt_mpuinit.c b/arch/arm/src/imxrt/imxrt_mpuinit.c index 4f3ff3a2a3548..75e09d19c96b5 100644 --- a/arch/arm/src/imxrt/imxrt_mpuinit.c +++ b/arch/arm/src/imxrt/imxrt_mpuinit.c @@ -269,6 +269,80 @@ void imxrt_mpu_initialize(void) * Not Shareable * No Subregion disable */ ); +# elif defined(CONFIG_ARCH_FAMILY_IMXRT118x) + uint32_t regval; + uint32_t region; + + /* Deny access by default to prevent speculative accesses outside the + * explicitly mapped RT118x address ranges (Arm erratum 1013783-B). + */ + + mpu_reset(); + region = mpu_allocregion(); + DEBUGASSERT(region == 0); + + putreg32(region, MPU_RNR); + putreg32(region | MPU_RBAR_VALID, MPU_RBAR); + + regval = MPU_RASR_ENABLE | + MPU_RASR_SIZE_LOG2(32) | + MPU_RASR_TEX_SO | + MPU_RASR_AP_NONO | + MPU_RASR_XN; + putreg32(regval, MPU_RASR); + + /* Map the external and internal peripheral spaces as device memory. */ + + mpu_configure_region(IMXRT_SEMC0_BASE, IMXRT_SEMC0_SIZE, + MPU_RASR_TEX_DEV | + MPU_RASR_AP_RWRW | + MPU_RASR_XN); + + mpu_configure_region(IMXRT_M7_SYSTEM_BASE, IMXRT_M7_SYSTEM_SIZE, + MPU_RASR_TEX_DEV | + MPU_RASR_AP_RWRW | + MPU_RASR_XN); + + /* Higher-numbered regions override the device mapping for executable and + * cacheable memories. + */ + + mpu_configure_region(IMXRT_M7_ROM_BASE, IMXRT_M7_ROM_SIZE, + MPU_RASR_TEX_NOR | + MPU_RASR_C | + MPU_RASR_B | + MPU_RASR_AP_RORO); + + mpu_configure_region(IMXRT_ITCM_BASE, 256 * 1024, + MPU_RASR_TEX_NOR | + RASR_C_VALUE | + RASR_B_VALUE | + MPU_RASR_AP_RWRW); + + mpu_configure_region(IMXRT_DTCM_BASE, 256 * 1024, + MPU_RASR_TEX_NOR | + RASR_C_VALUE | + RASR_B_VALUE | + MPU_RASR_AP_RWRW); + + mpu_configure_region(IMXRT_OCRAM1_BASE, 512 * 1024, + MPU_RASR_TEX_NOR | + RASR_C_VALUE | + RASR_B_VALUE | + MPU_RASR_AP_RWRW); + + mpu_configure_region(IMXRT_OCRAM2_BASE, 256 * 1024, + MPU_RASR_TEX_NOR | + RASR_C_VALUE | + RASR_B_VALUE | + MPU_RASR_AP_RWRW); + + mpu_configure_region(IMXRT_FLEXSPI1_XIP_BASE, 128 * 1024 * 1024, + MPU_RASR_TEX_NOR | + MPU_RASR_C | + MPU_RASR_B | + MPU_RASR_AP_RORO); + # else mpu_reset(); diff --git a/arch/arm/src/imxrt/imxrt_ocotp.c b/arch/arm/src/imxrt/imxrt_ocotp.c index cbb45ef7bd9ea..24ac4b716d9fb 100644 --- a/arch/arm/src/imxrt/imxrt_ocotp.c +++ b/arch/arm/src/imxrt/imxrt_ocotp.c @@ -49,6 +49,15 @@ * Private Function ****************************************************************************/ +#ifndef CONFIG_ARCH_FAMILY_IMXRT118x + +/* The private helpers below drive the classic OCOTP MMIO register + * controller present on RT10xx / RT117x. On chips that ship an EdgeLock + * Enclave (RT1180 / CONFIG_ARCH_FAMILY_IMXRT118x=y) the fuse controller + * is owned by the ELE and the SoC only exposes a shadow-read window; + * those chips do not need or have these helpers. + */ + static inline void imxrt_ocotp_reset_errors(void) { putreg32(OCOTP_CTRL_ERROR, IMXRT_OCOTP_CTRL_CLR); @@ -187,6 +196,8 @@ static int imxrt_ocotp_wait_for_completion(uint32_t timeout_ms) return OK; } +#endif /* !CONFIG_ARCH_FAMILY_IMXRT118x */ + /**************************************************************************** * Public Functions ****************************************************************************/ @@ -199,8 +210,16 @@ static int imxrt_ocotp_wait_for_completion(uint32_t timeout_ms) * ****************************************************************************/ -int imxrt_ocotp_reload() +int imxrt_ocotp_reload(void) { +#ifdef CONFIG_ARCH_FAMILY_IMXRT118x + /* Shadow reload on ELE-equipped chips (e.g. RT1180) is owned by the + * EdgeLock Enclave and would need to go through its messaging protocol. + * Not implemented in this port. + */ + + return -ENOSYS; +#else int ret; ret = imxrt_ocotp_wait_for_completion(OCOTP_OPT_TIMEOUT_MS); @@ -214,6 +233,7 @@ int imxrt_ocotp_reload() } return ret; +#endif } /**************************************************************************** @@ -234,6 +254,20 @@ int imxrt_ocotp_reload() int imxrt_ocotp_read(uint32_t otp_index, uint32_t *data) { +#ifdef CONFIG_ARCH_FAMILY_IMXRT118x + /* On ELE-equipped chips (e.g. RT1180) the SoC only exposes a read-only + * window of the non-security-related OCOTP shadow registers. Access it + * directly via IMXRT_OCOTP_SHADOW_BASE. + */ + + if (data == NULL) + { + return -EINVAL; + } + + *data = getreg32(IMXRT_OCOTP_SHADOW_BASE + (otp_index * 4)); + return OK; +#else int ret; ret = imxrt_ocotp_wait_for_completion(OCOTP_OPT_TIMEOUT_MS); @@ -262,6 +296,7 @@ int imxrt_ocotp_read(uint32_t otp_index, uint32_t *data) } return ret; +#endif } /**************************************************************************** @@ -283,6 +318,15 @@ int imxrt_ocotp_read(uint32_t otp_index, uint32_t *data) int imxrt_ocotp_write(uint32_t otp_index, uint32_t data) { +#ifdef CONFIG_ARCH_FAMILY_IMXRT118x + /* Fuse writes on ELE-equipped chips must go through the EdgeLock + * Enclave messaging protocol. Not implemented in this port. + */ + + UNUSED(otp_index); + UNUSED(data); + return -ENOSYS; +#else int ret; ret = imxrt_ocotp_wait_for_completion(OCOTP_OPT_TIMEOUT_MS); @@ -312,4 +356,5 @@ int imxrt_ocotp_write(uint32_t otp_index, uint32_t data) } return ret; +#endif } diff --git a/arch/arm/src/imxrt/imxrt_periphclks.h b/arch/arm/src/imxrt/imxrt_periphclks.h index 55f3c9d61e096..d8aaaeb354b2d 100644 --- a/arch/arm/src/imxrt/imxrt_periphclks.h +++ b/arch/arm/src/imxrt/imxrt_periphclks.h @@ -29,6 +29,17 @@ #include #include + +#ifdef CONFIG_IMXRT_CLOCKCONFIG_VER3 + +/* CCM v2 with per-peripheral LPCG registers: LPUART clock helpers are + * declared in imxrt_clockconfig_ver3.h. + */ + +#include "imxrt_clockconfig_ver3.h" + +#else + #include "hardware/imxrt_ccm.h" /**************************************************************************** @@ -590,6 +601,8 @@ void imxrt_periphclk_configure(uintptr_t regaddr, unsigned int index, #endif +#endif /* !CONFIG_ARCH_FAMILY_IMXRT118x */ + #undef EXTERN #if defined(__cplusplus) } diff --git a/arch/arm/src/imxrt/imxrt_rgpio.c b/arch/arm/src/imxrt/imxrt_rgpio.c new file mode 100644 index 0000000000000..c07986fe2d2ca --- /dev/null +++ b/arch/arm/src/imxrt/imxrt_rgpio.c @@ -0,0 +1,275 @@ +/**************************************************************************** + * arch/arm/src/imxrt/imxrt_rgpio.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include +#include + +#include + +#include "chip.h" +#include "arm_internal.h" +#include "imxrt_rgpio.h" + +/**************************************************************************** + * Public Data + ****************************************************************************/ + +/* Look-up table that maps GPIO1..GPIOn indexes into RGPIO base addresses. + * GPIO1 lives in the AON domain; GPIO2..GPIO6 are in the WAKEUPMIX. + */ + +const uintptr_t g_gpio_base[IMXRT_GPIO_NPORTS] = +{ + IMXRT_GPIO1_BASE, + IMXRT_GPIO2_BASE, + IMXRT_GPIO3_BASE, + IMXRT_GPIO4_BASE, + IMXRT_GPIO5_BASE, + IMXRT_GPIO6_BASE, +}; + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: imxrt_gpio_dirout + ****************************************************************************/ + +static inline void imxrt_gpio_dirout(uint32_t port, uint32_t pin) +{ + uint32_t regval = getreg32(IMXRT_GPIO_PDDR(port)); + + regval |= GPIO_PIN(pin); + putreg32(regval, IMXRT_GPIO_PDDR(port)); +} + +/**************************************************************************** + * Name: imxrt_gpio_dirin + ****************************************************************************/ + +static inline void imxrt_gpio_dirin(uint32_t port, uint32_t pin) +{ + uint32_t regval = getreg32(IMXRT_GPIO_PDDR(port)); + + regval &= ~GPIO_PIN(pin); + putreg32(regval, IMXRT_GPIO_PDDR(port)); +} + +/**************************************************************************** + * Name: imxrt_gpio_setoutput + ****************************************************************************/ + +static void imxrt_gpio_setoutput(uint32_t port, uint32_t pin, bool value) +{ + uintptr_t regaddr = value ? IMXRT_GPIO_PSOR(port) : IMXRT_GPIO_PCOR(port); + + putreg32(GPIO_PIN(pin), regaddr); +} + +/**************************************************************************** + * Name: imxrt_gpio_get_pinstatus + ****************************************************************************/ + +static inline bool imxrt_gpio_get_pinstatus(uint32_t port, uint32_t pin) +{ + uintptr_t regaddr = IMXRT_GPIO_PDOR(port); + uint32_t regval; + + regval = getreg32(regaddr); + return ((regval & GPIO_PIN(pin)) != 0); +} + +/**************************************************************************** + * Name: imxrt_gpio_getinput + ****************************************************************************/ + +static inline bool imxrt_gpio_getinput(uint32_t port, uint32_t pin) +{ + uintptr_t regaddr = IMXRT_GPIO_PDIR(port); + uint32_t regval; + + regval = getreg32(regaddr); + return ((regval & GPIO_PIN(pin)) != 0); +} + +/**************************************************************************** + * Name: imxrt_gpio_configinput + ****************************************************************************/ + +static int imxrt_gpio_configinput(uint16_t gpio) +{ + uint32_t port = (gpio & GPIO_PORT_MASK) >> GPIO_PORT_SHIFT; + uint32_t pin = (gpio & GPIO_PIN_MASK) >> GPIO_PIN_SHIFT; + + DEBUGASSERT(port < IMXRT_GPIO_NPORTS); + + imxrt_gpio_dirin(port, pin); + + return OK; +} + +/**************************************************************************** + * Name: imxrt_gpio_configoutput + ****************************************************************************/ + +static inline int imxrt_gpio_configoutput(uint16_t gpio) +{ + uint32_t port = (gpio & GPIO_PORT_MASK) >> GPIO_PORT_SHIFT; + uint32_t pin = (gpio & GPIO_PIN_MASK) >> GPIO_PIN_SHIFT; + bool value = ((gpio & GPIO_OUTPUT_ONE) != 0); + + DEBUGASSERT(port < IMXRT_GPIO_NPORTS); + + imxrt_gpio_setoutput(port, pin, value); + imxrt_gpio_dirout(port, pin); + return OK; +} + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: imxrt_config_gpio + * + * Description: + * Configure a GPIO pin based on pin-encoded description of the pin. + * + ****************************************************************************/ + +int imxrt_config_gpio(gpio_pinset_t pinset) +{ + irqstate_t flags; + uint16_t gpio = IMXRT_PINSET_GPIO(pinset); + int ret; + + flags = enter_critical_section(); + + ret = imxrt_iomux_configure(pinset); + if (ret < 0) + { + leave_critical_section(flags); + return ret; + } + + switch (gpio & GPIO_MODE_MASK) + { + case GPIO_INPUT: + { + ret = imxrt_gpio_configinput(gpio); + } + break; + + case GPIO_OUTPUT: + { + ret = imxrt_gpio_configinput(gpio); + if (ret >= 0) + { + ret = imxrt_gpio_configoutput(gpio); + } + } + break; + +#ifdef CONFIG_IMXRT_GPIO_IRQ + case GPIO_INTERRUPT: + { + ret = imxrt_gpio_configinput(gpio); + if (ret == OK) + { + ret = imxrt_gpioirq_configure(pinset); + } + } + break; +#endif + + default: + ret = OK; + break; + } + + leave_critical_section(flags); + return ret; +} + +/**************************************************************************** + * Name: imxrt_gpio_write + * + * Description: + * Write one or zero to the selected GPIO pin + * + ****************************************************************************/ + +void imxrt_gpio_write(gpio_pinset_t pinset, bool value) +{ + irqstate_t flags; + uint16_t gpio = IMXRT_PINSET_GPIO(pinset); + uint32_t port = (gpio & GPIO_PORT_MASK) >> GPIO_PORT_SHIFT; + uint32_t pin = (gpio & GPIO_PIN_MASK) >> GPIO_PIN_SHIFT; + + DEBUGASSERT(port < IMXRT_GPIO_NPORTS); + + flags = enter_critical_section(); + imxrt_gpio_setoutput(port, pin, value); + leave_critical_section(flags); +} + +/**************************************************************************** + * Name: imxrt_gpio_read + * + * Description: + * Read one or zero from the selected GPIO pin + * + ****************************************************************************/ + +bool imxrt_gpio_read(gpio_pinset_t pinset) +{ + irqstate_t flags; + uint16_t gpio = IMXRT_PINSET_GPIO(pinset); + uint32_t port = (gpio & GPIO_PORT_MASK) >> GPIO_PORT_SHIFT; + uint32_t pin = (gpio & GPIO_PIN_MASK) >> GPIO_PIN_SHIFT; + bool value; + + DEBUGASSERT(port < IMXRT_GPIO_NPORTS); + + flags = enter_critical_section(); + if ((gpio & GPIO_MODE_MASK) == GPIO_OUTPUT) + { + value = imxrt_gpio_get_pinstatus(port, pin); + } + else + { + value = imxrt_gpio_getinput(port, pin); + } + + leave_critical_section(flags); + return value; +} diff --git a/arch/arm/src/imxrt/imxrt_rgpio.h b/arch/arm/src/imxrt/imxrt_rgpio.h new file mode 100644 index 0000000000000..38e838f1d883e --- /dev/null +++ b/arch/arm/src/imxrt/imxrt_rgpio.h @@ -0,0 +1,251 @@ +/**************************************************************************** + * arch/arm/src/imxrt/imxrt_rgpio.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_IMXRT_IMXRT_RGPIO_H +#define __ARCH_ARM_SRC_IMXRT_IMXRT_RGPIO_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include + +#include "chip.h" +#include "hardware/rt118x/imxrt118x_gpio.h" +#include "imxrt_iomuxc_ver3.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* 16-bit gpio pinset bit layout (lives in bits 48..63 of imxrt_pinset_t): + * + * 1111 1100 0000 0000 + * 5432 1098 7654 3210 + * ENCODING MMVX BEEG GGGP PPPP + * GPIO INPUT 00.. BEEG GGGP PPPP + * INT INPUT 11.. BEEG GGGP PPPP + * GPIO OUTPUT 01V. ...G GGGP PPPP + */ + +/* Input/Output Selection: bits 14-15 */ + +#define GPIO_MODE_SHIFT (14) +#define GPIO_MODE_MASK (0x3u << GPIO_MODE_SHIFT) +# define GPIO_INPUT (0u << GPIO_MODE_SHIFT) +# define GPIO_OUTPUT (1u << GPIO_MODE_SHIFT) +# define GPIO_INTERRUPT (2u << GPIO_MODE_SHIFT) +# define GPIO_NONE (3u << GPIO_MODE_SHIFT) + +/* Initial Output Value: bit 13 (only meaningful for GPIO_OUTPUT) */ + +#define GPIO_OUTPUT_SHIFT (13) +#define GPIO_OUTPUT_MASK (0x1u << GPIO_OUTPUT_SHIFT) +# define GPIO_OUTPUT_ZERO (0u << GPIO_OUTPUT_SHIFT) +# define GPIO_OUTPUT_ONE (1u << GPIO_OUTPUT_SHIFT) + +/* Interrupt "both edges" flag: bit 11 (only for GPIO_INTERRUPT) */ + +#define GPIO_INTBOTHCFG_SHIFT (11) +#define GPIO_INTBOTHCFG_MASK (1u << GPIO_INTBOTHCFG_SHIFT) +# define GPIO_INTBOTH_EDGES (1u << GPIO_INTBOTHCFG_SHIFT) + +/* Interrupt edge/level configuration: bits 9-10 (only for GPIO_INTERRUPT) */ + +#define GPIO_INTCFG_SHIFT (9) +#define GPIO_INTCFG_MASK (0x3u << GPIO_INTCFG_SHIFT) +# define GPIO_INT_LOWLEVEL (0u << GPIO_INTCFG_SHIFT) +# define GPIO_INT_HIGHLEVEL (1u << GPIO_INTCFG_SHIFT) +# define GPIO_INT_RISINGEDGE (2u << GPIO_INTCFG_SHIFT) +# define GPIO_INT_FALLINGEDGE (3u << GPIO_INTCFG_SHIFT) + +/* GPIO Port Number: bits 5-8 (GPIO1..GPIO6) */ + +#define GPIO_PORT_SHIFT (5) +#define GPIO_PORT_MASK (0xfu << GPIO_PORT_SHIFT) +# define GPIO_PORT1 (GPIO1 << GPIO_PORT_SHIFT) +# define GPIO_PORT2 (GPIO2 << GPIO_PORT_SHIFT) +# define GPIO_PORT3 (GPIO3 << GPIO_PORT_SHIFT) +# define GPIO_PORT4 (GPIO4 << GPIO_PORT_SHIFT) +# define GPIO_PORT5 (GPIO5 << GPIO_PORT_SHIFT) +# define GPIO_PORT6 (GPIO6 << GPIO_PORT_SHIFT) + +/* GPIO Pin Number: bits 0-4 */ + +#define GPIO_PIN_SHIFT (0) +#define GPIO_PIN_MASK (0x1fu << GPIO_PIN_SHIFT) +# define GPIO_PIN0 (0u << GPIO_PIN_SHIFT) +# define GPIO_PIN1 (1u << GPIO_PIN_SHIFT) +# define GPIO_PIN2 (2u << GPIO_PIN_SHIFT) +# define GPIO_PIN3 (3u << GPIO_PIN_SHIFT) +# define GPIO_PIN4 (4u << GPIO_PIN_SHIFT) +# define GPIO_PIN5 (5u << GPIO_PIN_SHIFT) +# define GPIO_PIN6 (6u << GPIO_PIN_SHIFT) +# define GPIO_PIN7 (7u << GPIO_PIN_SHIFT) +# define GPIO_PIN8 (8u << GPIO_PIN_SHIFT) +# define GPIO_PIN9 (9u << GPIO_PIN_SHIFT) +# define GPIO_PIN10 (10u << GPIO_PIN_SHIFT) +# define GPIO_PIN11 (11u << GPIO_PIN_SHIFT) +# define GPIO_PIN12 (12u << GPIO_PIN_SHIFT) +# define GPIO_PIN13 (13u << GPIO_PIN_SHIFT) +# define GPIO_PIN14 (14u << GPIO_PIN_SHIFT) +# define GPIO_PIN15 (15u << GPIO_PIN_SHIFT) +# define GPIO_PIN16 (16u << GPIO_PIN_SHIFT) +# define GPIO_PIN17 (17u << GPIO_PIN_SHIFT) +# define GPIO_PIN18 (18u << GPIO_PIN_SHIFT) +# define GPIO_PIN19 (19u << GPIO_PIN_SHIFT) +# define GPIO_PIN20 (20u << GPIO_PIN_SHIFT) +# define GPIO_PIN21 (21u << GPIO_PIN_SHIFT) +# define GPIO_PIN22 (22u << GPIO_PIN_SHIFT) +# define GPIO_PIN23 (23u << GPIO_PIN_SHIFT) +# define GPIO_PIN24 (24u << GPIO_PIN_SHIFT) +# define GPIO_PIN25 (25u << GPIO_PIN_SHIFT) +# define GPIO_PIN26 (26u << GPIO_PIN_SHIFT) +# define GPIO_PIN27 (27u << GPIO_PIN_SHIFT) +# define GPIO_PIN28 (28u << GPIO_PIN_SHIFT) +# define GPIO_PIN29 (29u << GPIO_PIN_SHIFT) +# define GPIO_PIN30 (30u << GPIO_PIN_SHIFT) +# define GPIO_PIN31 (31u << GPIO_PIN_SHIFT) + +/* Port access via global LUT */ + +#define IMXRT_GPIO_BASE(n) g_gpio_base[n] + +#define IMXRT_GPIO_VERID(n) (IMXRT_GPIO_BASE(n) + IMXRT_GPIO_VERID_OFFSET) +#define IMXRT_GPIO_PARAM(n) (IMXRT_GPIO_BASE(n) + IMXRT_GPIO_PARAM_OFFSET) +#define IMXRT_GPIO_LOCK(n) (IMXRT_GPIO_BASE(n) + IMXRT_GPIO_LOCK_OFFSET) +#define IMXRT_GPIO_PCNS(n) (IMXRT_GPIO_BASE(n) + IMXRT_GPIO_PCNS_OFFSET) +#define IMXRT_GPIO_ICNS(n) (IMXRT_GPIO_BASE(n) + IMXRT_GPIO_ICNS_OFFSET) +#define IMXRT_GPIO_PCNP(n) (IMXRT_GPIO_BASE(n) + IMXRT_GPIO_PCNP_OFFSET) +#define IMXRT_GPIO_ICNP(n) (IMXRT_GPIO_BASE(n) + IMXRT_GPIO_ICNP_OFFSET) +#define IMXRT_GPIO_PDOR(n) (IMXRT_GPIO_BASE(n) + IMXRT_GPIO_PDOR_OFFSET) +#define IMXRT_GPIO_PSOR(n) (IMXRT_GPIO_BASE(n) + IMXRT_GPIO_PSOR_OFFSET) +#define IMXRT_GPIO_PCOR(n) (IMXRT_GPIO_BASE(n) + IMXRT_GPIO_PCOR_OFFSET) +#define IMXRT_GPIO_PTOR(n) (IMXRT_GPIO_BASE(n) + IMXRT_GPIO_PTOR_OFFSET) +#define IMXRT_GPIO_PDIR(n) (IMXRT_GPIO_BASE(n) + IMXRT_GPIO_PDIR_OFFSET) +#define IMXRT_GPIO_PDDR(n) (IMXRT_GPIO_BASE(n) + IMXRT_GPIO_PDDR_OFFSET) +#define IMXRT_GPIO_PIDR(n) (IMXRT_GPIO_BASE(n) + IMXRT_GPIO_PIDR_OFFSET) +#define IMXRT_GPIO_GICLR(n) (IMXRT_GPIO_BASE(n) + IMXRT_GPIO_GICLR_OFFSET) +#define IMXRT_GPIO_GICHR(n) (IMXRT_GPIO_BASE(n) + IMXRT_GPIO_GICHR_OFFSET) + +/* Interrupt status flag registers (two channels). Channel selected via + * ICRN.IRQS. + */ + +#define IMXRT_GPIO_ISFR0(n) (IMXRT_GPIO_BASE(n) + IMXRT_GPIO_ISFR0_OFFSET) +#define IMXRT_GPIO_ISFR1(n) (IMXRT_GPIO_BASE(n) + IMXRT_GPIO_ISFR1_OFFSET) + +/* Per-pin ICR and PDR at n*4 offsets */ + +#define IMXRT_GPIO_P0DR(n) (IMXRT_GPIO_BASE(n) + IMXRT_GPIO_P0DR_OFFSET) +#define IMXRT_GPIO_PNDR(n, p) (IMXRT_GPIO_P0DR(n) + ((p) * 0x4)) +#define IMXRT_GPIO_ICR0(n) (IMXRT_GPIO_BASE(n) + IMXRT_GPIO_ICR0_OFFSET) +#define IMXRT_GPIO_ICRN(n, p) (IMXRT_GPIO_ICR0(n) + ((p) * 0x4)) + +/**************************************************************************** + * Public Types + ****************************************************************************/ + +typedef imxrt_pinset_t gpio_pinset_t; + +/**************************************************************************** + * Public Data + ****************************************************************************/ + +#undef EXTERN +#if defined(__cplusplus) +#define EXTERN extern "C" +extern "C" +{ +#else +#define EXTERN extern +#endif + +/* Look-up table that maps GPIO1..GPIOn indexes into RGPIO instance base + * addresses. + */ + +EXTERN const uintptr_t g_gpio_base[IMXRT_GPIO_NPORTS]; + +/**************************************************************************** + * Public Function Prototypes + ****************************************************************************/ + +/**************************************************************************** + * Name: imxrt_gpioirq_initialize + ****************************************************************************/ + +#ifdef CONFIG_IMXRT_GPIO_IRQ +void imxrt_gpioirq_initialize(void); +#else +# define imxrt_gpioirq_initialize() +#endif + +/**************************************************************************** + * Name: imxrt_config_gpio + * + * Description: + * Configure the pad routing and (for GPIO pins) the RGPIO direction, + * initial output value and interrupt configuration. + * + ****************************************************************************/ + +int imxrt_config_gpio(gpio_pinset_t pinset); + +/**************************************************************************** + * Name: imxrt_gpio_write + ****************************************************************************/ + +void imxrt_gpio_write(gpio_pinset_t pinset, bool value); + +/**************************************************************************** + * Name: imxrt_gpio_read + ****************************************************************************/ + +bool imxrt_gpio_read(gpio_pinset_t pinset); + +/**************************************************************************** + * Name: imxrt_gpioirq_attach / imxrt_gpioirq_configure / + * imxrt_gpioirq_enable / imxrt_gpioirq_disable + ****************************************************************************/ + +#ifdef CONFIG_IMXRT_GPIO_IRQ +int imxrt_gpioirq_attach(gpio_pinset_t pinset, xcpt_t isr, void *arg); +int imxrt_gpioirq_configure(gpio_pinset_t pinset); +int imxrt_gpioirq_enable(gpio_pinset_t pinset); +int imxrt_gpioirq_disable(gpio_pinset_t pinset); +#else +# define imxrt_gpioirq_attach(pinset, isr, arg) 0 +# define imxrt_gpioirq_configure(pinset) 0 +# define imxrt_gpioirq_enable(pinset) 0 +# define imxrt_gpioirq_disable(pinset) 0 +#endif + +#undef EXTERN +#if defined(__cplusplus) +} +#endif + +#endif /* __ARCH_ARM_SRC_IMXRT_IMXRT_RGPIO_H */ diff --git a/arch/arm/src/imxrt/imxrt_rgpioirq.c b/arch/arm/src/imxrt/imxrt_rgpioirq.c new file mode 100644 index 0000000000000..3065f5c2eecc0 --- /dev/null +++ b/arch/arm/src/imxrt/imxrt_rgpioirq.c @@ -0,0 +1,268 @@ +/**************************************************************************** + * arch/arm/src/imxrt/imxrt_rgpioirq.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include + +#include +#include + +#include "arm_internal.h" +#include "imxrt_gpio.h" + +#ifdef CONFIG_IMXRT_GPIO_IRQ + +/**************************************************************************** + * Private Types + ****************************************************************************/ + +struct imxrt_portisr_s +{ + struct + { + xcpt_t isr; + void *arg; + } + pins[IMXRT_GPIO_NPINS]; +}; + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +static struct imxrt_portisr_s g_isrtab[IMXRT_GPIO_NPORTS]; + +/* NVIC IRQ per RGPIO instance (channel 0). RGPIO1..3 also expose a + * second interrupt (channel 1) at IMXRT_IRQ_GPIOn_1; the driver uses + * channel 0 for all pins by leaving ICRN.IRQS at reset (0). + */ + +static const int g_gpio_irq[IMXRT_GPIO_NPORTS] = +{ + IMXRT_IRQ_GPIO1_0, + IMXRT_IRQ_GPIO2_0, + IMXRT_IRQ_GPIO3_0, + IMXRT_IRQ_GPIO4, + IMXRT_IRQ_GPIO5, + IMXRT_IRQ_GPIO6, +}; + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: imxrt_gpio_interrupt + * + * Description: + * Common ISR shared by every RGPIO instance. Scans the port's ISFR0 + * flag word and dispatches per-pin user handlers. + * + ****************************************************************************/ + +static int imxrt_gpio_interrupt(int irq, void *context, void *arg) +{ + uint32_t port = (uint32_t)((uintptr_t)arg); + uint32_t status; + uint32_t pin; + uintptr_t regaddr; + + regaddr = IMXRT_GPIO_ISFR0(port); + status = getreg32(regaddr); + + for (pin = 0; pin < IMXRT_GPIO_NPINS && status != 0; pin++) + { + uint32_t mask = (1u << pin); + + if ((status & mask) != 0) + { + struct imxrt_portisr_s *isrtab; + + putreg32(mask, regaddr); + status &= ~mask; + + isrtab = &g_isrtab[port]; + if (isrtab->pins[pin].isr != NULL) + { + isrtab->pins[pin].isr(irq, context, isrtab->pins[pin].arg); + } + } + } + + return OK; +} + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: imxrt_gpioirq_initialize + ****************************************************************************/ + +void imxrt_gpioirq_initialize(void) +{ + uint32_t port; + uint32_t pin; + + /* Reset every pin's ICR so no interrupt configuration survives across + * a warm reset from the M33. + */ + + for (port = 0; port < IMXRT_GPIO_NPORTS; port++) + { + for (pin = 0; pin < IMXRT_GPIO_NPINS; pin++) + { + putreg32(0, IMXRT_GPIO_ICRN(port, pin)); + } + } + + /* Attach the common ISR to every RGPIO NVIC line. */ + + for (port = 0; port < IMXRT_GPIO_NPORTS; port++) + { + up_disable_irq(g_gpio_irq[port]); + DEBUGVERIFY(irq_attach(g_gpio_irq[port], + imxrt_gpio_interrupt, + (void *)(uintptr_t)port)); + up_enable_irq(g_gpio_irq[port]); + } +} + +/**************************************************************************** + * Name: imxrt_gpioirq_attach + ****************************************************************************/ + +int imxrt_gpioirq_attach(gpio_pinset_t pinset, xcpt_t isr, void *arg) +{ + uint16_t gpio = IMXRT_PINSET_GPIO(pinset); + uint32_t port = (gpio & GPIO_PORT_MASK) >> GPIO_PORT_SHIFT; + uint32_t pin = (gpio & GPIO_PIN_MASK) >> GPIO_PIN_SHIFT; + irqstate_t flags; + + DEBUGASSERT(port < IMXRT_GPIO_NPORTS && pin < IMXRT_GPIO_NPINS); + + flags = enter_critical_section(); + + g_isrtab[port].pins[pin].isr = isr; + g_isrtab[port].pins[pin].arg = arg; + + leave_critical_section(flags); + return OK; +} + +/**************************************************************************** + * Name: imxrt_gpioirq_configure + * + * Description: + * Reset ICRN for the pin. Interrupt is enabled by imxrt_gpioirq_enable(). + * + ****************************************************************************/ + +int imxrt_gpioirq_configure(gpio_pinset_t pinset) +{ + uint16_t gpio = IMXRT_PINSET_GPIO(pinset); + uint32_t port = (gpio & GPIO_PORT_MASK) >> GPIO_PORT_SHIFT; + uint32_t pin = (gpio & GPIO_PIN_MASK) >> GPIO_PIN_SHIFT; + + DEBUGASSERT(port < IMXRT_GPIO_NPORTS && pin < IMXRT_GPIO_NPINS); + + putreg32(0, IMXRT_GPIO_ICRN(port, pin)); + return OK; +} + +/**************************************************************************** + * Name: imxrt_gpioirq_enable + ****************************************************************************/ + +int imxrt_gpioirq_enable(gpio_pinset_t pinset) +{ + uint16_t gpio = IMXRT_PINSET_GPIO(pinset); + uint32_t port = (gpio & GPIO_PORT_MASK) >> GPIO_PORT_SHIFT; + uint32_t pin = (gpio & GPIO_PIN_MASK) >> GPIO_PIN_SHIFT; + uint32_t both = (gpio & GPIO_INTBOTHCFG_MASK) >> GPIO_INTBOTHCFG_SHIFT; + uint32_t icr = (gpio & GPIO_INTCFG_MASK); + uint32_t regval; + uintptr_t regaddr; + + DEBUGASSERT(port < IMXRT_GPIO_NPORTS && pin < IMXRT_GPIO_NPINS); + + regaddr = IMXRT_GPIO_ICRN(port, pin); + regval = getreg32(regaddr); + regval &= ~IMXRT_GPIO_ICRN_MASK; + + if (both) + { + regval |= IMXRT_GPIO_ICRN_BOTH; + } + else if (icr == GPIO_INT_LOWLEVEL) + { + regval |= IMXRT_GPIO_ICRN_ZERO; + } + else if (icr == GPIO_INT_HIGHLEVEL) + { + regval |= IMXRT_GPIO_ICRN_ONE; + } + else if (icr == GPIO_INT_RISINGEDGE) + { + regval |= IMXRT_GPIO_ICRN_RISING; + } + else + { + regval |= IMXRT_GPIO_ICRN_FALLING; + } + + putreg32(regval, regaddr); + return OK; +} + +/**************************************************************************** + * Name: imxrt_gpioirq_disable + ****************************************************************************/ + +int imxrt_gpioirq_disable(gpio_pinset_t pinset) +{ + uint16_t gpio = IMXRT_PINSET_GPIO(pinset); + uint32_t port = (gpio & GPIO_PORT_MASK) >> GPIO_PORT_SHIFT; + uint32_t pin = (gpio & GPIO_PIN_MASK) >> GPIO_PIN_SHIFT; + uint32_t regval; + uintptr_t regaddr; + + DEBUGASSERT(port < IMXRT_GPIO_NPORTS && pin < IMXRT_GPIO_NPINS); + + regaddr = IMXRT_GPIO_ICRN(port, pin); + regval = getreg32(regaddr); + regval &= ~IMXRT_GPIO_ICRN_MASK; + + putreg32(regval, regaddr); + return OK; +} + +#endif /* CONFIG_IMXRT_GPIO_IRQ */ diff --git a/arch/arm/src/imxrt/imxrt_serial.c b/arch/arm/src/imxrt/imxrt_serial.c index 37b4543086c59..2f4a0872c3f3e 100644 --- a/arch/arm/src/imxrt/imxrt_serial.c +++ b/arch/arm/src/imxrt/imxrt_serial.c @@ -2465,7 +2465,13 @@ static int imxrt_dma_setup(struct uart_dev_s *dev) */ priv->rxdmanext = 0; + #ifdef CONFIG_ARMV7M_DCACHE + + /* Make sure the rx buffer area is all invalid or clean */ + + up_invalidate_dcache((uintptr_t)priv->rxfifo, + (uintptr_t)priv->rxfifo + RXDMA_BUFFER_SIZE); priv->rxdmaavail = 0; #endif @@ -3509,7 +3515,10 @@ static void imxrt_dma_txcallback(DMACH_HANDLE handle, void *arg, bool done, * This is important to free TX buffer space by 'uart_xmitchars_done'. */ - priv->dev.dmatx.nbytes = priv->dev.dmatx.length + priv->dev.dmatx.nlength; + priv->dev.dmatx.nbytes = priv->dev.dmatx.length; +#if CONFIG_IMXRT_EDMA_NTCD > 1 + priv->dev.dmatx.nbytes += priv->dev.dmatx.nlength; +#endif /* Adjust the pointers and unblock writers */ @@ -3592,6 +3601,7 @@ static void imxrt_dma_send(struct uart_dev_s *dev) imxrt_dmach_xfrsetup(priv->txdma, &config); +#if CONFIG_IMXRT_EDMA_NTCD > 1 /* Is this a split transfer? */ if (dev->dmatx.nbuffer) @@ -3606,6 +3616,7 @@ static void imxrt_dma_send(struct uart_dev_s *dev) imxrt_dmach_xfrsetup(priv->txdma, &config); } +#endif /* Start transmission with the callback on DMA completion */ diff --git a/arch/arm/src/imxrt/imxrt_start.c b/arch/arm/src/imxrt/imxrt_start.c index 4d78cdfad1480..5fcf30cb8ff6c 100644 --- a/arch/arm/src/imxrt/imxrt_start.c +++ b/arch/arm/src/imxrt/imxrt_start.c @@ -47,6 +47,14 @@ #include "imxrt_start.h" #include "imxrt_gpio.h" +#ifdef CONFIG_IMXRT_ELE +# include "imxrt118x_ele.h" +#endif + +#ifdef CONFIG_IMXRT_TRDC +# include "imxrt118x_trdc.h" +#endif + /**************************************************************************** * Pre-processor Definitions ****************************************************************************/ @@ -100,6 +108,7 @@ extern const void * const _vectors[]; static inline void imxrt_tcmenable(void) { +#ifdef CONFIG_ARCH_CORTEXM7 uint32_t regval; UP_MB(); @@ -131,6 +140,7 @@ static inline void imxrt_tcmenable(void) #warning Missing logic #endif +#endif /* CONFIG_ARCH_CORTEXM7 */ } /**************************************************************************** @@ -225,6 +235,12 @@ void __start(void) arm_stack_check_init(); #endif +#ifdef CONFIG_IMXRT_ELE + /* Bring the EdgeLock Enclave up */ + + imxrt118x_ele_init(); +#endif + /* Configure the UART so that we can get debug output as soon as possible */ imxrt_clockconfig(); @@ -240,6 +256,13 @@ void __start(void) imxrt_boardinitialize(); +#ifdef CONFIG_IMXRT_TRDC + /* Take ownership of the TRDCs from ELE and program them. */ + + imxrt118x_trdc_init(); + imxrt118x_trdc_config(); +#endif + #ifdef CONFIG_ARM_MPU #ifdef CONFIG_BUILD_PROTECTED /* For the case of the separate user-/kernel-space build, perform whatever diff --git a/arch/arm/src/imxrt/imxrt_usbdev.c b/arch/arm/src/imxrt/imxrt_usbdev.c index 5e380616dccb9..117cd5adf893b 100644 --- a/arch/arm/src/imxrt/imxrt_usbdev.c +++ b/arch/arm/src/imxrt/imxrt_usbdev.c @@ -207,11 +207,21 @@ const struct trace_msg_t g_usb_trace_strings_intdecode[] = #endif #if defined(CONFIG_ARMV7M_DCACHE) -# define cache_aligned_alloc(s) kmm_memalign(ARMV7M_DCACHE_LINESIZE,(s)) +# define cache_aligned_alloc(s) \ + kmm_memalign(ARMV7M_DCACHE_LINESIZE, \ + (((s) + ARMV7M_DCACHE_LINESIZE - 1) & \ + ~(ARMV7M_DCACHE_LINESIZE - 1))) # define CACHE_ALIGNED_DATA aligned_data(ARMV7M_DCACHE_LINESIZE) +# define DCACHE_LINEMASK (ARMV7M_DCACHE_LINESIZE - 1) +# define DCACHE_ALIGN_UP(a) (((a) + DCACHE_LINEMASK) & ~DCACHE_LINEMASK) +# define IS_CACHE_ALIGNED(x,y) \ + (((uintptr_t)(x) & DCACHE_LINEMASK) == 0 && \ + ((y) & DCACHE_LINEMASK) == 0) #else # define cache_aligned_alloc kmm_malloc # define CACHE_ALIGNED_DATA +# define DCACHE_ALIGN_UP(a) (a) +# define IS_CACHE_ALIGNED(x,y) (true) #endif /* Hardware interface *******************************************************/ @@ -369,7 +379,7 @@ struct imxrt_usbdev_s uint8_t ep0state; /* State of certain EP0 operations */ /* buffer for EP0 short transfers */ - uint8_t ep0buf[64] CACHE_ALIGNED_DATA; + uint8_t *ep0buf; uint8_t paddr; /* Address assigned by SETADDRESS */ uint8_t stalled:1; /* 1: Protocol stalled */ uint8_t selfpowered:1; /* 1: Device is self powered */ @@ -390,6 +400,8 @@ struct imxrt_usbdev_s struct imxrt_ep_s eplist[IMXRT_NPHYSENDPOINTS]; }; +#define IMXRT_EP0BUF_SIZE 64 /* Size of the EP0 short transfer buffer */ + #define EP0STATE_IDLE 0 /* Idle State, leave on receiving a setup packet or epsubmit */ #define EP0STATE_SETUP_OUT 1 /* Setup Packet received - SET/CLEAR */ #define EP0STATE_SETUP_IN 2 /* Setup Packet received - GET */ @@ -513,12 +525,34 @@ static int imxrt_pullup(struct usbdev_s *dev, bool enable); static struct imxrt_usbdev_s g_usbdev; +/* Normally g_qh, g_td and g_ep0buf are statically allocated in .bss. + * But they need to be DMA-capable for usb engine to access them. If we + * run with TCM memory as the primary, there has to be another memory + * segment elsewhere, in DMA capable memory (.dmamemory). Also we must have + * USBDEV_DMAMEMORY enabled to be able to dynamically allocate from there. + */ + +#ifdef CONFIG_IMXRT_TCM_PRIMARY +# ifndef CONFIG_USBDEV_DMAMEMORY +# error "CONFIG_USBDEV_DMAMEMORY must be defined" +# endif +# define USBDEV_DMA_SECTION locate_data(".dmamemory") +#else +# define USBDEV_DMA_SECTION +#endif + static struct imxrt_dqh_s g_qh[IMXRT_NPHYSENDPOINTS] + USBDEV_DMA_SECTION aligned_data(2048); static struct imxrt_dtd_s g_td[IMXRT_NPHYSENDPOINTS] + USBDEV_DMA_SECTION aligned_data(32); +static uint8_t g_ep0buf[IMXRT_EP0BUF_SIZE] + USBDEV_DMA_SECTION + aligned_data(32); + static const struct usbdev_epops_s g_epops = { .configure = imxrt_epconfigure, @@ -751,6 +785,11 @@ static inline void imxrt_writedtd(struct imxrt_dtd_s *dtd, const uint8_t *data, uint32_t nbytes) { +#if defined(CONFIG_ARMV7M_DCACHE) + DEBUGASSERT(data == NULL || + IS_CACHE_ALIGNED(data, DCACHE_ALIGN_UP(nbytes))); +#endif + dtd->nextdesc = DTD_NEXTDESC_INVALID; dtd->config = DTD_CONFIG_LENGTH(nbytes) | DTD_CONFIG_IOC | DTD_CONFIG_ACTIVE; @@ -1752,7 +1791,7 @@ static void imxrt_ep0complete(struct imxrt_usbdev_s *priv, uint8_t epphy) */ up_invalidate_dcache((uintptr_t)priv->ep0buf, - (uintptr_t)priv->ep0buf + sizeof(priv->ep0buf)); + (uintptr_t)priv->ep0buf + IMXRT_EP0BUF_SIZE); imxrt_dispatchrequest(priv, &priv->ep0ctrl); imxrt_ep0state(priv, EP0STATE_WAIT_NAK_IN); @@ -1887,8 +1926,6 @@ bool imxrt_epcomplete(struct imxrt_usbdev_s *priv, uint8_t epphy) up_invalidate_dcache((uintptr_t)dtd, (uintptr_t)dtd + sizeof(struct imxrt_dtd_s)); - up_invalidate_dcache((uintptr_t)dtd->buffer0, - (uintptr_t)dtd->buffer0 + dtd->xfer_len); int xfrd = dtd->xfer_len - (dtd->config >> 16); @@ -1903,6 +1940,14 @@ bool imxrt_epcomplete(struct imxrt_usbdev_s *priv, uint8_t epphy) */ usbtrace(TRACE_INTDECODE(IMXRT_TRACEINTID_EPIN), complete); + + /* Invalidate the RX buffer */ + + DEBUGASSERT(IS_CACHE_ALIGNED(privreq->req.buf, + DCACHE_ALIGN_UP(privreq->req.xfrd))); + up_invalidate_dcache((uintptr_t)privreq->req.buf, + (uintptr_t)privreq->req.buf + + DCACHE_ALIGN_UP(privreq->req.xfrd)); } else { @@ -2896,6 +2941,7 @@ void arm_usbinitialize(void) priv->usbdev.ops = &g_devops; priv->usbdev.ep0 = &priv->eplist[IMXRT_EP0_IN].ep; priv->epavail = IMXRT_EPALLSET & ~IMXRT_EPCTRLSET; + priv->ep0buf = g_ep0buf; /* Initialize the endpoint list */ @@ -2950,7 +2996,7 @@ void arm_usbinitialize(void) imxrt_clockall_usboh3(); -#ifdef CONFIG_ARCH_FAMILY_IMXRT117x +#if defined(CONFIG_ARCH_FAMILY_IMXRT117x) || defined(CONFIG_ARCH_FAMILY_IMXRT118x) up_mdelay(1); putreg32(USBPHY_PLL_SIC_PLL_POWER | diff --git a/boards/Kconfig b/boards/Kconfig index ea4bb7ef56ed8..4492115e516e9 100644 --- a/boards/Kconfig +++ b/boards/Kconfig @@ -1004,6 +1004,13 @@ config ARCH_BOARD_IMX93_QSB This is the board configuration for the port of NuttX to the NXP i.MX93 QSB (Quick Start Board), targeting the M33 core of the i.MX93 MCU. +config ARCH_BOARD_IMXRT1180_EVK + bool "NXP i.MX RT 1180 EVK" + depends on ARCH_CHIP_MIMXRT1189CVM8C || ARCH_CHIP_MIMXRT1189CVM8C_CM33 + ---help--- + This is the board configuration for the port of NuttX to the NXP i.MXRT + evaluation kit, MIMXRT1180-EVK. This board features the IMXRT1189 MCU. + config ARCH_BOARD_IMX95_EVK bool "NXP i.MX 95 EVK" depends on ARCH_CHIP_IMX9_CORTEX_M @@ -3983,6 +3990,7 @@ config ARCH_BOARD default "imxrt1060-evk" if ARCH_BOARD_IMXRT1060_EVK default "imxrt1064-evk" if ARCH_BOARD_IMXRT1064_EVK default "imxrt1170-evk" if ARCH_BOARD_IMXRT1170_EVK + default "imxrt1180-evk" if ARCH_BOARD_IMXRT1180_EVK default "imx93-qsb" if ARCH_BOARD_IMX93_QSB default "imx95-evk" if ARCH_BOARD_IMX95_EVK default "mr-navq95b" if ARCH_BOARD_MR_NAVQ95B @@ -4476,6 +4484,9 @@ endif if ARCH_BOARD_IMXRT1170_EVK source "boards/arm/imxrt/imxrt1170-evk/Kconfig" endif +if ARCH_BOARD_IMXRT1180_EVK +source "boards/arm/imxrt/imxrt1180-evk/Kconfig" +endif if ARCH_BOARD_IMX93_QSB source "boards/arm/imx9/imx93-qsb/Kconfig" endif diff --git a/boards/arm/imxrt/imxrt1180-evk/Kconfig b/boards/arm/imxrt/imxrt1180-evk/Kconfig new file mode 100644 index 0000000000000..0e10eeb24135f --- /dev/null +++ b/boards/arm/imxrt/imxrt1180-evk/Kconfig @@ -0,0 +1,22 @@ +# +# For a description of the syntax of this configuration file, +# see the file kconfig-language.txt in the NuttX tools repository. +# + +if ARCH_BOARD_IMXRT1180_EVK + +config IMXRT1180_EVK_BOOTLOADER + bool "Cortex-M33 bootloader application" + default n + depends on ARCH_CORTEXM33 + select IMXRT_CM7_BOOT + ---help--- + Build the minimal Cortex-M33 bootloader application + (src/imxrt_bootloader.c) instead of a normal NuttX application. + Its bootloader_main() entry point only releases the Cortex-M7, + which then runs the M7 NuttX image XIP'd at 0x28080000. + + Set CONFIG_INIT_ENTRYPOINT="bootloader_main" when this is + enabled (see the imxrt1180-evk:bl configuration). + +endif diff --git a/boards/arm/imxrt/imxrt1180-evk/configs/bl/defconfig b/boards/arm/imxrt/imxrt1180-evk/configs/bl/defconfig new file mode 100644 index 0000000000000..bd63df2babfd7 --- /dev/null +++ b/boards/arm/imxrt/imxrt1180-evk/configs/bl/defconfig @@ -0,0 +1,33 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_DEBUG_WARN is not set +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="imxrt1180-evk" +CONFIG_ARCH_BOARD_IMXRT1180_EVK=y +CONFIG_ARCH_CHIP="imxrt" +CONFIG_ARCH_CHIP_IMXRT=y +CONFIG_ARCH_CHIP_MIMXRT1189CVM8C_CM33=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_BINFMT_DISABLE=y +CONFIG_BOARD_LOOPSPERMSEC=104926 +CONFIG_DEBUG_ASSERTIONS=y +CONFIG_DEBUG_FEATURES=y +CONFIG_FS_PROCFS=y +CONFIG_IDLETHREAD_STACKSIZE=2048 +CONFIG_IMXRT1180_EVK_BOOTLOADER=y +CONFIG_IMXRT_ELE_LOAD_FW=y +CONFIG_IMXRT_LPUART1=y +CONFIG_INIT_ENTRYPOINT="bootloader_main" +CONFIG_INTELHEX_BINARY=y +CONFIG_LIBC_LOCALTIME=y +CONFIG_LPUART1_SERIAL_CONSOLE=y +CONFIG_RAM_SIZE=131072 +CONFIG_RAM_START=0x20000000 +CONFIG_RAW_BINARY=y +CONFIG_SCHED_BACKTRACE=y +CONFIG_START_MONTH=9 diff --git a/boards/arm/imxrt/imxrt1180-evk/configs/nsh-m33/defconfig b/boards/arm/imxrt/imxrt1180-evk/configs/nsh-m33/defconfig new file mode 100644 index 0000000000000..e535bda437af2 --- /dev/null +++ b/boards/arm/imxrt/imxrt1180-evk/configs/nsh-m33/defconfig @@ -0,0 +1,68 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_DEBUG_WARN is not set +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="imxrt1180-evk" +CONFIG_ARCH_BOARD_IMXRT1180_EVK=y +CONFIG_ARCH_CHIP="imxrt" +CONFIG_ARCH_CHIP_IMXRT=y +CONFIG_ARCH_CHIP_MIMXRT1189CVM8C_CM33=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_BINFMT_DISABLE=y +CONFIG_BOARD_LOOPSPERMSEC=104926 +CONFIG_BUILTIN=y +CONFIG_CDCACM=y +CONFIG_CDCACM_BULKIN_REQLEN=96 +CONFIG_CDCACM_PRODUCTID=0x0061 +CONFIG_CDCACM_PRODUCTSTR="IMXRT1180-EVK-M33" +CONFIG_CDCACM_RXBUFSIZE=600 +CONFIG_CDCACM_TXBUFSIZE=12000 +CONFIG_CDCACM_VENDORID=0x1FC9 +CONFIG_CDCACM_VENDORSTR="NXP SEMICONDUCTORS" +CONFIG_DEBUG_ASSERTIONS=y +CONFIG_DEBUG_FEATURES=y +CONFIG_DEBUG_FULLOPT=y +CONFIG_DEBUG_SYMBOLS=y +CONFIG_FS_NAMED_SEMAPHORES=y +CONFIG_FS_PROCFS=y +CONFIG_GRAN=y +CONFIG_IDLETHREAD_STACKSIZE=2048 +CONFIG_IMXRT_ELE_LOAD_FW=y +CONFIG_IMXRT_LPUART1=y +CONFIG_IMXRT_USBDEV=y +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INTELHEX_BINARY=y +CONFIG_LIBC_LOCALTIME=y +CONFIG_LINE_MAX=64 +CONFIG_LPUART1_SERIAL_CONSOLE=y +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_DISABLE_IFUPDOWN=y +CONFIG_NSH_FILEIOSIZE=512 +CONFIG_NSH_READLINE=y +CONFIG_PTHREAD_MUTEX_TYPES=y +CONFIG_RAM_SIZE=131072 +CONFIG_RAM_START=0x20000000 +CONFIG_RAW_BINARY=y +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_BACKTRACE=y +CONFIG_SCHED_EVENTS=y +CONFIG_SCHED_HPWORK=y +CONFIG_SCHED_SPORADIC=y +CONFIG_SCHED_THREAD_LOCAL=y +CONFIG_SCHED_WAITPID=y +CONFIG_SIG_EVTHREAD=y +CONFIG_START_MONTH=9 +CONFIG_SYSTEM_CDCACM=y +CONFIG_SYSTEM_NSH=y +CONFIG_TESTING_OSTEST=y +CONFIG_TLS_NCLEANUP=4 +CONFIG_TLS_NELEM=4 +CONFIG_USBDEV=y +CONFIG_USBDEV_DMA=y +CONFIG_USBDEV_DMAMEMORY=y +CONFIG_USBDEV_DUALSPEED=y diff --git a/boards/arm/imxrt/imxrt1180-evk/configs/nsh/defconfig b/boards/arm/imxrt/imxrt1180-evk/configs/nsh/defconfig new file mode 100644 index 0000000000000..2f04d395695e6 --- /dev/null +++ b/boards/arm/imxrt/imxrt1180-evk/configs/nsh/defconfig @@ -0,0 +1,76 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_DEBUG_WARN is not set +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="imxrt1180-evk" +CONFIG_ARCH_BOARD_IMXRT1180_EVK=y +CONFIG_ARCH_CHIP="imxrt" +CONFIG_ARCH_CHIP_IMXRT=y +CONFIG_ARCH_CHIP_MIMXRT1189CVM8C=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_ARMV7M_DCACHE=y +CONFIG_ARMV7M_ICACHE=y +CONFIG_BINFMT_DISABLE=y +CONFIG_BOARD_LOOPSPERMSEC=159610 +CONFIG_BUILTIN=y +CONFIG_CDCACM=y +CONFIG_CDCACM_BULKIN_REQLEN=96 +CONFIG_CDCACM_PRODUCTID=0x0060 +CONFIG_CDCACM_PRODUCTSTR="IMXRT1180-EVK" +CONFIG_CDCACM_RXBUFSIZE=600 +CONFIG_CDCACM_TXBUFSIZE=12000 +CONFIG_CDCACM_VENDORID=0x1FC9 +CONFIG_CDCACM_VENDORSTR="NXP SEMICONDUCTORS" +CONFIG_DEBUG_ASSERTIONS=y +CONFIG_DEBUG_BUSFAULT=y +CONFIG_DEBUG_FEATURES=y +CONFIG_DEBUG_FULLOPT=y +CONFIG_DEBUG_HARDFAULT_ALERT=y +CONFIG_DEBUG_SYMBOLS=y +CONFIG_DEBUG_USAGEFAULT=y +CONFIG_FS_NAMED_SEMAPHORES=y +CONFIG_FS_PROCFS=y +CONFIG_IDLETHREAD_STACKSIZE=4096 +CONFIG_IMXRT_EDMA=y +CONFIG_IMXRT_LPUART1=y +CONFIG_IMXRT_USBDEV=y +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INIT_STACKSIZE=8192 +CONFIG_INTELHEX_BINARY=y +CONFIG_LIBC_LOCALTIME=y +CONFIG_LINE_MAX=64 +CONFIG_LPUART1_RXDMA=y +CONFIG_LPUART1_SERIAL_CONSOLE=y +CONFIG_LPUART1_TXDMA=y +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_DISABLE_IFUPDOWN=y +CONFIG_NSH_FILEIOSIZE=512 +CONFIG_NSH_READLINE=y +CONFIG_PTHREAD_MUTEX_TYPES=y +CONFIG_PTHREAD_STACK_DEFAULT=8192 +CONFIG_RAM_SIZE=491520 +CONFIG_RAM_START=0x20484000 +CONFIG_RAW_BINARY=y +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_BACKTRACE=y +CONFIG_SCHED_EVENTS=y +CONFIG_SCHED_HPWORK=y +CONFIG_SCHED_SPORADIC=y +CONFIG_SCHED_THREAD_LOCAL=y +CONFIG_SCHED_WAITPID=y +CONFIG_SIG_EVTHREAD=y +CONFIG_START_MONTH=9 +CONFIG_SYSTEM_CDCACM=y +CONFIG_SYSTEM_NSH=y +CONFIG_TESTING_OSTEST=y +CONFIG_TESTING_OSTEST_STACKSIZE=16384 +CONFIG_TLS_NCLEANUP=4 +CONFIG_TLS_NELEM=4 +CONFIG_USBDEV=y +CONFIG_USBDEV_DMA=y +CONFIG_USBDEV_DUALSPEED=y diff --git a/boards/arm/imxrt/imxrt1180-evk/include/board.h b/boards/arm/imxrt/imxrt1180-evk/include/board.h new file mode 100644 index 0000000000000..22f2d79407935 --- /dev/null +++ b/boards/arm/imxrt/imxrt1180-evk/include/board.h @@ -0,0 +1,130 @@ +/**************************************************************************** + * boards/arm/imxrt/imxrt1180-evk/include/board.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __BOARDS_ARM_IMXRT_IMXRT1180_EVK_INCLUDE_BOARD_H +#define __BOARDS_ARM_IMXRT_IMXRT1180_EVK_INCLUDE_BOARD_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include "hardware/rt118x/imxrt118x_iomuxc.h" +#include "hardware/rt118x/imxrt118x_pinmux.h" +#include "imxrt_iomuxc.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Clocking *****************************************************************/ + +/* Both cores share ARM_PLL at its supported 798 MHz maximum: + * + * M7 = CLOCK_ROOT0 = ARM_PLL / 1 = 798 MHz + * M33 = CLOCK_ROOT1 = ARM_PLL / 3 = 266 MHz + * + * Both are within the HSRUN maxima of 800 / 300 MHz (IMXRT1180RM Rev. 10 + * Table 128). + * + * BOARD_CPU_FREQUENCY is the frequency of the core this image runs on: it + * drives the SysTick reload value, so it must match the core actually + * executing or the whole system time base is scaled wrong. + */ + +#define BOARD_XTAL_FREQUENCY 24000000 + +#define BOARD_CCM_DOMAIN_CM33 2 +#define BOARD_CCM_DOMAIN_CM7 4 + +#ifdef CONFIG_ARCH_CHIP_MIMXRT1189CVM8C_CM33 +# define BOARD_CPU_FREQUENCY 266000000 +# define BOARD_CCM_DOMAIN_ID BOARD_CCM_DOMAIN_CM33 +#else +# define BOARD_CPU_FREQUENCY 798000000 +# define BOARD_CCM_DOMAIN_ID BOARD_CCM_DOMAIN_CM7 +#endif + +/* LPUART1 pin configuration. The MIMXRT1180-EVK routes LPUART1 to + * GPIO_AON_08 (TX) and GPIO_AON_09 (RX) via the MCU-Link VCOM + * (verified against schematic SCH-50577_C4: net LPUART1_TXD -> RT1180 + * ball B1). + * + * The pad configuration flags are common to peripheral use of the + * LPUART: no pull, high drive strength. + */ + +#define IOMUX_LPUART_DEFAULT (IOMUXC_PAD_PDRV_HIGH | IOMUXC_PAD_PULL_NONE) + +#define GPIO_LPUART1_TX IOMUX_PIN(IOMUXC_PAD_GPIO_AON_08_LPUART1_TX, \ + IOMUX_LPUART_DEFAULT, 0) +#define GPIO_LPUART1_RX IOMUX_PIN(IOMUXC_PAD_GPIO_AON_09_LPUART1_RX, \ + IOMUX_LPUART_DEFAULT, IOMUXC_MUX_SION_ON) + +/* User LEDs: D6 (green) on GPIO_AD_27 = RGPIO4.27, + * D7 (red) on GPIO_AD_26 = RGPIO4.26. + */ + +#define IOMUX_LED_DEFAULT (IOMUXC_PAD_PDRV_HIGH | IOMUXC_PAD_PULL_NONE) + +#define GPIO_LED1 IOMUX_GPIO(IOMUXC_PAD_GPIO_AD_27_GPIO4_IO27, \ + IOMUX_LED_DEFAULT, \ + GPIO_OUTPUT | GPIO_OUTPUT_ZERO | \ + GPIO_PORT4 | GPIO_PIN27) +#define GPIO_LED2 IOMUX_GPIO(IOMUXC_PAD_GPIO_AD_26_GPIO4_IO26, \ + IOMUX_LED_DEFAULT, \ + GPIO_OUTPUT | GPIO_OUTPUT_ZERO | \ + GPIO_PORT4 | GPIO_PIN26) + +/* LPI2C2: routed to on-board sensors, ENET PHY ID EEPROM etc. + * GPIO_AON_15 -> LPI2C2_SDA + * GPIO_AON_16 -> LPI2C2_SCL + */ + +#define IOMUX_LPI2C_DEFAULT (IOMUXC_PAD_PDRV_HIGH | IOMUXC_PAD_PULL_UP | \ + IOMUXC_PAD_ODE_ON) + +#define GPIO_LPI2C2_SDA IOMUX_PIN(IOMUXC_PAD_GPIO_AON_15_LPI2C2_SDA, \ + IOMUX_LPI2C_DEFAULT, IOMUXC_MUX_SION_ON) +#define GPIO_LPI2C2_SCL IOMUX_PIN(IOMUXC_PAD_GPIO_AON_16_LPI2C2_SCL, \ + IOMUX_LPI2C_DEFAULT, IOMUXC_MUX_SION_ON) + +/* LPSPI1: routed to the on-board LPSPI NOR flash (U12 companion). + * GPIO_AON_04 -> LPSPI1_SCK + * GPIO_AON_05 -> LPSPI1_PCS0 + * GPIO_AON_06 -> LPSPI1_SDO + * GPIO_AON_07 -> LPSPI1_SDI + */ + +#define IOMUX_LPSPI_DEFAULT (IOMUXC_PAD_PDRV_HIGH | IOMUXC_PAD_PULL_NONE) + +#define GPIO_LPSPI1_SCK IOMUX_PIN(IOMUXC_PAD_GPIO_AON_04_LPSPI1_SCK, \ + IOMUX_LPSPI_DEFAULT, 0) +#define GPIO_LPSPI1_CS IOMUX_PIN(IOMUXC_PAD_GPIO_AON_05_LPSPI1_PCS0, \ + IOMUX_LPSPI_DEFAULT, 0) +#define GPIO_LPSPI1_MOSI IOMUX_PIN(IOMUXC_PAD_GPIO_AON_06_LPSPI1_SDO, \ + IOMUX_LPSPI_DEFAULT, 0) +#define GPIO_LPSPI1_MISO IOMUX_PIN(IOMUXC_PAD_GPIO_AON_07_LPSPI1_SDI, \ + IOMUX_LPSPI_DEFAULT, IOMUXC_MUX_SION_ON) + +#endif /* __BOARDS_ARM_IMXRT_IMXRT1180_EVK_INCLUDE_BOARD_H */ diff --git a/boards/arm/imxrt/imxrt1180-evk/include/imxrt118x_trdc_config.h b/boards/arm/imxrt/imxrt1180-evk/include/imxrt118x_trdc_config.h new file mode 100644 index 0000000000000..f5fc48a4bf1a3 --- /dev/null +++ b/boards/arm/imxrt/imxrt1180-evk/include/imxrt118x_trdc_config.h @@ -0,0 +1,257 @@ +/**************************************************************************** + * boards/arm/imxrt/imxrt1180-evk/include/imxrt118x_trdc_config.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __BOARDS_ARM_IMXRT_IMXRT1180_EVK_INCLUDE_IMXRT118X_TRDC_CONFIG_H +#define __BOARDS_ARM_IMXRT_IMXRT1180_EVK_INCLUDE_IMXRT118X_TRDC_CONFIG_H + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#define SP(X) ((X) << 12) +#define SU(X) ((X) << 8) +#define NP(X) ((X) << 4) +#define NU(X) ((X) << 0) +#define LK (1 << 31) +#define RWX 7 +#define RW 6 +#define RX 5 +#define R 4 +#define X 1 + +#define TRDC_FULL_ACCESS_GLBAC(id, mbc_mrc) \ + { mbc_mrc, id, SP(RWX) | SU(RWX) | NP(RWX) | NU(RWX) } + +/* Domain identifiers used by the TRDC setup. */ + +#define DID_CM33 BOARD_CCM_DOMAIN_CM33 +#define DID_EDMA3_RESET 4 +#define DID_CM7 BOARD_CCM_DOMAIN_CM7 +#define DID_USDHC1 5 +#define DID_USDHC2 6 +#define DID_DMA 7 +#define DID_EDMA3 DID_DMA +#define DID_EDMA4 DID_DMA +#define DID_CORESIGHT 8 +#define DID_DAP 9 +#define DID_NETC 10 +#define DID_FLEXSPI_FLR DID_NETC +#define DID_USB 11 + +#define TRDC_VALID_DOMAINS_MBC(mbc, mem) \ + { mbc, DID_CM33, mem, MBC_BLK_ALL, 0, true }, \ + { mbc, DID_CM7, mem, MBC_BLK_ALL, 0, true }, \ + { mbc, DID_USDHC1, mem, MBC_BLK_ALL, 0, true }, \ + { mbc, DID_USDHC2, mem, MBC_BLK_ALL, 0, true }, \ + { mbc, DID_DMA, mem, MBC_BLK_ALL, 0, true }, \ + { mbc, DID_CORESIGHT, mem, MBC_BLK_ALL, 0, true }, \ + { mbc, DID_DAP, mem, MBC_BLK_ALL, 0, true }, \ + { mbc, DID_NETC, mem, MBC_BLK_ALL, 0, true }, \ + { mbc, DID_USB, mem, MBC_BLK_ALL, 0, true } + +#define TRDC_VALID_DOMAINS_MRC(mrc, base, size) \ + { mrc, DID_CM33, 0, base, size, 0, true }, \ + { mrc, DID_CM7, 0, base, size, 0, true }, \ + { mrc, DID_USDHC1, 0, base, size, 0, true }, \ + { mrc, DID_USDHC2, 0, base, size, 0, true }, \ + { mrc, DID_DMA, 0, base, size, 0, true }, \ + { mrc, DID_CORESIGHT, 0, base, size, 0, true }, \ + { mrc, DID_DAP, 0, base, size, 0, true }, \ + { mrc, DID_NETC, 0, base, size, 0, true }, \ + { mrc, DID_USB, 0, base, size, 0, true } + +#define TRDC_CM33_ROM_BASE 0x00000000 +#define TRDC_CM33_ROM_SIZE 0x00028000 +#define TRDC_FLEXSPI2_BASE 0x04000000 +#define TRDC_FLEXSPI2_SIZE 0x04000000 +#define TRDC_FLEXSPI1_BASE 0x28000000 +#define TRDC_FLEXSPI1_SIZE 0x08000000 +#define TRDC_CM7_TCM_BASE 0x203c0000 +#define TRDC_CM7_TCM_SIZE 0x00080000 +#define TRDC_OCRAM1_BASE 0x20480000 +#define TRDC_OCRAM1_SIZE 0x00080000 +#define TRDC_OCRAM2_BASE 0x20500000 +#define TRDC_OCRAM2_SIZE 0x00040000 +#define TRDC_SEMC_BASE 0x80000000 +#define TRDC_SEMC_SIZE 0x10000000 +#define TRDC_NETC_BASE 0x60000000 +#define TRDC_NETC_SIZE 0x01000000 + +/* TRDC1 MBC access policy. */ + +struct trdc_glbac_config trdc_a_mbc_glbac[] = +{ + TRDC_FULL_ACCESS_GLBAC(0, 0), /* MBC0 */ + TRDC_FULL_ACCESS_GLBAC(1, 0), + TRDC_FULL_ACCESS_GLBAC(2, 0), + TRDC_FULL_ACCESS_GLBAC(3, 0), + TRDC_FULL_ACCESS_GLBAC(4, 0), + TRDC_FULL_ACCESS_GLBAC(5, 0), + TRDC_FULL_ACCESS_GLBAC(6, 0), + TRDC_FULL_ACCESS_GLBAC(7, 0), + TRDC_FULL_ACCESS_GLBAC(0, 1), /* MBC1 */ + TRDC_FULL_ACCESS_GLBAC(1, 1), + TRDC_FULL_ACCESS_GLBAC(2, 1), + TRDC_FULL_ACCESS_GLBAC(3, 1), + TRDC_FULL_ACCESS_GLBAC(4, 1), + TRDC_FULL_ACCESS_GLBAC(5, 1), + TRDC_FULL_ACCESS_GLBAC(6, 1), + TRDC_FULL_ACCESS_GLBAC(7, 1), +}; + +/* TRDC1 MBC block assignments. */ + +struct trdc_mbc_config trdc_a_mbc[] = +{ + TRDC_VALID_DOMAINS_MBC(0, 0), /* MBC_A0 AIPS1 */ + TRDC_VALID_DOMAINS_MBC(0, 2), /* MBC_A0 GPIO1 */ + TRDC_VALID_DOMAINS_MBC(1, 0), /* MBC_A1 CM33 Code-TCM */ + TRDC_VALID_DOMAINS_MBC(1, 1), /* MBC_A1 CM33 System-TCM */ +}; + +struct trdc_glbac_config trdc_a_mrc_glbac[] = +{ + TRDC_FULL_ACCESS_GLBAC(0, 0), /* MRC0 */ + TRDC_FULL_ACCESS_GLBAC(1, 0), + TRDC_FULL_ACCESS_GLBAC(2, 0), + TRDC_FULL_ACCESS_GLBAC(3, 0), + TRDC_FULL_ACCESS_GLBAC(4, 0), + TRDC_FULL_ACCESS_GLBAC(5, 0), + TRDC_FULL_ACCESS_GLBAC(6, 0), + TRDC_FULL_ACCESS_GLBAC(7, 0), + TRDC_FULL_ACCESS_GLBAC(0, 1), /* MRC1 */ + TRDC_FULL_ACCESS_GLBAC(1, 1), + TRDC_FULL_ACCESS_GLBAC(2, 1), + TRDC_FULL_ACCESS_GLBAC(3, 1), + TRDC_FULL_ACCESS_GLBAC(4, 1), + TRDC_FULL_ACCESS_GLBAC(5, 1), + TRDC_FULL_ACCESS_GLBAC(6, 1), + TRDC_FULL_ACCESS_GLBAC(7, 1), +}; + +struct trdc_mrc_config trdc_a_mrc[] = +{ + TRDC_VALID_DOMAINS_MRC(0, TRDC_CM33_ROM_BASE, TRDC_CM33_ROM_SIZE), + TRDC_VALID_DOMAINS_MRC(1, TRDC_FLEXSPI2_BASE, TRDC_FLEXSPI2_SIZE), +}; + +/* TRDC2 MBC access policy. */ + +struct trdc_glbac_config trdc_w_mbc_glbac[] = +{ + TRDC_FULL_ACCESS_GLBAC(0, 0), /* MBC0 */ + TRDC_FULL_ACCESS_GLBAC(1, 0), + TRDC_FULL_ACCESS_GLBAC(2, 0), + TRDC_FULL_ACCESS_GLBAC(3, 0), + TRDC_FULL_ACCESS_GLBAC(4, 0), + TRDC_FULL_ACCESS_GLBAC(5, 0), + TRDC_FULL_ACCESS_GLBAC(6, 0), + TRDC_FULL_ACCESS_GLBAC(7, 0), + TRDC_FULL_ACCESS_GLBAC(0, 1), /* MBC1 */ + TRDC_FULL_ACCESS_GLBAC(1, 1), + TRDC_FULL_ACCESS_GLBAC(2, 1), + TRDC_FULL_ACCESS_GLBAC(3, 1), + TRDC_FULL_ACCESS_GLBAC(4, 1), + TRDC_FULL_ACCESS_GLBAC(5, 1), + TRDC_FULL_ACCESS_GLBAC(6, 1), + TRDC_FULL_ACCESS_GLBAC(7, 1), +}; + +/* TRDC2 MBC block assignments. */ + +struct trdc_mbc_config trdc_w_mbc[] = +{ + TRDC_VALID_DOMAINS_MBC(0, 0), /* MBC_W0 AIPS2 */ + TRDC_VALID_DOMAINS_MBC(0, 1), /* MBC_W0 GPIO2/4/6 */ + TRDC_VALID_DOMAINS_MBC(0, 2), /* MBC_W0 GPIO3/5 */ + TRDC_VALID_DOMAINS_MBC(0, 3), /* MBC_W0 DAP */ + TRDC_VALID_DOMAINS_MBC(1, 0), /* MBC_W1 AIPS3 */ + TRDC_VALID_DOMAINS_MBC(1, 1), /* MBC_W1 AHB_ISPAP */ + TRDC_VALID_DOMAINS_MBC(1, 2), /* MBC_W1 NIC_MAIN GPV */ + TRDC_VALID_DOMAINS_MBC(1, 3), /* MBC_W1 SRAMC */ +}; + +struct trdc_glbac_config trdc_w_mrc_glbac[] = +{ + TRDC_FULL_ACCESS_GLBAC(0, 1), /* MRC1 */ + TRDC_FULL_ACCESS_GLBAC(1, 1), + TRDC_FULL_ACCESS_GLBAC(2, 1), + TRDC_FULL_ACCESS_GLBAC(3, 1), + TRDC_FULL_ACCESS_GLBAC(4, 1), + TRDC_FULL_ACCESS_GLBAC(5, 1), + TRDC_FULL_ACCESS_GLBAC(6, 1), + TRDC_FULL_ACCESS_GLBAC(7, 1), + TRDC_FULL_ACCESS_GLBAC(0, 2), /* MRC2 */ + TRDC_FULL_ACCESS_GLBAC(1, 2), + TRDC_FULL_ACCESS_GLBAC(2, 2), + TRDC_FULL_ACCESS_GLBAC(3, 2), + TRDC_FULL_ACCESS_GLBAC(4, 2), + TRDC_FULL_ACCESS_GLBAC(5, 2), + TRDC_FULL_ACCESS_GLBAC(6, 2), + TRDC_FULL_ACCESS_GLBAC(7, 2), + TRDC_FULL_ACCESS_GLBAC(0, 3), /* MRC3 */ + TRDC_FULL_ACCESS_GLBAC(1, 3), + TRDC_FULL_ACCESS_GLBAC(2, 3), + TRDC_FULL_ACCESS_GLBAC(3, 3), + TRDC_FULL_ACCESS_GLBAC(4, 3), + TRDC_FULL_ACCESS_GLBAC(5, 3), + TRDC_FULL_ACCESS_GLBAC(6, 3), + TRDC_FULL_ACCESS_GLBAC(7, 3), + TRDC_FULL_ACCESS_GLBAC(0, 4), /* MRC4 */ + TRDC_FULL_ACCESS_GLBAC(1, 4), + TRDC_FULL_ACCESS_GLBAC(2, 4), + TRDC_FULL_ACCESS_GLBAC(3, 4), + TRDC_FULL_ACCESS_GLBAC(4, 4), + TRDC_FULL_ACCESS_GLBAC(5, 4), + TRDC_FULL_ACCESS_GLBAC(6, 4), + TRDC_FULL_ACCESS_GLBAC(7, 4), + TRDC_FULL_ACCESS_GLBAC(0, 5), /* MRC5 */ + TRDC_FULL_ACCESS_GLBAC(1, 5), + TRDC_FULL_ACCESS_GLBAC(2, 5), + TRDC_FULL_ACCESS_GLBAC(3, 5), + TRDC_FULL_ACCESS_GLBAC(4, 5), + TRDC_FULL_ACCESS_GLBAC(5, 5), + TRDC_FULL_ACCESS_GLBAC(6, 5), + TRDC_FULL_ACCESS_GLBAC(7, 5), + TRDC_FULL_ACCESS_GLBAC(0, 6), /* MRC6 */ + TRDC_FULL_ACCESS_GLBAC(1, 6), + TRDC_FULL_ACCESS_GLBAC(2, 6), + TRDC_FULL_ACCESS_GLBAC(3, 6), + TRDC_FULL_ACCESS_GLBAC(4, 6), + TRDC_FULL_ACCESS_GLBAC(5, 6), + TRDC_FULL_ACCESS_GLBAC(6, 6), + TRDC_FULL_ACCESS_GLBAC(7, 6), +}; + +/* TRDC2 MRC region assignments. */ + +struct trdc_mrc_config trdc_w_mrc[] = +{ + TRDC_VALID_DOMAINS_MRC(1, TRDC_FLEXSPI1_BASE, TRDC_FLEXSPI1_SIZE), + TRDC_VALID_DOMAINS_MRC(2, TRDC_CM7_TCM_BASE, TRDC_CM7_TCM_SIZE), + TRDC_VALID_DOMAINS_MRC(3, TRDC_OCRAM1_BASE, TRDC_OCRAM1_SIZE), + TRDC_VALID_DOMAINS_MRC(4, TRDC_OCRAM2_BASE, TRDC_OCRAM2_SIZE), + TRDC_VALID_DOMAINS_MRC(5, TRDC_SEMC_BASE, TRDC_SEMC_SIZE), + TRDC_VALID_DOMAINS_MRC(6, TRDC_NETC_BASE, TRDC_NETC_SIZE), +}; + +#endif /* __BOARDS_ARM_IMXRT_IMXRT1180_EVK_INCLUDE_IMXRT118X_TRDC_CONFIG_H */ diff --git a/boards/arm/imxrt/imxrt1180-evk/scripts/Make.defs b/boards/arm/imxrt/imxrt1180-evk/scripts/Make.defs new file mode 100644 index 0000000000000..3566b440d9039 --- /dev/null +++ b/boards/arm/imxrt/imxrt1180-evk/scripts/Make.defs @@ -0,0 +1,107 @@ +############################################################################ +# boards/arm/imxrt/imxrt1180-evk/scripts/Make.defs +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more +# contributor license agreements. See the NOTICE file distributed with +# this work for additional information regarding copyright ownership. The +# ASF licenses this file to you under the Apache License, Version 2.0 (the +# "License"); you may not use this file except in compliance with the +# License. You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations +# under the License. +# +############################################################################ + +include $(TOPDIR)/.config +include $(TOPDIR)/tools/Config.mk + +# Select the right Toolchain.defs (ARMv7-M for the M7 build, ARMv8-M for the +# M33 build) and the matching per-core linker script. + +ifeq ($(CONFIG_ARCH_CORTEXM33),y) +include $(TOPDIR)/arch/arm/src/armv8-m/Toolchain.defs +LDSCRIPT = flash-m33.ld +else +include $(TOPDIR)/arch/arm/src/armv7-m/Toolchain.defs +LDSCRIPT = flash.ld +endif + +ARCHSCRIPT += $(BOARD_DIR)$(DELIM)scripts$(DELIM)$(LDSCRIPT) + +ARCHPICFLAGS = -fpic -msingle-pic-base -mpic-register=r10 + +CFLAGS := $(ARCHCFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) -pipe +CPICFLAGS = $(ARCHPICFLAGS) $(CFLAGS) +CXXFLAGS := $(ARCHCXXFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHXXINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) -pipe +CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS) +CPPFLAGS := $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) +AFLAGS := $(CFLAGS) -D__ASSEMBLY__ + +# Post-build: assemble the flashable image "flash.bin" for CM33 builds. +# +# CM33 builds +# flash.bin = FCB (0x400) +# + AHAB container (this NuttX image) at 0x1000 +# Programmed at FlexSPI offset 0 (flash address 0x28000000). The M33 +# image is confined to the first 512 KB of NOR. +# +# The AHAB container is assembled by NXP SPSDK "nxpimage". The build +# script bootstraps a private SPSDK venv on first run (see +# tools/imxrt1180/build_flash_image.sh for the license note and cache +# location). +# +# CONFIG_IMXRT_ELE_LOAD_FW selects which of the two mutually exclusive +# ELE firmware loading methods is built into the flash image: +# +# - disabled (the default): the NXP EdgeLock Enclave firmware +# (CONFIG_IMXRT_ELE_FW_PATH) is packed as a second image inside the +# AHAB container, so the RT118x ROM loads it automatically +# - enabled: the firmware is embedded in the NuttX image and +# loaded into the ELE at runtime via a LOAD_FW command. + +FLASH_BUILDER = $(TOPDIR)$(DELIM)tools$(DELIM)imxrt1180$(DELIM)build_flash_image.sh + +ifeq ($(CONFIG_IMXRT_ELE),y) +include $(TOPDIR)/tools/imxrt1180/Config.mk + +# Restore "all" as the default goal: Config.mk's FW target would +# otherwise become it, since this file is included before "all" is +# defined. +.DEFAULT_GOAL := all +endif + +ifeq ($(CONFIG_IMXRT_ELE_LOAD_FW),y) +FLASH_BUILDER_ELE_FW_ARGS = +else +ifeq ($(CONFIG_IMXRT_ELE),y) +FLASH_BUILDER_ELE_FW_ARGS = --ele-fw $(IMXRT_ELE_FW_ABS) +else +FLASH_BUILDER_ELE_FW_ARGS = +endif +endif + +ifeq ($(CONFIG_ARCH_CORTEXM33),y) +define POSTBUILD + $(Q) echo "Assembling MIMXRT1180-EVK FlexSPI NOR image (CM33 target)" + $(Q) $(OBJCOPY) -O binary -R .bss -R .initstack $(BIN) nuttx.bin + $(Q) $(MAKE) $(IMXRT_ELE_FW_ABS) + $(Q) $(FLASH_BUILDER) \ + --m33 nuttx.bin \ + --out flash.bin \ + $(FLASH_BUILDER_ELE_FW_ARGS) + $(Q) echo "flash.bin" >> nuttx.manifest +endef +else +define POSTBUILD + $(Q) echo "Building MIMXRT1180-EVK Cortex-M7 payload (nuttx.bin)" + $(Q) $(OBJCOPY) -O binary -R .bss -R .initstack $(BIN) nuttx.bin +endef +endif diff --git a/boards/arm/imxrt/imxrt1180-evk/scripts/flash-m33.ld b/boards/arm/imxrt/imxrt1180-evk/scripts/flash-m33.ld new file mode 100644 index 0000000000000..26f901bbc83b2 --- /dev/null +++ b/boards/arm/imxrt/imxrt1180-evk/scripts/flash-m33.ld @@ -0,0 +1,190 @@ +/**************************************************************************** + * boards/arm/imxrt/imxrt1180-evk/scripts/flash-m33.ld + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/* Linker script for the imxrt1180-evk NuttX build targeting the Cortex-M33 + * core (nsh-m33 config). This is a fully independent image; there is no + * M33 stub in front of it — the ROM's AHAB flow loads NuttX itself onto + * the M33. + * + * Layout of flash.bin (assembled by tools/imxrt1180/build_flash_image.sh): + * + * 0x2800_0400 FCB (baked into this image via .boot_hdr.conf) + * 0x2800_1000 NXP ELE FW AHAB container (injected by build script) + * 0x2800_?000 Our AHAB container header (injected by build script) + * 0x2800_B000 This image's .vectors and .text (XIP) + * + * The M33 image is confined to the first 512 KB of FlexSPI1 NOR; the + * Cortex-M7 image (scripts/flash.ld) starts at 0x2808_0000. + * + * Data/BSS live in the M33 System TCM at 0x2000_0000 (128 KB). Code TCM + * (0x0FFE_0000, 128 KB) is left alone for possible ramfuncs. + * + * USB DMA buffers cannot live in System TCM, since it is not reachable + * by the USB controller's DMA engine. These buffers are placed in the + * `.dmamemory` section in OCRAM2 instead (see imxrt_dma_alloc.c). + */ + +MEMORY +{ + flash (rx) : ORIGIN = 0x28000000, LENGTH = 512K /* FlexSPI XIP window reserved for the M33 image */ + systcm (rwx): ORIGIN = 0x20000000, LENGTH = 128K /* CM33 private System TCM */ + ocram2 (rw) : ORIGIN = 0x20500000, LENGTH = 16K /* OCRAM2 (DMA/TRDC accessible); USB DMA buffers only */ +} + +OUTPUT_ARCH(arm) +EXTERN(_vectors) +EXTERN(g_flash_config) +ENTRY(_stext) + +SECTIONS +{ + /* FCB slot at the ROM-mandated offset. */ + + .fcb 0x28000400 : ALIGN(4) + { + KEEP(*(.boot_hdr.conf)) + . = ALIGN(4); + } > flash + + /* Vector table + code at the fixed XIP address the ROM's AHAB flow + * will jump to after loading the ELE FW and validating our container. + */ + + .text 0x2800B000 : ALIGN(4) + { + _stext = ABSOLUTE(.); + *(.vectors) + *(.text .text.*) + *(.fixup) + *(.gnu.warning) + *(.rodata .rodata.*) + *(.gnu.linkonce.t.*) + *(.glue_7) + *(.glue_7t) + *(.got) + *(.gcc_except_table) + *(.gnu.linkonce.r.*) + _etext = ABSOLUTE(.); + } > flash + + .init_section : + { + _sinit = ABSOLUTE(.); + *(.init_array .init_array.*) + _einit = ABSOLUTE(.); + } > flash + + .ARM.extab : + { + *(.ARM.extab*) + } > flash + + .ARM.exidx : + { + __exidx_start = ABSOLUTE(.); + *(.ARM.exidx*) + __exidx_end = ABSOLUTE(.); + } > flash + + .tdata : + { + _stdata = ABSOLUTE(.); + *(.tdata .tdata.* .gnu.linkonce.td.*) + _etdata = ABSOLUTE(.); + } > flash + + .tbss : + { + _stbss = ABSOLUTE(.); + *(.tbss .tbss.* .gnu.linkonce.tb.* .tcommon) + _etbss = ABSOLUTE(.); + } > flash + + _eronly = ABSOLUTE(.); + + .data : + { + _sdata = ABSOLUTE(.); + *(.data .data.*) + *(.gnu.linkonce.d.*) + CONSTRUCTORS + . = ALIGN(4); + _edata = ABSOLUTE(.); + } > systcm AT > flash + + .ramfunc ALIGN(4): + { + _sramfuncs = ABSOLUTE(.); + *(.ramfunc .ramfunc.*) + _eramfuncs = ABSOLUTE(.); + } > systcm AT > flash + + _framfuncs = LOADADDR(.ramfunc); + + .bss : + { + _sbss = ABSOLUTE(.); + *(.bss .bss.*) + *(.gnu.linkonce.b.*) + *(COMMON) + . = ALIGN(8); + _ebss = ABSOLUTE(.); + } > systcm + + /* USB DMA-reachable buffers (endpoint queue heads/transfer + * descriptors, etc). See the OCRAM2 rationale above. + */ + + .dmamemory (NOLOAD) : + { + _sdmamemory = ABSOLUTE(.); + *(.dmamemory .dmamemory.*) + . = ALIGN(4); + _edmamemory = ABSOLUTE(.); + } > ocram2 + + /* Stabs debugging sections. */ + + .stab 0 : { *(.stab) } + .stabstr 0 : { *(.stabstr) } + .stab.excl 0 : { *(.stab.excl) } + .stab.exclstr 0 : { *(.stab.exclstr) } + .stab.index 0 : { *(.stab.index) } + .stab.indexstr 0 : { *(.stab.indexstr) } + .comment 0 : { *(.comment) } + .debug_abbrev 0 : { *(.debug_abbrev) } + .debug_info 0 : { *(.debug_info) } + .debug_line 0 : { *(.debug_line) } + .debug_pubnames 0 : { *(.debug_pubnames) } + .debug_aranges 0 : { *(.debug_aranges) } + + _boot_loadaddr = ORIGIN(flash); + _boot_size = LENGTH(flash); + _ram_size = LENGTH(systcm); +} + +/* The M7 image starts at 0x2808_0000. Fail the link rather than silently + * producing an M33 image that runs into it. + */ + +ASSERT(ORIGIN(flash) + LENGTH(flash) <= 0x28080000, + "M33 flash region overlaps the M7 image at 0x28080000") diff --git a/boards/arm/imxrt/imxrt1180-evk/scripts/flash.ld b/boards/arm/imxrt/imxrt1180-evk/scripts/flash.ld new file mode 100644 index 0000000000000..09e23a86f3692 --- /dev/null +++ b/boards/arm/imxrt/imxrt1180-evk/scripts/flash.ld @@ -0,0 +1,153 @@ +/**************************************************************************** + * boards/arm/imxrt/imxrt1180-evk/scripts/flash.ld + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/* The Cortex-M7 image is a raw XIP payload; it carries no FCB and no AHAB + * container of its own. The M33 image (the "bl" bootloader config, or any + * other M33 build) owns the first 512 KB of FlexSPI1 NOR and releases the + * M7 with INITVTOR pointing at this payload. + * + * FlexSPI1 NOR layout: + * + * 0x2800_0000 .. 0x2807_FFFF M33 image (512 KB reserved) + * 0x2808_0000 .. 0x287F_FFFF M7 image (this script, 7.5 MB window) + * + * NuttX's stack, .data, .ramfunc and .bss live in OCRAM1, which the M33 + * grants the M7 R/W/X through TRDC2 MRC_W3 before releasing it. DTCM and + * ITCM are declared above but are not used by any section; they are + * tightly-coupled to the M7 core and have no TRDC in the access path, so + * they remain available for opt-in placement. + */ + +MEMORY +{ + flash (rx) : ORIGIN = 0x28080000, LENGTH = 4M /* Cortex-M7 XIP window (after the 512K M33/bl reserve) */ + ocram (rwx) : ORIGIN = 0x20484000, LENGTH = 480K /* OCRAM1 minus ROM patch (0x20480000..0x20483fff) and M33 reserve (0x204fc000..0x204fffff) */ + dtcm (rwx) : ORIGIN = 0x20000000, LENGTH = 256K /* M7 DTCM (opt-in) */ + itcm (rwx) : ORIGIN = 0x00000000, LENGTH = 256K /* M7 ITCM (opt-in) */ +} + +OUTPUT_ARCH(arm) +EXTERN(_vectors) +ENTRY(_stext) + +SECTIONS +{ + .text : ALIGN(4) + { + _stext = ABSOLUTE(.); + *(.vectors) + *(.text .text.*) + *(.fixup) + *(.gnu.warning) + *(.rodata .rodata.*) + *(.gnu.linkonce.t.*) + *(.glue_7) + *(.glue_7t) + *(.got) + *(.gcc_except_table) + *(.gnu.linkonce.r.*) + _etext = ABSOLUTE(.); + } > flash + + .init_section : + { + _sinit = ABSOLUTE(.); + *(.init_array .init_array.*) + _einit = ABSOLUTE(.); + } > flash + + .ARM.extab : + { + *(.ARM.extab*) + } > flash + + .ARM.exidx : + { + __exidx_start = ABSOLUTE(.); + *(.ARM.exidx*) + __exidx_end = ABSOLUTE(.); + } > flash + + .tdata : + { + _stdata = ABSOLUTE(.); + *(.tdata .tdata.* .gnu.linkonce.td.*) + _etdata = ABSOLUTE(.); + } > flash + + .tbss : + { + _stbss = ABSOLUTE(.); + *(.tbss .tbss.* .gnu.linkonce.tb.* .tcommon) + _etbss = ABSOLUTE(.); + } > flash + + _eronly = ABSOLUTE(.); + + .data : + { + _sdata = ABSOLUTE(.); + *(.data .data.*) + *(.gnu.linkonce.d.*) + CONSTRUCTORS + . = ALIGN(4); + _edata = ABSOLUTE(.); + } > ocram AT > flash + + .ramfunc ALIGN(4): + { + _sramfuncs = ABSOLUTE(.); + *(.ramfunc .ramfunc.*) + _eramfuncs = ABSOLUTE(.); + } > ocram AT > flash + + _framfuncs = LOADADDR(.ramfunc); + + .bss : + { + _sbss = ABSOLUTE(.); + *(.bss .bss.*) + *(.gnu.linkonce.b.*) + *(COMMON) + . = ALIGN(8); + _ebss = ABSOLUTE(.); + } > ocram + + /* Stabs debugging sections. */ + + .stab 0 : { *(.stab) } + .stabstr 0 : { *(.stabstr) } + .stab.excl 0 : { *(.stab.excl) } + .stab.exclstr 0 : { *(.stab.exclstr) } + .stab.index 0 : { *(.stab.index) } + .stab.indexstr 0 : { *(.stab.indexstr) } + .comment 0 : { *(.comment) } + .debug_abbrev 0 : { *(.debug_abbrev) } + .debug_info 0 : { *(.debug_info) } + .debug_line 0 : { *(.debug_line) } + .debug_pubnames 0 : { *(.debug_pubnames) } + .debug_aranges 0 : { *(.debug_aranges) } + + _boot_loadaddr = ORIGIN(flash); + _boot_size = LENGTH(flash); + _ram_size = LENGTH(ocram); +} diff --git a/boards/arm/imxrt/imxrt1180-evk/src/Makefile b/boards/arm/imxrt/imxrt1180-evk/src/Makefile new file mode 100644 index 0000000000000..bc6e9e10913b6 --- /dev/null +++ b/boards/arm/imxrt/imxrt1180-evk/src/Makefile @@ -0,0 +1,51 @@ +############################################################################ +# boards/arm/imxrt/imxrt1180-evk/src/Makefile +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more +# contributor license agreements. See the NOTICE file distributed with +# this work for additional information regarding copyright ownership. The +# ASF licenses this file to you under the Apache License, Version 2.0 (the +# "License"); you may not use this file except in compliance with the +# License. You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations +# under the License. +# +############################################################################ + +include $(TOPDIR)/Make.defs + +CSRCS = imxrt_boot.c imxrt_bringup.c imxrt_appinit.c + +# On the M33 target the ROM boots our image directly, so we must supply the +# FlexSPI Configuration Block ourselves. The M7 image is a raw XIP payload +# and carries no flash headers. + +ifeq ($(CONFIG_ARCH_CORTEXM33),y) +CSRCS += imxrt_flash_headers.c +endif + +ifeq ($(CONFIG_IMXRT1180_EVK_BOOTLOADER),y) +CSRCS += imxrt_bootloader.c +endif + +ifeq ($(CONFIG_USBDEV_DMAMEMORY),y) +CSRCS += imxrt_dma_alloc.c +endif + +# TRDC descriptors can only be programmed by the core that owns them, which +# is the M33 (CONFIG_IMXRT_TRDC is selected only by the M33 chip choice). +# There is no weak fallback for the board hook: if TRDC is enabled the board +# must supply an access policy, or the link fails. + +ifeq ($(CONFIG_IMXRT_TRDC),y) +endif + +include $(TOPDIR)/boards/Board.mk diff --git a/boards/arm/imxrt/imxrt1180-evk/src/imxrt1180-evk.h b/boards/arm/imxrt/imxrt1180-evk/src/imxrt1180-evk.h new file mode 100644 index 0000000000000..648878bb21948 --- /dev/null +++ b/boards/arm/imxrt/imxrt1180-evk/src/imxrt1180-evk.h @@ -0,0 +1,45 @@ +/**************************************************************************** + * boards/arm/imxrt/imxrt1180-evk/src/imxrt1180-evk.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __BOARDS_ARM_IMXRT_IMXRT1180_EVK_SRC_IMXRT1180_EVK_H +#define __BOARDS_ARM_IMXRT_IMXRT1180_EVK_SRC_IMXRT1180_EVK_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include + +#include + +/**************************************************************************** + * Public Function Prototypes + ****************************************************************************/ + +int imxrt_bringup(void); + +#ifdef CONFIG_USBDEV_DMAMEMORY +int imxrt_dma_alloc_init(void); +#endif + +#endif /* __BOARDS_ARM_IMXRT_IMXRT1180_EVK_SRC_IMXRT1180_EVK_H */ diff --git a/boards/arm/imxrt/imxrt1180-evk/src/imxrt_appinit.c b/boards/arm/imxrt/imxrt1180-evk/src/imxrt_appinit.c new file mode 100644 index 0000000000000..c2d7a1808878a --- /dev/null +++ b/boards/arm/imxrt/imxrt1180-evk/src/imxrt_appinit.c @@ -0,0 +1,53 @@ +/**************************************************************************** + * boards/arm/imxrt/imxrt1180-evk/src/imxrt_appinit.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include + +#include "imxrt1180-evk.h" + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: board_app_initialize + * + * Description: + * Perform application-specific initialization. + * + ****************************************************************************/ + +int board_app_initialize(uintptr_t arg) +{ +#ifdef CONFIG_BOARD_LATE_INITIALIZE + return 0; +#else + return imxrt_bringup(); +#endif +} diff --git a/boards/arm/imxrt/imxrt1180-evk/src/imxrt_boot.c b/boards/arm/imxrt/imxrt1180-evk/src/imxrt_boot.c new file mode 100644 index 0000000000000..8197792d8586a --- /dev/null +++ b/boards/arm/imxrt/imxrt1180-evk/src/imxrt_boot.c @@ -0,0 +1,73 @@ +/**************************************************************************** + * boards/arm/imxrt/imxrt1180-evk/src/imxrt_boot.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include + +#include + +#include "arm_internal.h" +#include "imxrt_iomuxc.h" +#include "imxrt_gpio.h" +#include "imxrt_clockconfig.h" + +#include "imxrt1180-evk.h" + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: imxrt_boardinitialize + * + * Description: + * All i.MX RT architectures must provide the following entry point. This + * entry point is called early in the initialization -- after clocking and + * memory have been configured but before caches have been enabled and + * before any devices have been initialized. + * + ****************************************************************************/ + +void imxrt_boardinitialize(void) +{ + /* Configure the two user LEDs */ + + imxrt_clockall_gpio4(); + imxrt_config_gpio(GPIO_LED1); + imxrt_config_gpio(GPIO_LED2); + imxrt_gpio_write(GPIO_LED2, true); +} + +/**************************************************************************** + * Name: board_late_initialize + ****************************************************************************/ + +#ifdef CONFIG_BOARD_LATE_INITIALIZE +void board_late_initialize(void) +{ + imxrt_bringup(); +} +#endif diff --git a/boards/arm/imxrt/imxrt1180-evk/src/imxrt_bootloader.c b/boards/arm/imxrt/imxrt1180-evk/src/imxrt_bootloader.c new file mode 100644 index 0000000000000..6e56f2a3469df --- /dev/null +++ b/boards/arm/imxrt/imxrt1180-evk/src/imxrt_bootloader.c @@ -0,0 +1,75 @@ +/**************************************************************************** + * boards/arm/imxrt/imxrt1180-evk/src/imxrt_bootloader.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include +#include + +#include "imxrt118x_start_cm7.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#define M7_ENTRY 0x28080000u + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: bootloader_main + * + * Description: + * Release the Cortex-M7 and sleep forever. + * + ****************************************************************************/ + +int bootloader_main(int argc, char *argv[]) +{ + /* Hand over LPUART1 to the M7: disable the IRQ on the M33 NVIC and + * detach its handler. + */ + + up_disable_irq(IMXRT_IRQ_LPUART1); + irq_detach(IMXRT_IRQ_LPUART1); + + if (imxrt118x_release_cm7(M7_ENTRY) < 0) + { + return EXIT_FAILURE; + } + + while (1) + { + usleep(10000); + } + + return 0; +} diff --git a/boards/arm/imxrt/imxrt1180-evk/src/imxrt_bringup.c b/boards/arm/imxrt/imxrt1180-evk/src/imxrt_bringup.c new file mode 100644 index 0000000000000..7ce286c249095 --- /dev/null +++ b/boards/arm/imxrt/imxrt1180-evk/src/imxrt_bringup.c @@ -0,0 +1,71 @@ +/**************************************************************************** + * boards/arm/imxrt/imxrt1180-evk/src/imxrt_bringup.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include + +#include + +#include "imxrt1180-evk.h" + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: imxrt_bringup + * + * Description: + * Bring up board resources. For the minimal MIMXRT1180-EVK NSH + * configuration this only mounts /proc when procfs is enabled. + * + ****************************************************************************/ + +int imxrt_bringup(void) +{ + int ret = OK; + +#ifdef CONFIG_USBDEV_DMAMEMORY + ret = imxrt_dma_alloc_init(); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: Failed to initialize DMA allocator: %d\n", + ret); + } +#endif + +#ifdef CONFIG_FS_PROCFS + ret = nx_mount(NULL, "/proc", "procfs", 0, NULL); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: Failed to mount procfs: %d\n", ret); + } +#endif + + return ret; +} diff --git a/boards/arm/imxrt/imxrt1180-evk/src/imxrt_dma_alloc.c b/boards/arm/imxrt/imxrt1180-evk/src/imxrt_dma_alloc.c new file mode 100644 index 0000000000000..0b6218201f3e6 --- /dev/null +++ b/boards/arm/imxrt/imxrt1180-evk/src/imxrt_dma_alloc.c @@ -0,0 +1,160 @@ +/**************************************************************************** + * boards/arm/imxrt/imxrt1180-evk/src/imxrt_dma_alloc.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +#include +#include + +#include "imxrt1180-evk.h" + +#if defined(CONFIG_GRAN) + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* On the imxrt1180-evk M33 image, .data/.bss/heap live in the CM33's + * private System TCM, which the USB controller's DMA engine cannot reach + * (it isn't part of the TRDC-controlled shared memory map). The USB + * class driver's request buffers (imxrt_epallocbuffer()/usbdev_dma_alloc()) + * must therefore come from a separate, DMA-reachable pool. We put that + * pool in the same OCRAM2 `.dmamemory` linker section already used for the + * USB controller's endpoint queue heads/transfer descriptors and EP0 + * buffer (see arch/arm/src/imxrt/imxrt_usbdev.c and + * boards/arm/imxrt/imxrt1180-evk/scripts/flash-m33.ld). + * + * The pool must be big enough for all buffers that can be concurrently + * allocated by the bound class driver. For CDC/ACM with the default + * config (4 read + 4 write requests) this is roughly: + * 1 x CDCACM_MXDESCLEN (ctrlreq, 64B) + * CONFIG_CDCACM_NRDREQS x CONFIG_CDCACM_BULKOUT_REQLEN (4 x 512 = 2048B) + * CONFIG_CDCACM_NWRREQS x CONFIG_CDCACM_BULKIN_REQLEN (4 x 96 = 384B) + * i.e. ~2.5KB; round up generously to leave headroom for granule/alignment + * overhead and other endpoints. + */ + +#define IMXRT_DMA_POOL_SIZE (6 * 1024) + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +static GRAN_HANDLE g_dma_allocator; + +static uint8_t g_dma_heap[IMXRT_DMA_POOL_SIZE] + locate_data(".dmamemory") + aligned_data(32); + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: imxrt_dma_alloc_init + * + * Description: + * Initialize the DMA-reachable memory pool used to back board USB + * device request buffers. Called once from board bringup, before any + * USB device activity. + * + ****************************************************************************/ + +int imxrt_dma_alloc_init(void) +{ + g_dma_allocator = gran_initialize(g_dma_heap, + sizeof(g_dma_heap), + 5, /* 32-byte granule */ + 5); /* 32-byte alignment */ + + return g_dma_allocator == NULL ? -ENOMEM : OK; +} + +/**************************************************************************** + * Name: usbdev_dma_alloc + * + * Description: + * Allocate a DMA-reachable buffer for use by a USB device driver. + * + * gran_free() needs to know the size of the allocation being freed, but + * usbdev_dma_free() is not given a size (see include/nuttx/usb/usbdev.h). + * We work around this by prepending a small header that records the + * total granule allocation size. + * + ****************************************************************************/ + +struct usbdma_header_s +{ + size_t allocsize; +}; + +void *usbdev_dma_alloc(size_t size) +{ + struct usbdma_header_s *hdr; + size_t allocsize; + + DEBUGASSERT(g_dma_allocator != NULL); + + allocsize = size + sizeof(struct usbdma_header_s); + hdr = gran_alloc(g_dma_allocator, allocsize); + if (hdr == NULL) + { + return NULL; + } + + hdr->allocsize = allocsize; + return (void *)(hdr + 1); +} + +/**************************************************************************** + * Name: usbdev_dma_free + * + * Description: + * Free a DMA-reachable buffer previously allocated with + * usbdev_dma_alloc(). + * + ****************************************************************************/ + +void usbdev_dma_free(void *mem) +{ + struct usbdma_header_s *hdr; + + DEBUGASSERT(g_dma_allocator != NULL); + + if (mem == NULL) + { + return; + } + + hdr = ((struct usbdma_header_s *)mem) - 1; + gran_free(g_dma_allocator, hdr, hdr->allocsize); +} + +#endif /* CONFIG_GRAN */ diff --git a/boards/arm/imxrt/imxrt1180-evk/src/imxrt_flash_headers.c b/boards/arm/imxrt/imxrt1180-evk/src/imxrt_flash_headers.c new file mode 100644 index 0000000000000..fb858c8396b0d --- /dev/null +++ b/boards/arm/imxrt/imxrt1180-evk/src/imxrt_flash_headers.c @@ -0,0 +1,218 @@ +/**************************************************************************** + * boards/arm/imxrt/imxrt1180-evk/src/imxrt_flash_headers.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +/* Flash headers baked into the M33 boot image at the offsets the RT1180 + * ROM expects (IMXRT1180RM Ch. 12 Fig. 50): + * + * 0x0000_0400 Serial NOR Flash Configuration Block (FCB, 512 B) + * + * The AHAB container is NOT baked into this object file. It is added + * later by tools/imxrt1180/build_flash_image.sh, which invokes NXP's + * SPSDK "nxpimage" tool to assemble: + * + * 0x0000_?000 Application AHAB container (this M33 image) + * + * The Cortex-M7 image is flashed separately at offset 0x0008_0000 and is + * a raw XIP payload with no flash headers of its own. + * + * The M7 payload is not wrapped in an AHAB container: the M33 bootloader + * ("bl" configuration) points the M7 at raw flash offset 0x80000 (XIP + * address 0x28080000) and releases it by clearing M7_CFG.WAIT. + * + * The board fits a Winbond W25Q128JWSIQ (16 MB, 1.8 V QSPI) on + * FlexSPI1 Port A (verified in the MIMXRT1180-EVK schematic, ref U12). + */ + +#include + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* FlexSPI Configuration Block (FCB) */ + +#define FLEXSPI_LUT_OPCODE0(x) ((uint32_t)((x) & 0x3f) << 10) +#define FLEXSPI_LUT_NUM_PADS0(x) ((uint32_t)((x) & 0x03) << 8) +#define FLEXSPI_LUT_OPERAND0(x) ((uint32_t)((x) & 0xff)) +#define FLEXSPI_LUT_OPCODE1(x) ((uint32_t)((x) & 0x3f) << 26) +#define FLEXSPI_LUT_NUM_PADS1(x) ((uint32_t)((x) & 0x03) << 24) +#define FLEXSPI_LUT_OPERAND1(x) ((uint32_t)((x) & 0xff) << 16) + +#define FLEXSPI_LUT_SEQ(c0, p0, o0, c1, p1, o1) \ + (FLEXSPI_LUT_OPERAND0(o0) | FLEXSPI_LUT_NUM_PADS0(p0) | \ + FLEXSPI_LUT_OPCODE0(c0) | FLEXSPI_LUT_OPERAND1(o1) | \ + FLEXSPI_LUT_NUM_PADS1(p1) | FLEXSPI_LUT_OPCODE1(c1)) + +#define CMD_SDR 0x01 +#define RADDR_SDR 0x02 +#define DUMMY_SDR 0x0c +#define READ_SDR 0x09 +#define WRITE_SDR 0x08 +#define STOP 0x00 + +#define FLEXSPI_1PAD 0 +#define FLEXSPI_4PAD 2 + +/**************************************************************************** + * Private Types + ****************************************************************************/ + +/* Layout matches IMXRT1180RM Ch. 12 Table 62/65 (identical to the RT1170 + * FCB layout so we can reuse the flexspi_nor_config_s / flexspi_mem_config_s + * struct definitions from the imxrt1170-evk board without change). + */ + +struct flexspi_lut_seq_s +{ + uint8_t seq_num; + uint8_t seq_id; + uint16_t reserved; +}; + +struct flexspi_mem_config_s +{ + uint32_t tag; + uint32_t version; + uint32_t reserved0; + uint8_t read_sample_clk_src; + uint8_t cs_hold_time; + uint8_t cs_setup_time; + uint8_t column_address_width; + uint8_t device_mode_cfg_enable; + uint8_t device_mode_type; + uint16_t wait_time_cfg_commands; + struct flexspi_lut_seq_s device_mode_seq; + uint32_t device_mode_arg; + uint8_t config_cmd_enable; + uint8_t config_mode_type[3]; + struct flexspi_lut_seq_s config_cmd_seqs[3]; + uint32_t reserved1; + uint32_t config_cmd_args[3]; + uint32_t reserved2; + uint32_t controller_misc_option; + uint8_t device_type; + uint8_t sflash_pad_type; + uint8_t serial_clk_freq; + uint8_t lut_custom_seq_enable; + uint32_t reserved3[2]; + uint32_t sflash_a1_size; + uint32_t sflash_a2_size; + uint32_t sflash_b1_size; + uint32_t sflash_b2_size; + uint32_t cs_pad_setting_override; + uint32_t sclk_pad_setting_override; + uint32_t data_pad_setting_override; + uint32_t dqs_pad_setting_override; + uint32_t timeout_in_ms; + uint32_t command_interval; + uint16_t data_valid_time[2]; + uint16_t busy_offset; + uint16_t busy_bit_polarity; + uint32_t lookup_table[64]; + struct flexspi_lut_seq_s lut_custom_seq[12]; + uint32_t reserved4[4]; +}; + +struct flexspi_nor_config_s +{ + struct flexspi_mem_config_s mem_config; + uint32_t page_size; + uint32_t sector_size; + uint8_t ipcmd_serial_clk_freq; + uint8_t is_uniform_block_size; + uint8_t reserved0[2]; + uint32_t block_size; + uint32_t reserved1[11]; +}; + +#define FCB_TAG 0x42464346u /* 'FCFB' little endian */ +#define FCB_VERSION 0x56010400u /* v1.4.0 */ + +/**************************************************************************** + * Public Data + ****************************************************************************/ + +/* Winbond W25Q128JW: 16 MB, 4 KB sector, 64 KB block, 256 B page. + * QSPI @ 133 MHz, DQS loopback, LUT provides 0xEB Quad I/O Read (24-bit + * address, 6 dummy cycles) — matches the MCUXpresso SDK reference config + * for evkmimxrt1180 (evkmimxrt1180_flexspi_nor_config.c). + */ + +__attribute__((section(".boot_hdr.conf"), used)) +const struct flexspi_nor_config_s g_flash_config = +{ + .mem_config = + { + .tag = FCB_TAG, + .version = FCB_VERSION, + .read_sample_clk_src = 1, /* Loopback from DQS pad */ + .cs_hold_time = 3, + .cs_setup_time = 3, + .controller_misc_option = 0x10, + .device_type = 1, /* Serial NOR */ + .sflash_pad_type = 4, /* 4 pads (QSPI) */ + .serial_clk_freq = 7, /* 133 MHz */ + .sflash_a1_size = 16u * 1024u * 1024u, + .lookup_table = + { + [0] = FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0xeb, + RADDR_SDR, FLEXSPI_4PAD, 0x18), + [1] = FLEXSPI_LUT_SEQ(DUMMY_SDR, FLEXSPI_4PAD, 0x06, + READ_SDR, FLEXSPI_4PAD, 0x04), + [4 * 1] = FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x05, + READ_SDR, FLEXSPI_1PAD, 0x04), + [4 * 3] = FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x06, + STOP, FLEXSPI_1PAD, 0x00), + [4 * 5] = FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x20, + RADDR_SDR, FLEXSPI_1PAD, 0x18), + [4 * 8] = FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0xd8, + RADDR_SDR, FLEXSPI_1PAD, 0x18), + [4 * 9] = FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x02, + RADDR_SDR, FLEXSPI_1PAD, 0x18), + [4 * 9 + 1] = FLEXSPI_LUT_SEQ(WRITE_SDR, FLEXSPI_1PAD, 0x04, + STOP, FLEXSPI_1PAD, 0x00), + [4 * 11] = FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x60, + STOP, FLEXSPI_1PAD, 0x00), + }, + }, + .page_size = 256u, + .sector_size = 4u * 1024u, + .ipcmd_serial_clk_freq = 1, + .is_uniform_block_size = 0, + .block_size = 64u * 1024u, +}; + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/* No functions in this file — boot header data only. The AHAB container + * that references this M33 image is generated separately by + * tools/imxrt1180/build_flash_image.sh using NXP SPSDK "nxpimage". + * The M7 NuttX payload is not part of any AHAB container: it is flashed + * raw at flash offset 0x80000 (XIP address 0x28080000) and started by the + * M33 bootloader with WAIT cleared. + */ diff --git a/boards/arm/imxrt/imxrt1180-evk/tools/flash-jlink.sh b/boards/arm/imxrt/imxrt1180-evk/tools/flash-jlink.sh new file mode 100755 index 0000000000000..0c33b4ed89f30 --- /dev/null +++ b/boards/arm/imxrt/imxrt1180-evk/tools/flash-jlink.sh @@ -0,0 +1,135 @@ +#!/usr/bin/env sh +# SPDX-License-Identifier: Apache-2.0 +# +# Flash a NuttX image to the MIMXRT1180-EVK using SEGGER J-Link. +# +# Usage: +# ./flash-jlink.sh +# +# Arguments: +# image.bin Binary to program. +# flash-offset Offset within FlexSPI1 NOR, either as an absolute +# flash address (0x28080000) or as an offset from the +# flash base (0x80000). Both forms are accepted. +# +# The two images of the MIMXRT1180-EVK build are programmed with two +# separate invocations: +# +# # Cortex-M33 bootloader / application (imxrt1180-evk:bl, :nsh-m33) +# ./flash-jlink.sh flash.bin 0x0 +# +# # Cortex-M7 NuttX payload (imxrt1180-evk:nsh) +# ./flash-jlink.sh nuttx.bin 0x80000 +# +# J-Link only erases the sectors the image actually covers, so flashing +# one image leaves the other intact. +# +# The script assumes: +# * A SEGGER J-Link probe is attached to the EVK JTAG connector (J37) +# or an MCU-Link running SEGGER's "MCU-Link J-Link" firmware is used +# via J53. +# * SW5 = 0100 (FlexSPI Quad SPI NOR boot). +# * The J-Link software (v7.98a or later, which adds MIMXRT1189 +# device support) is installed and JLinkExe is on PATH. +# +# Overrides via environment variables: +# JLINK_EXE - JLinkExe binary (default: JLinkExe) +# JLINK_SPEED - SWD speed in kHz (default: 4000) +# JLINK_IF - Debug interface (default: SWD) + +set -eu + +FLASH_BASE=0x28000000 + +usage() { + sed -n '4,39p' "$0" | sed 's/^# \{0,1\}//' + exit "${1:-1}" +} + +# Programming targets the Cortex-M33 profile. On RT1180 the M33 is the +# boot core; the ROM initializes FlexSPI1 as part of the M33 boot, which +# is what the SEGGER flash loader needs. Connecting via the _M7 profile +# releases the M7 without running the M33/ROM init and leaves FlexSPI in +# a state where the RAM-side loader fails with "RAMCode-sided Prepare()". +# For interactive debugging of the running M7 use MIMXRT1189xxx8_M7 +# (see gdbserver-jlink.sh). + +JLINK_DEVICE=MIMXRT1189xxx8_M33 + +if [ $# -eq 0 ]; then + usage 0 +fi + +if [ $# -ne 2 ]; then + echo "Error: expected 2 arguments, got $#." >&2 + echo >&2 + usage 1 +fi + +FLASH_BIN="$1" +OFFSET_ARG="$2" + +JLINK_EXE="${JLINK_EXE:-JLinkExe}" +JLINK_SPEED="${JLINK_SPEED:-4000}" +JLINK_IF="${JLINK_IF:-SWD}" + +if [ ! -f "$FLASH_BIN" ]; then + echo "Error: $FLASH_BIN not found." >&2 + echo " Run 'make' first to produce it, or pass the path as an" >&2 + echo " argument to this script." >&2 + exit 1 +fi + +if ! command -v "$JLINK_EXE" >/dev/null 2>&1; then + echo "Error: '$JLINK_EXE' not found on PATH." >&2 + echo " Install the SEGGER J-Link Software Pack from" >&2 + echo " https://www.segger.com/downloads/jlink/" >&2 + exit 1 +fi + +# Resolve the offset to an absolute flash address. Values already inside +# the FlexSPI1 XIP window are taken as-is; anything smaller is treated as +# an offset relative to the flash base. + +OFFSET=$(printf "%d" "$OFFSET_ARG" 2>/dev/null) || { + echo "Error: '$OFFSET_ARG' is not a valid numeric offset." >&2 + exit 1 +} + +if [ "$OFFSET" -lt "$(printf "%d" $FLASH_BASE)" ]; then + ADDR=$((OFFSET + FLASH_BASE)) +else + ADDR=$OFFSET +fi + +ADDR_HEX=$(printf "0x%08X" "$ADDR") + +# JLinkExe reads the commander script from -CommanderScript. Generate it +# on the fly so the load address can be parameterized, and stage both in +# a temp working directory that JLinkExe is invoked from. + +WORK_DIR=$(mktemp -d) +trap 'rm -rf "$WORK_DIR"' EXIT + +cp "$FLASH_BIN" "$WORK_DIR/image.bin" + +cat > "$WORK_DIR/flash.jlink" </dev/null 2>&1; then + echo "Error: '$JLINK_GDBSERVER' not found on PATH." >&2 + echo " Install the SEGGER J-Link Software Pack from" >&2 + echo " https://www.segger.com/downloads/jlink/" >&2 + exit 1 +fi + +exec "$JLINK_GDBSERVER" \ + -device "$JLINK_DEVICE" \ + -if "$JLINK_IF" \ + -speed "$JLINK_SPEED" \ + -port "$JLINK_PORT" \ + -singlerun \ + -nogui diff --git a/tools/imxrt1180/.cache/.gitignore b/tools/imxrt1180/.cache/.gitignore new file mode 100644 index 0000000000000..d6b7ef32c8478 --- /dev/null +++ b/tools/imxrt1180/.cache/.gitignore @@ -0,0 +1,2 @@ +* +!.gitignore diff --git a/tools/imxrt1180/Config.mk b/tools/imxrt1180/Config.mk new file mode 100644 index 0000000000000..84155fa3b8605 --- /dev/null +++ b/tools/imxrt1180/Config.mk @@ -0,0 +1,38 @@ +############################################################################ +# tools/imxrt1180/Config.mk +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more +# contributor license agreements. See the NOTICE file distributed with +# this work for additional information regarding copyright ownership. The +# ASF licenses this file to you under the Apache License, Version 2.0 (the +# "License"); you may not use this file except in compliance with the +# License. You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations +# under the License. +# +############################################################################ + +# Resolves the location of the pinned NXP EdgeLock Enclave firmware AHAB +# container and defines a true Make target that downloads it into the +# shared build cache on demand. + +ifeq ($(CONFIG_IMXRT_ELE),y) + +ELE_FW_URL_BASE = https://raw.githubusercontent.com/nxp-mcuxpresso/mcux-sdk/6f3fd257cdcf978a4d26e7d6e9eed9240037422b/firmware/edgelock +ELE_FW_NAME = mxrt1180b0-ahab-container.img +ELE_FW_PATH := $(strip $(subst ",,$(CONFIG_IMXRT_ELE_FW_PATH))) +IMXRT_ELE_FW_ABS := $(if $(filter /%,$(ELE_FW_PATH)),$(ELE_FW_PATH),$(TOPDIR)/$(ELE_FW_PATH)) + +$(IMXRT_ELE_FW_ABS): + $(Q) mkdir -p $(dir $@) + $(call DOWNLOAD,$(ELE_FW_URL_BASE),$(ELE_FW_NAME),$@) + +endif diff --git a/tools/imxrt1180/build_flash_image.sh b/tools/imxrt1180/build_flash_image.sh new file mode 100755 index 0000000000000..5e950853923f6 --- /dev/null +++ b/tools/imxrt1180/build_flash_image.sh @@ -0,0 +1,257 @@ +#!/usr/bin/env bash +# SPDX-License-Identifier: Apache-2.0 +# +# build_flash_image.sh - assemble the MIMXRT1180-EVK bootable FlexSPI NOR +# image (flash.bin) from the freshly built +# Cortex-M33 NuttX image, using NXP SPSDK to +# generate the AHAB container. +# +# Only the Cortex-M33 image is bootable: it carries the FCB and the AHAB +# container that the ROM consumes. +# +# Tools are downloaded / installed on first use into a private cache +# directory. +# +# Usage examples: +# +# tools/imxrt1180/build_flash_image.sh --m33 nuttx.bin --out flash.bin +# tools/imxrt1180/build_flash_image.sh --m33 nuttx.bin --out flash.bin \ +# --ele-fw tools/imxrt1180/.cache/ele-fw/mxrt1180b0-ahab-container.img +# +# NXP EULA note: +# +# * The SPSDK Python package is BSD-3-Clause. +# * The ELE FW AHAB container is proprietary NXP object code covered by +# the LA_OPT NXP Software License (v56 April 2024). +# +# Running the script implies acceptance of the EULA +# (same convention as --auto-accept). +# +# --------------------------------------------------------------------------- + +set -euo pipefail + +# --------------------------------------------------------------------------- +# Configuration +# --------------------------------------------------------------------------- + +# Pinned versions. Bumping these is a code review. +SPSDK_VERSION="3.11.0" + +# Flash layout constants (must match flash-m33.ld). +M33_LOAD_ADDR="0x2800B000" +FLASH_ORIGIN="0x28000000" + +# The M33 image is confined to the first 512 KB of NOR; the Cortex-M7 +# image starts right after it (see boards/.../scripts/flash.ld). +M33_MAX_SIZE=$((512 * 1024)) + +# --------------------------------------------------------------------------- +# Argument parsing +# --------------------------------------------------------------------------- + +M33_BIN="" +OUT_BIN="flash.bin" +ELE_FW_BIN="" + +usage() { + sed -n '2,32p' "$0" + exit 0 +} + +err() { printf "error: %s\n" "$*" >&2; exit 1; } + +while [ $# -gt 0 ]; do + case "$1" in + --m33) M33_BIN="$2"; shift 2 ;; + --out) OUT_BIN="$2"; shift 2 ;; + --ele-fw) ELE_FW_BIN="$2"; shift 2 ;; + -h|--help) usage ;; + *) err "unknown argument: $1" ;; + esac +done + +# Only one mode: --m33 produces FCB @ 0x400 + AHAB @ 0x1000, +# the AHAB container holding the M33 app image and, when --ele-fw is +# given, the NXP ELE firmware as a second image in the same container so +# that the RT118x ROM loads it automatically before the M33 app runs. + +[ -n "${M33_BIN}" ] || err "--m33 is required" +[ -f "${M33_BIN}" ] || err "M33 nuttx binary '${M33_BIN}' not found" +[ -z "${ELE_FW_BIN}" ] || [ -f "${ELE_FW_BIN}" ] || \ + err "ELE firmware container '${ELE_FW_BIN}' not found" + +# --------------------------------------------------------------------------- +# Paths +# --------------------------------------------------------------------------- + +TOP_DIR="$(cd "$(dirname "$0")/../.." && pwd)" +CACHE_DIR="${TOP_DIR}/tools/imxrt1180/.cache" +VENV_DIR="${CACHE_DIR}/spsdk-venv" +WORK_DIR="${CACHE_DIR}/build-$$" +NXPIMAGE="${VENV_DIR}/bin/nxpimage" + +mkdir -p "${CACHE_DIR}" + +cleanup() { rm -rf "${WORK_DIR}"; } +trap cleanup EXIT + +# --------------------------------------------------------------------------- +# 1. Bootstrap SPSDK into a private venv (idempotent) +# --------------------------------------------------------------------------- + +if [ ! -x "${NXPIMAGE}" ] || \ + ! "${NXPIMAGE}" --version 2>/dev/null | grep -q "version ${SPSDK_VERSION}" +then + echo "Installing NXP SPSDK ${SPSDK_VERSION} into ${VENV_DIR}" + rm -rf "${VENV_DIR}" + python3 -m venv "${VENV_DIR}" + "${VENV_DIR}/bin/pip" install --quiet --upgrade pip + "${VENV_DIR}/bin/pip" install --quiet "spsdk==${SPSDK_VERSION}" +fi + +# --------------------------------------------------------------------------- +# 2. (nothing to do here — when requested, the ELE FW container fetched via +# tools/imxrt1180/Config.mk is packed directly into the AHAB image +# below, as a second image entry in the same container) +# --------------------------------------------------------------------------- + +# --------------------------------------------------------------------------- +# 3. Extract the FCB + XIP code from the input image +# +# The M33 linker script places the FCB at VMA 0x28000400 and the XIP code at VMA 0x2800B000. +# arm-none-eabi-objcopy lays these out as a flat binary starting from the +# lowest section VMA, so inside the input binary the FCB sits at file +# offset 0 and the code sits at 0xB000 - 0x400 = 0xAC00. +# --------------------------------------------------------------------------- + +mkdir -p "${WORK_DIR}" + +FCB_BIN="${WORK_DIR}/fcb.bin" +CODE_BIN="${WORK_DIR}/code.bin" + +SRC_BIN="${M33_BIN}" +LOAD_ADDR="${M33_LOAD_ADDR}" + +SRC_SIZE="$(stat -c%s "${SRC_BIN}")" + +# FCB: 512 B at file offset 0 +dd if="${SRC_BIN}" of="${FCB_BIN}" bs=1 count=512 status=none + +# XIP code: everything from file offset 0xAC00 (= 0xB000 - 0x400) onward. +CODE_OFF=$((0xB000 - 0x400)) +CODE_SIZE=$((SRC_SIZE - CODE_OFF)) +[ "${CODE_SIZE}" -gt 0 ] || \ + err "input binary shorter than expected (code offset 0x${CODE_OFF})" +dd if="${SRC_BIN}" of="${CODE_BIN}" bs=1 skip=${CODE_OFF} count=${CODE_SIZE} \ + status=none + +# --------------------------------------------------------------------------- +# 4. Emit the AHAB config YAML +# +# When --ele-fw is given, the output holds *two* AHAB containers back to +# back: container 0 is the raw NXP ELE FW AHAB container (embedded as-is +# via "binary_container" - it is already a complete, signed AHAB +# container in its own right, so it must be its own container, not an +# image inside ours), and container 1 is our own container holding the +# M33 app image. This is the layout the RT118x ROM understands for +# auto-loading ELE FW: it walks the container list, loads/starts the ELE +# container first, then processes ours. +# +# Because the code is linked for FlexSPI XIP at 0x2800B000, the code +# must physically land at flash offset 0xB000 = load_address - +# 0x28000000. nxpimage's "image_offset" is measured from the start of +# the AHAB image (not the container header), so: +# +# flash origin : 0x28000000 +# AHAB blob starts : 0x00001000 (see step 5) +# code flash target : 0xB000 +# image_offset in AHAB : 0xB000 - 0x1000 = 0xA000 +# --------------------------------------------------------------------------- + +AHAB_FLASH_OFFSET=0x1000 +CODE_FLASH_OFFSET=$(( LOAD_ADDR - FLASH_ORIGIN )) +IMAGE_OFFSET=$(( CODE_FLASH_OFFSET - AHAB_FLASH_OFFSET )) + +if [ "${IMAGE_OFFSET}" -le 0 ]; then + err "computed image_offset (${IMAGE_OFFSET}) is not positive - \ +the XIP address must be greater than the AHAB blob's flash offset." +fi + +AHAB_YAML="${WORK_DIR}/ahab.yaml" +AHAB_BIN="${WORK_DIR}/ahab.bin" + +cat > "${AHAB_YAML}" <> "${AHAB_YAML}" <> "${AHAB_YAML}" <