From 45d968f2c1459b3d0e64b56642be3dcd264e7a3f Mon Sep 17 00:00:00 2001 From: Jukka Laitinen Date: Mon, 14 Sep 2026 09:37:10 +0300 Subject: [PATCH 1/8] arch/arm/src/imxrt/imxrt_allocateheap.c: Fix nxstyle issues Add a missing blank line Signed-off-by: Jukka Laitinen --- arch/arm/src/imxrt/imxrt_allocateheap.c | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/src/imxrt/imxrt_allocateheap.c b/arch/arm/src/imxrt/imxrt_allocateheap.c index 4b7caa4049c50..8ad9ed5a4b945 100644 --- a/arch/arm/src/imxrt/imxrt_allocateheap.c +++ b/arch/arm/src/imxrt/imxrt_allocateheap.c @@ -385,6 +385,7 @@ void up_allocate_kheap(void **heap_start, size_t *heap_size) CONFIG_MM_KERNEL_HEAPSIZE; size_t usize = PRIMARY_RAM_END - ubase; int log2; + DEBUGASSERT(ubase < (uintptr_t)PRIMARY_RAM_END); /* Adjust that size to account for MPU alignment requirements. From 3967e562dedb5a8f71c215a9e8589eb03f80cf64 Mon Sep 17 00:00:00 2001 From: Jukka Laitinen Date: Mon, 14 Sep 2026 09:37:45 +0300 Subject: [PATCH 2/8] arch/arm/src/imxrt/imxrt_irq.c: Fix nxstyle issues Fix alignment issues Signed-off-by: Jukka Laitinen --- arch/arm/src/imxrt/imxrt_irq.c | 28 ++++++++++++++-------------- 1 file changed, 14 insertions(+), 14 deletions(-) diff --git a/arch/arm/src/imxrt/imxrt_irq.c b/arch/arm/src/imxrt/imxrt_irq.c index 920bee0225e6f..3a8a87059db3d 100644 --- a/arch/arm/src/imxrt/imxrt_irq.c +++ b/arch/arm/src/imxrt/imxrt_irq.c @@ -294,55 +294,55 @@ static int imxrt_irqinfo(int irq, uintptr_t *regaddr, uint32_t *bit, { if (extint < 32) { - *regaddr = (NVIC_IRQ0_31_ENABLE + offset); - *bit = 1 << extint; + *regaddr = (NVIC_IRQ0_31_ENABLE + offset); + *bit = 1 << extint; } else #if IMXRT_IRQ_NEXTINT > 32 if (extint < 64) { - *regaddr = (NVIC_IRQ32_63_ENABLE + offset); - *bit = 1 << (extint - 32); + *regaddr = (NVIC_IRQ32_63_ENABLE + offset); + *bit = 1 << (extint - 32); } else #endif #if IMXRT_IRQ_NEXTINT > 64 if (extint < 96) { - *regaddr = (NVIC_IRQ64_95_ENABLE + offset); - *bit = 1 << (extint - 64); + *regaddr = (NVIC_IRQ64_95_ENABLE + offset); + *bit = 1 << (extint - 64); } else #endif #if IMXRT_IRQ_NEXTINT > 96 if (extint < 128) { - *regaddr = (NVIC_IRQ96_127_ENABLE + offset); - *bit = 1 << (extint - 96); + *regaddr = (NVIC_IRQ96_127_ENABLE + offset); + *bit = 1 << (extint - 96); } else #endif #if IMXRT_IRQ_NEXTINT > 128 if (extint < 160) { - *regaddr = (NVIC_IRQ128_159_ENABLE + offset); - *bit = 1 << (extint - 128); + *regaddr = (NVIC_IRQ128_159_ENABLE + offset); + *bit = 1 << (extint - 128); } else #endif #if IMXRT_IRQ_NEXTINT > 160 if (extint < 192) { - *regaddr = (NVIC_IRQ160_191_ENABLE + offset); - *bit = 1 << (extint - 160); + *regaddr = (NVIC_IRQ160_191_ENABLE + offset); + *bit = 1 << (extint - 160); } else #endif #if IMXRT_IRQ_NEXTINT > 192 if (extint < 219) { - *regaddr = (NVIC_IRQ192_223_ENABLE + offset); - *bit = 1 << (extint - 192); + *regaddr = (NVIC_IRQ192_223_ENABLE + offset); + *bit = 1 << (extint - 192); } else #endif From e0439f77e7383e7222fae4c1c9c0b428e1cc8a21 Mon Sep 17 00:00:00 2001 From: Jukka Laitinen Date: Mon, 14 Sep 2026 09:38:24 +0300 Subject: [PATCH 3/8] arch/arm/src/imxrt/imxrt_lpi2c.c: Fix nxstyle issues Add blank lines, fix alignment and add braces to switch-case Signed-off-by: Jukka Laitinen --- arch/arm/src/imxrt/imxrt_lpi2c.c | 68 +++++++++++++++++++++----------- 1 file changed, 46 insertions(+), 22 deletions(-) diff --git a/arch/arm/src/imxrt/imxrt_lpi2c.c b/arch/arm/src/imxrt/imxrt_lpi2c.c index fa1ae16e86e7e..561ae36564c34 100644 --- a/arch/arm/src/imxrt/imxrt_lpi2c.c +++ b/arch/arm/src/imxrt/imxrt_lpi2c.c @@ -1653,6 +1653,7 @@ static int imxrt_lpi2c_isr(int irq, void *context, void *arg) DEBUGASSERT(priv != NULL); int rv = imxrt_lpi2c_isr_process(priv); + return rv; } #endif @@ -1862,6 +1863,7 @@ static int imxrt_lpi2c_deinit(struct imxrt_lpi2c_priv_s *priv) static int imxrt_lpi2c_dma_configure_mder(struct imxrt_lpi2c_priv_s *priv) { struct imxrt_edma_xfrconfig_s config; + memset(&config, 0, sizeof(config)); config.saddr = (uint32_t) &g_lpi2c_mder_rdde; @@ -1894,6 +1896,7 @@ static int imxrt_lpi2c_dma_command_configure(struct imxrt_lpi2c_priv_s *priv, uint16_t *ccmd, uint32_t ncmd) { struct imxrt_edma_xfrconfig_s config; + memset(&config, 0, sizeof(config)); config.saddr = (uint32_t) ccmd; @@ -1926,6 +1929,7 @@ static int imxrt_lpi2c_dma_data_configure(struct imxrt_lpi2c_priv_s *priv, struct i2c_msg_s *msg) { struct imxrt_edma_xfrconfig_s config; + memset(&config, 0, sizeof(config)); config.iter = msg->length; @@ -2250,8 +2254,8 @@ static int imxrt_lpi2c_transfer(struct i2c_master_s *dev, { if (msgs[m].flags & I2C_M_READ) { - up_invalidate_dcache((uintptr_t)msgs[m].buffer, - (uintptr_t)msgs[m].buffer + msgs[m].length); + up_invalidate_dcache((uintptr_t)msgs[m].buffer, + (uintptr_t)msgs[m].buffer + msgs[m].length); } } } @@ -2419,37 +2423,57 @@ struct i2c_master_s *imxrt_i2cbus_initialize(int port) switch (port) { #ifdef CONFIG_IMXRT_LPI2C1 - case 1: - priv = (struct imxrt_lpi2c_priv_s *)&imxrt_lpi2c1_priv; - break; + case 1: + { + priv = (struct imxrt_lpi2c_priv_s *)&imxrt_lpi2c1_priv; + break; + } + #endif #ifdef CONFIG_IMXRT_LPI2C2 - case 2: - priv = (struct imxrt_lpi2c_priv_s *)&imxrt_lpi2c2_priv; - break; + case 2: + { + priv = (struct imxrt_lpi2c_priv_s *)&imxrt_lpi2c2_priv; + break; + } + #endif #ifdef CONFIG_IMXRT_LPI2C3 - case 3: - priv = (struct imxrt_lpi2c_priv_s *)&imxrt_lpi2c3_priv; - break; + case 3: + { + priv = (struct imxrt_lpi2c_priv_s *)&imxrt_lpi2c3_priv; + break; + } + #endif #ifdef CONFIG_IMXRT_LPI2C4 - case 4: - priv = (struct imxrt_lpi2c_priv_s *)&imxrt_lpi2c4_priv; - break; + case 4: + { + priv = (struct imxrt_lpi2c_priv_s *)&imxrt_lpi2c4_priv; + break; + } + #endif #ifdef CONFIG_IMXRT_LPI2C5 - case 5: - priv = (struct imxrt_lpi2c_priv_s *)&imxrt_lpi2c5_priv; - break; + case 5: + { + priv = (struct imxrt_lpi2c_priv_s *)&imxrt_lpi2c5_priv; + break; + } + #endif #ifdef CONFIG_IMXRT_LPI2C6 - case 6: - priv = (struct imxrt_lpi2c_priv_s *)&imxrt_lpi2c6_priv; - break; + case 6: + { + priv = (struct imxrt_lpi2c_priv_s *)&imxrt_lpi2c6_priv; + break; + } + #endif - default: - return NULL; + default: + { + return NULL; + } } /* Initialize private data for the first time, increment reference count, From 4a0c4d677b303bed285697466423d5bc5695c0d8 Mon Sep 17 00:00:00 2001 From: Jukka Laitinen Date: Mon, 14 Sep 2026 09:39:11 +0300 Subject: [PATCH 4/8] arch/arm/src/imxrt/imxrt_lpspi.c: Fix nxstyle issues Add braces to switch-case Signed-off-by: Jukka Laitinen --- arch/arm/src/imxrt/imxrt_lpspi.c | 93 +++++++++++++++++++------------- 1 file changed, 55 insertions(+), 38 deletions(-) diff --git a/arch/arm/src/imxrt/imxrt_lpspi.c b/arch/arm/src/imxrt/imxrt_lpspi.c index 9a9404deb5f18..af34bdbde02d4 100644 --- a/arch/arm/src/imxrt/imxrt_lpspi.c +++ b/arch/arm/src/imxrt/imxrt_lpspi.c @@ -681,26 +681,32 @@ static inline void imxrt_lpspi_master_set_delay_scaler( { switch (type) { - case LPSPI_PCS_TO_SCK: - imxrt_lpspi_modifyreg32(priv, IMXRT_LPSPI_CCR_OFFSET, - LPSPI_CCR_PCSSCK_MASK, 0); - imxrt_lpspi_modifyreg32(priv, IMXRT_LPSPI_CCR_OFFSET, 0, - LPSPI_CCR_PCSSCK(scaler)); - break; + case LPSPI_PCS_TO_SCK: + { + imxrt_lpspi_modifyreg32(priv, IMXRT_LPSPI_CCR_OFFSET, + LPSPI_CCR_PCSSCK_MASK, 0); + imxrt_lpspi_modifyreg32(priv, IMXRT_LPSPI_CCR_OFFSET, 0, + LPSPI_CCR_PCSSCK(scaler)); + break; + } - case LPSPI_LAST_SCK_TO_PCS: - imxrt_lpspi_modifyreg32(priv, IMXRT_LPSPI_CCR_OFFSET, - LPSPI_CCR_SCKPCS_MASK, 0); - imxrt_lpspi_modifyreg32(priv, IMXRT_LPSPI_CCR_OFFSET, 0, - LPSPI_CCR_SCKPCS(scaler)); - break; + case LPSPI_LAST_SCK_TO_PCS: + { + imxrt_lpspi_modifyreg32(priv, IMXRT_LPSPI_CCR_OFFSET, + LPSPI_CCR_SCKPCS_MASK, 0); + imxrt_lpspi_modifyreg32(priv, IMXRT_LPSPI_CCR_OFFSET, 0, + LPSPI_CCR_SCKPCS(scaler)); + break; + } - case LPSPI_BETWEEN_TRANSFER: - imxrt_lpspi_modifyreg32(priv, IMXRT_LPSPI_CCR_OFFSET, - LPSPI_CCR_DBT_MASK, 0); - imxrt_lpspi_modifyreg32(priv, IMXRT_LPSPI_CCR_OFFSET, 0, - LPSPI_CCR_DBT(scaler)); - break; + case LPSPI_BETWEEN_TRANSFER: + { + imxrt_lpspi_modifyreg32(priv, IMXRT_LPSPI_CCR_OFFSET, + LPSPI_CCR_DBT_MASK, 0); + imxrt_lpspi_modifyreg32(priv, IMXRT_LPSPI_CCR_OFFSET, 0, + LPSPI_CCR_DBT(scaler)); + break; + } } } @@ -1123,28 +1129,38 @@ static void imxrt_lpspi_setmode(struct spi_dev_s *dev, switch (mode) { - case SPIDEV_MODE0: /* CPOL=0; CPHA=0 */ - setbits = 0; - clrbits = LPSPI_TCR_CPOL | LPSPI_TCR_CPHA; - break; + case SPIDEV_MODE0: /* CPOL=0; CPHA=0 */ + { + setbits = 0; + clrbits = LPSPI_TCR_CPOL | LPSPI_TCR_CPHA; + break; + } - case SPIDEV_MODE1: /* CPOL=0; CPHA=1 */ - setbits = LPSPI_TCR_CPHA; - clrbits = LPSPI_TCR_CPOL; - break; + case SPIDEV_MODE1: /* CPOL=0; CPHA=1 */ + { + setbits = LPSPI_TCR_CPHA; + clrbits = LPSPI_TCR_CPOL; + break; + } - case SPIDEV_MODE2: /* CPOL=1; CPHA=0 */ - setbits = LPSPI_TCR_CPOL; - clrbits = LPSPI_TCR_CPHA; - break; + case SPIDEV_MODE2: /* CPOL=1; CPHA=0 */ + { + setbits = LPSPI_TCR_CPOL; + clrbits = LPSPI_TCR_CPHA; + break; + } - case SPIDEV_MODE3: /* CPOL=1; CPHA=1 */ - setbits = LPSPI_TCR_CPOL | LPSPI_TCR_CPHA; - clrbits = 0; - break; + case SPIDEV_MODE3: /* CPOL=1; CPHA=1 */ + { + setbits = LPSPI_TCR_CPOL | LPSPI_TCR_CPHA; + clrbits = 0; + break; + } - default: - return; + default: + { + return; + } } imxrt_lpspi_modifyreg32(priv, IMXRT_LPSPI_TCR_OFFSET, @@ -1361,6 +1377,7 @@ static void imxrt_lpspi_exchange_nodma(struct spi_dev_s *dev, #endif { struct imxrt_lpspidev_s *priv = (struct imxrt_lpspidev_s *)dev; + DEBUGASSERT(priv && priv->spibase); spiinfo("txbuffer=%p rxbuffer=%p nwords=%d\n", txbuffer, rxbuffer, nwords); @@ -1581,8 +1598,8 @@ static void imxrt_lpspi_exchange(struct spi_dev_s *dev, if (rxbuffer) { - up_invalidate_dcache((uintptr_t)rxbuffer, - (uintptr_t)rxbuffer + nbytes); + up_invalidate_dcache((uintptr_t)rxbuffer, + (uintptr_t)rxbuffer + nbytes); } } From 94133af7d36291777ffdba7bf5ca87da240a5bad Mon Sep 17 00:00:00 2001 From: Jukka Laitinen Date: Mon, 14 Sep 2026 09:39:48 +0300 Subject: [PATCH 5/8] arch/arm/src/imxrt/imxrt_ocotp.c: Fix nxstyle issues Add a missing blank line Signed-off-by: Jukka Laitinen --- arch/arm/src/imxrt/imxrt_ocotp.c | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/src/imxrt/imxrt_ocotp.c b/arch/arm/src/imxrt/imxrt_ocotp.c index c30a26ed9b36d..cbb45ef7bd9ea 100644 --- a/arch/arm/src/imxrt/imxrt_ocotp.c +++ b/arch/arm/src/imxrt/imxrt_ocotp.c @@ -284,6 +284,7 @@ int imxrt_ocotp_read(uint32_t otp_index, uint32_t *data) int imxrt_ocotp_write(uint32_t otp_index, uint32_t data) { int ret; + ret = imxrt_ocotp_wait_for_completion(OCOTP_OPT_TIMEOUT_MS); if (ret == OK) { From 9b871745eb301e4ebd8d924f247cf27b35c88606 Mon Sep 17 00:00:00 2001 From: Jukka Laitinen Date: Mon, 14 Sep 2026 09:40:15 +0300 Subject: [PATCH 6/8] arch/arm/src/imxrt/imxrt_serial.c: Fix nxstyle issues Fix alignment in multiple places Signed-off-by: Jukka Laitinen --- arch/arm/src/imxrt/imxrt_serial.c | 476 +++++++++++++++--------------- 1 file changed, 241 insertions(+), 235 deletions(-) diff --git a/arch/arm/src/imxrt/imxrt_serial.c b/arch/arm/src/imxrt/imxrt_serial.c index d76e0262dc70a..37b4543086c59 100644 --- a/arch/arm/src/imxrt/imxrt_serial.c +++ b/arch/arm/src/imxrt/imxrt_serial.c @@ -2311,6 +2311,7 @@ static inline void imxrt_serialout(struct imxrt_uart_s *priv, static int imxrt_dma_nextrx(struct imxrt_uart_s *priv) { int dmaresidual = imxrt_dmach_getcount(priv->rxdma); + DEBUGASSERT(dmaresidual <= RXDMA_BUFFER_SIZE); return (RXDMA_BUFFER_SIZE - dmaresidual) % RXDMA_BUFFER_SIZE; @@ -2818,300 +2819,304 @@ static int imxrt_ioctl(struct file *filep, int cmd, unsigned long arg) switch (cmd) { #ifdef CONFIG_SERIAL_TIOCSERGSTRUCT - case TIOCSERGSTRUCT: - { - struct imxrt_uart_s *user = (struct imxrt_uart_s *)arg; - if (!user) - { - ret = -EINVAL; - } - else - { - memcpy(user, dev, sizeof(struct imxrt_uart_s)); - } - } - break; + case TIOCSERGSTRUCT: + { + struct imxrt_uart_s *user = (struct imxrt_uart_s *)arg; + + if (!user) + { + ret = -EINVAL; + } + else + { + memcpy(user, dev, sizeof(struct imxrt_uart_s)); + } + } + break; #endif #ifdef CONFIG_SERIAL_TERMIOS - case TCGETS: - { - struct termios *termiosp = (struct termios *)arg; - struct imxrt_uart_s *priv = (struct imxrt_uart_s *)dev; + case TCGETS: + { + struct termios *termiosp = (struct termios *)arg; + struct imxrt_uart_s *priv = (struct imxrt_uart_s *)dev; - if (!termiosp) - { - ret = -EINVAL; - break; - } + if (!termiosp) + { + ret = -EINVAL; + break; + } - /* Return parity */ + /* Return parity */ - termiosp->c_cflag = ((priv->parity != 0) ? PARENB : 0) | - ((priv->parity == 1) ? PARODD : 0); + termiosp->c_cflag = ((priv->parity != 0) ? PARENB : 0) | + ((priv->parity == 1) ? PARODD : 0); - /* Return stop bits */ + /* Return stop bits */ - termiosp->c_cflag |= (priv->stopbits2) ? CSTOPB : 0; + termiosp->c_cflag |= (priv->stopbits2) ? CSTOPB : 0; - /* Return flow control */ + /* Return flow control */ #ifdef CONFIG_SERIAL_OFLOWCONTROL - termiosp->c_cflag |= ((priv->oflow) ? CCTS_OFLOW : 0); + termiosp->c_cflag |= ((priv->oflow) ? CCTS_OFLOW : 0); #endif #ifdef CONFIG_SERIAL_IFLOWCONTROL - termiosp->c_cflag |= ((priv->iflow) ? CRTS_IFLOW : 0); + termiosp->c_cflag |= ((priv->iflow) ? CRTS_IFLOW : 0); #endif - /* Return baud */ + /* Return baud */ - cfsetispeed(termiosp, priv->baud); + cfsetispeed(termiosp, priv->baud); - /* Return number of bits */ + /* Return number of bits */ - switch (priv->bits) - { - case 5: - termiosp->c_cflag |= CS5; - break; + switch (priv->bits) + { + case 5: + termiosp->c_cflag |= CS5; + break; - case 6: - termiosp->c_cflag |= CS6; - break; + case 6: + termiosp->c_cflag |= CS6; + break; - case 7: - termiosp->c_cflag |= CS7; - break; + case 7: + termiosp->c_cflag |= CS7; + break; - default: - case 8: - termiosp->c_cflag |= CS8; - break; + default: + case 8: + termiosp->c_cflag |= CS8; + break; #if defined(CS9) - case 9: - termiosp->c_cflag |= CS9; - break; + case 9: + termiosp->c_cflag |= CS9; + break; #endif - } - } - break; + } + } + break; - case TCSETS: - { - struct termios *termiosp = (struct termios *)arg; - struct imxrt_uart_s *priv = (struct imxrt_uart_s *)dev; - uint32_t baud; - uint32_t ie; - uint8_t parity; - uint8_t nbits; - bool stop2; - - if ((!termiosp) + case TCSETS: + { + struct termios *termiosp = (struct termios *)arg; + struct imxrt_uart_s *priv = (struct imxrt_uart_s *)dev; + uint32_t baud; + uint32_t ie; + uint8_t parity; + uint8_t nbits; + bool stop2; + + if ((!termiosp) #ifdef CONFIG_SERIAL_OFLOWCONTROL - || ((termiosp->c_cflag & CCTS_OFLOW) && (priv->cts_gpio == 0)) + || ((termiosp->c_cflag & CCTS_OFLOW) && (priv->cts_gpio == 0)) #endif #ifdef CONFIG_SERIAL_IFLOWCONTROL - || ((termiosp->c_cflag & CRTS_IFLOW) && (priv->rts_gpio == 0)) + || ((termiosp->c_cflag & CRTS_IFLOW) && (priv->rts_gpio == 0)) #endif - ) - { - ret = -EINVAL; - break; - } + ) + { + ret = -EINVAL; + break; + } - /* Decode baud. */ + /* Decode baud. */ - ret = OK; - baud = cfgetispeed(termiosp); + ret = OK; + baud = cfgetispeed(termiosp); - /* Decode number of bits */ + /* Decode number of bits */ - switch (termiosp->c_cflag & CSIZE) - { - case CS5: - nbits = 5; - break; + switch (termiosp->c_cflag & CSIZE) + { + case CS5: + nbits = 5; + break; - case CS6: - nbits = 6; - break; + case CS6: + nbits = 6; + break; - case CS7: - nbits = 7; - break; + case CS7: + nbits = 7; + break; - case CS8: - nbits = 8; - break; + case CS8: + nbits = 8; + break; #if defined(CS9) - case CS9: - nbits = 9; - break; + case CS9: + nbits = 9; + break; #endif - default: - ret = -EINVAL; - break; - } + default: + ret = -EINVAL; + break; + } - /* Decode parity */ + /* Decode parity */ - if ((termiosp->c_cflag & PARENB) != 0) - { - parity = (termiosp->c_cflag & PARODD) ? 1 : 2; - } - else - { - parity = 0; - } + if ((termiosp->c_cflag & PARENB) != 0) + { + parity = (termiosp->c_cflag & PARODD) ? 1 : 2; + } + else + { + parity = 0; + } - /* Decode stop bits */ + /* Decode stop bits */ - stop2 = (termiosp->c_cflag & CSTOPB) != 0; + stop2 = (termiosp->c_cflag & CSTOPB) != 0; - /* Verify that all settings are valid before committing */ + /* Verify that all settings are valid before committing */ - if (ret == OK) - { - /* Commit */ + if (ret == OK) + { + /* Commit */ - priv->baud = baud; - priv->parity = parity; - priv->bits = nbits; - priv->stopbits2 = stop2; + priv->baud = baud; + priv->parity = parity; + priv->bits = nbits; + priv->stopbits2 = stop2; #ifdef CONFIG_SERIAL_OFLOWCONTROL - priv->oflow = (termiosp->c_cflag & CCTS_OFLOW) != 0; + priv->oflow = (termiosp->c_cflag & CCTS_OFLOW) != 0; #endif #ifdef CONFIG_SERIAL_IFLOWCONTROL - priv->iflow = (termiosp->c_cflag & CRTS_IFLOW) != 0; + priv->iflow = (termiosp->c_cflag & CRTS_IFLOW) != 0; #endif - /* effect the changes immediately - note that we do not - * implement TCSADRAIN / TCSAFLUSH - */ + /* effect the changes immediately - note that we do not + * implement TCSADRAIN / TCSAFLUSH + */ - flags = spin_lock_irqsave(&priv->lock); - imxrt_disableuartint(priv, &ie); - ret = dev->ops->setup(dev); + flags = spin_lock_irqsave(&priv->lock); + imxrt_disableuartint(priv, &ie); + ret = dev->ops->setup(dev); - /* Restore the interrupt state */ + /* Restore the interrupt state */ - imxrt_restoreuartint(priv, ie); - priv->ie = ie; - spin_unlock_irqrestore(&priv->lock, flags); - } - } - break; + imxrt_restoreuartint(priv, ie); + priv->ie = ie; + spin_unlock_irqrestore(&priv->lock, flags); + } + } + break; #endif /* CONFIG_SERIAL_TERMIOS */ #ifdef CONFIG_IMXRT_LPUART_SINGLEWIRE - case TIOCSSINGLEWIRE: - { - uint32_t regval; - struct imxrt_uart_s *priv = (struct imxrt_uart_s *)dev; - - flags = spin_lock_irqsave(&priv->lock); - regval = imxrt_serialin(priv, IMXRT_LPUART_CTRL_OFFSET); - - if ((arg & SER_SINGLEWIRE_ENABLED) != 0) - { - uint32_t gpio_val = (arg & SER_SINGLEWIRE_PUSHPULL) == - SER_SINGLEWIRE_PUSHPULL ? - IOMUX_CMOS_OUTPUT : IOMUX_OPENDRAIN; - gpio_val |= (arg & SER_SINGLEWIRE_PULL_MASK) == - SER_SINGLEWIRE_PULLUP ? - IOMUX_PULL_UP : IOMUX_PULL_NONE; - gpio_val |= (arg & SER_SINGLEWIRE_PULL_MASK) == - SER_SINGLEWIRE_PULLDOWN ? - IOMUX_PULL_DOWN : IOMUX_PULL_NONE; - imxrt_config_gpio((priv->tx_gpio & - ~(IOMUX_PULL_MASK | IOMUX_OPENDRAIN)) | gpio_val); - regval |= LPUART_CTRL_LOOPS | LPUART_CTRL_RSRC; - priv->prev_ops = priv->dev.ops; + case TIOCSSINGLEWIRE: + { + uint32_t regval; + struct imxrt_uart_s *priv = (struct imxrt_uart_s *)dev; + + flags = spin_lock_irqsave(&priv->lock); + regval = imxrt_serialin(priv, IMXRT_LPUART_CTRL_OFFSET); + + if ((arg & SER_SINGLEWIRE_ENABLED) != 0) + { + uint32_t gpio_val; + + gpio_val = (arg & SER_SINGLEWIRE_PUSHPULL) == + SER_SINGLEWIRE_PUSHPULL ? + IOMUX_CMOS_OUTPUT : IOMUX_OPENDRAIN; + gpio_val |= (arg & SER_SINGLEWIRE_PULL_MASK) == + SER_SINGLEWIRE_PULLUP ? + IOMUX_PULL_UP : IOMUX_PULL_NONE; + gpio_val |= (arg & SER_SINGLEWIRE_PULL_MASK) == + SER_SINGLEWIRE_PULLDOWN ? + IOMUX_PULL_DOWN : IOMUX_PULL_NONE; + imxrt_config_gpio((priv->tx_gpio & + ~(IOMUX_PULL_MASK | IOMUX_OPENDRAIN)) | + gpio_val); + regval |= LPUART_CTRL_LOOPS | LPUART_CTRL_RSRC; + priv->prev_ops = priv->dev.ops; #ifdef SERIAL_HAVE_RXDMA - if (priv->dev.ops->receive == imxrt_dma_receive) - { - priv->dev.ops = &g_lpuart_singlewire_rxdma_ops; - } - else -#endif - { - priv->dev.ops = &g_lpuart_singlewire_ops; - } - } - else - { - imxrt_config_gpio((priv->tx_gpio & ~(IOMUX_PULL_MASK | - IOMUX_OPENDRAIN)) | - IOMUX_PULL_NONE); - regval &= ~(LPUART_CTRL_LOOPS | LPUART_CTRL_RSRC); - if (priv->prev_ops) - { - priv->dev.ops = priv->prev_ops; - priv->prev_ops = 0; - } - } - - imxrt_serialout(priv, IMXRT_LPUART_CTRL_OFFSET, regval); - - spin_unlock_irqrestore(&priv->lock, flags); - } - break; + if (priv->dev.ops->receive == imxrt_dma_receive) + { + priv->dev.ops = &g_lpuart_singlewire_rxdma_ops; + } + else +#endif + { + priv->dev.ops = &g_lpuart_singlewire_ops; + } + } + else + { + imxrt_config_gpio((priv->tx_gpio & + ~(IOMUX_PULL_MASK | IOMUX_OPENDRAIN)) | + IOMUX_PULL_NONE); + regval &= ~(LPUART_CTRL_LOOPS | LPUART_CTRL_RSRC); + if (priv->prev_ops) + { + priv->dev.ops = priv->prev_ops; + priv->prev_ops = 0; + } + } + + imxrt_serialout(priv, IMXRT_LPUART_CTRL_OFFSET, regval); + + spin_unlock_irqrestore(&priv->lock, flags); + } + break; #endif #ifdef CONFIG_IMXRT_LPUART_INVERT - case TIOCSINVERT: - { - uint32_t ctrl; - uint32_t stat; - uint32_t regval; - struct imxrt_uart_s *priv = (struct imxrt_uart_s *)dev; - - flags = spin_lock_irqsave(&priv->lock); - ctrl = imxrt_serialin(priv, IMXRT_LPUART_CTRL_OFFSET); - stat = imxrt_serialin(priv, IMXRT_LPUART_STAT_OFFSET); - regval = ctrl; - - /* {R|T}XINV bit field can only be written when the receiver - * is disabled (RE=0). - */ - - regval &= ~LPUART_CTRL_RE; - - imxrt_serialout(priv, IMXRT_LPUART_CTRL_OFFSET, regval); - - /* Enable/disable signal inversion. */ - - if (arg & SER_INVERT_ENABLED_RX) - { - stat |= LPUART_STAT_RXINV; - } - else - { - stat &= ~LPUART_STAT_RXINV; - } - - if (arg & SER_INVERT_ENABLED_TX) - { - ctrl |= LPUART_CTRL_TXINV; - } - else - { - ctrl &= ~LPUART_CTRL_TXINV; - } - - imxrt_serialout(priv, IMXRT_LPUART_STAT_OFFSET, stat); - imxrt_serialout(priv, IMXRT_LPUART_CTRL_OFFSET, ctrl); - - spin_unlock_irqrestore(&priv->lock, flags); - } - break; -#endif - - case TIOCSBRK: /* BSD compatibility: Turn break on, unconditionally */ - case TIOCCBRK: /* BSD compatibility: Turn break off, unconditionally */ - default: - ret = -ENOTTY; - break; + case TIOCSINVERT: + { + uint32_t ctrl; + uint32_t stat; + uint32_t regval; + struct imxrt_uart_s *priv = (struct imxrt_uart_s *)dev; + + flags = spin_lock_irqsave(&priv->lock); + ctrl = imxrt_serialin(priv, IMXRT_LPUART_CTRL_OFFSET); + stat = imxrt_serialin(priv, IMXRT_LPUART_STAT_OFFSET); + regval = ctrl; + + /* {R|T}XINV bit field can only be written when the receiver + * is disabled (RE=0). + */ + + regval &= ~LPUART_CTRL_RE; + + imxrt_serialout(priv, IMXRT_LPUART_CTRL_OFFSET, regval); + + /* Enable/disable signal inversion. */ + + if (arg & SER_INVERT_ENABLED_RX) + { + stat |= LPUART_STAT_RXINV; + } + else + { + stat &= ~LPUART_STAT_RXINV; + } + + if (arg & SER_INVERT_ENABLED_TX) + { + ctrl |= LPUART_CTRL_TXINV; + } + else + { + ctrl &= ~LPUART_CTRL_TXINV; + } + + imxrt_serialout(priv, IMXRT_LPUART_STAT_OFFSET, stat); + imxrt_serialout(priv, IMXRT_LPUART_CTRL_OFFSET, ctrl); + + spin_unlock_irqrestore(&priv->lock, flags); + } + break; +#endif + + case TIOCSBRK: /* BSD compatibility: Turn break on, unconditionally */ + case TIOCCBRK: /* BSD compatibility: Turn break off, unconditionally */ + default: + ret = -ENOTTY; + break; } return ret; @@ -3647,6 +3652,7 @@ static void imxrt_singlewire_send(struct uart_dev_s *dev, int ch) static void imxrt_send(struct uart_dev_s *dev, int ch) { struct imxrt_uart_s *priv = (struct imxrt_uart_s *)dev; + imxrt_serialout(priv, IMXRT_LPUART_DATA_OFFSET, (uint32_t)ch); } From 500536e5202bf5203594de212bc87f14fad2b04c Mon Sep 17 00:00:00 2001 From: Jukka Laitinen Date: Mon, 14 Sep 2026 09:41:01 +0300 Subject: [PATCH 7/8] arch/arm/src/imxrt/imxrt_start.c: Fix nxstyle issues Fix alignment, add blank lines and add braces where missing. Signed-off-by: Jukka Laitinen --- arch/arm/src/imxrt/imxrt_start.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/src/imxrt/imxrt_start.c b/arch/arm/src/imxrt/imxrt_start.c index c4500868b88bc..4d78cdfad1480 100644 --- a/arch/arm/src/imxrt/imxrt_start.c +++ b/arch/arm/src/imxrt/imxrt_start.c @@ -176,7 +176,7 @@ void __start(void) #endif #if defined(CONFIG_BOOT_RUNFROMISRAM) || defined(CONFIG_IMXRT_INIT_FLEXRAM) - imxrt_ocram_initialize(); + imxrt_ocram_initialize(); #endif /* Clear .bss. We'll do this inline (vs. calling memset) just to be From e2e32ad07c0ac9ccbf038112a93f57e5bb013609 Mon Sep 17 00:00:00 2001 From: Jukka Laitinen Date: Mon, 14 Sep 2026 09:41:51 +0300 Subject: [PATCH 8/8] arch/arm/src/imxrt/imxrt_usbdev.c: Fix nxstyle issues Add blank lines, fix alignment and add braces to switch-case Signed-off-by: Jukka Laitinen --- arch/arm/src/imxrt/imxrt_usbdev.c | 763 ++++++++++++++++-------------- 1 file changed, 413 insertions(+), 350 deletions(-) diff --git a/arch/arm/src/imxrt/imxrt_usbdev.c b/arch/arm/src/imxrt/imxrt_usbdev.c index e8eb9faf98431..5e380616dccb9 100644 --- a/arch/arm/src/imxrt/imxrt_usbdev.c +++ b/arch/arm/src/imxrt/imxrt_usbdev.c @@ -647,6 +647,7 @@ static void imxrt_putreg(uint32_t val, uint32_t addr) static inline void imxrt_clrbits(uint32_t mask, uint32_t addr) { uint32_t reg = imxrt_getreg(addr); + reg &= ~mask; imxrt_putreg(reg, addr); } @@ -662,6 +663,7 @@ static inline void imxrt_clrbits(uint32_t mask, uint32_t addr) static inline void imxrt_setbits(uint32_t mask, uint32_t addr) { uint32_t reg = imxrt_getreg(addr); + reg |= mask; imxrt_putreg(reg, addr); } @@ -677,6 +679,7 @@ static inline void imxrt_setbits(uint32_t mask, uint32_t addr) static inline void imxrt_chgbits(uint32_t mask, uint32_t val, uint32_t addr) { uint32_t reg = imxrt_getreg(addr); + reg &= ~mask; reg |= val; imxrt_putreg(reg, addr); @@ -794,7 +797,8 @@ static void imxrt_queuedtd(uint8_t epphy, struct imxrt_dtd_s *dtd) imxrt_setbits(bit, IMXRT_USBDEV_ENDPTPRIME(0)); while (imxrt_getreg(IMXRT_USBDEV_ENDPTPRIME(0)) & bit) - ; + { + } } /**************************************************************************** @@ -886,11 +890,13 @@ static inline void imxrt_set_address(struct imxrt_usbdev_s *priv, static void imxrt_flushep(struct imxrt_ep_s *privep) { uint32_t mask = IMXRT_ENDPTMASK(privep->epphy); + do { imxrt_putreg(mask, IMXRT_USBDEV_ENDPTFLUSH(0)); while ((imxrt_getreg(IMXRT_USBDEV_ENDPTFLUSH(0)) & mask) != 0) - ; + { + } } while ((imxrt_getreg(IMXRT_USBDEV_ENDPTSTATUS(0)) & mask) != 0); } @@ -994,8 +1000,11 @@ static void imxrt_reqcomplete(struct imxrt_ep_s *privep, */ bool stalled = privep->stalled; + if (privep->epphy == IMXRT_EP0_IN) - privep->stalled = privep->dev->stalled; + { + privep->stalled = privep->dev->stalled; + } /* Save the result in the request structure */ @@ -1021,7 +1030,9 @@ static void imxrt_reqcomplete(struct imxrt_ep_s *privep, static void imxrt_cancelrequests(struct imxrt_ep_s *privep, int16_t status) { if (!imxrt_rqempty(privep)) + { imxrt_flushep(privep); + } while (!imxrt_rqempty(privep)) { @@ -1181,10 +1192,13 @@ static void imxrt_usbreset(struct imxrt_usbdev_s *priv) */ while (imxrt_getreg(IMXRT_USBDEV_ENDPTPRIME(0)) != 0) - ; + { + } + imxrt_putreg(IMXRT_ENDPTMASK_ALL, IMXRT_USBDEV_ENDPTFLUSH(0)); while (imxrt_getreg(IMXRT_USBDEV_ENDPTFLUSH(0))) - ; + { + } /* Reset endpoints */ @@ -1255,19 +1269,25 @@ static inline void imxrt_ep0state(struct imxrt_usbdev_s *priv, switch (state) { - case EP0STATE_WAIT_NAK_IN: - imxrt_putreg(IMXRT_ENDPTMASK(IMXRT_EP0_IN), - IMXRT_USBDEV_ENDPTNAKEN(0)); - break; + case EP0STATE_WAIT_NAK_IN: + { + imxrt_putreg(IMXRT_ENDPTMASK(IMXRT_EP0_IN), + IMXRT_USBDEV_ENDPTNAKEN(0)); + break; + } - case EP0STATE_WAIT_NAK_OUT: - imxrt_putreg(IMXRT_ENDPTMASK(IMXRT_EP0_OUT), - IMXRT_USBDEV_ENDPTNAKEN(0)); - break; + case EP0STATE_WAIT_NAK_OUT: + { + imxrt_putreg(IMXRT_ENDPTMASK(IMXRT_EP0_OUT), + IMXRT_USBDEV_ENDPTNAKEN(0)); + break; + } - default: - imxrt_putreg(0, IMXRT_USBDEV_ENDPTNAKEN(0)); - break; + default: + { + imxrt_putreg(0, IMXRT_USBDEV_ENDPTNAKEN(0)); + break; + } } } @@ -1350,316 +1370,330 @@ static inline void imxrt_ep0setup(struct imxrt_usbdev_s *priv) switch (ctrl->req) { - case USB_REQ_GETSTATUS: - { - /* type: device-to-host; recipient = device, interface, endpoint - * value: 0 - * index: zero interface endpoint - * len: 2; data = status - */ + case USB_REQ_GETSTATUS: + { + /* type: device-to-host; recipient = device, interface, + * endpoint + * value: 0 + * index: zero interface endpoint + * len: 2; data = status + */ - usbtrace(TRACE_INTDECODE(IMXRT_TRACEINTID_GETSTATUS), 0); - if (!priv->paddrset || len != 2 || - (ctrl->type & USB_REQ_DIR_IN) == 0 || value != 0) - { - priv->stalled = true; - } - else - { - switch (ctrl->type & USB_REQ_RECIPIENT_MASK) - { - case USB_REQ_RECIPIENT_ENDPOINT: + usbtrace(TRACE_INTDECODE(IMXRT_TRACEINTID_GETSTATUS), 0); + if (!priv->paddrset || len != 2 || + (ctrl->type & USB_REQ_DIR_IN) == 0 || value != 0) + { + priv->stalled = true; + } + else + { + switch (ctrl->type & USB_REQ_RECIPIENT_MASK) { - usbtrace( - TRACE_INTDECODE(IMXRT_TRACEINTID_EPGETSTATUS), 0); - privep = imxrt_epfindbyaddr(priv, index); - if (!privep) + case USB_REQ_RECIPIENT_ENDPOINT: { usbtrace( - TRACE_DEVERROR(IMXRT_TRACEERR_BADEPGETSTATUS), + TRACE_INTDECODE(IMXRT_TRACEINTID_EPGETSTATUS), 0); - priv->stalled = true; + privep = imxrt_epfindbyaddr(priv, index); + if (!privep) + { + usbtrace( + TRACE_DEVERROR( + IMXRT_TRACEERR_BADEPGETSTATUS), + 0); + priv->stalled = true; + } + else + { + if (privep->stalled) + { + priv->ep0buf[0] = 1; /* Stalled */ + } + else + { + priv->ep0buf[0] = 0; /* Not stalled */ + } + + priv->ep0buf[1] = 0; + + imxrt_ep0xfer(IMXRT_EP0_IN, priv->ep0buf, 2); + imxrt_ep0state(priv, EP0STATE_SHORTWRITE); + } } - else + break; + + case USB_REQ_RECIPIENT_DEVICE: { - if (privep->stalled) + if (index == 0) { - priv->ep0buf[0] = 1; /* Stalled */ + usbtrace( + TRACE_INTDECODE( + IMXRT_TRACEINTID_DEVGETSTATUS), 0); + + /* Features: Remote Wakeup=YES; + * selfpowered=? + */ + + priv->ep0buf[0] = + (priv->selfpowered << + USB_FEATURE_SELFPOWERED) | + (1 << USB_FEATURE_REMOTEWAKEUP); + priv->ep0buf[1] = 0; + + imxrt_ep0xfer(IMXRT_EP0_IN, priv->ep0buf, 2); + imxrt_ep0state(priv, EP0STATE_SHORTWRITE); } else { - priv->ep0buf[0] = 0; /* Not stalled */ + usbtrace( + TRACE_DEVERROR( + IMXRT_TRACEERR_BADDEVGETSTATUS), 0); + priv->stalled = true; } - - priv->ep0buf[1] = 0; - - imxrt_ep0xfer(IMXRT_EP0_IN, priv->ep0buf, 2); - imxrt_ep0state(priv, EP0STATE_SHORTWRITE); } - } - break; + break; - case USB_REQ_RECIPIENT_DEVICE: - { - if (index == 0) + case USB_REQ_RECIPIENT_INTERFACE: { usbtrace( - TRACE_INTDECODE(IMXRT_TRACEINTID_DEVGETSTATUS), + TRACE_INTDECODE(IMXRT_TRACEINTID_IFGETSTATUS), 0); - - /* Features: Remote Wakeup=YES; selfpowered=? */ - - priv->ep0buf[0] = - (priv->selfpowered << - USB_FEATURE_SELFPOWERED) | - (1 << USB_FEATURE_REMOTEWAKEUP); + priv->ep0buf[0] = 0; priv->ep0buf[1] = 0; imxrt_ep0xfer(IMXRT_EP0_IN, priv->ep0buf, 2); imxrt_ep0state(priv, EP0STATE_SHORTWRITE); } - else + break; + + default: { usbtrace( - TRACE_DEVERROR(IMXRT_TRACEERR_BADDEVGETSTATUS), + TRACE_DEVERROR(IMXRT_TRACEERR_BADGETSTATUS), 0); priv->stalled = true; } + break; } - break; - - case USB_REQ_RECIPIENT_INTERFACE: - { - usbtrace(TRACE_INTDECODE(IMXRT_TRACEINTID_IFGETSTATUS), - 0); - priv->ep0buf[0] = 0; - priv->ep0buf[1] = 0; - - imxrt_ep0xfer(IMXRT_EP0_IN, priv->ep0buf, 2); - imxrt_ep0state(priv, EP0STATE_SHORTWRITE); - } - break; - - default: - { - usbtrace(TRACE_DEVERROR(IMXRT_TRACEERR_BADGETSTATUS), - 0); - priv->stalled = true; - } - break; } } - } - break; - - case USB_REQ_CLEARFEATURE: - { - /* type: host-to-device; recipient = device, interface or endpoint - * value: feature selector - * index: zero interface endpoint; - * len: zero, data = none - */ + break; - usbtrace(TRACE_INTDECODE(IMXRT_TRACEINTID_CLEARFEATURE), 0); - if ((ctrl->type & USB_REQ_RECIPIENT_MASK) != - USB_REQ_RECIPIENT_ENDPOINT) + case USB_REQ_CLEARFEATURE: { - imxrt_dispatchrequest(priv, ctrl); + /* type: host-to-device; recipient = device, interface or + * endpoint + * value: feature selector + * index: zero interface endpoint; + * len: zero, data = none + */ + + usbtrace(TRACE_INTDECODE(IMXRT_TRACEINTID_CLEARFEATURE), 0); + if ((ctrl->type & USB_REQ_RECIPIENT_MASK) != + USB_REQ_RECIPIENT_ENDPOINT) + { + imxrt_dispatchrequest(priv, ctrl); + } + else if (priv->paddrset != 0 && + value == USB_FEATURE_ENDPOINTHALT && + len == 0 && + (privep = imxrt_epfindbyaddr(priv, index)) != NULL) + { + imxrt_epstall(&privep->ep, true); + imxrt_ep0state(priv, EP0STATE_WAIT_NAK_IN); + } + else + { + usbtrace( + TRACE_DEVERROR(IMXRT_TRACEERR_BADCLEARFEATURE), 0); + priv->stalled = true; + } } - else if (priv->paddrset != 0 && - value == USB_FEATURE_ENDPOINTHALT && - len == 0 && (privep = imxrt_epfindbyaddr(priv, index)) != NULL) + break; + + case USB_REQ_SETFEATURE: { - imxrt_epstall(&privep->ep, true); - imxrt_ep0state(priv, EP0STATE_WAIT_NAK_IN); + /* type: host-to-device; recipient = device, interface, + * endpoint + * value: feature selector + * index: zero interface endpoint; + * len: 0; data = none + */ + + usbtrace(TRACE_INTDECODE(IMXRT_TRACEINTID_SETFEATURE), 0); + if (((ctrl->type & USB_REQ_RECIPIENT_MASK) == + USB_REQ_RECIPIENT_DEVICE) && + value == USB_FEATURE_TESTMODE) + { + uinfo("test mode: %d\n", index); + } + else if ((ctrl->type & USB_REQ_RECIPIENT_MASK) != + USB_REQ_RECIPIENT_ENDPOINT) + { + imxrt_dispatchrequest(priv, ctrl); + } + else if (priv->paddrset != 0 && + value == USB_FEATURE_ENDPOINTHALT && + len == 0 && + (privep = imxrt_epfindbyaddr(priv, index)) != NULL) + { + imxrt_epstall(&privep->ep, false); + imxrt_ep0state(priv, EP0STATE_WAIT_NAK_IN); + } + else + { + usbtrace(TRACE_DEVERROR(IMXRT_TRACEERR_BADSETFEATURE), 0); + priv->stalled = true; + } } - else + break; + + case USB_REQ_SETADDRESS: { - usbtrace(TRACE_DEVERROR(IMXRT_TRACEERR_BADCLEARFEATURE), 0); - priv->stalled = true; - } - } - break; + /* type: host-to-device; recipient = device + * value: device address + * index: 0 + * len: 0; data = none + */ - case USB_REQ_SETFEATURE: - { - /* type: host-to-device; recipient = device, interface, endpoint - * value: feature selector - * index: zero interface endpoint; - * len: 0; data = none - */ + usbtrace(TRACE_INTDECODE(IMXRT_TRACEINTID_EP0SETUPSETADDRESS), + value); + if (((ctrl->type & USB_REQ_RECIPIENT_MASK) == + USB_REQ_RECIPIENT_DEVICE) && + index == 0 && len == 0 && value < 128) + { + /* Save the address. We cannot actually change to the next + * address until the completion of the status phase. + */ - usbtrace(TRACE_INTDECODE(IMXRT_TRACEINTID_SETFEATURE), 0); - if (((ctrl->type & USB_REQ_RECIPIENT_MASK) == - USB_REQ_RECIPIENT_DEVICE) && value == USB_FEATURE_TESTMODE) - { - uinfo("test mode: %d\n", index); - } - else if ((ctrl->type & USB_REQ_RECIPIENT_MASK) != - USB_REQ_RECIPIENT_ENDPOINT) - { - imxrt_dispatchrequest(priv, ctrl); - } - else if (priv->paddrset != 0 && - value == USB_FEATURE_ENDPOINTHALT && - len == 0 && (privep = imxrt_epfindbyaddr(priv, index)) != NULL) - { - imxrt_epstall(&privep->ep, false); - imxrt_ep0state(priv, EP0STATE_WAIT_NAK_IN); - } - else - { - usbtrace(TRACE_DEVERROR(IMXRT_TRACEERR_BADSETFEATURE), 0); - priv->stalled = true; + priv->paddr = ctrl->value[0]; + priv->paddrset = false; + imxrt_ep0state(priv, EP0STATE_WAIT_NAK_IN); + } + else + { + usbtrace(TRACE_DEVERROR(IMXRT_TRACEERR_BADSETADDRESS), 0); + priv->stalled = true; + } } - } - break; + break; - case USB_REQ_SETADDRESS: - { - /* type: host-to-device; recipient = device - * value: device address - * index: 0 - * len: 0; data = none - */ + case USB_REQ_GETDESCRIPTOR: + /* type: device-to-host; recipient = device + * value: descriptor type and index + * index: 0 or language ID; + * len: descriptor len; data = descriptor + */ - usbtrace(TRACE_INTDECODE(IMXRT_TRACEINTID_EP0SETUPSETADDRESS), - value); - if (((ctrl->type & USB_REQ_RECIPIENT_MASK) == - USB_REQ_RECIPIENT_DEVICE) && - index == 0 && len == 0 && value < 128) - { - /* Save the address. We cannot actually change to the next - * address until the completion of the status phase. - */ + case USB_REQ_SETDESCRIPTOR: + /* type: host-to-device; recipient = device + * value: descriptor type and index + * index: 0 or language ID; + * len: descriptor len; data = descriptor + */ - priv->paddr = ctrl->value[0]; - priv->paddrset = false; - imxrt_ep0state(priv, EP0STATE_WAIT_NAK_IN); - } - else { - usbtrace(TRACE_DEVERROR(IMXRT_TRACEERR_BADSETADDRESS), 0); - priv->stalled = true; + usbtrace(TRACE_INTDECODE(IMXRT_TRACEINTID_GETSETDESC), 0); + if ((ctrl->type & USB_REQ_RECIPIENT_MASK) == + USB_REQ_RECIPIENT_DEVICE) + { + imxrt_dispatchrequest(priv, ctrl); + } + else + { + usbtrace(TRACE_DEVERROR(IMXRT_TRACEERR_BADGETSETDESC), 0); + priv->stalled = true; + } } - } - break; + break; - case USB_REQ_GETDESCRIPTOR: - /* type: device-to-host; recipient = device - * value: descriptor type and index - * index: 0 or language ID; - * len: descriptor len; data = descriptor - */ - - case USB_REQ_SETDESCRIPTOR: - /* type: host-to-device; recipient = device - * value: descriptor type and index - * index: 0 or language ID; - * len: descriptor len; data = descriptor - */ + case USB_REQ_GETCONFIGURATION: + /* type: device-to-host; recipient = device + * value: 0; + * index: 0; + * len: 1; data = configuration value + */ - { - usbtrace(TRACE_INTDECODE(IMXRT_TRACEINTID_GETSETDESC), 0); - if ((ctrl->type & USB_REQ_RECIPIENT_MASK) == - USB_REQ_RECIPIENT_DEVICE) { - imxrt_dispatchrequest(priv, ctrl); + usbtrace(TRACE_INTDECODE(IMXRT_TRACEINTID_GETCONFIG), 0); + if (priv->paddrset && + ((ctrl->type & USB_REQ_RECIPIENT_MASK) == + USB_REQ_RECIPIENT_DEVICE) && + value == 0 && index == 0 && len == 1) + { + imxrt_dispatchrequest(priv, ctrl); + } + else + { + usbtrace(TRACE_DEVERROR(IMXRT_TRACEERR_BADGETCONFIG), 0); + priv->stalled = true; + } } - else + break; + + case USB_REQ_SETCONFIGURATION: + /* type: host-to-device; recipient = device + * value: configuration value + * index: 0; + * len: 0; data = none + */ + { - usbtrace(TRACE_DEVERROR(IMXRT_TRACEERR_BADGETSETDESC), 0); - priv->stalled = true; + usbtrace(TRACE_INTDECODE(IMXRT_TRACEINTID_SETCONFIG), 0); + if (((ctrl->type & USB_REQ_RECIPIENT_MASK) == + USB_REQ_RECIPIENT_DEVICE) && + index == 0 && len == 0) + { + imxrt_dispatchrequest(priv, ctrl); + } + else + { + usbtrace(TRACE_DEVERROR(IMXRT_TRACEERR_BADSETCONFIG), 0); + priv->stalled = true; + } } - } - break; + break; - case USB_REQ_GETCONFIGURATION: - /* type: device-to-host; recipient = device - * value: 0; - * index: 0; - * len: 1; data = configuration value - */ + case USB_REQ_GETINTERFACE: + /* type: device-to-host; recipient = interface + * value: 0 + * index: interface; + * len: 1; data = alt interface + */ + + case USB_REQ_SETINTERFACE: + /* type: host-to-device; recipient = interface + * value: alternate setting + * index: interface; + * len: 0; data = none + */ - { - usbtrace(TRACE_INTDECODE(IMXRT_TRACEINTID_GETCONFIG), 0); - if (priv->paddrset && - ((ctrl->type & USB_REQ_RECIPIENT_MASK) == - USB_REQ_RECIPIENT_DEVICE) && - value == 0 && index == 0 && len == 1) { + usbtrace(TRACE_INTDECODE(IMXRT_TRACEINTID_GETSETIF), 0); imxrt_dispatchrequest(priv, ctrl); } - else - { - usbtrace(TRACE_DEVERROR(IMXRT_TRACEERR_BADGETCONFIG), 0); - priv->stalled = true; - } - } - break; + break; - case USB_REQ_SETCONFIGURATION: - /* type: host-to-device; recipient = device - * value: configuration value - * index: 0; - * len: 0; data = none - */ + case USB_REQ_SYNCHFRAME: + /* type: device-to-host; recipient = endpoint + * value: 0 + * index: endpoint; + * len: 2; data = frame number + */ - { - usbtrace(TRACE_INTDECODE(IMXRT_TRACEINTID_SETCONFIG), 0); - if (((ctrl->type & USB_REQ_RECIPIENT_MASK) == - USB_REQ_RECIPIENT_DEVICE) && index == 0 && len == 0) { - imxrt_dispatchrequest(priv, ctrl); + usbtrace(TRACE_INTDECODE(IMXRT_TRACEINTID_SYNCHFRAME), 0); } - else + break; + + default: { - usbtrace(TRACE_DEVERROR(IMXRT_TRACEERR_BADSETCONFIG), 0); + usbtrace(TRACE_DEVERROR(IMXRT_TRACEERR_INVALIDCTRLREQ), 0); priv->stalled = true; } + break; } - break; - - case USB_REQ_GETINTERFACE: - /* type: device-to-host; recipient = interface - * value: 0 - * index: interface; - * len: 1; data = alt interface - */ - - case USB_REQ_SETINTERFACE: - /* type: host-to-device; recipient = interface - * value: alternate setting - * index: interface; - * len: 0; data = none - */ - - { - usbtrace(TRACE_INTDECODE(IMXRT_TRACEINTID_GETSETIF), 0); - imxrt_dispatchrequest(priv, ctrl); - } - break; - - case USB_REQ_SYNCHFRAME: - /* type: device-to-host; recipient = endpoint - * value: 0 - * index: endpoint; - * len: 2; data = frame number - */ - - { - usbtrace(TRACE_INTDECODE(IMXRT_TRACEINTID_SYNCHFRAME), 0); - } - break; - - default: - { - usbtrace(TRACE_DEVERROR(IMXRT_TRACEERR_INVALIDCTRLREQ), 0); - priv->stalled = true; - } - break; - } - } + } if (priv->stalled) { @@ -1687,77 +1721,77 @@ static void imxrt_ep0complete(struct imxrt_usbdev_s *priv, uint8_t epphy) switch (priv->ep0state) { - case EP0STATE_DATA_IN: - if (imxrt_rqempty(privep)) - { - return; - } + case EP0STATE_DATA_IN: + if (imxrt_rqempty(privep)) + { + return; + } - if (imxrt_epcomplete(priv, epphy)) - { - imxrt_ep0state(priv, EP0STATE_WAIT_NAK_OUT); - } - break; + if (imxrt_epcomplete(priv, epphy)) + { + imxrt_ep0state(priv, EP0STATE_WAIT_NAK_OUT); + } + break; - case EP0STATE_DATA_OUT: - if (imxrt_rqempty(privep)) - { - return; - } + case EP0STATE_DATA_OUT: + if (imxrt_rqempty(privep)) + { + return; + } - if (imxrt_epcomplete(priv, epphy)) - { - imxrt_ep0state(priv, EP0STATE_WAIT_NAK_IN); - } - break; + if (imxrt_epcomplete(priv, epphy)) + { + imxrt_ep0state(priv, EP0STATE_WAIT_NAK_IN); + } + break; - case EP0STATE_SHORTREAD: + case EP0STATE_SHORTREAD: - /* Make sure we have updated data after the DMA transfer. - * This invalidation matches the flush in writedtd(). - */ + /* Make sure we have updated data after the DMA transfer. + * This invalidation matches the flush in writedtd(). + */ - up_invalidate_dcache((uintptr_t)priv->ep0buf, - (uintptr_t)priv->ep0buf + sizeof(priv->ep0buf)); + up_invalidate_dcache((uintptr_t)priv->ep0buf, + (uintptr_t)priv->ep0buf + sizeof(priv->ep0buf)); - imxrt_dispatchrequest(priv, &priv->ep0ctrl); - imxrt_ep0state(priv, EP0STATE_WAIT_NAK_IN); - break; + imxrt_dispatchrequest(priv, &priv->ep0ctrl); + imxrt_ep0state(priv, EP0STATE_WAIT_NAK_IN); + break; - case EP0STATE_SHORTWRITE: - imxrt_ep0state(priv, EP0STATE_WAIT_NAK_OUT); - break; + case EP0STATE_SHORTWRITE: + imxrt_ep0state(priv, EP0STATE_WAIT_NAK_OUT); + break; - case EP0STATE_WAIT_STATUS_IN: - imxrt_ep0state(priv, EP0STATE_IDLE); + case EP0STATE_WAIT_STATUS_IN: + imxrt_ep0state(priv, EP0STATE_IDLE); - /* If we've received a SETADDRESS packet, then we set the address - * now that the status phase has completed - */ + /* If we've received a SETADDRESS packet, then we set the address + * now that the status phase has completed + */ - if (! priv->paddrset && priv->paddr != 0) - { - usbtrace(TRACE_INTDECODE(IMXRT_TRACEINTID_EP0INSETADDRESS), - (uint16_t)priv->paddr); - imxrt_set_address(priv, priv->paddr); - } + if (!priv->paddrset && priv->paddr != 0) + { + usbtrace(TRACE_INTDECODE(IMXRT_TRACEINTID_EP0INSETADDRESS), + (uint16_t)priv->paddr); + imxrt_set_address(priv, priv->paddr); + } - break; + break; - case EP0STATE_WAIT_STATUS_OUT: - imxrt_ep0state(priv, EP0STATE_IDLE); - break; + case EP0STATE_WAIT_STATUS_OUT: + imxrt_ep0state(priv, EP0STATE_IDLE); + break; - default: + default: #ifdef CONFIG_DEBUG_FEATURES - DEBUGASSERT(priv->ep0state != EP0STATE_DATA_IN && - priv->ep0state != EP0STATE_DATA_OUT && - priv->ep0state != EP0STATE_SHORTWRITE && - priv->ep0state != EP0STATE_WAIT_STATUS_IN && - priv->ep0state != EP0STATE_WAIT_STATUS_OUT); + DEBUGASSERT(priv->ep0state != EP0STATE_DATA_IN && + priv->ep0state != EP0STATE_DATA_OUT && + priv->ep0state != EP0STATE_SHORTWRITE && + priv->ep0state != EP0STATE_WAIT_STATUS_IN && + priv->ep0state != EP0STATE_WAIT_STATUS_OUT); #endif - priv->stalled = true; - break; + priv->stalled = true; + break; } if (priv->stalled) @@ -1784,23 +1818,29 @@ static void imxrt_ep0nak(struct imxrt_usbdev_s *priv, uint8_t epphy) switch (priv->ep0state) { - case EP0STATE_WAIT_NAK_IN: - imxrt_ep0xfer(IMXRT_EP0_IN, NULL, 0); - imxrt_ep0state(priv, EP0STATE_WAIT_STATUS_IN); - break; + case EP0STATE_WAIT_NAK_IN: + { + imxrt_ep0xfer(IMXRT_EP0_IN, NULL, 0); + imxrt_ep0state(priv, EP0STATE_WAIT_STATUS_IN); + break; + } - case EP0STATE_WAIT_NAK_OUT: - imxrt_ep0xfer(IMXRT_EP0_OUT, NULL, 0); - imxrt_ep0state(priv, EP0STATE_WAIT_STATUS_OUT); - break; + case EP0STATE_WAIT_NAK_OUT: + { + imxrt_ep0xfer(IMXRT_EP0_OUT, NULL, 0); + imxrt_ep0state(priv, EP0STATE_WAIT_STATUS_OUT); + break; + } - default: + default: + { #ifdef CONFIG_DEBUG_FEATURES - DEBUGASSERT(priv->ep0state != EP0STATE_WAIT_NAK_IN && - priv->ep0state != EP0STATE_WAIT_NAK_OUT); + DEBUGASSERT(priv->ep0state != EP0STATE_WAIT_NAK_IN && + priv->ep0state != EP0STATE_WAIT_NAK_OUT); #endif - priv->stalled = true; - break; + priv->stalled = true; + break; + } } if (priv->stalled) @@ -1855,6 +1895,7 @@ bool imxrt_epcomplete(struct imxrt_usbdev_s *priv, uint8_t epphy) privreq->req.xfrd += xfrd; bool complete = true; + if (IMXRT_EPPHYOUT(privep->epphy)) { /* read(OUT) completes when request filled, or a short transfer is @@ -1979,9 +2020,13 @@ static int imxrt_usbinterrupt(int irq, void *context, void *arg) portsc1 = imxrt_getreg(IMXRT_USBDEV_PORTSC1(0)); if (portsc1 & USBDEV_PRTSC1_HSP) - priv->usbdev.speed = USB_SPEED_HIGH; + { + priv->usbdev.speed = USB_SPEED_HIGH; + } else - priv->usbdev.speed = USB_SPEED_FULL; + { + priv->usbdev.speed = USB_SPEED_FULL; + } if (portsc1 & USBDEV_PRTSC1_FPR) { @@ -2055,6 +2100,7 @@ static int imxrt_usbinterrupt(int irq, void *context, void *arg) /* Handle setup interrupts */ uint32_t setupstat = imxrt_getreg(IMXRT_USBDEV_ENDPTSETUPSTAT(0)); + if (setupstat) { /* Clear the endpoint complete CTRL OUT and IN when a Setup is @@ -2077,7 +2123,8 @@ static int imxrt_usbinterrupt(int irq, void *context, void *arg) if (disr & USBDEV_USBSTS_NAKI) { uint32_t pending = imxrt_getreg(IMXRT_USBDEV_ENDPTNAK(0)) & - imxrt_getreg(IMXRT_USBDEV_ENDPTNAKEN(0)); + imxrt_getreg(IMXRT_USBDEV_ENDPTNAKEN(0)); + if (pending) { /* We shouldn't see NAK interrupts except on Endpoint 0 */ @@ -2134,6 +2181,7 @@ static int imxrt_epconfigure(struct usbdev_ep_s *ep, /* Initialise EP capabilities */ uint16_t maxsize = GETUINT16(desc->mxpacketsize); + if ((desc->attr & USB_EP_ATTR_XFERTYPE_MASK) == USB_EP_ATTR_XFER_ISOC) { dqh->capability = (DQH_CAPABILITY_MAX_PACKET(maxsize) | @@ -2340,6 +2388,7 @@ static void *imxrt_epallocbuffer(struct usbdev_ep_s *ep, uint16_t bytes) */ struct imxrt_ep_s *privep = (struct imxrt_ep_s *)ep; + UNUSED(privep); usbtrace(TRACE_EPALLOCBUFFER, privep->epphy); @@ -2363,6 +2412,7 @@ static void *imxrt_epallocbuffer(struct usbdev_ep_s *ep, uint16_t bytes) static void imxrt_epfreebuffer(struct usbdev_ep_s *ep, void *buf) { struct imxrt_ep_s *privep = (struct imxrt_ep_s *)ep; + UNUSED(privep); usbtrace(TRACE_EPFREEBUFFER, privep->epphy); @@ -2606,22 +2656,32 @@ static struct usbdev_ep_s *imxrt_allocep(struct usbdev_s *dev, switch (eptype) { - case USB_EP_ATTR_XFER_INT: /* Interrupt endpoint */ - epset &= IMXRT_EPINTRSET; - break; + case USB_EP_ATTR_XFER_INT: /* Interrupt endpoint */ + { + epset &= IMXRT_EPINTRSET; + break; + } - case USB_EP_ATTR_XFER_BULK: /* Bulk endpoint */ - epset &= IMXRT_EPBULKSET; - break; + case USB_EP_ATTR_XFER_BULK: /* Bulk endpoint */ + { + epset &= IMXRT_EPBULKSET; + break; + } - case USB_EP_ATTR_XFER_ISOC: /* Isochronous endpoint */ - epset &= IMXRT_EPISOCSET; - break; + case USB_EP_ATTR_XFER_ISOC: /* Isochronous endpoint */ + { + epset &= IMXRT_EPISOCSET; + break; + } - case USB_EP_ATTR_XFER_CONTROL: /* Control endpoint -- not a valid choice */ - default: - usbtrace(TRACE_DEVERROR(IMXRT_TRACEERR_BADEPTYPE), (uint16_t)eptype); - return NULL; + case USB_EP_ATTR_XFER_CONTROL: /* Control endpoint -- not a valid choice + */ + default: + { + usbtrace(TRACE_DEVERROR(IMXRT_TRACEERR_BADEPTYPE), + (uint16_t)eptype); + return NULL; + } } /* Is the resulting endpoint supported by the IMXRT3x? */ @@ -2641,6 +2701,7 @@ static struct usbdev_ep_s *imxrt_allocep(struct usbdev_s *dev, for (epndx = 2; epndx < IMXRT_NPHYSENDPOINTS; epndx++) { uint32_t bit = 1 << epndx; + if ((epset & bit) != 0) { /* Mark endpoint no longer available */ @@ -2782,6 +2843,7 @@ static int imxrt_pullup(struct usbdev_s *dev, bool enable) usbtrace(TRACE_DEVPULLUP, (uint16_t)enable); irqstate_t flags = enter_critical_section(); + if (enable) { imxrt_setbits(USBDEV_USBCMD_RS, IMXRT_USBDEV_USBCMD(0)); @@ -2931,7 +2993,8 @@ void arm_usbinitialize(void) imxrt_setbits(USBDEV_USBCMD_RST, IMXRT_USBDEV_USBCMD(0)); while (imxrt_getreg(IMXRT_USBDEV_USBCMD(0)) & USBDEV_USBCMD_RST) - ; + { + } /* Power up the PHY (turn off power disable) - USBPHYx_PWDn * Manual: The USB PHY Power-Down Register provides overall control of the @@ -2992,7 +3055,8 @@ void arm_usbuninitialize(void) imxrt_setbits(USBDEV_USBCMD_RST, IMXRT_USBDEV_USBCMD(0)); while (imxrt_getreg(IMXRT_USBDEV_USBCMD(0)) & USBDEV_USBCMD_RST) - ; + { + } /* Turn off USB power and clocking */ @@ -3098,4 +3162,3 @@ int usbdev_unregister(struct usbdevclass_driver_s *driver) g_usbdev.driver = NULL; return OK; } -