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39 lines (36 loc) · 1.54 KB
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-- Copyright (C) 2016 Intel Corporation. All rights reserved.
-- Your use of Intel Corporation's design tools, logic functions
-- and other software and tools, and its AMPP partner logic
-- functions, and any output files from any of the foregoing
-- (including device programming or simulation files), and any
-- associated documentation or information are expressly subject
-- to the terms and conditions of the Intel Program License
-- Subscription Agreement, the Intel Quartus Prime License Agreement,
-- the Intel MegaCore Function License Agreement, or other
-- applicable license agreement, including, without limitation,
-- that your use is for the sole purpose of programming logic
-- devices manufactured by Intel and sold by Intel or its
-- authorized distributors. Please refer to the applicable
-- agreement for further details.
-- Generated by Quartus Prime Version 16.1 (Build Build 196 10/24/2016)
-- Created on Wed May 31 18:02:32 2017
COMPONENT VGA_Controller
PORT
(
clk : IN STD_LOGIC;
rst : IN STD_LOGIC;
en : IN STD_LOGIC;
wr_req_disp : IN STD_LOGIC;
disp_width : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
disp_height : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
buffer_pos_rgb : IN STD_LOGIC_VECTOR(55 DOWNTO 0);
buffer_empty : IN STD_LOGIC;
buffer_read : OUT STD_LOGIC;
VGA_R : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
VGA_G : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
VGA_B : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
VGA_BLANK : OUT STD_LOGIC;
VGA_HSYNC : OUT STD_LOGIC;
VGA_VSYNC : OUT STD_LOGIC
);
END COMPONENT;