From f78dc6b85879e69da2ce72e493c066b54802aa4f Mon Sep 17 00:00:00 2001
From: Ludovic Henry <git@ludovic.dev>
Date: Thu, 10 Sep 2026 11:07:27 +0200
Subject: [PATCH] cython: add 3.2.9-specific riscv64 cibuildwheel patch

The 3.3.0 patch (patches/cython/3.3.0/) does not apply to 3.2.9: its
aarch64 override context includes an inherit.environment = "append"
line that 3.2.9's pyproject.toml does not have. Add a version-specific
patch carrying the same riscv64 CFLAGS override, matching 3.2.9's own
override style.
---
 ...64-cibuildwheel-environment-override.patch | 47 +++++++++++++++++++
 1 file changed, 47 insertions(+)
 create mode 100644 patches/cython/3.2.9/0001-Add-riscv64-cibuildwheel-environment-override.patch

diff --git a/patches/cython/3.2.9/0001-Add-riscv64-cibuildwheel-environment-override.patch b/patches/cython/3.2.9/0001-Add-riscv64-cibuildwheel-environment-override.patch
new file mode 100644
index 000000000..ad62c4066
--- /dev/null
+++ b/patches/cython/3.2.9/0001-Add-riscv64-cibuildwheel-environment-override.patch
@@ -0,0 +1,47 @@
+From 9166cd9b78944c6bbba3513f1d2dc161033642b1 Mon Sep 17 00:00:00 2001
+From: Ludovic Henry <git@ludovic.dev>
+Date: Thu, 10 Sep 2026 11:04:48 +0200
+Subject: [PATCH] Add riscv64 cibuildwheel environment override
+
+The [tool.cibuildwheel.linux.environment] default sets x86-specific
+CFLAGS (-march=core2 -mno-ssse3), and the per-arch overrides cover
+aarch64 and armv7l but not riscv64. Building manylinux_riscv64 wheels
+therefore inherits the x86 default and fails at the C compile:
+
+    gcc: error: '-march=core2': ISA string must begin with rv32 or rv64
+    gcc: error: unrecognized command-line option '-mno-ssse3'
+
+Add a riscv64 override mirroring the aarch64 one, using the RVA-baseline
+flags used to build riscv64gc packages (matches the Yocto qemuriscv64
+toolchain: rv64imafdc + lp64d ABI).
+
+Backport of the equivalent override added upstream for cython 3.3.0
+(commit 353d241c339f14e9bddf81d64a485859e57964b1), adapted for 3.2.9's
+pyproject.toml which predates the inherit.environment = "append" style
+adopted later.
+
+Upstream-Status: Backport [https://github.com/cython/cython/commit/353d241c339f14e9bddf81d64a485859e57964b1]
+
+Signed-off-by: Ludovic Henry <git@ludovic.dev>
+---
+ pyproject.toml | 4 ++++
+ 1 file changed, 4 insertions(+)
+
+diff --git a/pyproject.toml b/pyproject.toml
+index 2b68685..f990d76 100644
+--- a/pyproject.toml
++++ b/pyproject.toml
+@@ -35,6 +35,10 @@ RANLIB = "gcc-ranlib"
+ select = "*aarch64"
+ environment = {CFLAGS = "-O3 -g0 -pipe -fPIC -DNDEBUG -march=armv8-a -mtune=cortex-a72", AR = "gcc-ar", NM = "gcc-nm", RANLIB = "gcc-ranlib"}
+ 
++[[tool.cibuildwheel.overrides]]
++select = "*riscv64"
++environment = {CFLAGS = "-O3 -g0 -pipe -fPIC -DNDEBUG -march=rv64imafdc_zicsr_zifencei -mabi=lp64d -fstack-protector-strong", AR = "gcc-ar", NM = "gcc-nm", RANLIB = "gcc-ranlib"}
++
+ [[tool.cibuildwheel.overrides]]
+ select = "*armv7l"
+ environment.CFLAGS = "-O3 -g0 -pipe -fPIC"
+-- 
+2.50.1 (Apple Git-155)
+