Unified RISC-V Single Cycle Processor

This directory contains a unified implementation that merges the SingleProcessor and sc2 architectures into a single configurable design.

Architecture Overview

The unified processor supports both original architectures through a parameter ARCH_TYPE:

• ARCH_TYPE = 0: SingleProcessor style (simpler, uses ALU_decoder)
• ARCH_TYPE = 1: sc2 style (more comprehensive, direct ALU control)

Module Structure

Core Modules

1. RISCV_Single_Cycle.v - Main processor module

   • Configurable top-level module that instantiates all components
   • Supports both architecture styles through parameter

2. ALU.v - Arithmetic Logic Unit

   • Unified ALU supporting all operations from both architectures
   • sc2 style supports more operations (shifts, comparisons)

3. control_unit.v - Control Unit

   • SingleProcessor: Simple control with ALU_decoder
   • sc2: Comprehensive control with direct ALU operation encoding

4. RegisterFile.v - Register File

   • SingleProcessor: No reset support, simpler interface
   • sc2: Reset support, more robust interface

5. IMEM.v - Instruction Memory

   • SingleProcessor: Direct memory access
   • sc2: Bounds checking, hex file loading

6. DMEM.v - Data Memory

   • SingleProcessor: Simple read/write
   • sc2: Reset support, conditional read, hex initialization

7. Imm_Gen.v - Immediate Generator

   • SingleProcessor: Uses control signals (imm_src)
   • sc2: Opcode-based immediate generation

8. Branch_Comp.v - Branch Comparator

   • Used primarily by sc2 architecture
   • Supports all RISC-V branch conditions

9. ALU_decoder.v - ALU Decoder

   • Used primarily by SingleProcessor architecture
   • Converts ALU operation codes to control signals

Usage Examples

For SingleProcessor Style (ARCH_TYPE = 0)

RISCV_Single_Cycle #(.ARCH_TYPE(0)) processor (
    .clk(clk),
    .rst_n(rst_n),
    .PC_out_top(pc_out),
    .Instruction_out_top(instruction_out)
);

For sc2 Style (ARCH_TYPE = 1)

RISCV_Single_Cycle #(.ARCH_TYPE(1)) processor (
    .clk(clk),
    .rst_n(rst_n),
    .PC_out_top(pc_out),
    .Instruction_out_top(instruction_out)
);

Key Differences Between Architectures

Feature	SingleProcessor (ARCH_TYPE=0)	sc2 (ARCH_TYPE=1)
ALU Operations	Basic (AND, OR, ADD, SUB, SLT)	Extended (includes shifts, XOR)
Control Logic	Uses ALU_decoder	Direct ALU control
Branch Logic	Simple PC calculation	Branch comparator
Reset Support	Limited	Full reset support
Memory	Simple access	Bounds checking, file loading
Instruction Support	Basic RISC-V	More comprehensive

Memory Files

The sc2 architecture supports loading from memory files:

• ./mem/imem2.hex or ./mem/imem.hex for instruction memory
• ./mem/dmem_init2.hex or ./mem/dmem_init.hex for data memory initialization

Testing

To test the unified implementation:

1. SingleProcessor compatibility test: Set ARCH_TYPE = 0 and verify against original SingleProcessor testbench
2. sc2 compatibility test: Set ARCH_TYPE = 1 and verify against original sc2 testbench
3. Cross-architecture test: Run same instruction sequence on both architectures and compare results

Benefits of Unified Design

1. Code Reuse: Common functionality shared between architectures
2. Maintainability: Single codebase to maintain instead of two
3. Flexibility: Easy to switch between architectures for different use cases
4. Extensibility: New features can be added to benefit both architectures

Implementation Notes

• All modules use generate blocks to conditionally instantiate architecture-specific logic
• Interface mapping ensures compatibility with both original designs
• Default parameter values favor the more comprehensive sc2 architecture
• Unused ports are properly tied off to prevent synthesis warnings

Future Enhancements

• Add support for additional RISC-V instruction extensions
• Implement pipeline stages as configurable option
• Add performance monitoring capabilities
• Support for different memory configurations