A Verilog implementation of a single-cycle processor (a processor that executes one instruction per clock cycle). The design supports a subset of the MIPS Instruction Set Architecture. The exact list of instructions covered is shown in the figure below. There is also an excel file attached, which shows the complete signal assigning for each of them.
Figure 1 — List of the Instructions Covered
The processor is built around a classic single-cycle datapath. The overall schematic, showing the program counter, instruction memory, register file, ALU, data memory, and the control paths that tie them together, is shown in the figure below.
Figure 2 — Schematic of the Single Cycle Processor (source)
Simulation was done in ModelSim to verify correct execution of each supported instruction. The source code includes thorough inline comments explaining each module and the control signals that govern the datapath.
As a hands-on extension, GPIO and other board-specific settings were added to the Verilog code. The full design was then synthesized and deployed onto a Xilinx Zynq board using Vivado. This made it possible to feed the processor MIPS machine code and observe the results on physical hardware: register values, memory outputs, and peripheral signals.
| Layer | Tool / Device |
|---|---|
| Main Code | Verilog |
| Testbench | SystemVerilog |
| Verification | ModelSim |
| CAD Tool | Vivado |
| Implementation | Xilinx Zynq Board |