A fully combinational floating-point adder written from scratch in Verilog. The design follows the IEEE-754 single-precision standard and in order to challenge my Verilog skills, it is built entirely using combinational statements; no sequential logic, no clocks. It handles all input cases except ±∞ and NaN.
Figure 1 — The IEEE-754 Single-Precision Standard (source)
Inline comments in the source provide full documentation. Simulations were run in ModelSim to check functionality and the design was later implemented on a Zynq-7010 SoC board.
The below figure from Computer Organization and Design by D. A. Patterson and J. L. Hennessy, 5th edition, best show the workflow and the background idea behind the datapath coded.
Figure 2 — Workflow for Floating Point Addition
| Layer | Tool / Device |
|---|---|
| Main Code | Verilog |
| Testbench | SystemVerilog |
| Verification | ModelSim |
| Implementation | Zynq-7010 SoC |