Silicon Design Engineer |
ASIC Physical Design, Machine Learning, RTL Design, Processor Architecture, EDA Automation
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udp_camera_streaming
udp_camera_streaming PublicPure-HDL UDP/IPv4 video streamer — real-time OV2640 camera to Ethernet with no CPU in the data path. Near-10ms end-to-end latency on FPGA.
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DREAMPlace-hvp
DREAMPlace-hvp PublicForked from limbo018/DREAMPlace
Exact Hessian-Vector Products for all DREAMPlace objectives (density, LSE WL, WA WL) with convexity analysis and FD verification. Fork of limbo018/DREAMPlace.
C++
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TKB-FPGA/dimd-manycore-rv32
TKB-FPGA/dimd-manycore-rv32 Public256-core RISC-V processor with custom DIMD ISA extension, 2D-Torus NoC, and HBM2 integration. Implemented on Xilinx Alveo U280 at 400MHz. Published at HEART'24.
Assembly
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