🚀 RISC-V Processor Implementation on FPGA

This repository contains the design and implementation of a 32-bit RISC-V (RV32I) Processor tailored for FPGA platforms, specifically the PYNQ-Z2.

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🏗 Architecture

The project focuses on building a complete Single-Cycle Processor microarchitecture from scratch.

Single-Cycle Block Diagram

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🛠 Specifications

Category	Details
Instruction Set	RISC-V RV32I (Base Integer)
Microarchitecture	Evolutionary Design (Single-Cycle → Multi-Cycle → Pipelined)
Features	Hazard Handling, Performance Benchmarking, Cache Integration (TBD)
Target Hardware	PYNQ-Z2 (Xilinx Zynq-7000 SoC)
Hardware Language	Verilog HDL
EDA Tool	Xilinx Vivado 2025.2
Software Toolchain	TBD (e.g., RISC-V GNU Toolchain)

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📈 Project Roadmap & Progress

This project is structured in phases, moving from a basic functional processor to an optimized pipelined architecture with performance benchmarking.

Phase 1: Single-Cycle Processor

• Fundamental Architecture & Datapath Design
• Core RV32I Module Implementation (ALU, RegFile, ImmGen)
• Control Unit & Instruction Decoding Logic
• Functional Verification via Simulation (Vivado XSim)

Phase 2: Multi-Cycle Processor (⭐Current Focus⭐)

• State Machine Based Control Unit Design
• Resource Sharing Optimization (Shared ALU/Memory)
• Multi-cycle Instruction Timing Verification

Phase 3: Pipelined Processor

• 5-Stage Pipeline Implementation (IF, ID, EX, MEM, WB)
• Hazard Detection & Forwarding Unit (Data/Control Hazard Handling)
• Branch Prediction Logic Implementation

Phase 4: Performance Analysis & Optimization

• Benchmark Testing: Running Dhrystone/CoreMark on FPGA
• CPI Analysis: Cycles Per Instruction (CPI) measurement and comparison
• Timing & Resource Optimization: FPGA Synthesis/Implementation tuning
• Memory System Enhancement: Cache memory (L1) integration

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🔄 Development Workflow

The project follows a structured hardware design cycle for reliable implementation and verification.

1. RTL Coding: Modular design using Verilog HDL.
2. Functional Simulation: Verification using Vivado Simulator (XSim).
3. Synthesis & Implementation: Mapping logic to FPGA resources and timing analysis.
4. On-Board Testing: Final validation on the PYNQ-Z2 board.

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📚 References

This project is inspired by and references the following resources:

• Course: RISC-V Processor Design Course by Marco Spaziani Brunella
• Specification: Official RISC-V Instruction Set Manual