copper: model the WAIT/SKIP/COPJMP pipeline against the vAmiga copper trace

[LinuxJedi]

Rebased onto main c4c7207 (#141-#145); all numbers below are re-measured against a fresh c4c7207 baseline. savestate::STATE_VERSION is now 26 (#145 took 25). The interrupt-latency compensation from the pre-rebase version was dropped: #144's IPL poll placement models the recognition, and with the offset the Copper/Irq family regressed 15.0 -> 42.3 (without it: 14.9).

The class

Copper MOVE-after-WAIT register writes landed ~4 colour clocks late relative to vAmiga/real hardware (SPR0CTL at hpos $26 where the vAmigaTS spritedma/interfere real-A500 photos and vAmiga land it at $22). Three independent investigations converged on this class as the dominant Agnus/Copper residual.

Two-sided trace evidence

Both emulators instrumented with env-gated landing probes: COPPERLINE_DIAG_COP_WRITES=1 (new, this PR) and VAMIGA_COP_PROBE=1 in the local vAmiga tree (snapshot: vamigats-reports/vamiga-cop-probe.patch). Denise/Sprites/spritedma/interfere2 (WAIT $4721 / MOVE SPR0CTL / MOVE COLOR00 / WAIT $47B1 / MOVE COLOR00), per-frame steady state:

event	vAmiga	CL before	CL after
WAIT $4721 wakeup	v=047 h=1e	(match at h=20)	match at h=1e
MOVE SPR0CTL=$7F00	v=047 h=22	v=047 h=26	v=047 h=22
MOVE COLOR00=$F00	h=26	h=2a	h=26
MOVE COLOR00=$000 (after $47B1)	h=b2	h=b6	h=b2

The jumpbpu trace pinned two more pipeline differences: the frame-start stream (vAmiga's first line-0 MOVE write lands at h=$04; CL's landed at $08) and the post-COPJMP fetch (vAmiga strobe write at h=$04 fetches the new list's first MOVE at $0A, write at $0C; CL wrote at $08). Both are now cycle-exact against the vAmiga trace.

The pipeline model (all vAmiga-verified)

1. Comparator horizontal lookahead: the WAIT/SKIP comparator's horizontal input runs two colour clocks ahead of the beam and wraps through zero over the last three clocks of a line (vAmiga runHorizontalComparator). A sleeping WAIT wakes at target-2; the match clock is the bus-free wake-up cycle; the next fetch lands on the masked target, its write two clocks later.
2. WAIT/SKIP tail: two Copper cycles after the second word fetch (Minimig WAITSKIP1/2, vAmiga COP_WAIT1/2) -- an immediately-true WAIT resumes fetching at fetch2+6.
3. SKIP decision at the next first-word fetch (vAmiga evaluates the skip flag inside COP_FETCH): a line-end SKIP pushed past the wrap by the bus lockout sees the next line's vertical phase, which is what fires jumpbpu-style list switches.
4. COPJMP strobe tail: two Copper cycles (COP_JMP1/COP_JMP2) before the PC reloads from the live location register.
5. Line-end bus lockout at $E0 on short lines, $E1 on long lines (vAmiga busIsFree<COPPER>), previously fixed $E1.
6. Frame start at hpos $02 (first fetch), previously $06.

One calibration that had absorbed the old +4 landing moves in lockstep, with a TODO naming the CPU write-landing class it still compensates: copper-sourced render events are recorded at their Denise-effective position (DENISE_WRITE_EFFECT_DELAY_CCK, bus landing +4; CPU-sourced writes already carry that offset in their landing).

vAmigaTS results on the rebased stack (tools/vamigats-compare.py, diff% family sums, baseline = main c4c7207)

family	main c4c7207	this PR	note
Agnus/Copper (223)	1002.9	949.2 (-5.4%)	target family
- Skip	65.1	1.5	copstrt1/2 28.3 -> 0.000, copskip1 -> 0.0
- coptim	50.5	44.2	must-hold: improved
- mask	113.5	86.2
- cross	217.2	193.9	cross6 14.0 -> 0.024
- oldJump	138.0	132.0	jump2 -> 0.012, jumpbpu at base
- Irq	15.0	14.9	holds (compensation-free on top of #144)
- Wait / copvbl / CopDma	7.6 / 234.6 / 55.1	7.9 / 236.8 / 54.3	hold
- lc / halt / copbpl	hold	hold
- coprace	96.4	167.4	worst residual: 2 CPU-vs-copper COLOR race programs; the CPU loop's stripes interleave through bus contention with the shifted copper stream
Denise/Sprites/spritedma (66)	128.0	126.5	interfere1/1b/5 improved, interfere2/3/3b +0.3; residual is the sprite-side CTL-vs-DMA race replay, not the landing (now trace-exact)
Agnus/Blitter guard (233)	1641.5	1647.4 (+0.36%)	composes cleanly with #145 (pre-rebase, against old main, this guard read +4.2%); worst case +4.97pp (invisible11/13), improvements up to -6.0 (bltint6); no case over the 5pp gate

Other gates (rebased stack)

• cargo test --lib: 1329 passed.
• cargo clippy --all-targets --all-features --locked -- -D warnings and cargo fmt --check clean.
• 14-demo byte-identity vs main c4c7207: 13/14 byte-identical (eon, sota, itm, hamazing, genx, kick13boot, kicka1200, secondnature, roots-aga, gods, rebirth, tomato, zool). roots-ecs differs 1.76%: the bouncing "?" object at a different animation position at the 35s shot -- screenshot pair inspected, no glitches or corruption.

Rebase conflict resolutions

• src/savestate.rs: blitter: model the micro-cycle protocol against the vAmiga slot oracle #145 took version 25; this PR's bump renumbered to 26 with both changelog lines kept.
• src/bus/tests.rs (copper_wait_with_bfd_clear_resumes_after_busy_blitter_finishes): blitter: model the micro-cycle protocol against the vAmiga slot oracle #145's blit end protocol finishes the polled blit one colour clock earlier (wakeup prediction Some(8)); with this PR's wake semantics the MOVE write lands at hpos 0x2E, recorded at its Denise-effective position 0x32. Verified by the suite.
• No overlap with bus: mirror CPU byte writes to custom registers onto both bus halves #141 (custom-reg byte mirror), agnus: anchor below-hard-start DDFSTRT runs at their raw fetch grid #142 (DDF), cpu: calibrate 68010 MOVES/MOVE-from-CCR/RTE/dispatch cycles and fix STOP semantics #143/m68k: align per-instruction IPL poll points and interrupt dispatch idle placement with the 68000 microcode #144 (m68k/IPL): main's side taken untouched.

docs

• docs/internals/timing.md: fetch-cadence section rewritten for the lookahead/wake/tails/COPJMP model and the Denise write-effect recording.
• docs/debugger/headless.md: COPPERLINE_DIAG_COP_WRITES row.

[LinuxJedi]

Merge-order note: this PR and #145 both bump savestate::STATE_VERSION to 25 - whichever merges second must renumber to 26 (one-line change). The small guard-family movements (CIA +2.8, Paula +1.3, Blitter +4.2) are the CPU-vs-copper phase boundary and should be re-validated once stacked on #145's blitter model.