[TRTLLM-12720][feat] Support nvfp4 w4a16 on sm120 - #16511
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Signed-off-by: Pamela <179191831+pamelap-nvidia@users.noreply.github.com>
Signed-off-by: Pamela <179191831+pamelap-nvidia@users.noreply.github.com>
Signed-off-by: Pamela <179191831+pamelap-nvidia@users.noreply.github.com>
Signed-off-by: Pamela <179191831+pamelap-nvidia@users.noreply.github.com>
Signed-off-by: Pamela <179191831+pamelap-nvidia@users.noreply.github.com>
Signed-off-by: Pamela <179191831+pamelap-nvidia@users.noreply.github.com>
Signed-off-by: Pamela <179191831+pamelap-nvidia@users.noreply.github.com>
Signed-off-by: Pamela <179191831+pamelap-nvidia@users.noreply.github.com>
Signed-off-by: Pamela <179191831+pamelap-nvidia@users.noreply.github.com>
Signed-off-by: Pamela <179191831+pamelap-nvidia@users.noreply.github.com>
Signed-off-by: Pamela <179191831+pamelap-nvidia@users.noreply.github.com>
Signed-off-by: Pamela <179191831+pamelap-nvidia@users.noreply.github.com>
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Signed-off-by: Pamela <179191831+pamelap-nvidia@users.noreply.github.com>
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/bot skip --comment "Failure analysis: the failing SBSA multi-GPU Slurm job completed successfully with exit code 0:0; the pipeline failed in CI Slurm log-tracking/teardown after tail -f lost its transport endpoint and kill $tailPid errored. https://pbss.s8k.io/v1/AUTH_svc_tensorrt/sw-tensorrt-ci-analysis/LLM/main/L0_MergeRequest_PR/52563/failure_analysis.html " |
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Dev Engineer Review
The changes add SM120/121 PyTorch support for W4A16 NVFP4 inference across dense linear, LM-head, and MoE paths.
The reported local validation passes 74 merge-focused tests and 69 W4A16/model regression tests. Six CI runs failed or had L0 pipeline failures. Failure analysis and a new NVIDIA-triggered run are required.
QA Engineer Review
The PR adds test functions and coverage for:
No files under
tests/integration/test_lists/,test-db/,qa/, orwaives.txtwere modified. Coverage registration for the added test functions is not shown.Verdict: needs follow-up.
Summary
Adds end-to-end support for W4A16 NVFP4 checkpoints (packed FP4 weights + per-group FP8
scales, high-precision activations) in the PyTorch backend, targeting Qwen3.5/3.6 and
Nemotron-H NVFP4 exports on SM120/121 (RTX 5090/6000, GB10) and Hopper.
The core problem this solves: TRT-LLM previously conflated "has NVFP4 weights" with
"quantizes activations to NVFP4". W4A16 breaks that assumption — it has FP4 weights but
consumes BF16/FP16 activations and has no calibrated
input_scale. Every FP4 fusion sitekeyed on
has_nvfp4would therefore feed anFp4QuantizedTensorinto a layer that can'tconsume one, or read a
Noneactivation scale.Changes
Activation-quantization capability, made explicit
LinearMethodBase.quantizes_nvfp4_activationsClassVar, surfaced asLinear.has_nvfp4_activation_quantizationandMoE.has_nvfp4_activation_quantization.Linear
W4A16NVFP4LinearMethod: on-the-fly Triton weight dequant. Leavesinput_scale/inv_input_scale/alphaasNonefromcreate_weightsonward; the parentprocess_weights_after_loading_*now skip scales whose destination was never allocated.MarlinNVFP4LinearMethod: Marlin-backed W4A16, selected by default for BF16 onSM90/120/121. Handles its own K->64 / N->128 padding.
buffer, which also makes the GMS
cache_derived_staterefresh idempotent (the previousin-place unswizzle would double-apply on re-materialization).
MoE
CuteDslB12xFusedMoEacceptsW4A16_NVFP4and stays on the b12x path for both prefilland decode (
quant_mode="w4a16"); falls back to CUTLASS for EP / attention-DP ornon-SM120/121.
W4A16NVFP4CutlassFusedMoEMethodon the CUTLASS path; shared per-layer quant-configlookup so mixed-precision checkpoints resolve expert configs correctly.
body sublayers to CUTLASS.
C++
120fin addition to90; relax theruntime SM asserts to
9.x || 12.x. No kernel logic changes.No LLM API surface change —
llm_args.pyis untouched, so no golden-manifestregeneration.
Behavior changes for existing users
via
nvfp4_gemm_config.allowed_backends: [..., marlin]). Attention FP4 output and thetorch.compile inplace op are disabled on those layers as a consequence.
AUTOresolves toCUTEDSLfor W4A16 NVFP4 on SM120/121.Test coverage
test_w4a16_nvfp4_linear.py(new) covers method selection across SM90/100/120/121 and dtype,the Marlin-vs-Triton numerical match on GPU (including K/N padding shapes), scale-cache buffer
semantics, the mixed-precision
use_fused_gemm_allreducerebind, and every fusion gate thatchanged. Plus new checkpoint-parsing tests (
test_model_config.py,test_quant_config_utils.py,test_kv_cache_dtype_override.py), Nemotron-H MoE/MTP configtests, the weight-mapper tests, and W4A16 cases added to the b12x MoE backend suite.
PR Checklist
Please review the following before submitting your PR:
PR description clearly explains what and why. If using CodeRabbit's summary, please make sure it makes sense.
PR Follows TRT-LLM CODING GUIDELINES to the best of your knowledge.
Test cases are provided for new code paths (see test instructions)
If PR introduces API changes, an appropriate PR label is added - either
api-compatibleorapi-breaking. Forapi-breaking, includeBREAKINGin the PR title.Any new dependencies have been scanned for license and vulnerabilities
CODEOWNERS updated if ownership changes
Documentation updated as needed
Update tava architecture diagram if there is a significant design change in PR.
The reviewers assigned automatically/manually are appropriate for the PR.
Please check this after reviewing the above items as appropriate for this PR.
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