gk710x: SD recovery, boot-image swap in the flash driver, eFuse table as on cameras

CLAUDE.md

@@ -101,7 +101,9 @@ The kernel still needs the blob (see "Hand-off to the kernel").
   - the words around the table are as in every SDK prebuilt and camera
     flash seen;
   - the table is `openipc/<soc>.rvs`, taken from the SDK's prebuilt
-    U-Boots, which matches what is on cameras in the field;
+    U-Boots, with the eFuse lines as GK7102 cameras in the field have
+    them (no write to `0x6000B100`; wait for `0x6000B104 == 3` after
+    starting the load). A GK7102 with the SDK's lines did not start;
   - GK7101 and GK7102 differ only in the DDR controller word at
     `0x60004004` (128 vs 64 MiB). `dram_init()` reads the same word back.
 - **Byte order.** The flash controller packs bytes MSB first. U-Boot, the
@@ -117,6 +119,17 @@ The kernel still needs the blob (see "Hand-off to the kernel").
     in its `gk7101_sflash.c`), and so does `gk_sflash.c`. `run ub` from
     either bootloader therefore writes exactly the bytes a programmer
     would. A CPU-order image (the SDK's prebuilts) is written unchanged.
+  - `gk_sflash.c` swaps the boot image's span on read as well (the image
+    found at offset 0 at probe, or the one last written there). Every
+    caller (`sf read`, SD recovery's "already on the flash" check) sees
+    the boot image as the file. Everything past it is the controller's
+    plain round trip.
+  - A whole-chip dump in chip order (a programmer's) restores with one
+    `sf write` at 0: a write at 0 that starts with the swapped magic is
+    swapped over its whole length. `sf update` splits it into sectors and
+    only the boot image comes out right. `sf read` of the whole chip is
+    not a dump either: the boot image in chip order, the rest in CPU
+    order.
   - Exception: the first release (2026-10-18) wrote CPU-order images and
     its `gk_sflash.c` has no swap check. `run ub` on a camera running it
     would write a chip-order image swapped twice and brick it. Upgrade
@@ -181,9 +194,17 @@ included.
   - `gk_ephy_init()` does the vendor's PHY clock (audio PLL, out on a pin),
     analog trim and MAC/PHY mux.
   - External-PHY boards (`phytype=1/2`) are not handled.
-- **SD:** not enabled. The vendor U-Boot had none, the controller's base
-  clock is unknown, and the SD pins depend on the board map. SD recovery in
-  `common/openipc.c` is compiled out with `CONFIG_MMC`.
+- **SD:** for recovery, the only way back for a camera without Ethernet
+  (`common/openipc.c`: `script.txt`, or uImage-wrapped `*.img` written at
+  their load address). `arch/arm/mach-gk710x/sdhci.c`:
+  - GK7101/GK7102: a standard SDHCI at `0x60002000`;
+  - GK710xS: at `0x90000000` in the vendor's halfword layout, so every
+    access goes through a table of where each SDHCI register and bit
+    sits, taken from what the S HAL does;
+  - the base clock comes from the RCT SD PLL and scaler.
+
+  U-Boot sets the map's SD pins and SD power pin. MMC, FAT and LTO
+  together still fit the 256 KiB boot partition.
 - **SPI NAND:** not supported. OpenIPC's GK7102 firmware is NOR only.
 
 ## The GK710xS (GK7101S, GK7102S, GK7102C)

arch/arm/mach-gk710x/Kconfig

@@ -32,6 +32,7 @@ endchoice
 
 config GK710X_S
 	bool
+	select MMC_SDHCI_IO_ACCESSORS if MMC_SDHCI
 	help
 	  The GK710xS die: its blocks sit at the addresses the vendor
 	  drivers use, in their register layout, instead of being moved and

arch/arm/mach-gk710x/Makefile

@@ -1,3 +1,4 @@
 # SPDX-License-Identifier: GPL-2.0+
 
 obj-y += lowlevel_init.o soc.o gpio.o kernel.o
+obj-$(CONFIG_MMC_SDHCI) += sdhci.o

arch/arm/mach-gk710x/include/mach/gk710x.h

@@ -20,6 +20,7 @@
 #ifndef CONFIG_GK710X_S
 
 /* AHB */
+#define GK_SDIO0_BASE		0x60002000	/* SDHCI */
 #define GK_DDRC_BASE		0x60004000
 #define GK_GMAC_BASE		0x6000E000
 #define GK_SFLASH_BASE		0x60016000
@@ -52,6 +53,8 @@
 #define GK_RCT_DIV_AUDIO_PRE	(GK_RCT_BASE + 0x060)
 #define GK_RCT_SCALER_UART	(GK_RCT_BASE + 0x038)
 #define GK_RCT_PLL_CORE		(GK_RCT_BASE + 0x0E4)
+#define GK_RCT_PLL_SD		(GK_RCT_BASE + 0x000)	/* fields moved */
+#define GK_RCT_SCALER_SD	(GK_RCT_BASE + 0x00C)
 #define GK_RCT_IOCTRL_MISC2	(GK_RCT_BASE + 0x200)
 #define GK_IOCTRL_MISC2_VAL	0x11
 /* Pad drive and pull: one byte per pin, four pins per word */
@@ -70,6 +73,7 @@
  */
 
 /* AHB */
+#define GK_SDIO0_BASE		0x90000000	/* vendor layout, sdhci.c */
 #define GK_DDRC_BASE		0x90002000
 #define GK_GMAC_BASE		0x9000E000	/* DWMAC, registers reordered */
 #define GK_SFLASH_BASE		0x90016000
@@ -100,6 +104,8 @@
 #define GK_RCT_DIV_AUDIO_PST	(GK_RCT_BASE + 0x084)
 #define GK_RCT_DIV_AUDIO_PRE	(GK_RCT_BASE + 0x080)
 #define GK_RCT_SCALER_UART	(GK_RCT_BASE + 0x028)
+#define GK_RCT_PLL_SD		(GK_RCT_BASE + 0x014)
+#define GK_RCT_SCALER_SD	(GK_RCT_BASE + 0x018)
 #define GK_RCT_IOCTRL_MISC2	(GK_RCT_BASE + 0x198)
 #define GK_IOCTRL_MISC2_VAL	0x12	/* the flash HOLD pin pulled up */
 /* Pad control words count down from GPIO 55 (gk7101s_gpio.c) */
@@ -149,8 +155,6 @@
 #ifndef __ASSEMBLY__
 void gk_gpio_config(unsigned int pin, unsigned int type);
 void gk_gpio_init(void);
-/* drivers/mtd/spi/gk_sflash.c, for cmd/sf.c */
-void gk_sflash_boot_order(unsigned int offset, unsigned long len, void *buf);
 /* board/goke/gk710x/gpio_map.c */
 void gk_gpio_map_apply(void);
 void gk_gpio_map_save(void *dst);