[widgetii]

OpenIPC/u-boot-xmedia stopped publishing on 2026-10-16 (u-boot-xmedia#14), and OpenIPC/firmware latest has carried this tree's -nor/-nand builds of its SoCs since: hi3516ev200/ev300, hi3518ev300, hi3516dv200, the gk7205v200 family, gk7205v500/v510/v530. Their fmc100 ID tables lacked 36 SPI NAND and 8 SPI NOR chips the xmedia builds identified, so a camera with one of them lost its flash. A NAND U-Boot reported Cannot found a valid SPI Nand Device / 0 MiB; a NOR U-Boot fell back to another vendor's profile, or to "unknown" at 4 MiB.

SPI NAND, appended after the existing entries (the driver takes the first ID-prefix match, so they cannot shadow one above):

• Micron MT29F1G01ABA/ABB, MT29F2G01ABA/ABB, MT29F4G01ADAG/ABBFDWB;
• GigaDevice GD5F1GM7UEYIG, GD5F1/2/4GQ4UAYIG, GD5F4GQ4RAYIG/RBYIG, GD5F4GQ6RE9IG;
• ESMT F50L512M41A, F50L1G41A, F50L1G41LB;
• Winbond W25N02JW, W25N02KV;
• Macronix MX35LF2GE4AB, MX35LF2G24AD, MX35UF4GE4AD;
• ATO25D1GA, Paragon PN26G01A/G02A, Foresee FM25S01-DND/FM25S01A, Alliance AFS1GQ4UAC/AFS2GQ4UAD, Toshiba TH58CYG3S0H, HeYangTek HYF1/2/4G, Etron EM73C044/EM78D/E/F044.

GD5F2GQ4U9IGR/BYIG and XT26G01B were skipped: existing entries already identify the same IDs.

SPI NOR (longest exact ID match wins): S25FL256S, XT25F16BSSIGU, MT25QL256A, F25L64QA, GD25Q256, W25Q256JW-IQ, W25Q256JWFIM, W25Q512NW-IM. F25L64QA maps to spi_driver_no_qe (xmedia's spi_driver_f25l64q has identical fields). The NOR clock limits apply as to every entry.

Data only. Entries are copied from OpenIPC/u-boot-xmedia master (bfbba0e5a); the fmc100 driver cores and the spi_nand_info/spi_nor_info structs match between the trees.

Checked in qemu-hisilicon (FMC READ_ID overridden with -global hisi-fmc.nand-jedec / flash-jedec), the published latest U-Boot vs this build:

	Chip (ID)	Published U-Boot	This build
SPI NAND (gk7205v200, hi3516ev300, gk7205v500)	GD5F1GM7 (0xc8 0x91)	0 MiB	Name:"GD5F1GM7UEYIG", 128 MiB
	GD5F1GQ4UAYIG (0xc8 0xf1)	0 MiB	named, 128 MiB
	MT29F2G01ABA (0x2c 0x24)	0 MiB	named, 256 MiB
	W25N02KV (0xef 0xaa 0x22)	0 MiB	named, 256 MiB
	W25N01GV (0xef 0xaa 0x21), control	128 MiB	128 MiB
SPI NAND (hi3516ev300, gk7205v200)	GD5F4GQ6RE9IG (0xc8 0x45)	not found	named
SPI NOR (hi3516ev300, gk7205v200)	W25Q256JW (0xef 0x60 0x19)	"unknown", 4 MB	named, 32 MB
	W25Q512NW (0xef 0x80 0x20)	"unknown", 4 MB	named, 64 MB
	GD25Q256	taken as W25Q256JVFIQ	its own name
	XT25F16B	taken as GD25Q16ESIG	its own name
	W25Q128, control	unchanged	unchanged

hi3516ev300, gk7205v200, gk7205v500 and hi3516cv300 build (NOR and NAND). The largest NOR image is 224256 of 262144 bytes; NAND images fit the 768K boot area.

The QEMU model answers only READ_ID, so this shows identification, not reads, writes or ECC with each chip's geometry. Timings are as xmedia had them. Not run on hardware.

[qodo-free-for-open-source-projects]

PR Summary by Qodo

fmc100: recognize SPI NAND and NOR chips from u-boot-xmedia

✨ Enhancement 🕐 40+ Minutes

AI Description

• Add 36 SPI NAND and eight SPI NOR profiles previously recognized by u-boot-xmedia.
• Restore flash identification and correct capacity reporting for affected cameras without changing
 driver cores.
• Confirm representative IDs and control chips in QEMU; hardware read, write, and ECC remain
 untested.

Diagram

graph TD
  F["FMC READ_ID"] -->|first prefix match| N["NAND ID table"] --> NP["NAND profile"] --> M["MTD flash"]
  F -->|longest exact match| R["NOR ID table"] --> RP["NOR profile"] --> M

Loading

High-Level Assessment

Extending the existing ID tables is appropriate: the driver cores and profile structures already support these chips. Appending NAND entries preserves first-match precedence, while NOR's existing longest-exact-match behavior selects the new profiles. A driver rewrite would add risk without addressing the missing IDs.

Files changed (2) +1341 / -0

Enhancement (2) +1341 / -0

fmc_spi_nand_ids.cAdd 36 SPI NAND identification profiles +1137/-0

Add 36 SPI NAND identification profiles

• Appends u-boot-xmedia chip profiles with IDs, geometry, operation timings, and existing driver hooks. Adds operation definitions needed by those profiles and leaves earlier first-prefix matches ahead of them.

drivers/mtd/nand/raw/fmc100/fmc_spi_nand_ids.c

fmc_spi_nor_ids.cAdd eight SPI NOR identification profiles +204/-0

Add eight SPI NOR identification profiles

• Adds chip IDs, capacities, addressing, operations, and existing driver hooks so affected parts receive their own profiles instead of a fallback. The F25L64QA entry uses the existing no-QE hook.

drivers/mtd/spi/fmc100/fmc_spi_nor_ids.c

[qodo-free-for-open-source-projects]

Code Review by Qodo

🐞 Bugs (3) 📘 Rule violations (0) 📎 Requirement gaps (0) 🎨 UX issues (0) 🔗 Cross-repo conflicts (0) 📜 Skill insights (0)

1. ESMT flash reads fail with quad mode off 🐞 Bug ≡ Correctness

Description

F25L64QA advertises a quad read operation but selects spi_driver_no_qe, whose initialization
never enables the chip's quad-enable bit. When quad reads are supported and that bit is clear at
startup, the probe can identify the flash but subsequent reads use an unenabled mode; the existing
driver for this same chip in the sibling controller explicitly enables quad mode.

Code

drivers/mtd/spi/fmc100/fmc_spi_nor_ids.c[2204]

+		&spi_driver_no_qe,  /* xmedia spi_driver_f25l64q: the same fields */

Evidence

The new entry offers quad reads, the read selector chooses the highest supported interface, and
initialization invokes the selected driver's QE callback. The selected callback does nothing,
whereas the existing F25L64QA driver in the sibling controller uses a QE-programming callback.

drivers/mtd/spi/fmc100/fmc_spi_nor_ids.c[2187-2204]
drivers/mtd/spi/fmc100/fmc_spi_nor_ids.c[178-183]
drivers/mtd/spi/fmc100/fmc_spi_nor_ids.c[2300-2318]
drivers/mtd/spi/fmc100/fmc_spi_nor_ids.c[2535-2546]
drivers/mtd/spi/fmc100/fmc100_spi_general.c[354-361]
drivers/mtd/spi/hisfc350/hisfc350_spi_ids.c[261-266]
drivers/mtd/spi/hisfc350/hisfc350_spi_ids.c[1922-1944]

Agent prompt

The issue below was found during a code review. Follow the provided context and guidance below and implement a solution

## Issue description
The new F25L64QA entry selects quad reads without enabling the chip's quad-enable bit.
## Fix Focus Areas
- drivers/mtd/spi/fmc100/fmc_spi_nor_ids.c[2187-2204]
- drivers/mtd/spi/hisfc350/hisfc350_spi_ids.c[261-266]
## Recommended Fix
Provide an fmc100 driver for F25L64QA that enables its quad mode using the appropriate status-register routine, and select it in the new entry. Verify reads after startup with quad mode initially disabled.

ⓘ Copy this prompt and use it to remediate the issue with your preferred AI generation tools

---

2. Spansion flash reads fail with QE off 🐞 Bug ≡ Correctness

Description

S25FL256S offers quad read operations but selects spi_driver_s25fl256s, whose quad-enable
callback is a no-op. When quad reads are supported and QE is clear at startup, initialization leaves
the chip in that state before selecting quad reads; the sibling controller's driver for the same
chip programs QE.

Code

drivers/mtd/spi/fmc100/fmc_spi_nor_ids.c[2076]

+		&spi_driver_s25fl256s,

Evidence

The new table entry includes quad reads, which the read selector can choose. Its driver invokes a
no-op QE callback during initialization, while the sibling controller associates S25FL256S with a
callback that programs QE.

drivers/mtd/spi/fmc100/fmc_spi_nor_ids.c[2053-2076]
drivers/mtd/spi/fmc100/fmc_spi_nor_ids.c[222-227]
drivers/mtd/spi/fmc100/fmc_spi_nor_ids.c[2300-2318]
drivers/mtd/spi/fmc100/fmc_spi_nor_ids.c[2535-2546]
drivers/mtd/spi/hisfc350/hisfc350_spi_ids.c[235-241]
drivers/mtd/spi/hisfc350/hisfc350_spi_ids.c[876-903]

Agent prompt

The issue below was found during a code review. Follow the provided context and guidance below and implement a solution

## Issue description
The new S25FL256S entry can select quad reads while its driver leaves QE unchanged.
## Fix Focus Areas
- drivers/mtd/spi/fmc100/fmc_spi_nor_ids.c[2053-2076]
- drivers/mtd/spi/fmc100/fmc_spi_nor_ids.c[222-227]
## Recommended Fix
Give the fmc100 S25FL256S driver the appropriate QE-programming callback, following the existing sibling-controller implementation. Verify quad reads when QE is initially clear.

ⓘ Copy this prompt and use it to remediate the issue with your preferred AI generation tools

---

3. Larger Winbond flash reads fail with QE off 🐞 Bug ≡ Correctness

Description

W25Q512NW-IM offers quad read operations but selects spi_driver_w25q256jv, whose quad-enable
callback does nothing. When quad reads are supported and QE is clear at startup, those reads use an
unenabled mode; the two newly added Winbond 256-Mbit entries instead select the driver that sets QE.

Code

drivers/mtd/spi/fmc100/fmc_spi_nor_ids.c[2182]

+		&spi_driver_w25q256jv,

Evidence

The new 512-Mbit entry includes quad reads but uses a driver with a no-op QE callback.
Initialization calls that callback after choosing the read operation; the neighboring new Winbond
entries use a driver whose callback writes the QE bit.

drivers/mtd/spi/fmc100/fmc_spi_nor_ids.c[2159-2182]
drivers/mtd/spi/fmc100/fmc_spi_nor_ids.c[229-234]
drivers/mtd/spi/fmc100/fmc_spi_nor_ids.c[2107-2130]
drivers/mtd/spi/fmc100/fmc_spi_nor_ids.c[2133-2156]
drivers/mtd/spi/fmc100/fmc_spi_nor_ids.c[2300-2318]
drivers/mtd/spi/fmc100/fmc_spi_nor_ids.c[2535-2546]
drivers/mtd/spi/fmc100/fmc100_spi_w25q256fv.c[124-181]

Agent prompt

The issue below was found during a code review. Follow the provided context and guidance below and implement a solution

## Issue description
The W25Q512NW-IM entry can select quad reads but its chosen driver does not enable QE.
## Fix Focus Areas
- drivers/mtd/spi/fmc100/fmc_spi_nor_ids.c[2159-2182]
- drivers/mtd/spi/fmc100/fmc_spi_nor_ids.c[229-234]
- drivers/mtd/spi/fmc100/fmc100_spi_w25q256fv.c[124-181]
## Recommended Fix
Assign a QE callback appropriate for W25Q512NW-IM while preserving its intended addressing behavior. Verify quad reads following startup with QE initially clear.

ⓘ Copy this prompt and use it to remediate the issue with your preferred AI generation tools

---

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