Triton Backed Supported (Beta) - #313

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student-Jungmin wants to merge 81 commits into

PSAL-POSTECH:feature/triton-codegenfrom

student-Jungmin:develop-npu-fixed

Commits on Aug 6, 2026

[Frontend] Follow tnpu's checkout rename in triton_src_dir

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4e2ebd3
[Frontend] Bind libdevice instead of refusing the kernel

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eb352de
[Frontend] Set estimate_peak, and vendor the pure-triton helpers

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e6afeff
[Docs] Make shipping automatic, and say which remote

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bff0dd6
[Frontend] Fix the multi-axis grid, and size blocks from hardware_config

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751cf09
[Frontend] Carry the dtypes tnpu already round-trips, any, and R0_BLOCK

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f737d2e
[Frontend] Vendor the welford helpers too

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c90f017

Commits on Aug 9, 2026

[Frontend] Four blockers between DeepSeek-V3 and the Triton route

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cbf9717
[Frontend] Carry the mm/conv template wiring onto this branch, and render a template call

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7858a17
[Frontend] Expand integer min/max before the EmitC pipeline

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ad09f9d
[Frontend] Size conv blocks from the lane count, not from the GPU table

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06951dc
[Frontend] Take a template kernel's launch grid from the template

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8d35a60
[Frontend] Take a template kernel's grid from its own grid function
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1c1887c

Commits on Aug 10, 2026

[Frontend] Marshal a tensor in storage order, not in logical order

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9d78822
[Frontend] Replay a Triton kernel's Spike run when nothing it depends on changed

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849af5f
[Frontend] Make the Spike replay cache opt-in

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962fd55
[CI] Gate resnet18 on the Triton codegen route

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57232a2
[Frontend] Launch a grouped conv over one group's channels, and let timing be switched off

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621a51b
[Frontend] Switch the timing half off with the config the MLIR route reads

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2d75c17
[Frontend] Vendor the bitonic sort helpers, for top-k

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95ab0a9
[CI] Gate the Triton route on values, not on cycles, and add mobilenet

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d7da05f
[Frontend] Call a reduction persistent when our own block already covers it

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9459069
[Frontend] Stop splitting reductions while a split cannot be collected

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667eedd

Commits on Aug 11, 2026

[CI] Gate test_transformer on the Triton codegen route

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8749a8b
[Scripts] Clear the Triton route's artifacts too, for the reason they are missed

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62d4e12
[Frontend] Ask Inductor for persistent reductions, through its own choices hook

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026cef5
[Frontend] Size a Triton-route buffer by its strides, not by its shape

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ab60f6d
[Frontend] Ask the tensor for its strides, not the copy of it; test_vit passes

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47f0ae9
[Frontend] Stop claiming dim 0 is the lane axis, and that a lane holds one
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609e036
[Frontend] Gate CLIP and single_perceptron; vendor the two integer helpers

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80c296b
[Frontend] Record why SwinV2 is blocked, and that it is not blocked here

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715a55a
[Frontend] Hold a launch lock so two sessions cannot swap each other's tensors

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a2d5c9c
[Scripts] Clear the Triton route's artifacts too, for the reason they are missed

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7b9e256
[Frontend] Ask Inductor for persistent reductions, through its own choices hook

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23e03ae
[Frontend] Size a Triton-route buffer by its strides, not by its shape

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199cfc4
[Frontend] Ask the tensor for its strides, not the copy of it; test_vit passes

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88cdbba
[Frontend] Gate CLIP and single_perceptron; vendor the two integer helpers

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1511635
Merge feature/triton-codegen into develop-npu
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95aa32e
[Frontend] Let the Triton route honour pytorchsim_timing_mode
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0b6ae9d
[Frontend] Make the TOGSim YAML the one machine, and fix the template axis count
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1dca868
Merge e2e-transformer/scratch into develop-npu
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6c7565e
[Frontend] Gate convnextv2, which a masked-gather fix opened

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cea96eb

Commits on Aug 12, 2026

[Frontend] Record that swinv2's only blocker is the upstream one

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aaa6fa0
[Frontend] Build swinv2's mask on the device instead of compiling around it

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35cba64
[Tests] GPT-2 end to end on the Triton route

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b9f6d7e
[Frontend] Gate yolov5, whose only blocker was a stray opencv build

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e0eec1f
[Frontend] Read a transfer's indirect index off the types, not off slot 8

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c17ef94
[Frontend] Count a template kernel's grid axes once, and guard the count

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75feb81
[Frontend] Take mm tiles from PyTorchSim's own mapping, and drop the dead wrap

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45bb857
[Frontend] Force timing mode off on this branch, and fix what that exposed

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259533b
[Tests] Run BERT end to end on the Triton codegen route
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e93d804
[Frontend] Clamp the mm loads instead of folding them, on both sides now

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97e6393
[Frontend] Verify a buffer after the LAST kernel that writes it

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4381993
[Frontend] Name what the lane-count cap is actually holding up

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f5ab638
[Tests] Gate GPT-2 on the Triton route at the preset that passes

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fabb8e9
[Frontend] Say what the lane-count cap is over, now that two of three are gone

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de80b01
[Frontend] Reach the bmm spelling of the wrap, and drop the lane-count cap

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0e1e94c
[Frontend] Gate DeepSeek-V3, which now passes through the Triton route

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bc4cb0e
[Frontend] Ask the tile mapping about a rounded shape, so nothing is dropped

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a7d5058
[Frontend] Measure the scratchpad reservation instead of calling it a stopgap

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d36d0b1
[Frontend] Gate Mistral, and give the test the name it already answered to

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ceb986c
[Frontend] Never hand down a block wider than its numel, and sum(dim=0) works

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d615201
Merge remote-tracking branch 'fork/develop-npu' into develop-select-grid
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646f066
[Repo] Ignore .envrc, which docs/worktrees.md already calls uncommitted

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42b4645
[Tests] Raise the GPT-2 gate to the real 768-wide block

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7f67729
[Frontend] Persist a reduction only at a block this backend would have chosen
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[Frontend] Do not clamp a block whose numel is 1, which broke Mistral and DeepSeek

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74ded09
Merge remote-tracking branch 'fork/develop-npu' into e2e-gpt2/scratch
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c51f682
[Repo] Untrack .envrc, which the merge used to replace this worktree's env

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554b6cc
Merge develop-npu: the block-sizing and lane-cap work under this change
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f2fcf79
Merge remote-tracking branch 'fork/develop-npu' into e2e-gpt2/scratch
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c36616c
Merge remote-tracking branch 'fork/e2e-bert/scratch' into e2e-gpt2/scratch
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99c698b
[Tests] Gate BERT on the real 768-wide block, and read the spad size once
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Merge e2e-bert/scratch: BERT end to end, and persistence declined where the block is not ours
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fb10765
[Tests] Record that all four GPT-2 presets pass, up to GPT-2 base itself

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9825b6e
Merge remote-tracking branch 'fork/develop-npu' into e2e-gpt2/scratch
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6ef4342
[Frontend] Verify a buffer after a kernel that WRITES it, not one that names it

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17dcde9
[Frontend] Add a Llama 3 test and gate both Llama tests on the Triton route
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d9803b6

Commits on Aug 13, 2026

[Frontend] Gate Stable Diffusion v1.5, which now runs end to end

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815258b
Merge branch 'develop-e2e-sd15' into HEAD
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[Frontend] Stop tracking PyTorchSimDevice build output

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43a719f