Fix WARP_SIZE detection for gfx942 (MI300X)#93
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Replace broken __GFX9__ guard with __AMDGCN_WAVEFRONT_SIZE (compiler-provided) and default to 64 for CDNA. The __GFX9__ macro is not defined at compile time on recent ROCm, causing WARP_SIZE=32 on 64-wide wavefront gfx942 (MI300X). This broke the 4-bit GEMV inference kernel grid launch and warp reduction, producing ~50% element mismatches in test_gemv_eye_4bit. Co-Authored-By: Claude Opus 4 (1M context) <noreply@anthropic.com>
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Summary
__GFX9__guard with__AMDGCN_WAVEFRONT_SIZE(compiler-provided) in bothcsrc/kernels.hipandcsrc/ops.hipRoot Cause
__GFX9__is not defined at compile time on recent ROCm builds, causingWARP_SIZE=32on 64-wide wavefront gfx942. This affected:ops.hip: grid launch computednum_blocks = (m+3)/4instead of(m+1)/2, skipping half the output rowskernels.hip:hipcub::WarpReducetemplate and lane/stride calculations used wrong warp widthSame root cause as ROCM-21835. Upstream fix in bitsandbytes-foundation/bitsandbytes PR bitsandbytes-foundation#1877 (merged 2026-02-24) unified CUDA/HIP sources with
BNB_WARP_SIZEbut was never synced to this fork.Test plan
pytest -vvv ./tests/test_functional.py::test_gemv_eye_4bit— 6/6 passed (fp16/bf16/fp32 × nf4/fp4)test_functional.pysuite regression check🤖 Generated with Claude Code