usb: xhci-pci: Limit VIA VL805 DMA addressing to 36 bits - #349
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mainline inclusion from mainline-v7.2-rc5 commit 1fc50f1 category: bugfix bugzilla: RVCK-Project#347 -------------------------------- The VIA VL805/806 xHCI controller advertises AC64, but fails to handle DMA addresses at or above 0x1000000000. On systems with large amounts of RAM, this can cause USB device failures when the controller is given DMA addresses beyond its usable address width. Do not use XHCI_NO_64BIT_SUPPORT for this controller. That quirk clears the cached AC64 capability and limits DMA to 32 bits, causing unnecessary bouncing for addresses between 4GiB and 64GiB and hiding the controller's real AC64 capability from code that may need to distinguish register access width from usable DMA address width. Track the usable DMA address width separately from the AC64 capability. Initialize the generic xhci->dma_mask_bits field to 64 and let PCI quirks reduce it for controllers with narrower DMA support. Set VIA VL805/806 to 36 bits so the DMA API only hands it addresses in the range it can handle while keeping HCCPARAMS1.AC64 visible. Cc: stable <stable@kernel.org> Signed-off-by: Xincheng Zhang <zhangxincheng@ultrarisc.com> Link: https://patch.msgid.link/20260630-xhci-via-dma-fix-v3-1-690dcb8cf75a@ultrarisc.com Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org> [Keep the function-like HCC_64BIT_ADDR() helper used by the 6.6 xHCI code while applying the upstream DMA mask handling.] Signed-off-by: Jia Wang <wangjia@ultrarisc.com>
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开始测试 log: https://github.com/RVCK-Project/rvck/actions/runs/30319647071 参数解析结果
测试完成 详细结果:
Kunit Test Result[01:19:19] Testing complete. Ran 482 tests: passed: 465, skipped: 17
Kernel Build Result
Check Patch Result
LAVA Check (qemu)lava 执行失败. |
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fixed: #347
mainline inclusion
from mainline-v7.2-rc5
commit 1fc50f1
category: bugfix
bugzilla: #347
The VIA VL805/806 xHCI controller advertises AC64, but fails to handle DMA addresses at or above 0x1000000000. On systems with large amounts of RAM, this can cause USB device failures when the controller is given DMA addresses beyond its usable address width.
Do not use XHCI_NO_64BIT_SUPPORT for this controller. That quirk clears the cached AC64 capability and limits DMA to 32 bits, causing unnecessary bouncing for addresses between 4GiB and 64GiB and hiding the controller's real AC64 capability from code that may need to distinguish register access width from usable DMA address width.
Track the usable DMA address width separately from the AC64 capability. Initialize the generic xhci->dma_mask_bits field to 64 and let PCI quirks reduce it for controllers with narrower DMA support. Set VIA VL805/806 to 36 bits so the DMA API only hands it addresses in the range it can handle while keeping HCCPARAMS1.AC64 visible.
Cc: stable stable@kernel.org
Link: https://patch.msgid.link/20260630-xhci-via-dma-fix-v3-1-690dcb8cf75a@ultrarisc.com
[Keep the function-like HCC_64BIT_ADDR() helper used by the 6.6 xHCI code while applying the upstream DMA mask handling.]
Signed-off-by: Jia Wang wangjia@ultrarisc.com