riscv: backport mainline xtheadvector support - #355
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dist inclusion category: cleanup Link: RVCK-Project#354 -------------------------------- This reverts commit 30843df. Signed-off-by: ZhenXing Zhu <zhenxing.zhu@linux.alibaba.com>
dist inclusion category: cleanup Link: RVCK-Project#354 -------------------------------- This reverts commit 4a43937. Signed-off-by: ZhenXing Zhu <zhenxing.zhu@linux.alibaba.com>
dist inclusion category: cleanup Link: RVCK-Project#354 -------------------------------- This reverts commit 3401b2a. Signed-off-by: ZhenXing Zhu <zhenxing.zhu@linux.alibaba.com>
…ector specification." dist inclusion category: cleanup Link: RVCK-Project#354 -------------------------------- This reverts commit d701970. Signed-off-by: ZhenXing Zhu <zhenxing.zhu@linux.alibaba.com>
mainline inclusion from mainline-6.10 commit c3f7c14 ("riscv: dts: allwinner: convert isa detection to new properties") category: feature Link: RVCK-Project#354 -------------------------------- Convert the D1 devicetrees to use the new properties "riscv,isa-base" & "riscv,isa-extensions". For compatibility with other projects, "riscv,isa" remains. Acked-by: Jernej Skrabec <jernej.skrabec@gmail.com> Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Link: https://lore.kernel.org/r/20231009-moonlight-gray-92debdc89f30@wendy Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com> Signed-off-by: ZhenXing Zhu <zhenxing.zhu@linux.alibaba.com>
mainline inclusion from mainline-6.14 commit e576b7c ("dt-bindings: riscv: Add xtheadvector ISA extension description") category: feature Link: RVCK-Project#354 -------------------------------- The xtheadvector ISA extension is described on the T-Head extension spec Github page [1] at commit 95358cb2cca9. Link: https://github.com/T-head-Semi/thead-extension-spec/blob/95358cb2cca9489361c61d335e03d3134b14133f/xtheadvector.adoc [1] Signed-off-by: Charlie Jenkins <charlie@rivosinc.com> Reviewed-by: Conor Dooley <conor.dooley@microchip.com> Tested-by: Yangyu Chen <cyy@cyyself.name> Link: https://lore.kernel.org/r/20241113-xtheadvector-v11-1-236c22791ef9@rivosinc.com Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com> Signed-off-by: ZhenXing Zhu <zhenxing.zhu@linux.alibaba.com>
mainline inclusion from mainline-6.14 commit bf6279b ("dt-bindings: cpus: add a thead vlen register length property") category: feature Link: RVCK-Project#354 -------------------------------- Add a property analogous to the vlenb CSR so that software can detect the vector length of each CPU prior to it being brought online. Currently software has to assume that the vector length read from the boot CPU applies to all possible CPUs. On T-Head CPUs implementing pre-ratification vector, reading the th.vlenb CSR may produce an illegal instruction trap, so this property is required on such systems. Signed-off-by: Charlie Jenkins <charlie@rivosinc.com> Reviewed-by: Conor Dooley <conor.dooley@microchip.com> Tested-by: Yangyu Chen <cyy@cyyself.name> Link: https://lore.kernel.org/r/20241113-xtheadvector-v11-2-236c22791ef9@rivosinc.com Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com> Signed-off-by: ZhenXing Zhu <zhenxing.zhu@linux.alibaba.com>
mainline inclusion from mainline-6.14 commit ce1daee ("riscv: dts: allwinner: Add xtheadvector to the D1/D1s devicetree") category: feature Link: RVCK-Project#354 -------------------------------- The D1/D1s SoCs support xtheadvector so it can be included in the devicetree. Also include vlenb for the cpu. Signed-off-by: Charlie Jenkins <charlie@rivosinc.com> Reviewed-by: Conor Dooley <conor.dooley@microchip.com> Tested-by: Yangyu Chen <cyy@cyyself.name> Link: https://lore.kernel.org/r/20241113-xtheadvector-v11-3-236c22791ef9@rivosinc.com Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com> Signed-off-by: ZhenXing Zhu <zhenxing.zhu@linux.alibaba.com>
mainline inclusion from mainline-6.14 commit cddd638 ("riscv: Add thead and xtheadvector as a vendor extension") category: feature Link: RVCK-Project#354 -------------------------------- Add support to the kernel for THead vendor extensions with the target of the new extension xtheadvector. Signed-off-by: Charlie Jenkins <charlie@rivosinc.com> Reviewed-by: Conor Dooley <conor.dooley@microchip.com> Tested-by: Yangyu Chen <cyy@cyyself.name> Link: https://lore.kernel.org/r/20241113-xtheadvector-v11-4-236c22791ef9@rivosinc.com Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com> Signed-off-by: ZhenXing Zhu <zhenxing.zhu@linux.alibaba.com>
mainline inclusion from mainline-6.14 commit 377be47 ("riscv: vector: Use vlenb from DT for thead") category: feature Link: RVCK-Project#354 -------------------------------- If thead,vlenb is provided in the device tree, prefer that over reading the vlenb csr. Signed-off-by: Charlie Jenkins <charlie@rivosinc.com> Acked-by: Conor Dooley <conor.dooley@microchip.com> Tested-by: Yangyu Chen <cyy@cyyself.name> Link: https://lore.kernel.org/r/20241113-xtheadvector-v11-5-236c22791ef9@rivosinc.com Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com> Signed-off-by: ZhenXing Zhu <zhenxing.zhu@linux.alibaba.com>
mainline inclusion from mainline-6.14 commit 66f1977 ("RISC-V: define the elements of the VCSR vector CSR") category: feature Link: RVCK-Project#354 -------------------------------- The VCSR CSR contains two elements VXRM[2:1] and VXSAT[0]. Define constants for those to access the elements in a readable way. Acked-by: Guo Ren <guoren@kernel.org> Reviewed-by: Conor Dooley <conor.dooley@microchip.com> Signed-off-by: Heiko Stuebner <heiko.stuebner@vrull.eu> Signed-off-by: Charlie Jenkins <charlie@rivosinc.com> Tested-by: Yangyu Chen <cyy@cyyself.name> Link: https://lore.kernel.org/r/20241113-xtheadvector-v11-6-236c22791ef9@rivosinc.com Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com> Signed-off-by: ZhenXing Zhu <zhenxing.zhu@linux.alibaba.com>
mainline inclusion from mainline-6.14 commit b9a9314 ("riscv: csr: Add CSR encodings for CSR_VXRM/CSR_VXSAT") category: feature Link: RVCK-Project#354 -------------------------------- The VXRM vector csr for xtheadvector has an encoding of 0xa and VXSAT has an encoding of 0x9. Co-developed-by: Heiko Stuebner <heiko@sntech.de> Signed-off-by: Heiko Stuebner <heiko@sntech.de> Signed-off-by: Charlie Jenkins <charlie@rivosinc.com> Tested-by: Yangyu Chen <cyy@cyyself.name> Link: https://lore.kernel.org/r/20241113-xtheadvector-v11-7-236c22791ef9@rivosinc.com Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com> [zhenxing.zhu@linux.alibaba.com: adapted to rvck-6.6 baseline csr.h which already has partial CSR definitions] Signed-off-by: ZhenXing Zhu <zhenxing.zhu@linux.alibaba.com>
mainline inclusion from mainline-6.14 commit 01e3313 ("riscv: Add xtheadvector instruction definitions") category: feature Link: RVCK-Project#354 -------------------------------- xtheadvector uses different encodings than standard vector for vsetvli and vector loads/stores. Write the instruction formats to be used in assembly code. Co-developed-by: Heiko Stuebner <heiko@sntech.de> Signed-off-by: Heiko Stuebner <heiko@sntech.de> Signed-off-by: Charlie Jenkins <charlie@rivosinc.com> Tested-by: Yangyu Chen <cyy@cyyself.name> Link: https://lore.kernel.org/r/20241113-xtheadvector-v11-8-236c22791ef9@rivosinc.com Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com> Signed-off-by: ZhenXing Zhu <zhenxing.zhu@linux.alibaba.com>
mainline inclusion from mainline-6.14 commit d863910 ("riscv: vector: Support xtheadvector save/restore") category: feature Link: RVCK-Project#354 -------------------------------- Use alternatives to add support for xtheadvector vector save/restore routines. Signed-off-by: Charlie Jenkins <charlie@rivosinc.com> Reviewed-by: Conor Dooley <conor.dooley@microchip.com> Tested-by: Yangyu Chen <cyy@cyyself.name> Link: https://lore.kernel.org/r/20241113-xtheadvector-v11-9-236c22791ef9@rivosinc.com Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com> [zhenxing.zhu@linux.alibaba.com: only vector.h hunks needed, other files already in rvck-6.6 baseline] Signed-off-by: ZhenXing Zhu <zhenxing.zhu@linux.alibaba.com>
…ension mainline inclusion from mainline-6.14 commit 7fa00fd ("riscv: hwprobe: Document thead vendor extensions and xtheadvector extension") category: feature Link: RVCK-Project#354 -------------------------------- Document support for thead vendor extensions using the key RISCV_HWPROBE_KEY_VENDOR_EXT_THEAD_0 and xtheadvector extension using the key RISCV_HWPROBE_VENDOR_EXT_XTHEADVECTOR. Signed-off-by: Charlie Jenkins <charlie@rivosinc.com> Reviewed-by: Evan Green <evan@rivosinc.com> Tested-by: Yangyu Chen <cyy@cyyself.name> Link: https://lore.kernel.org/r/20241113-xtheadvector-v11-11-236c22791ef9@rivosinc.com Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com> Signed-off-by: ZhenXing Zhu <zhenxing.zhu@linux.alibaba.com>
mainline inclusion from mainline-6.14 commit 57d7713 ("selftests: riscv: Fix vector tests") category: feature Link: RVCK-Project#354 -------------------------------- Overhaul the riscv vector tests to use kselftest_harness to help the test cases correctly report the results and decouple the individual test cases from each other. With this refactoring, only run the test cases if vector is reported and properly report the test case as skipped otherwise. The v_initval_nolibc test was previously not checking if vector was supported and used a function (malloc) which invalidates the state of the vector registers. Signed-off-by: Charlie Jenkins <charlie@rivosinc.com> Tested-by: Yangyu Chen <cyy@cyyself.name> Link: https://lore.kernel.org/r/20241113-xtheadvector-v11-12-236c22791ef9@rivosinc.com Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com> Signed-off-by: ZhenXing Zhu <zhenxing.zhu@linux.alibaba.com>
mainline inclusion from mainline-6.14 commit c384c5d ("selftests: riscv: Support xtheadvector in vector tests") category: feature Link: RVCK-Project#354 -------------------------------- Extend existing vector tests to be compatible with the xtheadvector instructions. Signed-off-by: Charlie Jenkins <charlie@rivosinc.com> Tested-by: Yangyu Chen <cyy@cyyself.name> Link: https://lore.kernel.org/r/20241113-xtheadvector-v11-13-236c22791ef9@rivosinc.com Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com> Signed-off-by: ZhenXing Zhu <zhenxing.zhu@linux.alibaba.com>
mainline inclusion from mainline-6.16 commit 4262bd0 ("riscv: vector: Fix context save/restore with xtheadvector") category: feature Link: RVCK-Project#354 -------------------------------- Previously only v0-v7 were correctly saved/restored, and the context of v8-v31 are damanged. Correctly save/restore v8-v31 to avoid breaking userspace. Fixes: d863910 ("riscv: vector: Support xtheadvector save/restore") Cc: stable@vger.kernel.org Signed-off-by: Han Gao <rabenda.cn@gmail.com> Tested-by: Xiongchuan Tan <tanxiongchuan@isrc.iscas.ac.cn> Reviewed-by: Charlie Jenkins <charlie@rivosinc.com> Reviewed-by: Yanteng Si <si.yanteng@linux.dev> Reviewed-by: Andy Chiu <andybnac@gmail.com> Link: https://lore.kernel.org/r/9b9eb2337f3d5336ce813721f8ebea51e0b2b553.1747994822.git.rabenda.cn@gmail.com Signed-off-by: Alexandre Ghiti <alexghiti@rivosinc.com> Signed-off-by: Palmer Dabbelt <palmer@dabbelt.com> Signed-off-by: ZhenXing Zhu <zhenxing.zhu@linux.alibaba.com>
…ous_vlenb() mainline inclusion from mainline-6.18 commit 2dc99ea ("riscv: cpufeature: avoid uninitialized variable in has_thead_homogeneous_vlenb()") category: feature Link: RVCK-Project#354 -------------------------------- In has_thead_homogeneous_vlenb(), smatch detected that the vlenb variable could be used while uninitialized. It appears that this could happen if no CPUs described in DT have the "thead,vlenb" property. Fix by initializing vlenb to 0, which will keep thead_vlenb_of set to 0 (as it was statically initialized). This in turn will cause riscv_v_setup_vsize() to fall back to CSR probing - the desired result if thead,vlenb isn't provided in the DT data. While here, fix a nearby comment typo. Cc: stable@vger.kernel.org Cc: Charlie Jenkins <charlie@rivosinc.com> Fixes: 377be47 ("riscv: vector: Use vlenb from DT for thead") Signed-off-by: Paul Walmsley <pjw@kernel.org> Link: https://lore.kernel.org/r/22674afb-2fe8-2a83-1818-4c37bd554579@kernel.org Signed-off-by: ZhenXing Zhu <zhenxing.zhu@linux.alibaba.com>
mainline inclusion from mainline-6.18 commit 9f393d8 ("riscv: dts: allwinner: d1: fix vlenb property") category: feature Link: RVCK-Project#354 -------------------------------- According to [1], the C906 vector registers are 128 bits wide. The 'thead,vlenb' property specifies the vector register length in bytes, so its value must be set to 16. [1] https://dl.linux-sunxi.org/D1/Xuantie_C906_R1S0_User_Manual.pdf Fixes: ce1daee ("riscv: dts: allwinner: Add xtheadvector to the D1/D1s devicetree") Signed-off-by: Sergey Matyukevich <geomatsi@gmail.com> Link: https://patch.msgid.link/20251119203508.1032716-1-geomatsi@gmail.com Signed-off-by: Chen-Yu Tsai <wens@kernel.org> Signed-off-by: ZhenXing Zhu <zhenxing.zhu@linux.alibaba.com>
mainline inclusion from mainline-6.19 commit aef6dc0 ("riscv: dts: thead: add xtheadvector to the th1520 devicetree") category: feature Link: RVCK-Project#354 -------------------------------- The th1520 support xtheadvector [1] so it can be included in the devicetree. Also include vlenb for the cpu. And set vlenb=16 [2]. This can be tested by passing the "mitigations=off" kernel parameter. Link: https://lore.kernel.org/linux-riscv/20241113-xtheadvector-v11-4-236c22791ef9@rivosinc.com/ [1] Link: https://lore.kernel.org/linux-riscv/aCO44SAoS2kIP61r@ghost/ [2] Signed-off-by: Han Gao <rabenda.cn@gmail.com> Reviewed-by: Drew Fustini <fustini@kernel.org> Signed-off-by: Drew Fustini <fustini@kernel.org> [zhenxing.zhu@linux.alibaba.com: xtheadvector already in isa, only added thead,vlenb property] Signed-off-by: ZhenXing Zhu <zhenxing.zhu@linux.alibaba.com>
mainline inclusion from mainline-6.11 commit ac295b6 ("riscv: vector: adjust minimum Vector requirement to ZVE32X") category: feature Link: RVCK-Project#354 -------------------------------- Make has_vector() to check for ZVE32X. Every in-kernel usage of V that requires a more complicate version of V must then call out explicitly. Also, change riscv_v_first_use_handler(), and boot code that calls riscv_v_setup_vsize() to accept ZVE32X. Most kernel/user interfaces requires minimum of ZVE32X. Thus, programs compiled and run with ZVE32X should be supported by the kernel on most aspects. This includes context-switch, signal, ptrace, prctl, and hwprobe. One exception is that ELF_HWCAP returns 'V' only if full V is supported on the platform. This means that the system without a full V must not rely on ELF_HWCAP to tell whether it is allowable to execute Vector without first invoking a prctl() check. Signed-off-by: Andy Chiu <andy.chiu@sifive.com> Acked-by: Joel Granados <j.granados@samsung.com> Link: https://lore.kernel.org/r/20240510-zve-detection-v5-7-0711bdd26c12@sifive.com Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com> [zhenxing.zhu@linux.alibaba.com: partial backport, vector.h/cpufeature.c/vector.c already applied via baseline, only sys_hwprobe.c and uaccess.S hunks added] Signed-off-by: ZhenXing Zhu <zhenxing.zhu@linux.alibaba.com>
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开始测试 log: https://github.com/RVCK-Project/rvck/actions/runs/30614654906 参数解析结果
测试完成 详细结果:
Kunit Test Result[08:59:26] Testing complete. Ran 482 tests: passed: 465, skipped: 17
Kernel Build Result
Check Patch Result
LAVA Check (qemu)lava 执行失败. |
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将上游 xtheadvector 主线支持 backport 到 rvck-6.6。先 revert 基线 4 个旧改 commit,再合入 18 个上游 commit。共 22 commits。
Reverts (4)
Series 1: riscv: Add support for xtheadvector (v11, Charlie Jenkins)
Cover: https://lore.kernel.org/r/20241113-xtheadvector-v11-0-236c22791ef9@rivosinc.com
13 patches 合入 12 个,patch 10 (
21e49e64f307) 基线已有,跳过。e576b7cb8183dt-bindings: riscv: Add xtheadvector ISA extension descriptionbf6279b38a4bdt-bindings: cpus: add a thead vlen register length propertyce1daeeba600riscv: dts: allwinner: Add xtheadvector to the D1/D1s devicetreecddd63869f92riscv: Add thead and xtheadvector as a vendor extension377be47f90e4riscv: vector: Use vlenb from DT for thead66f197785d51RISC-V: define the elements of the VCSR vector CSRb9a931442451riscv: csr: Add CSR encodings for CSR_VXRM/CSR_VXSAT (有差异,基线 csr.h 已有部分定义)01e3313e34d0riscv: Add xtheadvector instruction definitionsd863910eabafriscv: vector: Support xtheadvector save/restore (有差异,仅需 vector.h hunks)21e49e64f307riscv: hwprobe: Add thead vendor extension probing — 基线已有,跳过7fa00fd6ff53riscv: hwprobe: Document thead vendor extensions and xtheadvector extension57d7713af93eselftests: riscv: Fix vector testsc384c5d4a2aeselftests: riscv: Support xtheadvector in vector testsSeries 2: D1 dts isa-extensions 转换 (依赖补丁)
Link: https://lore.kernel.org/r/20231009-moonlight-gray-92debdc89f30@wendy
c3f7c14856ebriscv: dts: allwinner: convert isa detection to new propertiesSeries 3: zve-detection v5 (仅 patch 7)
Link: https://lore.kernel.org/r/20240510-zve-detection-v5-7-0711bdd26c12@sifive.com
ac295b67422driscv: vector: adjust minimum Vector requirement to ZVE32X (有差异,部分 backport,仅 sys_hwprobe.c + uaccess.S)fixes (4)
4262bd0d9cc7riscv: vector: Fix context save/restore with xtheadvectorhttps://lore.kernel.org/r/9b9eb2337f3d5336ce813721f8ebea51e0b2b553.1747994822.git.rabenda.cn@gmail.com
2dc99ea27276riscv: cpufeature: avoid uninitialized variable in has_thead_homogeneous_vlenb()https://lore.kernel.org/r/22674afb-2fe8-2a83-1818-4c37bd554579@kernel.org
9f393d8e757friscv: dts: allwinner: d1: fix vlenb propertyhttps://patch.msgid.link/20251119203508.1032716-1-geomatsi@gmail.com
aef6dc006696riscv: dts: thead: add xtheadvector to the th1520 devicetree (有差异,仅添加 thead,vlenb 属性)https://lore.kernel.org/linux-riscv/aCO44SAoS2kIP61r@ghost/
测试
fixed: #354