mimcap: size the via array off the MIM's enclosure, not the metal's - #114
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`mimcap` draws FuseTop at `size` and hands `size` straight to `via_array`,
which decides how many via columns fit using the generic metal-over-via
enclosure -- 0.12um for met5 over via4 on gf180. The MIM plate has a
stricter rule: MIMTM.4 (option B) and MIM.4 (option A) both want 0.4um of
plate over the via that contacts it.
The plate-to-via margin is therefore a sawtooth in `size`: it grows until
one more column fits, then drops back.
5.00um 5 columns margin 0.770
5.03um 5 columns margin 0.785
5.05um 6 columns margin 0.395 <- column enters, margin drops
5.80um 6 columns margin 0.770
5.85um 7 columns margin 0.395
The floor of that sawtooth is 0.390um: ample for 0.12, and 10nm short of
0.4. So the violations do not scale with the size, they repeat with the
via pitch of 0.80um, and a generator picking the plate side from a target
capacitance lands on them regularly while a hand-picked round size does
not.
Shrinking the array region by the difference between the two rules lifts
the whole sawtooth by that amount, floor included: 0.390 -> 0.670um. The
rule goes in the PDK as `capmet.via_enclosure`; PDKs that do not declare
it keep the old sizing untouched.
Cost: a column enters later than it used to, so some sizes get one fewer
via row and column -- 5.05um goes from 6 to 5. That is more series
resistance into the plate, which a MIM can afford, and it buys an
enclosure that holds at every size instead of at most of them.
Verified on gf180, sweeping 5.00-8.00um in 0.01um steps and measuring the
FuseTop-to-via4 distance in the GDS rather than counting violations:
before 301 sizes, 5 below 0.4um (5.05 5.85 6.65 7.44 7.45), worst 0.390
after 301 sizes, 0 below 0.4um, worst 0.670
DRC agrees on the nine sizes it was run for: 24 MIMTM.4 at 5.05um and 28
at 5.85um before, 0 everywhere after. A 14-case cell sweep that had 48
MIMTM.4 in one case now passes all of them.
msaligane
approved these changes
Aug 27, 2026
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mimcapdraws FuseTop atsizeand handssizestraight tovia_array, which decides how many via columns fit using the generic metal-over-via enclosure — 0.12um for met5 over via4 on gf180. The MIM plate has a stricter rule: MIMTM.4 (option B) and MIM.4 (option A) both want 0.4um of plate over the via that contacts it.The plate-to-via margin is therefore a sawtooth in
size: it grows until one more column fits, then drops back.The floor of that sawtooth is 0.390um: ample for 0.12, and 10nm short of 0.4. So the violations do not scale with the size, they repeat with the via pitch of 0.80um — a hand-picked round size looks clean while a generator that derives the plate side from a target capacitance lands on them regularly.
Shrinking the array region by the difference between the two rules lifts the whole sawtooth by that amount, floor included: 0.390 → 0.670um. The rule goes in the PDK as
capmet.via_enclosure; PDKs that do not declare it keep the old sizing untouched.Cost, stated up front: a column enters later than it used to, so some sizes get one fewer via row and column — 5.05um goes from 6 to 5. That is more series resistance into the plate, which a MIM can afford, in exchange for an enclosure that holds at every size instead of at most of them. A minimal fix (shrink by one grid unit) would keep the vias and leave the margin sitting exactly on the rule; that seemed like the wrong trade.
Verification
Sweeping 5.00–8.00um in 0.01um steps and measuring the FuseTop-to-via4 distance in the GDS, rather than counting violations:
DRC agrees on the nine sizes it was run for: 24 MIMTM.4 at 5.05um and 28 at 5.85um before, 0 everywhere after. A 14-case cell sweep that had 48 MIMTM.4 in one case now passes all of them.
Independent of #102/#104 and of the other open PRs — applies cleanly on
mainon its own.