gf180 opamp: three cell fixes (phantom netlist node, comp fill outside the implant, floating output well)

[carloscl03]

Three cell fixes on the gf180 opamp path, split out of #110. They are independent of each other, of that PR's other half, and of every other open PR — this branch is main plus these three commits.

diff_to_single's netlist declares a node the layout does not build. TOP1 and BOT1 met at a private V1. The layout puts TOP1's drain, BOT1's source, BOT2's drain and the next stage's gate on one net, which the extractor reports with five terminals — that net is VOUT. It is the cell's structure, not a stray overlap: the two halves are joined by more than one path, and deleting the whole strip where their rails cross still leaves them on the same net. VSS2, the counterpart node, already matched the netlist on all three terminals.

The comp fill between multipliers falls outside the implant. It is routed between ports that sit on the implant layer, so at their own width its edges come out level with the implant's instead of inside it: 0.01um of enclosure where PP.5b and PP.5dii ask for 0.16. Insetting the fill by the implant enclosure puts it where the real comp is.

The output stage's well is floating. __connect_cs_netlist declares B = S = VSS and its comment assumes the welltie ring already delivers that; extraction puts the output pfets' bulk on a net of its own, separate from VDD, along with the 200um dummy. The ring abuts the device and both ports are met2, so the tie is a straight run.

Measured

Built on gdstk with #102 and #104 applied (the gdsfactory backend cannot build these cells here), DRC via the gf180 klayout deck, mim_option=B, metal_level=5LM:

cell	before	after
differential_to_single_ended_converter	8 — DF.14_3.3V x4, PP.5di x4	4 — DF.14_3.3V x4
opamp	126 — M1.2a x60, M2.2a x37, M3.2a x15, M4.2a x6, PP.5b x4, PP.5dii x4	118 — the four metal categories only

Both remaining sets are untouched by these fixes: DF.14 and the M*.2a spacing family are separate problems.

The netlist change shows up in both cells:

-XTOP1 V1   VIN VSS  VSS pfet_03v3 ...      -XBOT1 VIN  VIN V1   VSS pfet_03v3 ...
+XTOP1 VOUT VIN VSS  VSS pfet_03v3 ...      +XBOT1 VIN  VIN VOUT VSS pfet_03v3 ...

The well tie took opamp LVS from 16 mismatches to 8 when it was measured on the earlier branch.

On #110

Closing it in favour of this. Its two commits have both been overtaken:

• the mimcap routing fix is moot — main now routes the array with vglayer="met5", hglayer="met4", and capmet on gf180 resolves to exactly that (capmettop (81,0) -> met5, capmetbottom (46,0) -> met4), so the hardcoded layers already agree with the PDK rule;
• the pin-label half is superseded by Fixing LVS errors for diff_pair #105 and tests/lvs: let the reference netlist decide which labels are pins, and the caller pick the gf180 MIM option #112.

@msaligane — this is the answer to the conflict requests on #110: there is no conflict to resolve there, the PR simply no longer applies. These three fixes were the part still worth having.