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Sta update 0725 #393
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Sta update 0725 #393
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| Original file line number | Diff line number | Diff line change |
|---|---|---|
|
|
@@ -213,7 +213,6 @@ GraphDelayCalc::delaysInvalid() | |
| debugPrint(debug_, "delay_calc", 1, "delays invalid"); | ||
| delays_exist_ = false; | ||
| delays_seeded_ = false; | ||
| incremental_ = false; | ||
| iter_->clear(); | ||
| // No need to keep track of incremental updates any more. | ||
| invalid_delays_.clear(); | ||
|
|
@@ -224,7 +223,7 @@ GraphDelayCalc::delaysInvalid() | |
| void | ||
| GraphDelayCalc::delayInvalid(const Pin *pin) | ||
| { | ||
| if (graph_ && incremental_) { | ||
| if (graph_ && delays_exist_) { | ||
| if (network_->isHierarchical(pin)) { | ||
| EdgesThruHierPinIterator edge_iter(pin, network_, graph_); | ||
| while (edge_iter.hasNext()) { | ||
|
|
@@ -248,7 +247,7 @@ GraphDelayCalc::delayInvalid(Vertex *vertex) | |
| { | ||
| debugPrint(debug_, "delay_calc", 2, "delay invalid {}", | ||
| vertex->to_string(this)); | ||
| if (incremental_) { | ||
| if (delays_exist_) { | ||
| invalid_delays_.insert(vertex); | ||
| // Invalidate driver that triggers dcalc for multi-driver nets. | ||
| MultiDrvrNet *multi_drvr = multiDrvrNet(vertex); | ||
|
|
@@ -274,7 +273,7 @@ void | |
| GraphDelayCalc::deleteVertexBefore(Vertex *vertex) | ||
| { | ||
| iter_->deleteVertexBefore(vertex); | ||
| if (incremental_) | ||
| if (delays_exist_) | ||
| invalid_delays_.erase(vertex); | ||
| MultiDrvrNet *multi_drvr = multiDrvrNet(vertex); | ||
| if (multi_drvr) { | ||
|
|
@@ -329,7 +328,7 @@ FindVertexDelays::copy() const | |
| void | ||
| FindVertexDelays::visit(Vertex *vertex) | ||
| { | ||
| graph_delay_calc_->findVertexDelay(vertex, arc_delay_calc_, true); | ||
| graph_delay_calc_->findVertexDelay(vertex, arc_delay_calc_); | ||
| } | ||
|
|
||
| // The logical structure of incremental delay calculation closely | ||
|
|
@@ -348,7 +347,7 @@ GraphDelayCalc::findDelays(Level level) | |
| } | ||
| else | ||
| iter_->ensureSize(); | ||
| if (incremental_) | ||
| if (delays_exist_) | ||
| seedInvalidDelays(); | ||
|
|
||
| if (!iter_->empty()) { | ||
|
|
@@ -367,7 +366,6 @@ GraphDelayCalc::findDelays(Level level) | |
| invalid_latch_edges_.clear(); | ||
|
|
||
| delays_exist_ = true; | ||
| incremental_ = true; | ||
| debugPrint(debug_, "delay_calc", 1, "found {} delays", dcalc_count); | ||
| stats.report("Delay calc"); | ||
| } | ||
|
|
@@ -674,13 +672,12 @@ GraphDelayCalc::findInputArcDelay(const Pin *drvr_pin, | |
| void | ||
| GraphDelayCalc::findDelays(Vertex *drvr_vertex) | ||
| { | ||
| findVertexDelay(drvr_vertex, arc_delay_calc_, true); | ||
| findVertexDelay(drvr_vertex, arc_delay_calc_); | ||
| } | ||
|
|
||
| void | ||
| GraphDelayCalc::findVertexDelay(Vertex *vertex, | ||
| ArcDelayCalc *arc_delay_calc, | ||
| bool propagate) | ||
| ArcDelayCalc *arc_delay_calc) | ||
| { | ||
| const Pin *pin = vertex->pin(); | ||
| debugPrint(debug_, "delay_calc", 2, "find delays {} ({})", | ||
|
|
@@ -692,32 +689,38 @@ GraphDelayCalc::findVertexDelay(Vertex *vertex, | |
| || (vertex->isBidirectDriver() | ||
| && network_->isTopLevelPort(pin))) | ||
| seedRootSlew(vertex, arc_delay_calc); | ||
| else { | ||
| if (network_->isLeaf(pin)) { | ||
| if (vertex->isDriver(network_)) { | ||
| LoadPinIndexMap load_pin_index_map = makeLoadPinIndexMap(vertex); | ||
| DrvrLoadSlews load_slews_prev; | ||
| if (incremental_) | ||
| load_slews_prev = loadSlews(load_pin_index_map); | ||
| findDriverDelays(vertex, arc_delay_calc, load_pin_index_map); | ||
| if (propagate) { | ||
| if (network_->direction(pin)->isInternal()) | ||
| enqueueTimingChecksEdges(vertex); | ||
| // Enqueue adjacent vertices even if the load slews did not | ||
| // change when non-incremental to stride past annotations. | ||
| if (!incremental_ | ||
| || loadSlewsChanged(load_slews_prev, load_pin_index_map)) | ||
| iter_->enqueueFanout(vertex); | ||
| } | ||
| } | ||
| else { | ||
| // Load vertex. | ||
| enqueueTimingChecksEdges(vertex); | ||
| // Enqueue driver vertices from this input load. | ||
| if (propagate) | ||
| iter_->enqueueFanout(vertex); | ||
| } | ||
| } | ||
| else if (network_->isLeaf(pin) | ||
| && vertex->isDriver(network_)) { | ||
| LoadPinIndexMap load_pin_index_map = makeLoadPinIndexMap(vertex); | ||
| DrvrLoadSlews load_slews_prev; | ||
| if (delays_exist_) | ||
| load_slews_prev = loadSlews(load_pin_index_map); | ||
| findDriverDelays(vertex, arc_delay_calc, load_pin_index_map); | ||
| if (network_->direction(pin)->isInternal()) | ||
| enqueueCheckEdges(vertex); | ||
| graph_->visitFanouts(vertex, search_non_latch_pred_, | ||
| [this, &load_slews_prev, &load_pin_index_map] | ||
| (Vertex *fanout) { | ||
| // Enqueue adjacent vertices even if the load slew | ||
| // did not change when non-incremental to stride | ||
| // past annotations. | ||
| if (!delays_exist_ | ||
| || loadSlewChanged(fanout, load_slews_prev, | ||
| load_pin_index_map)) { | ||
| iter_->enqueue(fanout); | ||
| fanout->setBfsPredecessorChanged(true); | ||
| } | ||
| }); | ||
| } | ||
| else if (vertex->isLoad(network_)) { | ||
| // Load vertex. | ||
| // Includes top level bidirect load vertex with wire edge to bidirect driver. | ||
| enqueueCheckEdges(vertex); | ||
| graph_->visitFanouts(vertex, search_non_latch_pred_, | ||
| [this] (Vertex *fanout) { | ||
| iter_->enqueue(fanout); | ||
| fanout->setBfsPredecessorChanged(true); | ||
| }); | ||
| } | ||
| } | ||
|
|
||
|
|
@@ -737,24 +740,25 @@ GraphDelayCalc::loadSlews(LoadPinIndexMap &load_pin_index_map) | |
| } | ||
|
|
||
| bool | ||
| GraphDelayCalc::loadSlewsChanged(DrvrLoadSlews &load_slews_prev, | ||
| LoadPinIndexMap &load_pin_index_map) | ||
| { | ||
| GraphDelayCalc::loadSlewChanged(Vertex *load_vertex, | ||
| DrvrLoadSlews &load_slews_prev, | ||
| LoadPinIndexMap &load_pin_index_map) | ||
| { | ||
| if (load_slews_prev.empty()) | ||
| return true; | ||
| size_t index = load_pin_index_map[load_vertex->pin()]; | ||
| SlewSeq &slews_prev = load_slews_prev[index];; | ||
|
Comment on lines
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There was a problem hiding this comment. Choose a reason for hiding this commentThe reason will be displayed to describe this comment to others. Learn more. Using Instead, use auto ip = load_pin_index_map.find(load_vertex->pin());
if (ip == load_pin_index_map.end())
return true;
size_t index = ip->second;
SlewSeq &slews_prev = load_slews_prev[index]; |
||
| size_t slew_count = graph_->slewCount(); | ||
| for (auto const [pin, index] : load_pin_index_map) { | ||
| Vertex *load_vertex = graph_->pinLoadVertex(pin); | ||
| SlewSeq &slews_prev = load_slews_prev[index];; | ||
| for (size_t i = 0; i < slew_count; i++) { | ||
| const Slew slew = graph_->slew(load_vertex, i); | ||
| if (!delayEqual(slew, slews_prev[i], this)) | ||
| return true; | ||
| } | ||
| for (size_t i = 0; i < slew_count; i++) { | ||
| const Slew slew = graph_->slew(load_vertex, i); | ||
| if (!delayEqual(slew, slews_prev[i], this)) | ||
| return true; | ||
| } | ||
| return false; | ||
| } | ||
|
|
||
| void | ||
| GraphDelayCalc::enqueueTimingChecksEdges(Vertex *vertex) | ||
| GraphDelayCalc::enqueueCheckEdges(Vertex *vertex) | ||
| { | ||
| if (vertex->hasChecks()) { | ||
| VertexInEdgeIterator edge_iter(vertex, graph_); | ||
|
|
@@ -1180,10 +1184,10 @@ GraphDelayCalc::annotateDelaysSlews(Edge *edge, | |
| dcalc_result.drvrSlew(), scene, min_max); | ||
| if (!edge->role()->isLatchDtoQ()) { | ||
| Vertex *drvr_vertex = edge->to(graph_); | ||
| delay_changed |= annotateLoadDelays(drvr_vertex, arc->toEdge()->asRiseFall(), | ||
| dcalc_result, | ||
| load_pin_index_map, delay_zero, true, | ||
| scene, min_max); | ||
| annotateLoadDelays(drvr_vertex, arc->toEdge()->asRiseFall(), | ||
| dcalc_result, | ||
| load_pin_index_map, delay_zero, true, | ||
| scene, min_max); | ||
| } | ||
| return delay_changed; | ||
| } | ||
|
|
@@ -1238,7 +1242,7 @@ GraphDelayCalc::annotateDelaySlew(Edge *edge, | |
| // Annotate wire arc delays and load pin slews. | ||
| // extra_delay is additional wire delay to add to delay returned | ||
| // by the delay calculator. | ||
| bool | ||
| void | ||
| GraphDelayCalc::annotateLoadDelays(Vertex *drvr_vertex, | ||
| const RiseFall *drvr_rf, | ||
| ArcDcalcResult &dcalc_result, | ||
|
|
@@ -1249,7 +1253,6 @@ GraphDelayCalc::annotateLoadDelays(Vertex *drvr_vertex, | |
| const MinMax *min_max) | ||
| { | ||
| DcalcAPIndex ap_index = scene->dcalcAnalysisPtIndex(min_max); | ||
| bool changed = false; | ||
| VertexOutEdgeIterator edge_iter(drvr_vertex, graph_); | ||
| while (edge_iter.hasNext()) { | ||
| Edge *wire_edge = edge_iter.next(); | ||
|
|
@@ -1264,20 +1267,17 @@ GraphDelayCalc::annotateLoadDelays(Vertex *drvr_vertex, | |
| load_vertex->to_string(this), | ||
| delayAsString(wire_delay, this), | ||
| delayAsString(load_slew, this)); | ||
| bool load_changed = false; | ||
| if (!load_vertex->slewAnnotated(drvr_rf, min_max)) { | ||
| if (drvr_vertex->slewAnnotated(drvr_rf, min_max)) { | ||
| // Copy the driver slew to the load if it is annotated. | ||
| const Slew drvr_slew = graph_->slew(drvr_vertex, drvr_rf, ap_index); | ||
| graph_->setSlew(load_vertex, drvr_rf, ap_index, drvr_slew); | ||
| load_changed = true; | ||
| } | ||
| else { | ||
| const Slew slew = graph_->slew(load_vertex, drvr_rf, ap_index); | ||
| if (!merge | ||
| || delayGreater(load_slew, slew, min_max, this)) { | ||
| graph_->setSlew(load_vertex, drvr_rf, ap_index, load_slew); | ||
| load_changed = true; | ||
| } | ||
| } | ||
| } | ||
|
|
@@ -1290,18 +1290,12 @@ GraphDelayCalc::annotateLoadDelays(Vertex *drvr_vertex, | |
| if (!merge | ||
| || delayGreater(wire_delay_extra, delay, min_max, this)) { | ||
| graph_->setWireArcDelay(wire_edge, drvr_rf, ap_index, wire_delay_extra); | ||
| load_changed = true; | ||
| if (observer_) | ||
| observer_->delayChangedTo(load_vertex); | ||
| } | ||
| } | ||
| if (load_changed && observer_) | ||
| observer_->delayChangedTo(load_vertex); | ||
| // Enqueue bidirect driver from load vertex. | ||
| if (bidirectDrvrSlewFromLoad(load_pin)) | ||
| iter_->enqueue(graph_->pinDrvrVertex(load_pin)); | ||
| changed |= load_changed; | ||
| } | ||
| } | ||
| return changed; | ||
| } | ||
|
|
||
| LoadPinIndexMap | ||
|
|
||
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Why the rename?
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macOS default filesystem is case-insensitive, so top-level file BUILD collides with CMake build/ dir - mkdir build fails / build dir creation clashes. BUILD.bazel is Bazel's equally-valid canonical name, so Bazel keeps working while build/ becomes creatable.