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Tomer-Harari/README.md

Hi, I'm Tomer 👋

Electrical Engineer, B.Sc. from Afeka College - Computers & Communications track. I build FPGA systems end to end: RTL and DSP datapaths, the verification environments that prove them, and the software and lab work around them.

What I work with

  • HDL & design: SystemVerilog, VHDL, Verilog - FSMs, AXI-Stream datapaths, pipelining, timing closure (Vivado & Quartus)
  • Verification: cocotb golden-model testbenches, randomized stimulus with backpressure, self-checking multi-seed regressions, formal proofs (SymbiYosys), Verilator lint, ModelSim, CI (GitHub Actions), bit-exact and interoperability-based sign-off
  • Protocols: VITA 49.2 / VRT / DIFI (SDR packet transport), DVB-S2 GSE (IP over satellite), LoRa-style framing with FEC, UDP/IP; Wireshark dissector development (Lua)
  • DSP & compute: digital down-conversion, CIC/FIR filtering, CORDIC, FM demodulation, fixed-point and int8 quantization, CNN inference, RISC-V (RV32I)
  • Tools & software: Python (NumPy, pytest), C, MATLAB, TCL, Git, Linux, Rust toolchains for cross-validation

Open-source portfolio

Thirteen public repositories, all built to the same standard: a bit-exact golden model, a multi-seed random regression under backpressure, lint, synthesis reports with real numbers, and CI. If a README claims it, there is a command that proves it.

Satellite / SDR transport

  • vita49.2-core - VITA 49.2 packetizer, de-packetizer and command endpoint; cross-checked byte-exact against an independent Rust implementation
  • dvb-gse-core - DVB-S2 GSE encapsulation with Base Band framing
  • vita49.2-wireshark-dissector - full CIF0 context and command decoding, expert analysis, field-exact automated test suite

Processing cores

  • rv32i-core - full RV32I processor, lock-step verified against an instruction-set simulator
  • mnist-cnn-accel - CNN inference accelerator, 97.6% MNIST at int8 in 532 LUTs
  • sdr-fm-ddc - complete FM receiver chain: CORDIC mixer, CIC/FIR decimation, demodulator
  • cordic-core, fir-core - characterized DSP building blocks

Verification & reliability

  • cdc-verification-lib - clock-domain-crossing primitives with machine-checked formal proofs
  • lora-telemetry-link - telemetry link with Hamming SECDED that corrects real channel errors; zero silent corruption across a 14,000-frame sweep
  • fpga-image-denoising - six VHDL filter architectures on Cyclone IV, verified bit-exact (1.18M pixels) and on hardware via JTAG readback
  • cvi-image-studio - image-processing application in C: DLL engine with hand-written BMP/PNG/TIFF writers, threaded convolution and a 2-D FFT with frequency-domain filtering

Reach me

LinkedIn: linkedin.com/in/itstomerharari Email: tomer211996@gmail.com

Pinned Loading

  1. fpga-image-denoising fpga-image-denoising Public

    Real-time salt-and-pepper image denoising on a Cyclone IV FPGA - six VHDL architectures, verified bit-exact (golden model / ModelSim / hardware readback), with a Python JTAG control GUI

    VHDL 1

  2. cdc-verification-lib cdc-verification-lib Public

    CDC primitives in SystemVerilog with formal proofs (SymbiYosys+Z3) and dual-clock cocotb regressions

    SystemVerilog

  3. dvb-gse-core dvb-gse-core Public

    DVB GSE (ETSI TS 102 606-1) encapsulation in SystemVerilog - golden-model cocotb verification, hardware CRC-32, Vivado timing-clean

    SystemVerilog

  4. mnist-cnn-accel mnist-cnn-accel Public

    CNN inference accelerator in SystemVerilog - MNIST at 97.6% with int8 quantization, one MAC + ping-pong BRAM, bit-exact golden model, timing-closed at 156MHz

    SystemVerilog

  5. rv32i-core rv32i-core Public

    Single-cycle RISC-V RV32I core in SystemVerilog - full user ISA, lock-step verification against a Python ISS, mini assembler, constrained-random ISA streams

    SystemVerilog

  6. vita49.2-core vita49.2-core Public

    VITA 49.2 (VRT) packet engine in SystemVerilog - packetizer, depacketizer and command endpoint with DIFI profile support, bit-exact golden model, Rust interop and Wireshark-verified traffic

    SystemVerilog