EEL 4768 Computer Architecture RISC-V Course Project

Overview

This project aims to guide students in this course to design a RISC-V processor following the RV32I instruction set, and further extending and optimization as the project continues.

Phases

1. Assembly and Assembler
2. ALU, register file, decoder, and immediate generator
3. Single-Cycle processor
4. Pipelined processor
5. Cache integration
6. Multiplication and floating point extention
7. Out-of-order Pipelined processor
8. Synthesis and Place and Route