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report the PL clock source and divisor for Versal - #37

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jogomojo merged 1 commit into
Xilinx:pynq-nextfrom
jogomojo:versal-clock-source-select
Aug 20, 2026
Merged

report the PL clock source and divisor for Versal#37
jogomojo merged 1 commit into
Xilinx:pynq-nextfrom
jogomojo:versal-clock-source-select

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@jogomojo
jogomojo force-pushed the versal-clock-source-select branch from a7f6976 to f18704a Compare August 20, 2026 20:47
@jogomojo
jogomojo merged commit 6cef668 into Xilinx:pynq-next Aug 20, 2026
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jogomojo deleted the versal-clock-source-select branch August 20, 2026 21:02
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