Draft: Add initial support for CH32H417 (#1023)

build.zig

@@ -31,6 +31,7 @@ const port_list: []const struct {
     .{ .name = "rp2xxx", .dep_name = "port/raspberrypi/rp2xxx" },
     .{ .name = "stm32", .dep_name = "port/stmicro/stm32" },
     .{ .name = "ch32v", .dep_name = "port/wch/ch32v" },
+    .{ .name = "ch32h", .dep_name = "port/wch/ch32h" },
     .{ .name = "msp430", .dep_name = "port/texasinstruments/msp430" },
     .{ .name = "mspm0", .dep_name = "port/texasinstruments/mspm0" },
     .{ .name = "tm4c", .dep_name = "port/texasinstruments/tm4c" },
@@ -70,6 +71,7 @@ pub const PortSelect = struct {
     rp2xxx: bool = false,
     stm32: bool = false,
     ch32v: bool = false,
+    ch32h: bool = false,
     msp430: bool = false,
     mspm0: bool = false,
     tm4c: bool = false,

build.zig.zon

@@ -45,6 +45,7 @@
         .@"port/texasinstruments/mspm0" = .{ .path = "port/texasinstruments/mspm0", .lazy = true },
         .@"port/texasinstruments/tm4c" = .{ .path = "port/texasinstruments/tm4c", .lazy = true },
         .@"port/wch/ch32v" = .{ .path = "port/wch/ch32v", .lazy = true },
+        .@"port/wch/ch32h" = .{ .path = "port/wch/ch32h", .lazy = true },
     },
     .paths = .{
         "README.md",

examples/wch/ch32h/build.zig

@@ -0,0 +1,32 @@
+const std = @import("std");
+const microzig = @import("microzig");
+
+const MicroBuild = microzig.MicroBuild(.{
+    .ch32h = true,
+});
+
+pub fn build(b: *std.Build) void {
+    const optimize = b.standardOptimizeOption(.{ .preferred_optimize_mode = .small });
+
+    const mz_dep = b.dependency("microzig", .{});
+    const mb = MicroBuild.init(b, mz_dep) orelse return;
+
+    const v3f = mb.add_firmware(.{
+        .name = "v3f",
+        .root_source_file = b.path("src/v3f.zig"),
+        .optimize = optimize,
+        .target = mb.ports.ch32h.chips.ch32h417_v3f,
+    });
+
+    const v5f = mb.add_firmware(.{
+        .name = "v5f",
+        .root_source_file = b.path("src/v5f.zig"),
+        .optimize = optimize,
+        .target = mb.ports.ch32h.chips.ch32h417_v5f,
+    });
+
+    const merged_bin = mb.ports.ch32h.merge(mz_dep, v3f.get_emitted_elf(), v5f.get_emitted_elf(), "merged.bin");
+
+    const install = b.addInstallFileWithDir(merged_bin, .{ .custom = "firmware" }, "merged.bin");
+    b.getInstallStep().dependOn(&install.step);
+}

examples/wch/ch32h/build.zig.zon

@@ -0,0 +1,14 @@
+.{
+    .name = .examples_wch_ch32h,
+    .fingerprint = 0x98c6b66930eca2b,
+    .version = "0.0.0",
+    .dependencies = .{
+        .microzig = .{ .path = "../../.." },
+    },
+
+    .paths = .{
+        "build.zig",
+        "build.zig.zon",
+        "src",
+    },
+}

examples/wch/ch32h/src/v3f.zig

@@ -0,0 +1,40 @@
+const microzig = @import("microzig");
+const std = @import("std");
+
+pub const panic = microzig.panic;
+
+pub const std_options = microzig.std_options(.{});
+
+comptime {
+    _ = microzig.export_startup();
+}
+
+const gpio = microzig.hal.gpio;
+
+const RCC = microzig.chip.peripherals.RCC;
+const PFIC = microzig.chip.peripherals.PFIC;
+const GPIOC = microzig.chip.peripherals.GPIOC;
+
+const pin: u4 = 2;
+
+fn delay(cycles: u32) void {
+    for (0..cycles) |_| {
+        asm volatile ("nop");
+    }
+}
+
+pub fn main() !void {
+    RCC.HB2PCENR.modify(.{ .IOPCEN = 1 });
+
+    GPIOC.CFGLR.modify(.{ .MODE2 = 0b11, .CNF2 = 0b01 });
+
+    PFIC.WAKEIP1.raw = 0x10000 & ~@as(u32, 0x3FF);
+    PFIC.SCTLR.raw |= (1 << 5);
+
+    while (true) {
+        gpio.write(.C, pin, 1);
+        delay(10_000);
+        gpio.write(.C, pin, 0);
+        delay(10_000);
+    }
+}

examples/wch/ch32h/src/v5f.zig

@@ -0,0 +1,36 @@
+const microzig = @import("microzig");
+
+pub const panic = microzig.panic;
+
+pub const std_options = microzig.std_options(.{});
+
+comptime {
+    _ = microzig.export_startup();
+}
+
+const RCC = microzig.chip.peripherals.RCC;
+const GPIOC = microzig.chip.peripherals.GPIOC;
+
+const gpio = microzig.hal.gpio;
+const clock = microzig.hal.clock;
+
+const pin: u4 = 3;
+
+fn delay(cycles: u32) void {
+    for (0..cycles) |_| {
+        asm volatile ("nop");
+    }
+}
+
+pub fn main() !void {
+    clock.enable_gpio(.C);
+
+    GPIOC.CFGLR.modify(.{ .MODE3 = 0b11, .CNF3 = 0b01 });
+
+    while (true) {
+        gpio.write(.C, pin, 1);
+        delay(20_000);
+        gpio.write(.C, pin, 0);
+        delay(20_000);
+    }
+}

port/wch/ch32h/build.zig

@@ -0,0 +1,126 @@
+const std = @import("std");
+const microzig = @import("microzig/build-internals");
+
+const Self = @This();
+
+const KiB = 1024;
+
+pub fn build(b: *std.Build) void {
+    _ = b;
+}
+
+pub const v5f_image_offset: u64 = 0x10000;
+pub const flash_size: u64 = 960 * KiB;
+
+chips: struct {
+    ch32h417_v3f: *const microzig.Target,
+    ch32h417_v5f: *const microzig.Target,
+},
+
+boards: struct {},
+
+merge_exe: *std.Build.Step.Compile,
+
+fn create_core(
+    dep: *std.Build.Dependency,
+    cpu_name: []const u8,
+    cpu_impl_file: std.Build.LazyPath,
+    memory_regions: []const microzig.MemoryRegion,
+) *microzig.Target {
+    const b = dep.builder;
+
+    const cpu_imports = b.allocator.dupe(std.Build.Module.Import, &.{
+        .{
+            .name = "riscv32-common",
+            .module = b.dependency("microzig/modules/riscv32-common", .{}).module("riscv32-common"),
+        },
+        .{
+            .name = "cpu_impl",
+            .module = std.Build.Module.create(b, .{ .root_source_file = cpu_impl_file }),
+        },
+    }) catch @panic("out of memory");
+
+    const core = b.allocator.create(microzig.Target) catch @panic("out of memory");
+    core.* = .{
+        .dep = dep,
+        .preferred_binary_format = .binary,
+        .zig_target = .{
+            .cpu_arch = .riscv32,
+            .cpu_model = .{ .explicit = &std.Target.riscv.cpu.generic_rv32 },
+            .cpu_features_add = cpu_common_features,
+            .os_tag = .freestanding,
+            .abi = .eabi,
+        },
+        .cpu = .{
+            .name = cpu_name,
+            .root_source_file = dep.path("src/cpus/main.zig"),
+            .imports = cpu_imports,
+        },
+        .chip = .{
+            .name = "CH32H417",
+            .url = "https://www.wch-ic.com/products/CH32H417.html",
+            .register_definition = .{ .svd = b.path("src/chips/ch32h417.svd") },
+            .memory_regions = memory_regions,
+        },
+        .hal = .{
+            .root_source_file = dep.path("src/hals/ch32h417.zig"),
+        },
+    };
+
+    return core;
+}
+
+const cpu_common_features = std.Target.riscv.featureSet(&.{
+    .i, .m, .a, .f, .c, .b, .xwchc, .zicsr, .zifencei,
+});
+
+pub fn init(dep: *std.Build.Dependency) ?Self {
+    const b = dep.builder;
+
+    const chip_v3f = create_core(dep, "qingkev3f", dep.path("src/cpus/qingkev3f.zig"), &.{
+        .{ .name = "FLASH", .tag = .flash, .offset = 0x0000_0000, .length = v5f_image_offset, .access = .rx },
+        .{ .name = "SRAM", .tag = .ram, .offset = 0x2010_0000, .length = 512 * KiB, .access = .rwx },
+    });
+    const chip_v5f = create_core(dep, "qingkev5f", dep.path("src/cpus/qingkev5f.zig"), &.{
+        .{ .name = "FLASH", .tag = .flash, .offset = v5f_image_offset, .length = flash_size - v5f_image_offset, .access = .rx },
+        .{ .name = "DTCM", .tag = .ram, .offset = 0x200C_0000, .length = 256 * KiB, .access = .rw },
+        .{ .name = "ITCM", .tag = .ram, .offset = 0x200A_0000, .length = 128 * KiB, .access = .rwx },
+    });
+
+    const merge_exe = b.addExecutable(.{
+        .name = "ch32h417-merge",
+        .root_module = b.addModule("ch32h417-merge", .{
+            .root_source_file = dep.path("tools/merge.zig"),
+            .target = b.graph.host,
+        }),
+    });
+
+    return .{
+        .chips = .{
+            .ch32h417_v3f = chip_v3f,
+            .ch32h417_v5f = chip_v5f,
+        },
+        .boards = .{},
+        .merge_exe = merge_exe,
+    };
+}
+
+pub fn merge(
+    self: @This(),
+    dep: *std.Build.Dependency,
+    v3f_elf: std.Build.LazyPath,
+    v5f_elf: std.Build.LazyPath,
+    merged_bin_path: []const u8,
+) std.Build.LazyPath {
+    const b = dep.builder;
+
+    const merge_step = b.addRunArtifact(self.merge_exe);
+
+    merge_step.addFileArg(v3f_elf);
+    merge_step.addFileArg(v5f_elf);
+    const merged_bin = merge_step.addOutputFileArg2(merged_bin_path, .{});
+
+    b.getInstallStep().dependOn(&merge_step.step);
+
+    return merged_bin;
+}

port/wch/ch32h/build.zig.zon

@@ -0,0 +1,16 @@
+.{
+    .name = .mz_port_wch_ch32h,
+    .version = "0.0.0",
+    .fingerprint = 0x731af18d92d6c086,
+    .dependencies = .{
+        .@"microzig/build-internals" = .{ .path = "../../../build-internals" },
+        .@"microzig/modules/riscv32-common" = .{ .path = "../../../modules/riscv32-common" },
+    },
+    .paths = .{
+        "README.md",
+        "build.zig",
+        "build.zig.zon",
+        "src",
+        "tools",
+    },
+}