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[dxsa][mlir] Port LIT tests from dxilconv #196

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f46e042
[dxsa][mlir] Port LIT tests from dxilconv
asavonic Jun 5, 2026
b75f7d3
Remove disclaimers, rename *.bin to *.shex
asavonic Jun 25, 2026
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75 changes: 75 additions & 0 deletions mlir/test/Target/DXSA/asm/call2.test
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// RUN: mlir-translate --import-dxsa-bin %S/inputs/call2.shex | FileCheck %s
// NOTE: Assertions have been autogenerated by utils/generate-test-checks.py


// CHECK-LABEL: dxsa.dcl_global_flags <refactoringAllowed>
// CHECK: dxsa.dcl_input_ps linear v<0, <x>>
// CHECK: dxsa.dcl_input_ps constant v<1, <x, y, z>>
// CHECK: dxsa.dcl_output o<0, <x>>
// CHECK: dxsa.dcl_temps 1
// CHECK: %[[INDEX_0:.*]] = dxsa.index.imm {imm = 0 : i32}
// CHECK: %[[OPERAND_0:.*]] = dxsa.operand %[[INDEX_0]] {mask = 112 : i32, num_components = 4 : i32, type = 0 : i32}
// CHECK: %[[INDEX_1:.*]] = dxsa.index.imm {imm = 1 : i32}
// CHECK: %[[OPERAND_1:.*]] = dxsa.operand %[[INDEX_1]] {num_components = 4 : i32, swizzle = dense<[0, 1, 2, 2]> : vector<4xi32>, type = 1 : i32}
// CHECK: dxsa.instruction "mov" %[[OPERAND_0]], %[[OPERAND_1]]
// CHECK: %[[INDEX_2:.*]] = dxsa.index.imm {imm = 0 : i32}
// CHECK: %[[OPERAND_2:.*]] = dxsa.operand %[[INDEX_2]] {num_components = 0 : i32, type = 10 : i32}
// CHECK: dxsa.instruction "call" %[[OPERAND_2]]
// CHECK: %[[INDEX_3:.*]] = dxsa.index.imm {imm = 0 : i32}
// CHECK: %[[OPERAND_3:.*]] = dxsa.operand %[[INDEX_3]] {num_components = 4 : i32, one = 0 : i32, type = 0 : i32}
// CHECK: %[[INDEX_4:.*]] = dxsa.index.imm {imm = 0 : i32}
// CHECK: %[[OPERAND_4:.*]] = dxsa.operand %[[INDEX_4]] {num_components = 0 : i32, type = 10 : i32}
// CHECK: dxsa.instruction "callc" %[[OPERAND_3]], %[[OPERAND_4]]
// CHECK: %[[INDEX_5:.*]] = dxsa.index.imm {imm = 1 : i32}
// CHECK: %[[OPERAND_5:.*]] = dxsa.operand %[[INDEX_5]] {num_components = 4 : i32, one = 0 : i32, type = 1 : i32}
// CHECK: dxsa.instruction "switch" %[[OPERAND_5]]
// CHECK: %[[OPERAND_6:.*]] = dxsa.operand.imm {imm = dense<1> : vector<1xi32>}
// CHECK: dxsa.instruction "case" %[[OPERAND_6]]
// CHECK: %[[INDEX_6:.*]] = dxsa.index.imm {imm = 2 : i32}
// CHECK: %[[OPERAND_7:.*]] = dxsa.operand %[[INDEX_6]] {num_components = 0 : i32, type = 10 : i32}
// CHECK: dxsa.instruction "call" %[[OPERAND_7]]
// CHECK: %[[INDEX_7:.*]] = dxsa.index.imm {imm = 0 : i32}
// CHECK: %[[OPERAND_8:.*]] = dxsa.operand %[[INDEX_7]] {num_components = 4 : i32, one = 1 : i32, type = 0 : i32}
// CHECK: %[[INDEX_8:.*]] = dxsa.index.imm {imm = 1 : i32}
// CHECK: %[[OPERAND_9:.*]] = dxsa.operand %[[INDEX_8]] {num_components = 0 : i32, type = 10 : i32}
// CHECK: dxsa.instruction "callc" %[[OPERAND_8]], %[[OPERAND_9]]
// CHECK: dxsa.instruction "break"
// CHECK: dxsa.instruction "default"
// CHECK: %[[INDEX_9:.*]] = dxsa.index.imm {imm = 0 : i32}
// CHECK: %[[OPERAND_10:.*]] = dxsa.operand %[[INDEX_9]] {num_components = 4 : i32, one = 2 : i32, type = 0 : i32}
// CHECK: %[[INDEX_10:.*]] = dxsa.index.imm {imm = 2 : i32}
// CHECK: %[[OPERAND_11:.*]] = dxsa.operand %[[INDEX_10]] {num_components = 0 : i32, type = 10 : i32}
// CHECK: dxsa.instruction "callc" %[[OPERAND_10]], %[[OPERAND_11]]
// CHECK: dxsa.instruction "break"
// CHECK: %[[OPERAND_12:.*]] = dxsa.operand.imm {imm = dense<2> : vector<1xi32>}
// CHECK: dxsa.instruction "case" %[[OPERAND_12]]
// CHECK: dxsa.instruction "break"
// CHECK: dxsa.instruction "endswitch"
// CHECK: dxsa.add o<0, <x>>, r<0, <x>>, l(0x3F800000)
// CHECK: dxsa.instruction "ret"
// CHECK: %[[INDEX_11:.*]] = dxsa.index.imm {imm = 0 : i32}
// CHECK: %[[OPERAND_13:.*]] = dxsa.operand %[[INDEX_11]] {num_components = 0 : i32, type = 10 : i32}
// CHECK: dxsa.instruction "label" %[[OPERAND_13]]
// CHECK: %[[INDEX_12:.*]] = dxsa.index.imm {imm = 0 : i32}
// CHECK: %[[OPERAND_14:.*]] = dxsa.operand %[[INDEX_12]] {mask = 16 : i32, num_components = 4 : i32, type = 0 : i32}
// CHECK: %[[OPERAND_15:.*]] = dxsa.operand.imm {imm = dense<1084227584> : vector<1xi32>}
// CHECK: dxsa.instruction "mov" %[[OPERAND_14]], %[[OPERAND_15]]
// CHECK: dxsa.instruction "ret"
// CHECK: %[[INDEX_13:.*]] = dxsa.index.imm {imm = 1 : i32}
// CHECK: %[[OPERAND_16:.*]] = dxsa.operand %[[INDEX_13]] {num_components = 0 : i32, type = 10 : i32}
// CHECK: dxsa.instruction "label" %[[OPERAND_16]]
// CHECK: %[[INDEX_14:.*]] = dxsa.index.imm {imm = 0 : i32}
// CHECK: %[[OPERAND_17:.*]] = dxsa.operand %[[INDEX_14]] {mask = 16 : i32, num_components = 4 : i32, type = 0 : i32}
// CHECK: %[[INDEX_15:.*]] = dxsa.index.imm {imm = 0 : i32}
// CHECK: %[[OPERAND_18:.*]] = dxsa.operand %[[INDEX_15]] {num_components = 4 : i32, one = 0 : i32, type = 1 : i32}
// CHECK: dxsa.instruction "mov" %[[OPERAND_17]], %[[OPERAND_18]]
// CHECK: dxsa.instruction "ret"
// CHECK: %[[INDEX_16:.*]] = dxsa.index.imm {imm = 2 : i32}
// CHECK: %[[OPERAND_19:.*]] = dxsa.operand %[[INDEX_16]] {num_components = 0 : i32, type = 10 : i32}
// CHECK: dxsa.instruction "label" %[[OPERAND_19]]
// CHECK: %[[INDEX_17:.*]] = dxsa.index.imm {imm = 0 : i32}
// CHECK: %[[OPERAND_20:.*]] = dxsa.operand %[[INDEX_17]] {mask = 16 : i32, num_components = 4 : i32, type = 0 : i32}
// CHECK: %[[OPERAND_21:.*]] = dxsa.operand.imm {imm = dense<1077936128> : vector<1xi32>}
// CHECK: dxsa.instruction "mov" %[[OPERAND_20]], %[[OPERAND_21]]
// CHECK: dxsa.instruction "ret"

68 changes: 68 additions & 0 deletions mlir/test/Target/DXSA/asm/cs3.test
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// RUN: mlir-translate --import-dxsa-bin %S/inputs/cs3.shex | FileCheck %s
// NOTE: Assertions have been autogenerated by utils/generate-test-checks.py


// CHECK-LABEL: dxsa.dcl_global_flags <refactoringAllowed>
// CHECK: dxsa.dcl_constant_buffer <id = 0, size = 1>, <immediateIndexed>
// CHECK: dxsa.dcl_input vThreadIDInGroup<<x, y, z>>
// CHECK: dxsa.dcl_temps 3
// CHECK: dxsa.dcl_tgsm_raw g<0>, 1024
// CHECK: dxsa.dcl_thread_group <x = 4, y = 2, z = 3>
// CHECK: dxsa.ishl r<0, <x>>, vThreadIDInGroup<<z>>, l(0x2)
// CHECK: %[[INDEX_0:.*]] = dxsa.index.imm {imm = 0 : i32}
// CHECK: %[[OPERAND_0:.*]] = dxsa.operand %[[INDEX_0]] {mask = 48 : i32, num_components = 4 : i32, type = 31 : i32}
// CHECK: %[[INDEX_1:.*]] = dxsa.index.imm {imm = 0 : i32}
// CHECK: %[[OPERAND_1:.*]] = dxsa.operand %[[INDEX_1]] {num_components = 4 : i32, one = 0 : i32, type = 0 : i32}
// CHECK: %[[INDEX_2:.*]] = dxsa.index.imm {imm = 0 : i32}
// CHECK: %[[INDEX_3:.*]] = dxsa.index.imm {imm = 0 : i32}
// CHECK: %[[OPERAND_2:.*]] = dxsa.operand %[[INDEX_2]], %[[INDEX_3]] {num_components = 4 : i32, swizzle = dense<[3, 2, 1, 0]> : vector<4xi32>, type = 8 : i32}
// CHECK: dxsa.instruction "store_raw" %[[OPERAND_0]], %[[OPERAND_1]], %[[OPERAND_2]]
// CHECK: dxsa.instruction "sync"
// CHECK: dxsa.instruction "sync"
// CHECK: dxsa.instruction "sync"
// CHECK: dxsa.instruction "sync"
// CHECK: dxsa.instruction "sync"
// CHECK: dxsa.instruction "sync"
// CHECK: dxsa.instruction "sync"
// CHECK: dxsa.instruction "sync"
// CHECK: dxsa.instruction "sync"
// CHECK: dxsa.instruction "sync"
// CHECK: %[[INDEX_4:.*]] = dxsa.index.imm {imm = 0 : i32}
// CHECK: %[[OPERAND_3:.*]] = dxsa.operand %[[INDEX_4]] {mask = 80 : i32, num_components = 4 : i32, type = 0 : i32}
// CHECK: %[[INDEX_5:.*]] = dxsa.index.imm {imm = 0 : i32}
// CHECK: %[[OPERAND_4:.*]] = dxsa.operand %[[INDEX_5]] {num_components = 4 : i32, one = 0 : i32, type = 0 : i32}
// CHECK: %[[INDEX_6:.*]] = dxsa.index.imm {imm = 0 : i32}
// CHECK: %[[OPERAND_5:.*]] = dxsa.operand %[[INDEX_6]] {num_components = 4 : i32, swizzle = dense<[2, 0, 3, 1]> : vector<4xi32>, type = 31 : i32}
// CHECK: dxsa.instruction "ld_raw" %[[OPERAND_3]], %[[OPERAND_4]], %[[OPERAND_5]]
// CHECK: %[[INDEX_7:.*]] = dxsa.index.imm {imm = 2 : i32}
// CHECK: %[[OPERAND_6:.*]] = dxsa.operand %[[INDEX_7]] {mask = 16 : i32, num_components = 4 : i32, type = 0 : i32}
// CHECK: %[[INDEX_8:.*]] = dxsa.index.imm {imm = 0 : i32}
// CHECK: %[[OPERAND_7:.*]] = dxsa.operand %[[INDEX_8]] {num_components = 0 : i32, type = 31 : i32}
// CHECK: %[[INDEX_9:.*]] = dxsa.index.imm {imm = 1 : i32}
// CHECK: %[[OPERAND_8:.*]] = dxsa.operand %[[INDEX_9]] {num_components = 4 : i32, swizzle = dense<[0, 1, 0, 0]> : vector<4xi32>, type = 0 : i32}
// CHECK: %[[OPERAND_9:.*]] = dxsa.operand {num_components = 4 : i32, one = 0 : i32, type = 34 : i32}
// CHECK: dxsa.instruction "imm_atomic_iadd" %[[OPERAND_6]], %[[OPERAND_7]], %[[OPERAND_8]], %[[OPERAND_9]]
// CHECK: %[[INDEX_10:.*]] = dxsa.index.imm {imm = 0 : i32}
// CHECK: %[[OPERAND_10:.*]] = dxsa.operand %[[INDEX_10]] {num_components = 0 : i32, type = 31 : i32}
// CHECK: %[[INDEX_11:.*]] = dxsa.index.imm {imm = 1 : i32}
// CHECK: %[[OPERAND_11:.*]] = dxsa.operand %[[INDEX_11]] {num_components = 4 : i32, swizzle = dense<[0, 1, 0, 0]> : vector<4xi32>, type = 0 : i32}
// CHECK: %[[OPERAND_12:.*]] = dxsa.operand {num_components = 4 : i32, one = 0 : i32, type = 34 : i32}
// CHECK: dxsa.instruction "atomic_or" %[[OPERAND_10]], %[[OPERAND_11]], %[[OPERAND_12]]
// CHECK: %[[INDEX_12:.*]] = dxsa.index.imm {imm = 0 : i32}
// CHECK: %[[OPERAND_13:.*]] = dxsa.operand %[[INDEX_12]] {num_components = 0 : i32, type = 31 : i32}
// CHECK: %[[INDEX_13:.*]] = dxsa.index.imm {imm = 1 : i32}
// CHECK: %[[OPERAND_14:.*]] = dxsa.operand %[[INDEX_13]] {num_components = 4 : i32, swizzle = dense<[0, 1, 0, 0]> : vector<4xi32>, type = 0 : i32}
// CHECK: %[[OPERAND_15:.*]] = dxsa.operand {num_components = 4 : i32, one = 1 : i32, type = 34 : i32}
// CHECK: %[[OPERAND_16:.*]] = dxsa.operand {num_components = 4 : i32, one = 0 : i32, type = 34 : i32}
// CHECK: dxsa.instruction "atomic_cmp_store" %[[OPERAND_13]], %[[OPERAND_14]], %[[OPERAND_15]], %[[OPERAND_16]]
// CHECK: %[[INDEX_14:.*]] = dxsa.index.imm {imm = 1 : i32}
// CHECK: %[[OPERAND_17:.*]] = dxsa.operand %[[INDEX_14]] {mask = 16 : i32, num_components = 4 : i32, type = 0 : i32}
// CHECK: %[[INDEX_15:.*]] = dxsa.index.imm {imm = 0 : i32}
// CHECK: %[[OPERAND_18:.*]] = dxsa.operand %[[INDEX_15]] {num_components = 0 : i32, type = 31 : i32}
// CHECK: %[[INDEX_16:.*]] = dxsa.index.imm {imm = 1 : i32}
// CHECK: %[[OPERAND_19:.*]] = dxsa.operand %[[INDEX_16]] {num_components = 4 : i32, swizzle = dense<[0, 1, 0, 0]> : vector<4xi32>, type = 0 : i32}
// CHECK: %[[OPERAND_20:.*]] = dxsa.operand {num_components = 4 : i32, one = 1 : i32, type = 34 : i32}
// CHECK: %[[OPERAND_21:.*]] = dxsa.operand {num_components = 4 : i32, one = 0 : i32, type = 34 : i32}
// CHECK: dxsa.instruction "imm_atomic_cmp_exch" %[[OPERAND_17]], %[[OPERAND_18]], %[[OPERAND_19]], %[[OPERAND_20]], %[[OPERAND_21]]
// CHECK: dxsa.instruction "ret"

21 changes: 21 additions & 0 deletions mlir/test/Target/DXSA/asm/cyclecounter.test
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// RUN: mlir-translate --import-dxsa-bin %S/inputs/cyclecounter.shex | FileCheck %s
// NOTE: Assertions have been autogenerated by utils/generate-test-checks.py


// CHECK-LABEL: dxsa.dcl_temps 1
// CHECK: dxsa.dcl_output o<0>
// CHECK: dxsa.dcl_input cycleCounter<<x>>
// CHECK: %[[INDEX_0:.*]] = dxsa.index.imm {imm = 0 : i32}
// CHECK: %[[OPERAND_0:.*]] = dxsa.operand %[[INDEX_0]] {mask = 240 : i32, num_components = 4 : i32, type = 0 : i32}
// CHECK: %[[OPERAND_1:.*]] = dxsa.operand.imm {imm = dense<0> : vector<1xi32>}
// CHECK: dxsa.instruction "mov" %[[OPERAND_0]], %[[OPERAND_1]]
// CHECK: %[[INDEX_1:.*]] = dxsa.index.imm {imm = 0 : i32}
// CHECK: %[[OPERAND_2:.*]] = dxsa.operand %[[INDEX_1]] {mask = 64 : i32, num_components = 4 : i32, type = 0 : i32}
// CHECK: %[[OPERAND_3:.*]] = dxsa.operand {num_components = 4 : i32, one = 0 : i32, type = 40 : i32}
// CHECK: dxsa.instruction "mov" %[[OPERAND_2]], %[[OPERAND_3]]
// CHECK: %[[INDEX_2:.*]] = dxsa.index.imm {imm = 0 : i32}
// CHECK: %[[OPERAND_4:.*]] = dxsa.operand %[[INDEX_2]] {mask = 240 : i32, num_components = 4 : i32, type = 2 : i32}
// CHECK: %[[INDEX_3:.*]] = dxsa.index.imm {imm = 0 : i32}
// CHECK: %[[OPERAND_5:.*]] = dxsa.operand %[[INDEX_3]] {num_components = 4 : i32, swizzle = dense<[0, 1, 2, 3]> : vector<4xi32>, type = 0 : i32}
// CHECK: dxsa.instruction "mov" %[[OPERAND_4]], %[[OPERAND_5]]

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