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1. DDR2_Controller DDR2_Controller Public

   DDR2 memory controller written in Verilog

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2. brokenBench brokenBench Public

   Systemverilog and UVM exercises inspired by ziglings

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3. nvim nvim Public

   NeoVim configuration files

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4. Interrupt_Controller Interrupt_Controller Public

   An 8 input interrupt controller written in Verilog.

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5. uvmBasics uvmBasics Public

   Basics of UVM via an APB slave

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6. alu_tb alu_tb Public

   Basic ALU testbench written in UVM for experiments

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