[C++] Add RISC-V Vector (RVV) support and dynamic dispatch by zhanchangbao-sanechips · Pull Request #51340 · apache/arrow

zhanchangbao-sanechips · 2026-09-15T08:11:20Z

Rationale for this change

Add initial RISC-V Vector (RVV) support to Arrow C++. This mirrors the existing SVE dynamic-dispatch support on AArch64, paves the way for upcoming RVV‑related optimizations, providing:

Runtime CPU capability detection for RVV and vector length (VLEN = 128/256/512 bits) on riscv64 Linux.
A DispatchLevel::RVV entry so RVV-optimized kernels can be compiled with -march=rv64gcv and selected at runtime.
CMake plumbing: ARROW_SIMD_LEVEL=RVV for compile-time RVV and ARROW_RUNTIME_SIMD_LEVEL=RVV|MAX for runtime dispatch, with graceful fallback (NONE) when the toolchain lacks RVV support.

What changes are included

cpp/src/arrow/util/cpu_info.h/.cc: add RVV/RVV128/RVV256/RVV512 hardware flags; detect V extension via getauxval(AT_HWCAP) and VLEN via the vlenb CSR on Linux/riscv64.
cpp/src/arrow/util/dispatch_internal.h: add DispatchLevel::RVV and ARROW_DISPATCH_TARGET_RVV macro, wired into
DynamicDispatch::IsSupported.
cpp/cmake_modules/DefineOptions.cmake: add RVV to ARROW_SIMD_LEVEL and ARROW_RUNTIME_SIMD_LEVEL option lists.
cpp/cmake_modules/SetupCxxFlags.cmake: riscv64 handling — check -march=rv64gcv, set ARROW_HAVE_RVV (compile-time) / ARROW_HAVE_RUNTIME_RVV (runtime), default ARROW_SIMD_LEVEL=NONE.
cpp/src/arrow/util/simd.h: include <riscv_vector.h> when RVV is enabled.
cpp/src/arrow/util/io_util_test.cc: extend CpuInfo.Basic to assert RVV detection and a matching VLEN flag.

Are these changes tested?

Yes. Built and unit-tested on Sophgo SG2044 board with GCC 14.3.1.
Built with --DARROW_SIMD_LEVEL=RVV -DARROW_RUNTIME_SIMD_LEVEL=RVV, config passed.
All unittest passed.

Are there any user-facing changes?

No user-facing API changes; adds build-time options ARROW_SIMD_LEVEL=RVV and ARROW_RUNTIME_SIMD_LEVEL=RVV|MAX for riscv64.
GitHub Issue: #51334

…patch Adds support for the RISC‑V Vector (RVV) extension in the C++ runtime SIMD dispatch machinery, analogous to the existing NEON/SVE support for AArch64, and paves the way for upcoming RVV‑related optimizations.

github-actions · 2026-09-15T08:12:03Z

Thanks for opening a pull request!

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If this is not a minor PR. Could you open an issue for this pull request on GitHub? https://github.com/apache/arrow/issues/new/choose

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Then could you also rename the pull request title in the following format?

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See also:

pitrou · 2026-09-15T08:58:19Z

Hi @zhanchangbao-sanechips , as you probably have in seen the SVE-handling code above your changes, we are using xsimd for instruction set detection. Can we ask you to do that for RVV too?

(you may need to contribute the required additions to xsimd if not already available)

zhanchangbao-sanechips · 2026-09-15T09:12:57Z

Hi @zhanchangbao-sanechips , as you probably have in seen the SVE-handling code above your changes, we are using xsimd for instruction set detection. Can we ask you to do that for RVV too?

(you may need to contribute the required additions to xsimd if not already available)

I referred to my previous PR: apache/orc#2639. I will follow the same approach as the SVE handling and use xsimd for RVV instruction set detection.

…patch Use xsimd's cpu_features for RVV detection in cpu_info.cc, mirroring the existing SVE handling. The bundled xsimd 14.2.0 already provides rvv()/rvv_size_bytes().

pitrou · 2026-09-21T09:45:06Z

@zhanchangbao-sanechips Is this ready for review?

zhanchangbao-sanechips · 2026-09-21T10:46:11Z

@zhanchangbao-sanechips Is this ready for review?

Not ready yet. Some CI failures are unresolved. I was tied up with other work these days.

Fix trailing whitespace in DefineOptions.cmake and reformat the CpuInfo RVV test in io_util_test.cc to satisfy pre-commit (clang-format / cmake-format).

zhanchangbao-sanechips · 2026-10-26T06:55:00Z

@zhanchangbao-sanechips Is this ready for review?

I've been busy with other matters recently, as well as preparing for the ORC port to RISC-V and its performance optimization for a talk at this year's RISC-V Summit, which caused some delays. I'm now back to the work on porting and optimizing Arrow on RISC-V. Please take some time to review it when you can. Thank you.

pitrou · 2026-10-26T09:40:22Z

 #endif

+#if defined(ARROW_HAVE_RVV) || defined(ARROW_HAVE_RUNTIME_RVV)
+#  define ARROW_DISPATCH_TARGET_RVV(func)      \


I don't think that is right, we want per-vector width macros just like for SVE.

I don't think that is right, we want per-vector width macros just like for SVE.

Thank you for your review,you're right, and I've split RVV into per-vector-width macros to match SVE.

pitrou · 2026-10-26T09:44:18Z

+elseif(ARROW_CPU_FLAG STREQUAL "riscv64")
+  set(ARROW_RVV_MARCH "rv64gcv")
+  check_cxx_compiler_flag("-march=${ARROW_RVV_MARCH}" CXX_SUPPORTS_RVV)
+  if(CXX_SUPPORTS_RVV AND ARROW_RUNTIME_SIMD_LEVEL MATCHES "^(RVV|MAX)$")


Just like SVE, we probably want RVV128 etc.

pitrou · 2026-10-26T09:44:49Z

                       "SVE128" # fixed size SVE
                       "SVE256" # "
                       "SVE512" # "
+                       "RVV"


Just like SVE, we probably want RVV128 etc.

Split the single RVV SIMD dispatch target into per-vector-width RVV128/RVV256/RVV512, mirroring the existing SVE handling.

pitrou

Looks mostly good to me now, a couple suggestions.

pitrou · 2026-10-27T09:30:02Z

+    string(REGEX MATCH "[0-9]+" RVV_VECTOR_BITS ${ARROW_SIMD_LEVEL})
+    if(RVV_VECTOR_BITS)
+      set(ARROW_HAVE_RVV${RVV_VECTOR_BITS} ON)
+      add_definitions(-DARROW_HAVE_RVV${RVV_VECTOR_BITS})


Shouldn't we also enable a compiler option for the given vector size, as in SVE above?

pitrou · 2026-10-27T09:30:22Z

+      set(ARROW_HAVE_RVV${RVV_VECTOR_BITS} ON)
+      add_definitions(-DARROW_HAVE_RVV${RVV_VECTOR_BITS})
+    else()
+      set(ARROW_HAVE_RVV ON)


Perhaps call it ARROW_HAVE_RVV_SIZELESS just like SVE above?

pitrou · 2026-10-27T09:32:39Z

    message(WARNING "ARROW_SIMD_LEVEL=${ARROW_SIMD_LEVEL} not supported by Arm.")
  endif()
 endif()
+if(ARROW_CPU_FLAG STREQUAL "riscv64")


Nit: add line break as above.

Suggested change

if(ARROW_CPU_FLAG STREQUAL "riscv64")

if(ARROW_CPU_FLAG STREQUAL "riscv64")

zhanchangbao-sanechips added 2 commits September 15, 2026 11:12

Merge branch 'apache:main' into rvvopt

2490175

zhanchangbao-sanechips requested a review from pitrou as a code owner September 15, 2026 08:11

github-actions Bot added the awaiting review Awaiting review label Sep 15, 2026

github-actions Bot marked this pull request as draft September 15, 2026 08:12

github-actions Bot added the Component: C++ label Sep 15, 2026

zhanchangbao-sanechips marked this pull request as ready for review September 15, 2026 08:42

apacheGH-51334: [C++] Add RISC-V Vector (RVV) support and dynamic dis…

6dae1b4

…patch Use xsimd's cpu_features for RVV detection in cpu_info.cc, mirroring the existing SVE handling. The bundled xsimd 14.2.0 already provides rvv()/rvv_size_bytes().

zhanchangbao-sanechips added 2 commits September 28, 2026 09:20

Merge branch 'apache:main' into rvvopt

4fffad3

Merge branch 'apache:main' into rvvopt

1409867

zhanchangbao-sanechips marked this pull request as draft September 28, 2026 06:23

zhanchangbao-sanechips added 2 commits October 26, 2026 14:23

Merge branch 'apache:main' into rvvopt

1577b85

apacheGH-51334: [C++] Fix RVV code formatting

2a9a1ec

Fix trailing whitespace in DefineOptions.cmake and reformat the CpuInfo RVV test in io_util_test.cc to satisfy pre-commit (clang-format / cmake-format).

zhanchangbao-sanechips marked this pull request as ready for review October 26, 2026 06:51

pitrou reviewed Oct 26, 2026

View reviewed changes

apacheGH-51334: [C++] Use per-vector-width RVV dispatch macros

dc8c919

Split the single RVV SIMD dispatch target into per-vector-width RVV128/RVV256/RVV512, mirroring the existing SVE handling.

pitrou reviewed Oct 27, 2026

View reviewed changes

github-actions Bot added awaiting committer review Awaiting committer review and removed awaiting review Awaiting review labels Oct 27, 2026

	if(ARROW_CPU_FLAG STREQUAL "riscv64")

	if(ARROW_CPU_FLAG STREQUAL "riscv64")

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