[jschmied]

What this changes

docs/recipes/qwen3.8-27b.md only, two places:

• The intro said the 27B "has no CUDA backend yet". Since 1.1.0 (Windows: the native CUDA server, and Qwen3.5-2B and Qwen3.8-27B on CUDA #836, qwen3_5 cuda: mixed-width MLX checkpoints, 2 to 8 bits in groups of 64 #849, qwen3_5 cuda: 2, 3, 5 and 6-bit tiles of their own width and a prompt GEMM for them (27B oQ2 on 16 GB) #859, qwen3_5 cuda: --kv-cache fp8, e4m3 attention caches with a scale a row #886) the native engine serves the MLX affine checkpoints on CUDA (2, 3, 4, 5, 6 and 8 bits in groups of 64) from zig/src/families/qwen3_5/cuda_*.zig, with DFlash2 drafts and --kv-cache fp8. The intro now says that, and that it reads no NVFP4 or EXL3 checkpoint yet.
• The ## CUDA section says the 27B "serves NVFP4 and EXL3 checkpoints" on CUDA. That's the Python engine (0.6.6). The page already says further up that the rest of it describes the Python engine, but a reader who jumps to ## CUDA doesn't see that. A two-line note at the top of the section now says it's the Python engine's, and that neither reader is ported to the native engine yet (1.1.0 carries EXL3 checkpoints on the native engine (tracker) #832's shared EXL3 module, but the 27B doesn't read EXL3 through it yet).

Documentation only: no source, tests, fixtures or generated files change.

Receipt

• Environment: TensorFold d1018b31 (main) plus this branch.
• Checked against the source at d1018b31: a non-MLX 27B checkpoint gets UnsupportedQwenQuantization from zig/src/families/qwen3_5/cuda_geometry.zig (the native CUDA reader admits MLX affine tables in groups of 64 only). nvidia/Qwen3.8-27B-NVFP4 fails with it on a GB10.
• Not run: nothing to run, documentation only.

Gotchas

• Once Proposal: Qwen3.8-27B ModelOpt NVFP4 checkpoints on the native CUDA engine (both precision modes) #1144's PR lands, the intro's "reads no NVFP4 checkpoint yet" becomes stale. That PR should update the line, or this one can if it lands second.

[ashhart]

Thank you. This is on main as d9107c1, with your authorship: the 27B recipe now says the native CUDA engine serves the MLX affine checkpoints (2 to 8 bits in groups of 64) with DFlash2 drafts and --kv-cache fp8, reads no NVFP4 or EXL3 checkpoint yet, and that its CUDA section describes the Python engine. It ships with the next release. Closing as landed.

- Synthema, Ash's AI Assistant.