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CUDA: Ampere sm_80 in the release fatbins, with the ModelOpt floor named at its refusal - #846
liumorrisclaw wants to merge 3 commits into
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…med at its refusal Release fatbins build and check sm_80 alongside sm_86, sm_120 and sm_121, so the A100 and its Ampere peers load the 4-bit path. A ModelOpt checkpoint at the FP8/NVFP4 floor is refused by name now: the card, its sm and the cluster reason, from one tested helper (ashhart#840, the native port of ashhart#464).
…nts refuse anyway The lanes half drives the decode lane matmul the way the engine does not: with no reduce scratch, which only a cluster card serves. Below sm_90 the checkpoint path is refused at load, so the check says SKIP there instead of tripping the reduce launch on an unreachable configuration.
Device gate on Ampere sm_80: greenMachine: 4x NVIDIA CMP 170HX 64 GB (GA100, sm_80, 74 SMs), driver 610.43.03, CUDA toolkit 13.3 (nvcc V13.3.73), Linux x86_64, Zig 0.17.0. Branch at 1c8b571.
One commit lands for this: 1c8b571 makes |
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Hello @liumorrisclaw, Thank you for the sm_80 device gate on the GA100: all 34 kernels building for compute_80, every release fatbin carrying the four images, and 16/16 kernel checks on the card with glue byte-equal to the host references. That meets the bar the tracker set for this row. One thing is left. packaging/README.md:36-37 still builds the release fatbins with -Dsm=86,120,121 and says they carry three images. release_sms is now 80,86,120,121, and dist refuses a file without the sm_80 image. Please update those two lines, or we will when it lands. Before it lands we also build the sm_80 fatbins here and run the kernel contract's limits for sm_80. Thank you again. |
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Done — packaging/README.md now builds the release fatbins with |
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What this changes
Carries the Ampere sm_80 row of #840 (my #464) into the native engine.
zig/build/cuda.zig:release_smsgains sm_80, so every release fatbin carries an sm_80 SASS image and thecheck-fatbinsrelease gate demands one (-Dsm=80,86,120,121). The kernels' thread-block-cluster paths are already__CUDA_ARCH__ >= 900-guarded with__trap()fallbacks (qmm_group, qmmf, lane_gemv, probe), and the FP8 and NVFP4 experts form their products as bf16 MMA pairs, so the .cu sources build for compute_80 unchanged.modeloptRefusal(capability), and the native server renders a refusal at that floor by name: the card, its sm and the reason (decode's split-K sums meet in a thread-block cluster). Every card below sm_89 — the Ampere ones now admitted included — traps there instead of seeing the bare error name. The floor itself stays where it was: the decode lane matmul sizes no reduce scratch without a cluster, so admitting Ampere never loosens it (as build: admit Ampere (sm_80) via TENSORFOLD_MIN_CAPABILITY, keep NVFP4/cluster floors #464 kept the FP8 floor pinned).Receipt
zig build test-cuda-host: passes on Zig 0.17.0 (4 consecutive runs; one test-binary failure on the very first full build did not reproduce) (includes the new floor test and check_fatbins' fatbin-set test).python3 tools/zig/lean_check.py: 1375 files, 527 problems, the baseline's own count; no additions.