gpio: phytium: update phytium gpio controller driver support to 6.6.0.4#1750
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gpio: phytium: update phytium gpio controller driver support to 6.6.0.4#1750xiaqian1486 wants to merge 4 commits into
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Pull request overview
This PR updates and extends Phytium (and related Zhaoxin) platform support against the 6.6.0.4 kernel baseline, spanning GPIO suspend/resume handling as well as several adjacent subsystems (ASoC, PCI endpoint/hotplug, perf PMUs, devfreq, DT bindings, and maintenance metadata).
Changes:
- GPIO: rebind chained parent IRQ handler after S4 resume and related driver adjustments.
- Audio: improve ASoC machine/DP link identification and error handling; add new sysfs control; update Phytium codec handling and ES8388 init.
- PCI/perf/devfreq/platform: add Phytium-specific PCI EPC DMA hooks + DT binding/MAINTAINERS updates; extend HDA handling for Zhaoxin; add/update Phytium perf PMUs and devfreq drivers; various cleanups/guards (e.g., XFS trace compat guard).
Reviewed changes
Copilot reviewed 52 out of 52 changed files in this pull request and generated 21 comments.
Show a summary per file
| File | Description |
|---|---|
| sound/soc/phytium/pmdk_dp.c | Propagates jack setup return value; assigns DAI link IDs for DP audio links. |
| sound/soc/phytium/phytium-machine-v2.c | Adds DAI link ID for the V2 machine link. |
| sound/soc/phytium/phytium-i2s-v2.c | Updates version; sets component options; adds sysfs control attribute. |
| sound/soc/phytium/Kconfig | Adds ARCH_PHYTIUM dependency and formats help text consistently. |
| sound/soc/codecs/phytium-codec-v2.h | Introduces a codec status enum for clearer error reporting. |
| sound/soc/codecs/phytium-codec-v2.c | Reworks status handling; clears shared command structure at key transitions; stores channel count in priv. |
| sound/soc/codecs/Kconfig | Adds ARCH_PHYTIUM dependency for Phytium codec v2. |
| sound/soc/codecs/es8388.c | Updates version and adds error handling during component probe initialization. |
| sound/pci/hda/patch_hdmi.c | Adds additional HDMI/DP codec IDs mapped to gf HDMI patch handler. |
| sound/pci/hda/hda_intel.c | Extends VIA-specific position fix / snoop behavior and adds new PCI IDs for Zhaoxin HDMI controllers. |
| drivers/gpio/gpio-phytium-platform.c | Rebinds chained handler on resume via helper; adjusts suspend/resume flow. |
| include/linux/pci-epc.h | Adds Phytium-specific EPC DMA ops and exported APIs under CONFIG_ARCH_PHYTIUM. |
| drivers/pci/endpoint/pci-epc-core.c | Implements/exports Phytium-specific EPC DMA entry points. |
| drivers/pci/endpoint/pci-ep-cfs.c | Adds configfs exposure related to EPC function mapping. |
| drivers/pci/controller/pcie-phytium-ep.c | Updates Phytium PCIe EP controller behavior (BAR/DMA related paths). |
| Documentation/devicetree/bindings/pci/phytium,pe2201-pcie-ep.yaml | Adds DT binding for a Phytium PCIe EP device. |
| drivers/pci/hotplug/pciehp_hpc.c | Adds Phytium-specific link-status override logic for hotplug. |
| drivers/devfreq/phytium_noc.c | Adds/updates Phytium NoC devfreq driver functionality and PM behavior. |
| drivers/devfreq/phytium_dmu.c | Adds/updates Phytium DMU devfreq driver (incl. SPDX tag). |
| drivers/perf/phytium/phytium_ddr_pmu.c | Adds Phytium DDR PMU driver for perf. |
| drivers/perf/phytium/phytium_msi_pmu.c | Adds Phytium MSI PMU driver for perf (counter handling/overflow paths). |
| drivers/perf/phytium/phytium_pcie_link_pmu.c | Adds Phytium PCIe link PMU driver for perf (event/counter reads). |
| drivers/pinctrl/zhaoxin/pinctrl-zhaoxin.h | Adds a helper macro for socket-specific pin definitions. |
| drivers/pinctrl/zhaoxin/pinctrl-kh50000.c | Refactors KH50000 pin definitions using the new socket macro; adjusts resource/init paths. |
| fs/xfs/xfs_trace.h | Adjusts tracepoint definitions/guards (e.g., compat-ioctl tracepoint under CONFIG_COMPAT). |
| MAINTAINERS | Extends Phytium maintainer file globs to cover additional bindings and drivers. |
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| p = kmalloc(size, GFP_KERNEL); | ||
| if (p == NULL) | ||
| return -EINVAL; | ||
| strscpy(p, buf, sizeof(p)); | ||
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| token = strsep(&p, " "); | ||
| if (!token) { | ||
| ret = -EINVAL; | ||
| goto error; | ||
| } | ||
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| ret = kstrtol(token, 0, &value); | ||
| if (ret) | ||
| goto error; | ||
| loc = (u8)value; | ||
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| if (loc == 1) { | ||
| //Enable I2S and DMA | ||
| phyt_writel_reg(priv->dma_reg_base, PHYTIUM_DMA_CTL, 1); | ||
| phyt_writel_reg(priv->regfile_base, PHYTIUM_REGFILE_ITER, TX_EN); | ||
| } else if (loc == 0) { | ||
| //Disable I2S and DMA | ||
| phyt_writel_reg(priv->regfile_base, PHYTIUM_REGFILE_ITER, TX_DIS); | ||
| phyt_writel_reg(priv->dma_reg_base, PHYTIUM_DMA_CTL, 0); | ||
| } | ||
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| kfree(p); | ||
| return size; | ||
| error: | ||
| kfree(p); | ||
| return ret; |
| struct device; | ||
| struct zhaoxin_pinctrl; | ||
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| #define SOCKET_PINCTRL_PIN(sock, a, b) PINCTRL_PIN(a, b"_"#sock) |
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| res_pmio = platform_get_resource(pdev, IORESOURCE_IO, 0); | ||
| if (!res_pmio) { | ||
| dev_err(&pdev->dev, "can't fetch device pmio resource info\n"); | ||
| return; | ||
| } | ||
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| if (!request_region(res_pmio->start, resource_size(res_pmio), pdev->name)) { | ||
| dev_err(&pdev->dev, "can't request region\n"); | ||
| return; | ||
| } |
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| if (IS_ERR(epc)) | ||
| return -EINVAL; | ||
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| if (!epc->ops->start_dma) | ||
| return 0; |
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| j = event_type * 5; | ||
| for (i = 0; i < 4; i++) { | ||
| reqid_val = readl(misc_pmu->base + misc_reqid_record_reg_offset[j]); | ||
| req_cnt = readl(misc_pmu->base + misc_counter_reg_offset[j]); | ||
| record_mov_bits = (i % 2) * 16; | ||
| reqid[i] = (u32)(0xFFFF & (reqid_val >> record_mov_bits)); | ||
| cnt_mov_bits = i * 4; | ||
| reqcnt[i] = (u32)(0xF & (req_cnt >> cnt_mov_bits)); | ||
| dev_info(misc_pmu->dev, "reqid(%u),cnt=%u\n", reqid[i], reqcnt[i]); | ||
| j += 1; |
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| if ((event->attr.config & PHYTIUM_MSI_PMU_EVENT_MASK) > PHYTIUM_MISC_MAX_COUNTERS) | ||
| return -EINVAL; | ||
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| if (misc_pmu->on_cpu == -1) | ||
| return -EINVAL; | ||
|
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| static irqreturn_t phytium_msi_pmu_overflow_handler(int irq, void *dev_id) | ||
| { | ||
| struct phytium_msi_pmu *misc_pmu = dev_id; | ||
| struct perf_event *event; | ||
| unsigned long now_state, stop_state; | ||
| int idx, event_type; | ||
| unsigned long dev_stop_mask, dev_mask; | ||
| unsigned long *used_mask = misc_pmu->pmu_events.used_mask; | ||
| u32 opt_val = 0; | ||
| int event_added = bitmap_weight(used_mask, PHYTIUM_MISC_MAX_COUNTERS); | ||
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| // 0:pcu 1:pxu 2:peu | ||
| now_state = phytium_msi_pmu_get_now_status(misc_pmu); | ||
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| if (!is_interrupt_state(now_state)) | ||
| return IRQ_NONE; | ||
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| if (!event_added) { | ||
| phytium_msi_pmu_clear_counters(misc_pmu, MISC_MSI_MON_OPT_MASK); | ||
| return IRQ_HANDLED; | ||
| } | ||
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| stop_state = phytium_msi_pmu_get_stop_status(misc_pmu); | ||
| if (stop_state & MISC_MSI_MON_COUNT_FULL_MASK) { | ||
| for_each_set_bit(idx, used_mask, PHYTIUM_MISC_MAX_COUNTERS) { | ||
| event = misc_pmu->pmu_events.hw_events[idx]; | ||
| if (!event) | ||
| continue; | ||
| event_type = phytium_msi_pmu_get_event_type(event); | ||
| dev_stop_mask = pcie_dev_msi_mon_stop_mask[event_type]; | ||
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| if (stop_state & dev_stop_mask & MISC_MSI_MON_COUNT_FULL_MASK) { | ||
| phytium_msi_pmu_event_update(event); | ||
| opt_val |= pcie_dev_msi_mon_opt_bits[event_type]; | ||
| set_bit(event_type, &dev_mask); | ||
| } |
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| reg: | ||
| maxItems: 2 | ||
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| reg-names: | ||
| items: | ||
| - const: reg | ||
| - const: mem | ||
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| required: | ||
| - compatible | ||
| - reg | ||
| - reg-names | ||
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| examples: | ||
| - | | ||
| ep0: ep@0x31000000 { | ||
| compatible = "phytium,pe2201-pcie-ep"; | ||
| interrupts = <0x00000000 0x0000000a 0x00000004 0x00000000 0x0000000b 0x00000004>; | ||
| reg = <0x00000000 0x31000000 0x00000000 0x00010000 0x00000011 0x00000000 0x00000001 0x00000000 0x00000000 0x31100000 0x00000000 0x00001000>; | ||
| reg-names = "reg", "mem", "hpb"; | ||
| max-outbound-regions = <0x00000003>; | ||
| max-functions = [02]; |
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| /* Rebind parent-to-child dispatch chain and enable parent IRQ lines. */ | ||
| static void phytium_set_irq_chained_handler(struct phytium_gpio *gpio) | ||
| { | ||
| struct gpio_irq_chip *girq = &gpio->gc.irq; | ||
| int i; |
Add device IDs for the next generation of switchtec products. No changes to the driver were required with the new version of the hardware. [logang: rewrote commit message] Signed-off-by: Ben Reed <Ben.Reed@microchip.com> Signed-off-by: Logan Gunthorpe <logang@deltatee.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Link: https://patch.msgid.link/20260505161633.67454-1-logang@deltatee.com Link: https://git.kernel.org/pub/scm/linux/kernel/git/pci/pci.git/commit/?h=next&id=5e6c21c56998e1e58d2f314e70779989ea0fee5d Signed-off-by: WangYuli <wangyl5933@chinaunicom.cn>
Fix module (=m) case where GPIO interrupts stop after S4 resume because the parent IRQ loses the chained handler setting up at probe. So rebind the handler for each parent in resume() to restore parent-to-child dispatch. While builtin (=y) builds unaffected. Mainline: Open-Source Signed-off-by: zhuling <zhuling2709@phytium.com.cn> Signed-off-by: Wang Yinfeng <wangyinfeng@phytium.com.cn> Signed-off-by: Xia Qian <xiaqian1486@phytium.com.cn>
Linux PM framework automatically calls suspend_device_irqs() during suspend to disable IRQs, and resume_device_irqs() during resume to re-enable them. The current GPIO driver redundantly calls enable_irq() in its resume flow, which will create an unbalanced IRQ enable since the kernel has already restored the IRQ state through resume_device_irqs(). Mainline: Open-Source Signed-off-by: Zhu Ling <zhuling2709@phytium.com.cn> Signed-off-by: Wang Yinfeng <wangyinfeng@phytium.com.cn> Signed-off-by: Xia Qian <xiaqian1486@phytium.com.cn>
Ensure the Phytium GPIO PCI driver is only selectable for its intended environment. This driver depends on both the Phytium platform and a working PCI subsystem. Mainline: Open-Source Signed-off-by: Zhu Ling <zhuling2709@phytium.com.cn> Signed-off-by: Wang Yinfeng <wangyinfeng@phytium.com.cn> Signed-off-by: Xia Qian <xiaqian1486@phytium.com.cn>
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This patches updates the support for phytium gpio controller driver.