Designed & Simulated in FOSSEE eSim (KiCad-based workflow)
🧊 3D render of the routed 4-layer board — ESP32-C3-WROOM-02, USB-C, DC barrel jack, and dual GPIO headers.
Power In (7–24V) → Protection → 5V Buck → 3.3V LDO → ESP32-C3 ⚡
git clone https://github.com/devakumar18dk-spec/eSim_PCB_Design_Project_Files.git- Overview
- Highlights & Features
- System Architecture
- Power Architecture
- USB-C Interface
- Boot & Reset Control
- RTC Timing
- GPIO Expansion
- PCB Design (4-Layer)
- 📐 Schematic
- 🖼 PCB Layout
- Technical Specifications
- Design Verification Checklist
- Hardware Bring-Up Sequence
- Design Workflow
- Repository Structure
- Getting Started
- Contributing
- License
- Acknowledgements
This project presents the design and PCB implementation of a custom ESP32-C3-based development board, engineered end-to-end using the FOSSEE eSim electronics design environment. Rather than functioning as a simple ESP32 breakout, this board is architected as a complete embedded hardware platform — integrating wide-range DC power input, robust input protection, two-stage voltage regulation, USB-C connectivity with ESD protection, hardware boot/reset control, RTC timing, and expandable GPIO — all realized on a four-layer PCB.
Design philosophy: protect first, convert efficiently, regulate cleanly, then compute. Every subsystem exists to deliver a stable, low-noise supply and a reliable interface to the ESP32-C3.
7–24 V DC → Protection → 5 V Buck → 3.3 V LDO → ESP32-C3
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The board is organized into five functional sections: Power, USB-C, Main Controller, Boot/Reset, and GPIO/Expansion.
ESP32-C3 DEVELOPMENT BOARD
│
┌───────────────────┼───────────────────┐
│ │ │
▼ ▼ ▼
POWER SYSTEM USB-C SYSTEM CONTROL / I/O
│ │ │
7–24 V DC USB Type-C Boot Button
│ │ Reset Button
▼ │ │
Input Protection │ │
│ │ │
▼ ▼ ▼
5 V Buck ESD Protection ESP32-C3
│ │ │
▼ ▼ GPIO Headers
5 V Rail USB D+/D−
│
▼
3.3 V LDO
│
▼
+3.3 V Rail
│
▼
ESP32-C3 WROOM-02
│
└── 32.768 kHz RTC Crystal
Every subsystem on this board depends on a stable, protected supply — so power is treated as the primary design driver, not an afterthought.
DC Input → Protection → Buck Converter (5 V) → LDO (3.3 V) → ESP32-C3
The board deliberately avoids converting the full 7–24 V range directly to 3.3 V with a linear regulator. Instead, a switching regulator absorbs the large voltage difference efficiently, while an LDO performs final, low-noise regulation — the right tool for each job.
🛡️ Input Protection — click to expand
| Function | Component | Behavior |
|---|---|---|
| Transient protection | TVS / Zener network | Inactive under normal operation; clamps excess voltage during spikes |
| Reverse-polarity protection | P-channel MOSFET (STN3P6F6) | Low-resistance conduction on correct polarity; blocks reverse voltage |
Correct polarity Incorrect polarity
│ │
▼ ▼
P-MOSFET conducts MOSFET blocks
│ │
▼ ▼
Power reaches regulator Downstream circuitry protected
A P-MOSFET is used instead of a conventional diode because it offers much lower conduction loss.
⚙️ 5 V Buck Conversion — click to expand
The protected input feeds the LMR50410-Q1 switching regulator, which converts 7–24 V → 5 V by transferring energy through controlled switching rather than dissipating the difference as heat.
Supporting components: 4.7 µH inductor · bootstrap capacitor · input/output capacitors · feedback resistor network · 10 µF local input capacitor (placed close to the regulator to keep the high-frequency current loop compact).
7–24 V ─► Switching Node ─► 4.7 µH Inductor ─► Output Filter ─► 5 V
🎯 3.3 V LDO Post-Regulation — click to expand
The 5 V rail feeds an LM1117-3.3 LDO, which handles only the small 5 V → 3.3 V step. This division of labor means:
| Stage | Responsibility |
|---|---|
| Buck | Efficient large voltage conversion (7–24 V → 5 V) |
| LDO | Final clean regulation, ripple attenuation, low-impedance supply |
The LDO also provides power-supply rejection within its effective PSRR band, attenuating residual switching ripple before it reaches the ESP32-C3.
📎 MCU Decoupling — click to expand
Local 4.7 µF (bulk) and 100 nF (high-frequency) capacitors sit right at the ESP32-C3 supply pins, supplying transient current locally instead of forcing it through long PCB traces from the regulator — reducing supply impedance seen by the controller.
The USB-C section is an independent communication interface, cleanly separated from the main power path.
| Element | Detail |
|---|---|
| Connector | USB Type-C, 16-pin |
| CC configuration | 2 × 5.1 kΩ on CC1/CC2 → configures board as USB-C sink/device |
| ESD protection | USBLC6-2SC6, placed near the connector |
| Role | Data / programming only — not the primary power source |
External USB Connector → ESD Protection → ESP32-C3
Keeping USB power and main DC power separate lets the board run continuously from the 7–24 V input while still using USB freely for programming and debugging.
| Button | Signal | Function |
|---|---|---|
| Reset | EN | 10 kΩ pull-up; pressing forces EN low and resets the MCU |
| Boot | IO9 | 10 kΩ pull-up; pressing changes boot-strap state to enter programming mode |
USB connected → Hold BOOT → Reset ESP32-C3 → Enters programming mode
A 32.768 kHz crystal provides an external low-frequency timing reference for the ESP32-C3 RTC. It's placed close to the module to minimize parasitics and kept away from the buck converter's switching node to avoid noise coupling.
Two 8-pin, 2.54 mm pitch headers expose selected ESP32-C3 GPIOs, turning the board into a reusable development platform for sensors, LEDs, displays, communication modules, and breadboard prototyping.
| Layer | Purpose |
|---|---|
| F.Cu (Top) | Power distribution & primary component routing |
| In1.Cu | Signal routing (GPIO fan-out from the ESP32-C3) |
| In2.Cu | Mixed-purpose routing / secondary distribution |
| B.Cu (Bottom) | Continuous ground plane |
📍 Component Placement Strategy
| Region | Contents | Rationale |
|---|---|---|
| Upper | ESP32-C3 module, antenna toward board edge | Unobstructed RF environment |
| Central | Buck converter, LDO, protection circuitry, USB-C | Short, low-impedance power connections |
| Lower | Boot/Reset buttons | User accessibility |
| Sides | GPIO headers (left & right) | Convenient external interfacing |
📡 Antenna Keep-Out
A clearly defined keep-out zone sits above the ESP32-C3 module — no copper, tracks, or vias are routed through this area, per module manufacturer guidance, to prevent detuning or shielding the integrated antenna.
🧵 Routing & Grounding Philosophy
- High-current power paths — short and comparatively wide (DC input, MOSFET, buck, inductor, 5 V rail, LDO)
- Switching node — kept as small as practical to limit EMI coupling
- USB D+/D− — routed as a matched differential pair, ESD device close to the connector
- RTC crystal traces — short, isolated from switching noise
- Ground plane (B.Cu) — continuous reference plane minimizing loop area, EMI, and supply noise — especially important given the ESP32-C3's onboard radio
🌡️ Thermal Considerations
Primary heat sources are the buck converter, LDO, and protection MOSFET. The LDO has the most predictable thermal profile since it dissipates the 5 V→3.3 V difference directly — adequate copper area is provided around its thermal pads per datasheet recommendations.
| 🔋 Input → 5V → 3.3V | 🔌 USB-C & ESD | 🛠 Boot & Reset | 🧠 Main Controller | 🧩 GPIOs |
|---|---|---|---|---|
| ST6P3F6, LMR50410-Q1, LM1117-3.3 | USB-C receptacle, USBLC6-2SC6 | EN & IO9 push buttons | ESP32-C3-WROOM-02 | 2 × 8-pin headers |
📄 Captured entirely in FOSSEE eSim — five functional blocks laid out for clarity: power regulation (top), USB-C/protection, boot/reset, and GPIO breakout (bottom row), with the main ESP32-C3 controller on the right.
The board is routed across four copper layers, each with a distinct role. Toggle through the stack below — every view shares the same silhouette so you can trace a single net (e.g. GND) from top to bottom.
| 🟥 F.Cu — Power / Top Layer | 🟩 In1.Cu — Signal Layer |
|---|---|
 |
 |
| Primary power distribution & component-side routing | ESP32-C3 GPIO fan-out toward J3 / J4 headers |
| 🟧 In2.Cu — Mixed Routing Layer | 🟦 B.Cu — Ground Plane |
 |
 |
| Secondary power/signal distribution channel | Continuous ground reference plane |
🛰️ Antenna Keep-Out Zone — visible as the hatched
KEEP-OUT ZONE / Antennaregion above the ESP32-C3 module on every layer. No copper, tracks, or vias are routed through this area to protect RF performance.
📊 Routing Stats (from PCB editor)
| Metric | Count |
|---|---|
| Pads | 151 |
| Vias | 102 |
| Nets | 586 |
| Unrouted | 0 ✅ |
| Specification | Design |
|---|---|
| MCU | ESP32-C3-WROOM-02 |
| Main DC input | 7–24 V |
| Primary power connector | DC input connector |
| Input protection | TVS/Zener + P-channel MOSFET |
| Reverse polarity protection | STN3P6F6 P-MOSFET |
| Buck regulator | LMR50410-Q1 |
| Buck output | 5 V |
| Buck inductor | 4.7 µH |
| Post-regulator | LM1117-3.3 |
| Final logic rail | 3.3 V |
| RTC reference | 32.768 kHz crystal |
| USB connector | USB Type-C, 16-pin |
| USB CC resistors | 5.1 kΩ × 2 |
| USB ESD protection | USBLC6-2SC6 |
| Reset control | EN push button |
| Boot control | IO9 push button |
| Button pull-ups | 10 kΩ |
| GPIO expansion | 2 × 8-pin headers |
| GPIO header pitch | 2.54 mm |
| PCB structure | 4-layer |
| F.Cu | Primary power / component routing |
| In1.Cu | Signal routing |
| In2.Cu | Mixed routing / distribution |
| B.Cu | Ground plane |
| RF provision | ESP32 antenna keep-out |
| Design environment | FOSSEE eSim / KiCad-based workflow |
|
Schematic Checks
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PCB Checks
|
Do not connect the ESP32 module immediately after fabrication — follow a controlled sequence.
| Step | Test | Expected Result |
|---|---|---|
| 1 | Input protection | Protected input rail stable across 7–24 V |
| 2 | Buck converter | ~+5 V at buck output (before connecting downstream circuitry) |
| 3 | LDO | ~+3.3 V at LDO output |
| 4 | MCU power | ESP32-C3 receives correct 3.3 V supply |
| 5 | Reset | Pressing EN resets the MCU |
| 6 | Boot | IO9 + reset sequencing enters programming mode |
| 7 | USB | USB enumeration / programming succeeds |
| 8 | GPIO | Expansion headers verified with simple GPIO firmware |
| 9 | RTC | 32.768 kHz RTC functionality confirmed |
System Requirements → Circuit Architecture → Component Selection
→ Schematic Capture (eSim) → Electrical Connectivity Verification
→ Footprint Assignment → PCB Layout → 4-Layer Stack-up
→ Component Placement → Power Routing → Signal Routing
→ Ground Plane → Antenna Keep-Out → Design Rule Check
→ Gerber / Manufacturing Files → PCB Fabrication → Hardware Testing
eSim_PCB_Design_Project_Files/
├── assets/
│ └── images/
│ ├── board-render.png # 3D render
│ ├── schematic.png # Full eSim schematic
│ ├── pcb-layout-top.png # F.Cu — power layer
│ ├── pcb-layout-in1.png # In1.Cu — signal layer
│ ├── pcb-layout-in2.png # In2.Cu — mixed layer
│ └── pcb-layout-bottom.png # B.Cu — ground plane
├── hardware/
│ ├── schematic/ # eSim / KiCad schematic project files
│ ├── pcb/ # PCB layout project files
│ └── gerbers/ # Manufacturing output (Gerbers, drill files, BOM)
├── docs/
│ └── technical-report.md # Full design & verification report
├── firmware/ # (optional) example/bring-up firmware
├── LICENSE
└── README.md
- Clone the repository
git clone https://github.com/devakumar18dk-spec/eSim_PCB_Design_Project_Files.git cd eSim_PCB_Design_Project_Files - Open the schematic/PCB in FOSSEE eSim or KiCad from the
hardware/directory. - Review the Gerbers in
hardware/gerbers/before sending to fabrication. - Follow the Hardware Bring-Up Sequence after assembly.
- Flash firmware over USB-C once power rails are verified.
Contributions, issues, and design suggestions are welcome! Feel free to open a pull request or start a discussion if you'd like to improve the power architecture, layout, or documentation.
This project is released under the MIT License — see LICENSE for details. (Update if a different license applies.)
- FOSSEE eSim — schematic capture and simulation environment
- KiCad — PCB layout workflow
- Espressif Systems — ESP32-C3-WROOM-02 module
Wide-range power management · Protection · Wireless processing · USB-C · Hardware boot control · RTC · Expandable I/O — all in a single four-layer PCB.
⭐ If this project helped you, consider starring the repository!