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fix: UART parity mapping and digital-in reset before logic capture - #5
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The UART, SPI and CAN protocol functions run on the device's digital-in resource and leave it configured for themselves. arm() only sets part of the digital-in state, so a capture taken after a protocol was used inherited the rest (sample mode, input order, trigger details) and decoded wrongly. Digilent's SDK reference calls for FDwfDigitalInReset before reusing digital-in after a protocol; arm() now does that first. Co-Authored-By: Claude Opus 5.5 <noreply@anthropic.com> Claude-Session: https://claude.ai/code/session_01LKNpyfqJJLHgVZSg2kAePR
FDwfDigitalUartParitySet takes 1 for even and 2 for odd. The older SDK manual (and pydwf, which copies it) lists them the other way round; Digilent has confirmed that as a documentation error. The bench sent 2 for "even" and 1 for "odd", so the AD3 transmitted and checked the opposite parity to the one requested. Co-Authored-By: Claude Opus 5.5 <noreply@anthropic.com> Claude-Session: https://claude.ai/code/session_01LKNpyfqJJLHgVZSg2kAePR
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Fixes two tickets, with one commit for each. They can be reviewed commit by commit.
1.
LogicAnalyzer.arm()doesn't reset digital-in after the protocol decoders used it (f8cc4ae)The UART, SPI and CAN protocol functions run on the device's digital-in resource and leave it configured for their own use.
arm()sets only part of the digital-in state: acquisition mode, divider, sample format, buffer size and trigger. Everything else (sample mode, input order, other trigger details) was inherited from the protocol, so captures taken after a protocol had been used decoded wrongly.Digilent's SDK reference says to call
FDwfDigitalInResetbefore reusing digital-in after a protocol.arm()now makes that call first.Test:
test_logic_arm_resets_digital_in_left_configured_by_a_protocolconfigures and reads the UART, arms the logic analyzer, and asserts thatFDwfDigitalInResetis the first digital-in call. It failed before the fix and passes after it.2. UART parity mapping is swapped (
0e2f644)ProtocolUart.PARITYwas{"none": 0, "odd": 1, "even": 2}. It is now{"none": 0, "even": 1, "odd": 2}.The sources disagree on this, so it needs a careful review:
uart.pyall use it. The bench's mapping came from there.I added a one-line comment on
PARITYso the next reader doesn't "fix" it back from the manual.Tests:
test_uart_roundtripnow expects1for even. The new parametrized testtest_uart_parity_uses_the_runtime_encodingcovers none, even and odd.Verification
pytest: 127 passed, 1 skipped (the GUI test, because PySide6 isn't installed).ruff checkandruff format --checkare clean.mypyreports 11 errors, all ingui/because PySide6 isn't installed.mainhas the same errors.🤖 Generated with Claude Code
https://claude.ai/code/session_01LKNpyfqJJLHgVZSg2kAePR
Generated by Claude Code