Fragment asm: initial support of PSEQ fetch instruction and couple of minor changes - #63
Fragment asm: initial support of PSEQ fetch instruction and couple of minor changes#63digetx wants to merge 3 commits into
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It is easy to override ALU by accident, let's avoid that. Something like this isn't allowed to have in the code now: ALU: ALU0: NOP ALU0: NOP
Now ASM's error message gives correct line number if code contains multi-line comments.
PSEQ 'fetch' instruction reads data from given render target and loads it to destination registers. Add initial support of that instruction. Example: PSEQ: fetch r0, r1, rt15
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For the record: I've found that PSEQ doesn't work exactly as I supposed with different RT formats and we'll probably need some more GLES tests for experimenting with PSEQ. I should get back to this sometime soon. |
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I think this is more or less correct? But I think there'd be some conflicts by now, because the disassembler now prints some PSEQ bits. The big mystery is the difference between the two enable bits, but I think |
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Partially correct. Don't remember the enable bits details |
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My current suspicion is that bit 3 is the enable bit, and bit 23 is an fx10 bit. Similarly, I think DW has a fx10 bit in bit 17, and bit 0..1 is a 2-bit opcode, with 0=nop, 1=write and 2=spill. Non-fx10 (e.g fp20) seems to only practically happen with spilling (with RT=4 being a special-purpose spilling buffer). This hypothesis is based on analyzing |
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Add PSEQ fetch instruction to grate's asm and make couple corrections to the asm that bugged me a bit for quite some time.