Skip to content

fix avx10 detection under Intel SDE #9135

New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

Sign up for GitHub

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Merged
alexreinking merged 3 commits into from
May 14, 2026
+5 −3
Merged

fix avx10 detection under Intel SDE #9135

Show file tree
Hide file tree
Changes from all commits
Commits
Show all changes
3 commits
Select commit Hold shift + click to select a range
0f5dab1
x86: use generic x86-64-v{N} mcpu and explicit mattrs
abadams May 12, 2026
a88f977
x86: read CPUID.7.1.EDX, not CPUID.7.0.EDX, when probing for AVX10
abadams May 12, 2026
675674c
Merge branch 'main' into abadams/fix_avx10_detection
alexreinking May 14, 2026
File filter

Filter by extension

Filter by extension
Conversations
Failed to load comments.
Loading
Jump to
Jump to file
Failed to load files.
Loading
Diff view
Diff view
5 changes: 3 additions & 2 deletions src/Target.cpp
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -502,9 +502,10 @@ Target calculate_host_target() {
}
}

// AVX10 converged vector instructions.
// AVX10 converged vector instructions. The enumeration bit is
// CPUID.(EAX=7,ECX=1).EDX[19].
const uint32_t avx10 = 1U << 19;
if (os_avx512 && (info2.edx & avx10)) {
if (os_avx512 && (info3.edx & avx10)) {
const auto info_avx10 = cpuid(0x24, 0x0);

// This checks that the AVX10 version is greater than zero.
Expand Down
3 changes: 2 additions & 1 deletion src/runtime/x86_cpu_features.cpp
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -197,8 +197,9 @@ extern "C" WEAK int halide_get_cpu_features(CpuFeatures *features) {
// AVX10 converged vector instructions.
// AVX10 uses EVEX encoding with opmask registers at all vector widths,
// so it requires the same OS XSAVE support as AVX-512.
// The enumeration bit is CPUID.(EAX=7,ECX=1).EDX[19].
constexpr uint32_t avx10 = 1U << 19;
if (os_avx512 && (info2.edx & avx10)) {
if (os_avx512 && (info3.edx & avx10)) {
const auto info_avx10 = cpuid(0x24, 0x0);
if ((info_avx10.ebx & 0xff) >= 1) {
halide_set_available_cpu_feature(features, halide_target_feature_avx10_1);
Expand Down
Loading