Return the original signal when replicating by 1 - #689
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Thank you for your contribution! A couple notes/questions
`Logic.replicate(1)` built a `ReplicationOp`, which emits a redundant
`{1{...}}` in the generated SystemVerilog:
assign rep1 = {1{a}};
Replicating once is a no-op, so return the signal directly instead. The
generated output becomes:
assign rep1 = a;
`signExtend` already routes through `replicate`, so it inherits the same
benefit: sign-extending a 1-bit signal to width 1, or any signal to its
existing width, no longer emits a replication.
Validation of non-positive multipliers is unaffected; those still reach
`ReplicationOp` and throw `InvalidMultiplierException`.
Adds tests for the returned signal identity and for the absence of `{1{`
in generated SystemVerilog. The existing "multiply by 1" test only
checked simulated values, which pass either way.
Fixes intel#522
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Looks great! Thank you for the contribution!
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Logic.replicate(1)built aReplicationOp, which emits a redundant{1{...}}in the generated SystemVerilog:Replicating once is a no-op, so return the signal directly instead. The generated output becomes:
signExtendalready routes throughreplicate, so it inherits the same benefit: sign-extending a 1-bit signal to width 1, or any signal to its existing width, no longer emits a replication.Validation of non-positive multipliers is unaffected; those still reach
ReplicationOpand throwInvalidMultiplierException.Adds tests for the returned signal identity and for the absence of
{1{in generated SystemVerilog. The existing "multiply by 1" test only checked simulated values, which pass either way.Fixes #522
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