Compilation of J1B with Verilator does not work in Linux/Debian. Small modification of j1b.v needed.

[wzab]

When I try to run the j1b emulated with Verilator in the j1b/verilator directory, I get the following error:

verilator --l2-name v -Wall -I../verilog/ --cc j1b.v ../verilog/j1.v ../verilog/stack.v --top-module j1b --exe sim_main.cpp
%Error-PROCASSWIRE: j1b.v:28: Procedural assignment to wire, perhaps intended var (IEEE 2017 6.5): insn
%Error: Exiting due to 1 error(s)
%Error: See the manual and http://www.veripool.org/verilator for more assistance.
%Error: Command Failed /usr/bin/verilator_bin --l2-name v -Wall -I../verilog/ --cc j1b.v  ../verilog/j1.v ../verilog/stack.v --top-module j1b --exe sim_main.cpp
make: *** [Makefile:8: obj_dir/Vj1b] Error 10

To cure it, I have to change the 21st line in j1b from:

  wire [15:0] insn;

to

  reg [15:0] insn;

After that change the simulation and compilation goes fine.