Completed port to TinyFPGA-BX board complete with soft USB port.

[bmentink]

Hi David ...... if you are listening these days ... :)

I have completed the above port which includes a USB UART implemented in verilog. Works very well as a replacement for a hardware UART .. super fast, interpretation of swapforth.fs takes .2 seconds ...

The only issue I have is: In a standard UART when you hit the Enter key on the terminal, you get both Return(13) and Line Feed(10) sent ... with USB, you only get a Return(13). My question is: Is there any place in the code, or in the shell.py script that I can fix this issue?

Or, should I fix that in the UART emulation wrapper .... i.e. verilog layer ..

[Mecrisp]

@bmentink

That's exactly what I was looking for ! Where can I find your code, how did you solve the "overrun" problem of the USB logic ?

I maintain a descendant of Swapforth, "Mecrisp-Ice", and I wished to add a USB soft terminal when I ran into this issue:

davidthings/tinyfpga_bx_usbserial#12

Regarding your issue: CR/LF/CRLF can be easily fixed in Forth, don't mess with the character stream in Verilog, as the same interface may carry raw data.

Matthias