[SPIR-V] Reject OpSelect with scalar result and vector condition

[aobolensk]

Per SPIR-V spec, scalar Result Type requires a scalar bool condition. So, vector cond branches under a scalar result are unreachable

[llvmbot]

@llvm/pr-subscribers-backend-spir-v

Author: Arseniy Obolenskiy (aobolensk)

Changes

Per SPIR-V spec, scalar Result Type requires a scalar bool condition. So, vector cond branches under a scalar result are unreachable

---

Full diff: https://github.com/llvm/llvm-project/pull/193745.diff

3 Files Affected:

• (modified) llvm/lib/Target/SPIRV/SPIRVInstructionSelector.cpp (+6-3)
• (added) llvm/test/CodeGen/SPIRV/select-invalid-vector-cond.ll (+16)
• (added) llvm/test/CodeGen/SPIRV/select.ll (+77)

diff --git a/llvm/lib/Target/SPIRV/SPIRVInstructionSelector.cpp b/llvm/lib/Target/SPIRV/SPIRVInstructionSelector.cpp
index 8e3040c2667f6..c0925cfbba9d3 100644
--- a/llvm/lib/Target/SPIRV/SPIRVInstructionSelector.cpp
+++ b/llvm/lib/Target/SPIRV/SPIRVInstructionSelector.cpp
@@ -4007,12 +4007,15 @@ bool SPIRVInstructionSelector::selectSelect(Register ResVReg,
       Opcode = IsScalarBool ? SPIRV::OpSelectVISCond : SPIRV::OpSelectVIVCond;
     }
   } else {
+    if (!IsScalarBool)
+      report_fatal_error("OpSelect with a scalar result requires a scalar "
+                         "boolean condition");
     if (IsFloatTy) {
-      Opcode = IsScalarBool ? SPIRV::OpSelectSFSCond : SPIRV::OpSelectVFVCond;
+      Opcode = SPIRV::OpSelectSFSCond;
     } else if (IsPtrTy) {
-      Opcode = IsScalarBool ? SPIRV::OpSelectSPSCond : SPIRV::OpSelectVPVCond;
+      Opcode = SPIRV::OpSelectSPSCond;
     } else {
-      Opcode = IsScalarBool ? SPIRV::OpSelectSISCond : SPIRV::OpSelectVIVCond;
+      Opcode = SPIRV::OpSelectSISCond;
     }
   }
   BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(Opcode))
diff --git a/llvm/test/CodeGen/SPIRV/select-invalid-vector-cond.ll b/llvm/test/CodeGen/SPIRV/select-invalid-vector-cond.ll
new file mode 100644
index 0000000000000..a92d25f43ea94
--- /dev/null
+++ b/llvm/test/CodeGen/SPIRV/select-invalid-vector-cond.ll
@@ -0,0 +1,16 @@
+; RUN: not --crash llc -O0 -mtriple=spirv32-unknown-unknown %s -o /dev/null 2>&1 | FileCheck %s
+; RUN: not --crash llc -O0 -mtriple=spirv64-unknown-unknown %s -o /dev/null 2>&1 | FileCheck %s
+
+; __spirv_Select can pair a vector boolean condition with scalar operands,
+; which is malformed for OpSelect and must be diagnosed.
+
+; CHECK: LLVM ERROR: OpSelect with a scalar result requires a scalar boolean condition
+
+define spir_kernel void @bad_select(i32 %a, i32 %b, ptr addrspace(1) %out, <4 x i1> %cond) {
+entry:
+  %call = call spir_func i32 @_Z14__spirv_SelectDv4_bii(<4 x i1> %cond, i32 %a, i32 %b)
+  store i32 %call, ptr addrspace(1) %out
+  ret void
+}
+
+declare spir_func i32 @_Z14__spirv_SelectDv4_bii(<4 x i1>, i32, i32)
diff --git a/llvm/test/CodeGen/SPIRV/select.ll b/llvm/test/CodeGen/SPIRV/select.ll
new file mode 100644
index 0000000000000..019f713f739d4
--- /dev/null
+++ b/llvm/test/CodeGen/SPIRV/select.ll
@@ -0,0 +1,77 @@
+; RUN: llc -O0 -verify-machineinstrs -mtriple=spirv64-unknown-unknown %s -o - | FileCheck %s
+; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv64-unknown-unknown %s -o - -filetype=obj | spirv-val %}
+
+; OpSelect: condition and object component counts must match.
+
+; CHECK-DAG: %[[#Bool:]]    = OpTypeBool
+; CHECK-DAG: %[[#I32:]]     = OpTypeInt 32 0
+; CHECK-DAG: %[[#F32:]]     = OpTypeFloat 32
+; CHECK-DAG: %[[#I8:]]      = OpTypeInt 8 0
+; CHECK-DAG: %[[#PtrI8:]]   = OpTypePointer Function %[[#I8]]
+; CHECK-DAG: %[[#V4I32:]]   = OpTypeVector %[[#I32]] 4
+; CHECK-DAG: %[[#V4F32:]]   = OpTypeVector %[[#F32]] 4
+; CHECK-DAG: %[[#V4Bool:]]  = OpTypeVector %[[#Bool]] 4
+
+; Scalar result, scalar cond.
+; CHECK: OpFunction
+; CHECK: %[[#SC:]] = OpFunctionParameter %[[#Bool]]
+; CHECK: %[[#SA:]] = OpFunctionParameter %[[#I32]]
+; CHECK: %[[#SB:]] = OpFunctionParameter %[[#I32]]
+; CHECK: %{{[0-9]+}} = OpSelect %[[#I32]] %[[#SC]] %[[#SA]] %[[#SB]]
+define i32 @sel_i32_scond(i1 %c, i32 %a, i32 %b) {
+  %r = select i1 %c, i32 %a, i32 %b
+  ret i32 %r
+}
+
+; CHECK: OpFunction
+; CHECK: %[[#FC:]] = OpFunctionParameter %[[#Bool]]
+; CHECK: %[[#FA:]] = OpFunctionParameter %[[#F32]]
+; CHECK: %[[#FB:]] = OpFunctionParameter %[[#F32]]
+; CHECK: %{{[0-9]+}} = OpSelect %[[#F32]] %[[#FC]] %[[#FA]] %[[#FB]]
+define float @sel_f32_scond(i1 %c, float %a, float %b) {
+  %r = select i1 %c, float %a, float %b
+  ret float %r
+}
+
+; CHECK: OpFunction
+; CHECK: %[[#PC:]] = OpFunctionParameter %[[#Bool]]
+; CHECK: %[[#PA:]] = OpFunctionParameter %[[#PtrI8]]
+; CHECK: %[[#PB:]] = OpFunctionParameter %[[#PtrI8]]
+; CHECK: %{{[0-9]+}} = OpSelect %[[#PtrI8]] %[[#PC]] %[[#PA]] %[[#PB]]
+define ptr @sel_ptr_scond(i1 %c, ptr %a, ptr %b) {
+  %r = select i1 %c, ptr %a, ptr %b
+  ret ptr %r
+}
+
+; Vector result, scalar (broadcast) cond.
+; CHECK: OpFunction
+; CHECK: %[[#VSC:]] = OpFunctionParameter %[[#Bool]]
+; CHECK: %[[#VSA:]] = OpFunctionParameter %[[#V4I32]]
+; CHECK: %[[#VSB:]] = OpFunctionParameter %[[#V4I32]]
+; CHECK: %{{[0-9]+}} = OpSelect %[[#V4I32]] %[[#VSC]] %[[#VSA]] %[[#VSB]]
+define <4 x i32> @sel_v4i32_scond(i1 %c, <4 x i32> %a, <4 x i32> %b) {
+  %r = select i1 %c, <4 x i32> %a, <4 x i32> %b
+  ret <4 x i32> %r
+}
+
+; Vector result, vector cond.
+; CHECK: OpFunction
+; CHECK: %[[#VVIC:]] = OpFunctionParameter %[[#V4Bool]]
+; CHECK: %[[#VVIA:]] = OpFunctionParameter %[[#V4I32]]
+; CHECK: %[[#VVIB:]] = OpFunctionParameter %[[#V4I32]]
+; CHECK: %{{[0-9]+}} = OpSelect %[[#V4I32]] %[[#VVIC]] %[[#VVIA]] %[[#VVIB]]
+define <4 x i32> @sel_v4i32_vcond(<4 x i1> %c, <4 x i32> %a, <4 x i32> %b) {
+  %r = select <4 x i1> %c, <4 x i32> %a, <4 x i32> %b
+  ret <4 x i32> %r
+}
+
+; CHECK: OpFunction
+; CHECK: %[[#VVFC:]] = OpFunctionParameter %[[#V4Bool]]
+; CHECK: %[[#VVFA:]] = OpFunctionParameter %[[#V4F32]]
+; CHECK: %[[#VVFB:]] = OpFunctionParameter %[[#V4F32]]
+; CHECK: %{{[0-9]+}} = OpSelect %[[#V4F32]] %[[#VVFC]] %[[#VVFA]] %[[#VVFB]]
+define <4 x float> @sel_v4f32_vcond(<4 x i1> %c, <4 x float> %a, <4 x float> %b) {
+  %r = select <4 x i1> %c, <4 x float> %a, <4 x float> %b
+  ret <4 x float> %r
+}
+

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